/* * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "dra72x.dtsi" #include #include / { model = "TI DRA722"; compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; memory { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; aliases { display0 = &hdmi0; sound0 = &sound0; sound1 = &hdmi; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; ipu2_cma_pool: ipu2_cma@95800000 { compatible = "shared-dma-pool"; reg = <0x0 0x95800000 0x0 0x3800000>; reusable; status = "okay"; }; dsp1_cma_pool: dsp1_cma@99000000 { compatible = "shared-dma-pool"; reg = <0x0 0x99000000 0x0 0x4000000>; reusable; status = "okay"; }; ipu1_cma_pool: ipu1_cma@9d000000 { compatible = "shared-dma-pool"; reg = <0x0 0x9d000000 0x0 0x2000000>; reusable; status = "okay"; }; }; evm_3v3: fixedregulator-evm_3v3 { compatible = "regulator-fixed"; regulator-name = "evm_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; aic_dvdd: fixedregulator-aic_dvdd { /* TPS77018DBVT */ compatible = "regulator-fixed"; regulator-name = "aic_dvdd"; vin-supply = <&evm_3v3>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; evm_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; }; extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; }; extcon_usb2: extcon_usb2 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; }; hdmi0: connector { compatible = "hdmi-connector"; label = "hdmi"; type = "a"; port { hdmi_connector_in: endpoint { remote-endpoint = <&tpd12s015_out>; }; }; }; tpd12s015: encoder { compatible = "ti,tpd12s015"; gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; tpd12s015_in: endpoint { remote-endpoint = <&hdmi_out>; }; }; port@1 { reg = <1>; tpd12s015_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; }; sound0: sound@0 { compatible = "simple-audio-card"; simple-audio-card,name = "DRA7xx-EVM"; simple-audio-card,widgets = "Headphone", "Headphone Jack", "Line", "Line Out", "Microphone", "Mic Jack", "Line", "Line In"; simple-audio-card,routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC3L", "Mic Jack", "MIC3R", "Mic Jack", "Mic Jack", "Mic Bias", "LINE1L", "Line In", "LINE1R", "Line In"; simple-audio-card,format = "dsp_b"; simple-audio-card,bitclock-master = <&sound0_master>; simple-audio-card,frame-master = <&sound0_master>; simple-audio-card,bitclock-inversion; sound0_master: simple-audio-card,cpu { sound-dai = <&mcasp3>; system-clock-frequency = <5644800>; }; simple-audio-card,codec { sound-dai = <&tlv320aic3106>; clocks = <&atl_clkin2_ck>; }; }; vmmcwl_fixed: fixedregulator-mmcwl { compatible = "regulator-fixed"; regulator-name = "vmmcwl_fixed"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* gpio5_8 */ enable-active-high; }; kim { compatible = "kim"; nshutdown_gpio = <132>; dev_name = "/dev/ttyS2"; flow_cntrl = <1>; baud_rate = <3686400>; }; btwilink { compatible = "btwilink"; }; }; &dpll_dsp_ck { assigned-clock-rates = <700000000>; }; &dpll_dsp_m2_ck { assigned-clock-rates = <700000000>; }; &dpll_dsp_m3x2_ck { assigned-clock-rates = <466666667>; }; &dpll_iva_ck { assigned-clock-rates = <1064000000>; }; &dpll_iva_m2_ck { assigned-clock-rates = <532000000>; }; &dra7_pmx_core { mmc1_pins_default: mmc1_pins_default { pinctrl-single,pins = < 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_hs: pinmux_mmc1_hs_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ 0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ >; }; mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins { pinctrl-single,pins = < 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.mmc1_clk */ 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ 0x35C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ >; }; mmc2_pins_default: mmc2_pins_default { pinctrl-single,pins = < 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; mmc2_pins_hs: pinmux_mmc2_hs_pins { pinctrl-single,pins = < 0x08C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 0x090 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 0x094 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 0x098 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 0x09C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 0x0A0 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 0x0A4 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 0x0A8 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 0x0AC (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 0x0B0 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ >; }; mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins { pinctrl-single,pins = < 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ >; }; mmc2_pins_hs200_1_8v: pinmux_mmc2_hs200_1_8v_pins { pinctrl-single,pins = < 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ >; }; dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; dcan1_pins_sleep: dcan1_pins_sleep { pinctrl-single,pins = < 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; wlan_pins: pinmux_wlan_pins { pinctrl-single,pins = < 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */ >; }; wlirq_pins: pinmux_wlirq_pins { pinctrl-single,pins = < 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */ >; }; }; &dra7_iodelay_core { mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { pinctrl-single,pins = < 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ 0x620 (A_DELAY(1353) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ 0x62C (A_DELAY(1) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ 0x630 (A_DELAY(483) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ 0x638 (A_DELAY(16) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ 0x63C (A_DELAY(126) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ 0x648 (A_DELAY(104) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ 0x650 (A_DELAY(34) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ 0x654 (A_DELAY(33) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ 0x65C (A_DELAY(18) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ >; }; mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf { pinctrl-single,pins = < 0x18C (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */ 0x194 (A_DELAY(100) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ 0x1A4 (A_DELAY(391) | G_DELAY(0)) /* CFG_GPMC_A20_IN */ 0x1AC (A_DELAY(219) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ 0x1A8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ 0x1B0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_IN */ 0x1B8 (A_DELAY(24) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ 0x1B4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ 0x1BC (A_DELAY(211) | G_DELAY(0)) /* CFG_GPMC_A22_IN */ 0x1C4 (A_DELAY(88) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ 0x1C0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ 0x1C8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */ 0x1D0 (A_DELAY(626) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ 0x1D4 (A_DELAY(320) | G_DELAY(0)) /* CFG_GPMC_A24_IN */ 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ 0x1D8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ 0x1E0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ 0x1E8 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ 0x1E4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ 0x1EC (A_DELAY(159) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ 0x1F4 (A_DELAY(177) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ 0x1F0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ 0x1F8 (A_DELAY(232) | G_DELAY(0)) /* CFG_GPMC_A27_IN */ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ 0x1FC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ >; }; mmc2_iodelay_hs200_1_8v_conf: mmc2_iodelay_hs200_1_8v_conf { pinctrl-single,pins = < 0x194 (A_DELAY(0) | G_DELAY(95)) /* CFG_GPMC_A19_OUT */ 0x190 (A_DELAY(695) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ 0x1AC (A_DELAY(214) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ 0x1A8 (A_DELAY(924) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ 0x1B8 (A_DELAY(19) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ 0x1B4 (A_DELAY(719) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ 0x1C4 (A_DELAY(83) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ 0x1C0 (A_DELAY(824) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ 0x1D0 (A_DELAY(1020) | G_DELAY(416)) /* CFG_GPMC_A23_OUT */ 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ 0x1D8 (A_DELAY(877) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ 0x1E8 (A_DELAY(167) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ 0x1E4 (A_DELAY(446) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ 0x1F4 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ 0x1F0 (A_DELAY(847) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ 0x1FC (A_DELAY(586) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ 0x368 (A_DELAY(40) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ 0x364 (A_DELAY(1039) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ >; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; tps65917: tps65917@58 { compatible = "ti,tps65917"; reg = <0x58>; interrupts = ; /* IRQ_SYS_1N */ interrupt-controller; #interrupt-cells = <2>; ti,system-power-controller; tps65917_pmic { compatible = "ti,tps65917-pmic"; regulators { smps1_reg: smps1 { /* VDD_MPU */ regulator-name = "smps1"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; smps2_reg: smps2 { /* VDD_CORE */ regulator-name = "smps2"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1060000>; regulator-boot-on; regulator-always-on; }; smps3_reg: smps3 { /* VDD_GPU IVA DSPEVE */ regulator-name = "smps3"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1250000>; regulator-boot-on; regulator-always-on; }; smps4_reg: smps4 { /* VDDS1V8 */ regulator-name = "smps4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; smps5_reg: smps5 { /* VDD_DDR */ regulator-name = "smps5"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-boot-on; regulator-always-on; }; ldo1_reg: ldo1 { /* LDO1_OUT --> SDIO */ regulator-name = "ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; regulator-allow-bypass; }; ldo2_reg: ldo2 { /* LDO2_OUT --> TP1017 (UNUSED) */ regulator-name = "ldo2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-allow-bypass; }; ldo3_reg: ldo3 { /* VDDA_1V8_PHY */ regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo5_reg: ldo5 { /* VDDA_1V8_PLL */ regulator-name = "ldo5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; }; ldo4_reg: ldo4 { /* VDDA_3V_USB: VDDA_USBHS33 */ regulator-name = "ldo4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; }; }; }; tps65917_power_button { compatible = "ti,palmas-pwrbutton"; interrupt-parent = <&tps65917>; interrupts = <1 IRQ_TYPE_NONE>; wakeup-source; ti,palmas-long-press-seconds = <6>; }; }; pcf_lcd: gpio@20 { compatible = "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; }; pcf_gpio_21: gpio@21 { compatible = "ti,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio6>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; cpsw_sel_s0 { gpio-hog; gpios = <4 GPIO_ACTIVE_HIGH>; output-low; }; }; tlv320aic3106: tlv320aic3106@19 { #sound-dai-cells = <0>; compatible = "ti,tlv320aic3106"; reg = <0x19>; adc-settle-ms = <40>; ai3x-micbias-vg = <1>; /* 2.0V */ status = "okay"; /* Regulators */ AVDD-supply = <&evm_3v3>; IOVDD-supply = <&evm_3v3>; DRVDD-supply = <&evm_3v3>; DVDD-supply = <&aic_dvdd>; }; }; &i2c5 { status = "okay"; clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { compatible = "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; /* * initial state is used here to keep the mdio interface * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and * VIN2_S0 driven high otherwise Ethernet stops working * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 */ lines-initial-states = <0x0f2b>; p1 { /* vin6_sel_s0: high: VIN6, low: audio */ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-low; line-name = "vin6_sel_s0"; }; }; ov10633@37 { compatible = "ovti,ov10633"; reg = <0x37>; mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */ <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */ port { onboardLI: endpoint { remote-endpoint = <&vin2a>; hsync-active = <1>; vsync-active = <1>; pclk-sample = <0>; }; }; }; }; &uart1 { status = "okay"; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3e0>; }; &uart3 { status = "okay"; gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; }; &elm { status = "okay"; }; &gpmc { /* * For the existing IOdelay configuration via U-Boot we don't * support NAND on dra72-evm. Keep it disabled. Enabling it * requires a different configuration by U-Boot. */ status = "disabled"; ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { /* To use NAND, DIP switch SW5 must be set like so: * SW5.1 (NAND_SELn) = ON (LOW) * SW5.9 (GPMC_WPN) = OFF (HIGH) */ compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ interrupt-parent = <&crossbar_mpu>; interrupts = ; ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <80>; gpmc,cs-wr-off-ns = <80>; gpmc,adv-on-ns = <0>; gpmc,adv-rd-off-ns = <60>; gpmc,adv-wr-off-ns = <60>; gpmc,we-on-ns = <10>; gpmc,we-off-ns = <50>; gpmc,oe-on-ns = <4>; gpmc,oe-off-ns = <40>; gpmc,access-ns = <40>; gpmc,wr-access-ns = <80>; gpmc,rd-cycle-ns = <80>; gpmc,wr-cycle-ns = <80>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x000020000>; }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00020000 0x00020000>; }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00040000 0x00020000>; }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00060000 0x00020000>; }; partition@4 { label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { label = "NAND.u-boot"; reg = <0x000c0000 0x00100000>; }; partition@6 { label = "NAND.u-boot-env"; reg = <0x001c0000 0x00020000>; }; partition@7 { label = "NAND.u-boot-env.backup1"; reg = <0x001e0000 0x00020000>; }; partition@8 { label = "NAND.kernel"; reg = <0x00200000 0x00800000>; }; partition@9 { label = "NAND.file-system"; reg = <0x00a00000 0x0f600000>; }; }; }; &usb2_phy1 { phy-supply = <&ldo4_reg>; }; &usb2_phy2 { phy-supply = <&ldo4_reg>; }; &omap_dwc3_1 { extcon = <&extcon_usb1>; }; &omap_dwc3_2 { extcon = <&extcon_usb2>; }; &usb1 { dr_mode = "otg"; }; &usb2 { dr_mode = "host"; }; &mmc1 { status = "okay"; pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50"; pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_hs>; pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-3 = <&mmc1_pins_sdr25>; pinctrl-4 = <&mmc1_pins_sdr50>; pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>; vmmc-supply = <&evm_3v3_sd>; vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode * is a viable alternative */ cd-gpios = <&gpio6 27 0>; max-frequency = <192000000>; }; &mmc2 { /* SW5-3 in ON position */ status = "okay"; pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>; pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>; vmmc-supply = <&evm_3v3>; bus-width = <8>; ti,non-removable; max-frequency = <192000000>; }; &mmc4 { status = "okay"; vmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&wlan_pins &wlirq_pins>; cap-power-off-card; keep-power-in-suspend; ti,non-removable; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@0 { compatible = "ti,wl1835"; reg = <2>; interrupt-parent = <&gpio5>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; }; }; &mac { status = "okay"; slaves = <1>; }; &cpsw_emac0 { phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; }; &davinci_mdio { active_slave = <1>; }; &dcan1 { status = "ok"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; &qspi { status = "okay"; spi-max-frequency = <48000000>; m25p80@0 { compatible = "s25fl256s1"; spi-max-frequency = <48000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-cpol; spi-cpha; #address-cells = <1>; #size-cells = <1>; /* MTD partition table. * The ROM checks the first four physical blocks * for a valid file to boot and the flash here is * 64KiB block size. */ partition@0 { label = "QSPI.SPL"; reg = <0x00000000 0x000010000>; }; partition@1 { label = "QSPI.SPL.backup1"; reg = <0x00010000 0x00010000>; }; partition@2 { label = "QSPI.SPL.backup2"; reg = <0x00020000 0x00010000>; }; partition@3 { label = "QSPI.SPL.backup3"; reg = <0x00030000 0x00010000>; }; partition@4 { label = "QSPI.u-boot"; reg = <0x00040000 0x00100000>; }; partition@5 { label = "QSPI.u-boot-spl-os"; reg = <0x00140000 0x00080000>; }; partition@6 { label = "QSPI.u-boot-env"; reg = <0x001c0000 0x00010000>; }; partition@7 { label = "QSPI.u-boot-env.backup1"; reg = <0x001d0000 0x0010000>; }; partition@8 { label = "QSPI.kernel"; reg = <0x001e0000 0x0800000>; }; partition@9 { label = "QSPI.file-system"; reg = <0x009e0000 0x01620000>; }; }; }; &dss { status = "ok"; vdda_video-supply = <&ldo5_reg>; }; &hdmi { status = "ok"; vdda-supply = <&ldo3_reg>; port { hdmi_out: endpoint { remote-endpoint = <&tpd12s015_in>; }; }; }; &atl { status = "okay"; assigned-clocks = <&abe_dpll_sys_clk_mux>, <&atl_gfclk_mux>, <&dpll_abe_ck>, <&dpll_abe_m2x2_ck>, <&atl_clkin2_ck>; assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; atl2 { bws = ; aws = ; }; }; &mcasp3 { #sound-dai-cells = <0>; fck_parent = "atl_clkin2_ck"; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializer */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; tx-num-evt = <8>; rx-num-evt = <8>; }; &vip1 { status = "okay"; }; &vin2a { status = "okay"; endpoint@0 { slave-mode; remote-endpoint = <&onboardLI>; }; }; &cpu0 { cpu0-voltdm = <&voltdm_mpu>; voltage-tolerance = <1>; }; &voltdm_mpu { vdd-supply = <&smps1_reg>; }; &voltdm_core { vdd-supply = <&smps2_reg>; }; &voltdm_dspeve { vdd-supply = <&smps3_reg>; }; &voltdm_gpu { vdd-supply = <&smps3_reg>; }; &voltdm_ivahd { vdd-supply = <&smps3_reg>; }; &rtc { status = "okay"; ext-clk-src; }; &mailbox5 { status = "okay"; mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { status = "okay"; }; mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { status = "okay"; }; }; &mailbox6 { status = "okay"; mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { status = "okay"; }; }; &mmu0_dsp1 { status = "okay"; }; &mmu1_dsp1 { status = "okay"; }; &mmu_ipu1 { status = "okay"; }; &mmu_ipu2 { status = "okay"; }; &ipu2 { status = "okay"; memory-region = <&ipu2_cma_pool>; mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; timers = <&timer3>; watchdog-timers = <&timer4>, <&timer9>; }; &ipu1 { status = "okay"; memory-region = <&ipu1_cma_pool>; mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; timers = <&timer11>; }; &dsp1 { status = "okay"; memory-region = <&dsp1_cma_pool>; mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; timers = <&timer5>; };