diff options
| author | Sandeep Paulraj <s-paulraj@ti.com> | 2009-09-08 11:37:39 -0400 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-13 06:17:34 -0500 |
| commit | 7908c97a106765ad8816bf2271a5bf315728b274 (patch) | |
| tree | 0e21ae867e133c07c9eed06f82bc352a5deb2a79 /include/asm-arm/arch-davinci | |
| parent | 5d0f53624c24eaf82d58368a6a5b8476392dd5c7 (diff) | |
TI DaVinci: DM646x: Initial Support for DM646x SOC
DM646x is an SOC from TI which has both an ARM and a DSP.
There are multiple variants of the SOC mainly dealing with different
core speeds.
This patch adds the initial framework for the DM646x SOC.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'include/asm-arm/arch-davinci')
| -rw-r--r-- | include/asm-arm/arch-davinci/hardware.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index 313b3f3dba..ac32510a30 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -105,6 +105,13 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 #define DAVINCI_MMC_SD0_BASE 0x01d11000 +#elif defined(CONFIG_SOC_DM646X) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000 +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 + #endif /* Power and Sleep Controller (PSC) Domains */ @@ -153,6 +160,10 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_LPSC_GEM 39 #define DAVINCI_LPSC_IMCOP 40 +#define DAVINCI_DM646X_LPSC_EMAC 14 +#define DAVINCI_DM646X_LPSC_UART0 26 +#define DAVINCI_DM646X_LPSC_I2C 31 + void lpsc_on(unsigned int id); void dsp_on(void); |