Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

Conflicts:

	include/asm-ppc/fsl_lbc.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

5 files changed, 97 insertions, 5 deletions

diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h
index e955c756e8..227bf8326c 100644
--- a/include/asm-ppc/fsl_law.h
+++ b/include/asm-ppc/fsl_law.h
@@ -6,6 +6,9 @@
 #define SET_LAW_ENTRY(idx, a, sz, trgt) \
 	{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
 
+#define SET_LAW(a, sz, trgt) \
+	{ .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
+
 enum law_size {
 	LAW_SIZE_4K = 0xb,
 	LAW_SIZE_8K,
@@ -70,6 +73,8 @@ struct law_entry {
 };
 
 extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
 extern void disable_law(u8 idx);
 extern void init_laws(void);
 extern void print_laws(void);
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index 4529f028cc..c4af7971b1 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -59,6 +59,10 @@
 #define BR_V				0x00000001
 #define BR_V_SHIFT			0
 
+#define UPMA			0
+#define UPMB			1
+#define UPMC			2
+
 #if defined(CONFIG_MPC834X)
 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
 #else
@@ -161,11 +165,6 @@
 #define OR_UPM_EAD			0x00000001
 #define OR_UPM_EAD_SHIFT		0
 
-#define MxMR_OP_NORM			0x00000000 /* Normal Operation */
-#define MxMR_DSx_2_CYCL 		0x00400000 /* 2 cycle Disable Period */
-#define MxMR_OP_WARR			0x10000000 /* Write to Array */
-#define MxMR_BSEL			0x80000000 /* Bus Select */
-
 #define OR_SDRAM_AM			0xFFFF8000
 #define OR_SDRAM_AM_SHIFT		15
 #define OR_SDRAM_XAM			0x00006000
@@ -198,6 +197,44 @@
 #define OR_AM_2GB			0x80000000
 #define OR_AM_4GB			0x00000000
 
+/* MxMR - UPM Machine A/B/C Mode Registers
+ */
+#define MxMR_MAD_MSK		0x0000003f /* Machine Address Mask	   */
+#define MxMR_TLFx_MSK		0x000003c0 /* Refresh Loop Field Mask	   */
+#define MxMR_WLFx_MSK		0x00003c00 /* Write Loop Field Mask	   */
+#define MxMR_WLFx_1X		0x00000400 /*	executed 1 time		   */
+#define MxMR_WLFx_2X		0x00000800 /*	executed 2 times	   */
+#define MxMR_WLFx_3X		0x00000c00 /*	executed 3 times	   */
+#define MxMR_WLFx_4X		0x00001000 /*	executed 4 times	   */
+#define MxMR_WLFx_5X		0x00001400 /*	executed 5 times	   */
+#define MxMR_WLFx_6X		0x00001800 /*	executed 6 times	   */
+#define MxMR_WLFx_7X		0x00001c00 /*	executed 7 times	   */
+#define MxMR_WLFx_8X		0x00002000 /*	executed 8 times	   */
+#define MxMR_WLFx_9X		0x00002400 /*	executed 9 times	   */
+#define MxMR_WLFx_10X		0x00002800 /*	executed 10 times	   */
+#define MxMR_WLFx_11X		0x00002c00 /*	executed 11 times	   */
+#define MxMR_WLFx_12X		0x00003000 /*	executed 12 times	   */
+#define MxMR_WLFx_13X		0x00003400 /*	executed 13 times	   */
+#define MxMR_WLFx_14X		0x00003800 /*	executed 14 times	   */
+#define MxMR_WLFx_15X		0x00003c00 /*	executed 15 times	   */
+#define MxMR_WLFx_16X		0x00000000 /*	executed 16 times	   */
+#define MxMR_RLFx_MSK		0x0003c000 /* Read Loop Field Mask	   */
+#define MxMR_GPL_x4DIS		0x00040000 /* GPL_A4 Ouput Line Disable	   */
+#define MxMR_G0CLx_MSK		0x00380000 /* General Line 0 Control Mask  */
+#define MxMR_DSx_1_CYCL		0x00000000 /* 1 cycle Disable Period	   */
+#define MxMR_DSx_2_CYCL		0x00400000 /* 2 cycle Disable Period	   */
+#define MxMR_DSx_3_CYCL		0x00800000 /* 3 cycle Disable Period	   */
+#define MxMR_DSx_4_CYCL		0x00c00000 /* 4 cycle Disable Period	   */
+#define MxMR_DSx_MSK		0x00c00000 /* Disable Timer Period Mask	   */
+#define MxMR_AMx_MSK		0x07000000 /* Addess Multiplex Size Mask   */
+#define MxMR_OP_NORM		0x00000000 /* Normal Operation		   */
+#define MxMR_OP_WARR		0x10000000 /* Write to Array		   */
+#define MxMR_OP_RARR		0x20000000 /* Read from Array		   */
+#define MxMR_OP_RUNP		0x30000000 /* Run Pattern		   */
+#define MxMR_OP_MSK		0x30000000 /* Command Opcode Mask	   */
+#define MxMR_RFEN		0x40000000 /* Refresh Enable		   */
+#define MxMR_BSEL		0x80000000 /* Bus Select		   */
+
 #define LBLAWAR_EN			0x80000000
 #define LBLAWAR_4KB			0x0000000B
 #define LBLAWAR_8KB			0x0000000C
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index ea702662f8..8cf7b6fb3d 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -96,6 +96,9 @@ typedef	struct	global_data {
 	uint mp_alloc_base;
 	uint mp_alloc_top;
 #endif /* CONFIG_QE */
+#if defined(CONFIG_FSL_LAW)
+	u32 used_laws;
+#endif
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	ipb_clk;
 	unsigned long	pci_clk;
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 7cc28bfe3a..c3496818f0 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -238,6 +238,42 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
 /*
  * Given a physical address and a length, return a virtual address
  * that can be used to access the memory range with the caching
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 8bdfb9ddf3..61a0d053e2 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -960,6 +960,17 @@ n:
 #define SR15	15
 
 #ifndef __ASSEMBLY__
+
+struct cpu_type {
+	char name[15];
+	u32 soc_ver;
+};
+
+struct cpu_type *identify_cpu(uint ver);
+
+#define CPU_TYPE_ENTRY(n, v) \
+	{ .name = #n, .soc_ver = SVR_##v, }
+
 #ifndef CONFIG_MACH_SPECIFIC
 extern int _machine;
 extern int have_of;