diff options
298 files changed, 3634 insertions, 1456 deletions
diff --git a/.travis.yml b/.travis.yml index 8bd49ef1a5..6662ca126a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -50,6 +50,7 @@ install: - . /tmp/venv/bin/activate - pip install pytest==2.8.7 - pip install python-subunit + - pip install pyelftools - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - mkdir ~/grub2-arm @@ -183,6 +184,9 @@ matrix: - name: "buildman NXP AArch64 LS101x" env: - BUILDMAN="freescale&aarch64&ls101" + - name: "buildman NXP AArch64 LS102x" + env: + - BUILDMAN="freescale&aarch64&ls102" - name: "buildman NXP AArch64 LS104x" env: - BUILDMAN="freescale&aarch64&ls104" @@ -192,6 +196,9 @@ matrix: - name: "buildman NXP AArch64 LS20xx" env: - BUILDMAN="freescale&aarch64&&ls20" + - name: "buildman NXP AArch64 LX216x" + env: + - BUILDMAN="freescale&aarch64&lx216" - name: "buildman i.MX6 (non-NXP)" env: - BUILDMAN="mx6 -x freescale,toradex,boundary,engicam" @@ -20,6 +20,13 @@ config BROKEN This option cannot be enabled. It is used as dependency for broken and incomplete features. +config DEPRECATED + bool + help + This option cannot be enabled. It it used as a dependency for + code that relies on deprecated features that will be removed and + the conversion deadline has passed. + config LOCALVERSION string "Local version - append to U-Boot release" help @@ -243,7 +250,7 @@ config BUILD_TARGET default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 - default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI + default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI) default "u-boot.kwb" if KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help diff --git a/MAINTAINERS b/MAINTAINERS index 8e26eda2c8..bea3122f2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -55,7 +55,7 @@ M: Alexey Brodkin <alexey.brodkin@synopsys.com> M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> S: Maintained L: uboot-snps-arc@synopsys.com -T: git git://git.denx.de/u-boot-arc.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-arc.git F: arch/arc/ F: board/synopsys/ @@ -84,7 +84,7 @@ F: drivers/mmc/snps_dw_mmc.c ARM M: Albert Aribaud <albert.u.boot@aribaud.net> S: Maintained -T: git git://git.denx.de/u-boot-arm.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-arm.git F: arch/arm/ F: cmd/arm/ @@ -92,14 +92,14 @@ ARM ALTERA SOCFPGA M: Marek Vasut <marex@denx.de> M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> S: Maintainted -T: git git://git.denx.de/u-boot-socfpga.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git F: arch/arm/mach-socfpga/ ARM AMLOGIC SOC SUPPORT M: Neil Armstrong <narmstrong@baylibre.com> S: Maintained L: u-boot-amlogic@groups.io -T: git git://git.denx.de/u-boot-amlogic.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git F: arch/arm/mach-meson/ F: arch/arm/include/asm/arch-meson/ F: drivers/clk/meson/ @@ -153,7 +153,7 @@ M: Stefano Babic <sbabic@denx.de> M: Fabio Estevam <festevam@gmail.com> R: NXP i.MX U-Boot Team <uboot-imx@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-imx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git F: arch/arm/cpu/arm1136/mx*/ F: arch/arm/cpu/arm926ejs/mx*/ F: arch/arm/cpu/armv7/vf610/ @@ -174,7 +174,7 @@ F: arch/arm/include/asm/arch-hi6220/ ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese <sr@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-marvell.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-marvell.git F: arch/arm/mach-kirkwood/ F: arch/arm/mach-mvebu/ F: drivers/ata/ahci_mvebu.c @@ -188,7 +188,7 @@ F: drivers/watchdog/orion_wdt.c ARM MARVELL PXA M: Marek Vasut <marex@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-pxa.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ @@ -217,7 +217,7 @@ N: mediatek ARM MICROCHIP/ATMEL AT91 M: Eugen Hristev <eugen.hristev@microchip.com> S: Maintained -T: git git://git.denx.de/u-boot-atmel.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git F: arch/arm/mach-at91/ F: board/atmel/ @@ -234,7 +234,7 @@ ARM RENESAS RMOBILE/R-CAR M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> M: Marek Vasut <marek.vasut+renesas@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-sh.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git F: arch/arm/mach-rmobile/ ARM ROCKCHIP @@ -242,7 +242,7 @@ M: Simon Glass <sjg@chromium.org> M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> M: Kever Yang <kever.yang@rock-chips.com> S: Maintained -T: git git://git.denx.de/u-boot-rockchip.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git F: arch/arm/include/asm/arch-rockchip/ F: arch/arm/mach-rockchip/ F: board/rockchip/ @@ -264,7 +264,7 @@ F: tools/rkspi.c ARM SAMSUNG M: Minkyu Kang <mk7.kang@samsung.com> S: Maintained -T: git git://git.denx.de/u-boot-samsung.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.git F: arch/arm/mach-exynos/ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ @@ -289,13 +289,12 @@ F: arch/arm/include/asm/arch-sti*/ ARM STM SPEAR #M: Vipin Kumar <vipin.kumar@st.com> S: Orphaned (Since 2016-02) -T: git git://git.denx.de/u-boot-stm.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git F: arch/arm/cpu/arm926ejs/spear/ F: arch/arm/include/asm/arch-spear/ ARM STM STM32MP M: Patrick Delaunay <patrick.delaunay@st.com> -M: Christophe Kerello <christophe.kerello@st.com> M: Patrice Chotard <patrice.chotard@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) S: Maintained @@ -326,7 +325,7 @@ ARM SUNXI M: Jagan Teki <jagan@amarulasolutions.com> M: Maxime Ripard <maxime.ripard@bootlin.com> S: Maintained -T: git git://git.denx.de/u-boot-sunxi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git F: arch/arm/cpu/armv7/sunxi/ F: arch/arm/include/asm/arch-sunxi/ F: arch/arm/mach-sunxi/ @@ -335,14 +334,14 @@ F: board/sunxi/ ARM TEGRA M: Tom Warren <twarren@nvidia.com> S: Maintained -T: git git://git.denx.de/u-boot-tegra.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-tegra.git F: arch/arm/mach-tegra/ F: arch/arm/include/asm/arch-tegra*/ ARM TI M: Tom Rini <trini@konsulko.com> S: Maintained -T: git git://git.denx.de/u-boot-ti.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git F: arch/arm/mach-davinci/ F: arch/arm/mach-k3/ F: arch/arm/mach-keystone/ @@ -352,7 +351,7 @@ F: arch/arm/include/asm/ti-common/ ARM UNIPHIER M: Masahiro Yamada <yamada.masahiro@socionext.com> S: Maintained -T: git git://git.denx.de/u-boot-uniphier.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier.git F: arch/arm/mach-uniphier/ F: configs/uniphier_*_defconfig N: uniphier @@ -360,7 +359,7 @@ N: uniphier ARM VERSAL M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ ARM VERSATILE EXPRESS DRIVERS @@ -373,7 +372,7 @@ N: vexpress ARM ZYNQ M: Michal Simek <monstr@monstr.eu> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynq/ F: drivers/clk/clk_zynq.c F: drivers/fpga/zynqpl.c @@ -397,7 +396,7 @@ N: zynq ARM ZYNQMP M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp/ F: drivers/clk/clk_zynqmp.c F: drivers/fpga/zynqpl.c @@ -423,7 +422,7 @@ N: zynqmp ARM ZYNQMP R5 M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp-r5/ BINMAN @@ -439,7 +438,7 @@ F: tools/buildman/ CFI FLASH M: Stefan Roese <sr@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-cfi-flash.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash.git F: drivers/mtd/cfi_flash.c F: drivers/mtd/jedec_flash.c @@ -447,13 +446,13 @@ COLDFIRE M: Huan Wang <alison.wang@nxp.com> M: Angelo Dureghello <angelo@sysam.it> S: Maintained -T: git git://git.denx.de/u-boot-coldfire.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-coldfire.git F: arch/m68k/ DFU M: Lukasz Majewski <lukma@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-dfu.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-dfu.git F: cmd/dfu.c F: cmd/usb_*.c F: common/dfu.c @@ -465,7 +464,7 @@ F: drivers/usb/gadget/ DRIVER MODEL M: Simon Glass <sjg@chromium.org> S: Maintained -T: git git://git.denx.de/u-boot-dm.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-dm.git F: drivers/core/ F: include/dm/ F: test/dm/ @@ -474,10 +473,10 @@ EFI PAYLOAD M: Heinrich Schuchardt <xypron.glpk@gmx.de> R: Alexander Graf <agraf@csgraf.de> S: Maintained -T: git git://git.denx.de/u-boot-efi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git F: doc/README.uefi F: doc/README.iscsi -F: Documentation/efi.rst +F: doc/efi.rst F: include/capitalization.h F: include/charset.h F: include/cp1250.h @@ -497,7 +496,7 @@ F: tools/file2include.c FPGA M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: drivers/fpga/ F: cmd/fpga.c F: include/fpga.h @@ -505,7 +504,7 @@ F: include/fpga.h FLATTENED DEVICE TREE M: Simon Glass <sjg@chromium.org> S: Maintained -T: git git://git.denx.de/u-boot-fdt.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fdt.git F: lib/fdtdec* F: lib/libfdt/ F: include/fdt* @@ -516,24 +515,24 @@ F: common/fdt_support.c FREEBSD M: Rafal Jaworowski <raj@semihalf.com> S: Maintained -T: git git://git.denx.de/u-boot-freebsd.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-freebsd.git FREESCALE QORIQ M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-fsl-qoriq.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git F: drivers/watchdog/sp805_wdt.c I2C M: Heiko Schocher <hs@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-i2c.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-i2c.git F: drivers/i2c/ LOGGING M: Simon Glass <sjg@chromium.org> S: Maintained -T: git git://git.denx.de/u-boot.git +T: git https://gitlab.denx.de/u-boot/u-boot.git F: common/log.c F: cmd/log.c F: test/log/log_test.c @@ -549,7 +548,7 @@ F: drivers/i2c/i2c-versatile.c MICROBLAZE M: Michal Simek <monstr@monstr.eu> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/microblaze/ F: cmd/mfsl.c F: drivers/gpio/xilinx_gpio.c @@ -564,7 +563,7 @@ N: xilinx MIPS M: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-mips.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git F: arch/mips/ MIPS MSCC @@ -595,38 +594,38 @@ F: arch/mips/mach-jz47xx/ MMC M: Peng Fan <peng.fan@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-mmc.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git F: drivers/mmc/ NAND FLASH #M: Scott Wood <oss@buserror.net> S: Orphaned (Since 2018-07) -T: git git://git.denx.de/u-boot-nand-flash.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash.git F: drivers/mtd/nand/raw/ NDS32 M: Macpaul Lin <macpaul@andestech.com> S: Maintained -T: git git://git.denx.de/u-boot-nds32.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nds32.git F: arch/nds32/ NETWORK M: Joe Hershberger <joe.hershberger@ni.com> S: Maintained -T: git git://git.denx.de/u-boot-net.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-net.git F: drivers/net/ F: net/ NIOS M: Thomas Chou <thomas@wytron.com.tw> S: Maintained -T: git git://git.denx.de/u-boot-nios.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nios.git F: arch/nios2/ ONENAND #M: Lukasz Majewski <l.majewski@majess.pl> S: Orphaned (Since 2017-01) -T: git git://git.denx.de/u-boot-onenand.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-onenand.git F: drivers/mtd/onenand/ PATMAN @@ -637,7 +636,7 @@ F: tools/patman/ POWER M: Jaehoon Chung <jh80.chung@samsung.com> S: Maintained -T: git git://git.denx.de/u-boot-pmic.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-pmic.git F: drivers/power/ POWERPC @@ -648,13 +647,13 @@ F: arch/powerpc/ POWERPC MPC8XX M: Christophe Leroy <christophe.leroy@c-s.fr> S: Maintained -T: git git://git.denx.de/u-boot-mpc8xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc8xx.git F: arch/powerpc/cpu/mpc8xx/ POWERPC MPC83XX M: Mario Six <mario.six@gdsys.cc> S: Maintained -T: git git://git.denx.de/u-boot-mpc83xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx.git F: drivers/ram/mpc83xx_sdram.c F: include/dt-bindings/memory/mpc83xx-sdram.h F: drivers/sysreset/sysreset_mpc83xx.c @@ -672,19 +671,19 @@ F: arch/powerpc/include/asm/arch-mpc83xx/ POWERPC MPC85XX M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-mpc85xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx.git F: arch/powerpc/cpu/mpc85xx/ POWERPC MPC86XX M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-mpc86xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc86xx.git F: arch/powerpc/cpu/mpc86xx/ RISC-V M: Rick Chen <rick@andestech.com> S: Maintained -T: git git://git.denx.de/u-boot-riscv.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git F: arch/riscv/ F: cmd/riscv/ F: tools/prelink-riscv.c @@ -702,15 +701,16 @@ S: Maintained F: arch/sandbox/ SH +M: Marek Vasut <marek.vasut+renesas@gmail.com> M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> S: Maintained -T: git git://git.denx.de/u-boot-sh.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git F: arch/sh/ SPI M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained -T: git git://git.denx.de/u-boot-spi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-spi.git F: drivers/spi/ F: include/spi* @@ -772,25 +772,25 @@ UBI M: Kyungmin Park <kmpark@infradead.org> M: Heiko Schocher <hs@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-ubi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ USB M: Marek Vasut <marex@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-usb.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git F: drivers/usb/ USB xHCI M: Bin Meng <bmeng.cn@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-usb.git topic-xhci +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci F: drivers/usb/host/xhci* VIDEO M: Anatolij Gustschin <agust@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-video.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-video.git F: drivers/video/ F: common/lcd*.c F: include/lcd*.h @@ -800,7 +800,7 @@ X86 M: Simon Glass <sjg@chromium.org> M: Bin Meng <bmeng.cn@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-x86.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git F: arch/x86/ F: cmd/x86/ @@ -814,7 +814,7 @@ M: Tom Rini <trini@konsulko.com> L: u-boot@lists.denx.de Q: http://patchwork.ozlabs.org/project/uboot/list/ S: Maintained -T: git git://git.denx.de/u-boot.git +T: git https://gitlab.denx.de/u-boot/u-boot.git F: configs/tools-only_defconfig F: * F: */ @@ -168,7 +168,7 @@ MAKEFLAGS += --no-print-directory # Use 'make C=2' to enable checking of *all* source files, regardless # of whether they are re-compiled or not. # -# See the file "Documentation/sparse.txt" for more details, including +# See the file "doc/sparse.txt" for more details, including # where to get the "sparse" utility. ifeq ("$(origin C)", "command line") @@ -928,6 +928,14 @@ cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \ $(srctree)/scripts/config_whitelist.txt $(srctree) all: $(ALL-y) +ifeq ($(CONFIG_DEPRECATED),y) + $(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.") +ifeq ($(CONFIG_SPI),y) +ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy) + $(warning "The relevant config item with associated code will remove in v2019.07 release.") +endif +endif +endif ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y) @echo >&2 "===================== WARNING ======================" @echo >&2 "This board uses CONFIG_DM_I2C_COMPAT. Please remove" @@ -1004,17 +1012,6 @@ ifeq ($(CONFIG_OF_EMBED),y) @echo >&2 "See doc/README.fdt-control for more info." @echo >&2 "====================================================" endif -ifeq ($(CONFIG_SPI),y) -ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy) - @echo >&2 "===================== WARNING ======================" - @echo >&2 "This board does not use CONFIG_DM_SPI. Please update" - @echo >&2 "the board before v2019.04 for no dm conversion" - @echo >&2 "and v2019.07 for partially dm converted drivers." - @echo >&2 "Failure to update can lead to driver/board removal" - @echo >&2 "See doc/driver-model/MIGRATION.txt for more info." - @echo >&2 "====================================================" -endif -endif ifeq ($(CONFIG_SPI_FLASH),y) ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy) @echo >&2 "===================== WARNING ======================" @@ -1850,7 +1847,8 @@ clean: $(clean-dirs) -o -name modules.builtin -o -name '.tmp_*.o.*' \ -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \ -o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \ - -type f -print | xargs rm -f + -type f -print | xargs rm -f \ + bl31.c bl31.elf bl31_*.bin image.map # mrproper - Delete all generated files, including .config # @@ -1919,7 +1917,7 @@ help: @echo ' coccicheck - Execute static code analysis with Coccinelle' @echo '' @echo 'Documentation targets:' - @$(MAKE) -f $(srctree)/Documentation/Makefile dochelp + @$(MAKE) -f $(srctree)/doc/Makefile dochelp @echo '' @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build' @echo ' make V=2 [targets] 2 => give reason for rebuild of target' @@ -1948,7 +1946,7 @@ DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \ linkcheckdocs dochelp refcheckdocs PHONY += $(DOC_TARGETS) $(DOC_TARGETS): scripts_basic FORCE - $(Q)$(MAKE) $(build)=Documentation $@ + $(Q)$(MAKE) $(build)=doc $@ endif #ifeq ($(config-targets),1) endif #ifeq ($(mixed-targets),1) diff --git a/arch/Kconfig b/arch/Kconfig index e574b0d441..28afe39801 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -101,6 +101,7 @@ config SANDBOX imply CMD_IOTRACE imply CMD_LZMADEC imply CMD_SATA + imply CMD_SF imply CMD_SF_TEST imply CRC32_VERIFY imply FAT_WRITE @@ -147,6 +148,7 @@ config X86 imply CMD_IO imply CMD_IRQ imply CMD_PCI + imply CMD_SF imply CMD_SF_TEST imply CMD_ZBOOT imply DM_ETH diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 01ff57cf1b..f5a7630e4f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1406,14 +1406,24 @@ config TARGET_LS1046ARDB development platform that supports the QorIQ LS1046A Layerscape Architecture processor. +config TARGET_LS1046AFRWY + bool "Support ls1046afrwy" + select ARCH_LS1046A + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select DM_SPI_FLASH if DM_SPI + imply SCSI + help + Support for Freescale LS1046AFRWY platform. + The LS1046A Freeway Board (FRWY) is a high-performance + development platform that supports the QorIQ LS1046A + Layerscape Architecture processor. config TARGET_H2200 bool "Support h2200" select CPU_PXA -config TARGET_ZIPITZ2 - bool "Support zipitz2" - select CPU_PXA - config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA @@ -1697,6 +1707,7 @@ source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/ls1046ardb/Kconfig" +source "board/freescale/ls1046afrwy/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" @@ -1727,7 +1738,6 @@ source "board/woodburn/Kconfig" source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" -source "board/zipitz2/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 8a97d5b3fb..92a2b58ed4 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -107,6 +107,7 @@ config PSCI_RESET !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ + !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !TARGET_LX2160AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a843c1eb65..3f6c983aaf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -48,6 +48,7 @@ config ARCH_LS1028A select SYS_I2C_MXC_I2C6 select SYS_I2C_MXC_I2C7 select SYS_I2C_MXC_I2C8 + select SYS_FSL_ERRATUM_A008997 select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A008514 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 11117657fe..fabe0f0359 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -435,7 +435,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); -#ifdef CONFIG_PCI +#ifdef CONFIG_PCI_LAYERSCAPE ft_pci_setup(blob, bd); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 723d7eac5d..9ece4b90e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP. */ #include <common.h> @@ -250,6 +251,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index bc268e207c..a5540f2b9d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015, Freescale Semiconductor, Inc. + * Copyright 2019 NXP Semiconductors * * Derived from arch/power/cpu/mpc85xx/speed.c */ @@ -214,6 +215,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: + case MXC_ESDHC2_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6721a579ea..711ab87556 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014-2015 Freescale Semiconductor + * Copyright 2019 NXP * * Extracted from armv8/start.S */ @@ -356,31 +357,22 @@ get_svr: #if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: - /* x0 has the desired status, return 0 for success, 1 for timeout - * clobber x1, x2, x3, x4, x6, x7 + /* x0 has the desired status, return only if operation succeed + * clobber x1, x2, x6 */ mov x1, x0 - mov x7, #0 /* flag for timeout */ - mrs x3, cntpct_el0 /* read timer */ - add x3, x3, #1200 /* timeout after 100 microseconds */ + mov w6, #8 /* HN-F node count */ mov x0, #0x18 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ - mov w6, #8 /* HN-F node count */ 1: ldr x2, [x0] cmp x2, x1 /* check status */ b.eq 2f - mrs x4, cntpct_el0 - cmp x4, x3 - b.ls 1b - mov x7, #1 /* timeout */ - b 3f + b 1b 2: add x0, x0, #0x10000 /* move to next node */ subs w6, w6, #1 cbnz w6, 1b -3: - mov x0, x7 ret hnf_set_pstate: @@ -405,10 +397,8 @@ ENTRY(__asm_flush_l3_dcache) /* * Return status in x0 * success 0 - * timeout 1 for setting SFONLY, 2 for FAM, 3 for both */ mov x29, lr - mov x8, #0 dsb sy mov x0, #0x1 /* HNFPSTAT_SFONLY */ @@ -416,19 +406,15 @@ ENTRY(__asm_flush_l3_dcache) mov x0, #0x4 /* SFONLY status */ bl hnf_pstate_poll - cbz x0, 1f - mov x8, #1 /* timeout */ -1: + dsb sy mov x0, #0x3 /* HNFPSTAT_FAM */ bl hnf_set_pstate mov x0, #0xc /* FAM status */ bl hnf_pstate_poll - cbz x0, 1f - add x8, x8, #0x2 -1: - mov x0, x8 + + mov x0, #0 mov lr, x29 ret ENDPROC(__asm_flush_l3_dcache) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c index ef598c4cba..5835a3a69e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c @@ -22,6 +22,19 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} }, {0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} }, {0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {0xE031, {SXGMII1, QXGMII2, NONE, SATA1} }, + {0xB991, {SXGMII1, SGMII1, SGMII2, PCIE1} }, + {0xBB31, {SXGMII1, QXGMII2, PCIE1, PCIE1} }, + {0xCC31, {SXGMII1, QXGMII2, PCIE2, PCIE2} }, + {0xBB51, {SXGMII1, QSGMII_B, PCIE2, PCIE1} }, + {0xBB38, {SGMII_T1, QXGMII2, PCIE2, PCIE1} }, + {0xCC38, {SGMII_T1, QXGMII2, PCIE2, PCIE2} }, + {0xBB58, {SGMII_T1, QSGMII_B, PCIE2, PCIE1} }, + {0xCC58, {SGMII_T1, QSGMII_B, PCIE2, PCIE2} }, + {0xCC8B, {PCIE1, SGMII_T1, PCIE2, PCIE2} }, + {0xEB58, {SGMII_T1, QSGMII_B, PCIE2, SATA1} }, + {0xEB8B, {PCIE1, SGMII_T1, PCIE2, SATA1} }, + {0xE8CC, {PCIE1, PCIE1, SGMII_T1, SATA1} }, {} }; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c index f8310f2105..9347e516bf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -29,10 +30,11 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, - {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, + {0x3363, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6} }, {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x3040, {SGMII_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} }, {} }; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 06f3edb302..7414215208 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor + * Copyright 2019 NXP */ #include <common.h> @@ -126,6 +127,10 @@ static void erratum_a008997(void) set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); #endif +#elif defined(CONFIG_ARCH_LS1028A) + clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1, + 0x7F << 11, + DCSR_USB_PCSTXSWINGFULL << 11); #endif #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } @@ -139,7 +144,8 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -163,7 +169,8 @@ static void erratum_a009007(void) usb_phy = (void __iomem *)SCFG_USB_PHY3; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); #endif -#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); @@ -593,6 +600,9 @@ void fsl_lsch2_early_init_f(void) struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; +#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) + enum boot_src src; +#endif #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); @@ -602,9 +612,15 @@ void fsl_lsch2_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ #endif +#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) + src = get_boot_src(); + if (src != BOOT_SOURCE_QSPI_NOR) + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#else #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif +#endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | @@ -808,7 +824,11 @@ int board_late_init(void) * check if gd->env_addr is default_environment; then setenv bootcmd * and mcinitcmd. */ +#if !defined(CONFIG_ENV_ADDR) || defined(ENV_IS_EMBEDDED) + if (gd->env_addr == (ulong)&default_environment[0]) { +#else if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { +#endif fsl_setenv_bootcmd(); fsl_setenv_mcinitcmd(); } diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index fe52166e28..99d126660d 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -18,7 +18,7 @@ .globl _start _start: -#if defined(LINUX_KERNEL_IMAGE_HEADER) +#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER) #include <asm/boot0-linux-kernel-header.h> #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) /* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2271d78729..7fbd0a1d06 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb + rk3328-evb.dtb \ + rk3328-rock64.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ @@ -342,6 +343,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1046a-qds-duart.dtb \ fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ + fsl-ls1046a-frwy.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ fsl-ls1012a-2g5rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index e6a443aa77..49074112c4 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -108,6 +108,17 @@ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + pcie@1f0000000 { + compatible = "pci-host-ecam-generic"; + /* ECAM bus 0, HW has more space reserved but not populated */ + bus-range = <0x0 0x0>; + reg = <0x01 0xf0000000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; + }; + i2c0: i2c@2000000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; @@ -272,9 +283,10 @@ sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; interrupts = <0 133 4>; - clocks = <&clockgen 4 1>; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts new file mode 100644 index 0000000000..3d41e3bd44 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device Tree Include file for NXP Layerscape-1046A family SoC. + * + * Copyright 2019 NXP + * + */ + +/dts-v1/; +/include/ "fsl-ls1046a.dtsi" + +/ { + model = "LS1046A FRWY Board"; + + aliases { + spi0 = &qspi; + }; + +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: mt25qu512abb8esf@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + +}; + diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 6192156fc3..99836c4ccb 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -15,3 +15,26 @@ compatible = "fsl,lx2160aqds", "fsl,lx2160a"; }; +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 8a0f473e25..7fb24ab687 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -406,8 +406,7 @@ sata: sata@3200000 { compatible = "fsl,ls1021a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x0 0x20220520 0x0 0x4>; /* ecc sata addr*/ + reg = <0x3200000 0x10000 0x20220520 0x4>; reg-names = "sata-base", "ecc-addr"; interrupts = <0 101 4>; status = "disabled"; diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 0000000000..b077436cbc --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 0000000000..7bcc53fcce --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index ca0fc391b2..0e2e047180 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -629,7 +629,6 @@ ap_i2c_audio: &i2c8 { &uart2 { status = "okay"; - u-boot,dm-pre-reloc; }; &usb_host0_ohci { diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 897e0bda85..74368da550 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -639,7 +639,6 @@ }; &uart0 { - u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts>; status = "okay"; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 0786c1193a..fcfce9ae02 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -10,3 +10,11 @@ &spi1 { u-boot,dm-pre-reloc; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index ade7285786..d8f9d8dc5f 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -78,10 +78,6 @@ }; }; -&clk_hse { - u-boot,dm-pre-reloc; -}; - &fmc { /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ bank1: bank@0 { @@ -123,9 +119,7 @@ }; fmc_pins: fmc@0 { - u-boot,dm-pre-reloc; pins { - u-boot,dm-pre-reloc; pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */ <STM32_PINMUX('D', 9, AF12)>, /* D14 */ <STM32_PINMUX('D', 8, AF12)>, /* D13 */ diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 53a645dace..209a82c9cf 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -152,6 +152,16 @@ slew-rate = <2>; }; }; + + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; }; &qspi { diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 5b19e44d2f..994092a195 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -56,10 +56,6 @@ }; }; -&usbotg_hs { - g-tx-fifo-size = <576>; -}; - &v3v3 { regulator-always-on; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index cf058d22a9..b37a08d265 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP Semiconductors * */ @@ -14,6 +15,7 @@ enum mxc_clock { MXC_BUS_CLK, MXC_UART_CLK, MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, MXC_I2C_CLK, MXC_DSPI_CLK, }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index bdeb62576c..7759acdb8f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -42,7 +42,9 @@ #else #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#endif #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 #define SYS_PCIE5_PHYS_SIZE 0x800000000 #define SYS_PCIE6_PHYS_SIZE 0x800000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 68354ff546..8f43651756 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -64,6 +64,18 @@ enum srds_prtcl { QSGMII_B, QSGMII_C, QSGMII_D, + SGMII_T1, + SGMII_T2, + SGMII_T3, + SGMII_T4, + SXGMII1, + SXGMII2, + SXGMII3, + SXGMII4, + QXGMII1, + QXGMII2, + QXGMII3, + QXGMII4, _25GE1, _25GE2, _25GE3, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 24c1b0e482..ee9b33becf 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -186,6 +186,9 @@ #elif CONFIG_ARCH_LS1028A #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL +/* this is used by integrated PCI on LS1028, includes ECAM and register space */ +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL #else #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL @@ -226,6 +229,8 @@ #define USB_PHY_RX_EQ_VAL_2 0x0080 #define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_4 0x0b80 +#define DCSR_USB_IOCR1 0x108004 +#define DCSR_USB_PCSTXSWINGFULL 0x71 #define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f48..1624b084b9 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -158,6 +165,7 @@ config ROCKCHIP_RK3399 select SPL select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_BOARD_INIT if SPL select SPL_LOAD_FIT select SPL_CLK if SPL select SPL_PINCTRL if SPL @@ -183,6 +191,7 @@ config ROCKCHIP_RK3399 imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOARD_INIT imply TPL_BOOTROM_SUPPORT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_OF_CONTROL diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a..23760a959a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 212bd0a854..45ec105887 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -12,6 +12,7 @@ import os import sys import getopt +import logging # pip install pyelftools from elftools.elf.elffile import ELFFile @@ -89,13 +90,17 @@ def append_conf_section(file, cnt, dtname, segments): file.write('\t\tconfig_%d {\n' % cnt) file.write('\t\t\tdescription = "%s";\n' % dtname) file.write('\t\t\tfirmware = "atf_1";\n') - file.write('\t\t\tloadables = "uboot",') + file.write('\t\t\tloadables = "uboot"') + if segments != 0: + file.write(',') for i in range(1, segments): file.write('"atf_%d"' % (i)) if i != (segments - 1): file.write(',') else: file.write(';\n') + if segments == 0: + file.write(';\n') file.write('\t\t\tfdt = "fdt_1";\n') file.write('\t\t};\n') file.write('\n') @@ -171,8 +176,18 @@ def generate_atf_binary(bl31_file_name): def main(): uboot_elf = "./u-boot" - bl31_elf = "./bl31.elf" fit_its = sys.stdout + if "BL31" in os.environ: + bl31_elf=os.getenv("BL31"); + elif os.path.isfile("./bl31.elf"): + bl31_elf = "./bl31.elf" + else: + os.system("echo 'int main(){}' > bl31.c") + os.system("${CROSS_COMPILE}gcc -c bl31.c -o bl31.elf") + bl31_elf = "./bl31.elf" + logging.basicConfig(format='%(levelname)s:%(message)s', level=logging.DEBUG) + logging.warning(' BL31 file bl31.elf NOT found, resulting binary is non-functional') + logging.warning(' Please read Building section in doc/README.rockchip') opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h") for opt, val in opts: diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 0000000000..7f49d056a0 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 800ca80022..890d80025f 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -11,13 +11,16 @@ #include <spl.h> #include <spl_gpio.h> #include <syscon.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/periph.h> #include <asm/arch-rockchip/sys_proto.h> +#include <power/regulator.h> #include <dm/pinctrl.h> void board_return_to_bootrom(void) @@ -161,7 +164,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot SPL board init\n"); + debug("U-Boot SPL board init\n"); #endif ret = spl_early_init(); @@ -202,6 +205,66 @@ void board_init_f(ulong dummy) } } +#if defined(SPL_GPIO_SUPPORT) +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} +#endif + +void spl_board_init(void) +{ +#if defined(SPL_GPIO_SUPPORT) + struct rk3399_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); +#endif + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif + + preloader_console_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c index 86d3ffe97c..4a301249b4 100644 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -8,6 +8,7 @@ #include <dm.h> #include <ram.h> #include <spl.h> +#include <version.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> @@ -46,7 +47,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot TPL board init\n"); + debug("U-Boot TPL board init\n"); #endif ret = spl_early_init(); if (ret) { @@ -73,6 +74,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_BOOTROM; } +void spl_board_init(void) +{ + puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " + U_BOOT_TIME " " U_BOOT_TZ ")\n"); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 6ae31d3a1f..41338a1a33 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -18,7 +18,7 @@ int arch_cpu_init(void) */ #if defined(CONFIG_STM32F4) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_16MB }, + O_I_WB_RD_WR_ALLOC, REGION_512MB }, #endif { 0x90000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index aebf168a89..7572404625 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -533,6 +533,7 @@ config ARCH_BSC9132 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_ERRATUM_IFC_A002769 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -551,6 +552,7 @@ config ARCH_C29X select SYS_FSL_DDR_VER_46 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -566,6 +568,7 @@ config ARCH_MPC8536 select FSL_LAW select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -594,6 +597,7 @@ config ARCH_MPC8544 bool select FSL_LAW select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -609,6 +613,7 @@ config ARCH_MPC8548 select SYS_FSL_ERRATUM_NMG_LBC103 select SYS_FSL_ERRATUM_NMG_ETSEC129 select SYS_FSL_ERRATUM_I2C_A004447 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC @@ -633,6 +638,7 @@ config ARCH_MPC8560 config ARCH_MPC8568 bool select FSL_LAW + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -643,6 +649,7 @@ config ARCH_MPC8569 select FSL_LAW select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -657,6 +664,7 @@ config ARCH_MPC8572 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_DDR_115 select SYS_FSL_ERRATUM_DDR111_DDR134 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -681,6 +689,7 @@ config ARCH_P1010 select SYS_FSL_ERRATUM_P1010_A003549 select SYS_FSL_ERRATUM_SEC_A003571 select SYS_FSL_ERRATUM_IFC_A003399 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -702,6 +711,7 @@ config ARCH_P1011 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -716,6 +726,8 @@ config ARCH_P1020 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -735,6 +747,8 @@ config ARCH_P1021 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -756,6 +770,7 @@ config ARCH_P1022 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_SATA_A001 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -769,6 +784,7 @@ config ARCH_P1023 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_I2C_A004447 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -782,6 +798,8 @@ config ARCH_P1024 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -802,6 +820,8 @@ config ARCH_P1025 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -819,6 +839,7 @@ config ARCH_P2020 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC_A001 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -1074,6 +1095,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 @@ -1096,6 +1118,7 @@ config ARCH_T2081 select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 @@ -1429,6 +1452,12 @@ config SYS_P4080_ERRATUM_SERDES_A001 config SYS_P4080_ERRATUM_SERDES_A005 bool +config FSL_PCIE_DISABLE_ASPM + bool + +config FSL_PCIE_RESET + bool + config SYS_FSL_QORIQ_CHASSIS1 bool diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c index 90ccc3427c..1d0213a513 100644 --- a/arch/powerpc/cpu/mpc85xx/pci.c +++ b/arch/powerpc/cpu/mpc85xx/pci.c @@ -12,7 +12,7 @@ #include <asm/cpm_85xx.h> #include <pci.h> -#if !defined(CONFIG_FSL_PCI_INIT) +#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI) #ifndef CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index d2bebb08b6..999fa8cec4 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -104,4 +104,52 @@ sata-fpdma = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; }; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7c963cdc35..946e74a93b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -61,19 +61,16 @@ /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -95,14 +92,12 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig index a3bd16799d..d2b7edecd6 100644 --- a/arch/x86/cpu/tangier/Kconfig +++ b/arch/x86/cpu/tangier/Kconfig @@ -10,7 +10,6 @@ config INTEL_TANGIER imply MMC_SDHCI imply MMC_SDHCI_SDMA imply MMC_SDHCI_TANGIER - imply TANGIER_WATCHDOG imply USB imply USB_DWC3 diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index e8564bbb8a..c0487656d3 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -104,6 +104,10 @@ reg = <0xff009000 0x1000>; }; + watchdog: wdt@0 { + compatible = "intel,tangier-wdt"; + }; + reset { compatible = "intel,reset-tangier"; u-boot,dm-pre-reloc; diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index ac85278cdf..0481f453ca 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -18,10 +18,7 @@ __weak ulong board_get_usable_ram_top(ulong total_size) int init_cache_f_r(void) { -#if (CONFIG_IS_ENABLED(X86_32BIT_INIT) || \ - (!defined(CONFIG_SPL_BUILD) && \ - !CONFIG_IS_ENABLED(CONFIG_X86_RUN_64BIT))) && \ - !defined(CONFIG_HAVE_FSP) +#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) int ret; ret = mtrr_commit(false); diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c index 9579d52ffd..7a510c61fb 100644 --- a/board/Arcturus/ucp1020/cmd_arc.c +++ b/board/Arcturus/ucp1020/cmd_arc.c @@ -2,8 +2,8 @@ /* * Command for accessing Arcturus factory environment. * - * Copyright 2013-2015 Arcturus Networks Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks Inc. + * https://www.arcturusnetworks.com/products/ * by Oleksandr G Zhadan et al. * */ @@ -12,19 +12,13 @@ #include <div64.h> #include <malloc.h> #include <spi_flash.h> - +#include <mmc.h> +#include <version.h> +#include <environment.h> #include <asm/io.h> -#define MAX_SERIAL_SIZE 15 -#define MAX_HWADDR_SIZE 17 - -#define FIRM_ADDR1 (0x200 - sizeof(smac)) -#define FIRM_ADDR2 (0x400 - sizeof(smac)) -#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) -#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) - -static struct spi_flash *flash; -char smac[4][18]; +static ulong fwenv_addr[MAX_FWENV_ADDR]; +const char mystrerr[] = "ERROR: Failed to save factory info"; static int ishwaddr(char *hwaddr) { @@ -38,156 +32,349 @@ static int ishwaddr(char *hwaddr) return -1; } -static int set_arc_product(int argc, char *const argv[]) +#if (FWENV_TYPE == FWENV_MMC) + +static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */ + +int set_mmc_arc_product(int argc, char *const argv[]) { - int err = 0; - char *mystrerr = "ERROR: Failed to save factory info in spi location"; + struct mmc *mmc; + u32 blk, cnt, n; + int i, err = 1; + void *addr; + const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + + mmc = find_mmc_device(mmc_dev_num); + if (!mmc) { + printf("No SD/MMC/eMMC card found\n"); + return 0; + } + if (mmc_init(mmc)) { + printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", + mmc_dev_num); + return 0; + } + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return CMD_RET_FAILURE; + } - if (argc != 5) - return -1; + /* Save factory defaults */ + addr = (void *)smac; + cnt = 1; /* One 512 bytes block */ + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + blk = fwenv_addr[i] / 512; + n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); + if (n != cnt) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + } + if (err) + return -2; - /* Check serial number */ - if (strlen(argv[1]) != MAX_SERIAL_SIZE) - return -1; + return err; +} - /* Check HWaddrs */ - if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) - return -1; +static int read_mmc_arc_info(void) +{ + struct mmc *mmc; + u32 blk, cnt, n; + int i; + void *addr; + const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + + mmc = find_mmc_device(mmc_dev_num); + if (!mmc) { + printf("No SD/MMC/eMMC card found\n"); + return 0; + } + if (mmc_init(mmc)) { + printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", + mmc_dev_num); + return 0; + } - strcpy(smac[3], argv[1]); - strcpy(smac[2], argv[2]); - strcpy(smac[1], argv[3]); - strcpy(smac[0], argv[4]); + addr = (void *)smac; + cnt = 1; /* One 512 bytes block */ - flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + blk = fwenv_addr[i] / 512; + n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); + flush_cache((ulong) addr, 512); + if (n == cnt) + return (i + 1); + } + return 0; +} +#endif - /* - * Save factory defaults - */ +#if (FWENV_TYPE == FWENV_SPI_FLASH) - if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) { - printf("%s: %s [1]\n", __func__, mystrerr); - err++; - } - if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) { - printf("%s: %s [2]\n", __func__, mystrerr); - err++; - } +static struct spi_flash *flash; +static char smac[4][18]; - if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) { - printf("%s: %s [3]\n", __func__, mystrerr); - err++; - } +int set_spi_arc_product(int argc, char *const argv[]) +{ + int i, err = 1; - if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) { - printf("%s: %s [4]\n", __func__, mystrerr); - err++; + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", + CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); + return -1; } - if (err == 4) { - printf("%s: %s [ALL]\n", __func__, mystrerr); + /* Save factory defaults */ + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + if (spi_flash_write + (flash, fwenv_addr[i], sizeof(smac), smac)) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + if (err) return -2; - } - return 0; + return err; } -int get_arc_info(void) +static int read_spi_arc_info(void) { - int location = 1; - char *myerr = "ERROR: Failed to read all 4 factory info spi locations"; + int i; flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", + CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); + return 0; + } + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + if (!spi_flash_read + (flash, fwenv_addr[i], sizeof(smac), smac)) + return (i + 1); + return 0; +} +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) - if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac), - smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR4, - sizeof(smac), smac)) { - printf("%s: %s\n", __func__, myerr); - return -2; - } - } +static char smac[4][18]; + +int set_nor_arc_product(int argc, char *const argv[]) +{ + int i, err = 1; + + /* Save factory defaults */ + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + ulong fwenv_end = fwenv_addr[i] + 4; + + flash_sect_roundb(&fwenv_end); + flash_sect_protect(0, fwenv_addr[i], fwenv_end); + if (flash_write + ((char *)smac, fwenv_addr[i], sizeof(smac))) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + flash_sect_protect(1, fwenv_addr[i], fwenv_end); } - } - if (smac[3][0] != 0) { - if (location > 1) - printf("Using region %d\n", location); - printf("SERIAL: "); - if (smac[3][0] == 0xFF) { - printf("\t<not found>\n"); - } else { - printf("\t%s\n", smac[3]); - env_set("SERIAL", smac[3]); + if (err) + return -2; + + return err; +} + +static int read_nor_arc_info(void) +{ + int i; + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + memcpy(smac, (void *)fwenv_addr[i], sizeof(smac)); + return (i + 1); } + + return 0; +} +#endif + +int set_arc_product(int argc, char *const argv[]) +{ + if (argc != 5) + return -1; + + /* Check serial number */ + if (strlen(argv[1]) != MAX_SERIAL_SIZE) + return -1; + + /* Check HWaddrs */ + if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) + return -1; + + strcpy(smac[0], argv[1]); + strcpy(smac[1], argv[2]); + strcpy(smac[2], argv[3]); + strcpy(smac[3], argv[4]); + +#if (FWENV_TYPE == FWENV_NOR_FLASH) + return set_nor_arc_product(argc, argv); +#endif +#if (FWENV_TYPE == FWENV_SPI_FLASH) + return set_spi_arc_product(argc, argv); +#endif +#if (FWENV_TYPE == FWENV_MMC) + return set_mmc_arc_product(argc, argv); +#endif + return -2; +} + +static int read_arc_info(void) +{ +#if (FWENV_TYPE == FWENV_NOR_FLASH) + return read_nor_arc_info(); +#endif +#if (FWENV_TYPE == FWENV_SPI_FLASH) + return read_spi_arc_info(); +#endif +#if (FWENV_TYPE == FWENV_MMC) + return read_mmc_arc_info(); +#endif + return 0; +} + +static int do_get_arc_info(void) +{ + int l = read_arc_info(); + char *oldserial = env_get("SERIAL"); + char *oldversion = env_get("VERSION"); + + if (oldversion != NULL) + if (strcmp(oldversion, U_BOOT_VERSION) != 0) + oldversion = NULL; + + if (l == 0) { + printf("%s: failed to read factory info\n", __func__); + return -2; } - if (strcmp(smac[2], "00:00:00:00:00:00") == 0) - return 0; + printf("\rSERIAL: "); + if (smac[0][0] == EMPY_CHAR) { + printf("<not found>\n"); + } else { + printf("%s\n", smac[0]); + env_set("SERIAL", smac[0]); + } - printf("HWADDR0:"); - if (smac[2][0] == 0xFF) { - printf("\t<not found>\n"); + if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { + env_set("ethaddr", NULL); + env_set("eth1addr", NULL); + env_set("eth2addr", NULL); + goto done; + } + + printf("HWADDR0: "); + if (smac[1][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("ethaddr"); - if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { - env_set("ethaddr", smac[2]); - printf("\t%s (factory)\n", smac[2]); + if (ret == NULL) { + env_set("ethaddr", smac[1]); + printf("%s\n", smac[1]); + } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { + env_set("ethaddr", smac[1]); + printf("%s (factory)\n", smac[1]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } - if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { - env_set("eth1addr", smac[2]); - env_set("eth2addr", smac[2]); - return 0; + if (strcmp(smac[2], "00:00:00:00:00:00") == 0) { + env_set("eth1addr", NULL); + env_set("eth2addr", NULL); + goto done; } - printf("HWADDR1:"); - if (smac[1][0] == 0xFF) { - printf("\t<not found>\n"); + printf("HWADDR1: "); + if (smac[2][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("eth1addr"); - if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { - env_set("eth1addr", smac[1]); - printf("\t%s (factory)\n", smac[1]); + if (ret == NULL) { + env_set("ethaddr", smac[2]); + printf("%s\n", smac[2]); + } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { + env_set("eth1addr", smac[2]); + printf("%s (factory)\n", smac[2]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } - if (strcmp(smac[0], "00:00:00:00:00:00") == 0) { - env_set("eth2addr", smac[1]); - return 0; + if (strcmp(smac[3], "00:00:00:00:00:00") == 0) { + env_set("eth2addr", NULL); + goto done; } - printf("HWADDR2:"); - if (smac[0][0] == 0xFF) { - printf("\t<not found>\n"); + printf("HWADDR2: "); + if (smac[3][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("eth2addr"); - if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { - env_set("eth2addr", smac[0]); - printf("\t%s (factory)\n", smac[0]); + if (ret == NULL) { + env_set("ethaddr", smac[3]); + printf("%s\n", smac[3]); + } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { + env_set("eth2addr", smac[3]); + printf("%s (factory)\n", smac[3]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } +done: + if (oldserial == NULL || oldversion == NULL) { + if (oldversion == NULL) + env_set("VERSION", U_BOOT_VERSION); + env_save(); + } return 0; } -static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +static int init_fwenv(void) +{ + int i, ret = -1; + + fwenv_addr[0] = FWENV_ADDR1; + fwenv_addr[1] = FWENV_ADDR2; + fwenv_addr[2] = FWENV_ADDR3; + fwenv_addr[3] = FWENV_ADDR4; + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + ret = 0; + if (ret) + printf("%s: No firmfare info storage address is defined\n", + __func__); + return ret; +} + +void get_arc_info(void) +{ + if (!init_fwenv()) + do_get_arc_info(); +} + +static int do_arc_cmd(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]) { const char *cmd; int ret = -1; @@ -196,15 +383,14 @@ static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) --argc; ++argv; - if (strcmp(cmd, "product") == 0) { + if (init_fwenv()) + return ret; + + if (strcmp(cmd, "product") == 0) ret = set_arc_product(argc, argv); - goto done; - } - if (strcmp(cmd, "info") == 0) { - ret = get_arc_info(); - goto done; - } -done: + else if (strcmp(cmd, "info") == 0) + ret = do_get_arc_info(); + if (ret == -1) return CMD_RET_USAGE; diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c index 1a1fcb9be9..54fd1782cb 100644 --- a/board/Arcturus/ucp1020/ucp1020.c +++ b/board/Arcturus/ucp1020/ucp1020.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * by Oleksandr G Zhadan et al. * based on board/freescale/p1_p2_rdb_pc/spl.c * original copyright follows: @@ -108,7 +108,9 @@ int checkboard(void) { printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL); board_gpio_init(); +#ifdef CONFIG_MMC printf("SD/MMC: 4-bit Mode\n"); +#endif return 0; } @@ -193,7 +195,9 @@ int last_stage_init(void) static char newkernelargs[256]; static u8 id1[16]; static u8 id2; +#ifdef CONFIG_MMC struct mmc *mmc; +#endif char *sval, *kval; if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) { @@ -215,6 +219,7 @@ int last_stage_init(void) kval = env_get("kernelargs"); +#ifdef CONFIG_MMC mmc = find_mmc_device(0); if (mmc) if (!mmc_init(mmc)) { @@ -234,6 +239,7 @@ int last_stage_init(void) env_set("kernelargs", mmckargs); } } +#endif get_arc_info(); if (kval) { diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h index cf1ddd718b..1b527cdb1c 100644 --- a/board/Arcturus/ucp1020/ucp1020.h +++ b/board/Arcturus/ucp1020/ucp1020.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * by Oleksandr G Zhadan et al. */ @@ -35,8 +35,10 @@ #define GPIO_WD GPIO15 +#ifdef CONFIG_MMC static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro"; static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw"; +#endif int get_arc_info(void); diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 0608a5a88b..21156a4ca9 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) ARM Ltd 2015 * * Author: Liviu Dudau <Liviu.Dudau@arm.com> - * - * SPDX-Licence-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/bosch/guardian/MAINTAINERS b/board/bosch/guardian/MAINTAINERS index 8d16ec0202..2f674d7f83 100644 --- a/board/bosch/guardian/MAINTAINERS +++ b/board/bosch/guardian/MAINTAINERS @@ -1,5 +1,7 @@ Guardian BOARD M: Sjoerd Simons <sjoerd.simons@collabora.co.uk> +M: Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com> +M: Moses Christopher Bollavarapu <BollavarapuMoses.Christopher@in.bosch.com> S: Maintained F: board/bosch/guardian/ F: include/configs/am335x_guardian.h diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 97376c4165..dddfd26a13 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -79,7 +79,7 @@ int fsl_setenv_chain_of_trust(void) * bootdelay = 0 (To disable Boot Prompt) * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) */ - env_set("bootdelay", "0"); + env_set("bootdelay", "-2"); #ifdef CONFIG_ARM env_set("secureboot", "y"); diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS index 6f1a95ea3b..2c28825698 100644 --- a/board/freescale/ls1028a/MAINTAINERS +++ b/board/freescale/ls1028a/MAINTAINERS @@ -19,3 +19,13 @@ F: board/freescale/ls1028a/ F: include/configs/ls1028a_common.h F: include/configs/ls1028ardb.h F: configs/ls1028ardb_tfa_defconfig + +LS1028AQDS_SECURE_BOOT BOARD +M: Tang Yuantian <andy.tang@nxp.com> +S: Maintained +F: configs/ls1028aqds_tfa_SECURE_BOOT_defconfig + +LS1028ARDB_SECURE_BOOT BOARD +M: Tang Yuantian <andy.tang@nxp.com> +S: Maintained +F: configs/ls1028ardb_tfa_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 8763913e31..e1919d2988 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #include <common.h> @@ -161,16 +162,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { if (port == FM1_DTSEC9) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s1_p1"); + "sgmii-riser-s1-p1"); } else if (port == FM1_DTSEC2) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s2_p1"); + "sgmii-riser-s2-p1"); } else if (port == FM1_DTSEC5) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s3_p1"); + "sgmii-riser-s3-p1"); } else if (port == FM1_DTSEC6) { fdt_set_phy_handle(fdt, compat, addr, - "sgmii_riser_s4_p1"); + "sgmii-riser-s4-p1"); } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { @@ -191,19 +192,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p1"); + "qsgmii-s1-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p2"); + "qsgmii-s1-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p3"); + "qsgmii-s1-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s1_p4"); + "qsgmii-s1-p4"); break; default: break; @@ -213,19 +214,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, switch (port) { case FM1_DTSEC1: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p1"); + "qsgmii-s2-p1"); break; case FM1_DTSEC2: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p2"); + "qsgmii-s2-p2"); break; case FM1_DTSEC5: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p3"); + "qsgmii-s2-p3"); break; case FM1_DTSEC6: fdt_set_phy_handle(fdt, compat, addr, - "qsgmii_s2_p4"); + "qsgmii-s2-p4"); break; default: break; @@ -268,16 +269,16 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); + fdt_status_okay_by_alias(fdt, "emi1-slot3"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; diff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig new file mode 100644 index 0000000000..6a4c3e92f7 --- /dev/null +++ b/board/freescale/ls1046afrwy/Kconfig @@ -0,0 +1,17 @@ + +if TARGET_LS1046AFRWY + +config SYS_BOARD + default "ls1046afrwy" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1046afrwy" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS new file mode 100644 index 0000000000..357d23e70d --- /dev/null +++ b/board/freescale/ls1046afrwy/MAINTAINERS @@ -0,0 +1,7 @@ +LS1046AFRWY BOARD +M: Pramod Kumar <pramod.kumar_1@nxp.com> +S: Maintained +F: board/freescale/ls1046afrwy/ +F: board/freescale/ls1046afrwy/ls1046afrwy.c +F: include/configs/ls1046afrwy.h +F: configs/ls1046afrwy_tfa_defconfig diff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile new file mode 100644 index 0000000000..c70f5cda79 --- /dev/null +++ b/board/freescale/ls1046afrwy/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 NXP + +obj-y += ddr.o +obj-y += ls1046afrwy.o +obj-$(CONFIG_NET) += eth.o diff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README new file mode 100644 index 0000000000..d7b5a7794f --- /dev/null +++ b/board/freescale/ls1046afrwy/README @@ -0,0 +1,76 @@ +Overview +-------- +The LS1046A Freeway Board (iFRWY) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LS1046A +LayerScape Architecture processor. The FRWY-LS1046A provides SW development +platform for the Freescale LS1046A processor series, with a complete +debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant. + +LS1046A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A +SoC overview. + + FRWY-LS1046A board Overview + ----------------------- + - SERDES1 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: Unused + - Lane2: QSGMII + - Lane3: Unused + - SERDES2 Connections, 4 lanes supporting: + - Lane0: Unused + - Lane1: PCIe3 with PCIe x1 slot + - Lane2: Unused + - Lane3: PCIe3 with PCIe x1 slot + - DDR Controller + - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s + -IFC/Local Bus + - One 512 MB NAND flash with ECC support + - USB 3.0 + - Two Type A port + - SDHC: connects directly to a full microSD slot + - QSPI: 64 MB high-speed flash Memory for boot code and storage + - 4 I2C controllers + - UART + - Two 4-pin serial ports at up to 115.2 Kbit/s + - Two DB9 D-Type connectors supporting one Serial port each + - ARM JTAG support + +Memory map from core's view +---------------------------- +Start Address End Address Description Size +0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB +0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB +0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB +0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M +0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M +0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB +0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G +0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G +0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G + +QSPI flash map: +Start Address End Address Description Size +0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB +0x00_4010_0000 - 0x00_404F_FFFF FIP Image + (Bl31 + BL32(optee. + bin) + Bl33(uboot) + + headers for secure + boot) 4MB +0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB +0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB +0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB +0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB +0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB +0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB + +Booting Options +--------------- +a) QSPI boot +b) microSD boot diff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c new file mode 100644 index 0000000000..daf17e0169 --- /dev/null +++ b/board/freescale/ls1046afrwy/ddr.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c new file mode 100644 index 0000000000..9f8bd92850 --- /dev/null +++ b/board/freescale/ls1046afrwy/eth.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <fm_eth.h> +#include <fsl_dtsec.h> +#include <fsl_mdio.h> +#include <malloc.h> + +#include "../common/fman.h" + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info dtsec_mdio_info; + struct mii_dev *dev; + u32 srds_s1; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + /* QSGMII on lane B, MAC 6/5/10/1 */ + fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); + + switch (srds_s1) { + case 0x3040: + break; + default: + printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", + srds_s1); + break; + } + + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(FM1_DTSEC6, dev); + fm_info_set_mdio(FM1_DTSEC5, dev); + fm_info_set_mdio(FM1_DTSEC10, dev); + fm_info_set_mdio(FM1_DTSEC1, dev); + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#ifdef CONFIG_FMAN_ENET +int fdt_update_ethernet_dt(void *blob) +{ + u32 srds_s1; + int i, prop; + int offset, nodeoff; + const char *path; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + /* Cycle through all aliases */ + for (prop = 0; ; prop++) { + const char *name; + + /* FDT might have been edited, recompute the offset */ + offset = fdt_first_property_offset(blob, + fdt_path_offset(blob, + "/aliases") + ); + /* Select property number 'prop' */ + for (i = 0; i < prop; i++) + offset = fdt_next_property_offset(blob, offset); + + if (offset < 0) + break; + + path = fdt_getprop_by_offset(blob, offset, &name, NULL); + nodeoff = fdt_path_offset(blob, path); + + switch (srds_s1) { + case 0x3040: + if (!strcmp(name, "ethernet1")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet2")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet3")) + fdt_status_disabled(blob, nodeoff); + if (!strcmp(name, "ethernet6")) + fdt_status_disabled(blob, nodeoff); + break; + default: + printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n", + __func__, srds_s1); + break; + } + } + + return 0; +} +#endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c new file mode 100644 index 0000000000..41412a76b6 --- /dev/null +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_sec.h> +#include <fsl_dspi.h> + +#define LS1046A_PORSR1_REG 0x1EE0000 +#define BOOT_SRC_SD 0x20000000 +#define BOOT_SRC_MASK 0xFF800000 +#define BOARD_REV_GPIO 13 +#define USB2_SEL_MASK 0x00000100 + +#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ +(((word) & 0x00ff0000) >> 8) | \ +(((word) & 0x0000ff00) << 8) | \ +(((word) & 0x000000ff) << 24)) +#define SPI_MCR_REG 0x2100000 + +DECLARE_GLOBAL_DATA_PTR; + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static inline void demux_select_usb2(void) +{ + u32 val; + struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR); + + val = in_be32(&pgpio->gpdir); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdir, val); + + val = in_be32(&pgpio->gpdat); + val |= USB2_SEL_MASK; + out_be32(&pgpio->gpdat, val); +} + +static inline void set_spi_cs_signal_inactive(void) +{ + /* default: all CS signals inactive state is high */ + uint mcr_val; + uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | + DSPI_MCR_CRXF | DSPI_MCR_CTXF; + + mcr_val = in_be32(SPI_MCR_REG); + mcr_val |= DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); + out_be32(SPI_MCR_REG, mcr_cfg_val); + mcr_val = in_be32(SPI_MCR_REG); + mcr_val &= ~DSPI_MCR_HALT; + out_be32(SPI_MCR_REG, mcr_val); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +static inline uint8_t get_board_version(void) +{ + u8 val; + struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); + + val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03; + + return val; +} + +int checkboard(void) +{ + static const char *freq[2] = {"100.00MHZ", "100.00MHZ"}; + u32 boot_src; + u8 rev; + + rev = get_board_version(); + switch (rev) { + case 0x00: + puts("Board: LS1046AFRWY, Rev: A, boot from "); + break; + case 0x01: + puts("Board: LS1046AFRWY, Rev: B, boot from "); + break; + default: + puts("Board: LS1046AFRWY, Rev: Unknown, boot from "); + break; + } + boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG)); + + if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD) + puts("SD\n"); + else + puts("QSPI\n"); + printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SECURE_BOOT + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; +val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + return 0; +} + +int board_setup_core_volt(u32 vdd) +{ + return 0; +} + +void config_board_mux(void) +{ +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + /* + * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT + * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + */ + out_be32(&scfg->rcwpmuxcr0, 0x3300); +#ifdef CONFIG_HAS_FSL_IIC3 + /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */ + out_be32(&scfg->rcwpmuxcr0, 0x0000); +#endif + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#ifndef CONFIG_HAS_FSL_IIC3 + /* + * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input + * to select I2C3_USB2_SEL_IO + * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to + * I2C3 header (default) + * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to + * USB2 port + * programmed to select USB2 by setting GPIO3_23 output to one + */ + demux_select_usb2(); +#endif +#endif + set_spi_cs_signal_inactive(); +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + config_board_mux(); + return 0; +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + /* fixup DT for the two DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif + + fdt_fixup_icid(blob); + + return 0; +} diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index abe8ee95d4..1eb40677b5 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #include <common.h> @@ -161,19 +161,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { switch (port) { case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); break; case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1"); + fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); break; default: break; @@ -193,16 +193,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); break; case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); break; case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); break; case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); + fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); break; default: break; @@ -246,13 +246,13 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); + fdt_status_okay_by_alias(fdt, "emi1-slot1"); break; case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); + fdt_status_okay_by_alias(fdt, "emi1-slot2"); break; case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); + fdt_status_okay_by_alias(fdt, "emi1-slot4"); break; default: break; diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 6109b280c6..3b4cb86692 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -509,7 +509,8 @@ void fdt_fixup_board_enet(void *fdt) return; } - if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) { + if (get_mc_boot_status() == 0 && + (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); fdt_fixup_board_phy(fdt); } else { diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c index c761aea0ac..ef26f14c46 100644 --- a/board/freescale/t208xqds/pci.c +++ b/board/freescale/t208xqds/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c index 480933b3cc..da33a0bd8a 100644 --- a/board/renesas/sh7752evb/sh7752evb.c +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -174,6 +174,7 @@ int board_mmc_init(bd_t *bis) static int get_sh_eth_mac_raw(unsigned char *buf, int size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; @@ -190,6 +191,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size) return 1; } spi_flash_free(spi); +#endif return 0; } @@ -239,6 +241,7 @@ int board_late_init(void) return 0; } +#ifdef CONFIG_DEPRECATED int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret; @@ -302,3 +305,4 @@ U_BOOT_CMD( "write MAC address for GETHERC", "[GETHERC ch0] [GETHERC ch1]\n" ); +#endif diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c index dfdc6b79b7..5ddddb6571 100644 --- a/board/renesas/sh7753evb/sh7753evb.c +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -190,6 +190,7 @@ int board_mmc_init(bd_t *bis) static int get_sh_eth_mac_raw(unsigned char *buf, int size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; @@ -206,6 +207,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size) return 1; } spi_flash_free(spi); +#endif return 0; } @@ -255,6 +257,7 @@ int board_late_init(void) return 0; } +#ifdef CONFIG_DEPRECATED int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret; @@ -318,3 +321,4 @@ U_BOOT_CMD( "write MAC address for GETHERC", "[GETHERC ch0] [GETHERC ch1]\n" ); +#endif diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c index 90c5508e43..3222701ad2 100644 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ b/board/renesas/sh7757lcr/sh7757lcr.c @@ -30,6 +30,7 @@ static void init_gctrl(void) static int init_pcie_bridge_from_spi(void *buf, size_t size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; unsigned long pcie_addr; @@ -54,6 +55,10 @@ static int init_pcie_bridge_from_spi(void *buf, size_t size) spi_flash_free(spi); return 0; +#else + printf("No SPI support so no PCIe support\n"); + return 1; +#endif } static void init_pcie_bridge(void) @@ -231,6 +236,7 @@ int board_mmc_init(bd_t *bis) static int get_sh_eth_mac_raw(unsigned char *buf, int size) { +#ifdef CONFIG_DEPRECATED struct spi_flash *spi; int ret; @@ -247,6 +253,7 @@ static int get_sh_eth_mac_raw(unsigned char *buf, int size) return 1; } spi_flash_free(spi); +#endif return 0; } @@ -352,6 +359,7 @@ U_BOOT_CMD( "enable SH-G200 bus (disable PCIe-G200)" ); +#ifdef CONFIG_DEPRECATED int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret; @@ -418,3 +426,4 @@ U_BOOT_CMD( "write MAC address for ETHERC/GETHERC", "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" ); +#endif diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 2ee6e462a6..c661d2e06a 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,3 +4,9 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig + +ROCK64-RK3328 +M: Matwey V. Kornilov <matwey.kornilov@gmail.com> +S: Maintained +F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64-u-boot.dtsi diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index bf2ad98c47..eb1b832274 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -6,46 +6,14 @@ #include <common.h> #include <dm.h> #include <dm/pinctrl.h> -#include <dm/uclass-internal.h> #include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { - struct udevice *pinctrl, *regulator; + struct udevice *regulator; int ret; - /* - * The PWM do not have decicated interrupt number in dts and can - * not get periph_id by pinctrl framework, so let's init them here. - * The PWM2 and PWM3 are for pwm regulater. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto out; - } - - /* Enable pwm0 for panel backlight */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0); - if (ret) { - debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); - if (ret) { - debug("%s PWM2 pinctrl init fail!\n", __func__); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3); - if (ret) { - debug("%s PWM3 pinctrl init fail!\n", __func__); - goto out; - } - ret = regulators_enable_boot_on(false); if (ret) debug("%s: Cannot enable boot on regulator\n", __func__); @@ -65,30 +33,3 @@ int board_init(void) out: return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index f67dfb451f..9b31b0b379 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -60,7 +60,7 @@ Creating a SPL image for SD-Card/eMMC Creating a SPL image for SPI-NOR > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree - > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb + > make CROSS_COMPILE=aarch64-linux-gnu- Flash the image =============== diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its deleted file mode 100644 index 530f059f3d..0000000000 --- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ -/* - * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH - * - * Minimal dts for a SPL FIT image payload. - */ - -/dts-v1/; - -/ { - description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; - #address-cells = <1>; - - images { - uboot { - description = "U-Boot (64-bit)"; - data = /incbin/("../../../u-boot-nodtb.bin"); - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <0x00200000>; - }; - atf { - description = "ARM Trusted Firmware"; - data = /incbin/("../../../bl31-rk3399.bin"); - type = "firmware"; - arch = "arm64"; - os = "arm-trusted-firmware"; - compression = "none"; - load = <0x1000>; - entry = <0x1000>; - }; - pmu { - description = "Cortex-M0 firmware"; - data = /incbin/("../../../rk3399m0.bin"); - type = "pmu-firmware"; - compression = "none"; - load = <0x180000>; - }; - fdt { - description = "RK3399-Q7 (Puma) flat device-tree"; - data = /incbin/("../../../u-boot.dtb"); - type = "flat_dt"; - compression = "none"; - }; - }; - - configurations { - default = "conf"; - conf { - description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; - firmware = "atf"; - loadables = "uboot", "pmu"; - fdt = "fdt"; - }; - }; -}; diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh new file mode 100755 index 0000000000..420e7daf4c --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh @@ -0,0 +1,94 @@ +#!/bin/sh +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> +# +# Based on the board/sunxi/mksunxi_fit_atf.sh +# +# Script to generate FIT image source for 64-bit puma boards with +# U-Boot proper, ATF, PMU firmware and devicetree. +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +[ -z "$BL31" ] && BL31="bl31.bin" + +if [ ! -f $BL31 ]; then + echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + BL31=/dev/null +fi + +[ -z "$PMUM0" ] && PMUM0="rk3399m0.bin" + +if [ ! -f $PMUM0 ]; then + echo "WARNING: PMUM0 file $PMUM0 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + PMUM0=/dev/null +fi + +cat << __HEADER_EOF +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * Minimal dts for a SPL FIT image payload. + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x4a000000>; + }; + atf { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <0x1000>; + entry = <0x1000>; + }; + pmu { + description = "Cortex-M0 firmware"; + data = /incbin/("$PMUM0"); + type = "pmu-firmware"; + compression = "none"; + load = <0x180000>; + }; + fdt { + description = "RK3399-Q7 (Puma) flat device-tree"; + data = /incbin/("u-boot.dtb"); + type = "flat_dt"; + compression = "none"; + }; +__HEADER_EOF + +cat << __CONF_HEADER_EOF + }; + + configurations { + default = "conf"; + conf { + description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; + firmware = "atf"; + loadables = "uboot", "pmu"; + fdt = "fdt"; + }; +__CONF_HEADER_EOF + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index c6b509c109..251cd2d566 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -13,10 +13,8 @@ #include <dm/pinctrl.h> #include <dm/uclass-internal.h> #include <asm/io.h> -#include <asm/gpio.h> #include <asm/setup.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/periph.h> @@ -38,62 +36,6 @@ int board_init(void) return 0; } -static void rk3399_force_power_on_reset(void) -{ - ofnode node; - struct gpio_desc sysreset_gpio; - - debug("%s: trying to force a power-on reset\n", __func__); - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - debug("%s: no /config node?\n", __func__); - return; - } - - if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, - &sysreset_gpio, GPIOD_IS_OUT)) { - debug("%s: could not find a /config/sysreset-gpio\n", __func__); - return; - } - - dm_gpio_set_value(&sysreset_gpio, 1); -} - -void spl_board_init(void) -{ - int ret; - struct rk3399_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the TRM - * "3.9.4 Global software reset"), when issuing a software reset. - * This may cause issues during boot-up for some configurations of - * the application software stack. - * - * To work around this, we test whether the last reset reason was - * a power-on reset and (if not) issue an overtemp-reset to reset - * the entire module. - * - * While this was previously fixed by modifying the various places - * that could generate a software reset (e.g. U-Boot's sysreset - * driver, the ATF or Linux), we now have it here to ensure that - * we no longer have to track this through the various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); - - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - preloader_console_init(); -} - static void setup_macaddr(void) { #if CONFIG_IS_ENABLED(CMD_NET) diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README index d14399090e..c5c675c4ea 100644 --- a/board/vamrs/rock960_rk3399/README +++ b/board/vamrs/rock960_rk3399/README @@ -61,7 +61,6 @@ Compile the U-Boot > export CROSS_COMPILE=aarch64-linux-gnu- > make rock960-rk3399_defconfig > make - > make u-boot.itb Compile the rkdeveloptool ========================= diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 0f5ef3a09a..2eb7120e84 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -5,11 +5,7 @@ #include <common.h> #include <dm.h> -#include <dm/pinctrl.h> -#include <dm/uclass-internal.h> -#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { @@ -21,30 +17,3 @@ int board_init(void) return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile index e3803bb043..b837e7b0dd 100644 --- a/board/work-microwave/work_92105/Makefile +++ b/board/work-microwave/work_92105/Makefile @@ -6,5 +6,6 @@ ifdef CONFIG_SPL_BUILD obj-y += work_92105_spl.o else -obj-y += work_92105.o work_92105_display.o +obj-y += work_92105.o +obj-$(CONFIG_DEPRECATED) += work_92105_display.o endif diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index eb2e7d7eb8..3f23af9ed4 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -52,8 +52,10 @@ int board_early_init_r(void) gpio_request(GPO_19, "NAND_nWP"); gpio_direction_output(GPO_19, 1); +#ifdef CONFIG_DEPRECATED /* initialize display */ work_92105_display_init(); +#endif return 0; } diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index e6fed25152..efc1d356d6 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -2,6 +2,7 @@ XILINX_ZYNQMP BOARDS M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: arch/arm/dts/zynqmp-* +F: arch/arm/dts/avnet-ultra96* F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig deleted file mode 100644 index c6635040a3..0000000000 --- a/board/zipitz2/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_ZIPITZ2 - -config SYS_BOARD - default "zipitz2" - -config SYS_CONFIG_NAME - default "zipitz2" - -endif diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS deleted file mode 100644 index e027cd361a..0000000000 --- a/board/zipitz2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ZIPITZ2 BOARD -M: Vasily Khoruzhick <anarsoul@gmail.com> -S: Maintained -F: board/zipitz2/ -F: include/configs/zipitz2.h -F: configs/zipitz2_defconfig diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile deleted file mode 100644 index 2bbe4364e8..0000000000 --- a/board/zipitz2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2009 -# Marek Vasut <marek.vasut@gmail.com> -# -# Heavily based on pxa255_idp platform - -obj-y := zipitz2.o diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c deleted file mode 100644 index 9208c882c2..0000000000 --- a/board/zipitz2/zipitz2.c +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009 - * Marek Vasut <marek.vasut@gmail.com> - * - * Heavily based on pxa255_idp platform - */ - -#include <common.h> -#include <command.h> -#include <serial.h> -#include <asm/arch/hardware.h> -#include <asm/arch/pxa.h> -#include <asm/arch/regs-mmc.h> -#include <spi.h> -#include <asm/io.h> -#include <usb.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CMD_SPI -void lcd_start(void); -#else -inline void lcd_start(void) {}; -#endif - -/* - * Miscelaneous platform dependent initialisations - */ -int board_init(void) -{ - /* arch number of Z2 */ - gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Enable LCD */ - lcd_start(); - - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -#ifdef CONFIG_CMD_USB -int board_usb_init(int index, enum usb_init_type init) -{ - /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} - -void usb_board_stop(void) -{ -} -#endif - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -#ifdef CONFIG_CMD_SPI - -struct { - unsigned char reg; - unsigned short data; - unsigned char mdelay; -} lcd_data[] = { - { 0x07, 0x0000, 0 }, - { 0x13, 0x0000, 10 }, - { 0x11, 0x3004, 0 }, - { 0x14, 0x200F, 0 }, - { 0x10, 0x1a20, 0 }, - { 0x13, 0x0040, 50 }, - { 0x13, 0x0060, 0 }, - { 0x13, 0x0070, 200 }, - { 0x01, 0x0127, 0 }, - { 0x02, 0x0700, 0 }, - { 0x03, 0x1030, 0 }, - { 0x08, 0x0208, 0 }, - { 0x0B, 0x0620, 0 }, - { 0x0C, 0x0110, 0 }, - { 0x30, 0x0120, 0 }, - { 0x31, 0x0127, 0 }, - { 0x32, 0x0000, 0 }, - { 0x33, 0x0503, 0 }, - { 0x34, 0x0727, 0 }, - { 0x35, 0x0124, 0 }, - { 0x36, 0x0706, 0 }, - { 0x37, 0x0701, 0 }, - { 0x38, 0x0F00, 0 }, - { 0x39, 0x0F00, 0 }, - { 0x40, 0x0000, 0 }, - { 0x41, 0x0000, 0 }, - { 0x42, 0x013f, 0 }, - { 0x43, 0x0000, 0 }, - { 0x44, 0x013f, 0 }, - { 0x45, 0x0000, 0 }, - { 0x46, 0xef00, 0 }, - { 0x47, 0x013f, 0 }, - { 0x48, 0x0000, 0 }, - { 0x07, 0x0015, 30 }, - { 0x07, 0x0017, 0 }, - { 0x20, 0x0000, 0 }, - { 0x21, 0x0000, 0 }, - { 0x22, 0x0000, 0 }, -}; - -void zipitz2_spi_sda(int set) -{ - /* GPIO 13 */ - if (set) - writel((1 << 13), GPSR0); - else - writel((1 << 13), GPCR0); -} - -void zipitz2_spi_scl(int set) -{ - /* GPIO 22 */ - if (set) - writel((1 << 22), GPCR0); - else - writel((1 << 22), GPSR0); -} - -unsigned char zipitz2_spi_read(void) -{ - /* GPIO 40 */ - return !!(readl(GPLR1) & (1 << 8)); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* Always valid */ - return 1; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* GPIO 88 low */ - writel((1 << 24), GPCR2); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* GPIO 88 high */ - writel((1 << 24), GPSR2); -} - -void lcd_start(void) -{ - int i; - unsigned char reg[3] = { 0x74, 0x00, 0 }; - unsigned char data[3] = { 0x76, 0, 0 }; - unsigned char dummy[3] = { 0, 0, 0 }; - - /* PWM2 AF */ - writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); - /* Enable clock to all PWM */ - writel(readl(CKEN) | 0x3, CKEN); - /* Configure PWM2 */ - writel(0x4f, PWM_CTRL2); - writel(0x2ff, PWM_PWDUTY2); - writel(792, PWM_PERVAL2); - - /* Toggle the reset pin to reset the LCD */ - writel((1 << 19), GPSR0); - udelay(100000); - writel((1 << 19), GPCR0); - udelay(20000); - writel((1 << 19), GPSR0); - udelay(20000); - - /* Program the LCD init sequence */ - for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { - reg[0] = 0x74; - reg[1] = 0x0; - reg[2] = lcd_data[i].reg; - spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); - - data[0] = 0x76; - data[1] = lcd_data[i].data >> 8; - data[2] = lcd_data[i].data & 0xff; - spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); - - if (lcd_data[i].mdelay) - udelay(lcd_data[i].mdelay * 1000); - } - - writel((1 << 11), GPSR0); -} -#endif diff --git a/cmd/Kconfig b/cmd/Kconfig index 0badcb3fe0..cda7931fe3 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1035,11 +1035,13 @@ config CMD_SDRAM config CMD_SF bool "sf" + depends on DM_SPI_FLASH || SPI_FLASH help SPI Flash support config CMD_SF_TEST bool "sf test - Allow testing of SPI flash" + depends on CMD_SF help Provides a way to test that SPI flash is working correctly. The test is destructive, in that an area of SPI flash must be provided @@ -1051,6 +1053,7 @@ config CMD_SF_TEST config CMD_SPI bool "sspi - Command to access spi device" + depends on SPI help SPI utility command. diff --git a/cmd/efidebug.c b/cmd/efidebug.c index e657226254..cb152b3339 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -505,7 +505,8 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, struct efi_load_option lo; void *data = NULL; efi_uintn_t size; - int ret; + efi_status_t ret; + int r = CMD_RET_SUCCESS; if (argc < 6 || argc > 7) return CMD_RET_USAGE; @@ -538,7 +539,7 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, if (ret != EFI_SUCCESS) { printf("Cannot create device path for \"%s %s\"\n", argv[3], argv[4]); - ret = CMD_RET_FAILURE; + r = CMD_RET_FAILURE; goto out; } lo.file_path = file_path; @@ -553,7 +554,7 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, size = efi_serialize_load_option(&lo, (u8 **)&data); if (!size) { - ret = CMD_RET_FAILURE; + r = CMD_RET_FAILURE; goto out; } @@ -562,14 +563,17 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, size, data)); - ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE); + if (ret != EFI_SUCCESS) { + printf("Cannot set %ls\n", var_name16); + r = CMD_RET_FAILURE; + } out: free(data); efi_free_pool(device_path); efi_free_pool(file_path); free(lo.label); - return ret; + return r; } /** @@ -609,7 +613,7 @@ static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag, ret = EFI_CALL(RT->set_variable(var_name16, &guid, 0, 0, NULL)); if (ret) { - printf("cannot remove Boot%04X", id); + printf("Cannot remove Boot%04X", id); return CMD_RET_FAILURE; } } @@ -896,6 +900,7 @@ static int do_efi_boot_next(cmd_tbl_t *cmdtp, int flag, char *endp; efi_guid_t guid; efi_status_t ret; + int r = CMD_RET_SUCCESS; if (argc != 2) return CMD_RET_USAGE; @@ -903,7 +908,7 @@ static int do_efi_boot_next(cmd_tbl_t *cmdtp, int flag, bootnext = (u16)simple_strtoul(argv[1], &endp, 16); if (*endp != '\0' || bootnext > 0xffff) { printf("invalid value: %s\n", argv[1]); - ret = CMD_RET_FAILURE; + r = CMD_RET_FAILURE; goto out; } @@ -914,9 +919,12 @@ static int do_efi_boot_next(cmd_tbl_t *cmdtp, int flag, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, size, &bootnext)); - ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE); + if (ret != EFI_SUCCESS) { + printf("Cannot set BootNext\n"); + r = CMD_RET_FAILURE; + } out: - return ret; + return r; } /** @@ -941,6 +949,7 @@ static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag, char *endp; efi_guid_t guid; efi_status_t ret; + int r = CMD_RET_SUCCESS; if (argc == 1) return show_efi_boot_order(); @@ -957,7 +966,7 @@ static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag, id = (int)simple_strtoul(argv[i], &endp, 16); if (*endp != '\0' || id > 0xffff) { printf("invalid value: %s\n", argv[i]); - ret = CMD_RET_FAILURE; + r = CMD_RET_FAILURE; goto out; } @@ -970,11 +979,14 @@ static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, size, bootorder)); - ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE); + if (ret != EFI_SUCCESS) { + printf("Cannot set BootOrder\n"); + r = CMD_RET_FAILURE; + } out: free(bootorder); - return ret; + return r; } static cmd_tbl_t cmd_efidebug_boot_sub[] = { @@ -8,7 +8,6 @@ #include <common.h> #include <command.h> #include <fs.h> -#include <efi_loader.h> static int do_size_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -26,10 +25,6 @@ U_BOOT_CMD( static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { -#ifdef CONFIG_CMD_BOOTEFI - efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "", - (argc > 4) ? argv[4] : ""); -#endif return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY); } @@ -137,6 +137,6 @@ U_BOOT_CMD( led, 4, 1, do_led, "manage LEDs", "<led_label> on|off|toggle" BLINK "\tChange LED state\n" - "led [<led_label>]\tGet LED state\n" + "led <led_label>\tGet LED state\n" "led list\t\tshow a list of LEDs" ); diff --git a/cmd/usb_gadget_sdp.c b/cmd/usb_gadget_sdp.c index 808ed974fa..2ead06be9f 100644 --- a/cmd/usb_gadget_sdp.c +++ b/cmd/usb_gadget_sdp.c @@ -13,7 +13,7 @@ static int do_sdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int ret = CMD_RET_FAILURE; + int ret; if (argc < 2) return CMD_RET_USAGE; @@ -23,7 +23,11 @@ static int do_sdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) usb_gadget_initialize(controller_index); g_dnl_clear_detach(); - g_dnl_register("usb_dnl_sdp"); + ret = g_dnl_register("usb_dnl_sdp"); + if (ret) { + pr_err("SDP dnl register failed: %d\n", ret); + goto exit_register; + } ret = sdp_init(controller_index); if (ret) { @@ -37,9 +41,10 @@ static int do_sdp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) exit: g_dnl_unregister(); +exit_register: usb_gadget_release(controller_index); - return ret; + return CMD_RET_FAILURE; } U_BOOT_CMD(sdp, 2, 1, do_sdp, diff --git a/common/image-sig.c b/common/image-sig.c index 4f6b4ec412..004fbc525b 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -211,7 +211,7 @@ static int fit_image_setup_verify(struct image_sign_info *info, info->required_keynode = required_keynode; printf("%s:%s", algo_name, info->keyname); - if (!info->checksum || !info->crypto) { + if (!info->checksum || !info->crypto || !info->padding) { *err_msgp = "Unknown signature algorithm"; return -1; } diff --git a/common/spl/spl_dfu.c b/common/spl/spl_dfu.c index 01178f611f..c0225dc4e1 100644 --- a/common/spl/spl_dfu.c +++ b/common/spl/spl_dfu.c @@ -41,7 +41,7 @@ int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr) set_default_env(NULL, 0); str_env = env_get(dfu_alt_info); if (!str_env) { - pr_err("\"dfu_alt_info\" env variable not defined!\n"); + pr_err("\"%s\" env variable not defined!\n", dfu_alt_info); return -EINVAL; } diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index 51b245b886..806bf1327e 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -17,7 +17,11 @@ static int spl_sdp_load_image(struct spl_image_info *spl_image, const int controller_index = 0; g_dnl_clear_detach(); - g_dnl_register("usb_dnl_sdp"); + ret = g_dnl_register("usb_dnl_sdp"); + if (ret) { + pr_err("SDP dnl register failed: %d\n", ret); + return ret; + } ret = sdp_init(controller_index); if (ret) { diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 9c2182e8ba..ee2de0ad68 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -112,5 +112,4 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y -CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 9cd3daab35..a446bb9f2c 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -102,5 +102,4 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y -CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index f7dfb94768..0db930f733 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -66,6 +66,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index a89c410c12..f5cca80a6d 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -63,6 +63,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 6996f856a7..dea8479253 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -50,6 +50,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 101e23d250..60539f4380 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -64,6 +64,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 1346d5eaac..f4bebee147 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -43,6 +43,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index bcbd276b02..e22542fd8c 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -50,6 +50,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index 0a676d48c9..128f10fa5d 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -19,12 +19,9 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b" CONFIG_CMD_IMLS=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y # CONFIG_CMD_NAND is not set -CONFIG_CMD_MMC_SPI=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y +# CONFIG_CMD_PCI is not set +# CONFIG_CMD_SATA is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -35,26 +32,18 @@ CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_FSL_ESDHC=y +# CONFIG_SATA_SIL is not set +# CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_FS_CRAMFS=y CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index 05077c5b73..a0a4abab4e 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -17,7 +17,6 @@ CONFIG_BOOTDELAY=1 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" @@ -50,5 +49,6 @@ CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_TPS65910=y CONFIG_CONS_INDEX=4 +# CONFIG_OMAP_WATCHDOG is not set # CONFIG_USE_TINY_PRINTF is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig index 584e54d535..7f6ccc9f54 100644 --- a/configs/apalis-imx8qm_defconfig +++ b/configs/apalis-imx8qm_defconfig @@ -54,5 +54,4 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y # CONFIG_EFI_LOADER is not set diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 6f36f7b82e..248922cd56 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index b14786ed3d..5292ef96ee 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig index a71ec2b03e..353790f446 100644 --- a/configs/bg0900_defconfig +++ b/configs/bg0900_defconfig @@ -22,9 +22,6 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=2 CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -33,13 +30,7 @@ CONFIG_DOS_PARTITION=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=40000000 -CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y -CONFIG_MXS_SPI=y CONFIG_OF_LIBFDT=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 8baac6fc70..3cbc949a01 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -15,7 +15,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 4ce6a09483..67526e87c0 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -34,7 +34,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 8d63c874cc..c3c29d38e5 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 91d9fdf961..522e60bbb5 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -28,7 +28,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_PART=y CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 40f6bb9830..3b2cbdcd44 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_PART=y CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 0b0198151b..a42d726b71 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -18,7 +18,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 5c89439f7b..1c027299b6 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_COLIBRI_IMX6ULL=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig index d808bd7608..8d6c0788f1 100644 --- a/configs/colibri-imx8qxp_defconfig +++ b/configs/colibri-imx8qxp_defconfig @@ -3,8 +3,8 @@ CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_TARGET_COLIBRI_IMX8X=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=3 +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg" CONFIG_LOG=y @@ -52,5 +52,4 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y # CONFIG_EFI_LOADER is not set diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index a60d6951c9..56e512d529 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -85,7 +84,7 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index efbf5f55a3..e5e4168285 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SECURE_BOOT=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_NR_DRAM_BANKS=1 @@ -66,8 +65,8 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y -CONFIG_DM_USB=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 89f43e5fb9..06902b6311 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SECURE_BOOT=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_TARGET_COLIBRI_IMX7_EMMC=y @@ -45,6 +44,12 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_FSL_CAAM=y CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y @@ -59,22 +64,13 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_USB=y -CONFIG_FASTBOOT=y -CONFIG_FASTBOOT_USB_DEV=0 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_FASTBOOT_BUF_SIZE=0x10000000 diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index d6a20ca642..170a1b0b27 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -67,4 +67,3 @@ CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 8bce6b75ef..338317203e 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index b3cf9704d7..4fdee998be 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index c11d5f2147..b05da76ef1 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 092ab42941..e575040a47 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index c7a7983976..a47cf02b8f 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -22,7 +22,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -45,7 +44,6 @@ CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=31 CONFIG_SYS_NS16550=y CONFIG_SPI=y -CONFIG_LPC32XX_SSP=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index d8b900f964..111011c854 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 70f0277040..d71bbced01 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -10,8 +10,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 -CONFIG_DM_GPIO=y -CONFIG_DM_MMC=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_AHCI=y @@ -46,6 +44,8 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 840c87ac5a..468754493e 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -39,5 +39,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x8087 CONFIG_USB_GADGET_PRODUCT_NUM=0x0a99 CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_USB_HOST_ETHER is not set +CONFIG_WDT=y +CONFIG_WDT_TANGIER=y CONFIG_FAT_WRITE=y CONFIG_SHA1=y diff --git a/configs/efi-x86_app_defconfig b/configs/efi-x86_app_defconfig index b4e8921f8c..ea3743dd12 100644 --- a/configs/efi-x86_app_defconfig +++ b/configs/efi-x86_app_defconfig @@ -14,7 +14,6 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTM is not set CONFIG_CMD_PART=y -# CONFIG_CMD_SF_TEST is not set # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index aff9c32362..92d6817ad5 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,7 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -19,11 +22,15 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index db088c0e97..ba5a501963 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index f282064fc7..3db70827a1 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 5ad49b38ec..c27c5ccf69 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SECURE_BOOT=y CONFIG_TARGET_MX6DL_MAMOJ=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index d39fd957a3..ad4b930a39 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index 8704006ae7..f6fc59ff5e 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index b65979967a..5ab932d0ae 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 83b926b699..4b8998177b 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 318628b1a0..d5fdc43f48 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6UL_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 00c9bbd859..88b9b49781 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6UL_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index bc84a66b5f..f02b5e2084 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -3,7 +3,6 @@ CONFIG_SPL_SYS_ICACHE_OFF=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_IMX8MQ_EVK=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 1c67b98c5d..6db0669ef4 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_IMX8QM_MEK=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index eaa16d3680..1ef92b445a 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -36,6 +36,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index cef646b115..5428357030 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -36,6 +36,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index d521979e72..2b83e4ad17 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_DM=y # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index a41f97cf8f..3de0a982db 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -32,6 +32,7 @@ CONFIG_DM=y # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -43,6 +44,7 @@ CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index bf98466576..a4ae87b9a7 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -33,6 +33,7 @@ CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -45,6 +46,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index b0fdad6dd0..827d4ec2c0 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -33,6 +33,7 @@ CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -45,6 +46,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 6a70f5881b..cbeb9cabcf 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -34,6 +34,7 @@ CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_WINBOND=y CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -46,6 +47,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 7194182ce2..90b30a6172 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -53,6 +53,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -67,6 +68,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 6de203b1ec..ebd3eeaa12 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -59,6 +60,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 44b4e121c0..3a99037883 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -53,6 +53,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -67,6 +68,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index 54b050e029..533e251341 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_PCI=y @@ -49,6 +50,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 78b4186782..f9ea2097fb 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -37,6 +37,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -50,6 +51,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index b612587897..8e2ff1fe7b 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -38,6 +38,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_PCI=y @@ -49,6 +50,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 2f96abc1bf..8acc07d3c8 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -37,6 +37,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y @@ -50,6 +51,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..7cd2f59d7b --- /dev/null +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028AQDS=y +CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y +CONFIG_RSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index 717b810523..7982ce4157 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..3432f90087 --- /dev/null +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1028ARDB=y +CONFIG_SECURE_BOOT=y +CONFIG_SYS_FSL_SDHC_CLK_DIV=1 +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M" +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-rdb" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SP805=y +CONFIG_RSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index a8e4ddb7a8..c65e37df79 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_E1000=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_ECAM_GENERIC=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig new file mode 100644 index 0000000000..0b94b018d6 --- /dev/null +++ b/configs/ls1046afrwy_tfa_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AFRWY=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_QSPI_AHB_INIT=y +CONFIG_TFABOOT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_MISC_INIT_R=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 63f6588d2b..855edc726e 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index a4038b8d29..6326c47cdb 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -52,6 +52,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 92afc919a5..7bf23ad7fd 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_DM=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 9c124fd7e0..829861b03b 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index a375546a75..1f37729063 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -1,8 +1,8 @@ CONFIG_RISCV=y +CONFIG_TARGET_MICROCHIP_ICICLE=y CONFIG_ARCH_RV64I=y CONFIG_NR_CPUS=5 -CONFIG_TARGET_MICROCHIP_ICICLE=y +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_FIT=y CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 16df6ef137..446c2f2c03 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index 9fbe9ea510..27c152571a 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -22,9 +22,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=2 CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -44,15 +41,9 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_SST=y CONFIG_MII=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y -CONFIG_MXS_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 62661eac31..4cee901d83 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -22,9 +22,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=2 CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -44,15 +41,9 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_SST=y CONFIG_MII=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y -CONFIG_MXS_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index f18dbd3749..3875da733a 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -21,9 +21,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=2 CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -43,15 +40,9 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_SST=y CONFIG_MII=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y -CONFIG_MXS_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index db3ac7d7a2..37477b35f1 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -21,9 +21,6 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_DEFAULT_SPI_BUS=2 CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -39,19 +36,12 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:3m(bootloader)ro,512k(environment),512k(redundant-environment),4m(kernel),512k(fdt),8m(ramdisk),-(filesystem)" CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC_MXS=y CONFIG_NAND=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=2 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_SST=y CONFIG_MII=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y -CONFIG_MXS_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 89d542fef7..0739c581a7 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -82,16 +82,15 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_MII=y +CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y -CONFIG_PCI=y CONFIG_DM_REGULATOR=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y -# CONFIG_SPL_DM_USB is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 97a94cbc36..5799ab39f4 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -6,16 +6,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -26,7 +27,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index e649ebb549..2a7807d360 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_MX6_DDRCAL=y CONFIG_TARGET_KOSAGI_NOVENA=y CONFIG_SPL_MMC_SUPPORT=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index badc4b0236..b0ec1208f5 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_OPOS6ULDEV=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 2a21ff1dd0..4bd8cd29f3 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -4,8 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TEGRA210=y CONFIG_TARGET_P2371_2180=y -CONFIG_OF_SYSTEM_SETUP=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # " diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 4ac810db35..808577167e 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -3,8 +3,8 @@ CONFIG_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=1026 CONFIG_TEGRA186=y -CONFIG_OF_SYSTEM_SETUP=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # " diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 3ca85272a8..b222bfa446 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -3,8 +3,8 @@ CONFIG_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=1026 CONFIG_TEGRA186=y -CONFIG_OF_SYSTEM_SETUP=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # " diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 75408a8344..5c07b954b6 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -6,10 +6,9 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_PCL063_ULL=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=8 CONFIG_SPL=y -# CONFIG_CMD_DEKBLOB is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=8 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 03f0bfdb59..5cb2273a15 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,13 +15,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" +CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index b1cd5b4f44..d89cd44144 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 2a36f405f4..898d656ac3 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -21,7 +21,6 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 32da77aa39..be670df23f 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -6,16 +6,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -26,7 +27,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 0000000000..6529dedfb6 --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 90bcaedbd2..e8fc7ae141 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -6,16 +6,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -26,7 +27,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index bfb1eaf0e7..29a9df8ab0 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 4cffa2c604..6894262b89 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -44,7 +44,6 @@ CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_AXI=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index dda6832f83..af335285c9 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index ec8726b798..da9229fc79 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 3e0bf5d3b5..d355cc3f3b 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -45,7 +45,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index b34709d1ea..d9fa1ca57f 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_MD5SUM=y # CONFIG_CMD_LOADB is not set CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y -CONFIG_CMD_SF=y # CONFIG_CMD_ECHO is not set # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set @@ -29,14 +28,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y CONFIG_SH_MMCIF=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y CONFIG_SH_ETHER=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y -CONFIG_SH_SPI=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index 857e90b86a..e5698d802f 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -17,7 +17,6 @@ CONFIG_CMD_MD5SUM=y # CONFIG_CMD_LOADB is not set CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y -CONFIG_CMD_SF=y # CONFIG_CMD_ECHO is not set # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set @@ -28,14 +27,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y CONFIG_SH_MMCIF=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y CONFIG_SH_ETHER=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y -CONFIG_SH_SPI=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index 8314435b93..f9b7379cee 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_MD5SUM=y # CONFIG_CMD_LOADB is not set CONFIG_CMD_MMC=y CONFIG_CMD_SDRAM=y -CONFIG_CMD_SF=y # CONFIG_CMD_ECHO is not set # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set @@ -31,13 +30,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y CONFIG_SH_MMCIF=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y CONFIG_SH_ETHER=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y -CONFIG_SH_SPI=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 0287314469..fe1aa8236b 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 66361c8715..5fe9477823 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -73,7 +73,7 @@ CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_DWC_ETH_QOS=y CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y CONFIG_PINCONF=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index f01e53055c..2653f71f78 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index a0586145d5..ee9189aeae 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 2f8eaa4402..7da1beaa99 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 0e8cf73fe9..27a5fc0dfb 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -3,10 +3,10 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_SIZE_LIMIT=30720 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_SIZE_LIMIT=30720 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/u200_defconfig b/configs/u200_defconfig index 2c0999c707..ced6ca84b6 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -15,6 +15,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y @@ -27,6 +29,7 @@ CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=8 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y CONFIG_DM_REGULATOR=y @@ -36,21 +39,16 @@ CONFIG_DEBUG_UART_MESON=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_USB=y -CONFIG_USB_HOST=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_PHY=y -CONFIG_MESON_G12A_USB_PHY=y CONFIG_DM_USB=y -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MESON_G12A=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index bbd13e0cd9..01c8884f2b 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -28,7 +28,6 @@ CONFIG_CMD_EEPROM=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -41,4 +40,3 @@ CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y -CONFIG_LPC32XX_SSP=y diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig deleted file mode 100644 index 509adcffd9..0000000000 --- a/configs/zipitz2_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_ZIPITZ2=y -CONFIG_SYS_TEXT_BASE=0x0 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=tty0 console=ttyS2,115200 fbcon=rotate:3" -# CONFIG_CONSOLE_MUX is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="$ " -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -# CONFIG_NET is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_CONS_INDEX=2 -CONFIG_PXA_SERIAL=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_LCD=y -CONFIG_LZMA=y -CONFIG_OF_LIBFDT=y -# CONFIG_EFI_LOADER is not set diff --git a/disk/part.c b/disk/part.c index 862078f3e7..f14bc22b6d 100644 --- a/disk/part.c +++ b/disk/part.c @@ -414,11 +414,10 @@ int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str, #ifdef CONFIG_HAVE_BLOCK_DEVICE /* * Updates the partition table for the specified hw partition. - * Does not need to be done for hwpart 0 since it is default and - * already loaded. + * Always should be done, otherwise hw partition 0 will return stale + * data after displaying a non-zero hw partition. */ - if(hwpart != 0) - part_init(*dev_desc); + part_init(*dev_desc); #endif cleanup: diff --git a/Documentation/Makefile b/doc/Makefile index 2ca77ad0f2..5135a96e88 100644 --- a/Documentation/Makefile +++ b/doc/Makefile @@ -8,7 +8,7 @@ subdir-y := SPHINXBUILD = sphinx-build SPHINXOPTS = SPHINXDIRS = . -_SPHINXDIRS = $(patsubst $(srctree)/Documentation/%/conf.py,%,$(wildcard $(srctree)/Documentation/*/conf.py)) +_SPHINXDIRS = $(patsubst $(srctree)/doc/%/conf.py,%,$(wildcard $(srctree)/doc/*/conf.py)) SPHINX_CONF = conf.py PAPER = BUILDDIR = $(obj)/output @@ -49,10 +49,10 @@ loop_cmd = $(echo-cmd) $(cmd_$(1)) || exit; # * cache folder relative to $(BUILDDIR)/.doctrees # $4 dest subfolder e.g. "man" for man pages at media/man # $5 reST source folder relative to $(srctree)/$(src), -# e.g. "media" for the linux-tv book-set at ./Documentation/media +# e.g. "media" for the linux-tv book-set at ./doc/media quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4) - cmd_sphinx = $(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/media $2 && \ + cmd_sphinx = $(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=doc/media $2 && \ PYTHONDONTWRITEBYTECODE=1 \ BUILDDIR=$(abspath $(BUILDDIR)) SPHINX_CONF=$(abspath $(srctree)/$(src)/$5/$(SPHINX_CONF)) \ $(SPHINXBUILD) \ @@ -102,7 +102,7 @@ refcheckdocs: cleandocs: $(Q)rm -rf $(BUILDDIR) - $(Q)$(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/media clean + $(Q)$(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=doc/media clean dochelp: @echo ' Linux kernel internal documentation in different formats from ReST:' @@ -121,4 +121,4 @@ dochelp: @echo ' make SPHINX_CONF={conf-file} [target] use *additional* sphinx-build' @echo ' configuration. This is e.g. useful to build with nit-picking config.' @echo - @echo ' Default location for the generated documents is Documentation/output' + @echo ' Default location for the generated documents is doc/output' diff --git a/doc/README.rockchip b/doc/README.rockchip index 264f7e4994..02e2497b15 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -48,9 +48,10 @@ Two RK3036 boards are supported: - EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration -One RK3328 board is supported: +Two RK3328 board are supported: - - EVB RK3328 + - EVB RK3328 - use evb-rk3328_defconfig + - Pine64 Rock64 board - use rock64-rk3328_defconfig Size RK3399 boards are supported (aarch64): @@ -103,7 +104,6 @@ For example: => cd /path/to/u-boot => make nanopi-neo4-rk3399_defconfig => make - => make u-boot.itb - Get the rkbin @@ -137,8 +137,8 @@ For example: => cd arm-trusted-firmware => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 - (copy bl31.bin into U-Boot root dir) - => cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin + (export bl31.bin) + => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.bin For rest of rk3399 boards. @@ -149,8 +149,8 @@ For example: => make realclean => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 - (copy bl31.elf into U-Boot root dir) - => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot + (export bl31.elf) + => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf - Compile PMU M0 firmware @@ -162,15 +162,14 @@ For example: (export cross compiler path for Cortex-M0 PMU) => make CROSS_COMPILE=arm-cortex_m0-eabi- - (copy rk3399m0.bin into U-Boot root dir) - => cp rk3399m0.bin /path/to/u-boot + (export rk3399m0.bin) + => export PMUM0=/path/to/rk3399-cortex-m0/rk3399m0.bin - Compile U-Boot => cd /path/to/u-boot => make orangepi-rk3399_defconfig => make - => make u-boot.itb (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL @@ -310,6 +309,31 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out +Booting from an SD card on Pine64 Rock64 (RK3328) +================================================= + +For Rock64 rk3328 board the following three parts are required: +TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and +u-boot.itb are to be compiled as usual, TPL is currently not +implemented in u-boot, so you need to pick one from rkbin: + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create TPL/SPL image + + => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img + => cat spl/u-boot-spl.bin >> idbloader.img + + - Write TPL/SPL image at 64 sector + + => sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 + + - Write u-boot image tree blob at 16384 sector + + => sudo dd if=u-boot.itb of=/dev/mmcblk0 seek=16384 + Booting from an SD card on RK3399 ================================= diff --git a/Documentation/conf.py b/doc/conf.py index 168c31346b..168c31346b 100644 --- a/Documentation/conf.py +++ b/doc/conf.py diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/doc/device-tree-bindings/arm/l2c2x0.txt index fbe6cb21f4..fbe6cb21f4 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/doc/device-tree-bindings/arm/l2c2x0.txt diff --git a/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt b/doc/device-tree-bindings/axi/gdsys,ihs_axi.txt index 110788fa91..110788fa91 100644 --- a/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt +++ b/doc/device-tree-bindings/axi/gdsys,ihs_axi.txt diff --git a/Documentation/devicetree/bindings/board/gdsys,board_gazerbeam.txt b/doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt index 28c1080d90..28c1080d90 100644 --- a/Documentation/devicetree/bindings/board/gdsys,board_gazerbeam.txt +++ b/doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt diff --git a/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt index 8313da8507..8313da8507 100644 --- a/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt +++ b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt diff --git a/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt index ac563d906a..ac563d906a 100644 --- a/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt +++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt diff --git a/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt b/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt index 64a9b5b154..64a9b5b154 100644 --- a/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt +++ b/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt b/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt index db2ff8ca12..db2ff8ca12 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt b/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt index acd466fdc6..acd466fdc6 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt b/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt index 819db22bf7..819db22bf7 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt b/doc/device-tree-bindings/misc/misc/gdsys,soc.txt index 278e935b16..278e935b16 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,soc.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,soc.txt diff --git a/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt b/doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt index da01fe908d..da01fe908d 100644 --- a/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt +++ b/doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/doc/device-tree-bindings/reserved-memory/reserved-memory.txt index bac4afa3b1..bac4afa3b1 100644 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +++ b/doc/device-tree-bindings/reserved-memory/reserved-memory.txt diff --git a/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt b/doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt index 608d24110b..608d24110b 100644 --- a/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt +++ b/doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt diff --git a/Documentation/efi.rst b/doc/efi.rst index 5337a55c3b..5337a55c3b 100644 --- a/Documentation/efi.rst +++ b/doc/efi.rst diff --git a/Documentation/index.rst b/doc/index.rst index 0353c10a4b..0353c10a4b 100644 --- a/Documentation/index.rst +++ b/doc/index.rst diff --git a/Documentation/linker_lists.rst b/doc/linker_lists.rst index 72f514e0ac..72f514e0ac 100644 --- a/Documentation/linker_lists.rst +++ b/doc/linker_lists.rst diff --git a/Documentation/media/Makefile b/doc/media/Makefile index 0efd18ab4d..b9b43a34c3 100644 --- a/Documentation/media/Makefile +++ b/doc/media/Makefile @@ -1,7 +1,7 @@ # Rules to convert a .h file to inline RST documentation -SRC_DIR=$(srctree)/Documentation/media -PARSER = $(srctree)/Documentation/sphinx/parse-headers.pl +SRC_DIR=$(srctree)/doc/media +PARSER = $(srctree)/doc/sphinx/parse-headers.pl API = $(srctree)/include FILES = linker_lists.h.rst diff --git a/Documentation/media/linker_lists.h.rst.exceptions b/doc/media/linker_lists.h.rst.exceptions index e69de29bb2..e69de29bb2 100644 --- a/Documentation/media/linker_lists.h.rst.exceptions +++ b/doc/media/linker_lists.h.rst.exceptions diff --git a/Documentation/serial.rst b/doc/serial.rst index ed34e592a4..ed34e592a4 100644 --- a/Documentation/serial.rst +++ b/doc/serial.rst diff --git a/Documentation/sphinx-static/theme_overrides.css b/doc/sphinx-static/theme_overrides.css index 522b6d4c49..522b6d4c49 100644 --- a/Documentation/sphinx-static/theme_overrides.css +++ b/doc/sphinx-static/theme_overrides.css diff --git a/Documentation/sphinx/cdomain.py b/doc/sphinx/cdomain.py index cf13ff3a65..cf13ff3a65 100644 --- a/Documentation/sphinx/cdomain.py +++ b/doc/sphinx/cdomain.py diff --git a/Documentation/sphinx/kernel_include.py b/doc/sphinx/kernel_include.py index f523aa68a3..f523aa68a3 100755 --- a/Documentation/sphinx/kernel_include.py +++ b/doc/sphinx/kernel_include.py diff --git a/Documentation/sphinx/kerneldoc.py b/doc/sphinx/kerneldoc.py index fbedcc3946..fbedcc3946 100644 --- a/Documentation/sphinx/kerneldoc.py +++ b/doc/sphinx/kerneldoc.py diff --git a/Documentation/sphinx/kfigure.py b/doc/sphinx/kfigure.py index b97228d2cc..b97228d2cc 100644 --- a/Documentation/sphinx/kfigure.py +++ b/doc/sphinx/kfigure.py diff --git a/Documentation/sphinx/load_config.py b/doc/sphinx/load_config.py index 301a21aa4f..301a21aa4f 100644 --- a/Documentation/sphinx/load_config.py +++ b/doc/sphinx/load_config.py diff --git a/Documentation/sphinx/parse-headers.pl b/doc/sphinx/parse-headers.pl index d410f47567..d4f38262eb 100755 --- a/Documentation/sphinx/parse-headers.pl +++ b/doc/sphinx/parse-headers.pl @@ -382,7 +382,7 @@ ioctl. The EXCEPTIONS_FILE contain two rules to allow ignoring a symbol or to replace the default references by a custom one. -Please read Documentation/doc-guide/parse-headers.rst at the Kernel's +Please read doc/doc-guide/parse-headers.rst at the Kernel's tree for more details. =head1 BUGS diff --git a/Documentation/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 742be3e126..742be3e126 100644 --- a/Documentation/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt diff --git a/Documentation/sphinx/rstFlatTable.py b/doc/sphinx/rstFlatTable.py index 25feb0d35e..f9a4b46dbe 100755 --- a/Documentation/sphinx/rstFlatTable.py +++ b/doc/sphinx/rstFlatTable.py @@ -54,7 +54,7 @@ from docutils.utils import SystemMessagePropagation # ============================================================================== # The version numbering follows numbering of the specification -# (Documentation/books/kernel-doc-HOWTO). +# (doc/books/kernel-doc-HOWTO). __version__ = '1.0' PY3 = sys.version_info[0] == 3 diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 4268628f5e..bf957e8326 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -20,7 +20,9 @@ static void getvar_product(char *var_parameter, char *response); static void getvar_platform(char *var_parameter, char *response); static void getvar_current_slot(char *var_parameter, char *response); static void getvar_slot_suffixes(char *var_parameter, char *response); +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) static void getvar_has_slot(char *var_parameter, char *response); +#endif #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) static void getvar_partition_type(char *part_name, char *response); #endif @@ -65,9 +67,11 @@ static const struct { }, { .variable = "slot-suffixes", .dispatch = getvar_slot_suffixes +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) }, { .variable = "has-slot", .dispatch = getvar_has_slot +#endif #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) }, { .variable = "partition-type", @@ -81,6 +85,47 @@ static const struct { } }; +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) +/** + * Get partition number and size for any storage type. + * + * Can be used to check if partition with specified name exists. + * + * If error occurs, this function guarantees to fill @p response with fail + * string. @p response can be rewritten in caller, if needed. + * + * @param[in] part_name Info for which partition name to look for + * @param[in,out] response Pointer to fastboot response buffer + * @param[out] size If not NULL, will contain partition size (in blocks) + * @return Partition number or negative value on error + */ +static int getvar_get_part_info(const char *part_name, char *response, + size_t *size) +{ + int r; +# if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) + struct blk_desc *dev_desc; + disk_partition_t part_info; + + r = fastboot_mmc_get_part_info(part_name, &dev_desc, &part_info, + response); + if (r >= 0 && size) + *size = part_info.size; +# elif CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND) + struct part_info *part_info; + + r = fastboot_nand_get_part_info(part_name, &part_info, response); + if (r >= 0 && size) + *size = part_info->size; +# else + fastboot_fail("this storage is not supported in bootloader", response); + r = -ENODEV; +# endif + + return r; +} +#endif + static void getvar_version(char *var_parameter, char *response) { fastboot_okay(FASTBOOT_VERSION, response); @@ -133,23 +178,48 @@ static void getvar_platform(char *var_parameter, char *response) static void getvar_current_slot(char *var_parameter, char *response) { - /* A/B not implemented, for now always return _a */ - fastboot_okay("_a", response); + /* A/B not implemented, for now always return "a" */ + fastboot_okay("a", response); } static void getvar_slot_suffixes(char *var_parameter, char *response) { - fastboot_okay("_a,_b", response); + fastboot_okay("a,b", response); } +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) static void getvar_has_slot(char *part_name, char *response) { - if (part_name && (!strcmp(part_name, "boot") || - !strcmp(part_name, "system"))) - fastboot_okay("yes", response); - else - fastboot_okay("no", response); + char part_name_wslot[PART_NAME_LEN]; + size_t len; + int r; + + if (!part_name || part_name[0] == '\0') + goto fail; + + /* part_name_wslot = part_name + "_a" */ + len = strlcpy(part_name_wslot, part_name, PART_NAME_LEN - 3); + if (len > PART_NAME_LEN - 3) + goto fail; + strcat(part_name_wslot, "_a"); + + r = getvar_get_part_info(part_name_wslot, response, NULL); + if (r >= 0) { + fastboot_okay("yes", response); /* part exists and slotted */ + return; + } + + r = getvar_get_part_info(part_name, response, NULL); + if (r >= 0) + fastboot_okay("no", response); /* part exists but not slotted */ + + /* At this point response is filled with okay or fail string */ + return; + +fail: + fastboot_fail("invalid partition name", response); } +#endif #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) static void getvar_partition_type(char *part_name, char *response) @@ -176,22 +246,7 @@ static void getvar_partition_size(char *part_name, char *response) int r; size_t size; -#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) - struct blk_desc *dev_desc; - disk_partition_t part_info; - - r = fastboot_mmc_get_part_info(part_name, &dev_desc, &part_info, - response); - if (r >= 0) - size = part_info.size; -#endif -#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND) - struct part_info *part_info; - - r = fastboot_nand_get_part_info(part_name, &part_info, response); - if (r >= 0) - size = part_info->size; -#endif + r = getvar_get_part_info(part_name, response, &size); if (r >= 0) fastboot_response("OKAY", response, "0x%016zx", size); } diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 90ca81da9b..0a335db3a6 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -298,7 +298,8 @@ static int fb_mmc_update_zimage(struct blk_desc *dev_desc, * @part_info: Pointer to returned disk_partition_t * @response: Pointer to fastboot response buffer */ -int fastboot_mmc_get_part_info(char *part_name, struct blk_desc **dev_desc, +int fastboot_mmc_get_part_info(const char *part_name, + struct blk_desc **dev_desc, disk_partition_t *part_info, char *response) { int r; diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_nand.c index 526bc12307..6756ea769f 100644 --- a/drivers/fastboot/fb_nand.c +++ b/drivers/fastboot/fb_nand.c @@ -152,8 +152,8 @@ static lbaint_t fb_nand_sparse_reserve(struct sparse_storage *info, * @part_info: Pointer to returned part_info pointer * @response: Pointer to fastboot response buffer */ -int fastboot_nand_get_part_info(char *part_name, struct part_info **part_info, - char *response) +int fastboot_nand_get_part_info(const char *part_name, + struct part_info **part_info, char *response) { struct mtd_info *mtd = NULL; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 672691fa6a..6a191a1765 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc + * Copyright 2019 NXP Semiconductors * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -25,6 +26,10 @@ #include <asm-generic/gpio.h> #include <dm/pinctrl.h> +#if !CONFIG_IS_ENABLED(BLK) +#include "mmc_private.h" +#endif + DECLARE_GLOBAL_DATA_PTR; #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ @@ -34,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ IRQSTATEN_DINT) #define MAX_TUNING_LOOP 40 +#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ @@ -1457,6 +1463,9 @@ static int fsl_esdhc_probe(struct udevice *dev) fdt_addr_t addr; unsigned int val; struct mmc *mmc; +#if !CONFIG_IS_ENABLED(BLK) + struct blk_desc *bdesc; +#endif int ret; addr = dev_read_addr(dev); @@ -1593,6 +1602,26 @@ static int fsl_esdhc_probe(struct udevice *dev) mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev; +#if !CONFIG_IS_ENABLED(BLK) + mmc->priv = priv; + + /* Setup dsr related values */ + mmc->dsr_imp = 0; + mmc->dsr = ESDHC_DRIVER_STAGE_VALUE; + /* Setup the universal parts of the block interface just once */ + bdesc = mmc_get_blk_desc(mmc); + bdesc->if_type = IF_TYPE_MMC; + bdesc->removable = 1; + bdesc->devnum = mmc_get_next_devnum(); + bdesc->block_read = mmc_bread; + bdesc->block_write = mmc_bwrite; + bdesc->block_erase = mmc_berase; + + /* setup initial part type */ + bdesc->part_type = mmc->cfg->part_type; + mmc_list_add(mmc); +#endif + upriv->mmc = mmc; return esdhc_init_common(priv, mmc); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 456c1b4cc9..71b52c6cf2 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -905,14 +905,14 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num) { int forbidden = 0; bool change = false; if (part_num & PART_ACCESS_MASK) - forbidden = MMC_CAP(MMC_HS_200); + forbidden = MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400); if (MMC_CAP(mmc->selected_mode) & forbidden) { pr_debug("selected mode (%s) is forbidden for part %d\n", diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 429bb836a8..3fe38f7315 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,6 +60,14 @@ config PCIE_DW_MVEBU Armada-8K SoCs. The PCIe controller on Armada-8K is based on DesignWare hardware. +config PCIE_FSL + bool "FSL PowerPC PCIe support" + depends on DM_PCI + help + Say Y here if you want to enable PCIe controller support on FSL + PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. + This driver does not support SRIO_PCIE_BOOT feature. + config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index bd392edba1..b5ebd50c85 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o +obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c index 183787333e..84908e6154 100644 --- a/drivers/pci/pci_auto_common.c +++ b/drivers/pci/pci_auto_common.c @@ -21,9 +21,10 @@ void pciauto_region_init(struct pci_region *res) /* * Avoid allocating PCI resources from address 0 -- this is illegal * according to PCI 2.1 and moreover, this is known to cause Linux IDE - * drivers to fail. Use a reasonable starting value of 0x1000 instead. + * drivers to fail. Use a reasonable starting value of 0x1000 instead + * if the bus start address is below 0x1000. */ - res->bus_lower = res->bus_start ? res->bus_start : 0x1000; + res->bus_lower = res->bus_start < 0x1000 ? 0x1000 : res->bus_start; } void pciauto_region_align(struct pci_region *res, pci_size_t size) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c new file mode 100644 index 0000000000..4d61a46cef --- /dev/null +++ b/drivers/pci/pcie_fsl.c @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 NXP + * + * PCIe DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + */ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <mapmem.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_serdes.h> +#include <asm/io.h> +#include "pcie_fsl.h" + +LIST_HEAD(fsl_pcie_list); + +static int fsl_pcie_link_up(struct fsl_pcie *pcie); + +static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf) +{ + struct udevice *bus = pcie->bus; + + if (!pcie->enabled) + return -ENXIO; + + if (PCI_BUS(bdf) < bus->seq) + return -EINVAL; + + if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode)) + return -EINVAL; + + if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0)) + return -EINVAL; + + if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0)) + return -EINVAL; + + return 0; +} + +static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct fsl_pcie *pcie = dev_get_priv(bus); + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + + if (fsl_pcie_addr_valid(pcie, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + + bdf = bdf - PCI_BDF(bus->seq, 0, 0); + val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + out_be32(®s->cfg_addr, val); + + sync(); + + switch (size) { + case PCI_SIZE_8: + *valuep = in_8((u8 *)®s->cfg_data + (offset & 3)); + break; + case PCI_SIZE_16: + *valuep = in_le16((u16 *)((u8 *)®s->cfg_data + + (offset & 2))); + break; + case PCI_SIZE_32: + *valuep = in_le32(®s->cfg_data); + break; + } + + return 0; +} + +static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct fsl_pcie *pcie = dev_get_priv(bus); + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + u8 val_8; + u16 val_16; + u32 val_32; + + if (fsl_pcie_addr_valid(pcie, bdf)) + return 0; + + bdf = bdf - PCI_BDF(bus->seq, 0, 0); + val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + out_be32(®s->cfg_addr, val); + + sync(); + + switch (size) { + case PCI_SIZE_8: + val_8 = value; + out_8((u8 *)®s->cfg_data + (offset & 3), val_8); + break; + case PCI_SIZE_16: + val_16 = value; + out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16); + break; + case PCI_SIZE_32: + val_32 = value; + out_le32(®s->cfg_data, val_32); + break; + } + + return 0; +} + +static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset, + ulong *valuep, enum pci_size_t size) +{ + int ret; + struct udevice *bus = pcie->bus; + + ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0), + offset, valuep, size); + + return ret; +} + +static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset, + ulong value, enum pci_size_t size) +{ + struct udevice *bus = pcie->bus; + + return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0), + offset, value, size); +} + +static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset, + u8 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset, + u16 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset, + u32 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset, + u8 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8); +} + +static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset, + u16 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16); +} + +static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset, + u32 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32); +} + +static int fsl_pcie_link_up(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u16 ltssm; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + ltssm = (in_be32(®s->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + return ltssm == LTSSM_L0_REV3; + } + + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + + return ltssm == LTSSM_L0; +} + +static bool fsl_pcie_is_agent(struct fsl_pcie *pcie) +{ + u8 header_type; + + fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type); + + return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; +} + +static int fsl_pcie_setup_law(struct fsl_pcie *pcie) +{ + struct pci_region *io, *mem, *pref; + + pci_get_regions(pcie->bus, &io, &mem, &pref); + + if (mem) + set_next_law(mem->phys_start, + law_size_bits(mem->size), + pcie->law_trgt_if); + + if (io) + set_next_law(io->phys_start, + law_size_bits(io->size), + pcie->law_trgt_if); + + return 0; +} + +static void fsl_pcie_config_ready(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY); + return; + } + + fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1); +} + +static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx, + int type, u64 phys, u64 bus_addr, + pci_size_t size) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + pot_t *po = ®s->pot[idx]; + u32 war, sz; + + if (idx < 0) + return -EINVAL; + + out_be32(&po->powbar, phys >> 12); + out_be32(&po->potar, bus_addr >> 12); +#ifdef CONFIG_SYS_PCI_64BIT + out_be32(&po->potear, bus_addr >> 44); +#else + out_be32(&po->potear, 0); +#endif + + sz = (__ilog2_u64((u64)size) - 1); + war = POWAR_EN | sz; + + if (type == PCI_REGION_IO) + war |= POWAR_IO_READ | POWAR_IO_WRITE; + else + war |= POWAR_MEM_READ | POWAR_MEM_WRITE; + + out_be32(&po->powar, war); + + return 0; +} + +static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx, + bool pf, u64 phys, u64 bus_addr, + pci_size_t size) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + pit_t *pi = ®s->pit[idx]; + u32 sz = (__ilog2_u64(size) - 1); + u32 flag = PIWAR_LOCAL; + + if (idx < 0) + return -EINVAL; + + out_be32(&pi->pitar, phys >> 12); + out_be32(&pi->piwbar, bus_addr >> 12); + +#ifdef CONFIG_SYS_PCI_64BIT + out_be32(&pi->piwbear, bus_addr >> 44); +#else + out_be32(&pi->piwbear, 0); +#endif + + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434)) + flag = 0; + + flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; + if (pf) + flag |= PIWAR_PF; + out_be32(&pi->piwar, flag | sz); + + return 0; +} + +static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie) +{ + struct pci_region *io, *mem, *pref; + int idx = 1; /* skip 0 */ + + pci_get_regions(pcie->bus, &io, &mem, &pref); + + if (io) + /* ATU : OUTBOUND : IO */ + fsl_pcie_setup_outbound_win(pcie, idx++, + PCI_REGION_IO, + io->phys_start, + io->bus_start, + io->size); + + if (mem) + /* ATU : OUTBOUND : MEM */ + fsl_pcie_setup_outbound_win(pcie, idx++, + PCI_REGION_MEM, + mem->phys_start, + mem->bus_start, + mem->size); + return 0; +} + +static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) +{ + phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; + pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; + u64 sz = min((u64)gd->ram_size, (1ull << 32)); + pci_size_t pci_sz; + int idx; + + if (pcie->block_rev >= PEX_IP_BLK_REV_2_2) + idx = 2; + else + idx = 3; + + pci_sz = 1ull << __ilog2_u64(sz); + + dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)bus_start, (u64)phys_start, (u64)sz); + + /* if we aren't an exact power of two match, pci_sz is smaller + * round it up to the next power of two. We report the actual + * size to pci region tracking. + */ + if (pci_sz != sz) + sz = 2ull << __ilog2_u64(sz); + + fsl_pcie_setup_inbound_win(pcie, idx--, true, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_BUS, sz); +#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) + /* + * On 64-bit capable systems, set up a mapping for all of DRAM + * in high pci address space. + */ + pci_sz = 1ull << __ilog2_u64(gd->ram_size); + /* round up to the next largest power of two */ + if (gd->ram_size > pci_sz) + pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); + + dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)CONFIG_SYS_PCI64_MEMORY_BUS, + (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); + + fsl_pcie_setup_inbound_win(pcie, idx--, true, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz); +#endif + + return 0; +} + +static int fsl_pcie_init_atmu(struct fsl_pcie *pcie) +{ + fsl_pcie_setup_outbound_wins(pcie); + fsl_pcie_setup_inbound_wins(pcie); + + return 0; +} + +static int fsl_pcie_init_port(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val_32; + u16 val_16; + + fsl_pcie_init_atmu(pcie); + + if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) { + val_32 = 0; + fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); + val_32 &= ~0x03; + fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); + udelay(1); + } + + if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) { + u16 ltssm; + int i; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } else { + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + if (ltssm == 1) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(100); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && + !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } + } + } + + if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) && + !fsl_pcie_link_up(pcie)) { + serdes_corenet_t *srds_regs; + + srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + val_32 = in_be32(&srds_regs->srdspccr0); + + if ((val_32 >> 28) == 3) { + int i; + + out_be32(&srds_regs->srdspccr0, 2 << 28); + setbits_be32(®s->pdb_stat, 0x08000000); + in_be32(®s->pdb_stat); + udelay(100); + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } + } + + /* + * The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815)) + clrbits_be32(®s->dbi_ro_wr_en, 0x01); + + /* + * Enable All Error Interrupts except + * - Master abort (pci) + * - Master PERR (pci) + * - ICCA (PCIe) + */ + out_be32(®s->peer, ~0x20140); + + /* set URR, FER, NFER (but not CER) */ + fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32); + val_32 |= 0xf000e; + fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32); + + /* Clear all error indications */ + out_be32(®s->pme_msg_det, 0xffffffff); + out_be32(®s->pme_msg_int_en, 0xffffffff); + out_be32(®s->pedr, 0xffffffff); + + fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16); + if (val_16) + fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff); + + fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16); + if (val_16) + fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff); + + return 0; +} + +static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + + setbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + val &= 0xff; + val |= PCI_CLASS_BRIDGE_PCI << 16; + fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); + clrbits_be32(®s->dbi_ro_wr_en, 0x01); + + return 0; +} + +static int fsl_pcie_init_rc(struct fsl_pcie *pcie) +{ + return fsl_pcie_fixup_classcode(pcie); +} + +static int fsl_pcie_init_ep(struct fsl_pcie *pcie) +{ + fsl_pcie_config_ready(pcie); + + return 0; +} + +static int fsl_pcie_probe(struct udevice *dev) +{ + struct fsl_pcie *pcie = dev_get_priv(dev); + ccsr_fsl_pci_t *regs = pcie->regs; + u16 val_16; + + pcie->bus = dev; + pcie->block_rev = in_be32(®s->block_rev1); + + list_add(&pcie->list, &fsl_pcie_list); + pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx); + if (!pcie->enabled) { + printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + return 0; + } + + fsl_pcie_setup_law(pcie); + + pcie->mode = fsl_pcie_is_agent(pcie); + + fsl_pcie_init_port(pcie); + + printf("PCIe%d: %s ", pcie->idx, dev->name); + + if (pcie->mode) { + printf("Endpoint"); + fsl_pcie_init_ep(pcie); + } else { + printf("Root Complex"); + fsl_pcie_init_rc(pcie); + } + + if (!fsl_pcie_link_up(pcie)) { + printf(": %s\n", pcie->mode ? "undetermined link" : "no link"); + return 0; + } + + fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16); + printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf)); + + return 0; +} + +static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) +{ + struct fsl_pcie *pcie = dev_get_priv(dev); + int ret; + + pcie->regs = dev_remap_addr(dev); + if (!pcie->regs) { + pr_err("\"reg\" resource not found\n"); + return -EINVAL; + } + + ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if); + if (ret < 0) { + pr_err("\"law_trgt_if\" not found\n"); + return ret; + } + + pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + + return 0; +} + +static const struct dm_pci_ops fsl_pcie_ops = { + .read_config = fsl_pcie_read_config, + .write_config = fsl_pcie_write_config, +}; + +static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-t2080" }, + { } +}; + +U_BOOT_DRIVER(fsl_pcie) = { + .name = "fsl_pcie", + .id = UCLASS_PCI, + .of_match = fsl_pcie_ids, + .ops = &fsl_pcie_ops, + .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata, + .probe = fsl_pcie_probe, + .priv_auto_alloc_size = sizeof(struct fsl_pcie), +}; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h new file mode 100644 index 0000000000..5eefc31fa9 --- /dev/null +++ b/drivers/pci/pcie_fsl.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * + * PCIe DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + */ + +#ifndef _PCIE_FSL_H_ +#define _PCIE_FSL_H_ + +#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +#define FSL_PCIE_CAP_ID 0x70 +#else +#define FSL_PCIE_CAP_ID 0x4c +#endif +/* PCIe Device Control Register */ +#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08) +/* PCIe Device Status Register */ +#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a) +/* PCIe Link Control Register */ +#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10) +/* PCIe Link Status Register */ +#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12) + +#ifndef CONFIG_SYS_PCI_MEMORY_BUS +#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_PHYS +#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#endif + +#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) +#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#endif + +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define LTSSM_L0_REV3 0x11 +#define LTSSM_L0 0x16 + +struct fsl_pcie { + int idx; + struct udevice *bus; + void __iomem *regs; + u32 law_trgt_if; /* LAW target ID */ + u32 block_rev; /* IP block revision */ + bool mode; /* RC&EP mode flag */ + bool enabled; /* Enable status */ + struct list_head list; +}; + +extern struct list_head fsl_pcie_list; + +#endif /* _PCIE_FSL_H_ */ diff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c new file mode 100644 index 0000000000..cbdc0ef291 --- /dev/null +++ b/drivers/pci/pcie_fsl_fixup.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 NXP + * + * PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + */ + +#include <common.h> +#ifdef CONFIG_OF_BOARD_SETUP +#include <dm.h> +#include <fdt_support.h> +#include <asm/fsl_pci.h> +#include <linux/libfdt.h> +#include "pcie_fsl.h" + +static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie) +{ + struct pci_controller *hose = dev_get_uclass_priv(pcie->bus); + fdt_addr_t regs_addr; + int off; + + regs_addr = dev_read_addr(pcie->bus); + off = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT, regs_addr); + if (off < 0) { + printf("%s: Fail to find PCIe node@0x%pa\n", + FSL_PCIE_COMPAT, ®s_addr); + return; + } + + if (!hose || !pcie->enabled) + fdt_del_node(blob, off); + else + fdt_pci_dma_ranges(blob, off, hose); +} + +/* Fixup Kernel DT for PCIe */ +void pci_of_setup(void *blob, bd_t *bd) +{ + struct fsl_pcie *pcie; + + list_for_each_entry(pcie, &fsl_pcie_list, list) + ft_fsl_pcie_setup(blob, pcie); +} + +#else +void pci_of_setup(void *blob, bd_t *bd) +{ +} +#endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 04ddb32a8f..9469147152 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -322,6 +322,7 @@ endif # if DM_SPI config SOFT_SPI bool "Soft SPI driver" + depends on DM_SPI || (DEPRECATED && !DM_SPI) help Enable Soft SPI driver. This driver is to use GPIO simulate the SPI protocol. @@ -362,6 +363,7 @@ config DAVINCI_SPI config SH_SPI bool "SuperH SPI driver" + depends on DEPRECATED help Enable the SuperH SPI controller driver. This driver can be used on various SuperH SoCs, such as SH7757. @@ -380,6 +382,7 @@ config KIRKWOOD_SPI config LPC32XX_SSP bool "LPC32XX SPI Driver" + depends on DEPRECATED help Enable support for SPI on LPC32xx @@ -391,6 +394,7 @@ config MXC_SPI config MXS_SPI bool "MXS SPI Driver" + depends on DEPRECATED help Enable the MXS SPI controller driver. This driver can be used on the i.MX23 and i.MX28 SoCs. diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 494ab533cc..35f4147840 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -1039,8 +1039,10 @@ static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) int node = dev_of_offset(dev); ulong drvdata; void (*set_params)(struct dwc2_plat_otg_data *data); + int ret; - if (usb_get_dr_mode(node) != USB_DR_MODE_PERIPHERAL) { + if (usb_get_dr_mode(node) != USB_DR_MODE_PERIPHERAL && + usb_get_dr_mode(node) != USB_DR_MODE_OTG) { dev_dbg(dev, "Invalid mode\n"); return -ENODEV; } @@ -1050,7 +1052,18 @@ static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0); platdata->np_tx_fifo_sz = dev_read_u32_default(dev, "g-np-tx-fifo-size", 0); - platdata->tx_fifo_sz = dev_read_u32_default(dev, "g-tx-fifo-size", 0); + + platdata->tx_fifo_sz_nb = + dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32); + if (platdata->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS) + platdata->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS; + if (platdata->tx_fifo_sz_nb) { + ret = dev_read_u32_array(dev, "g-tx-fifo-size", + platdata->tx_fifo_sz_array, + platdata->tx_fifo_sz_nb); + if (ret) + return ret; + } platdata->force_b_session_valid = dev_read_bool(dev, "u-boot,force-b-session-valid"); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index dbafb74a34..ee0ddffe73 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -41,15 +41,6 @@ config OMAP_WATCHDOG help Say Y here to enable the OMAP3+ watchdog driver. -config TANGIER_WATCHDOG - bool "Intel Tangier watchdog" - depends on INTEL_MID - select HW_WATCHDOG - help - This enables support for watchdog controller available on - Intel Tangier SoC. If you're using a board with Intel Tangier - SoC, say Y here. - config ULP_WATCHDOG bool "i.MX7ULP watchdog" help @@ -170,4 +161,12 @@ config XILINX_TB_WATCHDOG Select this to enable Xilinx Axi watchdog timer, which can be found on some Xilinx Microblaze Platforms. +config WDT_TANGIER + bool "Intel Tangier watchdog timer support" + depends on WDT && INTEL_MID + help + This enables support for watchdog controller available on + Intel Tangier SoC. If you're using a board with Intel Tangier + SoC, say Y here. + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index e3f4fdb406..68c989aa0b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o -obj-$(CONFIG_TANGIER_WATCHDOG) += tangier_wdt.o obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o obj-$(CONFIG_WDT) += wdt-uclass.o obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o @@ -29,3 +28,4 @@ obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o +obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c index 523484b1ff..d344d54aee 100644 --- a/drivers/watchdog/ast_wdt.c +++ b/drivers/watchdog/ast_wdt.c @@ -23,6 +23,12 @@ static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags) ulong driver_data = dev_get_driver_data(dev); u32 reset_mode = ast_reset_mode_from_flags(flags); + /* 32 bits at 1MHz is 4294967ms */ + timeout = min_t(u64, timeout, 4294967); + + /* WDT counts in ticks of 1MHz clock. 1ms / 1e3 * 1e6 */ + timeout *= 1000; + clrsetbits_le32(&priv->regs->ctrl, WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT, reset_mode << WDT_CTRL_RESET_MODE_SHIFT); diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 0b501733f2..a7d4c7a3b8 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -70,18 +70,30 @@ static int mtk_wdt_expire_now(struct udevice *dev, ulong flags) return 0; } -static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout) +static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms) { struct mtk_wdt_priv *priv = dev_get_priv(dev); /* - * One bit is the value of 512 ticks - * The clock has 32 KHz + * One WDT_LENGTH count is 512 ticks of the wdt clock + * Clock runs at 32768 Hz + * e.g. 15.625 ms per count (nominal) + * We want the ceiling after dividing timeout_ms by 15.625 ms + * We add 15624 prior to the divide to implement the ceiling + * We prevent over-flow by clamping the timeout_ms value here + * as the maximum WDT_LENGTH counts is 1023 -> 15.984375 sec + * We also enforce a minimum of 1 count + * Many watchdog peripherals have a self-imposed count of 1 + * that is added to the register counts. + * The MediaTek docs lack details to know if this is the case here. + * So we enforce a minimum of 1 to guarantee operation. */ - timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY; - writel(timeout, priv->base + MTK_WDT_LENGTH); - - mtk_wdt_reset(dev); + if(timeout_ms > 15984) timeout_ms = 15984; + u64 timeout_us = timeout_ms * 1000; + u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 ); + if(timeout_cc == 0) timeout_cc = 1; + u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY; + writel(length, priv->base + MTK_WDT_LENGTH); } static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags) @@ -90,6 +102,8 @@ static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags) mtk_wdt_set_timeout(dev, timeout); + mtk_wdt_reset(dev); + /* Enable watchdog reset signal */ setbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN); diff --git a/drivers/watchdog/tangier_wdt.c b/drivers/watchdog/tangier_wdt.c index be4a8f467a..ba265cf223 100644 --- a/drivers/watchdog/tangier_wdt.c +++ b/drivers/watchdog/tangier_wdt.c @@ -3,20 +3,21 @@ * Copyright (c) 2017 Intel Corporation */ #include <common.h> -#include <watchdog.h> +#include <dm.h> +#include <wdt.h> +#include <div64.h> #include <asm/scu.h> /* Hardware timeout in seconds */ #define WDT_PRETIMEOUT 15 #define WDT_TIMEOUT_MIN (1 + WDT_PRETIMEOUT) #define WDT_TIMEOUT_MAX 170 -#define WDT_DEFAULT_TIMEOUT 90 -#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS -#define WATCHDOG_HEARTBEAT 60000 -#else -#define WATCHDOG_HEARTBEAT CONFIG_WATCHDOG_TIMEOUT_MSECS -#endif +/* + * Note, firmware chooses 90 seconds as a default timeout for watchdog on + * Intel Tangier SoC. It means that without handling it in the running code + * the reboot will happen. + */ enum { SCU_WATCHDOG_START = 0, @@ -25,39 +26,33 @@ enum { SCU_WATCHDOG_SET_ACTION_ON_TIMEOUT = 3, }; -void hw_watchdog_reset(void) +static int tangier_wdt_reset(struct udevice *dev) { - static unsigned long last; - unsigned long now; - - if (gd->timer) - now = timer_get_us(); - else - now = rdtsc() / 1000; - - /* Do not flood SCU */ - if (last > now) - last = 0; - - if (unlikely((now - last) > (WDT_PRETIMEOUT / 2) * 1000000)) { - last = now; - scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_KEEPALIVE); - } + scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_KEEPALIVE); + return 0; } -int hw_watchdog_disable(void) +static int tangier_wdt_stop(struct udevice *dev) { return scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_STOP); } -void hw_watchdog_init(void) +static int tangier_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { - u32 timeout = WATCHDOG_HEARTBEAT / 1000; + u32 timeout_sec; int in_size; struct ipc_wd_start { u32 pretimeout; u32 timeout; - } ipc_wd_start = { timeout - WDT_PRETIMEOUT, timeout }; + } ipc_wd_start; + + /* Calculate timeout in seconds and restrict to min and max value */ + do_div(timeout_ms, 1000); + timeout_sec = clamp_t(u32, timeout_ms, WDT_TIMEOUT_MIN, WDT_TIMEOUT_MAX); + + /* Update values in the IPC request */ + ipc_wd_start.pretimeout = timeout_sec - WDT_PRETIMEOUT; + ipc_wd_start.timeout = timeout_sec; /* * SCU expects the input size for watchdog IPC @@ -67,4 +62,31 @@ void hw_watchdog_init(void) scu_ipc_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_START, (u32 *)&ipc_wd_start, in_size, NULL, 0); + + return 0; } + +static const struct wdt_ops tangier_wdt_ops = { + .reset = tangier_wdt_reset, + .start = tangier_wdt_start, + .stop = tangier_wdt_stop, +}; + +static const struct udevice_id tangier_wdt_ids[] = { + { .compatible = "intel,tangier-wdt" }, + { /* sentinel */ } +}; + +static int tangier_wdt_probe(struct udevice *dev) +{ + debug("%s: Probing wdt%u\n", __func__, dev->seq); + return 0; +} + +U_BOOT_DRIVER(wdt_tangier) = { + .name = "wdt_tangier", + .id = UCLASS_WDT, + .of_match = tangier_wdt_ids, + .ops = &tangier_wdt_ops, + .probe = tangier_wdt_probe, +}; diff --git a/env/Kconfig b/env/Kconfig index 5651685c15..b9439171fd 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -287,7 +287,7 @@ config ENV_IS_IN_REMOTE config ENV_IS_IN_SPI_FLASH bool "Environment is in SPI flash" - depends on !CHAIN_OF_TRUST + depends on !CHAIN_OF_TRUST && SPI default y if ARMADA_XP default y if INTEL_BAYTRAIL default y if INTEL_BRASWELL @@ -17,6 +17,7 @@ #include <asm/io.h> #include <div64.h> #include <linux/math64.h> +#include <efi_loader.h> DECLARE_GLOBAL_DATA_PTR; @@ -700,6 +701,10 @@ int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], else pos = 0; +#ifdef CONFIG_CMD_BOOTEFI + efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "", + (argc > 4) ? argv[4] : ""); +#endif time = get_timer(0); ret = _fs_read(filename, addr, pos, bytes, 1, &len_read); time = get_timer(time); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 4993303f4d..26e61ef196 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -229,10 +229,23 @@ #endif #ifdef CONFIG_IDE -#define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide) +#define BOOTENV_RUN_IDE_INIT "run ide_init; " +#define BOOTENV_SET_IDE_NEED_INIT "setenv ide_need_init; " +#define BOOTENV_SHARED_IDE \ + "ide_init=" \ + "if ${ide_need_init}; then " \ + "setenv ide_need_init false; " \ + "ide reset; " \ + "fi\0" \ + \ + "ide_boot=" \ + BOOTENV_RUN_IDE_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(ide) #define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV #else +#define BOOTENV_RUN_IDE_INIT +#define BOOTENV_SET_IDE_NEED_INIT #define BOOTENV_SHARED_IDE #define BOOTENV_DEV_IDE \ BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE @@ -451,6 +464,7 @@ \ "distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ BOOTENV_SET_NVME_NEED_INIT \ + BOOTENV_SET_IDE_NEED_INIT \ "for target in ${boot_targets}; do " \ "run bootcmd_${target}; " \ "done\0" diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 1537b45cc1..1c615acb3b 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -57,7 +57,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index e9371a025b..5a1a29bd9e 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -66,7 +66,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 819129033f..7697e8d3e0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,7 +36,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 280b873aee..2cbe855235 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -16,7 +16,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index be600becfe..b37601c794 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -20,7 +20,6 @@ #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 5515b9232c..01ee69c013 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -16,7 +16,6 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3c6661fc83..de187bf9a4 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -15,7 +15,6 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 13fbbb3044..e3952f423b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,7 +27,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 025aa33083..1152bca03b 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -115,7 +115,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 62943a3b0c..4b2eb6525b 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -81,7 +81,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 7fe34c332e..9535a7bbb2 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -24,7 +24,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #ifndef __ASSEMBLY__ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb3342b9..54ec1abd66 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -491,50 +491,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4b53e19fd4..ab92ca3b68 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -476,7 +476,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index b518c222d4..268a41c82c 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * based on include/configs/p1_p2_rdb_pc.h * original copyright follows: * Copyright 2009-2011 Freescale Semiconductor, Inc. @@ -13,11 +13,66 @@ #ifndef __CONFIG_H #define __CONFIG_H +/*** Arcturus FirmWare Environment */ + +#define MAX_SERIAL_SIZE 15 +#define MAX_HWADDR_SIZE 17 + +#define MAX_FWENV_ADDR 4 + +#define FWENV_MMC 1 +#define FWENV_SPI_FLASH 2 +#define FWENV_NOR_FLASH 3 +/* + #define FWENV_TYPE FWENV_MMC + #define FWENV_TYPE FWENV_SPI_FLASH +*/ +#define FWENV_TYPE FWENV_NOR_FLASH + +#if (FWENV_TYPE == FWENV_MMC) +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 +#endif +#define FWENV_ADDR1 -1 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0 +#endif + +#if (FWENV_TYPE == FWENV_SPI_FLASH) +#ifndef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +#define FWENV_ADDR1 (0x200 - sizeof(smac)) +#define FWENV_ADDR2 (0x400 - sizeof(smac)) +#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) +#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) +#define EMPY_CHAR 0xff +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) +#define FWENV_ADDR1 0xEC080000 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0xff +#endif +/***********************************/ + #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #if defined(CONFIG_TARTGET_UCP1020T1) @@ -38,8 +93,6 @@ #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_ETHPRIME "eTSEC3" -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -52,7 +105,6 @@ #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" #define CONFIG_TSEC1 -#define CONFIG_TSEC2 #define CONFIG_TSEC3 #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 @@ -68,7 +120,7 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_ETHPRIME "eTSEC1" -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#undef CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SYS_L2_SIZE (256 << 10) diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index f1c3522c68..19223e2947 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -204,7 +204,6 @@ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 5581cfd1c9..dd2a679b79 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -43,7 +43,6 @@ #define CONFIG_FSL_SPI_INTERFACE #define CONFIG_SF_DATAFLASH -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define CONFIG_SPI_FLASH_SPANSION diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 0db86396e9..d3d787f14d 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -197,4 +197,8 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + #endif /* __L1028A_COMMON_H */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 34b4756ed8..59c43f1ae1 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP */ #ifndef __LS1046A_COMMON_H @@ -202,6 +203,15 @@ #include <config_distro_bootcmd.h> #endif +#if defined(CONFIG_TARGET_LS1046AFRWY) +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046afrwy_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" +#else +#define LS1046A_BOOT_SRC_AND_HDR\ + "boot_scripts=ls1046ardb_boot.scr\0" \ + "boot_script_hdr=hdr_ls1046ardb_bs.out\0" +#endif #ifndef SPL_NO_MISC /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -232,8 +242,7 @@ "console=ttyS0,115200\0" \ CONFIG_MTDPARTS_DEFAULT "\0" \ BOOTENV \ - "boot_scripts=ls1046ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \ + LS1046A_BOOT_SRC_AND_HDR \ "scan_dev_for_boot_part=" \ "part list ${devtype} ${devnum} devplist; " \ "env exists devplist || setenv devplist 1; " \ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h new file mode 100644 index 0000000000..791bb8dc47 --- /dev/null +++ b/include/configs/ls1046afrwy.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __LS1046AFRWY_H__ +#define __LS1046AFRWY_H__ + +#include "ls1046a_common.h" + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define CONFIG_LAYERSCAPE_NS_ACCESS + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_UBOOT_BASE 0x40100000 + +/* IFC */ +#define CONFIG_FSL_IFC +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* IFC Timing Params */ +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#define I2C_RETIMER_ADDR 0x18 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/ +#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ + +/* FMan */ +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET + +#define QSGMII_PORT1_PHY_ADDR 0x1c +#define QSGMII_PORT2_PHY_ADDR 0x1d +#define QSGMII_PORT3_PHY_ADDR 0x1e +#define QSGMII_PORT4_PHY_ADDR 0x1f + +#define FDT_SEQ_MACADDR_FROM_ENV + +#define CONFIG_ETHPRIME "FM1@DTSEC3" + +#endif + +/* QSPI device */ +#ifdef CONFIG_FSL_QSPI +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define FSL_QSPI_FLASH_NUM 1 +#endif + +#undef CONFIG_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#include <asm/fsl_secure_boot.h> + +#endif /* __LS1046AFRWY_H__ */ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 831767235e..2d20f15683 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor + * Copyright 2019 NXP */ #ifndef __LS1046ARDB_H__ @@ -162,6 +163,8 @@ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET #else #if defined(CONFIG_SD_BOOT) #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 74c7dc4f8a..18f30b585c 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -368,9 +368,9 @@ unsigned long get_board_ddr_clk(void); #else #ifdef CONFIG_TFABOOT #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" @@ -378,8 +378,8 @@ unsigned long get_board_ddr_clk(void); "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "loadaddr_sd=0x90100000\0" \ - "kernel_addr=0x100000\0" \ - "kernel_addr_sd=0x800\0" \ + "kernel_addr=0x581000000\0" \ + "kernel_addr_sd=0x8000\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ @@ -389,9 +389,23 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ - "mcinitcmd=fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" \ - "mcmemsize=0x70000000 \0" + "load_addr=0xa0000000\0" \ + "kernelheader_addr=0x580800000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_size=0x40000\0" \ + "BOARD=ls2088aqds\0" \ + "mcmemsize=0x70000000 \0" \ + IFC_MC_INIT_CMD \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size ; env exists secureboot && " \ + "cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "bootm $load_addr#$BOARD\0" #elif defined(CONFIG_SD_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -426,6 +440,25 @@ unsigned long get_board_ddr_clk(void); #endif /* CONFIG_TFABOOT */ #endif /* CONFIG_SECURE_BOOT */ +#ifdef CONFIG_TFABOOT +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ + "&& esbc_validate $load_addr; " \ + "env exists mcinitcmd && run mcinitcmd " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ + "run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#define IFC_NOR_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x580780000; env exists mcinitcmd "\ + "&& fsl_mc lazyapply dpl 0x580d00000;" \ + "run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif + #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) #define CONFIG_FSL_MEMAC #define CONFIG_PHYLIB_10G diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 2e8a8bbdb7..bfb54be79b 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -342,14 +342,14 @@ unsigned long get_board_sys_clk(void); "esbc_validate 0x20740000;" \ "fsl_mc start mc 0x20a00000 0x20e00000 \0" #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ "env exists secureboot && " \ "mmc read 0x80700000 0x3800 0x10 && " \ "mmc read 0x80740000 0x3A00 0x10 && " \ "esbc_validate 0x80700000 && " \ "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "env exists secureboot && " \ "esbc_validate 0x580700000 && " \ @@ -528,8 +528,8 @@ unsigned long get_board_sys_clk(void); "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ "&& esbc_validate $load_addr; " \ "env exists mcinitcmd && run mcinitcmd " \ - "&& mmc read 0x88000000 0x6800 0x800 " \ - "&& fsl_mc lazyapply dpl 0x88000000; " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ "run distro_bootcmd;run sd_bootcmd; " \ "env exists secureboot && esbc_halt;" diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index eb0b1766aa..711b434baf 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -246,12 +246,6 @@ unsigned long get_board_ddr_clk(void); "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d9312bd149..e07d2a178f 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -209,7 +209,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index e42b9b0cb9..1e0708a71b 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -34,7 +34,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a..2a81c803b6 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 9df8604af7..ba613672eb 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif #ifdef CONFIG_PCIE1 -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #endif #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index 1f29e3d221..c90d8e0e9a 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -63,7 +63,6 @@ #define CONFIG_SH_MMCIF_CLK 48000000 /* ENV setting */ -#define CONFIG_ENV_IS_EMBEDDED #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_ADDR (0x00080000) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index 0693fb5a3c..83d123f33a 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -63,7 +63,6 @@ #define CONFIG_SH_MMCIF_CLK 48000000 /* ENV setting */ -#define CONFIG_ENV_IS_EMBEDDED #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_ADDR (0x00080000) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 05b2f01c15..f92f066494 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -75,7 +75,6 @@ #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) /* ENV setting */ -#define CONFIG_ENV_IS_EMBEDDED #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_ADDR (0x00080000) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 22dd3c036e..0a87f226f8 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -22,7 +22,6 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ /* * Multicore config diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index a7c8dc4e33..0389874609 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -22,7 +22,6 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ /* * Multicore config diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h deleted file mode 100644 index 24fea68a11..0000000000 --- a/include/configs/zipitz2.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Aeronix Zipit Z2 configuration file - * - * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ - -#undef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_PREBOOT - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_SYS_MALLOC_LEN (128*1024) -#define CONFIG_ARCH_CPU_INIT - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ - "then " \ - "source 0xa0000000; " \ - "else " \ - "bootm 0x50000; " \ - "fi; " -#define CONFIG_TIMESTAMP -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * Serial Console Configuration - * STUART - the lower serial port on Colibri board - */ -#define CONFIG_STUART 1 - -/* - * Bootloader Components Configuration - */ - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_PXA_MMC_GENERIC -#define CONFIG_SYS_MMC_BASE 0xF0000000 -#endif - -/* - * SPI and LCD - */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_SOFT_SPI -#define CONFIG_LCD_ROTATION -#define CONFIG_PXA_LCD -#define CONFIG_LMS283GF05 - -#define SPI_DELAY udelay(10) -#define SPI_SDA(val) zipitz2_spi_sda(val) -#define SPI_SCL(val) zipitz2_spi_scl(val) -#define SPI_READ zipitz2_spi_read() -#ifndef __ASSEMBLY__ -void zipitz2_spi_sda(int); -void zipitz2_spi_scl(int); -unsigned char zipitz2_spi_read(void); -#endif -#endif - -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ - -/* - * SRAM Map - */ -#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ -#define PHYS_SRAM_SIZE 0x00040000 /* 256k */ - -/* - * DRAM Map - */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) - -/* - * NOR FLASH - */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ -#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 240000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 240000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GAFR0_L_VAL 0x02000140 -#define CONFIG_SYS_GAFR0_U_VAL 0x59188000 -#define CONFIG_SYS_GAFR1_L_VAL 0x63900002 -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 -#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x29000308 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000000 -#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000020 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 -#define CONFIG_SYS_GPDR0_VAL 0xdafcee00 -#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab -#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff -#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a -#define CONFIG_SYS_GPSR0_VAL 0x06080400 -#define CONFIG_SYS_GPSR1_VAL 0x007f0000 -#define CONFIG_SYS_GPSR2_VAL 0x032a0000 -#define CONFIG_SYS_GPSR3_VAL 0x00000180 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00511220 -#define CONFIG_SYS_CCCR 0x00000190 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 -#define CONFIG_SYS_MSC1_VAL 0x0000ccd1 -#define CONFIG_SYS_MSC2_VAL 0x0000b884 -#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 -#define CONFIG_SYS_MDREFR_VAL 0x2011a01e -#define CONFIG_SYS_MDMRS_VAL 0x00000000 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000001 -#define CONFIG_SYS_MCMEM0_VAL 0x00014307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x0001c787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0001430f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -#include "pxa-common.h" - -#endif /* __CONFIG_H */ diff --git a/include/efi_api.h b/include/efi_api.h index d7d95edd4d..4de5d208f5 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -577,7 +577,9 @@ struct simple_text_output_mode { #define EFI_ATTR_BG(attr) (((attr) >> 4) & 0x7) struct efi_simple_text_output_protocol { - void *reset; + efi_status_t (EFIAPI *reset)( + struct efi_simple_text_output_protocol *this, + char extended_verification); efi_status_t (EFIAPI *output_string)( struct efi_simple_text_output_protocol *this, const efi_string_t str); diff --git a/include/fb_mmc.h b/include/fb_mmc.h index fd5db9eac8..95db001bee 100644 --- a/include/fb_mmc.h +++ b/include/fb_mmc.h @@ -14,7 +14,8 @@ * @part_info: Pointer to returned disk_partition_t * @response: Pointer to fastboot response buffer */ -int fastboot_mmc_get_part_info(char *part_name, struct blk_desc **dev_desc, +int fastboot_mmc_get_part_info(const char *part_name, + struct blk_desc **dev_desc, disk_partition_t *part_info, char *response); /** diff --git a/include/fb_nand.h b/include/fb_nand.h index 08ab0e28a6..6d7999f262 100644 --- a/include/fb_nand.h +++ b/include/fb_nand.h @@ -16,8 +16,8 @@ * @part_info: Pointer to returned part_info pointer * @response: Pointer to fastboot response buffer */ -int fastboot_nand_get_part_info(char *part_name, struct part_info **part_info, - char *response); +int fastboot_nand_get_part_info(const char *part_name, + struct part_info **part_info, char *response); /** * fastboot_nand_flash_write() - Write image to NAND for fastboot diff --git a/include/fm_eth.h b/include/fm_eth.h index 2e2ba756a0..729ad63cd5 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2019 NXP */ #ifndef __FM_ETH_H__ @@ -41,8 +42,19 @@ enum fm_eth_type { FM_ETH_10G_E, }; +/* Historically, on FMan v3 platforms, the first MDIO bus has been used for + * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the + * TGEC name). + * + * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus, + * and no TGEC ports are present on-board. + */ #ifdef CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_TARGET_LS1046AFRWY +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#else #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) +#endif #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) #if (CONFIG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) diff --git a/lib/Makefile b/lib/Makefile index 09c45b8122..2fffd68f94 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -88,7 +88,7 @@ obj-y += crc32.o obj-$(CONFIG_CRC32C) += crc32c.o obj-y += ctype.o obj-y += div64.o -obj-$(CONFIG_OF_LIBFDT) += fdtdec.o +obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdtdec.o fdtdec_common.o obj-y += hang.o obj-y += linux_compat.o obj-y += linux_string.o diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index b26291b919..d104cc6b31 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -3620,11 +3620,11 @@ struct efi_system_table __efi_runtime_data systab = { }, .fw_vendor = firmware_vendor, .fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8, - .con_in = (void *)&efi_con_in, - .con_out = (void *)&efi_con_out, - .std_err = (void *)&efi_con_out, - .runtime = (void *)&efi_runtime_services, - .boottime = (void *)&efi_boot_services, + .con_in = &efi_con_in, + .con_out = &efi_con_out, + .std_err = &efi_con_out, + .runtime = &efi_runtime_services, + .boottime = &efi_boot_services, .nr_tables = 0, .tables = NULL, }; diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 706e6ad31e..6c8229da42 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -481,10 +481,8 @@ void set_shift_mask(int mod, struct efi_key_state *key_state) key_state->key_shift_state |= EFI_LEFT_ALT_PRESSED; if (mod & 4) key_state->key_shift_state |= EFI_LEFT_CONTROL_PRESSED; - if (mod & 8) + if (!mod || (mod & 8)) key_state->key_shift_state |= EFI_LEFT_LOGO_PRESSED; - } else { - key_state->key_shift_state |= EFI_LEFT_LOGO_PRESSED; } } @@ -563,10 +561,13 @@ static efi_status_t efi_cin_read_key(struct efi_key_data *key) case cESC: /* ESC */ pressed_key.scan_code = 23; break; - case 'O': /* F1 - F4 */ + case 'O': /* F1 - F4, End */ ch = getc(); /* consider modifiers */ - if (ch < 'P') { + if (ch == 'F') { /* End */ + pressed_key.scan_code = 6; + break; + } else if (ch < 'P') { set_shift_mask(ch - '0', &key->key_state); ch = getc(); } @@ -590,17 +591,20 @@ static efi_status_t efi_cin_read_key(struct efi_key_data *key) case '1'...'5': /* F1 - F5 */ pressed_key.scan_code = ch - '1' + 11; break; - case '7'...'9': /* F6 - F8 */ - pressed_key.scan_code = ch - '7' + 16; + case '6'...'9': /* F5 - F8 */ + pressed_key.scan_code = ch - '6' + 15; break; case 'A'...'D': /* up, down right, left */ pressed_key.scan_code = ch - 'A' + 1; break; - case 'F': - pressed_key.scan_code = 6; /* End */ + case 'F': /* End */ + pressed_key.scan_code = 6; + break; + case 'H': /* Home */ + pressed_key.scan_code = 5; break; - case 'H': - pressed_key.scan_code = 5; /* Home */ + case '~': /* Home */ + pressed_key.scan_code = 5; break; } break; diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 182d735e6b..36ca719a82 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -307,16 +307,10 @@ static efi_status_t EFIAPI efi_file_delete(struct efi_file_handle *file) EFI_ENTRY("%p", file); - if (set_blk_dev(fh)) { - ret = EFI_DEVICE_ERROR; - goto error; - } + if (set_blk_dev(fh) || fs_unlink(fh->path)) + ret = EFI_WARN_DELETE_FAILURE; - if (fs_unlink(fh->path)) - ret = EFI_DEVICE_ERROR; file_close(fh); - -error: return EFI_EXIT(ret); } diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index e003823b60..cad509bfea 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -41,24 +41,25 @@ static efi_status_t EFIAPI gop_query_mode(struct efi_gop *this, u32 mode_number, struct efi_gop_mode_info **info) { struct efi_gop_obj *gopobj; + efi_status_t ret = EFI_SUCCESS; EFI_ENTRY("%p, %x, %p, %p", this, mode_number, size_of_info, info); + if (!this || !size_of_info || !info || mode_number) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + gopobj = container_of(this, struct efi_gop_obj, ops); + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, sizeof(gopobj->info), + (void **)info); + if (ret != EFI_SUCCESS) + goto out; *size_of_info = sizeof(gopobj->info); - *info = &gopobj->info; - - return EFI_EXIT(EFI_SUCCESS); -} - -static efi_status_t EFIAPI gop_set_mode(struct efi_gop *this, u32 mode_number) -{ - EFI_ENTRY("%p, %x", this, mode_number); - - if (mode_number != 0) - return EFI_EXIT(EFI_INVALID_PARAMETER); + memcpy(*info, &gopobj->info, sizeof(gopobj->info)); - return EFI_EXIT(EFI_SUCCESS); +out: + return EFI_EXIT(ret); } static __always_inline struct efi_gop_pixel efi_vid16_to_blt_col(u16 vid) @@ -309,6 +310,44 @@ static efi_status_t gop_blt_vid_to_buf(struct efi_gop *this, dx, dy, width, height, delta, vid_bpp); } +/** + * gop_set_mode() - set graphical output mode + * + * This function implements the SetMode() service. + * + * See the Unified Extensible Firmware Interface (UEFI) specification for + * details. + * + * @this: the graphical output protocol + * @model_number: the mode to be set + * Return: status code + */ +static efi_status_t EFIAPI gop_set_mode(struct efi_gop *this, u32 mode_number) +{ + struct efi_gop_obj *gopobj; + struct efi_gop_pixel buffer = {0, 0, 0, 0}; + efi_uintn_t vid_bpp; + efi_status_t ret = EFI_SUCCESS; + + EFI_ENTRY("%p, %x", this, mode_number); + + if (!this) { + ret = EFI_INVALID_PARAMETER; + goto out; + } + if (mode_number) { + ret = EFI_UNSUPPORTED; + goto out; + } + gopobj = container_of(this, struct efi_gop_obj, ops); + vid_bpp = gop_get_bpp(this); + ret = gop_blt_video_fill(this, &buffer, EFI_BLT_VIDEO_FILL, 0, 0, 0, 0, + gopobj->info.width, gopobj->info.height, 0, + vid_bpp); +out: + return EFI_EXIT(ret); +} + /* * Copy rectangle. * @@ -367,7 +406,7 @@ efi_status_t EFIAPI gop_blt(struct efi_gop *this, struct efi_gop_pixel *buffer, dy, width, height, delta, vid_bpp); break; default: - ret = EFI_UNSUPPORTED; + ret = EFI_INVALID_PARAMETER; } if (ret != EFI_SUCCESS) @@ -464,26 +503,26 @@ efi_status_t efi_gop_register(void) gopobj->mode.info = &gopobj->info; gopobj->mode.info_size = sizeof(gopobj->info); + gopobj->mode.fb_base = fb_base; + gopobj->mode.fb_size = fb_size; + + gopobj->info.version = 0; + gopobj->info.width = col; + gopobj->info.height = row; #ifdef CONFIG_DM_VIDEO if (bpix == VIDEO_BPP32) #else if (bpix == LCD_COLOR32) #endif { - /* - * With 32bit color space we can directly expose the frame - * buffer - */ - gopobj->mode.fb_base = fb_base; - gopobj->mode.fb_size = fb_size; + gopobj->info.pixel_format = EFI_GOT_BGRA8; + } else { + gopobj->info.pixel_format = EFI_GOT_BITMASK; + gopobj->info.pixel_bitmask[0] = 0xf800; /* red */ + gopobj->info.pixel_bitmask[1] = 0x07e0; /* green */ + gopobj->info.pixel_bitmask[2] = 0x001f; /* blue */ } - - gopobj->info.version = 0; - gopobj->info.width = col; - gopobj->info.height = row; - gopobj->info.pixel_format = EFI_GOT_BGRA8; gopobj->info.pixels_per_scanline = col; - gopobj->bpix = bpix; gopobj->fb = fb; diff --git a/lib/efi_loader/efi_hii.c b/lib/efi_loader/efi_hii.c index 61b71dec62..77e330285a 100644 --- a/lib/efi_loader/efi_hii.c +++ b/lib/efi_loader/efi_hii.c @@ -581,18 +581,22 @@ list_package_lists(const struct efi_hii_database_protocol *this, struct efi_hii_packagelist *hii = (struct efi_hii_packagelist *)handle; int package_cnt, package_max; - efi_status_t ret = EFI_SUCCESS; + efi_status_t ret = EFI_NOT_FOUND; EFI_ENTRY("%p, %u, %pUl, %p, %p", this, package_type, package_guid, handle_buffer_length, handle); if (!handle_buffer_length || - (*handle_buffer_length && !handle)) - return EFI_EXIT(EFI_INVALID_PARAMETER); + (*handle_buffer_length && !handle)) { + ret = EFI_INVALID_PARAMETER; + goto out; + } if ((package_type != EFI_HII_PACKAGE_TYPE_GUID && package_guid) || - (package_type == EFI_HII_PACKAGE_TYPE_GUID && !package_guid)) - return EFI_EXIT(EFI_INVALID_PARAMETER); + (package_type == EFI_HII_PACKAGE_TYPE_GUID && !package_guid)) { + ret = EFI_INVALID_PARAMETER; + goto out; + } EFI_PRINT("package type=%x, guid=%pUl, length=%zu\n", (int)package_type, package_guid, *handle_buffer_length); @@ -607,53 +611,28 @@ list_package_lists(const struct efi_hii_database_protocol *this, if (!list_empty(&hii->guid_list)) break; continue; - case EFI_HII_PACKAGE_FORMS: - EFI_PRINT("Form package not supported\n"); - ret = EFI_INVALID_PARAMETER; - continue; case EFI_HII_PACKAGE_STRINGS: if (!list_empty(&hii->string_tables)) break; continue; - case EFI_HII_PACKAGE_FONTS: - EFI_PRINT("Font package not supported\n"); - ret = EFI_INVALID_PARAMETER; - continue; - case EFI_HII_PACKAGE_IMAGES: - EFI_PRINT("Image package not supported\n"); - ret = EFI_INVALID_PARAMETER; - continue; - case EFI_HII_PACKAGE_SIMPLE_FONTS: - EFI_PRINT("Simple font package not supported\n"); - ret = EFI_INVALID_PARAMETER; - continue; - case EFI_HII_PACKAGE_DEVICE_PATH: - EFI_PRINT("Device path package not supported\n"); - ret = EFI_INVALID_PARAMETER; - continue; case EFI_HII_PACKAGE_KEYBOARD_LAYOUT: if (!list_empty(&hii->keyboard_packages)) break; continue; - case EFI_HII_PACKAGE_ANIMATIONS: - EFI_PRINT("Animation package not supported\n"); - ret = EFI_INVALID_PARAMETER; - continue; - case EFI_HII_PACKAGE_END: - case EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN: - case EFI_HII_PACKAGE_TYPE_SYSTEM_END: default: continue; } package_cnt++; - if (package_cnt <= package_max) + if (package_cnt <= package_max) { *handle++ = hii; - else + ret = EFI_SUCCESS; + } else { ret = EFI_BUFFER_TOO_SMALL; + } } *handle_buffer_length = package_cnt * sizeof(*handle); - +out: return EFI_EXIT(ret); } diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 1d1b23b0e5..d6b75ca02e 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -148,7 +148,7 @@ static const char *parse_attr(const char *str, u32 *attrp) } /** - * efi_efi_get_variable() - retrieve value of a UEFI variable + * efi_get_variable() - retrieve value of a UEFI variable * * This function implements the GetVariable runtime service. * @@ -404,7 +404,7 @@ efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t *variable_name_size, } /** - * efi_efi_set_variable() - set value of a UEFI variable + * efi_set_variable() - set value of a UEFI variable * * This function implements the SetVariable runtime service. * diff --git a/lib/efi_selftest/efi_selftest_gop.c b/lib/efi_selftest/efi_selftest_gop.c index 4ad043c597..d64294ac79 100644 --- a/lib/efi_selftest/efi_selftest_gop.c +++ b/lib/efi_selftest/efi_selftest_gop.c @@ -80,6 +80,11 @@ static int execute(void) } efi_st_printf("Mode %u: %u x %u\n", i, info->width, info->height); + ret = boottime->free_pool(info); + if (ret != EFI_SUCCESS) { + efi_st_printf("FreePool failed"); + return EFI_ST_FAILURE; + } } return EFI_ST_SUCCESS; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 22de7a4b6c..d252045d80 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,6 +1,5 @@ CONFIG_16BIT CONFIG_33 -CONFIG_400MHZ_MODE CONFIG_64BIT_PHYS_ADDR CONFIG_66 CONFIG_8349_CLKIN @@ -238,9 +237,7 @@ CONFIG_CONS_ON_SCC CONFIG_CONS_SCIF0 CONFIG_CONS_SCIF1 CONFIG_CONS_SCIF2 -CONFIG_CONS_SCIF3 CONFIG_CONS_SCIF4 -CONFIG_CONS_SCIF5 CONFIG_CONTROL CONFIG_CONTROLCENTERD CONFIG_CON_ROT @@ -268,9 +265,6 @@ CONFIG_CPU_PXA27X CONFIG_CPU_PXA300 CONFIG_CPU_R8000 CONFIG_CPU_SH7722 -CONFIG_CPU_SH7723 -CONFIG_CPU_SH7734 -CONFIG_CPU_SH7750 CONFIG_CPU_SH7751 CONFIG_CPU_SH7752 CONFIG_CPU_SH7753 @@ -372,7 +366,6 @@ CONFIG_DRIVER_NE2000_BASE CONFIG_DRIVER_NE2000_CCR CONFIG_DRIVER_NE2000_VAL CONFIG_DRIVER_SMC911X_BASE -CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE CONFIG_DRIVER_TI_EMAC_USE_RMII CONFIG_DSP_CLUSTER_START CONFIG_DUOVERO @@ -614,8 +607,6 @@ CONFIG_FSL_LBC CONFIG_FSL_MC9SDZ60 CONFIG_FSL_MEMAC CONFIG_FSL_NGPIXIS -CONFIG_FSL_PCIE_DISABLE_ASPM -CONFIG_FSL_PCIE_RESET CONFIG_FSL_PCI_INIT CONFIG_FSL_PIXIS CONFIG_FSL_PMIC_BITLEN @@ -685,7 +676,6 @@ CONFIG_GICV2 CONFIG_GLOBAL_DATA_NOT_REG10 CONFIG_GLOBAL_TIMER CONFIG_GMII -CONFIG_GOOD_SESH4 CONFIG_GPCNTRL CONFIG_GPIO_ENABLE_SPI_FLASH CONFIG_GPIO_LED_INVERTED_TABLE @@ -923,9 +913,6 @@ CONFIG_IO_TRACE CONFIG_IPADDR CONFIG_IPADDR1 CONFIG_IPADDR2 -CONFIG_IPAM390_GPIO_BOOTMODE -CONFIG_IPAM390_GPIO_LED_GREEN -CONFIG_IPAM390_GPIO_LED_RED CONFIG_IPROC CONFIG_IRAM_BASE CONFIG_IRAM_END @@ -1072,7 +1059,6 @@ CONFIG_LCD_INFO_BELOW_LOGO CONFIG_LCD_IN_PSRAM CONFIG_LCD_LOGO CONFIG_LCD_MENU -CONFIG_LCD_ROTATION CONFIG_LD9040 CONFIG_LEGACY CONFIG_LEGACY_BOOTCMD_ENV @@ -1135,7 +1121,6 @@ CONFIG_MACRESET_TIMEOUT CONFIG_MALLOC_F_ADDR CONFIG_MALTA CONFIG_MARCO_MEMSET -CONFIG_MARUBUN_PCCARD CONFIG_MARVELL_GPIO CONFIG_MARVELL_MFP CONFIG_MASK_AER_AO @@ -1601,7 +1586,6 @@ CONFIG_SATA1 CONFIG_SATA2 CONFIG_SATA_ULI5288 CONFIG_SCF0403_LCD -CONFIG_SCIF CONFIG_SCIF_A CONFIG_SCIF_USE_EXT_CLK CONFIG_SCSI_AHCI_PLAT @@ -1701,7 +1685,6 @@ CONFIG_SMSTP7_ENA CONFIG_SMSTP8_ENA CONFIG_SMSTP9_ENA CONFIG_SOCRATES -CONFIG_SOC_DM644X CONFIG_SOC_K2E CONFIG_SOC_K2G CONFIG_SOC_K2HK @@ -1858,7 +1841,6 @@ CONFIG_STRIDER_CON_DP CONFIG_STRIDER_CPU CONFIG_STRIDER_CPU_DP CONFIG_STRIDER_FANS -CONFIG_STUART CONFIG_STV0991 CONFIG_STV0991_HZ CONFIG_STV0991_HZ_CLOCK @@ -2135,8 +2117,6 @@ CONFIG_SYS_CSPR6 CONFIG_SYS_CSPR6_EXT CONFIG_SYS_CSPR7 CONFIG_SYS_CSPR7_EXT -CONFIG_SYS_DA850_CS2CFG -CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_DDR2_DDRPHYCR CONFIG_SYS_DA850_DDR2_PBBPR CONFIG_SYS_DA850_DDR2_SDBCR @@ -3402,7 +3382,6 @@ CONFIG_SYS_NAND_MASK_CLE CONFIG_SYS_NAND_MAX_ECCPOS CONFIG_SYS_NAND_MAX_OOBFREE CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES -CONFIG_SYS_NAND_NO_SUBPAGE CONFIG_SYS_NAND_NO_SUBPAGE_WRITE CONFIG_SYS_NAND_ONFI_DETECTION CONFIG_SYS_NAND_OR_PRELIM @@ -4209,9 +4188,6 @@ CONFIG_SYS_VXWORKS_MAC_PTR CONFIG_SYS_WATCHDOG_FREQ CONFIG_SYS_WATCHDOG_VALUE CONFIG_SYS_WDTC_WDMR_VAL -CONFIG_SYS_WDTTIMERBASE -CONFIG_SYS_WDT_PERIOD_HIGH -CONFIG_SYS_WDT_PERIOD_LOW CONFIG_SYS_WINDOW1_BASE CONFIG_SYS_WRITE_SWAPPED_DATA CONFIG_SYS_XHCI_USB1_ADDR @@ -4222,7 +4198,6 @@ CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL CONFIG_TAM3517_SETTINGS -CONFIG_TAM3517_SW3_SETTINGS CONFIG_TCA642X CONFIG_TEGRA_BOARD_STRING CONFIG_TEGRA_CLOCK_SCALING @@ -4454,7 +4429,6 @@ CONFIG_X86_REFCODE_ADDR CONFIG_X86_REFCODE_RUN_ADDR CONFIG_XGI_XG22_BASE CONFIG_XILINX_SPI_IDLE_VAL -CONFIG_XR16L2751 CONFIG_XSENGINE CONFIG_XTFPGA CONFIG_YAFFSFS_PROVIDE_VALUES diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index cfada0ee11..eef12dd2b7 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1317,7 +1317,7 @@ static int flash_io_write(int fd_current) rc = -1; } - if (target_temp) { + if (rc >= 0 && target_temp) { int dir_fd; dir_fd = open(dname, O_DIRECTORY | O_RDONLY); |