diff options
| -rw-r--r-- | CHANGELOG | 6 | ||||
| -rwxr-xr-x | MAKEALL | 2 | ||||
| -rw-r--r-- | board/mpc8349ads/Makefile | 45 | ||||
| -rw-r--r-- | board/mpc8349ads/config.mk | 27 | ||||
| -rw-r--r-- | board/mpc8349ads/mpc8349ads.c | 235 | ||||
| -rw-r--r-- | board/mpc8349ads/u-boot.lds | 122 | ||||
| -rw-r--r-- | board/mpc8349emds/mpc8349emds.c | 46 | ||||
| -rw-r--r-- | board/mpc8349emds/pci.c (renamed from board/mpc8349ads/pci.c) | 9 | ||||
| -rw-r--r-- | cpu/mpc83xx/i2c.c | 2 | ||||
| -rw-r--r-- | include/asm-ppc/i2c.h | 2 | ||||
| -rw-r--r-- | include/configs/MPC8349ADS.h | 653 | ||||
| -rw-r--r-- | include/configs/MPC8349EMDS.h | 94 |
12 files changed, 66 insertions, 1177 deletions
@@ -2,6 +2,12 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port: + - Removed MPC8349ADS port + - Added PCI support to MPC8349ADS + - reworked memory map to allow mapping of all regions with BATs + Patch by Kumar Gala 20 Apr 2006 + * Coding Style cleanup * Write RTC seconds first to maintain settings integrity per @@ -117,7 +117,7 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ - MPC8349ADS TQM834x MPC8349EMDS \ + TQM834x MPC8349EMDS \ " diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile deleted file mode 100644 index f865f9c83b..0000000000 --- a/board/mpc8349ads/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = lib$(BOARD).a - -OBJS := $(BOARD).o pci.o - -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ - --include .depend - -######################################################################### diff --git a/board/mpc8349ads/config.mk b/board/mpc8349ads/config.mk deleted file mode 100644 index 4602169ecb..0000000000 --- a/board/mpc8349ads/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# MPC83xxADS -# - -TEXT_BASE = 0xFE700000 diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c deleted file mode 100644 index 9841298d6e..0000000000 --- a/board/mpc8349ads/mpc8349ads.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Change log: - * 20050101: Eran Liberty (liberty@freescale.com) - * Initial file creating (porting from 85XX & 8260) - */ - -#include <common.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <asm/mpc8349_pci.h> -#include <i2c.h> -#include <spd.h> -#include <miiphy.h> -#if defined(CONFIG_PCI) -#include <pci.h> -#endif -#if defined(CONFIG_SPD_EEPROM) -#include <spd_sdram.h> -#endif -int fixed_sdram(void); -void sdram_init(void); - -int board_early_init_f (void) -{ - volatile u8* bcsr = (volatile u8*)CFG_BCSR; - - /* Enable flash write */ - bcsr[1] &= ~0x01; - - return 0; -} - - -#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) - -long int initdram (int board_type) -{ - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - puts(" DDR RAM: "); - /* return total bus SDRAM size(bytes) -- DDR */ - return (msize * 1024 * 1024); -} - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMRBAR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif - - im->ddr.csbnds[0].csbnds = 0x00100017; - im->ddr.csbnds[1].csbnds = 0x0018001f; - im->ddr.csbnds[2].csbnds = 0x00000007; - im->ddr.csbnds[3].csbnds = 0x0008000f; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - im->ddr.cs_config[1] = CFG_DDR_CONFIG; - im->ddr.cs_config[2] = CFG_DDR_CONFIG; - im->ddr.cs_config[3] = CFG_DDR_CONFIG; - im->ddr.timing_cfg_1 = - 3 << TIMING_CFG1_PRETOACT_SHIFT | - 7 << TIMING_CFG1_ACTTOPRE_SHIFT | - 3 << TIMING_CFG1_ACTTORW_SHIFT | - 4 << TIMING_CFG1_CASLAT_SHIFT | - 3 << TIMING_CFG1_REFREC_SHIFT | - 3 << TIMING_CFG1_WRREC_SHIFT | - 2 << TIMING_CFG1_ACTTOACT_SHIFT | - 1 << TIMING_CFG1_WRTORD_SHIFT; - im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT; - im->ddr.sdram_cfg = - SDRAM_CFG_SREN -#if defined(CONFIG_DDR_2T_TIMING) - | SDRAM_CFG_2T_EN -#endif - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; - im->ddr.sdram_mode = - 0x2000 << SDRAM_MODE_ESD_SHIFT | - 0x0162 << SDRAM_MODE_SD_SHIFT; - - im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT | - 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT; - udelay(200); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} -#endif/*!CFG_SPD_EEPROM*/ - - -int checkboard (void) -{ - puts("Board: Freescale MPC8349ADS\n"); - return 0; -} - -/* - * if MPC8349ADS is soldered with SDRAM - */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void -sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; - volatile lbus8349_t *lbc= &immap->lbus; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; - - puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); - - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /*setup mtrpt, lsrt and lbcr for LB bus*/ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/ - - lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ - asm("sync"); - /*1 times*/ - *sdram_addr = 0xff; - udelay(100); - /*2 times*/ - *sdram_addr = 0xff; - udelay(100); - /*3 times*/ - *sdram_addr = 0xff; - udelay(100); - /*4 times*/ - *sdram_addr = 0xff; - udelay(100); - /*5 times*/ - *sdram_addr = 0xff; - udelay(100); - /*6 times*/ - *sdram_addr = 0xff; - udelay(100); - /*7 times*/ - *sdram_addr = 0xff; - udelay(100); - /*8 times*/ - *sdram_addr = 0xff; - udelay(100); - - /* 0x58636733;mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/ - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void -sdram_init(void) -{ - put("SDRAM on Local Bus is NOT available!\n"); -} -#endif diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349ads/u-boot.lds deleted file mode 100644 index 020cfa66f8..0000000000 --- a/board/mpc8349ads/u-boot.lds +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc83xx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 7ece7db7d0..b5ccb53604 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -30,9 +30,6 @@ #include <spd.h> #include <miiphy.h> #include <command.h> -#if defined(CONFIG_PCI) -#include <pci.h> -#endif #if defined(CONFIG_SPD_EEPROM) #include <spd_sdram.h> #endif @@ -50,6 +47,11 @@ int board_early_init_f (void) /* Enable flash write */ bcsr[1] &= ~0x01; +#ifdef CFG_USE_MPC834XSYS_USB_PHY + /* Use USB PHY on SYS board */ + bcsr[5] |= 0x02; +#endif + return 0; } @@ -152,44 +154,6 @@ int checkboard (void) return 0; } -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349emds_config_table[] = { - {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER - } }, - {} -} -#endif - -volatile static struct pci_controller hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - } -}; -#endif /* CONFIG_PCI */ - -void pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc83xx_init(volatile struct pci_controller *hose); - - pci_mpc83xx_init(hose); -#endif /* CONFIG_PCI */ -} - /* * if MPC8349EMDS is soldered with SDRAM */ diff --git a/board/mpc8349ads/pci.c b/board/mpc8349emds/pci.c index 319e35c970..63e4405578 100644 --- a/board/mpc8349ads/pci.c +++ b/board/mpc8349emds/pci.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE #ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxads_config_table[] = { +static struct pci_config_table pci_mpc8349emds_config_table[] = { {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID, pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, @@ -50,12 +50,12 @@ static struct pci_config_table pci_mpc83xxads_config_table[] = { static struct pci_controller pci_hose[] = { { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxads_config_table, + config_table:pci_mpc8349emds_config_table, #endif }, { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxads_config_table, + config_table:pci_mpc8349emds_config_table, #endif } }; @@ -188,7 +188,7 @@ pci_init_board(void) pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; /* * Configure PCI Outbound Translation Windows @@ -378,4 +378,5 @@ pci_init_board(void) #endif } + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c index 4e70f808a4..70450f9e49 100644 --- a/cpu/mpc83xx/i2c.c +++ b/cpu/mpc83xx/i2c.c @@ -41,7 +41,7 @@ #include <i2c.h> #include <asm/i2c.h> -#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X) +#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); #endif diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h index fa9d164e9a..1680d3a7c1 100644 --- a/include/asm-ppc/i2c.h +++ b/include/asm-ppc/i2c.h @@ -87,7 +87,7 @@ typedef struct i2c #error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h #endif -#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X) +#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) /* * MPC8349 have two i2c bus */ diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h deleted file mode 100644 index 1e9a1f7ab6..0000000000 --- a/include/configs/MPC8349ADS.h +++ /dev/null @@ -1,653 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * mpc8349ads board configuration file - * - * Please refer to doc/README.mpc83xxads for more info. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef DEBUG - -#define CONFIG_MII - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ -#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */ - -#define CONFIG_PCI -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ - -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66000000 -#else -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif -#endif - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ - -#define CFG_IMMRBAR 0xE0000000 - -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00000000 /* memtest region */ -#define CFG_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else - /* - * Manually set up DDR parameters - */ - #define CFG_DDR_SIZE 256 /* Mb */ - #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) - #define CFG_DDR_TIMING_1 0x37344321 - #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ - #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ - #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ - #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ -#endif - -/* - * SDRAM on the Local Bus - */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CFG_FLASH_CFI /* use the Common Flash Interface */ -#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ -/* #define CFG_FLASH_USE_BUFFER_WRITE */ - -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ - BR_V) /* valid */ -#define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/ -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */ - -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CFG_MID_FLASH_JUMP 0x7F000000 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT -#else -#undef CFG_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for ADS config reg - */ -#define CFG_BCSR 0xF8000000 -#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ -#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ -#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ -#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */ - -#define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ - -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* - * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 - * External Local Bus rate is - * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV - */ -#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) -#define CFG_LBC_LBCR 0x00000000 - -#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/ -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/ - -/* - * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CFG_OR2_PRELIM 0xfc006901 - -#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ - -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK get_bus_freq(0) - -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) - -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 -#define CFG_I2C2_OFFSET 0x3100 - -/* TSEC */ -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) - -/* IO Configuration */ -#define CFG_IO_CONF (\ - IO_CONF_UART |\ - IO_CONF_TSEC1 |\ - IO_CONF_IRQ0 |\ - IO_CONF_IRQ1 |\ - IO_CONF_IRQ2 |\ - IO_CONF_IRQ3 |\ - IO_CONF_IRQ4 |\ - IO_CONF_IRQ5 |\ - IO_CONF_IRQ6 |\ - IO_CONF_IRQ7 ) - -/* - * General PCI - * Addresses are mapped 1-1. - */ - -#define CFG_PCI1_MEM_BASE 0x80000000 -#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI1_MMIO_BASE 0x90000000 -#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE -#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CFG_PCI2_MEM_BASE 0xa0000000 -#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_MMIO_BASE 0xb0000000 -#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE -#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ -#if defined(CONFIG_PCI) - -#define PCI_ALL_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#ifndef CFG_RAMBOOT - #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 -#else - #define CFG_NO_FLASH 1 /* Flash is not usable now */ - #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) - #define CFG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII \ - ) -#endif -#endif - -#include <cmd_confdefs.h> - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -#define CFG_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#else -#define CFG_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII ) -#endif - -/* System IO Config */ -#define CFG_SICRH SICRH_TSOBI1 -#define CFG_SICRL SICRL_LDP_A - -#define CFG_HID0_INIT 0x000000000 - -#define CFG_HID0_FINAL CFG_HID0_INIT - -/* #define CFG_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST ) */ - -#define CFG_HID2 HID2_HBE - -/* DDR 0 - 256MB */ -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -/* stack in DCACHE @ 1GB (no backing mem) */ -#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* 2G - 3G PCI */ -#ifdef CONFIG_PCI -#define CFG_IBAT2L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT2U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT3U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT2L (0) -#define CFG_IBAT2U (0) -#define CFG_IBAT3L (0) -#define CFG_IBAT3U (0) -#endif - -#ifdef CONFIG_MPC83XX_PCI2 -#define CFG_IBAT4L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT4U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT5L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT4L (0) -#define CFG_IBAT4U (0) -#define CFG_IBAT5L (0) -#define CFG_IBAT5U (0) -#endif - -/* IMMRBAR */ -#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) - -/* SDRAM, BCSR & FLASH */ -#define CFG_IBAT7L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT7U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U -#define CFG_DBAT4L CFG_IBAT4L -#define CFG_DBAT4U CFG_IBAT4U -#define CFG_DBAT5L CFG_IBAT5L -#define CFG_DBAT5U CFG_IBAT5U -#define CFG_DBAT6L CFG_IBAT6L -#define CFG_DBAT6U CFG_IBAT6U -#define CFG_DBAT7L CFG_IBAT7L -#define CFG_DBAT7U CFG_IBAT7U - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:04:9f:11:22:33 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=ramfs.83xx\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1a479805e0..0300b0d949 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -29,7 +29,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define DEBUG #undef DEBUG /* @@ -40,8 +39,8 @@ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ -/* FIXME: Real PCI support will come in a follow-up update. */ -#undef CONFIG_PCI +#undef CONFIG_PCI +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #define PCI_66M #ifdef PCI_66M @@ -53,8 +52,10 @@ #ifndef CONFIG_SYS_CLK_FREQ #ifdef PCI_66M #define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #else #define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 #endif #endif @@ -69,7 +70,7 @@ /* * DDR Setup */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ @@ -157,7 +158,7 @@ /* * BCSR register on local bus 32KB, 8-bit wide for MDS config reg */ -#define CFG_BCSR 0xF8000000 +#define CFG_BCSR 0xE2400000 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ @@ -165,7 +166,7 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xE8000000 /* Initial RAM address */ +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ @@ -322,18 +323,8 @@ #define CFG_TSEC2_OFFSET 0x25000 #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) -/* IO Configuration */ -#define CFG_IO_CONF (\ - IO_CONF_UART |\ - IO_CONF_TSEC1 |\ - IO_CONF_IRQ0 |\ - IO_CONF_IRQ1 |\ - IO_CONF_IRQ2 |\ - IO_CONF_IRQ3 |\ - IO_CONF_IRQ4 |\ - IO_CONF_IRQ5 |\ - IO_CONF_IRQ6 |\ - IO_CONF_IRQ7 ) +/* USB */ +#define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ /* * General PCI @@ -341,21 +332,27 @@ */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xA0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE 0xB0000000 +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe3000000 -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_PHYS 0xE2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) -#define PCI_ALL_PCI1 +#define PCI_ONE_PCI1 #if defined(PCI_64BIT) #undef PCI_ALL_PCI1 #undef PCI_TWO_PCI1 @@ -512,35 +509,35 @@ #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CSB_TO_CLKIN |\ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1) #elif 0 /*396/132*/ #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CSB_TO_CLKIN |\ HRCWL_VCO_1X4 |\ HRCWL_CORE_TO_CSB_3X1) #elif 0 /*264/132*/ #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CSB_TO_CLKIN |\ HRCWL_VCO_1X4 |\ HRCWL_CORE_TO_CSB_2X1) #elif 0 /*132/132*/ #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CSB_TO_CLKIN |\ HRCWL_VCO_1X4 |\ HRCWL_CORE_TO_CSB_1X1) #elif 0 /*264/264 */ #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CSB_TO_CLKIN |\ HRCWL_VCO_1X4 |\ HRCWL_CORE_TO_CSB_1X1) #endif @@ -578,7 +575,7 @@ #define CFG_SICRL SICRL_LDP_A #define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK /* #define CFG_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ @@ -605,25 +602,28 @@ #define CFG_IBAT2U (0) #endif -/* IMMRBAR @ 0xE0000000 */ -#define CFG_IBAT3L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT3U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) - -/* stack in DCACHE (no backing mem) @ 0xE8000000 */ -#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#endif -/* LBC SDRAM @ 0xF0000000 */ -#define CFG_IBAT5L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT5U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) -/* BCSR @ 0xF8000000 */ -#define CFG_IBAT6L (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT6U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) -/* FLASH @ 0xFE000000 */ -#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) #define CFG_DBAT0L CFG_IBAT0L #define CFG_DBAT0U CFG_IBAT0U |