diff options
295 files changed, 5085 insertions, 3181 deletions
@@ -1,7 +1,7 @@ VERSION = 2015 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 NAME = # *DOCUMENTATION* @@ -977,8 +977,6 @@ The following options need to be configured: CONFIG_AUTOBOOT_PROMPT CONFIG_AUTOBOOT_DELAY_STR CONFIG_AUTOBOOT_STOP_STR - CONFIG_AUTOBOOT_DELAY_STR2 - CONFIG_AUTOBOOT_STOP_STR2 CONFIG_ZERO_BOOTDELAY_CHECK CONFIG_RESET_TO_RETRY diff --git a/arch/Kconfig b/arch/Kconfig index 200588aef6..96db5c5088 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -25,6 +25,7 @@ config ARM config AVR32 bool "AVR32 architecture" select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config BLACKFIN bool "Blackfin architecture" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2985e6e065..ac86518eb0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -369,6 +369,14 @@ config TARGET_PENGWYN select DM_SERIAL select DM_GPIO +config TARGET_AM335X_BALTOS + bool "Support am335x_baltos" + select CPU_V7 + select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO + config TARGET_AM335X_EVM bool "Support am335x_evm" select CPU_V7 @@ -668,6 +676,7 @@ config TEGRA select SUPPORT_SPL select SPL select OF_CONTROL + select SPL_DISABLE_OF_CONTROL select CPU_V7 select DM select DM_SPI_FLASH @@ -794,6 +803,7 @@ config ARCH_UNIPHIER select DM select DM_SERIAL select DM_I2C + select SPL_DISABLE_OF_CONTROL help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) @@ -962,6 +972,7 @@ source "board/trizepsiv/Kconfig" source "board/ttcontrol/vision2/Kconfig" source "board/udoo/Kconfig" source "board/vpac270/Kconfig" +source "board/vscom/baltos/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" source "board/woodburn/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index c342217fa9..42f3df2ac2 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -332,6 +332,11 @@ static void mxs_enable_4p2_dcdc_input(int xfer) debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling"); + if (xfer && (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return; + } + prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_PWDN_5VBRNOUT; prev_5v_droop = readl(&power_regs->hw_power_ctrl) & @@ -343,11 +348,6 @@ static void mxs_enable_4p2_dcdc_input(int xfer) clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); - if (xfer && (readl(&power_regs->hw_power_5vctrl) & - POWER_5VCTRL_ENABLE_DCDC)) { - return; - } - /* * Recording orignal values that will be modified temporarlily * to handle a chip bug. See chip errata for CQ ENGR00115837 diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index f5b16b4b72..b3fb0c47ab 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -123,30 +123,33 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); - /* Perform hardware leveling. */ - udelay(1000); - writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | - 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); - writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | - 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); - - writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); - - /* Enable read leveling */ - writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); - - /* - * Enable full read and write leveling. Wait for read and write - * leveling bit to clear RDWRLVLFULL_START bit 31 - */ - while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0) - ; - - /* Check the timeout register to see if leveling is complete */ - if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0) - puts("DDR3 H/W leveling incomplete with errors\n"); - - if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { + /* Perform hardware leveling for DDR3 */ + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { + udelay(1000); + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | + 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); + + /* Enable read leveling */ + writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl); + + /* + * Enable full read and write leveling. Wait for read and write + * leveling bit to clear RDWRLVLFULL_START bit 31 + */ + while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) + != 0) + ; + + /* Check the timeout register to see if leveling is complete */ + if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0) + puts("DDR3 H/W leveling incomplete with errors\n"); + + } else { + /* DDR2 */ configure_mr(nr, 0); configure_mr(nr, 1); } @@ -183,9 +186,49 @@ void set_sdram_timings(const struct emif_regs *regs, int nr) } /* + * Configure EXT PHY registers for software leveling + */ +static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + __maybe_unused const u32 *ext_phy_ctrl_const_regs; + u32 i = 0; + __maybe_unused u32 size; + + ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = + (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + +#ifdef CONFIG_AM43XX + /* + * External phy 6-24 registers do not change with ddr frequency. + * These only need to be set on DDR2 on AM43xx. + */ + emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size); + + if (!size) + return; + + for (i = 0; i < size; i++) { + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); + } +#endif +} + +/* * Configure EXT PHY registers for hardware leveling */ -static void ext_phy_settings(const struct emif_regs *regs, int nr) +static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) { /* * Enable hardware leveling on the EMIF. For details about these @@ -256,8 +299,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); - if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) - ext_phy_settings(regs, nr); + if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) { + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) + ext_phy_settings_hwlvl(regs, nr); + else + ext_phy_settings_swlvl(regs, nr); + } } /** diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 9cf816c89a..27fa3fb462 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -124,8 +124,9 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); - /* Allow EMIF to control DDR_RESET */ - writel(0x00000000, &ddrctrl->ddrioctrl); + if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) + /* Allow EMIF to control DDR_RESET */ + writel(0x00000000, &ddrctrl->ddrioctrl); #endif /* Program EMIF instance */ diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index c56417dd2f..0b0e5003cc 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -24,7 +24,7 @@ void __weak cpu_cache_initialization(void){} -int cleanup_before_linux(void) +int cleanup_before_linux_select(int flags) { /* * this function is called just before we call linux @@ -42,24 +42,30 @@ int cleanup_before_linux(void) icache_disable(); invalidate_icache_all(); - /* - * turn off D-cache - * dcache_disable() in turn flushes the d-cache and disables MMU - */ - dcache_disable(); - v7_outer_cache_disable(); + if (flags & CBL_DISABLE_CACHES) { + /* + * turn off D-cache + * dcache_disable() in turn flushes the d-cache and disables MMU + */ + dcache_disable(); + v7_outer_cache_disable(); - /* - * After D-cache is flushed and before it is disabled there may - * be some new valid entries brought into the cache. We are sure - * that these lines are not dirty and will not affect our execution. - * (because unwinding the call-stack and setting a bit in CP15 SCTLR - * is all we did during this. We have not pushed anything on to the - * stack. Neither have we affected any static data) - * So just invalidate the entire d-cache again to avoid coherency - * problems for kernel - */ - invalidate_dcache_all(); + /* + * After D-cache is flushed and before it is disabled there may + * be some new valid entries brought into the cache. We are + * sure that these lines are not dirty and will not affect our + * execution. (because unwinding the call-stack and setting a + * bit in CP15 SCTRL is all we did during this. We have not + * pushed anything on to the stack. Neither have we affected + * any static data) So just invalidate the entire d-cache again + * to avoid coherency problems for kernel + */ + invalidate_dcache_all(); + } else { + flush_dcache_all(); + invalidate_icache_all(); + icache_enable(); + } /* * Some CPU need more cache attention before starting the kernel. @@ -68,3 +74,8 @@ int cleanup_before_linux(void) return 0; } + +int cleanup_before_linux(void) +{ + return cleanup_before_linux_select(CBL_ALL); +} diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index c61442578d..3ca7128ed7 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -8,6 +8,7 @@ config TARGET_SMDKV310 select SUPPORT_SPL bool "Exynos4210 SMDKV310 board" select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_TRATS bool "Exynos4210 Trats board" @@ -28,6 +29,7 @@ config TARGET_ODROID config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_ARNDALE bool "Exynos5250 Arndale board" @@ -35,31 +37,37 @@ config TARGET_ARNDALE select CPU_V7_HAS_VIRT select SUPPORT_SPL select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_SMDK5250 bool "SMDK5250 board" select SUPPORT_SPL select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_SNOW bool "Snow board" select SUPPORT_SPL select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_SMDK5420 bool "SMDK5420 board" select SUPPORT_SPL select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_PEACH_PI bool "Peach Pi board" select SUPPORT_SPL select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_PEACH_PIT bool "Peach Pit board" select SUPPORT_SPL select OF_CONTROL + select SPL_DISABLE_OF_CONTROL endchoice diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 03674e609f..c94a807819 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -372,6 +372,7 @@ static void setup_dplls(void) { u32 temp; const struct dpll_params *params; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; debug("setup_dplls\n"); @@ -382,7 +383,8 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) + if (emif_sdram_type(readl(&emif->emif_sdram_config)) == + EMIF_SDRAM_TYPE_LPDDR2) do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else @@ -508,6 +510,12 @@ static u32 optimize_vcore_voltage(struct volts const *v) return val; } +#ifdef CONFIG_IODELAY_RECALIBRATION +void __weak recalibrate_iodelay(void) +{ +} +#endif + /* * Setup the voltages for the main SoC core power domains. * We start with the maximum voltages allowed here, as set in the corresponding @@ -561,6 +569,16 @@ void scale_vcores(struct vcores_data const *vcores) debug("cor: %d\n", vcores->core.value); do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic); + /* + * IO delay recalibration should be done immediately after + * adjusting AVS voltages for VDD_CORE_L. + * Respective boards should call __recalibrate_iodelay() + * with proper mux, virtual and manual mode configurations. + */ +#ifdef CONFIG_IODELAY_RECALIBRATION + recalibrate_iodelay(); +#endif + debug("mpu: %d\n", vcores->mpu.value); do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); /* Configure MPU ABB LDO after scale */ @@ -587,6 +605,16 @@ void scale_vcores(struct vcores_data const *vcores) val = optimize_vcore_voltage(&vcores->core); do_scale_vcore(vcores->core.addr, val, vcores->core.pmic); + /* + * IO delay recalibration should be done immediately after + * adjusting AVS voltages for VDD_CORE_L. + * Respective boards should call __recalibrate_iodelay() + * with proper mux, virtual and manual mode configurations. + */ +#ifdef CONFIG_IODELAY_RECALIBRATION + recalibrate_iodelay(); +#endif + val = optimize_vcore_voltage(&vcores->mpu); do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic); diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index c01a98f719..f5b22f6a78 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -242,13 +242,122 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) __udelay(130); } -static void ddr3_leveling(u32 base, const struct emif_regs *regs) +static void update_hwleveling_output(u32 base, const struct emif_regs *regs) { - if (is_omap54xx()) - omap5_ddr3_leveling(base, regs); + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; + u32 reg, i; + + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + + /* Update PHY_REG_RDDQS_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; + for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; + for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ + emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; + for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { + reg = readl(emif_phy_status++); + writel(reg, emif_ext_phy_ctrl_reg++); + writel(reg, emif_ext_phy_ctrl_reg++); + } + + /* Disable Leveling */ + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); } -static void ddr3_init(u32 base, const struct emif_regs *regs) +static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* Clear Error Status */ + clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); + + clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, + EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); + + /* Disable refreshed before leveling */ + clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT, + EMIF_REG_INITREF_DIS_SHIFT); + + /* Start Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + __udelay(300); + + /* Check for leveling timeout */ + if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { + printf("Leveling timeout on EMIF%d\n", emif_num(base)); + return; + } + + /* Enable refreshes after leveling */ + clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT); + + debug("HW leveling success\n"); + /* + * Update slave ratios in EXT_PHY_CTRLx registers + * as per HW leveling output + */ + update_hwleveling_output(base, regs); +} + +static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + if (warm_reset()) + emif_reset_phy(base); + do_ext_phy_settings(base, regs); + + writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, + &emif->emif_sdram_ref_ctrl); + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + writel(regs->zq_config, &emif->emif_zq_config); + writel(regs->temp_alert_config, &emif->emif_temp_alert_config); + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); + + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + + __udelay(1000); + + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); + + if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) + dra7_ddr3_leveling(base, regs); +} + +static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -269,25 +378,20 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - /* - * The same sequence should work on OMAP5432 as well. But strange that - * it is not working - */ - if (is_dra7xx()) { - do_ext_phy_settings(base, regs); - writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - } else { - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - do_ext_phy_settings(base, regs); - } + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + do_ext_phy_settings(base, regs); - /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + omap5_ddr3_leveling(base, regs); +} - ddr3_leveling(base, regs); +static void ddr3_init(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + omap5_ddr3_init(base, regs); + else + dra7_ddr3_init(base, regs); } #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1066,16 +1170,18 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!(in_sdram || warm_reset())) { - if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) + if (!in_sdram && (!warm_reset() || is_dra7xx())) { + if (emif_sdram_type(regs->sdram_config) == + EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); else ddr3_init(base, regs); } - if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { + if (warm_reset() && (emif_sdram_type(regs->sdram_config) == + EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - ddr3_leveling(base, regs); + omap5_ddr3_leveling(base, regs); } /* Write to the shadow registers */ @@ -1294,7 +1400,8 @@ static void do_bug0039_workaround(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; - u32 sdram_type = emif_sdram_type(); + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); debug(">>sdram_init()\n"); diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 64c68791f1..e709f14a92 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -11,3 +11,4 @@ obj-y += sdram.o obj-y += prcm-regs.o obj-y += hw_data.o obj-y += abb.o +obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o diff --git a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c new file mode 100644 index 0000000000..9fa6e6991f --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * Lokesh Vutla <lokeshvutla@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/utils.h> +#include <asm/arch/dra7xx_iodelay.h> +#include <asm/arch/omap.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/arch/mux_dra7xx.h> +#include <asm/omap_common.h> + +static int isolate_io(u32 isolate) +{ + if (isolate) { + clrsetbits_le32((*ctrl)->control_pbias, SDCARD_PWRDNZ, + SDCARD_PWRDNZ); + clrsetbits_le32((*ctrl)->control_pbias, SDCARD_BIAS_PWRDNZ, + SDCARD_BIAS_PWRDNZ); + } + + /* Override control on ISOCLKIN signal to IO pad ring. */ + clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, + PMCTRL_ISOCLK_OVERRIDE_CTRL); + if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, PMCTRL_ISOCLK_STATUS_MASK, + (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) + return ERR_DEISOLATE_IO << isolate; + + /* Isolate/Deisolate IO */ + clrsetbits_le32((*ctrl)->ctrl_core_sma_sw_0, CTRL_ISOLATE_MASK, + isolate << CTRL_ISOLATE_SHIFT); + /* Dummy read to add delay t > 10ns */ + readl((*ctrl)->ctrl_core_sma_sw_0); + + /* Return control on ISOCLKIN to hardware */ + clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, + PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL); + if (!wait_on_value(PMCTRL_ISOCLK_STATUS_MASK, + 0 << PMCTRL_ISOCLK_STATUS_SHIFT, + (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) + return ERR_DEISOLATE_IO << isolate; + + return 0; +} + +static int calibrate_iodelay(u32 base) +{ + u32 reg; + + /* Configure REFCLK period */ + reg = readl(base + CFG_REG_2_OFFSET); + reg &= ~CFG_REG_REFCLK_PERIOD_MASK; + reg |= CFG_REG_REFCLK_PERIOD; + writel(reg, base + CFG_REG_2_OFFSET); + + /* Initiate Calibration */ + clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_CALIB_STRT_MASK, + CFG_REG_CALIB_STRT << CFG_REG_CALIB_STRT_SHIFT); + if (!wait_on_value(CFG_REG_CALIB_STRT_MASK, CFG_REG_CALIB_END, + (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) + return ERR_CALIBRATE_IODELAY; + + return 0; +} + +static int update_delay_mechanism(u32 base) +{ + /* Initiate the reload of calibrated values. */ + clrsetbits_le32(base + CFG_REG_0_OFFSET, CFG_REG_ROM_READ_MASK, + CFG_REG_ROM_READ_START); + if (!wait_on_value(CFG_REG_ROM_READ_MASK, CFG_REG_ROM_READ_END, + (u32 *)(base + CFG_REG_0_OFFSET), LDELAY)) + return ERR_UPDATE_DELAY; + + return 0; +} + +static u32 calculate_delay(u32 base, u16 offset, u16 den) +{ + u16 refclk_period, dly_cnt, ref_cnt; + u32 reg, q, r; + + refclk_period = readl(base + CFG_REG_2_OFFSET) & + CFG_REG_REFCLK_PERIOD_MASK; + + reg = readl(base + offset); + dly_cnt = (reg & CFG_REG_DLY_CNT_MASK) >> CFG_REG_DLY_CNT_SHIFT; + ref_cnt = (reg & CFG_REG_REF_CNT_MASK) >> CFG_REG_REF_CNT_SHIFT; + + if (!dly_cnt || !den) + return 0; + + /* + * To avoid overflow and integer truncation, delay value + * is calculated as quotient + remainder. + */ + q = 5 * ((ref_cnt * refclk_period) / (dly_cnt * den)); + r = (10 * ((ref_cnt * refclk_period) % (dly_cnt * den))) / + (2 * dly_cnt * den); + + return q + r; +} + +static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde) +{ + u32 g_delay_coarse, g_delay_fine; + u32 a_delay_coarse, a_delay_fine; + u32 c_elements, f_elements; + u32 total_delay, reg = 0; + + g_delay_coarse = g_delay / 920; + g_delay_fine = ((g_delay % 920) * 10) / 60; + + a_delay_coarse = a_delay / cpde; + a_delay_fine = ((a_delay % cpde) * 10) / fpde; + + c_elements = g_delay_coarse + a_delay_coarse; + f_elements = (g_delay_fine + a_delay_fine) / 10; + + if (f_elements > 22) { + total_delay = c_elements * cpde + f_elements * fpde; + + c_elements = total_delay / cpde; + f_elements = (total_delay % cpde) / fpde; + } + + reg = (c_elements << CFG_X_COARSE_DLY_SHIFT) & CFG_X_COARSE_DLY_MASK; + reg |= (f_elements << CFG_X_FINE_DLY_SHIFT) & CFG_X_FINE_DLY_MASK; + reg |= CFG_X_SIGNATURE << CFG_X_SIGNATURE_SHIFT; + reg |= CFG_X_LOCK << CFG_X_LOCK_SHIFT; + + return reg; +} + +static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array, + int niodelays) +{ + struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array; + u32 reg, cpde, fpde, i; + + if (!niodelays) + return 0; + + cpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_3_OFFSET, + 88); + if (!cpde) + return ERR_CPDE; + + fpde = calculate_delay((*ctrl)->iodelay_config_base, CFG_REG_4_OFFSET, + 264); + if (!fpde) + return ERR_FPDE; + + for (i = 0; i < niodelays; i++, iodelay++) { + reg = get_cfg_reg(iodelay->a_delay, iodelay->g_delay, cpde, + fpde); + writel(reg, base + iodelay->offset); + } + + return 0; +} + +void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays) +{ + int ret = 0; + + /* IO recalibration should be done only from SRAM */ + if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) { + puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n"); + return; + } + + /* unlock IODELAY CONFIG registers */ + writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + + ret = calibrate_iodelay((*ctrl)->iodelay_config_base); + if (ret) + goto err; + + ret = isolate_io(ISOLATE_IO); + if (ret) + goto err; + + ret = update_delay_mechanism((*ctrl)->iodelay_config_base); + if (ret) + goto err; + + /* Configure Mux settings */ + do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); + + /* Configure Manual IO timing modes */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); + if (ret) + goto err; + + ret = isolate_io(DEISOLATE_IO); + +err: + /* lock IODELAY CONFIG registers */ + writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + /* + * UART cannot be used during IO recalibration sequence as IOs are in + * isolation. So error handling and debug prints are done after + * complete IO delay recalibration sequence + */ + switch (ret) { + case ERR_CALIBRATE_IODELAY: + puts("IODELAY: IO delay calibration sequence failed\n"); + break; + case ERR_ISOLATE_IO: + puts("IODELAY: Isolation of Device IOs failed\n"); + break; + case ERR_UPDATE_DELAY: + puts("IODELAY: Delay mechanism update with new calibrated values failed\n"); + break; + case ERR_DEISOLATE_IO: + puts("IODELAY: De-isolation of Device IOs failed\n"); + break; + case ERR_CPDE: + puts("IODELAY: CPDE calculation failed\n"); + break; + case ERR_FPDE: + puts("IODELAY: FPDE calculation failed\n"); + break; + default: + debug("IODELAY: IO delay recalibration successfully completed\n"); + } +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 868415d038..f1a59a3ca9 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -534,6 +534,9 @@ void enable_basic_clocks(void) void enable_basic_uboot_clocks(void) { u32 const clk_domains_essential[] = { +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + (*prcm)->cm_ipu_clkstctrl, +#endif 0 }; @@ -547,7 +550,11 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l4per_i2c2_clkctrl, (*prcm)->cm_l4per_i2c3_clkctrl, (*prcm)->cm_l4per_i2c4_clkctrl, +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + (*prcm)->cm_ipu_i2c5_clkctrl, +#else (*prcm)->cm_l4per_i2c5_clkctrl, +#endif (*prcm)->cm_l3init_hsusbhost_clkctrl, (*prcm)->cm_l3init_fsusb_clkctrl, 0 @@ -592,11 +599,11 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x80808080, - .ctrl_ddrio_0 = 0xA2084210, - .ctrl_ddrio_1 = 0x84210840, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_emif_sdram_config_ext = 0x0001C127, + .ctrl_emif_sdram_config_ext_final = 0x0001C127, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; @@ -604,11 +611,11 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x60606080, - .ctrl_ddrio_0 = 0xA2084210, - .ctrl_ddrio_1 = 0x84210840, + .ctrl_ddrio_0 = 0x00094A40, + .ctrl_ddrio_1 = 0x04A52000, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0x0001C1A7, - .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, + .ctrl_emif_sdram_config_ext = 0x0001C127, + .ctrl_emif_sdram_config_ext_final = 0x0001C127, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 8d6b59eeb0..39f8d0d5e2 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -40,6 +40,15 @@ static struct gpio_bank gpio_bank_54xx[8] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; +void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *)array; + + for (i = 0; i < size; i++, pad++) + writel(pad->val, base + pad->offset); +} + #ifdef CONFIG_SPL_BUILD /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) @@ -75,16 +84,20 @@ static void io_settings_ddr3(void) writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); - writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); + + if (!is_dra7xx()) { + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); + } /* omap5432 does not use lpddr2 */ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); - writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif1_sdram_config_ext); - writel(ioregs->ctrl_emif_sdram_config_ext, - (*ctrl)->control_emif2_sdram_config_ext); + if (!is_dra72x()) + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif2_sdram_config_ext); if (is_omap54xx()) { /* Disable DLL select */ @@ -109,6 +122,7 @@ static void io_settings_ddr3(void) void do_io_settings(void) { u32 io_settings = 0, mask = 0; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; /* Impedance settings EMMC, C2C 1,2, hsi2 */ mask = (ds_mask << 2) | (ds_mask << 8) | @@ -164,7 +178,7 @@ void do_io_settings(void) (sc_fast << 17) | (sc_fast << 14); writel(io_settings, (*ctrl)->control_smart3io_padconf_1); - if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) + if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) io_settings_lpddr2(); else io_settings_ddr3(); diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index f80d36dc3c..cd51fe7678 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -378,6 +378,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, .control_phy_power_usb = 0x4A002370, .control_phy_power_sata = 0x4A002374, + .ctrl_core_sma_sw_0 = 0x4A0023FC, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, .control_core_mac_id_1_lo = 0x4A00251C, @@ -457,6 +458,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_efuse_3 = 0x4AE0C5D0, .control_efuse_4 = 0x4AE0C5D4, .control_efuse_13 = 0x4AE0C5F0, + .iodelay_config_base = 0x4844A000, }; struct prcm_regs const omap5_es2_prcm = { @@ -815,6 +817,10 @@ struct prcm_regs const dra7xx_prcm = { .cm_dsp_clkstctrl = 0x4a005400, .cm_dsp_dsp_clkctrl = 0x4a005420, + /* cm IPU */ + .cm_ipu_clkstctrl = 0x4a005540, + .cm_ipu_i2c5_clkctrl = 0x4a005578, + /* prm irqstatus regs */ .prm_irqstatus_mpu_2 = 0x4ae06014, @@ -976,6 +982,7 @@ struct prcm_regs const dra7xx_prcm = { .prm_rstctrl = 0x4ae07d00, .prm_rstst = 0x4ae07d04, .prm_rsttime = 0x4ae07d08, + .prm_io_pmctrl = 0x4ae07d20, .prm_vc_val_bypass = 0x4ae07da0, .prm_vc_cfg_i2c_mode = 0x4ae07db4, .prm_vc_cfg_i2c_clk = 0x4ae07db8, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 5f8daa1ee1..cf4452d260 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -146,18 +146,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -171,18 +171,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_phy_ctlr_1_init = 0x0024400B, + .emif_ddr_phy_ctlr_1 = 0x0E24400B, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00910091, .emif_ddr_ext_phy_ctrl_3 = 0x00950095, .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -191,15 +191,15 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61862B32, .sdram_config = 0x61862B32, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x0000493E, + .ref_ctrl = 0x0000514C, .ref_ctrl_final = 0x0000144A, .sdram_tim1 = 0xD113781C, - .sdram_tim2 = 0x308F7FE3, - .sdram_tim3 = 0x009F86A8, + .sdram_tim2 = 0x305A7FDA, + .sdram_tim3 = 0x409F86A8, .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190B, + .zq_config = 0x5007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E24400D, + .emif_ddr_phy_ctlr_1_init = 0x0024400D, .emif_ddr_phy_ctlr_1 = 0x0E24400D, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, @@ -207,7 +207,7 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; @@ -421,8 +421,14 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { 0x0 }; +/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, 0x00980098, 0x00340034, 0x00350035, @@ -441,17 +447,28 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { 0x00500050, 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x0, 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; +/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { + 0x10040100, + 0x00910091, + 0x00950095, + 0x009B009B, + 0x009E009E, 0x00980098, 0x00330033, 0x00330033, @@ -470,17 +487,28 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { 0x00500050, 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x0, 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; +/* Ext phy ctrl 1-35 regs */ const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { + 0x10040100, + 0x00A400A4, + 0x00A900A9, + 0x00B000B0, + 0x00B000B0, 0x00A400A4, 0x00390039, 0x00320032, @@ -505,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { 0x0, 0x0, 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, 0x0 }; @@ -562,7 +595,7 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) *regs = &mr_regs; } -void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; @@ -601,6 +634,58 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) } } +static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; + const u32 *ext_phy_ctrl_const_regs; + u32 i, hw_leveling, size; + + emif_nr = (base == EMIF1_BASE) ? 1 : 2; + + hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; + + emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1); + + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]); + writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]); + + if (!hw_leveling) { + /* + * Copy the predefined PHY register values + * in case of sw leveling + */ + for (i = 1; i < 25; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + } else { + /* + * Write the init value for HW levling to occur + */ + for (i = 21; i < 35; i++) { + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2]); + writel(ext_phy_ctrl_const_regs[i], + &emif_ext_phy_ctrl_base[i * 2 + 1]); + } + } +} + +void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + do_ext_phy_settings_omap5(base, regs); + else + do_ext_phy_settings_dra7(base, regs); +} + #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS static const struct lpddr2_ac_timings timings_jedec_532_mhz = { .max_freq = 532000000, diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig index 04acdaad79..792ef595e4 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -7,10 +7,12 @@ choice config TARGET_S5P_GONI bool "S5P Goni board" select OF_CONTROL + select SPL_DISABLE_OF_CONTROL config TARGET_SMDKC100 bool "Support smdkc100 board" select OF_CONTROL + select SPL_DISABLE_OF_CONTROL endchoice diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index a82c8b9d44..4b2494ea37 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -223,6 +223,7 @@ int cpu_eth_init(bd_t *bis) __maybe_unused int rc; #ifdef CONFIG_MACPWR + gpio_request(CONFIG_MACPWR, "macpwr"); gpio_direction_output(CONFIG_MACPWR, 1); mdelay(200); #endif diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 1bb9b8ed1d..05c401dc73 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -198,6 +198,11 @@ static u32 get_i2c_clk(void) return get_ipg_clk(); } +static u32 get_dspi_clk(void) +{ + return get_ipg_clk(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -215,6 +220,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_fec_clk(); case MXC_I2C_CLK: return get_i2c_clk(); + case MXC_DSPI_CLK: + return get_dspi_clk(); default: break; } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fe3aa8935d..9c735c672a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -133,9 +133,13 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb +dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ + vf610-colibri.dtb + targets += $(dtb-y) -DTC_FLAGS += -R 4 -p 0x1000 +# Add any required device tree compiler flags here +DTC_FLAGS += PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 415dfeab6a..d572f1e72b 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -43,140 +43,102 @@ voltage-regulators { ldo1_reg: ldo1 { - regulator-compatible = "LDO1"; regulator-name = "VDD_ALIVE_1.0V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; ldo2_reg: ldo2 { - regulator-compatible = "LDO2"; regulator-name = "VDDQ_VM1M2_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; ldo3_reg: ldo3 { - regulator-compatible = "LDO3"; regulator-name = "VCC_1.8V_AP"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo4_reg: ldo4 { - regulator-compatible = "LDO4"; regulator-name = "VDDQ_MMC2_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; ldo5_reg: ldo5 { - regulator-compatible = "LDO5"; regulator-name = "VDDQ_MMC0/1/3_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo6_reg: ldo6 { - regulator-compatible = "LDO6"; regulator-name = "VMPLL_1.0V"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; ldo7_reg: ldo7 { - regulator-compatible = "LDO7"; regulator-name = "VPLL_1.1V"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; ldo8_reg: ldo8 { - regulator-compatible = "LDO8"; regulator-name = "VDD_MIPI/HDMI_1.0V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; - ldo9_reg: ldo9 { - regulator-compatible = "LDO9"; - regulator-name = "nc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - ldo10_reg: ldo10 { - regulator-compatible = "LDO10"; regulator-name = "VDD_MIPI/HDMI_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo11_reg: ldo11 { - regulator-compatible = "LDO11"; regulator-name = "VDD_ABB1_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo12_reg: ldo12 { - regulator-compatible = "LDO12"; regulator-name = "VDD_UOTG_3.0V"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; }; ldo13_reg: ldo13 { - regulator-compatible = "LDO13"; regulator-name = "VDD_C2C_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo14_reg: ldo14 { - regulator-compatible = "LDO14"; regulator-name = "VDD_ABB02_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo15_reg: ldo15 { - regulator-compatible = "LDO15"; regulator-name = "VDD_HSIC/OTG_1.0V"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; ldo16_reg: ldo16 { - regulator-compatible = "LDO16"; regulator-name = "VDD_HSIC_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo17_reg: ldo17 { - regulator-compatible = "LDO17"; regulator-name = "VDDQ_CAM_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; - ldo18_reg: ldo18 { - regulator-compatible = "LDO18"; - regulator-name = "nc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: ldo19 { - regulator-compatible = "LDO19"; - regulator-name = "nc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - ldo20_reg: ldo20 { - regulator-compatible = "LDO20"; regulator-name = "VDDQ_EMMC_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -185,7 +147,6 @@ }; ldo21_reg: ldo21 { - regulator-compatible = "LDO21"; regulator-name = "TFLASH_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -194,7 +155,6 @@ }; ldo22_reg: ldo22 { - regulator-compatible = "LDO22"; regulator-name = "VDDQ_EMMC_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -202,20 +162,6 @@ regulator-boot-on; }; - ldo23_reg: ldo23 { - regulator-compatible = "LDO23"; - regulator-name = "nc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo24_reg: ldo24 { - regulator-compatible = "LDO24"; - regulator-name = "nc"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - ldo25_reg: ldo25 { regulator-compatible = "LDO25"; regulator-name = "VDDQ_LCD_3.0V"; @@ -223,75 +169,53 @@ regulator-max-microvolt = <3000000>; }; - ldo26_reg: ldo26 { - regulator-compatible = "LDO26"; - regulator-name = "nc"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - buck1_reg: buck@1 { - regulator-compatible = "BUCK1"; + buck1_reg: buck1 { regulator-name = "VDD_MIF_1.0V"; regulator-min-microvolt = <8500000>; regulator-max-microvolt = <1100000>; }; - buck2_reg: buck@2 { - regulator-compatible = "BUCK2"; + buck2_reg: buck2 { regulator-name = "VDD_ARM_1.0V"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1500000>; }; buck3_reg: buck3 { - regulator-compatible = "BUCK3"; regulator-name = "VDD_INT_1.1V"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; }; buck4_reg: buck4 { - regulator-compatible = "BUCK4"; regulator-name = "VDD_G3D_1.0V"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; }; buck5_reg: buck5 { - regulator-compatible = "BUCK5"; regulator-name = "VDDQ_AP_1.2V"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; buck6_reg: buck6 { - regulator-compatible = "BUCK6"; regulator-name = "VCC_INL1/7_1.35V"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; }; buck7_reg: buck7 { - regulator-compatible = "BUCK7"; regulator-name = "VCC_INL2/3/5_2.0V"; regulator-min-microvolt = <2000000>; regulator-max-microvolt = <2000000>; }; buck8_reg: buck8 { - regulator-compatible = "BUCK8"; regulator-name = "VCC_P3V3_2.85V"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <3300000>; }; - - buck9_reg: buck9 { - regulator-compatible = "BUCK9"; - regulator-name = "nc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; }; }; }; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 5a39e93c68..8be6adbf07 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -163,12 +163,15 @@ spi@7000d400 { status = "okay"; + spi-deactivate-delay = <200>; + spi-max-frequency = <3000000>; cros_ec: cros-ec@0 { compatible = "google,cros-ec-spi"; spi-max-frequency = <3000000>; interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; + ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; reg = <0>; google,cros-ec-spi-msg-delay = <2000>; diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi new file mode 100644 index 0000000000..7a8e9bee33 --- /dev/null +++ b/arch/arm/dts/vf-colibri.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include "vf.dtsi" + +&dspi1 { + status = "okay"; + bus-num = <1>; + + spi_cmd: sspi@0 { + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi new file mode 100644 index 0000000000..78706e118e --- /dev/null +++ b/arch/arm/dts/vf.dtsi @@ -0,0 +1,100 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +/include/ "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + spi0 = &dspi0; + spi1 = &dspi1; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips0: aips-bus@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dspi0: dspi0@4002c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002c000 0x1000>; + num-cs = <5>; + status = "disabled"; + }; + + dspi1: dspi1@4002d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002d000 0x1000>; + num-cs = <5>; + status = "disabled"; + }; + + qspi0: quadspi@40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>; + status = "disabled"; + }; + + gpio0: gpio@40049000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff000 0x40>; + #gpio-cells = <2>; + }; + + gpio1: gpio@4004a000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff040 0x40>; + #gpio-cells = <2>; + }; + + gpio2: gpio@4004b000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff080 0x40>; + #gpio-cells = <2>; + }; + + gpio3: gpio@4004c000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff0c0 0x40>; + #gpio-cells = <2>; + }; + + gpio4: gpio@4004d000 { + compatible = "fsl,vf610-gpio"; + reg = <0x400ff100 0x40>; + #gpio-cells = <2>; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + }; +}; diff --git a/arch/arm/dts/vf500-colibri.dts b/arch/arm/dts/vf500-colibri.dts new file mode 100644 index 0000000000..e3833064d2 --- /dev/null +++ b/arch/arm/dts/vf500-colibri.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF50"; + compatible = "toradex,vf500-colibri_vf50", "toradex,vf500-colibri_vf50", "fsl,vf500"; +}; diff --git a/arch/arm/dts/vf610-colibri.dts b/arch/arm/dts/vf610-colibri.dts new file mode 100644 index 0000000000..63bb3f4ee7 --- /dev/null +++ b/arch/arm/dts/vf610-colibri.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61"; + compatible = "toradex,vf610-colibri_vf61", "toradex,vf610-colibri_vf61", "fsl,vf610"; +}; diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 275befd2f8..5e56cfe8f2 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -145,7 +145,8 @@ const char *get_imx_type(u32 imxtype) int print_cpuinfo(void) { - u32 cpurev, max_freq; + u32 cpurev; + __maybe_unused u32 max_freq; #if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL) struct udevice *thermal_dev; diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index e88e6e2a98..7fb23dd027 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -92,3 +92,29 @@ void imx_iomux_set_gpr_register(int group, int start_bit, reg |= (value << start_bit); writel(reg, base + group * 4); } + +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction) +{ + u32 reg; + /* + * Only on Vybrid the input/output buffer enable flags + * are part of the shared mux/conf register. + */ + reg = readl(base + (gpio << 2)); + + if (direction) + reg |= 0x2; + else + reg &= ~0x2; + + writel(reg, base + (gpio << 2)); +} + +void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state) +{ + *gpio_state = readl(base + (gpio << 2)) & + ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE); +} +#endif diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h new file mode 100644 index 0000000000..2f53d85283 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2015 + * Texas Instruments Incorporated + * + * Lokesh Vutla <lokeshvutla@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DRA7_IODELAY_H_ +#define _DRA7_IODELAY_H_ + +#include <common.h> +#include <asm/arch/sys_proto.h> + +/* CONFIG_REG_0 */ +#define CFG_REG_0_OFFSET 0xC +#define CFG_REG_ROM_READ_SHIFT 1 +#define CFG_REG_ROM_READ_MASK (1 << 1) +#define CFG_REG_CALIB_STRT_SHIFT 0 +#define CFG_REG_CALIB_STRT_MASK (1 << 0) +#define CFG_REG_CALIB_STRT 1 +#define CFG_REG_CALIB_END 0 +#define CFG_REG_ROM_READ_START (1 << 1) +#define CFG_REG_ROM_READ_END (0 << 1) + +/* CONFIG_REG_2 */ +#define CFG_REG_2_OFFSET 0x14 +#define CFG_REG_REFCLK_PERIOD_SHIFT 0 +#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0) +#define CFG_REG_REFCLK_PERIOD 0x2EF + +/* CONFIG_REG_8 */ +#define CFG_REG_8_OFFSET 0x2C +#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA +#define CFG_IODELAY_LOCK_KEY 0x0000AAAB + +/* CONFIG_REG_3/4 */ +#define CFG_REG_3_OFFSET 0x18 +#define CFG_REG_4_OFFSET 0x1C +#define CFG_REG_DLY_CNT_SHIFT 16 +#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16) +#define CFG_REG_REF_CNT_SHIFT 0 +#define CFG_REG_REF_CNT_MASK (0xFFFF << 0) + +/* CTRL_CORE_SMA_SW_0 */ +#define CTRL_ISOLATE_SHIFT 2 +#define CTRL_ISOLATE_MASK (1 << 2) +#define ISOLATE_IO 1 +#define DEISOLATE_IO 0 + +/* PRM_IO_PMCTRL */ +#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 +#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) +#define PMCTRL_ISOCLK_STATUS_SHIFT 1 +#define PMCTRL_ISOCLK_STATUS_MASK (1 << 1) +#define PMCTRL_ISOCLK_OVERRIDE_CTRL 1 +#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0 + +#define ERR_CALIBRATE_IODELAY 0x1 +#define ERR_DEISOLATE_IO 0x2 +#define ERR_ISOLATE_IO 0x4 +#define ERR_UPDATE_DELAY 0x8 +#define ERR_CPDE 0x3 +#define ERR_FPDE 0x5 + +/* CFG_XXX */ +#define CFG_X_SIGNATURE_SHIFT 12 +#define CFG_X_SIGNATURE_MASK (0x3F << 12) +#define CFG_X_LOCK_SHIFT 10 +#define CFG_X_LOCK_MASK (0x1 << 10) +#define CFG_X_COARSE_DLY_SHIFT 5 +#define CFG_X_COARSE_DLY_MASK (0x1F << 5) +#define CFG_X_FINE_DLY_SHIFT 0 +#define CFG_X_FINE_DLY_MASK (0x1F << 0) +#define CFG_X_SIGNATURE 0x29 +#define CFG_X_LOCK 1 + +void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays); + +#endif diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index e1553879d0..2115abb555 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -26,6 +26,21 @@ #define WKEN (1 << 24) #define WKDIS (0 << 24) +#define PULL_ENA (0 << 16) +#define PULL_DIS (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCONTROL (1 << 19) + +/* Active pin states */ +#define PIN_OUTPUT (0 | PULL_DIS) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN (0) +#define PIN_INPUT (INPUT_EN | PULL_DIS) +#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + #define M0 0 #define M1 1 #define M2 2 @@ -43,6 +58,28 @@ #define M14 14 #define M15 15 +#define MODE_SELECT (1 << 8) +#define DELAYMODE_SHIFT 4 + +#define MANUAL_MODE MODE_SELECT + +#define VIRTUAL_MODE0 (MODE_SELECT | (0x0 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE1 (MODE_SELECT | (0x1 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE2 (MODE_SELECT | (0x2 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE3 (MODE_SELECT | (0x3 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE4 (MODE_SELECT | (0x4 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE5 (MODE_SELECT | (0x5 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE6 (MODE_SELECT | (0x6 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE7 (MODE_SELECT | (0x7 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE8 (MODE_SELECT | (0x8 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE9 (MODE_SELECT | (0x9 << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE10 (MODE_SELECT | (0xa << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE11 (MODE_SELECT | (0xb << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE12 (MODE_SELECT | (0xc << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE13 (MODE_SELECT | (0xd << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE14 (MODE_SELECT | (0xe << DELAYMODE_SHIFT)) +#define VIRTUAL_MODE15 (MODE_SELECT | (0xf << DELAYMODE_SHIFT)) + #define SAFE_MODE M15 #define GPMC_AD0 0x000 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index e844bfb884..68c6d6dc0a 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -216,27 +216,6 @@ struct s32ktimer { #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) -/* IO Delay module defines */ -#define CFG_IO_DELAY_BASE 0x4844A000 -#define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) - -/* CPSW IO Delay registers*/ -#define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) -#define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) -#define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) -#define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) -#define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) -#define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) -#define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) -#define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) -#define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) -#define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) - -#define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA -#define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB -#define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 -#define CFG_IO_DELAY_LOCK_MASK 0x400 - #ifndef __ASSEMBLY__ struct srcomp_params { s8 divide_factor; @@ -255,9 +234,5 @@ struct ctrl_ioregs { u32 ctrl_ddr_ctrl_ext_0; }; -struct io_delay { - u32 addr; - u32 dly; -}; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index ea84665f5b..6da8297c72 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -18,6 +18,18 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Structure for Iodelay configuration registers. + * Theoretical max for g_delay is 21560 ps. + * Theoretical max for a_delay is 1/3rd of g_delay max. + * So using u16 for both a/g_delay. + */ +struct iodelay_cfg_entry { + u16 offset; + u16 a_delay; + u16 g_delay; +}; + struct pad_conf_entry { u32 offset; u32 val; @@ -32,6 +44,7 @@ void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 04011ae255..f9dd3c817d 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -336,4 +336,12 @@ void arch_timer_init(void); void tegra30_set_up_pllp(void); +/** + * Enable output clock for external peripherals + * + * @param clk_id Clock ID to output (1, 2 or 3) + * @return 0 if OK. -ve on error + */ +int clock_external_output(int clk_id); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h index 83f9f472c9..b64f9d813b 100644 --- a/arch/arm/include/asm/arch-tegra/sys_proto.h +++ b/arch/arm/include/asm/arch-tegra/sys_proto.h @@ -25,4 +25,11 @@ int tegra_board_id(void); */ int tegra_lcd_pmic_init(int board_id); +/** + * nvidia_board_init() - perform any board-specific init + * + * @return 0 if OK, -ve on error + */ +int nvidia_board_init(void); + #endif diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index 7005855999..3c67e72afe 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -285,12 +285,12 @@ enum periph_id { /* 184 */ PERIPH_ID_GPU, PERIPH_ID_AMX1, - PERIPH_ID_X_RESERVED26, - PERIPH_ID_X_RESERVED27, - PERIPH_ID_X_RESERVED28, - PERIPH_ID_X_RESERVED29, - PERIPH_ID_X_RESERVED30, - PERIPH_ID_X_RESERVED31, + PERIPH_ID_AFC5, + PERIPH_ID_AFC4, + PERIPH_ID_AFC3, + PERIPH_ID_AFC2, + PERIPH_ID_AFC1, + PERIPH_ID_AFC0, PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index d6f515f1e9..7818b1bd34 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -26,6 +26,12 @@ struct flow_ctlr { u32 cpu_pwr_csr; /* offset 0x38 */ u32 mpid; /* offset 0x3c */ u32 ram_repair; /* offset 0x40 */ + u32 flow_dbg_sel; /* offset 0x44 */ + u32 flow_dbg_cnt0; /* offset 0x48 */ + u32 flow_dbg_cnt1; /* offset 0x4c */ + u32 flow_dbg_qual; /* offset 0x50 */ + u32 flow_ctlr_spare; /* offset 0x54 */ + u32 ram_repair_cluster1;/* offset 0x58 */ }; /* HALT_COP_EVENTS_0, 0x04 */ @@ -43,4 +49,10 @@ struct flow_ctlr { #define CSR_WAIT_WFI_SHIFT 8 #define CSR_PWR_OFF_STS (1 << 16) +/* RAM_REPAIR, 0x40, 0x58 */ +enum { + RAM_REPAIR_REQ = 0x1 << 0, + RAM_REPAIR_STS = 0x1 << 1, +}; + #endif /* _TEGRA124_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 535adadd79..e5a5c6d28f 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -17,6 +17,7 @@ enum mxc_clock { MXC_ESDHC_CLK, MXC_FEC_CLK, MXC_I2C_CLK, + MXC_DSPI_CLK, }; void enable_ocotp_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index bc6db2a5a5..fdb45e9954 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -189,6 +189,8 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) +#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) #define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) @@ -206,6 +208,8 @@ struct anadig_reg { #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) #define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) +#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) +#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) #define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h new file mode 100644 index 0000000000..622b8f0dea --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/gpio.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_VF610_GPIO_H +#define __ASM_ARCH_VF610_GPIO_H + +#define VYBRID_GPIO_COUNT 32 +#define VF610_GPIO_DIRECTION_IN 0x0 +#define VF610_GPIO_DIRECTION_OUT 0x1 + +/* GPIO registers */ +struct vybrid_gpio_regs { + u32 gpio_pdor; + u32 gpio_psor; + u32 gpio_pcor; + u32 gpio_ptor; + u32 gpio_pdir; +}; + +struct vybrid_gpio_platdata { + unsigned int chip; + u32 base; + const char *port_name; +}; +#endif /* __ASM_ARCH_VF610_GPIO_H */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 202198133c..7df3b1e392 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -81,6 +81,11 @@ #define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) #define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) #define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) +#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) +#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) +#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) +#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) +#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100) /* AIPS 1 */ #define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 9226e69fec..019307b2f9 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -32,22 +32,61 @@ #define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE) + +#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) +#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) + enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -57,6 +96,12 @@ enum { VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL), + VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL), + VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), @@ -66,26 +111,40 @@ enum { VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), + VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), + VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 7a545ea01a..7986e6e794 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -44,6 +44,8 @@ #define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) #define EMIF_REG_FAST_INIT_SHIFT 29 #define EMIF_REG_FAST_INIT_MASK (1 << 29) +#define EMIF_REG_LEVLING_TO_SHIFT 4 +#define EMIF_REG_LEVELING_TO_MASK (7 << 4) #define EMIF_REG_PHY_DLL_READY_SHIFT 2 #define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) @@ -509,6 +511,13 @@ #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) +/* EMIF_PHY_CTRL_36 */ +#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR (1 << 8) + +#define PHY_RDDQS_RATIO_REGS 5 +#define PHY_FIFO_WE_SLAVE_RATIO_REGS 5 +#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS 10 + /*Leveling Fields */ #define DDR3_WR_LVL_INT 0x73 #define DDR3_RD_LVL_INT 0x33 @@ -1200,12 +1209,10 @@ static inline u32 get_emif_rev(u32 base) * which is typically the case. So it is sufficient to get * SDRAM type from EMIF1. */ -static inline u32 emif_sdram_type(void) +static inline u32 emif_sdram_type(u32 sdram_config) { - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - return (readl(&emif->emif_sdram_config) & - EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; + return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK) + >> EMIF_REG_SDRAM_TYPE_SHIFT; } /* assert macros */ @@ -1235,6 +1242,5 @@ extern u32 *const T_den; #endif void config_data_eye_leveling_samples(u32 emif_base); -u32 emif_sdram_type(void); const struct read_write_regs *get_bug_regs(u32 *iterations); #endif diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index e0a49be4ff..258101949a 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -187,6 +187,12 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, */ void imx_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG +void imx_iomux_gpio_set_direction(unsigned int gpio, + unsigned int direction); +void imx_iomux_gpio_get_function(unsigned int gpio, + u32 *gpio_state); +#endif /* macros for declaring and using pinmux array */ #if defined(CONFIG_MX6QDL) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index b0296fbae6..5469435cc7 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -313,6 +313,7 @@ struct prcm_regs { u32 prm_rstctrl; u32 prm_rstst; u32 prm_rsttime; + u32 prm_io_pmctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk; @@ -344,6 +345,10 @@ struct prcm_regs { /* GMAC Clk Ctrl */ u32 cm_gmac_gmac_clkctrl; u32 cm_gmac_clkstctrl; + + /* IPU */ + u32 cm_ipu_clkstctrl; + u32 cm_ipu_i2c5_clkctrl; }; struct omap_sys_ctrl_regs { @@ -455,6 +460,8 @@ struct omap_sys_ctrl_regs { u32 control_efuse_12; u32 control_efuse_13; u32 control_padconf_wkup_base; + u32 iodelay_config_base; + u32 ctrl_core_sma_sw_0; }; struct dpll_params { @@ -583,6 +590,7 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); void usb_fake_mac_from_die_id(u32 *id); void usb_set_serial_num_from_die_id(u32 *id); +void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); @@ -622,12 +630,19 @@ static inline u8 is_omap54xx(void) } #define DRA7XX 0x07000000 +#define DRA72X 0x07200000 static inline u8 is_dra7xx(void) { extern u32 *const omap_si_rev; return ((*omap_si_rev & 0xFF000000) == DRA7XX); } + +static inline u8 is_dra72x(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFFF00000) == DRA72X; +} #endif /* diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 04681fc5a0..0121db8bb5 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -7,6 +7,7 @@ #include <common.h> #include <netdev.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> @@ -160,10 +161,17 @@ static void update_sdram_window_sizes(void) } #ifdef CONFIG_ARCH_CPU_INIT +static void set_cbar(u32 addr) +{ + asm("mcr p15, 4, %0, c15, c0" : : "r" (addr)); +} + + int arch_cpu_init(void) { /* Linux expects the internal registers to be at 0xf1000000 */ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); + set_cbar(SOC_REGS_PHY_BASE + 0xC000); /* * We need to call mvebu_mbus_probe() before calling @@ -240,6 +248,13 @@ int cpu_eth_init(bd_t *bis) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + /* First disable L2 cache - may still be enable from BootROM */ + if (mvebu_soc_family() == MVEBU_SOC_A38X) + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + /* Avoid problem with e.g. neta ethernet driver */ invalidate_dcache_all(); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 9b42871935..f5b5ee9cb7 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -24,9 +24,15 @@ config SYS_MALLOC_F_LEN config USE_PRIVATE_LIBGCC default y +config DM_USB + default y + config SPL_DM default y +config SPL_DISABLE_OF_CONTROL + default y + source "arch/arm/mach-tegra/tegra20/Kconfig" source "arch/arm/mach-tegra/tegra30/Kconfig" source "arch/arm/mach-tegra/tegra114/Kconfig" diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 131802ae62..ce9b6959ef 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -107,6 +107,11 @@ __weak int tegra_lcd_pmic_init(int board_it) return 0; } +__weak int nvidia_board_init(void) +{ + return 0; +} + /* * Routine: board_init * Description: Early hardware init. @@ -156,7 +161,6 @@ int board_init(void) #ifdef CONFIG_USB_EHCI_TEGRA pin_mux_usb(); - usb_process_devicetree(gd->fdt_blob); #endif #ifdef CONFIG_LCD @@ -180,8 +184,7 @@ int board_init(void) /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif - - return 0; + return nvidia_board_init(); } #ifdef CONFIG_BOARD_EARLY_INIT_F diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index cdd54388c5..24047b8c82 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -17,11 +17,13 @@ /* Tegra SoC common clock control functions */ #include <common.h> +#include <errno.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> @@ -82,7 +84,7 @@ static struct clk_pll *get_pll(enum clock_id clkid) assert(clock_id_is_pll(clkid)); if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) { - debug("%s: Invalid PLL\n", __func__); + debug("%s: Invalid PLL %d\n", __func__, clkid); return NULL; } return &clkrst->crc_pll[clkid]; @@ -118,9 +120,12 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon) { - struct clk_pll *pll = get_pll(clkid); + struct clk_pll *pll = NULL; u32 misc_data, data; + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + pll = get_pll(clkid); + /* * We cheat by treating all PLL (except PLLU) in the same fashion. * This works only because: @@ -702,3 +707,18 @@ void tegra30_set_up_pllp(void) set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4); } + +int clock_external_output(int clk_id) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + if (clk_id >= 1 && clk_id <= 3) { + setbits_le32(&pmc->pmc_clk_out_cntrl, + 1 << (2 + (clk_id - 1) * 8)); + } else { + printf("%s: Unknown output clock id %d\n", __func__, clk_id); + return -EINVAL; + } + + return 0; +} diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 6331cd40fd..30ae036bff 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -9,7 +9,7 @@ #include <asm/io.h> #include <asm/types.h> - +#include <asm/arch/flow.h> #include <asm/arch/powergate.h> #include <asm/arch/tegra.h> @@ -75,11 +75,29 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id) return 0; } +static void tegra_powergate_ram_repair(void) +{ +#ifdef CONFIG_TEGRA124 + struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; + + /* Request RAM repair for cluster 0 and wait until complete */ + setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); + while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS)) + ; + + /* Same for cluster 1 */ + setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); + while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS)) + ; +#endif +} + int tegra_powergate_sequence_power_up(enum tegra_powergate id, enum periph_id periph) { int err; + tegra_powergate_ram_repair(); reset_set_enable(periph, 1); err = tegra_powergate_power_on(id); diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 6579e3f30c..f3324ffaa8 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -10,7 +10,7 @@ config TARGET_JETSON_TK1 select CPU_V7_HAS_VIRT if !SPL_BUILD config TARGET_NYAN_BIG - bool "Google/NVIDIA Nyan-big Chrombook" + bool "Google/NVIDIA Nyan-big Chromebook" help Nyan Big is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard CD and WP diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 2d17550f73..b9558484b0 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -475,7 +475,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { PERIPHC_ACTMON, /* 120 */ - NONE(EXTPERIPH1), + PERIPHC_EXTPERIPH1, NONE(EXTPERIPH2), NONE(EXTPERIPH3), NONE(OOB), diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index c69654c993..eb3377486f 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -17,35 +17,14 @@ config TARGET_ATNGW100MKII config TARGET_ATSTK1002 bool "Support atstk1002" -config TARGET_ATSTK1003 - bool "Support atstk1003" - -config TARGET_ATSTK1004 - bool "Support atstk1004" - -config TARGET_ATSTK1006 - bool "Support atstk1006" - -config TARGET_FAVR_32_EZKIT - bool "Support favr-32-ezkit" - config TARGET_GRASSHOPPER bool "Support grasshopper" -config TARGET_MIMC200 - bool "Support mimc200" - -config TARGET_HAMMERHEAD - bool "Support hammerhead" - endchoice source "board/atmel/atngw100/Kconfig" source "board/atmel/atngw100mkii/Kconfig" source "board/atmel/atstk1000/Kconfig" -source "board/earthlcd/favr-32-ezkit/Kconfig" source "board/in-circuit/grasshopper/Kconfig" -source "board/mimc/mimc200/Kconfig" -source "board/miromico/hammerhead/Kconfig" endmenu diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile index 6750913630..8108ae5272 100644 --- a/arch/avr32/lib/Makefile +++ b/arch/avr32/lib/Makefile @@ -8,9 +8,6 @@ # obj-y += memset.o -ifndef CONFIG_SYS_GENERIC_BOARD -obj-y += board.o -endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += interrupts.o obj-y += dram_init.o diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c deleted file mode 100644 index aacfcbf69a..0000000000 --- a/arch/avr32/lib/board.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <stdio_dev.h> -#include <version.h> -#include <net.h> - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -#include <asm/sections.h> -#include <asm/arch/mmu.h> -#include <asm/arch/hardware.h> - -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -#include <mmc.h> -#endif -DECLARE_GLOBAL_DATA_PTR; - -unsigned long monitor_flash_len; - -__weak void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} - -/* Weak aliases for optional board functions */ -static int __do_nothing(void) -{ - return 0; -} -int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); -int board_early_init_r(void) __attribute__((weak, alias("__do_nothing"))); - -static int init_baudrate(void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - -static int display_banner (void) -{ - printf ("\n\n%s\n\n", version_string); - printf ("U-Boot code: %08lx -> %08lx data: %08lx -> %08lx\n", - (unsigned long)_text, (unsigned long)_etext, - (unsigned long)_data, (unsigned long)(&__bss_end)); - return 0; -} - -static int display_dram_config (void) -{ - int i; - - puts ("DRAM Configuration:\n"); - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); - print_size (gd->bd->bi_dram[i].size, "\n"); - } - - return 0; -} - -static void display_flash_config (void) -{ - puts ("Flash: "); - print_size(gd->bd->bi_flashsize, " "); - printf("at address 0x%08lx\n", gd->bd->bi_flashstart); -} - -void board_init_f(ulong board_type) -{ - gd_t gd_data; - gd_t *new_gd; - bd_t *bd; - unsigned long *new_sp; - unsigned long monitor_len; - unsigned long monitor_addr; - unsigned long addr; - - /* Initialize the global data pointer */ - memset(&gd_data, 0, sizeof(gd_data)); - gd = &gd_data; - - /* Perform initialization sequence */ - board_early_init_f(); - arch_cpu_init(); - board_postclk_init(); - env_init(); - init_baudrate(); - serial_init(); - console_init_f(); - display_banner(); - dram_init(); - - /* If we have no SDRAM, we can't go on */ - if (gd->ram_size <= 0) - panic("No working SDRAM available\n"); - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - u-boot image - * - heap for malloc() - * - board info struct - * - global data struct - * - stack - */ - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; - monitor_len = (char *)(&__bss_end) - _text; - - /* - * Reserve memory for u-boot code, data and bss. - * Round down to next 4 kB limit. - */ - addr -= monitor_len; - addr &= ~(4096UL - 1); - monitor_addr = addr; - - /* Reserve memory for malloc() */ - addr -= CONFIG_SYS_MALLOC_LEN; - -#ifdef CONFIG_LCD -#ifdef CONFIG_FB_ADDR - printf("LCD: Frame buffer allocated at preset 0x%08x\n", - CONFIG_FB_ADDR); - gd->fb_base = CONFIG_FB_ADDR; -#else - addr = lcd_setmem(addr); - printf("LCD: Frame buffer allocated at 0x%08lx\n", addr); - gd->fb_base = addr; -#endif /* CONFIG_FB_ADDR */ -#endif /* CONFIG_LCD */ - - /* Allocate a Board Info struct on a word boundary */ - addr -= sizeof(bd_t); - addr &= ~3UL; - gd->bd = bd = (bd_t *)addr; - - /* Allocate a new global data copy on a 8-byte boundary. */ - addr -= sizeof(gd_t); - addr &= ~7UL; - new_gd = (gd_t *)addr; - - /* And finally, a new, bigger stack. */ - new_sp = (unsigned long *)addr; - gd->start_addr_sp = addr; - *(--new_sp) = 0; - *(--new_sp) = 0; - - dram_init_banksize(); - - memcpy(new_gd, gd, sizeof(gd_t)); - - relocate_code((unsigned long)new_sp, new_gd, monitor_addr); -} - -void board_init_r(gd_t *new_gd, ulong dest_addr) -{ -#ifndef CONFIG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif - bd_t *bd; - - gd = new_gd; - bd = gd->bd; - - gd->flags |= GD_FLG_RELOC; - gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; - - /* Enable the MMU so that we can keep u-boot simple */ - mmu_init_r(dest_addr); - - board_early_init_r(); - - monitor_flash_len = _edata - _text; - -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - /* - * We have to relocate the command table manually - */ - fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), - ll_entry_count(cmd_tbl_t, cmd)); -#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ - - /* there are some other pointer constants we must deal with */ -#ifndef CONFIG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - - timer_init(); - - /* The malloc area is right below the monitor image in RAM */ - mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); - - enable_interrupts(); - - bd->bi_flashstart = 0; - bd->bi_flashsize = 0; - bd->bi_flashoffset = 0; - -#ifndef CONFIG_SYS_NO_FLASH - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; - bd->bi_flashsize = flash_init(); - bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text; - - if (bd->bi_flashsize) - display_flash_config(); -#endif - - if (bd->bi_dram[0].size) - display_dram_config(); - - gd->bd->bi_boot_params = malloc(CONFIG_SYS_BOOTPARAMS_LEN); - if (!gd->bd->bi_boot_params) - puts("WARNING: Cannot allocate space for boot parameters\n"); - - /* initialize environment */ - env_relocate(); - - stdio_init(); - jumptable_init(); - console_init_r(); - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - puts("Net: "); - eth_initialize(); -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI - mmc_initialize(gd->bd); -#endif - for (;;) { - main_loop(); - } -} diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 02c4cd366d..e6ddb17a14 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -52,6 +52,11 @@ int cleanup_before_linux(void) return 0; } +int cleanup_before_linux_select(int flags) +{ + return 0; +} + void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { #ifdef CONFIG_PCI diff --git a/board/atmel/atstk1000/Kconfig b/board/atmel/atstk1000/Kconfig index 6d4151453f..b4fa9a2b38 100644 --- a/board/atmel/atstk1000/Kconfig +++ b/board/atmel/atstk1000/Kconfig @@ -13,51 +13,3 @@ config SYS_CONFIG_NAME default "atstk1002" endif - -if TARGET_ATSTK1003 - -config SYS_BOARD - default "atstk1000" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atstk1003" - -endif - -if TARGET_ATSTK1004 - -config SYS_BOARD - default "atstk1000" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atstk1004" - -endif - -if TARGET_ATSTK1006 - -config SYS_BOARD - default "atstk1000" - -config SYS_VENDOR - default "atmel" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "atstk1006" - -endif diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS index 378e1b3dbc..1070f98e53 100644 --- a/board/atmel/atstk1000/MAINTAINERS +++ b/board/atmel/atstk1000/MAINTAINERS @@ -1,12 +1,6 @@ ATSTK1000 BOARD -#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> -S: Orphan (since 2014-06) +M: Andreas Bießmann <andreas.biessmann@corscience.de> +S: Maintained F: board/atmel/atstk1000/ F: include/configs/atstk1002.h F: configs/atstk1002_defconfig -F: include/configs/atstk1003.h -F: configs/atstk1003_defconfig -F: include/configs/atstk1004.h -F: configs/atstk1004_defconfig -F: include/configs/atstk1006.h -F: configs/atstk1006_defconfig diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index fd4363bece..679b67432c 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -30,32 +30,12 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { }; static const struct sdram_config sdram_config = { -#if defined(CONFIG_ATSTK1006) - /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */ .data_bits = SDRAM_DATA_32BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 2, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 4, - .txsr = 7, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -#else - /* MT48LC2M32B2P-5 (8 MB) on motherboard */ -#ifdef CONFIG_ATSTK1004 - .data_bits = SDRAM_DATA_16BIT, -#else - .data_bits = SDRAM_DATA_32BIT, -#endif #ifdef CONFIG_ATSTK1000_16MB_SDRAM /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */ .row_bits = 12, #else + /* MT48LC2M32B2P-5 (8 MB) on motherboard */ .row_bits = 11, #endif .col_bits = 8, @@ -69,7 +49,6 @@ static const struct sdram_config sdram_config = { .txsr = 5, /* 15.6 us */ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, -#endif }; int board_early_init_f(void) diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index e434ed9b87..2237b7aa1f 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -120,6 +120,42 @@ static void setup_iomux_features(void) ARRAY_SIZE(feature_pads)); } +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C2 - EEPROM */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, + .gp = IMX_GPIO_NR(3, 16) + } +}; + +/* I2C3 - IO expander */ +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, + .gp = IMX_GPIO_NR(3, 17) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, + .gp = IMX_GPIO_NR(3, 18) + } +}; + +static void setup_iomux_i2c(void) +{ + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +} + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -151,6 +187,7 @@ int board_early_init_f(void) setup_iomux_uart(); setup_iomux_spi(); + setup_iomux_i2c(); setup_iomux_features(); return 0; @@ -236,22 +273,6 @@ int board_mmc_init(bd_t *bis) return 0; } -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - -/* I2C3 - IO expander */ -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - static iomux_v3_cfg_t const pwm_pad[] = { MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM), }; @@ -315,8 +336,6 @@ int board_init(void) backlight_lcd_off(); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); - leds_on(); #ifdef CONFIG_CMD_SATA diff --git a/board/earthlcd/favr-32-ezkit/Kconfig b/board/earthlcd/favr-32-ezkit/Kconfig deleted file mode 100644 index 50e29ec241..0000000000 --- a/board/earthlcd/favr-32-ezkit/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_FAVR_32_EZKIT - -config SYS_BOARD - default "favr-32-ezkit" - -config SYS_VENDOR - default "earthlcd" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "favr-32-ezkit" - -endif diff --git a/board/earthlcd/favr-32-ezkit/MAINTAINERS b/board/earthlcd/favr-32-ezkit/MAINTAINERS deleted file mode 100644 index 89ba862149..0000000000 --- a/board/earthlcd/favr-32-ezkit/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -FAVR-32-EZKIT BOARD -#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> -S: Orphan (since 2014-06) -F: board/earthlcd/favr-32-ezkit/ -F: include/configs/favr-32-ezkit.h -F: configs/favr-32-ezkit_defconfig diff --git a/board/earthlcd/favr-32-ezkit/Makefile b/board/earthlcd/favr-32-ezkit/Makefile deleted file mode 100644 index f712ab9c7a..0000000000 --- a/board/earthlcd/favr-32-ezkit/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2008 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := favr-32-ezkit.o flash.o diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c deleted file mode 100644 index f9ac330c33..0000000000 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <netdev.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - /* MT48LC4M32B2P-6 (16 MB) */ - .data_bits = SDRAM_DATA_32BIT, - .row_bits = 12, - .col_bits = 8, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 5, - .txsr = 5, - /* 15.6 us */ - .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); - - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart3(PORTMUX_DRIVE_MIN); -#if defined(CONFIG_MACB) - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - return 0; -} - -#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) -int board_eth_init(bd_t *bi) -{ - return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, - bi->bi_phy_id[0]); -} -#endif diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c deleted file mode 100644 index e45c6f4d01..0000000000 --- a/board/earthlcd/favr-32-ezkit/flash.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> - -#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH -#include <asm/arch/cacheflush.h> -#include <asm/io.h> -#include <asm/sections.h> - -DECLARE_GLOBAL_DATA_PTR; - -flash_info_t flash_info[1]; - -static void flash_identify(uint16_t *flash, flash_info_t *info) -{ - unsigned long flags; - - flags = disable_interrupts(); - - dcache_flush_unlocked(); - - writew(0xaa, flash + 0x555); - writew(0x55, flash + 0xaaa); - writew(0x90, flash + 0x555); - info->flash_id = readl(flash); - writew(0xff, flash); - - readw(flash); - - if (flags) - enable_interrupts(); -} - -unsigned long flash_init(void) -{ - unsigned long addr; - unsigned int i; - - flash_info[0].size = CONFIG_SYS_FLASH_SIZE; - flash_info[0].sector_count = 135; - - flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); - - for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) - flash_info[0].start[i] = addr; - for (; i < flash_info[0].sector_count; i++, addr += 0x10000) - flash_info[0].start[i] = addr; - - return CONFIG_SYS_FLASH_SIZE; -} - -void flash_print_info(flash_info_t *info) -{ - printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", - info->flash_id >> 16, info->flash_id & 0xffff); - printf("Size: %ld MB in %d sectors\n", - info->size >> 10, info->sector_count); -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - unsigned long flags; - unsigned long start_time; - uint16_t *fb, *sb; - unsigned int i; - int ret; - uint16_t status; - - if ((s_first < 0) || (s_first > s_last) - || (s_last >= info->sector_count)) { - puts("Error: first and/or last sector out of range\n"); - return ERR_INVAL; - } - - for (i = s_first; i < s_last; i++) - if (info->protect[i]) { - printf("Error: sector %d is protected\n", i); - return ERR_PROTECTED; - } - - fb = (uint16_t *)uncached(info->start[0]); - - dcache_flush_unlocked(); - - for (i = s_first; (i <= s_last) && !ctrlc(); i++) { - printf("Erasing sector %3d...", i); - - sb = (uint16_t *)uncached(info->start[i]); - - flags = disable_interrupts(); - - start_time = get_timer(0); - - /* Unlock sector */ - writew(0xaa, fb + 0x555); - writew(0x70, sb); - - /* Erase sector */ - writew(0xaa, fb + 0x555); - writew(0x55, fb + 0xaaa); - writew(0x80, fb + 0x555); - writew(0xaa, fb + 0x555); - writew(0x55, fb + 0xaaa); - writew(0x30, sb); - - /* Wait for completion */ - ret = ERR_OK; - do { - /* TODO: Timeout */ - status = readw(sb); - } while ((status != 0xffff) && !(status & 0x28)); - - writew(0xf0, fb); - - /* - * Make sure the command actually makes it to the bus - * before we re-enable interrupts. - */ - readw(fb); - - if (flags) - enable_interrupts(); - - if (status != 0xffff) { - printf("Flash erase error at address 0x%p: 0x%02x\n", - sb, status); - ret = ERR_PROG_ERROR; - break; - } - } - - if (ctrlc()) - printf("User interrupt!\n"); - - return ERR_OK; -} - -int write_buff(flash_info_t *info, uchar *src, - ulong addr, ulong count) -{ - unsigned long flags; - uint16_t *base, *p, *s, *end; - uint16_t word, status, status1; - int ret = ERR_OK; - - if (addr < info->start[0] - || (addr + count) > (info->start[0] + info->size) - || (addr + count) < addr) { - puts("Error: invalid address range\n"); - return ERR_INVAL; - } - - if (addr & 1 || count & 1 || (unsigned int)src & 1) { - puts("Error: misaligned source, destination or count\n"); - return ERR_ALIGN; - } - - base = (uint16_t *)uncached(info->start[0]); - end = (uint16_t *)uncached(addr + count); - - flags = disable_interrupts(); - - dcache_flush_unlocked(); - sync_write_buffer(); - - for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; - p < end && !ctrlc(); p++, s++) { - word = *s; - - writew(0xaa, base + 0x555); - writew(0x55, base + 0xaaa); - writew(0xa0, base + 0x555); - writew(word, p); - - sync_write_buffer(); - - /* Wait for completion */ - status1 = readw(p); - do { - /* TODO: Timeout */ - status = status1; - status1 = readw(p); - } while (((status ^ status1) & 0x40) /* toggled */ - && !(status1 & 0x28)); /* error bits */ - - /* - * We'll need to check once again for toggle bit - * because the toggle bit may stop toggling as I/O5 - * changes to "1" (ref at49bv642.pdf p9) - */ - status1 = readw(p); - status = readw(p); - if ((status ^ status1) & 0x40) { - printf("Flash write error at address 0x%p: " - "0x%02x != 0x%02x\n", - p, status,word); - ret = ERR_PROG_ERROR; - writew(0xf0, base); - readw(base); - break; - } - - writew(0xf0, base); - readw(base); - } - - if (flags) - enable_interrupts(); - - return ret; -} - -#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */ diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 5fa5d6a4de..d406c83481 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -191,7 +191,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* MX6_LOCLED# */ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* GPS_SHDN */ @@ -204,11 +205,17 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* PCI_RST# (GW522x) */ IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -227,36 +234,46 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* MX6_LOCLED# */ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), /* MIPI_DIO */ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), /* RS485_EN */ IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), /* IOEXP_PWREN# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ - IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* VID_EN */ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw551x_gpio_pads[] = { + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLED# */ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* PCI_RST# */ @@ -266,6 +283,10 @@ static iomux_v3_cfg_t const gw551x_gpio_pads[] = { }; static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* USBOTG_SEL */ + IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -522,12 +543,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, .dio_cfg = { { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, IMX_GPIO_NR(1, 19), { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, @@ -539,12 +554,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 3 }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, }, .num_gpios = 2, .leds = { @@ -560,6 +569,12 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, .dio_cfg = { { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, IMX_GPIO_NR(1, 19), { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, @@ -571,6 +586,12 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, 3 }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, }, .num_gpios = 4, .leds = { @@ -579,6 +600,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { IMX_GPIO_NR(4, 15), }, .pcie_rst = IMX_GPIO_NR(1, 29), + .usb_sel = IMX_GPIO_NR(1, 7), .wdis = IMX_GPIO_NR(7, 12), }, }; @@ -712,7 +734,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info) * Configure DIO pinmux/padctl registers * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions */ - for (i = 0; i < 4; i++) { + for (i = 0; i < gpio_cfg[board].num_gpios; i++) { struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; iomux_v3_cfg_t ctrl = DIO_PAD_CFG; unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index b7c0e96f2d..28f58160de 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -34,10 +34,6 @@ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -46,7 +42,7 @@ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) +#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION) #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 22f3b3860b..3b7c82b1dc 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -157,20 +157,18 @@ static iomux_v3_cfg_t const usb_pads[] = { int board_ehci_hcd_init(int port) { - struct ventana_board_info *info = &ventana_info; int gpio; SETUP_IOMUX_PADS(usb_pads); - /* Reset USB HUB (present on GW54xx/GW53xx) */ - switch (info->model[3]) { - case '3': /* GW53xx */ - case '5': /* GW552x */ - SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); + /* Reset USB HUB */ + switch (board_type) { + case GW53xx: + case GW552x: gpio = (IMX_GPIO_NR(1, 9)); break; - case '4': /* GW54xx */ - SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); + case GW54proto: + case GW54xx: gpio = (IMX_GPIO_NR(1, 16)); break; default: @@ -687,8 +685,7 @@ int misc_init_r(void) memset(str, 0, sizeof(str)); for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) str[i] = tolower(info->model[i]); - if (!getenv("model")) - setenv("model", str); + setenv("model", str); if (!getenv("fdt_file")) { sprintf(fdt, "%s-%s.dtb", cputype, str); setenv("fdt_file", fdt); @@ -698,18 +695,14 @@ int misc_init_r(void) *p++ = 0; setenv("model_base", str); - if (!getenv("fdt_file1")) { - sprintf(fdt, "%s-%s.dtb", cputype, str); - setenv("fdt_file1", fdt); - } + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file1", fdt); if (board_type != GW551x && board_type != GW552x) str[4] = 'x'; str[5] = 'x'; str[6] = 0; - if (!getenv("fdt_file2")) { - sprintf(fdt, "%s-%s.dtb", cputype, str); - setenv("fdt_file2", fdt); - } + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file2", fdt); } /* initialize env from EEPROM */ @@ -818,9 +811,11 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - /* Update partition nodes using info from mtdparts env var */ - puts(" Updating MTD partitions...\n"); - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + if (test_bit(EECONFIG_NAND, info->config)) { + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + } /* Update display timings from display env var */ if (display) { @@ -829,10 +824,6 @@ int ft_board_setup(void *blob, bd_t *bd) printf(" Set display timings for %s...\n", display); } - if (!model) { - puts("invalid board info: Leaving FDT fully enabled\n"); - return 0; - } printf(" Adjusting FDT per EEPROM for %s...\n", model); /* board serial number */ diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 9f5d2b17cd..d4418e554c 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -515,10 +515,8 @@ void board_init_f(ulong dummy) setup_iomux_gpio(board_model, &ventana_info); /* provide some some default: 32bit 128MB */ - if (GW_UNKNOWN == board_model) { - ventana_info.sdram_width = 2; - ventana_info.sdram_size = 3; - } + if (GW_UNKNOWN == board_model) + hang(); /* configure MMDC for SDRAM width/size and per-model calibration */ spl_dram_init(8 << ventana_info.sdram_width, diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index beb2fac374..d76c28bd3c 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -33,6 +33,46 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD +#define OSC (V_OSCK/1000000) + +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + static const struct ddr_data ddr2_data = { .datardsratio0 = MT47H128M16RT25E_RD_DQS, .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, @@ -56,6 +96,70 @@ static const struct emif_regs ddr2_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, }; +const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1}; + +const struct ctrl_ioregs ioregs_ddr2 = { + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, +}; + +static int read_eeprom(struct pepper_board_id *header) +{ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + return -ENODEV; + } + + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(struct pepper_board_id))) { + return -EIO; + } + + return 0; +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + struct pepper_board_id header; + + enable_i2c0_pin_mux(); + i2c_set_bus_num(0); + + if (read_eeprom(&header) < 0) + return &dpll_ddr3; + + switch (header.device_vendor) { + case GUMSTIX_PEPPER: + return &dpll_ddr2; + case GUMSTIX_PEPPER_DVI: + return &dpll_ddr3; + default: + return &dpll_ddr3; + } +} + +void sdram_init(void) +{ + const struct dpll_params *dpll = get_dpll_ddr_params(); + + /* + * Here we are assuming PLL clock reveals the type of RAM. + * DDR2 = 266 + * DDR3 = 400 + * Note that DDR3 is the default. + */ + if (dpll->m == 266) { + config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data, + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); + } + else if (dpll->m == 400) { + config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data, + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); + } +} + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { @@ -64,14 +168,6 @@ int spl_start_uboot(void) } #endif -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - void set_uart_mux_conf(void) { enable_uart0_pin_mux(); @@ -82,19 +178,7 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, - .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, -}; -void sdram_init(void) -{ - config_ddr(266, &ioregs, &ddr2_data, - &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -} #endif int board_init(void) diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h index 0512735a7b..a6df3196f4 100644 --- a/board/gumstix/pepper/board.h +++ b/board/gumstix/pepper/board.h @@ -9,6 +9,18 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +#define GUMSTIX_PEPPER 0x30000200 +#define GUMSTIX_PEPPER_DVI 0x31000200 + +struct pepper_board_id { + unsigned int device_vendor; + unsigned char revision; + unsigned char content; + char fab_revision[8]; + char env_var[16]; + char en_setting[64]; +}; + /* * We must be able to enable uart0, for initial output. We then have a * main pinmux function that can be overridden to enable all other pinmux that @@ -16,4 +28,5 @@ */ void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c index 50b12666d6..92c73f8df8 100644 --- a/board/gumstix/pepper/mux.c +++ b/board/gumstix/pepper/mux.c @@ -64,6 +64,11 @@ void enable_uart0_pin_mux(void) configure_module_pin_mux(uart0_pin_mux); } +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + /* * Do board-specific muxes. */ diff --git a/board/highbank/Makefile b/board/highbank/Makefile index d3eb23220b..ce7ee68d4a 100644 --- a/board/highbank/Makefile +++ b/board/highbank/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := highbank.o +obj-y := highbank.o ahci.o diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c new file mode 100644 index 0000000000..00153232f6 --- /dev/null +++ b/board/highbank/ahci.c @@ -0,0 +1,218 @@ +/* + * Copyright 2012 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <ahci.h> +#include <asm/io.h> + +#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f)) +#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2)) +#define CPHY_BASE 0xfff58000 +#define CPHY_WIDTH 0x1000 +#define CPHY_DTE_XS 5 +#define CPHY_MII 31 +#define SERDES_CR_CTL 0x80a0 +#define SERDES_CR_ADDR 0x80a1 +#define SERDES_CR_DATA 0x80a2 +#define CR_BUSY 0x0001 +#define CR_START 0x0001 +#define CR_WR_RDN 0x0002 +#define CPHY_TX_INPUT_STS 0x2001 +#define CPHY_RX_INPUT_STS 0x2002 +#define CPHY_SATA_TX_OVERRIDE_BIT 0x8000 +#define CPHY_SATA_RX_OVERRIDE_BIT 0x4000 +#define CPHY_TX_INPUT_OVERRIDE 0x2004 +#define CPHY_RX_INPUT_OVERRIDE 0x2005 +#define SPHY_LANE 0x100 +#define SPHY_HALF_RATE 0x0001 +#define CPHY_SATA_DPLL_MODE 0x0700 +#define CPHY_SATA_DPLL_SHIFT 8 +#define CPHY_SATA_TX_ATTEN 0x1c00 +#define CPHY_SATA_TX_ATTEN_SHIFT 10 + +#define HB_SREG_SATA_ATTEN 0xfff3cf24 + +#define SATA_PORT_BASE 0xffe08000 +#define SATA_VERSIONR 0xf8 +#define SATA_HB_VERSION 0x3332302a + +static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr) +{ + u32 data; + writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); + data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); + return data; +} + +static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data) +{ + writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy); + writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr)); +} + +static u32 combo_phy_read(u8 phy, u32 addr) +{ + u8 dev = CPHY_DTE_XS; + if (phy == 5) + dev = CPHY_MII; + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr); + __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START); + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA); +} + +static void combo_phy_write(u8 phy, u32 addr, u32 data) +{ + u8 dev = CPHY_DTE_XS; + if (phy == 5) + dev = CPHY_MII; + while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY) + udelay(5); + __combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr); + __combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data); + __combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START); +} + +static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) +{ + u32 tmp; + tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp &= ~CPHY_SATA_DPLL_MODE; + tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +static void cphy_tx_attenuation_override(u8 phy, u8 lane) +{ + u32 val; + u32 tmp; + u8 shift; + + shift = ((phy == 5) ? 4 : lane) * 4; + + val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf; + + if (val & 0x8) + return; + + tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +static void cphy_disable_port_overrides(u8 port) +{ + u32 tmp; + u8 lane = 0, phy = 0; + + if (port == 0) + phy = 5; + else if (port < 5) + lane = port - 1; + else + return; + tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); + + tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE); + tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT; + combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); +} + +void cphy_disable_overrides(void) +{ + int i; + u32 port_map; + + port_map = readl(0xffe08000 + HOST_PORTS_IMPL); + for (i = 0; i < 5; i++) { + if (port_map & (1 << i)) + cphy_disable_port_overrides(i); + } +} + +static void cphy_override_lane(u8 port) +{ + u32 tmp, k = 0; + u8 lane = 0, phy = 0; + + if (port == 0) + phy = 5; + else if (port < 5) + lane = port - 1; + else + return; + + do { + tmp = combo_phy_read(0, CPHY_RX_INPUT_STS + + lane * SPHY_LANE); + } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); + cphy_spread_spectrum_override(phy, lane, 3); + cphy_tx_attenuation_override(phy, lane); +} + +#define WAIT_MS_LINKUP 4 + +int ahci_link_up(struct ahci_probe_ent *probe_ent, int port) +{ + u32 tmp; + int j = 0; + u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; + u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) == + SATA_HB_VERSION ? 1 : 0; + + /* Bring up SATA link. + * SATA link bringup time is usually less than 1 ms; only very + * rarely has it taken between 1-2 ms. Never seen it above 2 ms. + */ + while (j < WAIT_MS_LINKUP) { + if (is_highbank && (j == 0)) { + cphy_disable_port_overrides(port); + writel(0x301, port_mmio + PORT_SCR_CTL); + udelay(1000); + writel(0x300, port_mmio + PORT_SCR_CTL); + udelay(1000); + cphy_override_lane(port); + } + + tmp = readl(port_mmio + PORT_SCR_STAT); + if ((tmp & 0xf) == 0x3) + return 0; + udelay(1000); + j++; + + if ((j == WAIT_MS_LINKUP) && (tmp & 0xf)) + j = 0; /* retry phy reset */ + } + return 1; +} diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index ba1beb5bbc..469ee8e114 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -14,9 +14,11 @@ #define HB_AHCI_BASE 0xffe08000 +#define HB_SCU_A9_PWR_STATUS 0xfff10008 #define HB_SREG_A9_PWR_REQ 0xfff3cf00 #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 #define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20 +#define HB_SREG_A15_PWR_CTRL 0xfff3c200 #define HB_PWR_SUSPEND 0 #define HB_PWR_SOFT_RESET 1 @@ -27,8 +29,14 @@ #define PWRDOM_STAT_PCI 0x40000000 #define PWRDOM_STAT_EMMC 0x20000000 +#define HB_SCU_A9_PWR_NORMAL 0 +#define HB_SCU_A9_PWR_DORMANT 2 +#define HB_SCU_A9_PWR_OFF 3 + DECLARE_GLOBAL_DATA_PTR; +void cphy_disable_overrides(void); + /* * Miscellaneous platform dependent initialisations */ @@ -56,6 +64,7 @@ void scsi_init(void) { u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); + cphy_disable_overrides(); if (reg & PWRDOM_STAT_SATA) { ahci_init((void __iomem *)HB_AHCI_BASE); scsi_scan(1); @@ -111,9 +120,31 @@ int ft_board_setup(void *fdt, bd_t *bd) } #endif +static int is_highbank(void) +{ + uint32_t midr; + + asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); + + return (midr & 0xfff0) == 0xc090; +} + void reset_cpu(ulong addr) { writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); + if (is_highbank()) + writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS); + else + writel(0x1, HB_SREG_A15_PWR_CTRL); wfi(); } + +/* + * turn off the override before transferring control to Linux, since Linux + * may not support spread spectrum. + */ +void arch_preboot_os(void) +{ + cphy_disable_overrides(); +} diff --git a/board/mimc/mimc200/Kconfig b/board/mimc/mimc200/Kconfig deleted file mode 100644 index 18736d7f96..0000000000 --- a/board/mimc/mimc200/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MIMC200 - -config SYS_BOARD - default "mimc200" - -config SYS_VENDOR - default "mimc" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "mimc200" - -endif diff --git a/board/mimc/mimc200/MAINTAINERS b/board/mimc/mimc200/MAINTAINERS deleted file mode 100644 index 6cb51dd3cb..0000000000 --- a/board/mimc/mimc200/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MIMC200 BOARD -M: Mark Jackson <mpfj@mimc.co.uk> -S: Maintained -F: board/mimc/mimc200/ -F: include/configs/mimc200.h -F: configs/mimc200_defconfig diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile deleted file mode 100644 index 5c30c0dbca..0000000000 --- a/board/mimc/mimc200/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2005-2006 Atmel Corporation -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := mimc200.o diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c deleted file mode 100644 index f078295508..0000000000 --- a/board/mimc/mimc200/mimc200.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <netdev.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> -#include <atmel_lcdc.h> -#include <lcd.h> - -#include "../../../arch/avr32/cpu/hsmc3.h" - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT, - .phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -#if defined(CONFIG_LCD) -/* 480x272x16 @ 72 Hz */ -vidinfo_t panel_info = { - .vl_col = 480, /* Number of columns */ - .vl_row = 272, /* Number of rows */ - .vl_clk = 5000000, /* pixel clock in ps */ - .vl_sync = ATMEL_LCDC_INVCLK_INVERTED | - ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - .vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */ - .vl_tft = 1, /* 0 = passive, 1 = TFT */ - .vl_hsync_len = 42, /* Length of horizontal sync */ - .vl_left_margin = 1, /* Time from sync to picture */ - .vl_right_margin = 1, /* Time from picture to sync */ - .vl_vsync_len = 1, /* Length of vertical sync */ - .vl_upper_margin = 12, /* Time from sync to picture */ - .vl_lower_margin = 1, /* Time from picture to sync */ - .mmio = LCDC_BASE, /* Memory mapped registers */ -}; - -void lcd_enable(void) -{ -} - -void lcd_disable(void) -{ -} -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static const struct sdram_config sdram_config = { - .data_bits = SDRAM_DATA_16BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 6, - .trp = 2, - .trcd = 2, - .tras = 6, - .txsr = 6, - /* 15.6 us */ - .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, -}; - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - /* Enable 26 address bits and NCS2 */ - portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH); - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart1(PORTMUX_DRIVE_MIN); - - /* de-assert "force sys reset" pin */ - portmux_select_gpio(PORTMUX_PORT_D, 1 << 15, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - - /* init custom i/o */ - /* cpu type inputs */ - portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23), - PORTMUX_DIR_INPUT); - /* main board type inputs */ - portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29), - PORTMUX_DIR_INPUT); - /* DEBUG input (use weak pullup) */ - portmux_select_gpio(PORTMUX_PORT_E, 1 << 21, - PORTMUX_DIR_INPUT | PORTMUX_PULL_UP); - - /* are we suppressing the console ? */ - if (gpio_get_value(GPIO_PIN_PE(21)) == 1) - gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE); - - /* reset phys */ - portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT); - portmux_select_gpio(PORTMUX_PORT_C, 1 << 18, - PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - - udelay(5000); - - /* release phys reset */ - gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */ - - /* setup Data Flash chip select (NCS2) */ - hsmc3_writel(MODE2, 0x20121003); - hsmc3_writel(CYCLE2, 0x000a0009); - hsmc3_writel(PULSE2, 0x0a060806); - hsmc3_writel(SETUP2, 0x00030102); - - /* setup FRAM chip select (NCS3) */ - hsmc3_writel(MODE3, 0x10120001); - hsmc3_writel(CYCLE3, 0x001e001d); - hsmc3_writel(PULSE3, 0x08040704); - hsmc3_writel(SETUP3, 0x02050204); - -#if defined(CONFIG_MACB) - /* init macb0 pins */ - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); - portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif - -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif - -#if defined(CONFIG_LCD) - portmux_enable_lcdc(1); -#endif - - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - gd->bd->bi_phy_id[1] = 0x03; - return 0; -} - -int board_postclk_init(void) -{ - /* Use GCLK0 as 10MHz output */ - gclk_enable_output(0, PORTMUX_DRIVE_LOW); - gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000); - return 0; -} - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#include <spi.h> - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return (bus == 0) && (cs == 0); -} - -void spi_cs_activate(struct spi_slave *slave) -{ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ -} -#endif /* CONFIG_ATMEL_SPI */ - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bi) -{ - macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); - - return 0; -} -#endif diff --git a/board/miromico/hammerhead/Kconfig b/board/miromico/hammerhead/Kconfig deleted file mode 100644 index 1f09ef782e..0000000000 --- a/board/miromico/hammerhead/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_HAMMERHEAD - -config SYS_BOARD - default "hammerhead" - -config SYS_VENDOR - default "miromico" - -config SYS_SOC - default "at32ap700x" - -config SYS_CONFIG_NAME - default "hammerhead" - -endif diff --git a/board/miromico/hammerhead/MAINTAINERS b/board/miromico/hammerhead/MAINTAINERS deleted file mode 100644 index a87ceeeb73..0000000000 --- a/board/miromico/hammerhead/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -HAMMERHEAD BOARD -M: Alex Raimondi <alex.raimondi@miromico.ch> -S: Maintained -F: board/miromico/hammerhead/ -F: include/configs/hammerhead.h -F: configs/hammerhead_defconfig diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile deleted file mode 100644 index 638a9df930..0000000000 --- a/board/miromico/hammerhead/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (C) 2008 Miromico AG -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := hammerhead.o diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c deleted file mode 100644 index a0c7d3b323..0000000000 --- a/board/miromico/hammerhead/hammerhead.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2008 Miromico AG - * - * Mostly copied form atmel ATNGW100 sources - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> - -#include <asm/io.h> -#include <asm/sdram.h> -#include <asm/arch/clk.h> -#include <asm/arch/hmatrix.h> -#include <asm/arch/hardware.h> -#include <asm/arch/mmu.h> -#include <asm/arch/portmux.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { - { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_NONE, - }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) - | MMU_VMR_CACHE_WRBACK, - }, -}; - -static const struct sdram_config sdram_config = { - .data_bits = SDRAM_DATA_32BIT, - .row_bits = 13, - .col_bits = 9, - .bank_bits = 2, - .cas = 3, - .twr = 2, - .trc = 7, - .trp = 2, - .trcd = 2, - .tras = 5, - .txsr = 5, - /* 7.81 us */ - .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, -}; - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, - bis->bi_phy_id[0]); -} -#endif - -int board_early_init_f(void) -{ - /* Enable SDRAM in the EBI mux */ - hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - - portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); - sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); - - portmux_enable_usart1(PORTMUX_DRIVE_MIN); - -#if defined(CONFIG_MACB) - portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); -#endif -#if defined(CONFIG_MMC) - portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); -#endif - return 0; -} - -int board_early_init_r(void) -{ - gd->bd->bi_phy_id[0] = 0x01; - return 0; -} - -int board_postclk_init(void) -{ - /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ - gclk_enable_output(3, PORTMUX_DRIVE_LOW); - gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000); - return 0; -} diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S index 9d4ea1b3f9..420ad13a12 100644 --- a/board/nokia/rx51/lowlevel_init.S +++ b/board/nokia/rx51/lowlevel_init.S @@ -105,10 +105,6 @@ fix_start: /* r6 - maximal u-boot size */ ldr r6, imagesize - /* fix return address */ - subhi lr, lr, r5 - addlo lr, lr, r5 - /* r1 - start of u-boot after */ ldr r1, startaddr diff --git a/board/nvidia/nyan-big/MAINTAINERS b/board/nvidia/nyan-big/MAINTAINERS index ff74627af2..779077729c 100644 --- a/board/nvidia/nyan-big/MAINTAINERS +++ b/board/nvidia/nyan-big/MAINTAINERS @@ -1,4 +1,4 @@ -NORRIN BOARD +NYAN-BIG BOARD M: Allen Martin <amartin@nvidia.com> S: Maintained F: board/nvidia/nyan-big/ diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ae8874bbd2..ba96401890 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -8,7 +8,12 @@ #include <common.h> #include <errno.h> #include <asm/gpio.h> +#include <asm/io.h> #include <asm/arch/pinmux.h> +#include <asm/arch/clock.h> +#include <asm/arch/mc.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra/pmc.h> #include <power/as3722.h> #include <power/pmic.h> #include "pinmux-config-nyan-big.h" @@ -57,3 +62,67 @@ int tegra_lcd_pmic_init(int board_id) return 0; } + +/* Setup required information for Linux kernel */ +static void setup_kernel_info(void) +{ + struct mc_ctlr *mc = (void *)NV_PA_MC_BASE; + + /* The kernel graphics driver needs this region locked down */ + writel(0, &mc->mc_video_protect_bom); + writel(0, &mc->mc_video_protect_size_mb); + writel(1, &mc->mc_video_protect_reg_ctrl); +} + +/* + * We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF, + * I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks. + * Otherwise reading AHUB devices will hang when the kernel boots. + */ +static void enable_required_clocks(void) +{ + static enum periph_id ids[] = { + PERIPH_ID_I2S0, + PERIPH_ID_I2S1, + PERIPH_ID_I2S2, + PERIPH_ID_I2S3, + PERIPH_ID_I2S4, + PERIPH_ID_AUDIO, + PERIPH_ID_APBIF, + PERIPH_ID_DAM0, + PERIPH_ID_DAM1, + PERIPH_ID_DAM2, + PERIPH_ID_AMX0, + PERIPH_ID_AMX1, + PERIPH_ID_ADX0, + PERIPH_ID_ADX1, + PERIPH_ID_SPDIF, + PERIPH_ID_AFC0, + PERIPH_ID_AFC1, + PERIPH_ID_AFC2, + PERIPH_ID_AFC3, + PERIPH_ID_AFC4, + PERIPH_ID_AFC5, + PERIPH_ID_EXTPERIPH1 + }; + int i; + + for (i = 0; i < ARRAY_SIZE(ids); i++) + clock_enable(ids[i]); + udelay(2); + for (i = 0; i < ARRAY_SIZE(ids); i++) + reset_set_enable(ids[i], 0); +} + +int nvidia_board_init(void) +{ + clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000); + clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000); + + /* For external MAX98090 audio codec */ + clock_external_output(1); + setup_kernel_info(); + enable_required_clocks(); + + return 0; +} diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 4aae230608..d7b9e5af88 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -148,6 +148,29 @@ static const struct dpll_params idk_dpll_ddr = { 400, 23, 1, -1, 2, -1, -1 }; +static const u32 ext_phy_ctrl_const_base_lpddr2[] = { + 0x00500050, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00350035, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40001000, + 0x08102040 +}; + const struct ctrl_ioregs ioregs_lpddr2 = { .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, @@ -318,6 +341,16 @@ static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { .emif_cos_config = 0x00ffffff }; +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + if (board_is_eposevm()) { + *regs = ext_phy_ctrl_const_base_lpddr2; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); + } + + return; +} + /* * get_sys_clk_index : returns the index of the sys_clk read from * ctrl status register. This value is either diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index ffcd53185b..b6c17ec83f 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -15,6 +15,7 @@ #include <asm/omap_common.h> #include <asm/emif.h> #include <asm/arch/clock.h> +#include <asm/arch/dra7xx_iodelay.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -52,23 +53,29 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00740074, .emif_ddr_ext_phy_ctrl_3 = 0x00780078, .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; +/* Ext phy ctrl regs 1-35 */ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00740074, + 0x00780078, + 0x007c007c, + 0x007b007b, 0x00800080, 0x00360036, 0x00340034, @@ -90,14 +97,19 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x00400040, 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { @@ -109,23 +121,28 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050001, + .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190b, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0e24400a, - .emif_ddr_phy_ctlr_1 = 0x0e24400a, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00820082, .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, .emif_ddr_ext_phy_ctrl_4 = 0x00800080, .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, .emif_rd_wr_exec_thresh = 0x00000305 }; static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00820082, + 0x008b008b, + 0x00800080, + 0x007e007e, 0x00800080, 0x00370037, 0x00390039, @@ -145,14 +162,19 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { 0x00000000, 0x00600020, - 0x40010080, + 0x40011080, 0x08102040, 0x00400040, 0x00400040, 0x00400040, 0x00400040, - 0x00400040 + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) @@ -240,23 +262,20 @@ int board_late_init(void) return 0; } -static void do_set_mux32(u32 base, - struct pad_conf_entry const *array, int size) +void set_muxconf_regs_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *)array; - - for (i = 0; i < size; i++, pad++) - writel(pad->val, base + pad->offset); + do_set_mux32((*ctrl)->control_padconf_core_base, + early_padconf, ARRAY_SIZE(early_padconf)); } -void set_muxconf_regs_essential(void) +#ifdef CONFIG_IODELAY_RECALIBRATION +void recalibrate_iodelay(void) { - do_set_mux32((*ctrl)->control_padconf_core_base, - core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); + __recalibrate_iodelay(core_padconf_array_essential, + ARRAY_SIZE(core_padconf_array_essential), + iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array)); } +#endif #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h index df658c5211..09d3650983 100644 --- a/board/ti/beagle_x15/mux_data.h +++ b/board/ti/beagle_x15/mux_data.h @@ -13,43 +13,318 @@ #include <asm/arch/mux_dra7xx.h> const struct pad_conf_entry core_padconf_array_essential[] = { - {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ - {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ - {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ - {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ - {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ - {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ - {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ - {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ - {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ - {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ - {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ - {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ - {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ - {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ - {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ - {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ - {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ - {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ - {UART2_CTSN, (FSC | IEN | PTU | PDIS | M2)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (FSC | IEN | PTU | PDIS | M1)}, /* uart2_rtsn.uart3_txd */ - {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ - {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ - {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ - {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ - {RGMII0_TXC, (M0) }, - {RGMII0_TXCTL, (M0) }, - {RGMII0_TXD3, (M0) }, - {RGMII0_TXD2, (M0) }, - {RGMII0_TXD1, (M0) }, - {RGMII0_TXD0, (M0) }, - {RGMII0_RXC, (IEN | M0) }, - {RGMII0_RXCTL, (IEN | M0) }, - {RGMII0_RXD3, (IEN | M0) }, - {RGMII0_RXD2, (IEN | M0) }, - {RGMII0_RXD1, (IEN | M0) }, - {RGMII0_RXD0, (IEN | M0) }, - {USB1_DRVVBUS, (M0 | FSC) }, - {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */ + {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */ + {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */ + {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */ + {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */ + {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */ + {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */ + {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */ + {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */ + {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */ + {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */ + {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */ + {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */ + {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */ + {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */ + {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */ + {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */ + {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */ + {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */ + {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */ + {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */ + {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */ + {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */ + {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */ + {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */ + {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */ + {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */ + {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */ + {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */ + {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */ + {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */ + {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */ + {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */ + {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */ + {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */ + {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */ + {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */ + {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */ + {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */ + {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */ + {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */ + {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ + {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */ + {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */ + {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */ + {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */ + {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */ + {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */ + {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */ + {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */ + {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */ + {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */ + {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */ + {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */ + {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */ + {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */ + {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */ + {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */ + {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */ + {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */ + {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */ + {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */ + {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */ + {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */ + {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ + {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */ + {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */ + {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */ + {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */ + {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */ + {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */ + {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */ + {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */ + {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */ + {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */ + {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */ + {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */ + {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ + {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */ + {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */ + {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */ + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */ + {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */ + {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */ + {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */ + {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */ + {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ + {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */ + {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */ + {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */ + {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */ + {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */ + {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */ + {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */ + {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */ + {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */ + {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */ + {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */ + {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */ + {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */ + {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */ + {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */ + {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */ + {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */ + {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */ + {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */ + {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */ + {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */ + {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */ + {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */ + {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */ + {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */ + {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */ + {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */ + {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */ + {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */ + {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */ + {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */ + {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */ + {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */ + {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ + {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ + {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ + {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ + {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */ + {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */ + {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */ + {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */ + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ + {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ }; + +const struct pad_conf_entry early_padconf[] = { + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry iodelay_cfg_array[] = { + {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */ + {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */ + {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */ + {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */ + {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */ + {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */ + {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */ + {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */ + {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */ + {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */ + {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */ + {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */ + {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */ + {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */ + {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */ + {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */ + {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */ + {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */ + {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */ + {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */ + {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */ + {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */ + {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */ + {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */ + {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */ + {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */ + {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */ + {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ +}; +#endif #endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d4648558ec..94a1a8c256 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -17,6 +17,7 @@ #include <usb.h> #include <linux/usb/gadget.h> #include <asm/arch/gpio.h> +#include <asm/arch/dra7xx_iodelay.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sata.h> @@ -40,43 +41,6 @@ const struct omap_sysinfo sysinfo = { "Board: DRA7xx\n" }; -/* - * Adjust I/O delays on the Tx control and data lines of each MAC port. This - * is a workaround in order to work properly with the DP83865 PHYs on the EVM. - * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we - * essentially need to counteract the DRA7xx internal delay, and we do this - * by delaying the control and data lines. If not using this PHY, you probably - * don't need to do this stuff! - */ -static void dra7xx_adj_io_delay(const struct io_delay *io_dly) -{ - int i = 0; - u32 reg_val; - u32 delta; - u32 coarse; - u32 fine; - - writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); - - while(io_dly[i].addr) { - writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, - io_dly[i].addr); - delta = io_dly[i].dly; - reg_val = readl(io_dly[i].addr) & 0x3ff; - coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); - coarse = (coarse > 0x1F) ? (0x1F) : (coarse); - fine = (reg_val & 0x1F) + (delta & 0x1F); - fine = (fine > 0x1F) ? (0x1F) : (fine); - reg_val = CFG_IO_DELAY_ACCESS_PATTERN | - CFG_IO_DELAY_LOCK_MASK | - ((coarse << 5) | (fine)); - writel(reg_val, io_dly[i].addr); - i++; - } - - writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); -} - /** * @brief board_init * @@ -107,23 +71,28 @@ int board_late_init(void) return 0; } -static void do_set_mux32(u32 base, - struct pad_conf_entry const *array, int size) +void set_muxconf_regs_essential(void) { - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *)array; - - for (i = 0; i < size; i++, pad++) - writel(pad->val, base + pad->offset); + do_set_mux32((*ctrl)->control_padconf_core_base, + early_padconf, ARRAY_SIZE(early_padconf)); } -void set_muxconf_regs_essential(void) +#ifdef CONFIG_IODELAY_RECALIBRATION +void recalibrate_iodelay(void) { - do_set_mux32((*ctrl)->control_padconf_core_base, - core_padconf_array_essential, - sizeof(core_padconf_array_essential) / - sizeof(struct pad_conf_entry)); + if (is_dra72x()) { + __recalibrate_iodelay(core_padconf_array_essential, + ARRAY_SIZE(core_padconf_array_essential), + iodelay_cfg_array, + ARRAY_SIZE(iodelay_cfg_array)); + } else { + __recalibrate_iodelay(dra74x_core_padconf_array, + ARRAY_SIZE(dra74x_core_padconf_array), + dra742_iodelay_cfg_array, + ARRAY_SIZE(dra742_iodelay_cfg_array)); + } } +#endif #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) @@ -257,19 +226,6 @@ int spl_start_uboot(void) #endif #ifdef CONFIG_DRIVER_TI_CPSW - -/* Delay value to add to calibrated value */ -#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) -#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) -#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) -#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) - extern u32 *const omap_si_rev; static void cpsw_control(int enabled) @@ -317,22 +273,6 @@ int board_eth_init(bd_t *bis) uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; - const struct io_delay io_dly[] = { - {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, - {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, - {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, - {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, - {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, - {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, - {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, - {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, - {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, - {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, - {0} - }; - - /* Adjust IO delay for RGMII tx path */ - dra7xx_adj_io_delay(io_dly); /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 48240779c9..c9301a51c0 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -76,30 +76,30 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */ - {RGMII0_TXC, (M0) }, - {RGMII0_TXCTL, (M0) }, - {RGMII0_TXD3, (M0) }, - {RGMII0_TXD2, (M0) }, - {RGMII0_TXD1, (M0) }, - {RGMII0_TXD0, (M0) }, - {RGMII0_RXC, (IEN | M0) }, - {RGMII0_RXCTL, (IEN | M0) }, - {RGMII0_RXD3, (IEN | M0) }, - {RGMII0_RXD2, (IEN | M0) }, - {RGMII0_RXD1, (IEN | M0) }, - {RGMII0_RXD0, (IEN | M0) }, - {VIN2A_D12, (M3) }, - {VIN2A_D13, (M3) }, - {VIN2A_D14, (M3) }, - {VIN2A_D15, (M3) }, - {VIN2A_D16, (M3) }, - {VIN2A_D17, (M3) }, - {VIN2A_D18, (IEN | M3)}, - {VIN2A_D19, (IEN | M3)}, - {VIN2A_D20, (IEN | M3)}, - {VIN2A_D21, (IEN | M3)}, - {VIN2A_D22, (IEN | M3)}, - {VIN2A_D23, (IEN | M3)}, + {RGMII0_TXC, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXCTL, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD3, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD2, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD1, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_TXD0, (PIN_OUTPUT | MANUAL_MODE | M0) }, + {RGMII0_RXC, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXCTL, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD3, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD2, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD1, (PIN_INPUT | MANUAL_MODE | M0) }, + {RGMII0_RXD0, (PIN_INPUT | MANUAL_MODE | M0) }, + {VIN2A_D12, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D13, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D14, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D15, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D16, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D17, (PIN_OUTPUT | MANUAL_MODE | M3) }, + {VIN2A_D18, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D19, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D20, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D21, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D22, (PIN_INPUT | MANUAL_MODE | M3)}, + {VIN2A_D23, (PIN_INPUT | MANUAL_MODE | M3)}, #if defined(CONFIG_NAND) || defined(CONFIG_NOR) /* NAND / NOR pin-mux */ {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ @@ -141,4 +141,295 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {USB2_DRVVBUS, (M0 | IEN | FSC) }, {SPI1_CS1, (PEN | IDIS | M14) }, }; + +const struct pad_conf_entry early_padconf[] = { +#if (CONFIG_CONS_INDEX == 1) + {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ + {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ +#elif (CONFIG_CONS_INDEX == 3) + {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */ + {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */ +#endif + {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry iodelay_cfg_array[] = { + {0x6F0, 480, 0}, /* RGMMI0_RXC_IN */ + {0x6FC, 111, 1641}, /* RGMMI0_RXCTL_IN */ + {0x708, 272, 1116}, /* RGMMI0_RXD0_IN */ + {0x714, 243, 1260}, /* RGMMI0_RXD1_IN */ + {0x720, 0, 1614}, /* RGMMI0_RXD2_IN */ + {0x72C, 105, 1673}, /* RGMMI0_RXD3_IN */ + {0x740, 531, 120}, /* RGMMI0_TXC_OUT */ + {0x74C, 11, 60}, /* RGMMI0_TXCTL_OUT */ + {0x758, 7, 120}, /* RGMMI0_TXD0_OUT */ + {0x764, 0, 0}, /* RGMMI0_TXD1_OUT */ + {0x770, 276, 120}, /* RGMMI0_TXD2_OUT */ + {0x77C, 440, 120}, /* RGMMI0_TXD3_OUT */ + {0xAB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0xABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0xAD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0xAE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0xAEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0xAF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ + {0xA70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ + {0xA7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ + {0xA88, 876, 0}, /* CFG_VIN2A_D14_OUT */ + {0xA94, 312, 0}, /* CFG_VIN2A_D15_OUT */ + {0xAA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ + {0xAAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ +}; +#endif + +const struct pad_conf_entry dra74x_core_padconf_array[] = { + {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ + {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ + {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ + {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */ + {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */ + {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */ + {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */ + {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */ + {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */ + {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */ + {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */ + {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */ + {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */ + {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */ + {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */ + {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */ + {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */ + {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */ + {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */ + {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */ + {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */ + {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */ + {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */ + {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */ + {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */ + {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */ + {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */ + {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */ + {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */ + {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */ + {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */ + {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */ + {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */ + {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */ + {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */ + {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */ + {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */ + {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */ + {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */ + {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */ + {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */ + {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */ + {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */ + {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */ + {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */ + {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */ + {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */ + {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */ + {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */ + {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */ + {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */ + {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */ + {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */ + {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */ + {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */ + {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */ + {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */ + {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */ + {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ + {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ + {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */ + {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */ + {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */ + {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */ + {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ + {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ + {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ + {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ + {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ + {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ + {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ + {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */ + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */ + {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */ + {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */ + {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */ + {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */ + {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ + {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ + {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ + {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */ + {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = { + {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */ + {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */ + {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */ + {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */ + {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */ + {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */ + {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */ + {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */ + {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */ + {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */ + {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */ + {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */ + {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */ + {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */ + {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */ + {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */ + {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */ + {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */ + {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */ + {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */ + {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */ + {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */ + {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */ + {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */ + {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */ + {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */ + {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */ + {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */ + {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */ + {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ +}; +#endif + #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 551c575c9d..a1217a47bd 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -4,3 +4,7 @@ S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h F: configs/colibri_vf_defconfig +F: configs/colibri_vf_dtb_defconfig +F: arch/arm/dts/vf-colibri.dtsi +F: arch/arm/dts/vf500-colibri.dts +F: arch/arm/dts/vf610-colibri.dts diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 31ebb1935f..8618fd068c 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -20,6 +20,7 @@ #include <netdev.h> #include <i2c.h> #include <g_dnl.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -32,6 +33,12 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) +#define USB_PEN_GPIO 83 + +static const iomux_v3_cfg_t usb_pads[] = { + VF610_PAD_PTD4__GPIO_83, +}; + int dram_init(void) { static const struct ddr3_jedec_timings timings = { @@ -146,6 +153,76 @@ static void setup_iomux_nfc(void) } #endif +#ifdef CONFIG_FSL_DSPI +static void setup_iomux_dspi(void) +{ + static const iomux_v3_cfg_t dspi1_pads[] = { + VF610_PAD_PTD5__DSPI1_CS0, + VF610_PAD_PTD6__DSPI1_SIN, + VF610_PAD_PTD7__DSPI1_SOUT, + VF610_PAD_PTD8__DSPI1_SCK, + }; + + imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); +} +#endif + +#ifdef CONFIG_VYBRID_GPIO +static void setup_iomux_gpio(void) +{ + static const iomux_v3_cfg_t gpio_pads[] = { + VF610_PAD_PTA17__GPIO_7, + VF610_PAD_PTA20__GPIO_10, + VF610_PAD_PTA21__GPIO_11, + VF610_PAD_PTA30__GPIO_20, + VF610_PAD_PTA31__GPIO_21, + VF610_PAD_PTB0__GPIO_22, + VF610_PAD_PTB1__GPIO_23, + VF610_PAD_PTB6__GPIO_28, + VF610_PAD_PTB7__GPIO_29, + VF610_PAD_PTB8__GPIO_30, + VF610_PAD_PTB9__GPIO_31, + VF610_PAD_PTB12__GPIO_34, + VF610_PAD_PTB13__GPIO_35, + VF610_PAD_PTB16__GPIO_38, + VF610_PAD_PTB17__GPIO_39, + VF610_PAD_PTB18__GPIO_40, + VF610_PAD_PTB21__GPIO_43, + VF610_PAD_PTB22__GPIO_44, + VF610_PAD_PTC0__GPIO_45, + VF610_PAD_PTC1__GPIO_46, + VF610_PAD_PTC2__GPIO_47, + VF610_PAD_PTC3__GPIO_48, + VF610_PAD_PTC4__GPIO_49, + VF610_PAD_PTC5__GPIO_50, + VF610_PAD_PTC6__GPIO_51, + VF610_PAD_PTC7__GPIO_52, + VF610_PAD_PTC8__GPIO_53, + VF610_PAD_PTD31__GPIO_63, + VF610_PAD_PTD30__GPIO_64, + VF610_PAD_PTD29__GPIO_65, + VF610_PAD_PTD28__GPIO_66, + VF610_PAD_PTD27__GPIO_67, + VF610_PAD_PTD26__GPIO_68, + VF610_PAD_PTD25__GPIO_69, + VF610_PAD_PTD24__GPIO_70, + VF610_PAD_PTD9__GPIO_88, + VF610_PAD_PTD10__GPIO_89, + VF610_PAD_PTD11__GPIO_90, + VF610_PAD_PTD12__GPIO_91, + VF610_PAD_PTD13__GPIO_92, + VF610_PAD_PTB23__GPIO_93, + VF610_PAD_PTB26__GPIO_96, + VF610_PAD_PTB28__GPIO_98, + VF610_PAD_PTC29__GPIO_102, + VF610_PAD_PTC30__GPIO_103, + VF610_PAD_PTA7__GPIO_134, + }; + + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, @@ -196,6 +273,9 @@ static void clock_init(void) clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART0_CTRL_MASK); +#ifdef CONFIG_FSL_DSPI + setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); +#endif clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, @@ -304,6 +384,14 @@ int board_early_init_f(void) setup_iomux_nfc(); #endif +#ifdef CONFIG_VYBRID_GPIO + setup_iomux_gpio(); +#endif + +#ifdef CONFIG_FSL_DSPI + setup_iomux_dspi(); +#endif + return 0; } @@ -383,3 +471,21 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) return 0; } + +#ifdef CONFIG_USB_EHCI_VF +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + switch (port) { + case 0: + /* USBC does not have PEN, also configured as USB client only */ + break; + case 1: + gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); + gpio_direction_output(USB_PEN_GPIO, 0); + break; + } + return 0; +} +#endif diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig new file mode 100644 index 0000000000..bc1edcf3a4 --- /dev/null +++ b/board/vscom/baltos/Kconfig @@ -0,0 +1,24 @@ +if TARGET_AM335X_BALTOS + +config SYS_BOARD + default "baltos" + +config SYS_VENDOR + default "vscom" + +config SYS_SOC + default "am33xx" + +config SYS_CONFIG_NAME + default "baltos" + +config CONS_INDEX + int "UART used for console" + range 1 6 + default 1 + help + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced + in documentation, etc) available to it. Depending on your specific + board you may want something other than UART0. + +endif diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile new file mode 100644 index 0000000000..804ac379db --- /dev/null +++ b/board/vscom/baltos/Makefile @@ -0,0 +1,13 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),) +obj-y := mux.o +endif + +obj-y += board.o diff --git a/board/vscom/baltos/README b/board/vscom/baltos/README new file mode 100644 index 0000000000..f744ace997 --- /dev/null +++ b/board/vscom/baltos/README @@ -0,0 +1 @@ +BSP for VScom OnRISC Balios family devices, like Balios iR 5221. diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c new file mode 100644 index 0000000000..99ca60e2ac --- /dev/null +++ b/board/vscom/baltos/board.c @@ -0,0 +1,474 @@ +/* + * board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include <environment.h> +#include <watchdog.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO that controls power to DDR on EVM-SK */ +#define GPIO_DDR_VTT_EN 7 +#define DIP_S1 44 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int baltos_set_console(void) +{ + int val, i, dips = 0; + char buf[7]; + + for (i = 0; i < 4; i++) { + sprintf(buf, "dip_s%d", i + 1); + + if (gpio_request(DIP_S1 + i, buf)) { + printf("failed to export GPIO %d\n", DIP_S1 + i); + return 0; + } + + if (gpio_direction_input(DIP_S1 + i)) { + printf("failed to set GPIO %d direction\n", DIP_S1 + i); + return 0; + } + + val = gpio_get_value(DIP_S1 + i); + dips |= val << i; + } + + printf("DIPs: 0x%1x\n", (~dips) & 0xf); + + if ((dips & 0xf) == 0xe) + setenv("console", "ttyUSB0,115200n8"); + + return 0; +} + +static int read_eeprom(BSP_VS_HWPARAM *header) +{ + i2c_set_bus_num(1); + + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + puts("Could not probe the EEPROM; something fundamentally " + "wrong on the I2C bus.\n"); + return -ENODEV; + } + + /* read the eeprom using i2c */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + sizeof(BSP_VS_HWPARAM))) { + puts("Could not read the EEPROM; something fundamentally" + " wrong on the I2C bus.\n"); + return -EIO; + } + + if (header->Magic != 0xDEADBEEF) { + + printf("Incorrect magic number (0x%x) in EEPROM\n", + header->Magic); + + /* fill default values */ + header->SystemId = 211; + header->MAC1[0] = 0x00; + header->MAC1[1] = 0x00; + header->MAC1[2] = 0x00; + header->MAC1[3] = 0x00; + header->MAC1[4] = 0x00; + header->MAC1[5] = 0x01; + + header->MAC2[0] = 0x00; + header->MAC2[1] = 0x00; + header->MAC2[2] = 0x00; + header->MAC2[3] = 0x00; + header->MAC2[4] = 0x00; + header->MAC2[5] = 0x02; + + header->MAC3[0] = 0x00; + header->MAC3[1] = 0x00; + header->MAC3[2] = 0x00; + header->MAC3[3] = 0x00; + header->MAC3[4] = 0x00; + header->MAC3[5] = 0x03; + } + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + +static const struct ddr_data ddr3_baltos_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_baltos_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_baltos_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + return (serial_tstc() && serial_getc() == 'c'); +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_baltos = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + int sil_rev; + + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + i2c_set_bus_num(1); + + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { + puts("i2c: cannot access TPS65910\n"); + return; + } + + /* + * Depending on MPU clock and PG we will need a different + * VDD to drive at that speed. + */ + sil_rev = readl(&cdev->deviceid) >> 28; + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, + dpll_mpu_opp100.m); + + /* Tell the TPS65910 to use i2c */ + tps65910_set_i2c_control(); + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + + writel(0x000010ff, PRM_DEVICE_INST + 4); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + enable_i2c1_pin_mux(); + i2c_set_bus_num(1); + + return &dpll_ddr_baltos; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +const struct ctrl_ioregs ioregs_baltos = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +void sdram_init(void) +{ + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); + + config_ddr(400, &ioregs_baltos, + &ddr3_baltos_data, + &ddr3_baltos_cmd_ctrl_data, + &ddr3_baltos_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) + gpmc_init(); +#endif + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + int node, ret; + unsigned char mac_addr[6]; + BSP_VS_HWPARAM header; + + /* get production data */ + if (read_eeprom(&header)) + return 0; + + /* setup MAC1 */ + mac_addr[0] = header.MAC1[0]; + mac_addr[1] = header.MAC1[1]; + mac_addr[2] = header.MAC1[2]; + mac_addr[3] = header.MAC1[3]; + mac_addr[4] = header.MAC1[4]; + mac_addr[5] = header.MAC1[5]; + + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + /* setup MAC2 */ + mac_addr[0] = header.MAC2[0]; + mac_addr[1] = header.MAC2[1]; + mac_addr[2] = header.MAC2[2]; + mac_addr[3] = header.MAC2[3]; + mac_addr[4] = header.MAC2[4]; + mac_addr[5] = header.MAC2[5]; + + node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300"); + if (node < 0) { + printf("no /soc/fman/ethernet path offset\n"); + return -ENODEV; + } + + ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); + if (ret) { + printf("error setting local-mac-address property\n"); + return -ENODEV; + } + + printf("\nFDT was successfully setup\n"); + + return 0; +} + +static struct module_pin_mux dip_pin_mux[] = { + {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */ + {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */ + {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */ + {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */ + {-1}, +}; + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + BSP_VS_HWPARAM header; + char model[4]; + + /* get production data */ + if (read_eeprom(&header)) { + sprintf(model, "211"); + } else { + sprintf(model, "%d", header.SystemId); + if (header.SystemId == 215) { + configure_module_pin_mux(dip_pin_mux); + baltos_set_console(); + } + } + setenv("board_name", model); +#endif + + return 0; +} +#endif + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 7, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .active_slave = 1, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif + +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + __maybe_unused struct am335x_baseboard_id header; + + /* + * Note here that we're using CPSW1 since that has a 1Gbit PHY while + * CSPW0 has a 100Mbit PHY. + * + * On product, CPSW1 maps to port labeled WAN. + */ + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid1l); + mac_hi = readl(&cdev->macid1h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + +#ifdef CONFIG_DRIVER_TI_CPSW + writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel); + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + + /* + * + * CPSW RGMII Internal Delay Mode is not supported in all PVT + * operating points. So we must set the TX clock delay feature + * in the AR8051 PHY. Since we only support a single ethernet + * device in U-Boot, we only do this for the first instance. + */ +#define AR8051_PHY_DEBUG_ADDR_REG 0x1d +#define AR8051_PHY_DEBUG_DATA_REG 0x1e +#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 +#define AR8051_RGMII_TX_CLK_DLY 0x100 + const char *devname; + devname = miiphy_get_current_dev(); + + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG, + AR8051_DEBUG_RGMII_CLK_DLY_REG); + miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG, + AR8051_RGMII_TX_CLK_DLY); +#endif + return n; +} +#endif diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h new file mode 100644 index 0000000000..bcdb6485d2 --- /dev/null +++ b/board/vscom/baltos/board.h @@ -0,0 +1,90 @@ +/* + * board.h + * + * TI AM335x boards information header + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * TI AM335x parts define a system EEPROM that defines certain sub-fields. + * We use these fields to in turn see what board we are on, and what + * that might require us to set or not set. + */ +#define HDR_NO_OF_MAC_ADDR 3 +#define HDR_ETH_ALEN 6 +#define HDR_NAME_LEN 8 + +struct am335x_baseboard_id { + unsigned int magic; + char name[HDR_NAME_LEN]; + char version[4]; + char serial[12]; + char config[32]; + char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; +}; + +typedef struct _BSP_VS_HWPARAM // v1.0 +{ + uint32_t Magic; + uint32_t HwRev; + uint32_t SerialNumber; + char PrdDate[11]; // as a string ie. "01.01.2006" + uint16_t SystemId; + uint8_t MAC1[6]; // internal EMAC + uint8_t MAC2[6]; // SMSC9514 + uint8_t MAC3[6]; // WL1271 WLAN +} __attribute__ ((packed)) BSP_VS_HWPARAM; + +static inline int board_is_bone(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); +} + +static inline int board_is_bone_lt(struct am335x_baseboard_id *header) +{ + return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); +} + +static inline int board_is_evm_sk(struct am335x_baseboard_id *header) +{ + return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); +} + +static inline int board_is_idk(struct am335x_baseboard_id *header) +{ + return !strncmp(header->config, "SKU#02", 6); +} + +static inline int board_is_gp_evm(struct am335x_baseboard_id *header) +{ + return !strncmp("A33515BB", header->name, HDR_NAME_LEN); +} + +static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) +{ + return (board_is_gp_evm(header) && + strncmp("1.5", header->version, 3) <= 0); +} + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_i2c1_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c new file mode 100644 index 0000000000..8783b25b5f --- /dev/null +++ b/board/vscom/baltos/mux.c @@ -0,0 +1,194 @@ +/* + * mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart1_pin_mux[] = { + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ + {-1}, +}; + +static struct module_pin_mux uart2_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux uart4_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ + {-1}, +}; + +static struct module_pin_mux uart5_pin_mux[] = { + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux gpio0_7_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ + {-1}, +}; + +static struct module_pin_mux rmii1_pin_mux[] = { + {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart1_pin_mux(void) +{ + configure_module_pin_mux(uart1_pin_mux); +} + +void enable_uart2_pin_mux(void) +{ + configure_module_pin_mux(uart2_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_uart4_pin_mux(void) +{ + configure_module_pin_mux(uart4_pin_mux); +} + +void enable_uart5_pin_mux(void) +{ + configure_module_pin_mux(uart5_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_i2c1_pin_mux(void) +{ + configure_module_pin_mux(i2c1_pin_mux); +} + +void enable_board_pin_mux() +{ + /* Baltos */ + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(gpio0_7_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); + configure_module_pin_mux(rmii1_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + +#if defined(CONFIG_NAND) + configure_module_pin_mux(nand_pin_mux); +#endif +} diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds new file mode 100644 index 0000000000..315ba5b99a --- /dev/null +++ b/board/vscom/baltos/u-boot.lds @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + *(.vectors) + CPUDIR/start.o (.text*) + board/vscom/baltos/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + .hash : { *(.hash*) } + + .end : + { + *(.__end) + } + + _image_binary_end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + .dynsym _image_binary_end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .gnu.hash : { *(.gnu.hash) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } +} diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 90625ab9e0..0af63d291f 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR; #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) +#define REV_DETECTION IMX_GPIO_NR(2, 28) int dram_init(void) { @@ -105,6 +106,10 @@ static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +static iomux_v3_cfg_t const rev_detection_pad[] = { + IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static void setup_iomux_uart(void) { SETUP_IOMUX_PADS(uart1_pads); @@ -393,6 +398,17 @@ static const struct boot_mode board_boot_modes[] = { }; #endif +static bool is_revc1(void) +{ + SETUP_IOMUX_PADS(rev_detection_pad); + gpio_direction_input(REV_DETECTION); + + if (gpio_get_value(REV_DETECTION)) + return true; + else + return false; +} + int board_late_init(void) { #ifdef CONFIG_CMD_BMODE @@ -404,6 +420,11 @@ int board_late_init(void) setenv("board_rev", "MX6Q"); else setenv("board_rev", "MX6DL"); + + if (is_revc1()) + setenv("board_name", "C1"); + else + setenv("board_name", "B1"); #endif return 0; } @@ -424,7 +445,10 @@ int board_init(void) int checkboard(void) { - puts("Board: Wandboard\n"); + if (is_revc1()) + puts("Board: Wandboard rev C1\n"); + else + puts("Board: Wandboard rev B1\n"); return 0; } diff --git a/board/warp/README b/board/warp/README index db3100edba..22f9055eb6 100644 --- a/board/warp/README +++ b/board/warp/README @@ -34,7 +34,7 @@ Then U-boot should start and its messages will appear in the console program. Use the default environment variables: => env default -f -a -=> save +=> saveenv Run the DFU command: => dfu 0 mmc 0 diff --git a/common/Kconfig b/common/Kconfig index a2167f01f7..f6478fad0b 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -17,6 +17,84 @@ config SYS_HUSH_PARSER help Backward compatibility. +menu "Autoboot options" + +config AUTOBOOT_KEYED + bool "Stop autobooting via specific input key / string" + default n + help + This option enables stopping (aborting) of the automatic + boot feature only by issuing a specific input key or + string. If not enabled, any input key will abort the + U-Boot automatic booting process and bring the device + to the U-Boot prompt for user input. + +config AUTOBOOT_PROMPT + string "Autoboot stop prompt" + depends on AUTOBOOT_KEYED + default "Autoboot in %d seconds\\n" + help + This string is displayed before the boot delay selected by + CONFIG_BOOTDELAY starts. If it is not defined there is no + output indicating that autoboot is in progress. + + Note that this define is used as the (only) argument to a + printf() call, so it may contain '%' format specifications, + provided that it also includes, sepearated by commas exactly + like in a printf statement, the required arguments. It is + the responsibility of the user to select only such arguments + that are valid in the given context. + +config AUTOBOOT_ENCRYPTION + bool "Enable encryption in autoboot stopping" + depends on AUTOBOOT_KEYED + default n + +config AUTOBOOT_DELAY_STR + string "Delay autobooting via specific input key / string" + depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION + help + This option delays the automatic boot feature by issuing + a specific input key or string. If CONFIG_AUTOBOOT_DELAY_STR + or the environment variable "bootdelaykey" is specified + and this string is received from console input before + autoboot starts booting, U-Boot gives a command prompt. The + U-Boot prompt will time out if CONFIG_BOOT_RETRY_TIME is + used, otherwise it never times out. + +config AUTOBOOT_STOP_STR + string "Stop autobooting via specific input key / string" + depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION + help + This option enables stopping (aborting) of the automatic + boot feature only by issuing a specific input key or + string. If CONFIG_AUTOBOOT_STOP_STR or the environment + variable "bootstopkey" is specified and this string is + received from console input before autoboot starts booting, + U-Boot gives a command prompt. The U-Boot prompt never + times out, even if CONFIG_BOOT_RETRY_TIME is used. + +config AUTOBOOT_KEYED_CTRLC + bool "Enable Ctrl-C autoboot interruption" + depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION + default n + help + This option allows for the boot sequence to be interrupted + by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey". + Setting this variable provides an escape sequence from the + limited "password" strings. + +config AUTOBOOT_STOP_STR_SHA256 + string "Stop autobooting via SHA256 encrypted password" + depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION + help + This option adds the feature to only stop the autobooting, + and therefore boot into the U-Boot prompt, when the input + string / password matches a values that is encypted via + a SHA256 hash and saved in the environment. + +endmenu + comment "Commands" menu "Info commands" diff --git a/common/autoboot.c b/common/autoboot.c index c27cc2c751..c367076257 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -12,6 +12,7 @@ #include <fdtdec.h> #include <menu.h> #include <post.h> +#include <u-boot/sha256.h> DECLARE_GLOBAL_DATA_PTR; @@ -26,15 +27,81 @@ DECLARE_GLOBAL_DATA_PTR; /* Stored value of bootdelay, used by autoboot_command() */ static int stored_bootdelay; -/*************************************************************************** - * Watch for 'delay' seconds for autoboot stop or autoboot delay string. - * returns: 0 - no key string, allow autoboot 1 - got key string, abort +#if defined(CONFIG_AUTOBOOT_KEYED) +#if defined(CONFIG_AUTOBOOT_STOP_STR_SHA256) + +/* + * Use a "constant-length" time compare function for this + * hash compare: + * + * https://crackstation.net/hashing-security.htm */ -# if defined(CONFIG_AUTOBOOT_KEYED) -static int abortboot_keyed(int bootdelay) +static int slow_equals(u8 *a, u8 *b, int len) +{ + int diff = 0; + int i; + + for (i = 0; i < len; i++) + diff |= a[i] ^ b[i]; + + return diff == 0; +} + +static int passwd_abort(uint64_t etime) +{ + const char *sha_env_str = getenv("bootstopkeysha256"); + u8 sha_env[SHA256_SUM_LEN]; + u8 sha[SHA256_SUM_LEN]; + char presskey[MAX_DELAY_STOP_STR]; + const char *algo_name = "sha256"; + u_int presskey_len = 0; + int abort = 0; + int size; + int ret; + + if (sha_env_str == NULL) + sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256; + + /* + * Generate the binary value from the environment hash value + * so that we can compare this value with the computed hash + * from the user input + */ + ret = hash_parse_string(algo_name, sha_env_str, sha_env); + if (ret) { + printf("Hash %s not supported!\n", algo_name); + return 0; + } + + /* + * We don't know how long the stop-string is, so we need to + * generate the sha256 hash upon each input character and + * compare the value with the one saved in the environment + */ + do { + if (tstc()) { + /* Check for input string overflow */ + if (presskey_len >= MAX_DELAY_STOP_STR) + return 0; + + presskey[presskey_len++] = getc(); + + /* Calculate sha256 upon each new char */ + hash_block(algo_name, (const void *)presskey, + presskey_len, sha, &size); + + /* And check if sha matches saved value in env */ + if (slow_equals(sha, sha_env, SHA256_SUM_LEN)) + abort = 1; + } + } while (!abort && get_ticks() <= etime); + + return abort; +} +#else +static int passwd_abort(uint64_t etime) { int abort = 0; - uint64_t etime = endtick(bootdelay); struct { char *str; u_int len; @@ -42,9 +109,7 @@ static int abortboot_keyed(int bootdelay) } delaykey[] = { { .str = getenv("bootdelaykey"), .retry = 1 }, - { .str = getenv("bootdelaykey2"), .retry = 1 }, { .str = getenv("bootstopkey"), .retry = 0 }, - { .str = getenv("bootstopkey2"), .retry = 0 }, }; char presskey[MAX_DELAY_STOP_STR]; @@ -52,30 +117,13 @@ static int abortboot_keyed(int bootdelay) u_int presskey_max = 0; u_int i; -#ifndef CONFIG_ZERO_BOOTDELAY_CHECK - if (bootdelay == 0) - return 0; -#endif - -# ifdef CONFIG_AUTOBOOT_PROMPT - printf(CONFIG_AUTOBOOT_PROMPT); -# endif - # ifdef CONFIG_AUTOBOOT_DELAY_STR if (delaykey[0].str == NULL) delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR; # endif -# ifdef CONFIG_AUTOBOOT_DELAY_STR2 - if (delaykey[1].str == NULL) - delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2; -# endif # ifdef CONFIG_AUTOBOOT_STOP_STR - if (delaykey[2].str == NULL) - delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR; -# endif -# ifdef CONFIG_AUTOBOOT_STOP_STR2 - if (delaykey[3].str == NULL) - delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2; + if (delaykey[1].str == NULL) + delaykey[1].str = CONFIG_AUTOBOOT_STOP_STR; # endif for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) { @@ -125,6 +173,33 @@ static int abortboot_keyed(int bootdelay) } } while (!abort && get_ticks() <= etime); + return abort; +} +#endif + +/*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot 1 - got key string, abort + */ +static int abortboot_keyed(int bootdelay) +{ + int abort; + uint64_t etime = endtick(bootdelay); + +#ifndef CONFIG_ZERO_BOOTDELAY_CHECK + if (bootdelay == 0) + return 0; +#endif + +# ifdef CONFIG_AUTOBOOT_PROMPT + /* + * CONFIG_AUTOBOOT_PROMPT includes the %d for all boards. + * To print the bootdelay value upon bootup. + */ + printf(CONFIG_AUTOBOOT_PROMPT, bootdelay); +# endif + + abort = passwd_abort(etime); if (!abort) debug_bootkeys("key timeout\n"); diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index f16d5c719f..ed3b9351b1 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -400,6 +400,9 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq); printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq); #endif +#ifdef CONFIG_BOARD_TYPES + printf("Board Type = %ld\n", gd->board_type); +#endif return 0; } diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index cc904c2535..cb1f07119b 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -34,12 +34,12 @@ static int bmp_info (ulong addr); * didn't contain a valid BMP signature. */ #ifdef CONFIG_VIDEO_BMP_GZIP -bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp, - void **alloc_addr) +struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, + void **alloc_addr) { void *dst; unsigned long len; - bmp_image_t *bmp; + struct bmp_image *bmp; /* * Decompress bmp image @@ -55,7 +55,7 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp, bmp = dst; /* align to 32-bit-aligned-address + 2 */ - bmp = (bmp_image_t *)((((unsigned int)dst + 1) & ~3) + 2); + bmp = (struct bmp_image *)((((unsigned int)dst + 1) & ~3) + 2); if (gunzip(bmp, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) { free(dst); @@ -80,8 +80,8 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp, return bmp; } #else -bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp, - void **alloc_addr) +struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp, + void **alloc_addr) { return NULL; } @@ -187,7 +187,7 @@ U_BOOT_CMD( */ static int bmp_info(ulong addr) { - bmp_image_t *bmp=(bmp_image_t *)addr; + struct bmp_image *bmp = (struct bmp_image *)addr; void *bmp_alloc_addr = NULL; unsigned long len; @@ -224,7 +224,7 @@ static int bmp_info(ulong addr) int bmp_display(ulong addr, int x, int y) { int ret; - bmp_image_t *bmp = (bmp_image_t *)addr; + struct bmp_image *bmp = (struct bmp_image *)addr; void *bmp_alloc_addr = NULL; unsigned long len; diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index f80f549d4e..aaca3e8a2a 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -54,10 +54,12 @@ static block_dev_desc_t scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE]; * forward declerations of some Setup Routines */ void scsi_setup_test_unit_ready(ccb * pccb); -void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks); -void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks); -static void scsi_setup_write_ext(ccb *pccb, unsigned long start, - unsigned short blocks); +void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks); +void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks); +void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks); + +static void scsi_setup_write_ext(ccb *pccb, lbaint_t start, + unsigned short blocks); void scsi_setup_inquiry(ccb * pccb); void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); @@ -357,7 +359,9 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * scsi_read */ -#define SCSI_MAX_READ_BLK 0xFFFF /* almost the maximum amount of the scsi_ext command.. */ +/* almost the maximum amount of the scsi_ext command.. */ +#define SCSI_MAX_READ_BLK 0xFFFF +#define SCSI_LBA48_READ 0xFFFFFFF static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer) @@ -379,7 +383,17 @@ static ulong scsi_read(int device, lbaint_t blknr, lbaint_t blkcnt, device, start, blks, (unsigned long)buffer); do { pccb->pdata=(unsigned char *)buf_addr; - if(blks>SCSI_MAX_READ_BLK) { +#ifdef CONFIG_SYS_64BIT_LBA + if (start > SCSI_LBA48_READ) { + unsigned long blocks; + blocks = min_t(lbaint_t, blks, SCSI_MAX_READ_BLK); + pccb->datalen = scsi_dev_desc[device].blksz * blocks; + scsi_setup_read16(pccb, start, blocks); + start += blocks; + blks -= blocks; + } else +#endif + if (blks > SCSI_MAX_READ_BLK) { pccb->datalen=scsi_dev_desc[device].blksz * SCSI_MAX_READ_BLK; smallblks=SCSI_MAX_READ_BLK; scsi_setup_read_ext(pccb,start,smallblks); @@ -579,7 +593,38 @@ void scsi_setup_test_unit_ready(ccb * pccb) pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */ } -void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks) +#ifdef CONFIG_SYS_64BIT_LBA +void scsi_setup_read16(ccb * pccb, lbaint_t start, unsigned long blocks) +{ + pccb->cmd[0] = SCSI_READ16; + pccb->cmd[1] = pccb->lun<<5; + pccb->cmd[2] = ((unsigned char) (start >> 56)) & 0xff; + pccb->cmd[3] = ((unsigned char) (start >> 48)) & 0xff; + pccb->cmd[4] = ((unsigned char) (start >> 40)) & 0xff; + pccb->cmd[5] = ((unsigned char) (start >> 32)) & 0xff; + pccb->cmd[6] = ((unsigned char) (start >> 24)) & 0xff; + pccb->cmd[7] = ((unsigned char) (start >> 16)) & 0xff; + pccb->cmd[8] = ((unsigned char) (start >> 8)) & 0xff; + pccb->cmd[9] = ((unsigned char) (start)) & 0xff; + pccb->cmd[10] = 0; + pccb->cmd[11] = ((unsigned char) (blocks >> 24)) & 0xff; + pccb->cmd[12] = ((unsigned char) (blocks >> 16)) & 0xff; + pccb->cmd[13] = ((unsigned char) (blocks >> 8)) & 0xff; + pccb->cmd[14] = (unsigned char) blocks & 0xff; + pccb->cmd[15] = 0; + pccb->cmdlen = 16; + pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ + debug ("scsi_setup_read16: cmd: %02X %02X " + "startblk %02X%02X%02X%02X%02X%02X%02X%02X " + "blccnt %02X%02X%02X%02X\n", + pccb->cmd[0], pccb->cmd[1], + pccb->cmd[2], pccb->cmd[3], pccb->cmd[4], pccb->cmd[5], + pccb->cmd[6], pccb->cmd[7], pccb->cmd[8], pccb->cmd[9], + pccb->cmd[11], pccb->cmd[12], pccb->cmd[13], pccb->cmd[14]); +} +#endif + +void scsi_setup_read_ext(ccb * pccb, lbaint_t start, unsigned short blocks) { pccb->cmd[0]=SCSI_READ10; pccb->cmd[1]=pccb->lun<<5; @@ -599,7 +644,7 @@ void scsi_setup_read_ext(ccb * pccb, unsigned long start, unsigned short blocks) pccb->cmd[7],pccb->cmd[8]); } -void scsi_setup_write_ext(ccb *pccb, unsigned long start, unsigned short blocks) +void scsi_setup_write_ext(ccb *pccb, lbaint_t start, unsigned short blocks) { pccb->cmd[0] = SCSI_WRITE10; pccb->cmd[1] = pccb->lun << 5; @@ -620,7 +665,7 @@ void scsi_setup_write_ext(ccb *pccb, unsigned long start, unsigned short blocks) pccb->cmd[7], pccb->cmd[8]); } -void scsi_setup_read6(ccb * pccb, unsigned long start, unsigned short blocks) +void scsi_setup_read6(ccb * pccb, lbaint_t start, unsigned short blocks) { pccb->cmd[0]=SCSI_READ6; pccb->cmd[1]=pccb->lun<<5 | (((unsigned char)(start>>16))&0x1f); diff --git a/common/hash.c b/common/hash.c index c94c98be9e..a1b048204d 100644 --- a/common/hash.c +++ b/common/hash.c @@ -227,6 +227,26 @@ int hash_progressive_lookup_algo(const char *algo_name, } #ifndef USE_HOSTCC +int hash_parse_string(const char *algo_name, const char *str, uint8_t *result) +{ + struct hash_algo *algo; + int ret; + int i; + + ret = hash_lookup_algo(algo_name, &algo); + if (ret) + return ret; + + for (i = 0; i < algo->digest_size; i++) { + char chr[3]; + + strncpy(chr, &str[i * 2], 2); + result[i] = simple_strtoul(chr, NULL, 16); + } + + return 0; +} + /** * store_result: Store the resulting sum to an address or variable * @@ -315,7 +335,6 @@ static int parse_verify_sum(struct hash_algo *algo, char *verify_str, buf = map_sysmem(addr, algo->digest_size); memcpy(vsum, buf, algo->digest_size); } else { - unsigned int i; char *vsum_str; int digits = algo->digest_size * 2; @@ -335,14 +354,7 @@ static int parse_verify_sum(struct hash_algo *algo, char *verify_str, } } - for (i = 0; i < algo->digest_size; i++) { - char *nullp = vsum_str + (i + 1) * 2; - char end = *nullp; - - *nullp = '\0'; - vsum[i] = simple_strtoul(vsum_str + (i * 2), NULL, 16); - *nullp = end; - } + hash_parse_string(algo->name, vsum_str, vsum); } return 0; } diff --git a/common/lcd.c b/common/lcd.c index 055c366b19..5a52fe4287 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -448,8 +448,8 @@ static void draw_encoded_bitmap(ushort **fbp, ushort c, int cnt) /* * Do not call this function directly, must be called from lcd_display_bitmap. */ -static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb, - int x_off, int y_off) +static void lcd_display_rle8_bitmap(struct bmp_image *bmp, ushort *cmap, + uchar *fb, int x_off, int y_off) { uchar *bmap; ulong width, height; @@ -548,10 +548,10 @@ __weak void fb_put_word(uchar **fb, uchar **from) } #endif /* CONFIG_BMP_16BPP */ -__weak void lcd_set_cmap(bmp_image_t *bmp, unsigned colors) +__weak void lcd_set_cmap(struct bmp_image *bmp, unsigned colors) { int i; - bmp_color_table_entry_t cte; + struct bmp_color_table_entry cte; ushort *cmap = configuration_get_cmap(); for (i = 0; i < colors; ++i) { @@ -572,12 +572,14 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) ushort *cmap_base = NULL; ushort i, j; uchar *fb; - bmp_image_t *bmp = (bmp_image_t *)map_sysmem(bmp_image, 0); + struct bmp_image *bmp = (struct bmp_image *)map_sysmem(bmp_image, 0); uchar *bmap; ushort padded_width; unsigned long width, height, byte_width; unsigned long pwidth = panel_info.vl_col; unsigned colors, bpix, bmp_bpix; + int hdr_size; + struct bmp_color_table_entry *palette = bmp->color_table; if (!bmp || !(bmp->header.signature[0] == 'B' && bmp->header.signature[1] == 'M')) { @@ -589,6 +591,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) width = get_unaligned_le32(&bmp->header.width); height = get_unaligned_le32(&bmp->header.height); bmp_bpix = get_unaligned_le16(&bmp->header.bit_count); + hdr_size = get_unaligned_le16(&bmp->header.size); + debug("hdr_size=%d, bmp_bpix=%d\n", hdr_size, bmp_bpix); colors = 1 << bmp_bpix; @@ -613,8 +617,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) return 1; } - debug("Display-bmp: %d x %d with %d colors\n", - (int)width, (int)height, (int)colors); + debug("Display-bmp: %d x %d with %d colors, display %d\n", + (int)width, (int)height, (int)colors, 1 << bpix); if (bmp_bpix == 8) lcd_set_cmap(bmp, colors); @@ -641,6 +645,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) cmap_base = configuration_get_cmap(); #ifdef CONFIG_LCD_BMP_RLE8 u32 compression = get_unaligned_le32(&bmp->header.compression); + debug("compressed %d %d\n", compression, BMP_BI_RLE8); if (compression == BMP_BI_RLE8) { if (bpix != 16) { /* TODO implement render code for bpix != 16 */ @@ -663,7 +668,19 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) if (bpix != 16) { fb_put_byte(&fb, &bmap); } else { - *(uint16_t *)fb = cmap_base[*(bmap++)]; + struct bmp_color_table_entry *entry; + uint val; + + if (cmap_base) { + val = cmap_base[*bmap]; + } else { + entry = &palette[*bmap]; + val = entry->blue >> 3 | + entry->green >> 2 << 5 | + entry->red >> 3 << 11; + } + *(uint16_t *)fb = val; + bmap++; fb += sizeof(uint16_t) / sizeof(*fb); } } diff --git a/common/malloc_simple.c b/common/malloc_simple.c index d445199c58..9811ab60f6 100644 --- a/common/malloc_simple.c +++ b/common/malloc_simple.c @@ -26,6 +26,20 @@ void *malloc_simple(size_t bytes) return ptr; } +void *memalign_simple(size_t align, size_t bytes) +{ + ulong addr, new_ptr; + void *ptr; + + addr = ALIGN(gd->malloc_base + gd->malloc_ptr, bytes); + new_ptr = addr + bytes; + if (new_ptr > gd->malloc_limit) + return NULL; + ptr = map_sysmem(addr, bytes); + gd->malloc_ptr = ALIGN(new_ptr, sizeof(new_ptr)); + return ptr; +} + #ifdef CONFIG_SYS_MALLOC_SIMPLE void *calloc(size_t nmemb, size_t elem_size) { diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig index 1eff08299e..93ab5b0ac0 100644 --- a/configs/CPCI4052_defconfig +++ b/configs/CPCI4052_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_4xx=y CONFIG_TARGET_CPCI4052=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig index f9d340ab72..0e47ffed8e 100644 --- a/configs/O2DNT2_RAMBOOT_defconfig +++ b/configs/O2DNT2_RAMBOOT_defconfig @@ -1,5 +1,8 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2DNT2=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" +CONFIG_AUTOBOOT_STOP_STR="++++++++++" diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig index ce952e8b0f..3501761450 100644 --- a/configs/O2DNT2_defconfig +++ b/configs/O2DNT2_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_O2DNT2=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" +CONFIG_AUTOBOOT_STOP_STR="++++++++++" diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig index 459b6908d4..f7da9801f0 100644 --- a/configs/PLU405_defconfig +++ b/configs/PLU405_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_4xx=y CONFIG_TARGET_PLU405=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig index e7e157f8ef..aec6b51470 100644 --- a/configs/PMC405DE_defconfig +++ b/configs/PMC405DE_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_4xx=y CONFIG_TARGET_PMC405DE=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig index 779087d817..44c81b3f66 100644 --- a/configs/PMC440_defconfig +++ b/configs/PMC440_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_4xx=y CONFIG_TARGET_PMC440=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig index d6ea20e52e..18691aa57b 100644 --- a/configs/UCP1020_SPIFLASH_defconfig +++ b/configs/UCP1020_SPIFLASH_defconfig @@ -1,6 +1,9 @@ CONFIG_PPC=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_NET=y CONFIG_MPC85xx=y CONFIG_TARGET_UCP1020=y CONFIG_TARGET_UCP1020_SPIFLASH=y -CONFIG_CMD_SETEXPR=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b" diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index 50cb7deca1..f9f45aea0e 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -1,5 +1,8 @@ CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_UCP1020=y CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y +CONFIG_MPC85xx=y +CONFIG_TARGET_UCP1020=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b" diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig index a91c89b57d..c979493f82 100644 --- a/configs/a4m072_defconfig +++ b/configs/a4m072_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_A4M072=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="asdfg" diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig new file mode 100644 index 0000000000..679b04f198 --- /dev/null +++ b/configs/am335x_baltos_defconfig @@ -0,0 +1,7 @@ +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SYS_EXTRA_OPTIONS="NAND" +CONFIG_CONS_INDEX=1 +CONFIG_ARM=y +CONFIG_TARGET_AM335X_BALTOS=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index a8584e9b84..67ad959eef 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_AM335X_EVM=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack" CONFIG_SPL=y CONFIG_SPL_STACK_R=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 4ad266717a..29a3892982 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y CONFIG_TARGET_AM43XX_EVM=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" CONFIG_CMD_NET=y diff --git a/configs/arches_defconfig b/configs/arches_defconfig index 469dace8b1..c55357b375 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -6,3 +6,4 @@ CONFIG_DEFAULT_DEVICE_TREE="arches" CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig index b00ae3a098..03ce63b9fa 100644 --- a/configs/atngw100_defconfig +++ b/configs/atngw100_defconfig @@ -1,3 +1,7 @@ CONFIG_AVR32=y -CONFIG_TARGET_ATNGW100=y CONFIG_CMD_NET=y +CONFIG_TARGET_ATNGW100=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig index 6caf691d00..2d1845f98a 100644 --- a/configs/atngw100mkii_defconfig +++ b/configs/atngw100mkii_defconfig @@ -1,3 +1,7 @@ CONFIG_AVR32=y -CONFIG_TARGET_ATNGW100MKII=y CONFIG_CMD_NET=y +CONFIG_TARGET_ATNGW100MKII=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig index e407dc56a1..f74060e482 100644 --- a/configs/atstk1002_defconfig +++ b/configs/atstk1002_defconfig @@ -1,3 +1,7 @@ CONFIG_AVR32=y -CONFIG_TARGET_ATSTK1002=y CONFIG_CMD_NET=y +CONFIG_TARGET_ATSTK1002=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/atstk1003_defconfig b/configs/atstk1003_defconfig deleted file mode 100644 index b704532dbf..0000000000 --- a/configs/atstk1003_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_ATSTK1003=y diff --git a/configs/atstk1004_defconfig b/configs/atstk1004_defconfig deleted file mode 100644 index 76502549c1..0000000000 --- a/configs/atstk1004_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_ATSTK1004=y diff --git a/configs/atstk1006_defconfig b/configs/atstk1006_defconfig deleted file mode 100644 index 31482fcee2..0000000000 --- a/configs/atstk1006_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_ATSTK1006=y -CONFIG_CMD_NET=y diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig index f963502b8c..dd48d6a8ae 100644 --- a/configs/bf527-ezkit-v2_defconfig +++ b/configs/bf527-ezkit-v2_defconfig @@ -3,3 +3,4 @@ CONFIG_TARGET_BF527_EZKIT=y CONFIG_SYS_EXTRA_OPTIONS="BF527_EZKIT_REV_2_1" CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/bf533-ezkit_defconfig b/configs/bf533-ezkit_defconfig index 66c11451af..04210d8618 100644 --- a/configs/bf533-ezkit_defconfig +++ b/configs/bf533-ezkit_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF533_EZKIT=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/bf533-stamp_defconfig b/configs/bf533-stamp_defconfig index ca1202d849..191e2d6399 100644 --- a/configs/bf533-stamp_defconfig +++ b/configs/bf533-stamp_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF533_STAMP=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/bf538f-ezkit_defconfig b/configs/bf538f-ezkit_defconfig index 84449ec42d..f8ae21b205 100644 --- a/configs/bf538f-ezkit_defconfig +++ b/configs/bf538f-ezkit_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF538F_EZKIT=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig index 46c8fe2cf1..6bd9e9bad4 100644 --- a/configs/bf548-ezkit_defconfig +++ b/configs/bf548-ezkit_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF548_EZKIT=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/bf561-acvilon_defconfig b/configs/bf561-acvilon_defconfig index b558066d8f..7a65892311 100644 --- a/configs/bf561-acvilon_defconfig +++ b/configs/bf561-acvilon_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF561_ACVILON=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/bf561-ezkit_defconfig b/configs/bf561-ezkit_defconfig index 0ef1a1cdb0..e8a1ea48f3 100644 --- a/configs/bf561-ezkit_defconfig +++ b/configs/bf561-ezkit_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BF561_EZKIT=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/bf609-ezkit_defconfig b/configs/bf609-ezkit_defconfig index 72e0606f7c..d8c2629751 100644 --- a/configs/bf609-ezkit_defconfig +++ b/configs/bf609-ezkit_defconfig @@ -3,3 +3,4 @@ CONFIG_NETDEVICES=y CONFIG_TARGET_BF609_EZKIT=y CONFIG_CMD_NET=y CONFIG_ETH_DESIGNWARE=y +CONFIG_LIB_RAND=y diff --git a/configs/br4_defconfig b/configs/br4_defconfig index e6970a40de..7247b9c473 100644 --- a/configs/br4_defconfig +++ b/configs/br4_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_BR4=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig index a601b0381d..b1c5fa933c 100644 --- a/configs/calimain_defconfig +++ b/configs/calimain_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_CALIMAIN=y CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="\x0b" diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index 12d335233d..e838a6c56a 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -6,4 +6,5 @@ CONFIG_DEFAULT_DEVICE_TREE="canyonlands" CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/cm-bf533_defconfig b/configs/cm-bf533_defconfig index 42d568e473..89a5c0f0a4 100644 --- a/configs/cm-bf533_defconfig +++ b/configs/cm-bf533_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_CM_BF533=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/cm-bf548_defconfig b/configs/cm-bf548_defconfig index 906a9bd743..b9b6044785 100644 --- a/configs/cm-bf548_defconfig +++ b/configs/cm-bf548_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_CM_BF548=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/cm-bf561_defconfig b/configs/cm-bf561_defconfig index 023cc65ecc..a304e572e8 100644 --- a/configs/cm-bf561_defconfig +++ b/configs/cm-bf561_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_CM_BF561=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index b2d1ed803f..5d4f30756d 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -4,3 +4,4 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_I CONFIG_CMD_NET=y CONFIG_NAND_VF610_NFC=y CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y diff --git a/configs/colibri_vf_dtb_defconfig b/configs/colibri_vf_dtb_defconfig new file mode 100644 index 0000000000..d4c8c58d6b --- /dev/null +++ b/configs/colibri_vf_dtb_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_TARGET_COLIBRI_VF=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_vf/imximage.cfg,ENV_IS_IN_NAND,IMX_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y +CONFIG_DM=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="vf610-colibri" diff --git a/configs/cpuat91_defconfig b/configs/cpuat91_defconfig index 7a87f4ae11..676e1a59d2 100644 --- a/configs/cpuat91_defconfig +++ b/configs/cpuat91_defconfig @@ -2,3 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPUAT91=y CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/cpuat91_ram_defconfig b/configs/cpuat91_ram_defconfig index 7b92ed6826..95e88c4f6c 100644 --- a/configs/cpuat91_ram_defconfig +++ b/configs/cpuat91_ram_defconfig @@ -1,5 +1,9 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CPUAT91=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" CONFIG_CMD_NET=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig index daaf1dcf4a..311ac8e58c 100644 --- a/configs/digsy_mtc_RAMBOOT_defconfig +++ b/configs/digsy_mtc_RAMBOOT_defconfig @@ -1,5 +1,9 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_DIGSY_MTC=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000" -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig index c1706d1bd1..f4f0a6d2b5 100644 --- a/configs/digsy_mtc_defconfig +++ b/configs/digsy_mtc_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_DIGSY_MTC=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR=" " diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig index 6a4869dc03..554f907ef9 100644 --- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig +++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig @@ -1,5 +1,9 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_DIGSY_MTC=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000,DIGSY_REV5" -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig index 9370fdd30e..83b8ac2adb 100644 --- a/configs/digsy_mtc_rev5_defconfig +++ b/configs/digsy_mtc_rev5_defconfig @@ -1,5 +1,9 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_DIGSY_MTC=y CONFIG_SYS_EXTRA_OPTIONS="DIGSY_REV5" -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig index b067c8697d..3687111c16 100644 --- a/configs/dlvision-10g_defconfig +++ b/configs/dlvision-10g_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_DLVISION_10G=y CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y +CONFIG_4xx=y +CONFIG_TARGET_DLVISION_10G=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 4c514a39ef..80cb44bf53 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -1,4 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_DRACO=y -CONFIG_SPL=y CONFIG_CMD_NET=y +CONFIG_SPL=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" diff --git a/configs/dxr2_defconfig b/configs/dxr2_defconfig index c2a14b794c..1041031870 100644 --- a/configs/dxr2_defconfig +++ b/configs/dxr2_defconfig @@ -1,4 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_DXR2=y -CONFIG_SPL=y CONFIG_CMD_NET=y +CONFIG_SPL=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" diff --git a/configs/favr-32-ezkit_defconfig b/configs/favr-32-ezkit_defconfig deleted file mode 100644 index fabb50c249..0000000000 --- a/configs/favr-32-ezkit_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_FAVR_32_EZKIT=y -CONFIG_CMD_NET=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index a3b564ec54..5045510433 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -5,5 +5,6 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo" CONFIG_TARGET_GALILEO=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_ETH_DESIGNWARE=y CONFIG_GENERATE_PIRQ_TABLE=y diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig index c6c7161c26..9fe229e40f 100644 --- a/configs/gdppc440etx_defconfig +++ b/configs/gdppc440etx_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_GDPPC440ETX=y CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y +CONFIG_4xx=y +CONFIG_TARGET_GDPPC440ETX=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig index 451ce9f12c..85b5f4318c 100644 --- a/configs/grasshopper_defconfig +++ b/configs/grasshopper_defconfig @@ -1,3 +1,7 @@ CONFIG_AVR32=y -CONFIG_TARGET_GRASSHOPPER=y CONFIG_CMD_NET=y +CONFIG_TARGET_GRASSHOPPER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/hammerhead_defconfig b/configs/hammerhead_defconfig deleted file mode 100644 index 1130d92988..0000000000 --- a/configs/hammerhead_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_HAMMERHEAD=y -CONFIG_CMD_NET=y diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index e1875dbb67..ed3b7e4961 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_HIGHBANK=y CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n" +CONFIG_AUTOBOOT_KEYED_CTRLC=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index 4f2a55dae7..77072436ce 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -1,4 +1,6 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/ibf-dsp561_defconfig b/configs/ibf-dsp561_defconfig index eb80798a94..15f24bbc43 100644 --- a/configs/ibf-dsp561_defconfig +++ b/configs/ibf-dsp561_defconfig @@ -1,3 +1,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_IBF_DSP561=y CONFIG_CMD_NET=y +CONFIG_LIB_RAND=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 21977c876b..cb795fc6e2 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -1,7 +1,10 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC83xx=y CONFIG_TARGET_IDS8313=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000" -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n" +CONFIG_AUTOBOOT_DELAY_STR="ids" diff --git a/configs/intip_defconfig b/configs/intip_defconfig index 476616cd97..82ed775e18 100644 --- a/configs/intip_defconfig +++ b/configs/intip_defconfig @@ -1,6 +1,8 @@ CONFIG_PPC=y +CONFIG_CMD_SETEXPR=y +CONFIG_CMD_NET=y CONFIG_4xx=y CONFIG_TARGET_INTIP=y CONFIG_SYS_EXTRA_OPTIONS="INTIB" -CONFIG_CMD_SETEXPR=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/io64_defconfig b/configs/io64_defconfig index 7f1825adab..3276cc409c 100644 --- a/configs/io64_defconfig +++ b/configs/io64_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_IO64=y CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y +CONFIG_4xx=y +CONFIG_TARGET_IO64=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/io_defconfig b/configs/io_defconfig index 7713232336..ad3a651daf 100644 --- a/configs/io_defconfig +++ b/configs/io_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_IO=y CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y +CONFIG_4xx=y +CONFIG_TARGET_IO=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig index 95758cf868..f966dead76 100644 --- a/configs/iocon_defconfig +++ b/configs/iocon_defconfig @@ -1,5 +1,7 @@ CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_IOCON=y CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y +CONFIG_4xx=y +CONFIG_TARGET_IOCON=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 5740359d20..1e4cf7b631 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -4,4 +4,5 @@ CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SPL=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/mimc200_defconfig b/configs/mimc200_defconfig deleted file mode 100644 index 85c646ec16..0000000000 --- a/configs/mimc200_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_AVR32=y -CONFIG_TARGET_MIMC200=y -CONFIG_CMD_NET=y diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig index 8bc367b7fe..eaa222eb42 100644 --- a/configs/motionpro_defconfig +++ b/configs/motionpro_defconfig @@ -1,4 +1,7 @@ CONFIG_PPC=y +CONFIG_CMD_NET=y CONFIG_MPC5xxx=y CONFIG_TARGET_MOTIONPRO=y -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index e03f586880..3aff2e6d04 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -1,3 +1,4 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_NOKIA_RX51=y +CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 92acab293b..81949e8950 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -6,3 +6,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" CONFIG_CMD_NET=y CONFIG_DISPLAY_PORT=y CONFIG_VIDEO_TEGRA124=y +CONFIG_DM_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index 5efcdf592e..41005c78ca 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_ODROID=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" CONFIG_CMD_SETEXPR=y CONFIG_CMD_NET=y diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig index ec4924b82a..fd3902dfaf 100644 --- a/configs/omap3_mvblx_defconfig +++ b/configs/omap3_mvblx_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_MVBLX=y CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="S" diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 3c59b9b07a..657ef7e7da 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_ORIGEN=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen" CONFIG_SPL=y CONFIG_CMD_SETEXPR=y diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 82ce8c79b7..723989c0fb 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -9,6 +9,10 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y CONFIG_CMD_BOOTD=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 671d9cc46d..a2e2d4f4d7 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -8,6 +8,10 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y CONFIG_CMD_BOOTD=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 3e763dc5ab..dc59dcbaa8 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -9,6 +9,10 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" +CONFIG_AUTOBOOT_DELAY_STR="d" +CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_BDI=y CONFIG_CMD_CONSOLE=y CONFIG_CMD_BOOTD=y diff --git a/configs/pr1_defconfig b/configs/pr1_defconfig index f85cc7746b..a8eb7f3f3e 100644 --- a/configs/pr1_defconfig +++ b/configs/pr1_defconfig @@ -2,3 +2,4 @@ CONFIG_BLACKFIN=y CONFIG_TARGET_PR1=y CONFIG_CMD_NET=y CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y +CONFIG_LIB_RAND=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index e65dff597d..10f2fe9067 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -1,4 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_PXM2=y -CONFIG_SPL=y CONFIG_CMD_NET=y +CONFIG_SPL=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 45ed12c745..93ab51494b 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -1,4 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_RUT=y -CONFIG_SPL=y CONFIG_CMD_NET=y +CONFIG_SPL=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index 633698edca..32ac86ad82 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_S5PC210_UNIVERSAL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210" CONFIG_CMD_SETEXPR=y CONFIG_OF_CONTROL=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 345b701f14..31fe2f9f45 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -41,3 +41,4 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y +CONFIG_SANDBOX_SERIAL=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index bbe4e806ff..c9fcb74eec 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_NETDEVICES=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL=y diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig index 2790ffce9e..2d27e7a662 100644 --- a/configs/spear600_defconfig +++ b/configs/spear600_defconfig @@ -1,6 +1,9 @@ CONFIG_ARM=y CONFIG_TARGET_SPEAR600=y CONFIG_NETDEVICES=y -CONFIG_SYS_EXTRA_OPTIONS="spear600" CONFIG_CMD_NET=y +CONFIG_SYS_EXTRA_OPTIONS="spear600" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_ETH_DESIGNWARE=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 6c27666ad7..f8ec5dbaa0 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -2,7 +2,10 @@ CONFIG_ARM=y CONFIG_TARGET_STV0991=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NETDEVICES=y +CONFIG_CMD_NET=y CONFIG_DEFAULT_DEVICE_TREE="stv0991" CONFIG_SYS_EXTRA_OPTIONS="stv0991" -CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_ETH_DESIGNWARE=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 75a8aec103..52e87a131a 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_TRATS2=y +CONFIG_SPL_DISABLE_OF_CONTROL=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2" CONFIG_CMD_SETEXPR=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index a1aa892b29..25315b3414 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_TRATS=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats" CONFIG_CMD_SETEXPR=y CONFIG_OF_CONTROL=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 3122a2b276..8e22a184c5 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -1,6 +1,9 @@ CONFIG_ARM=y CONFIG_TARGET_X600=y CONFIG_NETDEVICES=y -CONFIG_SPL=y CONFIG_CMD_NET=y +CONFIG_SPL=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_ETH_DESIGNWARE=y diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig index 84c789aa20..259d4a93e5 100644 --- a/configs/zmx25_defconfig +++ b/configs/zmx25_defconfig @@ -1,3 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_ZMX25=y CONFIG_CMD_NET=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="boot in %d s\n" +CONFIG_AUTOBOOT_DELAY_STR="delaygs" +CONFIG_AUTOBOOT_STOP_STR="stopgs" diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 9215ac55a6..03f4bf732a 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_ZYNQ_MICROZED=y CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed" # CONFIG_SYS_MALLOC_F is not set CONFIG_SPL=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig index a018b6e89e..7377619da7 100644 --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC70X=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" # CONFIG_SYS_MALLOC_F is not set CONFIG_SPL=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 7c83e8ba21..c948ad76e7 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" # CONFIG_SYS_MALLOC_F is not set CONFIG_SPL=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 2659d0ae24..3429bf9b6c 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" # CONFIG_SYS_MALLOC_F is not set CONFIG_SPL=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 64624ea012..a435229d6e 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" # CONFIG_SYS_MALLOC_F is not set CONFIG_SPL=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 55d58a70b0..8f94d21174 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZED=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" # CONFIG_SYS_MALLOC_F is not set CONFIG_SPL=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index f119532fad..1849c74b8d 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_TARGET_ZYNQ_ZYBO=y +CONFIG_SPL_DISABLE_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" # CONFIG_SYS_MALLOC_F is not set CONFIG_SPL=y diff --git a/doc/README.autoboot b/doc/README.autoboot index 14e3660dd8..227e3b5dbb 100644 --- a/doc/README.autoboot +++ b/doc/README.autoboot @@ -78,13 +78,9 @@ What they do CONFIG_AUTOBOOT_PROMPT CONFIG_AUTOBOOT_DELAY_STR CONFIG_AUTOBOOT_STOP_STR - CONFIG_AUTOBOOT_DELAY_STR2 - CONFIG_AUTOBOOT_STOP_STR2 "bootdelaykey" environment variable "bootstopkey" environment variable - "bootdelaykey2" environment variable - "bootstopkey2" environment variable These options give more control over stopping autoboot. When they are used a specific character or string is required to @@ -130,12 +126,6 @@ What they do character of a key string does not appear in the rest of the string. - Using the CONFIG_AUTOBOOT_DELAY_STR2 #define or the - "bootdelaykey2" environment variable and/or the - CONFIG_AUTOBOOT_STOP_STR2 #define or the "bootstopkey" - environment variable you can specify a second, alternate - string (which allows you to have two "password" strings). - The CONFIG_AUTOBOOT_KEYED_CTRLC #define allows for the boot sequence to be interrupted by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey". Setting this variable diff --git a/doc/README.scrapyard b/doc/README.scrapyard index a62bd0ba4c..f029a0f757 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,12 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +mimc200 avr32 - c62d2f8f 2015-06-10 Mark Jackson <mpfj@mimc.co.uk> +hammerhead avr32 - e3693076 2015-06-10 Alex Raimondi <alex.raimondi@miromico.ch> +favr-32-ezkit avr32 - 9eb45aab 2015-06-10 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> afeb9260 arm arm926ejs f6b42c14 2015-05-13 Sergey Lapin <slapin@ossfans.org> tny_a9260 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com> sbc35_a9g20 arm arm926ejs f6b42c14 2015-05-13 Albin Tonnerre <albin.tonnerre@free-electrons.com> diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 65086484ee..4fb846ad37 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -39,7 +39,7 @@ u16 *ataid[AHCI_MAX_PORTS]; /* Maximum timeouts for each event */ #define WAIT_MS_SPINUP 20000 -#define WAIT_MS_DATAIO 5000 +#define WAIT_MS_DATAIO 10000 #define WAIT_MS_FLUSH 5000 #define WAIT_MS_LINKUP 200 @@ -726,18 +726,25 @@ static int ata_scsiop_inquiry(ccb *pccb) */ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) { - u32 lba = 0; + lbaint_t lba = 0; u16 blocks = 0; u8 fis[20]; u8 *user_buffer = pccb->pdata; u32 user_buffer_size = pccb->datalen; /* Retrieve the base LBA number from the ccb structure. */ - memcpy(&lba, pccb->cmd + 2, sizeof(lba)); - lba = be32_to_cpu(lba); + if (pccb->cmd[0] == SCSI_READ16) { + memcpy(&lba, pccb->cmd + 2, 8); + lba = be64_to_cpu(lba); + } else { + u32 temp; + memcpy(&temp, pccb->cmd + 2, 4); + lba = be32_to_cpu(temp); + } /* - * And the number of blocks. + * Retrieve the base LBA number and the block count from + * the ccb structure. * * For 10-byte and 16-byte SCSI R/W commands, transfer * length 0 means transfer 0 block of data. @@ -746,10 +753,13 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) * * WARNING: one or two older ATA drives treat 0 as 0... */ - blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); + if (pccb->cmd[0] == SCSI_READ16) + blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]); + else + blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); - debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", - is_write ? "write" : "read", (unsigned)lba, blocks); + debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n", + is_write ? "write" : "read", blocks, lba); /* Preset the FIS */ memset(fis, 0, sizeof(fis)); @@ -770,14 +780,23 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) return -EIO; } - /* LBA48 SATA command but only use 32bit address range within - * that. The next smaller command range (28bit) is too small. + /* + * LBA48 SATA command but only use 32bit address range within + * that (unless we've enabled 64bit LBA support). The next + * smaller command range (28bit) is too small. */ fis[4] = (lba >> 0) & 0xff; fis[5] = (lba >> 8) & 0xff; fis[6] = (lba >> 16) & 0xff; fis[7] = 1 << 6; /* device reg: set LBA mode */ fis[8] = ((lba >> 24) & 0xff); +#ifdef CONFIG_SYS_64BIT_LBA + if (pccb->cmd[0] == SCSI_READ16) { + fis[9] = ((lba >> 32) & 0xff); + fis[10] = ((lba >> 40) & 0xff); + } +#endif + fis[3] = 0xe0; /* features */ /* Block (sector) count */ @@ -883,6 +902,7 @@ int scsi_exec(ccb *pccb) int ret; switch (pccb->cmd[0]) { + case SCSI_READ16: case SCSI_READ10: ret = ata_scsiop_read_write(pccb, 0); break; diff --git a/drivers/core/Makefile b/drivers/core/Makefile index f14695b2d6..a3fec38503 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -5,5 +5,7 @@ # obj-$(CONFIG_DM) += device.o lists.o root.o uclass.o util.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_OF_CONTROL) += simple-bus.o +endif obj-$(CONFIG_DM_DEVICE_REMOVE) += device-remove.o diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0840a30fba..0c43777cef 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -35,3 +35,10 @@ config SANDBOX_GPIO_COUNT are specified using the device tree. But you can also have a number of 'anonymous' GPIOs that do not belong to any device or bank. Select a suitable value depending on your needs. + +config VYBRID_GPIO + bool "Vybrid GPIO driver" + depends on DM + default n + help + Say yes here to support Vybrid vf610 GPIOs. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index ba9efe8d54..586485055d 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o +obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 530bb3e128..bf982b9d19 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -757,6 +757,7 @@ static int gpio_pre_remove(struct udevice *dev) UCLASS_DRIVER(gpio) = { .id = UCLASS_GPIO, .name = "gpio", + .flags = DM_UC_FLAG_SEQ_ALIAS, .post_probe = gpio_post_probe, .pre_remove = gpio_pre_remove, .per_device_auto_alloc_size = sizeof(struct gpio_dev_priv), diff --git a/drivers/gpio/vybrid_gpio.c b/drivers/gpio/vybrid_gpio.c new file mode 100644 index 0000000000..6eaf0a9ad4 --- /dev/null +++ b/drivers/gpio/vybrid_gpio.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2015 + * Bhuvanchandra DV, Toradex, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct vybrid_gpios { + unsigned int chip; + struct vybrid_gpio_regs *reg; +}; + +static int vybrid_gpio_direction_input(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_IN); + + return 0; +} + +static int vybrid_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + gpio_set_value(gpio, value); + imx_iomux_gpio_set_direction(gpio, VF610_GPIO_DIRECTION_OUT); + + return 0; +} + +static int vybrid_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + + return ((readl(&gpios->reg->gpio_pdir) & (1 << gpio))) ? 1 : 0; +} + +static int vybrid_gpio_set_value(struct udevice *dev, unsigned gpio, + int value) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + if (value) + writel((1 << gpio), &gpios->reg->gpio_psor); + else + writel((1 << gpio), &gpios->reg->gpio_pcor); + + return 0; +} + +static int vybrid_gpio_get_function(struct udevice *dev, unsigned gpio) +{ + const struct vybrid_gpios *gpios = dev_get_priv(dev); + u32 g_state = 0; + + gpio = gpio + (gpios->chip * VYBRID_GPIO_COUNT); + + imx_iomux_gpio_get_function(gpio, &g_state); + + if (((g_state & (0x07 << PAD_MUX_MODE_SHIFT)) >> PAD_MUX_MODE_SHIFT) > 0) + return GPIOF_FUNC; + if (g_state & PAD_CTL_OBE_ENABLE) + return GPIOF_OUTPUT; + if (g_state & PAD_CTL_IBE_ENABLE) + return GPIOF_INPUT; + if (!(g_state & PAD_CTL_OBE_IBE_ENABLE)) + return GPIOF_UNUSED; + + return GPIOF_UNKNOWN; +} + +static const struct dm_gpio_ops gpio_vybrid_ops = { + .direction_input = vybrid_gpio_direction_input, + .direction_output = vybrid_gpio_direction_output, + .get_value = vybrid_gpio_get_value, + .set_value = vybrid_gpio_set_value, + .get_function = vybrid_gpio_get_function, +}; + +static int vybrid_gpio_probe(struct udevice *dev) +{ + struct vybrid_gpios *gpios = dev_get_priv(dev); + struct vybrid_gpio_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->bank_name = plat->port_name; + uc_priv->gpio_count = VYBRID_GPIO_COUNT; + gpios->reg = (struct vybrid_gpio_regs *)plat->base; + gpios->chip = plat->chip; + + return 0; +} + +static int vybrid_gpio_bind(struct udevice *dev) +{ + struct vybrid_gpio_platdata *plat = dev->platdata; + fdt_addr_t base_addr; + + if (plat) + return 0; + + base_addr = dev_get_addr(dev); + if (base_addr == FDT_ADDR_T_NONE) + return -ENODEV; + + /* + * TODO: + * When every board is converted to driver model and DT is + * supported, this can be done by auto-alloc feature, but + * not using calloc to alloc memory for platdata. + */ + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + + plat->base = base_addr; + plat->chip = dev->req_seq; + plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL); + dev->platdata = plat; + + return 0; +} + +#ifndef CONFIG_OF_CONTROL +static const struct vybrid_gpio_platdata vybrid_gpio[] = { + {0, GPIO0_BASE_ADDR, "GPIO0 "}, + {1, GPIO1_BASE_ADDR, "GPIO1 "}, + {2, GPIO2_BASE_ADDR, "GPIO2 "}, + {3, GPIO3_BASE_ADDR, "GPIO3 "}, + {4, GPIO4_BASE_ADDR, "GPIO4 "}, +}; + +U_BOOT_DEVICES(vybrid_gpio) = { + { "gpio_vybrid", &vybrid_gpio[0] }, + { "gpio_vybrid", &vybrid_gpio[1] }, + { "gpio_vybrid", &vybrid_gpio[2] }, + { "gpio_vybrid", &vybrid_gpio[3] }, + { "gpio_vybrid", &vybrid_gpio[4] }, +}; +#endif + +static const struct udevice_id vybrid_gpio_ids[] = { + { .compatible = "fsl,vf610-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_vybrid) = { + .name = "gpio_vybrid", + .id = UCLASS_GPIO, + .ops = &gpio_vybrid_ops, + .probe = vybrid_gpio_probe, + .priv_auto_alloc_size = sizeof(struct vybrid_gpios), + .of_match = vybrid_gpio_ids, + .bind = vybrid_gpio_bind, +}; diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c index 223f238f4b..5606d1f807 100644 --- a/drivers/i2c/i2c-uclass-compat.c +++ b/drivers/i2c/i2c-uclass-compat.c @@ -106,3 +106,24 @@ void board_i2c_init(const void *blob) { /* Nothing to do here - the init happens through driver model */ } + +uint8_t i2c_reg_read(uint8_t chip_addr, uint8_t offset) +{ + struct udevice *dev; + int ret; + + ret = i2c_compat_get_device(chip_addr, 1, &dev); + if (ret) + return 0xff; + return dm_i2c_reg_read(dev, offset); +} + +void i2c_reg_write(uint8_t chip_addr, uint8_t offset, uint8_t val) +{ + struct udevice *dev; + int ret; + + ret = i2c_compat_get_device(chip_addr, 1, &dev); + if (!ret) + dm_i2c_reg_write(dev, offset, val); +} diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index fd7e4d499f..ca485ba90c 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -588,7 +588,9 @@ static int imx_pcie_link_up(void) udelay(10); count++; if (count >= 2000) { - debug("phy link never came up\n"); +#ifdef CONFIG_PCI_SCAN_SHOW + puts("PCI: pcie phy link never came up\n"); +#endif debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R0), readl(MX6_DBI_ADDR + PCIE_PHY_DEBUG_R1)); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5611fac0dc..4829284216 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -76,6 +76,26 @@ config DEBUG_UART_SHIFT value. Use this value to specify the shift to use, where 0=byte registers, 2=32-bit word registers, etc. +config SANDBOX_SERIAL + bool "Sandbox UART support" + depends on SANDBOX && DM + help + Select this to enable a seral UART for sandbox. This is required to + operate correctly, otherwise you will see no serial output from + sandbox. The emulated UART will display to the console and console + input will be fed into the UART. This allows you to interact with + U-Boot. + + The operation of the console is controlled by the -t command-line + flag. In raw mode, U-Boot sees all characters from the terminal + before they are processed, including Ctrl-C. In cooked mode, Ctrl-C + is processed by the terminal, and terminates U-Boot. Valid options + are: + + -t raw-with-sigs Raw mode, Ctrl-C will terminate U-Boot + -t raw Raw mode, Ctrl-C is processed by U-Boot + -t cooked Cooked mode, Ctrl-C terminates + config UNIPHIER_SERIAL bool "Support for UniPhier on-chip UART" depends on ARCH_UNIPHIER && DM_SERIAL diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 3d376d7580..9b044a37da 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -65,6 +65,8 @@ static inline void serial_out_shift(void *addr, int shift, int value) out_le32(addr, value); #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) out_be32(addr, value); +#elif defined(CONFIG_SYS_NS16550_MEM32) + writel(value, addr); #elif defined(CONFIG_SYS_BIG_ENDIAN) writeb(value, addr + (1 << shift) - 1); #else @@ -80,6 +82,8 @@ static inline int serial_in_shift(void *addr, int shift) return in_le32(addr); #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) return in_be32(addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) + return readl(addr); #elif defined(CONFIG_SYS_BIG_ENDIAN) return readb(addr + (1 << shift) - 1); #else diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index b8c2f48228..815fec3264 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -30,49 +30,55 @@ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; static void serial_find_console_or_panic(void) { struct udevice *dev; - -#ifdef CONFIG_OF_CONTROL int node; - /* Check for a chosen console */ - node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); - if (node < 0) - node = fdt_path_offset(gd->fdt_blob, "console"); - if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) { - gd->cur_serial_dev = dev; - return; - } - - /* - * If the console is not marked to be bound before relocation, bind - * it anyway. - */ - if (node > 0 && - !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) { - if (!device_probe(dev)) { + if (OF_CONTROL && gd->fdt_blob) { + /* Check for a chosen console */ + node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); + if (node < 0) + node = fdt_path_offset(gd->fdt_blob, "console"); + if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, + &dev)) { gd->cur_serial_dev = dev; return; } + + /* + * If the console is not marked to be bound before relocation, + * bind it anyway. + */ + if (node > 0 && + !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) { + if (!device_probe(dev)) { + gd->cur_serial_dev = dev; + return; + } + } } -#endif - /* - * Try to use CONFIG_CONS_INDEX if available (it is numbered from 1!). - * - * Failing that, get the device with sequence number 0, or in extremis - * just the first serial device we can find. But we insist on having - * a console (even if it is silent). - */ + if (!SPL_BUILD || !OF_CONTROL || !gd->fdt_blob) { + /* + * Try to use CONFIG_CONS_INDEX if available (it is numbered + * from 1!). + * + * Failing that, get the device with sequence number 0, or in + * extremis just the first serial device we can find. But we + * insist on having a console (even if it is silent). + */ #ifdef CONFIG_CONS_INDEX #define INDEX (CONFIG_CONS_INDEX - 1) #else #define INDEX 0 #endif - if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) && - uclass_get_device(UCLASS_SERIAL, INDEX, &dev) && - (uclass_first_device(UCLASS_SERIAL, &dev) || !dev)) - panic_str("No serial driver found"); + if (!uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) || + !uclass_get_device(UCLASS_SERIAL, INDEX, &dev) || + (!uclass_first_device(UCLASS_SERIAL, &dev) || dev)) { + gd->cur_serial_dev = dev; + return; + } #undef INDEX - gd->cur_serial_dev = dev; + } + + panic_str("No serial driver found"); } /* Called prior to relocation */ diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 4bec66309e..d7eecd5bc6 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -143,24 +143,30 @@ static int tegra114_spi_probe(struct udevice *bus) { struct tegra_spi_platdata *plat = dev_get_platdata(bus); struct tegra114_spi_priv *priv = dev_get_priv(bus); + struct spi_regs *regs; + ulong rate; priv->regs = (struct spi_regs *)plat->base; + regs = priv->regs; priv->last_transaction_us = timer_get_us(); priv->freq = plat->frequency; priv->periph_id = plat->periph_id; - return 0; -} - -static int tegra114_spi_claim_bus(struct udevice *dev) -{ - struct udevice *bus = dev->parent; - struct tegra114_spi_priv *priv = dev_get_priv(bus); - struct spi_regs *regs = priv->regs; - - /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + /* + * Change SPI clock to correct frequency, PLLP_OUT0 source, falling + * back to the oscillator if that is too fast. + */ + rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, + priv->freq); + if (rate > priv->freq + 100000) { + rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC, + priv->freq); + if (rate != priv->freq) { + printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n", + bus->name, priv->freq, rate); + } + } /* Clear stale status here */ setbits_le32(®s->fifo_status, @@ -175,9 +181,8 @@ static int tegra114_spi_claim_bus(struct udevice *dev) SPI_FIFO_STS_RX_FIFO_EMPTY); debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); - /* Set master mode and sw controlled CS */ - setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | - (priv->mode << SPI_CMD1_MODE_SHIFT)); + setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | + (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL); debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); return 0; @@ -249,6 +254,9 @@ static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, ret = 0; + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + /* clear all error status bits */ reg = readl(®s->fifo_status); writel(reg, ®s->fifo_status); @@ -260,9 +268,6 @@ static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, /* set xfer size to 1 block (32 bits) */ writel(0, ®s->dma_blk); - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(dev); - /* handle data in 32-bit chunks */ while (num_bytes > 0) { int bytes; @@ -385,7 +390,6 @@ static int tegra114_spi_set_mode(struct udevice *bus, uint mode) } static const struct dm_spi_ops tegra114_spi_ops = { - .claim_bus = tegra114_spi_claim_bus, .xfer = tegra114_spi_xfer, .set_speed = tegra114_spi_set_speed, .set_mode = tegra114_spi_set_mode, diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 27705d6627..e2574d7958 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -35,12 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif #endif -#ifndef CONFIG_DM_USB -enum { - USB_PORTS_MAX = 3, /* Maximum ports we allow */ -}; -#endif - /* Parameters we need for USB */ enum { PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ @@ -82,9 +76,6 @@ struct fdt_usb { unsigned ulpi:1; /* 1 if port has external ULPI transceiver */ unsigned enabled:1; /* 1 to enable, 0 to disable */ unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ -#ifndef CONFIG_DM_USB - unsigned initialized:1; /* has this port already been initialized? */ -#endif enum usb_ctlr_type type; enum usb_init_type init_type; enum dr_mode dr_mode; /* dual role mode */ @@ -93,11 +84,6 @@ struct fdt_usb { struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */ }; -#ifndef CONFIG_DM_USB -static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ -static unsigned port_count; /* Number of available ports */ -#endif - /* * This table has USB timing parameters for each Oscillator frequency we * support. There are four sets of values: @@ -173,8 +159,6 @@ static const u8 utmip_elastic_limit = 16; static const u8 utmip_hs_sync_start_delay = 9; struct fdt_usb_controller { - /* TODO(sjg@chromium.org): Remove when we only use driver model */ - int compat; /* flag to determine whether controller supports hostpc register */ u32 has_hostpc:1; const unsigned *pll_parameter; @@ -182,17 +166,14 @@ struct fdt_usb_controller { static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = { { - .compat = COMPAT_NVIDIA_TEGRA20_USB, .has_hostpc = 0, .pll_parameter = (const unsigned *)T20_usb_pll, }, { - .compat = COMPAT_NVIDIA_TEGRA30_USB, .has_hostpc = 1, .pll_parameter = (const unsigned *)T30_usb_pll, }, { - .compat = COMPAT_NVIDIA_TEGRA114_USB, .has_hostpc = 1, .pll_parameter = (const unsigned *)T114_usb_pll, }, @@ -754,12 +735,6 @@ int usb_common_init(struct fdt_usb *config, enum usb_init_type init) return -1; } -#ifndef CONFIG_DM_USB - /* skip init, if the port is already initialized */ - if (config->initialized && config->init_type == init) - return 0; -#endif - debug("%d, %d\n", config->utmi, config->ulpi); if (config->utmi) ret = init_utmi_usb_controller(config, init); @@ -796,130 +771,6 @@ static const struct ehci_ops tegra_ehci_ops = { .powerup_fixup = tegra_ehci_powerup_fixup, }; -#ifndef CONFIG_DM_USB -/* - * process_usb_nodes() - Process a list of USB nodes, adding them to our list - * of USB ports. - * @blob: fdt blob - * @node_list: list of nodes to process (any <=0 are ignored) - * @count: number of nodes to process - * @id: controller type (enum usb_ctlr_type) - * - * Return: 0 - ok, -1 - error - */ -static int process_usb_nodes(const void *blob, int node_list[], int count, - enum usb_ctlr_type id) -{ - struct fdt_usb config; - int node, i; - int clk_done = 0; - - port_count = 0; - for (i = 0; i < count; i++) { - if (port_count == USB_PORTS_MAX) { - printf("tegrausb: Cannot register more than %d ports\n", - USB_PORTS_MAX); - return -1; - } - - debug("USB %d: ", i); - node = node_list[i]; - if (!node) - continue; - if (fdt_decode_usb(blob, node, &config)) { - debug("Cannot decode USB node %s\n", - fdt_get_name(blob, node, NULL)); - return -1; - } - if (!clk_done) { - config_clock(get_pll_timing( - &fdt_usb_controllers[id])); - clk_done = 1; - } - config.type = id; - config.initialized = 0; - - /* add new USB port to the list of available ports */ - port[port_count++] = config; - } - - return 0; -} - -int usb_process_devicetree(const void *blob) -{ - int node_list[USB_PORTS_MAX]; - int count, err = 0; - int i; - - for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) { - count = fdtdec_find_aliases_for_id(blob, "usb", - fdt_usb_controllers[i].compat, node_list, - USB_PORTS_MAX); - if (count) { - err = process_usb_nodes(blob, node_list, count, i); - if (err) - printf("%s: Error processing USB node!\n", - __func__); - return err; - } - } - - return err; -} - -/** - * Start up the given port number (ports are numbered from 0 on each board). - * This returns values for the appropriate hccr and hcor addresses to use for - * USB EHCI operations. - * - * @param index port number to start - * @param hccr returns start address of EHCI HCCR registers - * @param hcor returns start address of EHCI HCOR registers - * @return 0 if ok, -1 on error (generally invalid port number) - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - struct fdt_usb *config; - struct usb_ctlr *usbctlr; - int ret; - - if (index >= port_count) - return -1; - - config = &port[index]; - ehci_set_controller_priv(index, config, &tegra_ehci_ops); - - ret = usb_common_init(config, init); - if (ret) { - printf("tegrausb: Cannot init port %d\n", index); - return ret; - } - - config->initialized = 1; - - usbctlr = config->reg; - *hccr = (struct ehci_hccr *)&usbctlr->cap_length; - *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd; - - return 0; -} - -/* - * Bring down the specified USB controller - */ -int ehci_hcd_stop(int index) -{ - usb_common_uninit(&port[index]); - - port[index].initialized = 0; - - return 0; -} -#endif /* !CONFIG_DM_USB */ - -#ifdef CONFIG_DM_USB static int ehci_usb_ofdata_to_platdata(struct udevice *dev) { struct fdt_usb *priv = dev_get_priv(dev); @@ -987,4 +838,3 @@ U_BOOT_DRIVER(usb_ehci) = { .priv_auto_alloc_size = sizeof(struct fdt_usb), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 54548554df..98e0fc6ca6 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -121,6 +121,11 @@ static void usb_oc_config(int index) setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); } +int __weak board_ehci_hcd_init(int port) +{ + return 0; +} + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -136,6 +141,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, ehci = (struct usb_ehci *)nc_reg_bases[index]; + /* Do board specific initialisation */ + board_ehci_hcd_init(index); + usb_power_config(index); usb_oc_config(index); usb_internal_phy_clock_gate(index); diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 963464cff9..6e86f4a24a 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -628,6 +628,49 @@ int usb_scan_device(struct udevice *parent, int port, return 0; } +/* + * Detect if a USB device has been plugged or unplugged. + */ +int usb_detect_change(void) +{ + struct udevice *hub; + struct uclass *uc; + int change = 0; + int ret; + + ret = uclass_get(UCLASS_USB_HUB, &uc); + if (ret) + return ret; + + uclass_foreach_dev(hub, uc) { + struct usb_device *udev; + struct udevice *dev; + + if (!device_active(hub)) + continue; + for (device_find_first_child(hub, &dev); + dev; + device_find_next_child(&dev)) { + struct usb_port_status status; + + if (!device_active(dev)) + continue; + + udev = dev_get_parentdata(dev); + if (usb_get_port_status(udev, udev->portnr, &status) + < 0) + /* USB request failed */ + continue; + + if (le16_to_cpu(status.wPortChange) & + USB_PORT_STAT_C_CONNECTION) + change++; + } + } + + return change; +} + int usb_child_post_bind(struct udevice *dev) { struct usb_dev_platdata *plat = dev_get_parent_platdata(dev); diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 4ed3a49bec..d43d8a59d3 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -81,12 +81,12 @@ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) #endif } -void lcd_set_cmap(bmp_image_t *bmp, unsigned colors) +void lcd_set_cmap(struct bmp_image *bmp, unsigned colors) { int i; for (i = 0; i < colors; ++i) { - bmp_color_table_entry_t cte = bmp->color_table[i]; + struct bmp_color_table_entry cte = bmp->color_table[i]; lcd_setcolreg(i, cte.red, cte.green, cte.blue); } } diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c index 60a5cc5b71..2f54d3d147 100644 --- a/drivers/video/bus_vcxk.c +++ b/drivers/video/bus_vcxk.c @@ -358,7 +358,7 @@ void vcxk_draw_mono(unsigned char *dataptr, unsigned long linewidth, int vcxk_display_bitmap(ulong addr, int x, int y) { - bmp_image_t *bmp; + struct bmp_image *bmp; unsigned long width; unsigned long height; unsigned long bpp; @@ -369,7 +369,7 @@ int vcxk_display_bitmap(ulong addr, int x, int y) unsigned long c_height; unsigned char *dataptr; - bmp = (bmp_image_t *) addr; + bmp = (struct bmp_image *)addr; if ((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M')) { width = le32_to_cpu(bmp->header.width); diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index f4231b8e62..7f2ddc10c6 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1295,7 +1295,7 @@ static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p, *fb = (uchar *) addr; /* return modified address */ } -static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff, +static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, int width, int height) { unsigned char *bm; @@ -1304,7 +1304,7 @@ static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff, int decode = 1; int x, y, bpp, i, ncolors; struct palette p[256]; - bmp_color_table_entry_t cte; + struct bmp_color_table_entry cte; int green_shift, red_off; int limit = VIDEO_COLS * VIDEO_ROWS; int pixels = 0; @@ -1447,13 +1447,13 @@ int video_display_bitmap(ulong bmp_image, int x, int y) { ushort xcount, ycount; uchar *fb; - bmp_image_t *bmp = (bmp_image_t *) bmp_image; + struct bmp_image *bmp = (struct bmp_image *)bmp_image; uchar *bmap; ushort padded_line; unsigned long width, height, bpp; unsigned colors; unsigned long compression; - bmp_color_table_entry_t cte; + struct bmp_color_table_entry cte; #ifdef CONFIG_VIDEO_BMP_GZIP unsigned char *dst = NULL; @@ -1495,7 +1495,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y) /* * Set addr to decompressed image */ - bmp = (bmp_image_t *)(dst+2); + bmp = (struct bmp_image *)(dst+2); if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { diff --git a/drivers/video/tegra124/tegra124-lcd.c b/drivers/video/tegra124/tegra124-lcd.c index 2733590754..cfdc77ffe3 100644 --- a/drivers/video/tegra124/tegra124-lcd.c +++ b/drivers/video/tegra124/tegra124-lcd.c @@ -51,15 +51,13 @@ static int tegra124_lcd_init(void *lcdbase) int ret; clock_set_up_plldp(); - clock_adjust_periph_pll_div(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, - 408000000, NULL); + clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000); clock_enable(PERIPH_ID_HOST1X); clock_enable(PERIPH_ID_DISP1); clock_enable(PERIPH_ID_PWM); clock_enable(PERIPH_ID_DPAUX); clock_enable(PERIPH_ID_SOR0); - udelay(2); reset_set_enable(PERIPH_ID_HOST1X, 0); diff --git a/include/bmp_layout.h b/include/bmp_layout.h index 22b1fbc943..55db8b86ea 100644 --- a/include/bmp_layout.h +++ b/include/bmp_layout.h @@ -11,17 +11,17 @@ #ifndef _BMP_H_ #define _BMP_H_ -typedef struct bmp_color_table_entry { +struct __packed bmp_color_table_entry { __u8 blue; __u8 green; __u8 red; __u8 reserved; -} __attribute__ ((packed)) bmp_color_table_entry_t; +}; /* When accessing these fields, remember that they are stored in little endian format, so use linux macros, e.g. le32_to_cpu(width) */ -typedef struct bmp_header { +struct __packed bmp_header { /* Header */ char signature[2]; __u32 file_size; @@ -40,15 +40,14 @@ typedef struct bmp_header { __u32 colors_used; __u32 colors_important; /* ColorTable */ +}; -} __attribute__ ((packed)) bmp_header_t; - -typedef struct bmp_image { - bmp_header_t header; +struct bmp_image { + struct bmp_header header; /* We use a zero sized array just as a placeholder for variable sized array */ - bmp_color_table_entry_t color_table[0]; -} bmp_image_t; + struct bmp_color_table_entry color_table[0]; +}; /* Data in the bmp_image is aligned to this length */ #define BMP_DATA_ALIGN 4 diff --git a/include/common.h b/include/common.h index ea5aeb0014..8f4b2ec212 100644 --- a/include/common.h +++ b/include/common.h @@ -714,6 +714,21 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop); void invalidate_dcache_all(void); void invalidate_icache_all(void); +enum { + /* Disable caches (else flush caches but leave them active) */ + CBL_DISABLE_CACHES = 1 << 0, + CBL_SHOW_BOOTSTAGE_REPORT = 1 << 1, + + CBL_ALL = 3, +}; + +/** + * Clean up ready for linux + * + * @param flags Flags to control what is done + */ +int cleanup_before_linux_select(int flags); + /* arch/$(ARCH)/lib/ticks.S */ uint64_t get_ticks(void); void wait_ticks (unsigned long); diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 38cb0e8aba..c191f5634e 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -20,7 +20,9 @@ #undef CONFIG_CMD_SNTP #undef CONFIG_CMD_TFTPPUT #undef CONFIG_CMD_TFTPSRV +#ifdef CONFIG_SPL_DISABLE_OF_CONTROL #undef CONFIG_OF_CONTROL +#endif #ifndef CONFIG_SPL_DM #undef CONFIG_DM_SERIAL diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index ceddd7accc..c20ecbd06d 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -141,12 +141,6 @@ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ /*----------------------------------------------------------------------- diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index a236e117a0..80f42768f0 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -138,15 +138,6 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -/* Only interrupt boot if space is pressed */ -/* If a long serial cable is connected but */ -/* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index f7d28e39dd..a64c82a272 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -110,12 +110,6 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - /* * PCI stuff */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index b8d4dc5eb8..31b9050032 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -331,12 +331,6 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR -#define CONFIG_AUTOBOOT_STOP_STR " " - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------*/ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index ec52d6a768..b9bbe340f3 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -626,17 +626,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -/* - * Autobooting - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "\x1b" -#define DEBUG_BOOTKEYS 0 -#undef CONFIG_AUTOBOOT_DELAY_STR -#undef CONFIG_BOOTARGS -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press \"<Esc>\" to stop\n", bootdelay - #define CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 00589b7e68..b03f163d65 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -123,10 +123,6 @@ #define CONFIG_SYS_AUTOLOAD "n" -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "asdfg" - #undef CONFIG_BOOTARGS #define CONFIG_PREBOOT "run try_update" diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 8da3325b7e..a5f1f06c22 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -54,12 +54,12 @@ "${optargs} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ "nandrootfstype=ubifs rootwait=1\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${fdtaddr} u-boot-spl-os; " \ - "nand read ${loadaddr} kernel; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ "bootz ${loadaddr} - ${fdtaddr}\0" #else #define NANDARGS "" @@ -248,7 +248,7 @@ "128k(NAND.u-boot-env)," \ "128k(NAND.u-boot-env.backup1)," \ "8m(NAND.kernel)," \ - "-(NAND.rootfs)" + "-(NAND.file-system)" #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_NAND diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d4f4c236a9..9d6511118a 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -17,7 +17,7 @@ #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include <asm/arch/omap.h> @@ -295,13 +295,15 @@ "setenv fdtfile am437x-idk-evm.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree; fi; \0" \ + NANDARGS \ NETARGS \ DFUARGS \ #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ "run mmcboot;" \ - "run usbboot;" + "run usbboot;" \ + NANDBOOT \ #endif @@ -378,7 +380,7 @@ "256k(NAND.u-boot-env)," \ "256k(NAND.u-boot-env.backup1)," \ "7m(NAND.kernel)," \ - "-(NAND.rootfs)" + "-(NAND.file-system)" #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 /* NAND: SPL related configs */ #ifdef CONFIG_SPL_NAND_SUPPORT @@ -390,6 +392,24 @@ #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ #define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #endif -#endif /* !CONFIG_NAND */ +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ + "nand read ${loadaddr} NAND.kernel; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" +#define NANDBOOT "run nandboot; " +#else /* !CONFIG_NAND */ +#define NANDARGS +#define NANDBOOT +#endif /* CONFIG_NAND */ #endif /* __CONFIG_AM43XX_EVM_H */ diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 540e86ae47..c4a69526e7 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -14,6 +14,9 @@ #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + /* * Set up the PLL to run at 140 MHz, the CPU to run at the PLL * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency @@ -59,17 +62,7 @@ #define CONFIG_BOOTCOMMAND \ "fsload; bootm" -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 83747336c6..868ec3a6cf 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -16,7 +16,6 @@ #define CONFIG_AT32AP7000 #define CONFIG_ATNGW100MKII -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R @@ -82,17 +81,7 @@ #define CONFIG_BOOTCOMMAND \ "fsload 0x10400000 /uImage; bootm" -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index a9c064a45d..4beb068da0 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -79,17 +79,7 @@ #define CONFIG_BOOTCOMMAND \ "fsload; bootm $(fileaddr)" -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " /* * After booting the board for the first time, new ethernet addresses @@ -105,7 +95,6 @@ #define CONFIG_BOOTP_GATEWAY /* generic board */ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h deleted file mode 100644 index b2ad30ec90..0000000000 --- a/include/configs/atstk1003.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation - * - * Configuration settings for the ATSTK1003 CPU daughterboard - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7001 -#define CONFIG_ATSTK1003 -#define CONFIG_ATSTK1000 - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mmcblk0p1 rootwait" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm" - -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h deleted file mode 100644 index 19f049a519..0000000000 --- a/include/configs/atstk1004.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2007 Atmel Corporation - * - * Configuration settings for the ATSTK1003 CPU daughterboard - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7002 -#define CONFIG_ATSTK1004 -#define CONFIG_ATSTK1000 - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mmcblk0p1 rootwait" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm" - -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 2MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h deleted file mode 100644 index 25090a68fa..0000000000 --- a/include/configs/atstk1006.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2005-2006 Atmel Corporation - * - * Configuration settings for the ATSTK1002 CPU daughterboard - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_ATSTK1006 -#define CONFIG_ATSTK1000 - - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=mtd3 fbmem=2400k" - -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm $(fileaddr)" - -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/baltos.h b/include/configs/baltos.h new file mode 100644 index 0000000000..6242895014 --- /dev/null +++ b/include/configs/baltos.h @@ -0,0 +1,340 @@ +/* + * am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_BALTOS_H +#define __CONFIG_BALTOS_H + +#include <configs/ti_am335x_common.h> + +#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM +#define CONFIG_BOARD_LATE_INIT + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/vscom/baltos/u-boot.lds" + +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* FIT support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +#define CONFIG_OF_BOARD_SETUP + +/* UBI Support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS + +/* I2C configuration */ +#undef CONFIG_SYS_OMAP24_I2C_SPEED +#define CONFIG_SYS_OMAP24_I2C_SPEED 10000 + +#ifdef CONFIG_NAND +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif +#define NANDARGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "setenv loadaddr 0x84000000; " \ + "ubi part UBI; " \ + "ubifsmount ubi0:kernel; " \ + "ubifsload $loadaddr kernel-fit.itb;" \ + "ubifsumount; " \ + "bootm ${loadaddr}#conf${board_name}\0" +#else +#define NANDARGS "" +#endif + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + "boot_fdt=try\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ + "fdtfile=undefined\0" \ + "console=ttyO0,115200n8\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ + "ramroot=/dev/ram0 rw\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "${mtdparts} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "mmcloados=run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi;\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootz ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ + "run netargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ + "findfdt=setenv fdtfile am335x-baltos.dtb\0" \ + NANDARGS + /*DFUARGS*/ +#endif + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run mmcboot;" \ + "setenv mmcdev 1; " \ + "setenv bootpart 1:2; " \ + "run mmcboot;" \ + "run nandboot;" + +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_NFS + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS + +/* PMIC support */ +#define CONFIG_POWER_TPS65910 + +/* SPL */ +#ifndef CONFIG_NOR_BOOT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +/* Bootcount using the RTC block */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_BOOTCOUNT_AM33XX + +/* USB gadget RNDIS */ +/*#define CONFIG_SPL_MUSB_NEW_SUPPORT*/ + +/* General network SPL, both CPSW and USB gadget RNDIS */ +/*#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/ + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#ifdef CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#endif +#endif + +/* + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" +#endif /* CONFIG_MUSB_GADGET */ + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* disable EFI partitions and partition UUID support */ +#undef CONFIG_PARTITION_UUIDS +#undef CONFIG_EFI_PARTITION +/* + * Disable CPSW SPL support so we fit within the 101KiB limit. + */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* Network. */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_SMSC +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_PHY_ATHEROS + +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 +#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3)," \ + "1920k(u-boot)," \ + "-(UBI)" +#define CONFIG_ENV_IS_NOWHERE +#endif +#endif + +#endif /* ! __CONFIG_BALTOS_H */ diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h index 369f7b82e6..8d072c6ed0 100644 --- a/include/configs/beagle_x15.h +++ b/include/configs/beagle_x15.h @@ -14,6 +14,10 @@ #define CONFIG_AM57XX +#ifdef CONFIG_SPL_BUILD +#define CONFIG_IODELAY_RECALIBRATION +#endif + #define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_ENV_SIZE (64 << 10) diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 84ef4ed4c2..b5e59ffe04 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -269,10 +269,6 @@ /* These are for board tests */ #if 0 #define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds: press space to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR " " #endif diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 5169b41b4f..8353fc95dd 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -221,8 +221,6 @@ #define CONFIG_BOOTDELAY 0 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_DELAY_STR "\x0d" /* press ENTER to interrupt BOOT */ #define CONFIG_RESET_TO_RETRY /* diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 4dec42a953..f26aad4d8b 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -54,6 +54,11 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR +/* GPIO support */ +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO +#define CONFIG_VYBRID_GPIO + /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */ #define CONFIG_MTD_PARTITIONS @@ -266,4 +271,11 @@ #define CONFIG_USB_GADGET_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE +/* Enable SPI support */ +#ifdef CONFIG_OF_CONTROL +#define CONFIG_DM_SPI +#define CONFIG_CMD_SPI +#define CONFIG_FSL_DSPI +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 8c7d97a18e..77d3ab878c 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -195,12 +195,6 @@ #define CONFIG_DEVICE_NULLDEV #define CONFIG_SILENT_CONSOLE -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot\n" -#define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_AUTOBOOT_DELAY_STR "d" - #define CONFIG_VERSION_VARIABLE #define MTDIDS_DEFAULT "nor0=physmap-flash.0" diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 76ec168c20..06da3c3e76 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -396,10 +396,6 @@ #define CONFIG_CMDLINE_EDITING 1 #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR " " - #define CONFIG_LOOPW 1 #define CONFIG_MX_CYCLIC 1 #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index d9bd564880..0f67595903 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -29,8 +29,6 @@ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR " " /* * Configure PLL diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 77edc21d9c..24fe1231f1 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -15,6 +15,10 @@ #define CONFIG_DRA7XX #define CONFIG_BOARD_EARLY_INIT_F +#ifdef CONFIG_SPL_BUILD +#define CONFIG_IODELAY_RECALIBRATION +#endif + #ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC @@ -38,6 +42,7 @@ #define CONFIG_SYS_OMAP_ABE_SYSCK +#ifndef CONFIG_SPL_BUILD /* Define the default GPT table for eMMC */ #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ @@ -91,6 +96,7 @@ #define CONFIG_USB_FASTBOOT_BUF_SIZE 0x2F000000 #define CONFIG_FASTBOOT_FLASH #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif #include <configs/ti_omap5_common.h> @@ -248,7 +254,7 @@ "128k(NAND.u-boot-env)," \ "128k(NAND.u-boot-env.backup1)," \ "8m(NAND.kernel)," \ - "-(NAND.rootfs)" + "-(NAND.file-system)" #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 /* NAND: SPL related configs */ #ifdef CONFIG_SPL_NAND_SUPPORT diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h deleted file mode 100644 index 75bff4ce28..0000000000 --- a/include/configs/favr-32-ezkit.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (C) 2008 Atmel Corporation - * - * Configuration settings for the Favr-32 EarthLCD LCD kit. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_FAVR32_EZKIT - -#define CONFIG_FAVR32_EZKIT_EXT_FLASH - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the - * PLL frequency. - * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 20000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 7 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -/* - * Set the CPU running at: - * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz - */ -#define CONFIG_SYS_CLKDIV_CPU 0 -/* - * Set the HSB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz - */ -#define CONFIG_SYS_CLKDIV_HSB 1 -/* - * Set the PBA running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz - */ -#define CONFIG_SYS_CLKDIV_PBA 2 -/* - * Set the PBB running at: - * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz - */ -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART3 -#define CONFIG_USART_ID 3 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k" - -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm $(fileaddr)" - -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -/* External flash on Favr-32 */ -#if 0 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#endif - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index 12fd75d743..bfaba42643 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_GENERIC_BOARD #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR " " /* * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index 54eb9777d7..e183f518d4 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -62,7 +62,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_USART1 #define CONFIG_USART_ID 1 -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R @@ -75,17 +74,7 @@ #define CONFIG_BAUDRATE 115200 -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d" \ - " seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " /* * After booting the board for the first time, new ethernet addresses diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h deleted file mode 100644 index 0bc42f12e0..0000000000 --- a/include/configs/hammerhead.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) 2008 Miromico AG - * - * Configuration settings for the Miromico Hammerhead AVR32 board - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_HAMMERHEAD - -/* - * Set up the PLL to run at 125 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency - * and the PBA bus to run at 1/4 the PLL frequency. - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 25000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 5 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -#define CONFIG_SYS_CLKDIV_CPU 0 -#define CONFIG_SYS_CLKDIV_HSB 1 -#define CONFIG_SYS_CLKDIV_PBA 2 -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM and NOR flash */ -#define CONFIG_SYS_NR_VM_REGIONS 2 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -#define CONFIG_HOSTNAME hammerhead - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "console=ttyS0 root=mtd1 rootfstype=jffs2" -#define CONFIG_BOOTCOMMAND \ - "fsload; bootm" - -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " - -/* - * After booting the board for the first time, new ethernet address - * should be generated and assigned to the environment variables - * "ethaddr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP/DHCP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_SETGETDCR - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE 0x24000000 -#define CONFIG_SYS_INTRAM_SIZE 0x8000 - -#define CONFIG_SYS_SDRAM_BASE 0x10000000 - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (256*1024) - - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "Hammerhead> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index da1c837cc7..08dcdf8986 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -63,9 +63,7 @@ #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_RESET_TO_RETRY -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n", bootdelay -#define CONFIG_AUTOBOOT_KEYED_CTRLC + /* * Miscellaneous configurable options */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 2916987cf2..bea19853c9 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -490,8 +490,6 @@ int fpga_gpio_get(unsigned int bus, int pin); #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 8b4278dfd3..10f840db32 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -25,10 +25,6 @@ #define CONFIG_MISC_INIT_R -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY -#define CONFIG_AUTOBOOT_DELAY_STR "ids" #define CONFIG_BOOT_RETRY_TIME 900 #define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_BOOTDELAY 1 diff --git a/include/configs/intip.h b/include/configs/intip.h index 928eb5b9db..18d314006f 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -51,8 +51,6 @@ #define CFG_ALT_MEMTEST #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR " " /* * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/io.h b/include/configs/io.h index d4ae0adfda..810193343f 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -35,8 +35,6 @@ #define PLLMR1_DEFAULT PLLMR1_266_133_66 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR " " /* new uImage format support */ #define CONFIG_FIT diff --git a/include/configs/io64.h b/include/configs/io64.h index 2a9ff376ef..94ccb6bab7 100644 --- a/include/configs/io64.h +++ b/include/configs/io64.h @@ -46,8 +46,6 @@ #define CONFIG_SYS_GENERIC_BOARD #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR " " /* new uImage format support */ #define CONFIG_FIT diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 38d473de42..9d9dabf242 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -34,8 +34,6 @@ #define PLLMR1_DEFAULT PLLMR1_266_133_66 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR " " /* new uImage format support */ #define CONFIG_FIT diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 73bbcb6b69..a6aed5d65f 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -136,7 +136,6 @@ /* Enable this if bootretry required; currently it's disabled */ #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" /* diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h deleted file mode 100644 index e8e5ae73ec..0000000000 --- a/include/configs/mimc200.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * Configuration settings for the AVR32 Network Gateway - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/hardware.h> - -#define CONFIG_AT32AP -#define CONFIG_AT32AP7000 -#define CONFIG_MIMC200 - -#define CONFIG_MIMC200_EXT_FLASH - -/* - * Set up the PLL to run at 140 MHz, the CPU to run at the PLL - * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency - * and the PBA bus to run at 1/4 the PLL frequency. - */ -#define CONFIG_PLL -#define CONFIG_SYS_POWER_MANAGER -#define CONFIG_SYS_OSC0_HZ 10000000 -#define CONFIG_SYS_PLL0_DIV 1 -#define CONFIG_SYS_PLL0_MUL 15 -#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 -#define CONFIG_SYS_CLKDIV_CPU 0 -#define CONFIG_SYS_CLKDIV_HSB 1 -#define CONFIG_SYS_CLKDIV_PBA 2 -#define CONFIG_SYS_CLKDIV_PBB 1 - -/* Reserve VM regions for SDRAM, NOR flash and FRAM */ -#define CONFIG_SYS_NR_VM_REGIONS 3 - -/* - * The PLLOPT register controls the PLL like this: - * icp = PLLOPT<2> - * ivco = PLLOPT<1:0> - * - * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). - */ -#define CONFIG_SYS_PLL0_OPT 0x04 - -#define CONFIG_USART_BASE ATMEL_BASE_USART1 -#define CONFIG_USART_ID 1 - -#define CONFIG_MIMC200_DBGLINK 1 - -/* User serviceable stuff */ -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_STACKSIZE (2048) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTARGS \ - "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1" -#define CONFIG_BOOTCOMMAND \ - "fsload boot/uImage; bootm" - -#define CONFIG_SILENT_CONSOLE /* enable silent startup */ -#define CONFIG_DISABLE_CONSOLE /* disable console */ -#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */ - -#define CONFIG_LCD 1 - -/* - * Only interrupt autoboot if <space> is pressed. Otherwise, garbage - * data on the serial line may interrupt the boot sequence. - */ -#define CONFIG_BOOTDELAY 0 -#define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_AUTOBOOT - -/* - * After booting the board for the first time, new ethernet addresses - * should be generated and assigned to the environment variables - * "ethaddr" and "eth1addr". This is normally done during production. - */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/* - * BOOTP/DHCP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MMC - -#define CONFIG_ATMEL_USART -#define CONFIG_MACB -#define CONFIG_PORTMUX_PIO -#define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC -#define CONFIG_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_GENERIC_MMC - -#if defined(CONFIG_LCD) -#define CONFIG_CMD_BMP -#define CONFIG_ATMEL_LCD 1 -#define LCD_BPP LCD_COLOR16 -#define CONFIG_BMP_16BPP 1 -#define CONFIG_FB_ADDR 0x10600000 -#define CONFIG_WHITE_ON_BLACK 1 -#define CONFIG_VIDEO_BMP_GZIP 1 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144 -#define CONFIG_ATMEL_LCD_BGR555 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SPLASH_SCREEN 1 -#endif - -#define CONFIG_SYS_DCACHE_LINESZ 32 -#define CONFIG_SYS_ICACHE_LINESZ 32 - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x800000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_TEXT_BASE 0x00000000 - -#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE -#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE -#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE - -#define CONFIG_SYS_FRAM_BASE 0x08000000 -#define CONFIG_SYS_FRAM_SIZE 0x20000 - -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 65536 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (1024*1024) - -/* Allow 4MB for the kernel run-time image */ -#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) - -/* Other configuration settings that shouldn't have to change all that often */ -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP - -#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) - -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } - -#endif /* __CONFIG_H */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 96a6b89232..cdd5c79dce 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -72,13 +72,7 @@ * Autobooting */ #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" -#define DEBUG_BOOTKEYS 0 -#undef CONFIG_AUTOBOOT_DELAY_STR #undef CONFIG_BOOTARGS -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press \"<Esc><Esc>\" to stop\n", bootdelay #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 233c6d2e88..50370e1366 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -53,11 +53,19 @@ #define CONFIG_REVISION_TAG /* Boot options */ +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL)) +#define CONFIG_LOADADDR 0x82000000 +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x87800000 +#endif +#else #define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x17800000 #endif +#endif +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #ifndef CONFIG_BOOTDELAY #define CONFIG_BOOTDELAY 3 #endif diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index d1bb1a182a..ed98425899 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -396,7 +396,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "echo" #define CONFIG_BOOTDELAY 30 -#define CONFIG_AUTOBOOT_KEYED #define CONFIG_MENU #define CONFIG_MENU_SHOW diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index a92112f870..b99d762761 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -47,6 +47,7 @@ #define CONFIG_AS3722_POWER #define LCD_BPP LCD_COLOR16 #define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CMD_BMP /* Align LCD to 1MB boundary */ #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE @@ -77,8 +78,14 @@ #define CONFIG_CMD_DHCP #define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH #define CONFIG_OF_LIBFDT +#define CONFIG_KEYBOARD + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x82408000 + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 18388d150b..3248429631 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -98,18 +98,6 @@ #error "CONFIG_SYS_TEXT_BASE value is invalid" #endif -/* - * Autobooting - * Be selective on what keys can delay or stop the autoboot process - * To stop use: "++++++++++" - */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press password to stop\n", bootdelay -#define CONFIG_AUTOBOOT_STOP_STR "++++++++++" -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 - #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "run master" diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 10d1f77c9d..e88cdaaca9 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -144,8 +144,6 @@ #undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */ #define CONFIG_BOOTDELAY 0 #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "S" #define CONFIG_EXTRA_ENV_SETTINGS \ "silent=true\0" \ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 4215156063..cb12c6c2ac 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -12,10 +12,12 @@ #ifndef __CONFIG_OMAP5_EVM_H #define __CONFIG_OMAP5_EVM_H +#ifndef CONFIG_SPL_BUILD /* Define the default GPT table for eMMC */ #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" +#endif #include <configs/ti_omap5_common.h> diff --git a/include/configs/pepper.h b/include/configs/pepper.h index cc153abaa9..16149f69d5 100644 --- a/include/configs/pepper.h +++ b/include/configs/pepper.h @@ -20,6 +20,8 @@ #undef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "pepper# " +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + /* Mach type */ #define MACH_TYPE_PEPPER 4207 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_PEPPER diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index f6aebf4e4a..9bdbf53fd1 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -339,7 +339,6 @@ #define CONFIG_BOOTCOMMAND "run flashboot" #define CONFIG_ROOTPATH "/ronetix/rootfs" -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay #define CONFIG_CON_ROT "fbcon=rotate:3 " #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 3a857e2a3d..3caa83ce09 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -113,7 +113,6 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#define CONFIG_SANDBOX_SERIAL #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index f086e730cd..b005c86c32 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -476,12 +476,6 @@ /* Watchdog */ #define CONFIG_HW_WATCHDOG -/* Stop autoboot with ESC ESC key detected */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press \"<Esc><Esc>\" to stop\n", bootdelay - /* Reboot after 60 sec if bootcmd fails */ #define CONFIG_RESET_TO_RETRY #define CONFIG_BOOT_RETRY_TIME 60 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 30a3f509ae..b386c7ca70 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -200,10 +200,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_MISC_INIT_R #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_AUTOBOOT_PROMPT \ - "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay #define CONFIG_SYS_MEMTEST_START 0x00800000 #define CONFIG_SYS_MEMTEST_END 0x04000000 diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 888d29cd0f..d8f51d8997 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,10 +74,7 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "go 0x40040000" -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_AUTOBOOT_PROMPT \ - "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + #define CONFIG_OF_SEPARATE #define CONFIG_OF_CONTROL #define CONFIG_OF_LIBFDT diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 07db736d31..063abd56a9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -126,6 +126,7 @@ #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SUNXI_AHCI +#define CONFIG_SYS_64BIT_LBA #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 0cea795de1..483222fbcf 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -40,8 +40,14 @@ #define STDOUT_LCD "" #endif +#ifdef CONFIG_CROS_EC_KEYB +#define STDOUT_CROS_EC ",cros-ec-keyb" +#else +#define STDOUT_CROS_EC "" +#endif + #define TEGRA_DEVICE_SETTINGS \ - "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \ + "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \ "stdout=serial" STDOUT_LCD "\0" \ "stderr=serial" STDOUT_LCD "\0" \ "" @@ -52,13 +58,18 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS +#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdt_high=ffffffff\0" \ "initrd_high=ffffffff\0" \ BOOTENV \ - BOARD_EXTRA_ENV_SETTINGS + BOARD_EXTRA_ENV_SETTINGS \ + CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) #define CONFIG_TEGRA_SPI diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 0bac9ad5c4..2d5842229f 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -104,7 +104,7 @@ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 4faffef047..3da7816527 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -71,6 +71,7 @@ #define DFUARGS #endif +#ifndef CONFIG_SPL_BUILD #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -146,6 +147,7 @@ "setenv mmcroot /dev/mmcblk0p2 rw; " \ "run mmcboot;" \ "" +#endif /* diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 4859e03890..00294f6d52 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -22,6 +22,13 @@ /* #endif */ +/* place code in last 4 MiB of RAM */ +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#define CONFIG_SYS_TEXT_BASE 0x2fc00000 +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#define CONFIG_SYS_TEXT_BASE 0x4fc00000 +#endif + #include "mx6_common.h" #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) @@ -116,13 +123,6 @@ #define CONFIG_CMD_BMODE #define CONFIG_CMD_ITEST -/* place code in last 4 MiB of RAM */ -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -#define CONFIG_SYS_TEXT_BASE 0x2fc00000 -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) -#define CONFIG_SYS_TEXT_BASE 0x4fc00000 -#endif - #define CONFIG_ENV_SIZE (SZ_8K) /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) @@ -367,10 +367,6 @@ "panicboot=echo No boot device !!! reset\0" \ TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_STACKSIZE (128u * SZ_1K) /* Physical Memory Map */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 88c00679b6..2f52598f2e 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com> + * Copyright (C) 2013 - 2015 Markus Niebel <Markus.Niebel@tq-group.com> * * Configuration settings for the TQ Systems TQMa6<Q,S> module. * @@ -11,7 +11,7 @@ #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) #define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" #endif diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 8510472d95..5c7a342d73 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -198,11 +198,6 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "d" -#define CONFIG_AUTOBOOT_STOP_STR " " /* * Network Configuration diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 0144e16131..f05b55a0e2 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -192,10 +192,14 @@ "bootz; " \ "fi;\0" \ "findfdt="\ - "if test $board_rev = MX6Q ; then " \ + "if test $board_name = C1 && test $board_rev = MX6Q ; then " \ "setenv fdtfile imx6q-wandboard.dtb; fi; " \ - "if test $board_rev = MX6DL ; then " \ + "if test $board_name = C1 && test $board_rev = MX6DL ; then " \ "setenv fdtfile imx6dl-wandboard.dtb; fi; " \ + "if test $board_name = B1 && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-wandboard-revb1.dtb; fi; " \ + "if test $board_name = B1 && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; \0" \ diff --git a/include/configs/warp.h b/include/configs/warp.h index e38b425215..39b49198bf 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -25,9 +25,10 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE +#define CONFIG_SUPPORT_EMMC_BOOT /* Command definition */ #undef CONFIG_CMD_NFS @@ -93,9 +94,13 @@ #define CONFIG_CMD_DFU #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M #define DFU_DEFAULT_POLL_TIMEOUT 300 +/* Fuses */ +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/x600.h b/include/configs/x600.h index d235da4ad6..a07482cb27 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -151,10 +151,6 @@ #define CONFIG_LOOPW /* enable loopw command */ #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_AUTOBOOT_PROMPT \ - "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay #define CONFIG_SYS_MEMTEST_START 0x00800000 #define CONFIG_SYS_MEMTEST_END 0x04000000 diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index d57e665822..004af386ce 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -150,10 +150,6 @@ #define CONFIG_PREBOOT "" #define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" -#define CONFIG_AUTOBOOT_STOP_STR "stopgs" /* * Size of malloc() pool diff --git a/include/fdtdec.h b/include/fdtdec.h index 4fb8a2a1ba..232360341a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -41,6 +41,12 @@ struct fdt_memory { fdt_addr_t end; }; +#ifdef CONFIG_SPL_BUILD +#define SPL_BUILD 1 +#else +#define SPL_BUILD 0 +#endif + #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && defined(SPL_DISABLE_OF_CONTROL) # define OF_CONTROL 0 @@ -122,9 +128,6 @@ static inline fdt_size_t fdt_resource_size(const struct fdt_resource *res) */ enum fdt_compat_id { COMPAT_UNKNOWN, - COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */ - COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */ - COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */ COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */ diff --git a/include/hash.h b/include/hash.h index f4eb100de0..e6d0f1db92 100644 --- a/include/hash.h +++ b/include/hash.h @@ -158,4 +158,18 @@ int hash_lookup_algo(const char *algo_name, struct hash_algo **algop); int hash_progressive_lookup_algo(const char *algo_name, struct hash_algo **algop); +/** + * hash_parse_string() - Parse hash string into a binary array + * + * The function parses a hash string into a binary array that + * can for example easily be used to compare to hash values. + * + * @algo_name: Hash algorithm to look up + * @str: Hash string to get parsed + * @result: Binary array of the parsed hash string + * + * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm. + */ +int hash_parse_string(const char *algo_name, const char *str, uint8_t *result); + #endif diff --git a/include/i2c.h b/include/i2c.h index ddfebc4107..9300d97e14 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -284,6 +284,12 @@ void i2c_init(int speed, int slaveaddr); */ void board_i2c_init(const void *blob); +/* + * Compatibility functions for driver model. + */ +uint8_t i2c_reg_read(uint8_t addr, uint8_t reg); +void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val); + #endif /* diff --git a/include/ns16550.h b/include/ns16550.h index 0607379537..4e620676c4 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -33,7 +33,7 @@ #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) #error "Please define NS16550 registers size." -#elif defined(CONFIG_SYS_NS16550_MEM32) +#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) #define UART_REG(x) u32 x #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) #define UART_REG(x) \ diff --git a/include/scsi.h b/include/scsi.h index 73de7b7460..7e3759140b 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -132,6 +132,7 @@ typedef struct SCSI_cmd_block{ #define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */ #define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */ #define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */ +#define SCSI_READ16 0x48 #define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */ #define SCSI_RD_CAPAC10 SCSI_RD_CAPAC /* Read Capacity (10) */ #define SCSI_RD_CAPAC16 0x9e /* Read Capacity (16) */ diff --git a/include/spl.h b/include/spl.h index b2e5bf726f..d19940f2a3 100644 --- a/include/spl.h +++ b/include/spl.h @@ -11,6 +11,8 @@ #include <linux/compiler.h> #include <asm/spl.h> +/* Value in r0 indicates we booted from U-Boot */ +#define UBOOT_NOT_LOADED_FROM_SPL 0x13578642 /* Boot type */ #define MMCSD_MODE_UNDEFINED 0 @@ -82,4 +84,15 @@ int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition); #ifdef CONFIG_SPL_BOARD_INIT void spl_board_init(void); #endif + +/** + * spl_was_boot_source() - check if U-Boot booted from SPL + * + * This will normally be true, but if U-Boot jumps to second U-Boot, it will + * be false. This should be implemented by board-specific code. + * + * @return true if U-Boot booted from SPL, else false + */ +bool spl_was_boot_source(void); + #endif diff --git a/lib/Kconfig b/lib/Kconfig index 3c8de869b1..7ec8c98da2 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -45,7 +45,9 @@ config REGEX "setexpr". config LIB_RAND - bool + bool "Pseudo-random library support " + help + This library provides pseudo-random number generator functions. source lib/rsa/Kconfig diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 46dfcb675c..9877849f99 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -22,9 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; #define COMPAT(id, name) name static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, "<none>"), - COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), - COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"), - COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"), COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"), COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"), COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"), diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl index 343c3fc199..4f056525bb 100644 --- a/scripts/Makefile.uncmd_spl +++ b/scripts/Makefile.uncmd_spl @@ -3,7 +3,9 @@ # TODO: Invent a better way ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_DISABLE_OF_CONTROL CONFIG_OF_CONTROL= +endif ifndef CONFIG_SPL_DM CONFIG_DM_SERIAL= diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c index f88d90f202..2f778df206 100644 --- a/scripts/kconfig/confdata.c +++ b/scripts/kconfig/confdata.c @@ -155,18 +155,14 @@ static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p) case S_STRING: if (*p++ != '"') break; - for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) { - if (*p2 == '"') { - *p2 = 0; - break; - } - memmove(p2, p2 + 1, strlen(p2)); - } - if (!p2) { + /* Last char has to be a '"' */ + if (p[strlen(p) - 1] != '"') { if (def != S_DEF_AUTO) conf_warning("invalid string found"); return 1; } + /* Overwrite '"' with \0 for string termination */ + p[strlen(p) - 1] = 0; /* fall through */ case S_INT: case S_HEX: @@ -624,6 +620,7 @@ static void conf_write_symbol(FILE *fp, struct symbol *sym, struct conf_printer *printer, void *printer_arg) { const char *str; + char *str2; switch (sym->type) { case S_OTHER: @@ -631,9 +628,10 @@ static void conf_write_symbol(FILE *fp, struct symbol *sym, break; case S_STRING: str = sym_get_string_value(sym); - str = sym_escape_string_value(str); - printer->print_symbol(fp, sym, str, printer_arg); - free((void *)str); + str2 = xmalloc(strlen(str) + 3); + sprintf(str2, "\"%s\"", str); + printer->print_symbol(fp, sym, str2, printer_arg); + free((void *)str2); break; default: str = sym_get_string_value(sym); diff --git a/scripts/kconfig/symbol.c b/scripts/kconfig/symbol.c index 7caabdb51c..ab339ebbe3 100644 --- a/scripts/kconfig/symbol.c +++ b/scripts/kconfig/symbol.c @@ -912,49 +912,6 @@ const char *sym_expand_string_value(const char *in) return res; } -const char *sym_escape_string_value(const char *in) -{ - const char *p; - size_t reslen; - char *res; - size_t l; - - reslen = strlen(in) + strlen("\"\"") + 1; - - p = in; - for (;;) { - l = strcspn(p, "\"\\"); - p += l; - - if (p[0] == '\0') - break; - - reslen++; - p++; - } - - res = xmalloc(reslen); - res[0] = '\0'; - - strcat(res, "\""); - - p = in; - for (;;) { - l = strcspn(p, "\"\\"); - strncat(res, p, l); - p += l; - - if (p[0] == '\0') - break; - - strcat(res, "\\"); - strncat(res, p++, 1); - } - - strcat(res, "\""); - return res; -} - struct sym_match { struct symbol *sym; off_t so, eo; diff --git a/tools/buildman/kconfiglib.py b/tools/buildman/kconfiglib.py index 655cf4470f..c662b64dad 100644 --- a/tools/buildman/kconfiglib.py +++ b/tools/buildman/kconfiglib.py @@ -429,7 +429,15 @@ class Config(): If the environment variable 'srctree' was set when the Config was created, get_defconfig_filename() will first look relative to that directory before looking in the current directory; see - Config.__init__().""" + Config.__init__(). + + WARNING: A wart here is that scripts/kconfig/Makefile sometimes uses the + --defconfig=<defconfig> option when calling the C implementation of e.g. + 'make defconfig'. This option overrides the 'option defconfig_list' + symbol, meaning the result from get_defconfig_filename() might not + match what 'make defconfig' would use. That probably ought to be worked + around somehow, so that this function always gives the "expected" + result.""" if self.defconfig_sym is None: return None @@ -506,7 +514,7 @@ class Config(): For example, if FOO and BAR are tristate symbols at least one of which has the value "y", then config.eval("y && (FOO || BAR)") => "y" - This functions always yields a tristate value. To get the value of + This function always yields a tristate value. To get the value of non-bool, non-tristate symbols, use Symbol.get_value(). The result of this function is consistent with how evaluation works for @@ -1066,7 +1074,7 @@ class Config(): choice.block = self._parse_block(line_feeder, T_ENDCHOICE, choice, - None, + deps, visible_if_deps) choice._determine_actual_symbols() @@ -1326,10 +1334,21 @@ error, and you should e-mail kconfiglib@gmail.com. elif tokens.check(T_MODULES): self._warn("the 'modules' option is not supported. " "Let me know if this is a problem for you; " - "it shouldn't be that hard to implement.", + "it shouldn't be that hard to implement. " + "(Note that modules are still supported -- " + "Kconfiglib just assumes the symbol name " + "MODULES.)", filename, linenr) + elif tokens.check(T_ALLNOCONFIG_Y): + if not isinstance(stmt, Symbol): + _parse_error(line, + "the 'allnoconfig_y' option is only valid for symbols.", + filename, + linenr) + stmt.allnoconfig_y = True + else: _parse_error(line, "unrecognized option.", filename, linenr) @@ -2023,8 +2042,8 @@ def _make_and(e1, e2): T_OPTIONAL, T_PROMPT, T_DEFAULT, T_BOOL, T_TRISTATE, T_HEX, T_INT, T_STRING, T_DEF_BOOL, T_DEF_TRISTATE, - T_SELECT, T_RANGE, T_OPTION, T_ENV, - T_DEFCONFIG_LIST, T_MODULES, T_VISIBLE) = range(0, 38) + T_SELECT, T_RANGE, T_OPTION, T_ALLNOCONFIG_Y, T_ENV, + T_DEFCONFIG_LIST, T_MODULES, T_VISIBLE) = range(0, 39) # Keyword to token map keywords = { @@ -2056,6 +2075,7 @@ keywords = { "select" : T_SELECT, "range" : T_RANGE, "option" : T_OPTION, + "allnoconfig_y" : T_ALLNOCONFIG_Y, "env" : T_ENV, "defconfig_list" : T_DEFCONFIG_LIST, "modules" : T_MODULES, @@ -2080,7 +2100,7 @@ set_re = re.compile(r"CONFIG_(\w+)=(.*)") unset_re = re.compile(r"# CONFIG_(\w+) is not set") # Regular expression for finding $-references to symbols in strings -sym_ref_re = re.compile(r"\$[A-Za-z_]+") +sym_ref_re = re.compile(r"\$[A-Za-z0-9_]+") # Integers representing symbol types UNKNOWN, BOOL, TRISTATE, STRING, HEX, INT = range(0, 6) @@ -2765,6 +2785,11 @@ class Symbol(Item, _HasVisibility): and sym.get_parent().get_selection() is sym'.""" return self.is_choice_symbol_ and self.parent.get_selection() is self + def is_allnoconfig_y(self): + """Returns True if the symbol has the 'allnoconfig_y' option set; + otherwise, returns False.""" + return self.allnoconfig_y + def __str__(self): """Returns a string containing various information about the symbol.""" return self.config._get_sym_or_choice_str(self) @@ -2862,6 +2887,9 @@ class Symbol(Item, _HasVisibility): # Does the symbol get its value from the environment? self.is_from_env = False + # Does the symbol have the 'allnoconfig_y' option set? + self.allnoconfig_y = False + def _invalidate(self): if self.is_special_: return diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 9540e7eb84..1ff17cab26 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -420,6 +420,18 @@ static size_t image_headersz_v1(struct image_tool_params *params, *hasext = 1; } +#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) + if (headersz > CONFIG_SYS_SPI_U_BOOT_OFFS) { + fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n"); + fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n", + (int)headersz, CONFIG_SYS_SPI_U_BOOT_OFFS); + fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n"); + return 0; + } else { + headersz = CONFIG_SYS_SPI_U_BOOT_OFFS; + } +#endif + /* * The payload should be aligned on some reasonable * boundary @@ -869,16 +881,6 @@ static int kwbimage_generate(struct image_tool_params *params, sizeof(struct ext_hdr_v0); } else { alloc_len = image_headersz_v1(params, NULL); -#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) - if (alloc_len > CONFIG_SYS_SPI_U_BOOT_OFFS) { - fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n"); - fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n", - alloc_len, CONFIG_SYS_SPI_U_BOOT_OFFS); - fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n"); - } else { - alloc_len = CONFIG_SYS_SPI_U_BOOT_OFFS; - } -#endif } hdr = malloc(alloc_len); diff --git a/tools/kwboot.c b/tools/kwboot.c index 1368b4c948..af7a6ee3f6 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -657,7 +657,7 @@ static void kwboot_usage(FILE *stream, char *progname) { fprintf(stream, - "Usage: %s [-d | -a | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", + "Usage: %s [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", progname); fprintf(stream, "\n"); fprintf(stream, @@ -667,6 +667,8 @@ kwboot_usage(FILE *stream, char *progname) " -D <image>: boot <image> without preamble (Dove)\n"); fprintf(stream, " -d: enter debug mode\n"); fprintf(stream, " -a: use timings for Armada XP\n"); + fprintf(stream, " -q <req-delay>: use specific request-delay\n"); + fprintf(stream, " -s <resp-timeo>: use specific response-timeout\n"); fprintf(stream, "\n"); fprintf(stream, " -t: mini terminal\n"); fprintf(stream, "\n"); @@ -699,7 +701,7 @@ main(int argc, char **argv) kwboot_verbose = isatty(STDOUT_FILENO); do { - int c = getopt(argc, argv, "hb:ptaB:dD:"); + int c = getopt(argc, argv, "hb:ptaB:dD:q:s:"); if (c < 0) break; @@ -731,6 +733,14 @@ main(int argc, char **argv) msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO_AXP; break; + case 'q': + msg_req_delay = atoi(optarg); + break; + + case 's': + msg_rsp_timeo = atoi(optarg); + break; + case 'B': speed = kwboot_tty_speed(atoi(optarg)); if (speed == -1) |