diff options
81 files changed, 1287 insertions, 1696 deletions
diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S index eaea9d2535..8b58ba9fa5 100644 --- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/at91/lowlevel_init.S @@ -65,7 +65,8 @@ LoopOsc: ldr r0, =SMRDATA ldr r1, _MTEXT_BASE sub r0, r0, r1 - add r2, r0, #80 + ldr r2, =SMRDATAE + sub r2, r2, r1 pllloop: /* the address */ ldr r1, [r0], #4 @@ -83,7 +84,8 @@ lock: ldr r0, =SMRDATA1 ldr r1, _MTEXT_BASE sub r0, r0, r1 - add r2, r0, #176 + ldr r2, =SMRDATA1E + sub r2, r2, r1 sdinit: /* the address */ ldr r1, [r0], #4 @@ -114,6 +116,7 @@ SMRDATA: .word CONFIG_SYS_PLLBR_VAL .word AT91_ASM_PMC_MCKR .word CONFIG_SYS_MCKR_VAL +SMRDATAE: /* here there's a delay */ SMRDATA1: .word AT91_ASM_PIOC_ASR @@ -160,5 +163,6 @@ SMRDATA1: .word CONFIG_SYS_SDRC_MR_VAL3 .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL +SMRDATA1E: /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index be9f6dddf0..f333753c71 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_AT91CAP9) += at91cap9_devices.o COBJS-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o +COBJS-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c index c1822b713d..6bdc75c702 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -23,10 +23,10 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> /* * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all @@ -45,70 +45,51 @@ void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */ - writel(1 << AT91SAM9260_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */ - writel(1 << AT91SAM9260_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */ - writel(1 << AT91SAM9260_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9260_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -138,14 +119,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9260_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 1); diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c index deda3e54d9..15e880accd 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -3,7 +3,7 @@ * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009 + * (C) Copyright 2009-2011 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -27,78 +27,59 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pio.h> void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ - writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* RXD1 */ - writel(1 << AT91SAM9263_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* RXD2 */ - writel(1 << AT91SAM9263_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif -} - -#ifdef CONFIG_HAS_DATAFLASH +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_b_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_b_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_b_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PIO_PORTA, 5, 1); @@ -128,14 +109,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 15, 1); @@ -203,12 +184,12 @@ void at91_uhp_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer); + writel(1 << ATMEL_ID_CAN, &pmc->pcer); } #endif diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index 7a10a77877..608af2cf72 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -12,8 +12,8 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> @@ -57,7 +57,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return AT91_SLOW_CLOCK; + return CONFIG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -145,7 +145,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; #ifndef CONFIG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* @@ -159,7 +159,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->main_clk_rate_hz = main_clock; diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c index 5e30f1dccc..c47fb31e99 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/cpu/arm926ejs/at91/cpu.c @@ -24,13 +24,12 @@ */ #include <common.h> - +#include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_gpbr.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> #ifndef CONFIG_SYS_AT91_MAIN_CLOCK #define CONFIG_SYS_AT91_MAIN_CLOCK 0 @@ -44,7 +43,7 @@ int arch_cpu_init(void) void arch_preboot_os(void) { ulong cpiv; - at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); @@ -61,7 +60,7 @@ int print_cpuinfo(void) { char buf[32]; - printf("CPU: %s\n", CONFIG_SYS_AT91_CPU_NAME); + printf("CPU: %s\n", ATMEL_CPU_NAME); printf("Crystal frequency: %8s MHz\n", strmhz(buf, get_main_clk_rate())); printf("CPU clock : %8s MHz\n", @@ -80,7 +79,7 @@ int print_cpuinfo(void) */ void bootcount_store (ulong a) { - at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff), &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); @@ -88,7 +87,7 @@ void bootcount_store (ulong a) ulong bootcount_load (void) { - at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c index 938c3b1f05..b0c1e1e814 100644 --- a/arch/arm/cpu/arm926ejs/at91/eflash.c +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -60,8 +60,8 @@ * do a read-modify-write for partially programmed pages */ #include <common.h> +#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_eefc.h> #include <asm/arch/at91_dbu.h> @@ -77,8 +77,8 @@ static u32 pagesize; unsigned long flash_init (void) { - at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; - at91_dbu_t *dbu = (at91_dbu_t *) 0xfffff200; + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; + at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU; u32 id, size, nplanes, planesize, nlocks; u32 addr, i, tmp=0; @@ -119,7 +119,7 @@ unsigned long flash_init (void) flash_info[0].sector_count = nlocks; flash_info[0].flash_id = id; - addr = AT91SAM9XE_FLASH_BASE; + addr = ATMEL_BASE_FLASH; for (i=0; i<nlocks; i++) { tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */ flash_info[0].start[i] = addr; @@ -167,8 +167,8 @@ void flash_print_info (flash_info_t *info) int flash_real_protect (flash_info_t *info, long sector, int prot) { - at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; - u32 pagenum = (info->start[sector]-AT91SAM9XE_FLASH_BASE)/pagesize; + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; + u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize; u32 i, tmp=0; debug("protect sector=%ld prot=%d\n", sector, prot); @@ -205,7 +205,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot) static u32 erase_write_page (u32 pagenum) { - at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; debug("erase+write page=%u\n", pagenum); @@ -249,7 +249,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) } /* now start copying data */ - pagenum = (addr-AT91SAM9XE_FLASH_BASE)/pagesize; + pagenum = (addr-ATMEL_BASE_FLASH)/pagesize; src32 = (u32 *) src; dst32 = (u32 *) addr; while (cnt > 0) { diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c index 0a315c4971..6bcfa7f2fd 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/cpu/arm926ejs/at91/led.c @@ -23,10 +23,10 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pio.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> #ifdef CONFIG_RED_LED void red_LED_on(void) diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c index d2569d8bae..023719a683 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/cpu/arm926ejs/at91/reset.c @@ -23,14 +23,14 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_rstc.h> -#include <asm/arch/io.h> /* Reset the cpu by telling the reset controller to do so */ void reset_cpu(ulong ignored) { - at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST /* Processor Reset */ diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c index 82b8d7e7d7..a0876879d3 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/cpu/arm926ejs/at91/timer.c @@ -23,11 +23,11 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> #include <div64.h> #if !defined(CONFIG_AT91FAMILY) @@ -70,11 +70,11 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) */ int timer_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; /* Enable PITC Clock */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); @@ -90,7 +90,7 @@ int timer_init(void) */ unsigned long long get_ticks(void) { - at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; ulong now = readl(&pit->piir); @@ -103,33 +103,28 @@ unsigned long long get_ticks(void) void __udelay(unsigned long usec) { - unsigned long long tmp; + unsigned long long start; ulong tmo; - tmo = usec_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - ; + start = get_ticks(); /* get current timestamp */ + tmo = usec_to_tick(usec); /* convert usecs to ticks */ + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ } /* - * reset_timer() and get_timer(base) are a pair of functions that are used by - * some timeout/sleep mechanisms in u-boot. + * get_timer(base) can be used to check for timeouts or + * to measure elasped time relative to an event: * - * reset_timer() marks the current time as epoch and - * get_timer(base) works relative to that epoch. + * ulong start_time = get_timer(0) sets start_time to the current + * time value. + * get_timer(start_time) returns the time elapsed since then. * * The time is used in CONFIG_SYS_HZ units! */ -void reset_timer(void) -{ - gd->timer_reset_value = get_ticks(); -} - ulong get_timer(ulong base) { - return tick_to_time(get_ticks() - gd->timer_reset_value) - base; + return tick_to_time(get_ticks()) - base; } /* diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index 0067190a20..330edd83c5 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -28,11 +28,10 @@ void at91_can_hw_init(void); void at91_macb_hw_init(void); void at91_mci_hw_init(void); -void at91_serial_hw_init(void); void at91_serial0_hw_init(void); void at91_serial1_hw_init(void); void at91_serial2_hw_init(void); -void at91_serial3_hw_init(void); +void at91_seriald_hw_init(void); void at91_spi0_hw_init(unsigned long cs_mask); void at91_spi1_hw_init(unsigned long cs_mask); void at91_uhp_hw_init(void); diff --git a/arch/arm/include/asm/arch-at91/at91_mc.h b/arch/arm/include/asm/arch-at91/at91_mc.h index acfbd10c5c..09453a9450 100644 --- a/arch/arm/include/asm/arch-at91/at91_mc.h +++ b/arch/arm/include/asm/arch-at91/at91_mc.h @@ -36,7 +36,7 @@ typedef struct at91_ebi { u32 csa; /* 0x00 Chip Select Assignment Register */ u32 cfgr; /* 0x04 Configuration Register */ u32 reserved[2]; -} __attribute__ ((packed)) at91_ebi_t; +} at91_ebi_t; #define AT91_EBI_CSA_CS0A 0x0001 #define AT91_EBI_CSA_CS1A 0x0002 @@ -55,11 +55,11 @@ typedef struct at91_sdramc { u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ u32 reserved[3]; -} __attribute__ ((packed)) at91_sdramc_t; +} at91_sdramc_t; typedef struct at91_smc { u32 csr[8]; /* 0x00 SDRAMC Mode Register */ -} __attribute__ ((packed)) at91_smc_t; +} at91_smc_t; #define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) #define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) @@ -78,7 +78,7 @@ typedef struct at91_smc { typedef struct at91_bfc { u32 mr; /* 0x00 SDRAMC Mode Register */ -} __attribute__ ((packed)) at91_bfc_t; +} at91_bfc_t; typedef struct at91_mc { u32 rcr; /* 0x00 MC Remap Control Register */ @@ -91,7 +91,7 @@ typedef struct at91_mc { at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ at91_bfc_t bfc; /* 0xC0 BFC User Interface */ u32 reserved2[15]; -} __attribute__ ((packed)) at91_mc_t; +} at91_mc_t; #endif #endif diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index f7915a3322..0b5bd69db8 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -76,32 +76,19 @@ typedef struct at91_port { u32 reserved6[85]; } at91_port_t; -#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ - defined(CONFIG_AT91SAM9G10) || defined(CONFIG_AT91SAM9G20) -#define AT91_PIO_PORTS 3 -#elif defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ - defined(CONFIG_AT91SAM9M10G45) -#define AT91_PIO_PORTS 5 -#elif defined(CONFIG_AT91RM9200) || defined(CONFIG_AT91CAP9) || \ - defined(CONFIG_AT91SAM9RL) -#define AT91_PIO_PORTS 4 -#else -#error "Unsupported cpu. Please update at91_pio.h" -#endif - typedef union at91_pio { struct { at91_port_t pioa; at91_port_t piob; at91_port_t pioc; - #if (AT91_PIO_PORTS > 3) + #if (ATMEL_PIO_PORTS > 3) at91_port_t piod; #endif - #if (AT91_PIO_PORTS > 4) + #if (ATMEL_PIO_PORTS > 4) at91_port_t pioe; #endif } ; - at91_port_t port[AT91_PIO_PORTS]; + at91_port_t port[ATMEL_PIO_PORTS]; } at91_pio_t; #ifdef CONFIG_AT91_GPIO diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h index 9ff2c5b7ac..510eed5840 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/include/asm/arch-at91/at91_rstc.h @@ -41,29 +41,4 @@ typedef struct at91_rstc { #define AT91_RSTC_SR_NRSTL 0x00010000 -#ifdef CONFIG_AT91_LEGACY - -#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ -#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ -#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ -#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ - -#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ -#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ -#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ -#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) -#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) -#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) -#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) -#define AT91_RSTC_RSTTYP_USER (4 << 8) -#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ -#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ - -#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ -#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ -#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ -#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ - -#endif /* CONFIG_AT91_LEGACY */ - #endif diff --git a/arch/arm/include/asm/arch-at91/at91_st.h b/arch/arm/include/asm/arch-at91/at91_st.h index 53f932085b..98b0a7640b 100644 --- a/arch/arm/include/asm/arch-at91/at91_st.h +++ b/arch/arm/include/asm/arch-at91/at91_st.h @@ -35,7 +35,7 @@ typedef struct at91_st { u32 imr; u32 rtar; u32 crtr; -} __attribute__ ((packed)) at91_st_t ; +} at91_st_t ; #define AT91_ST_CR_WDRST 1 diff --git a/arch/arm/include/asm/arch-at91/at91_tc.h b/arch/arm/include/asm/arch-at91/at91_tc.h index 1e180adb3c..1eae4e95c7 100644 --- a/arch/arm/include/asm/arch-at91/at91_tc.h +++ b/arch/arm/include/asm/arch-at91/at91_tc.h @@ -36,7 +36,7 @@ typedef struct at91_tcc { u32 idr; /* 0x28 Interrupt Disable Register */ u32 imr; /* 0x2C Interrupt Mask Register */ u32 reserved3[4]; -} __attribute__ ((packed)) at91_tcc_t; +} at91_tcc_t; #define AT91_TC_CCR_CLKEN 0x00000001 #define AT91_TC_CCR_CLKDIS 0x00000002 @@ -57,7 +57,7 @@ typedef struct at91_tc { at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ u32 bcr; /* 0xC0 TC Block Control Register */ u32 bmr; /* 0xC4 TC Block Mode Register */ -} __attribute__ ((packed)) at91_tc_t; +} at91_tc_t; #define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 #define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/include/asm/arch-at91/at91sam9260.h index 7fd60b74ff..dd68485c62 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260.h @@ -2,9 +2,15 @@ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] * * (C) 2006 Andrew Victor + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * - * Common definitions. - * Based on AT91SAM9260 datasheet revision A (Preliminary). + * Definitions for the SoCs: + * AT91SAM9260, AT91SAM9G20, AT91SAM9XE + * + * Note that those SoCs are mostly software and pin compatible, + * therefore this file applies to all of them. Differences between + * those SoCs are concentrated at the end of this file. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,145 +22,151 @@ #define AT91SAM9260_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ -#define AT91SAM9260_ID_US0 6 /* USART 0 */ -#define AT91SAM9260_ID_US1 7 /* USART 1 */ -#define AT91SAM9260_ID_US2 8 /* USART 2 */ -#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ -#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9260_ID_UHP 20 /* USB Host port */ -#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ -#define AT91SAM9260_ID_US3 23 /* USART 3 */ -#define AT91SAM9260_ID_US4 24 /* USART 4 */ -#define AT91SAM9260_ID_US5 25 /* USART 5 */ -#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ -#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ -#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ -#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ -#define AT91_EMAC_BASE 0xfffc4000 -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_SHDWN_BASE 0xfffffd10 -#define AT91_RTT_BASE 0xfffffd20 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 /* - * The AT91SAM9XE has the GPBRs at a different address than - * the AT91SAM9260/9G20. + * Peripheral identifiers/interrupts. */ -#ifdef CONFIG_AT91SAM9XE -# define AT91_GPR_BASE 0xfffffd60 -#else -# define AT91_GPR_BASE 0xfffffd50 -#endif - -#ifdef CONFIG_AT91_LEGACY +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ +#define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_USART2 8 /* USART 2 */ +#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ +#define ATMEL_ID_UDP 10 /* USB Device Port */ +#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ +#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +/* Reserved: 15 */ +/* Reserved: 16 */ +#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ +#define ATMEL_ID_UHP 20 /* USB Host port */ +#define ATMEL_ID_EMAC0 21 /* Ethernet 0 */ +#define ATMEL_ID_ISI 22 /* Image Sensor Interface */ +#define ATMEL_ID_USART3 23 /* USART 3 */ +#define ATMEL_ID_USART4 24 /* USART 4 */ +/* USART5 or TWI1: 25 */ +#define ATMEL_ID_TC3 26 /* Timer Counter 3 */ +#define ATMEL_ID_TC4 27 /* Timer Counter 4 */ +#define ATMEL_ID_TC5 28 /* Timer Counter 5 */ +#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ /* - * User Peripheral physical base addresses. + * User Peripherals physical base addresses. */ -#define AT91SAM9260_BASE_TCB0 0xfffa0000 -#define AT91SAM9260_BASE_TC0 0xfffa0000 -#define AT91SAM9260_BASE_TC1 0xfffa0040 -#define AT91SAM9260_BASE_TC2 0xfffa0080 -#define AT91SAM9260_BASE_UDP 0xfffa4000 -#define AT91SAM9260_BASE_MCI 0xfffa8000 -#define AT91SAM9260_BASE_TWI 0xfffac000 -#define AT91SAM9260_BASE_US0 0xfffb0000 -#define AT91SAM9260_BASE_US1 0xfffb4000 -#define AT91SAM9260_BASE_US2 0xfffb8000 -#define AT91SAM9260_BASE_SSC 0xfffbc000 -#define AT91SAM9260_BASE_ISI 0xfffc0000 -#define AT91SAM9260_BASE_EMAC 0xfffc4000 -#define AT91SAM9260_BASE_SPI0 0xfffc8000 -#define AT91SAM9260_BASE_SPI1 0xfffcc000 -#define AT91SAM9260_BASE_US3 0xfffd0000 -#define AT91SAM9260_BASE_US4 0xfffd4000 -#define AT91SAM9260_BASE_US5 0xfffd8000 -#define AT91SAM9260_BASE_TCB1 0xfffdc000 -#define AT91SAM9260_BASE_TC3 0xfffdc000 -#define AT91SAM9260_BASE_TC4 0xfffdc040 -#define AT91SAM9260_BASE_TC5 0xfffdc080 -#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800 +#define ATMEL_BASE_TCB0 0xfffa0000 +#define ATMEL_BASE_TC0 0xfffa0000 +#define ATMEL_BASE_TC1 0xfffa0040 +#define ATMEL_BASE_TC2 0xfffa0080 +#define ATMEL_BASE_UDP0 0xfffa4000 +#define ATMEL_BASE_MCI 0xfffa8000 +#define ATMEL_BASE_TWI0 0xfffac000 +#define ATMEL_BASE_USART0 0xfffb0000 +#define ATMEL_BASE_USART1 0xfffb4000 +#define ATMEL_BASE_USART2 0xfffb8000 +#define ATMEL_BASE_SSC0 0xfffbc000 +#define ATMEL_BASE_ISI0 0xfffc0000 +#define ATMEL_BASE_EMAC0 0xfffc4000 +#define ATMEL_BASE_SPI0 0xfffc8000 +#define ATMEL_BASE_SPI1 0xfffcc000 +#define ATMEL_BASE_USART3 0xfffd0000 +#define ATMEL_BASE_USART4 0xfffd4000 +/* USART5 or TWI1: 0xfffd8000 */ +#define ATMEL_BASE_TCB1 0xfffdc000 +#define ATMEL_BASE_TC3 0xfffdc000 +#define ATMEL_BASE_TC4 0xfffdc040 +#define ATMEL_BASE_TC5 0xfffdc080 +#define ATMEL_BASE_ADC 0xfffe0000 +/* Reserved: 0xfffe4000 - 0xffffe7ff */ /* - * System Peripherals (offset from AT91_BASE_SYS) + * System Peripherals physical base addresses. */ -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9260_BASE_US0 -#define AT91_USART1 AT91SAM9260_BASE_US1 -#define AT91_USART2 AT91SAM9260_BASE_US2 -#define AT91_USART3 AT91SAM9260_BASE_US3 -#define AT91_USART4 AT91SAM9260_BASE_US4 -#define AT91_USART5 AT91SAM9260_BASE_US5 - -#endif /* CONFIG_AT91_LEGACY */ +#define ATMEL_BASE_SYS 0xffffe800 +#define ATMEL_BASE_SDRAMC 0xffffea00 +#define ATMEL_BASE_SMC 0xffffec00 +#define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +/* EEFC: 0xfffffa00 */ +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +/* GPBR(non-XE SoCs): 0xfffffd50 */ +/* GPBR(XE SoCs): 0xfffffd60 */ +/* Reserved: 0xfffffd70 - 0xffffffff */ /* - * Internal Memory. + * Internal Memory common on all these SoCs */ -#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ -#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ - -#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ -#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ -#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ -#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ +#define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */ +#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ +/* SRAM or FLASH: 0x00200000 */ +/* SRAM: 0x00300000 */ +/* Reserved: 0x00400000 */ +#define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 -#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ -#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* - * Cpu Name + * SoC specific defines */ #if defined(CONFIG_AT91SAM9XE) -# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9XE" +# define ATMEL_CPU_NAME "AT91SAM9XE" +# define ATMEL_ID_TWI1 25 /* TWI 1 */ +# define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */ +# define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */ +# define ATMEL_BASE_TWI1 0xfffd8000 +# define ATMEL_BASE_EEFC 0xfffffa00 +# define ATMEL_BASE_GPBR 0xfffffd60 #elif defined(CONFIG_AT91SAM9260) -# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9260" +# define ATMEL_CPU_NAME "AT91SAM9260" +# define ATMEL_ID_USART5 25 /* USART 5 */ +# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ +# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ +# define ATMEL_BASE_USART5 0xfffd8000 +# define ATMEL_BASE_GPBR 0xfffffd50 #elif defined(CONFIG_AT91SAM9G20) -# define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G20" +# define ATMEL_CPU_NAME "AT91SAM9G20" +# define ATMEL_ID_USART5 25 /* USART 5 */ +# define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ +# define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ +# define ATMEL_BASE_USART5 0xfffd8000 +# define ATMEL_BASE_GPBR 0xfffffd50 #endif #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h index f8b023d932..be28ad1c1d 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h @@ -15,66 +15,54 @@ #ifndef AT91SAM9260_MATRIX_H #define AT91SAM9260_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +/* + * This struct defines access to the matrix' maximum of + * 16 masters and 16 slaves. + * However, on the AT91SAM9260/9G20/9XE there exist only + * 6 Masters and 5 Slaves! + */ +struct at91_matrix { + u32 mcfg[16]; /* Master Configuration Registers */ + u32 scfg[16]; /* Slave Configuration Registers */ + u32 pras[16][2]; /* Priority Assignment Slave Registers */ + u32 mrcr; /* Master Remap Control Register */ + u32 filler[0x06]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; + +#endif /* __ASSEMBLY__ */ + +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index 7ca0283135..f8048d5612 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -2,9 +2,15 @@ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] * * Copyright (C) SAN People + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * - * Common definitions. - * Based on AT91SAM9261 datasheet revision E. (Preliminary) + * Definitions for the SoCs: + * AT91SAM9261, AT91SAM9G10 + * + * Note that those SoCs are mostly software and pin compatible, + * therefore this file applies to all of them. Differences between + * those SoCs are concentrated at the end of this file. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,106 +22,117 @@ #define AT91SAM9261_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9261_ID_US0 6 /* USART 0 */ -#define AT91SAM9261_ID_US1 7 /* USART 1 */ -#define AT91SAM9261_ID_US2 8 /* USART 2 */ -#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ -#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ -#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ -#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ -#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ -#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ -#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ -#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ -#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ -#define AT91SAM9261_ID_UHP 20 /* USB Host port */ -#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ -#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_RTT_BASE 0xfffffd20 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 -#define AT91_GPBR_BASE 0xfffffd50 +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ +/* Reserved: 5 */ +#define ATMEL_ID_USART0 6 /* USART 0 */ +#define ATMEL_ID_USART1 7 /* USART 1 */ +#define ATMEL_ID_USART2 8 /* USART 2 */ +#define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ +#define ATMEL_ID_UDP 10 /* USB Device Port */ +#define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ +#define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define ATMEL_ID_TC0 17 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 18 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 19 /* Timer Counter 2 */ +#define ATMEL_ID_UHP 20 /* USB Host port */ +#define ATMEL_ID_LCDC 21 /* LDC Controller */ +/* Reserved: 22-28 */ +#define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ -#ifdef CONFIG_AT91_LEGACY +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_TCB0 0xfffa0000 +#define ATMEL_BASE_TC0 0xfffa0000 +#define ATMEL_BASE_TC1 0xfffa0040 +#define ATMEL_BASE_TC2 0xfffa0080 +#define ATMEL_BASE_UDP0 0xfffa4000 +#define ATMEL_BASE_MCI 0xfffa8000 +#define ATMEL_BASE_TWI0 0xfffac000 +#define ATMEL_BASE_USART0 0xfffb0000 +#define ATMEL_BASE_USART1 0xfffb4000 +#define ATMEL_BASE_USART2 0xfffb8000 +#define ATMEL_BASE_SSC0 0xfffbc000 +#define ATMEL_BASE_SSC1 0xfffc0000 +#define ATMEL_BASE_SSC2 0xfffc4000 +#define ATMEL_BASE_SPI0 0xfffc8000 +#define ATMEL_BASE_SPI1 0xfffcc000 +/* Reserved: 0xfffc4000 - 0xffffe9ff */ /* - * User Peripheral physical base addresses. + * System Peripherals physical base addresses. */ -#define AT91SAM9261_BASE_TCB0 0xfffa0000 -#define AT91SAM9261_BASE_TC0 0xfffa0000 -#define AT91SAM9261_BASE_TC1 0xfffa0040 -#define AT91SAM9261_BASE_TC2 0xfffa0080 -#define AT91SAM9261_BASE_UDP 0xfffa4000 -#define AT91SAM9261_BASE_MCI 0xfffa8000 -#define AT91SAM9261_BASE_TWI 0xfffac000 -#define AT91SAM9261_BASE_US0 0xfffb0000 -#define AT91SAM9261_BASE_US1 0xfffb4000 -#define AT91SAM9261_BASE_US2 0xfffb8000 -#define AT91SAM9261_BASE_SSC0 0xfffbc000 -#define AT91SAM9261_BASE_SSC1 0xfffc0000 -#define AT91SAM9261_BASE_SSC2 0xfffc4000 -#define AT91SAM9261_BASE_SPI0 0xfffc8000 -#define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00 +#define ATMEL_BASE_SYS 0xffffea00 +#define ATMEL_BASE_SDRAMC 0xffffea00 +#define ATMEL_BASE_SMC 0xffffec00 +#define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_GPBR 0xfffffd50 /* - * System Peripherals (offset from AT91_BASE_SYS) + * Internal Memory common on all these SoCs */ -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */ -#define AT91_USART0 AT91SAM9261_BASE_US0 -#define AT91_USART1 AT91SAM9261_BASE_US1 -#define AT91_USART2 AT91SAM9261_BASE_US2 +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ +#define ATMEL_SIZE_ROM SZ_32K /* Internal ROM size (32Kb) */ -#endif /* CONFIG_AT91_LEGACY */ +#define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */ +#define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */ /* - * Internal Memory. + * External memory */ -#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ - -#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ +#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 -#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ -#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ /* - * Cpu Name + * SoC specific defines */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" +#if defined(CONFIG_AT91SAM9261) +# define ATMEL_CPU_NAME "AT91SAM9261" +#elif defined(CONFIG_AT91SAM9G10) +# define ATMEL_CPU_NAME "AT91SAM9G10" +#endif #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index 4ada1ceaf8..bfd408bb1d 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -2,9 +2,11 @@ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] * * (C) 2007 Atmel Corporation. + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de * - * Common definitions. - * Based on AT91SAM9263 datasheet revision B (Preliminary). + * Definitions for the SoC: + * AT91SAM9263 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,140 +18,120 @@ #define AT91SAM9263_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Peripherals */ -#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ -#define AT91SAM9263_ID_US0 7 /* USART 0 */ -#define AT91SAM9263_ID_US1 8 /* USART 1 */ -#define AT91SAM9263_ID_US2 9 /* USART 2 */ -#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ -#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ -#define AT91SAM9263_ID_CAN 12 /* CAN */ -#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ -#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ -#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ -#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ -#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ -#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ -#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ -#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ -#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ -#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ -#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ -#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ -#define AT91SAM9263_ID_UHP 29 /* USB Host port */ -#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_ECC0_BASE 0xffffe000 -#define AT91_SDRAMC0_BASE 0xffffe200 -#define AT91_SMC0_BASE 0xffffe400 -#define AT91_ECC1_BASE 0xffffe600 -#define AT91_SDRAMC1_BASE 0xffffe800 -#define AT91_SMC1_BASE 0xffffea00 -#define AT91_MATRIX_BASE 0xffffec00 -#define AT91_CCFG_BASE 0xffffed10 -#define AT91_DBGU_BASE 0xffffee00 -#define AT91_AIC_BASE 0xfffff000 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_RTT0_BASE 0xfffffd20 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 -#define AT91_RTT1_BASE 0xfffffd50 -#define AT91_GPBR_BASE 0xfffffd60 - -#ifdef CONFIG_AT91_LEGACY +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* - * User Peripheral physical base addresses. + * Peripheral identifiers/interrupts. */ -#define AT91SAM9263_BASE_UDP 0xfff78000 -#define AT91SAM9263_BASE_TCB0 0xfff7c000 -#define AT91SAM9263_BASE_TC0 0xfff7c000 -#define AT91SAM9263_BASE_TC1 0xfff7c040 -#define AT91SAM9263_BASE_TC2 0xfff7c080 -#define AT91SAM9263_BASE_MCI0 0xfff80000 -#define AT91SAM9263_BASE_MCI1 0xfff84000 -#define AT91SAM9263_BASE_TWI 0xfff88000 -#define AT91SAM9263_BASE_US0 0xfff8c000 -#define AT91SAM9263_BASE_US1 0xfff90000 -#define AT91SAM9263_BASE_US2 0xfff94000 -#define AT91SAM9263_BASE_SSC0 0xfff98000 -#define AT91SAM9263_BASE_SSC1 0xfff9c000 -#define AT91SAM9263_BASE_AC97C 0xfffa0000 -#define AT91SAM9263_BASE_SPI0 0xfffa4000 -#define AT91SAM9263_BASE_SPI1 0xfffa8000 -#define AT91SAM9263_BASE_CAN 0xfffac000 -#define AT91SAM9263_BASE_PWMC 0xfffb8000 -#define AT91SAM9263_BASE_EMAC 0xfffbc000 -#define AT91SAM9263_BASE_ISI 0xfffc4000 -#define AT91SAM9263_BASE_2DGE 0xfffc8000 -#define AT91_BASE_SYS 0xffffe000 +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Peripherals */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ +/* Reserved: 5 */ +/* Reserved: 6 */ +#define ATMEL_ID_USART0 7 /* USART 0 */ +#define ATMEL_ID_USART1 8 /* USART 1 */ +#define ATMEL_ID_USART2 9 /* USART 2 */ +#define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */ +#define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */ +#define ATMEL_ID_CAN 12 /* CAN */ +#define ATMEL_ID_TWI 13 /* Two-Wire Interface */ +#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_AC97C 18 /* AC97 Controller */ +#define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ +#define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_EMAC 21 /* Ethernet */ +/* Reserved: 22 */ +#define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */ +#define ATMEL_ID_UDP 24 /* USB Device Port */ +#define ATMEL_ID_ISI 25 /* Image Sensor Interface */ +#define ATMEL_ID_LCDC 26 /* LCD Controller */ +#define ATMEL_ID_DMA 27 /* DMA Controller */ +/* Reserved: 28 */ +#define ATMEL_ID_UHP 29 /* USB Host port */ +#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ /* - * System Peripherals (offset from AT91_BASE_SYS) + * User Peripherals physical base addresses. */ -#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) -#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) -#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) -#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) -#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9263_BASE_US0 -#define AT91_USART1 AT91SAM9263_BASE_US1 -#define AT91_USART2 AT91SAM9263_BASE_US2 - -#define AT91_SMC AT91_SMC0 -#define AT91_SDRAMC AT91_SDRAMC0 +#define ATMEL_BASE_UDP 0xfff78000 +#define ATMEL_BASE_TCB0 0xfff7c000 +#define ATMEL_BASE_TC0 0xfff7c000 +#define ATMEL_BASE_TC1 0xfff7c040 +#define ATMEL_BASE_TC2 0xfff7c080 +#define ATMEL_BASE_MCI0 0xfff80000 +#define ATMEL_BASE_MCI1 0xfff84000 +#define ATMEL_BASE_TWI 0xfff88000 +#define ATMEL_BASE_USART0 0xfff8c000 +#define ATMEL_BASE_USART1 0xfff90000 +#define ATMEL_BASE_USART2 0xfff94000 +#define ATMEL_BASE_SSC0 0xfff98000 +#define ATMEL_BASE_SSC1 0xfff9c000 +#define ATMEL_BASE_AC97C 0xfffa0000 +#define ATMEL_BASE_SPI0 0xfffa4000 +#define ATMEL_BASE_SPI1 0xfffa8000 +#define ATMEL_BASE_CAN 0xfffac000 +#define ATMEL_BASE_PWMC 0xfffb8000 +#define ATMEL_BASE_EMAC 0xfffbc000 +#define ATMEL_BASE_ISI 0xfffc4000 +#define ATMEL_BASE_2DGE 0xfffc8000 -#endif /* CONFIG_AT91_LEGACY */ +/* + * System Peripherals physical base addresses. + */ +#define ATMEL_BASE_ECC0 0xffffe000 +#define ATMEL_BASE_SDRAMC0 0xffffe200 +#define ATMEL_BASE_SMC0 0xffffe400 +#define ATMEL_BASE_ECC1 0xffffe600 +#define ATMEL_BASE_SDRAMC1 0xffffe800 +#define ATMEL_BASE_SMC1 0xffffea00 +#define ATMEL_BASE_MATRIX 0xffffec00 +#define ATMEL_BASE_CCFG 0xffffed10 +#define ATMEL_BASE_DBGU 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_PIOA 0xfffff200 +#define ATMEL_BASE_PIOB 0xfffff400 +#define ATMEL_BASE_PIOC 0xfffff600 +#define ATMEL_BASE_PIOD 0xfffff800 +#define ATMEL_BASE_PIOE 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWC 0xfffffd10 +#define ATMEL_BASE_RTT0 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_RTT1 0xfffffd50 +#define ATMEL_BASE_GPBR 0xfffffd60 /* * Internal Memory. */ -#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ -#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ +#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */ + +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */ -#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ +#define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */ -#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ -#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ +#define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */ +#define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */ +#define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */ -#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ -#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ -#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ /* * Cpu Name */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" +#define ATMEL_CPU_NAME "AT91SAM9263" #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 445f4b2123..364b86c88f 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -1,10 +1,10 @@ /* * Chip-specific header file for the AT91SAM9M1x family * - * Copyright (C) 2008 Atmel Corporation. + * (C) 2008 Atmel Corporation. * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. + * Definitions for the SoC: + * AT91SAM9G45 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,137 +16,126 @@ #define AT91SAM9G45_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller Interrupt */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_SMC_BASE 0xffffe800 -#define AT91_MATRIX_BASE 0xffffea00 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* - * User Peripheral physical base addresses. + * Peripheral identifiers/interrupts. */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 -#define AT91_BASE_SYS 0xffffe200 +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ +#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */ +#define ATMEL_ID_TRNG 6 /* True Random Number Generator */ +#define ATMEL_ID_USART0 7 /* USART 0 */ +#define ATMEL_ID_USART1 8 /* USART 1 */ +#define ATMEL_ID_USART2 9 /* USART 2 */ +#define ATMEL_ID_USART3 10 /* USART 3 */ +#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ +#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */ +#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */ +#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */ +#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */ +#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */ +#define ATMEL_ID_DMA 21 /* DMA Controller */ +#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ +#define ATMEL_ID_LCDC 23 /* LCD Controller */ +#define ATMEL_ID_AC97C 24 /* AC97 Controller */ +#define ATMEL_ID_EMAC 25 /* Ethernet MAC */ +#define ATMEL_ID_ISI 26 /* Image Sensor Interface */ +#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */ +#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ +#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ +#define ATMEL_ID_VDEC 30 /* Video Decoder */ +#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */ /* - * System Peripherals (offset from AT91_BASE_SYS) + * User Peripherals physical base addresses. */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) -#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9G45_BASE_US0 -#define AT91_USART1 AT91SAM9G45_BASE_US1 -#define AT91_USART2 AT91SAM9G45_BASE_US2 -#define AT91_USART3 AT91SAM9G45_BASE_US3 +#define ATMEL_BASE_UDPHS 0xfff78000 +#define ATMEL_BASE_TC0 0xfff7c000 +#define ATMEL_BASE_TC1 0xfff7c040 +#define ATMEL_BASE_TC2 0xfff7c080 +#define ATMEL_BASE_MCI0 0xfff80000 +#define ATMEL_BASE_TWI0 0xfff84000 +#define ATMEL_BASE_TWI1 0xfff88000 +#define ATMEL_BASE_USART0 0xfff8c000 +#define ATMEL_BASE_USART1 0xfff90000 +#define ATMEL_BASE_USART2 0xfff94000 +#define ATMEL_BASE_USART3 0xfff98000 +#define ATMEL_BASE_SSC0 0xfff9c000 +#define ATMEL_BASE_SSC1 0xfffa0000 +#define ATMEL_BASE_SPI0 0xfffa4000 +#define ATMEL_BASE_SPI1 0xfffa8000 +#define ATMEL_BASE_AC97C 0xfffac000 +#define ATMEL_BASE_TSC 0xfffb0000 +#define ATMEL_BASE_ISI 0xfffb4000 +#define ATMEL_BASE_PWMC 0xfffb8000 +#define ATMEL_BASE_EMAC 0xfffbc000 +#define ATMEL_BASE_AES 0xfffc0000 +#define ATMEL_BASE_TDES 0xfffc4000 +#define ATMEL_BASE_SHA 0xfffc8000 +#define ATMEL_BASE_TRNG 0xfffcc000 +#define ATMEL_BASE_MCI1 0xfffd0000 +#define ATMEL_BASE_TC3 0xfffd4000 +#define ATMEL_BASE_TC4 0xfffd4040 +#define ATMEL_BASE_TC5 0xfffd4080 +/* Reserved: 0xfffd8000 - 0xffffe1ff */ -#endif +/* + * System Peripherals physical base addresses. + */ +#define ATMEL_BASE_SYS 0xffffe200 +#define ATMEL_BASE_ECC 0xffffe200 +#define ATMEL_BASE_DDRSDRC1 0xffffe400 +#define ATMEL_BASE_DDRSDRC0 0xffffe600 +#define ATMEL_BASE_SMC 0xffffe800 +#define ATMEL_BASE_MATRIX 0xffffea00 +#define ATMEL_BASE_DMA 0xffffec00 +#define ATMEL_BASE_DBGU 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_PIOA 0xfffff200 +#define ATMEL_BASE_PIOB 0xfffff400 +#define ATMEL_BASE_PIOC 0xfffff600 +#define ATMEL_BASE_PIOD 0xfffff800 +#define ATMEL_BASE_PIOE 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_GPBR 0xfffffd60 +#define ATMEL_BASE_RTC 0xfffffdb0 +/* Reserved: 0xfffffdc0 - 0xffffffff */ /* * Internal Memory. */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ +#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ +#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ +#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */ +#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ /* * Cpu Name */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" +#define ATMEL_CPU_NAME "AT91SAM9G45" #endif diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h index 716f81fa3c..293d0bf56b 100644 --- a/arch/arm/include/asm/arch-at91/gpio.h +++ b/arch/arm/include/asm/arch-at91/gpio.h @@ -18,7 +18,7 @@ #include <asm/arch/at91_pio.h> #include <asm/arch/hardware.h> -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #define PIN_BASE 32 @@ -192,13 +192,13 @@ #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) static unsigned long at91_pios[] = { - AT91_PIOA, - AT91_PIOB, - AT91_PIOC, -#ifdef AT91_PIOD - AT91_PIOD, -#ifdef AT91_PIOE - AT91_PIOE + ATMEL_BASE_PIOA, + ATMEL_BASE_PIOB, + ATMEL_BASE_PIOC, +#ifdef ATMEL_BASE_PIOD + ATMEL_BASE_PIOD, +#ifdef ATMEL_BASE_PIOE + ATMEL_BASE_PIOE #endif #endif }; @@ -207,7 +207,7 @@ static inline void *pin_to_controller(unsigned pin) { pin -= PIN_BASE; pin /= 32; - return (void *)(AT91_BASE_SYS + at91_pios[pin]); + return (void *)(at91_pios[pin]); } static inline unsigned pin_to_mask(unsigned pin) diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h index 6b44d61207..36af571a5b 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/include/asm/arch-at91/hardware.h @@ -1,80 +1,48 @@ /* - * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> * - * Copyright (C) 2003 SAN People - * Copyright (C) 2003 ATMEL + * See file CREDITS for list of people who contributed to this + * project. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <asm/sizes.h> +#ifndef __ASM_ARM_ARCH_HARDWARE_H__ +#define __ASM_ARM_ARCH_HARDWARE_H__ #if defined(CONFIG_AT91RM9200) -#include <asm/arch-at91/at91rm9200.h> -#define AT91_PMC_UHP AT91RM9200_PMC_UHP -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#include <asm/arch/at91sam9260.h> -#define AT91_BASE_MCI AT91SAM9260_BASE_MCI -#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 -#define AT91_BASE_SPI1 AT91SAM9260_BASE_SPI1 -#define AT91_ID_UHP AT91SAM9260_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include <asm/arch/at91rm9200.h> +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) || \ + defined(CONFIG_AT91SAM9XE) +# include <asm/arch/at91sam9260.h> #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9G10) -#include <asm/arch/at91sam9261.h> -#define AT91_BASE_SPI AT91SAM9261_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9261_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include <asm/arch/at91sam9261.h> #elif defined(CONFIG_AT91SAM9263) -#include <asm/arch/at91sam9263.h> -#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9263_ID_UHP -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include <asm/arch/at91sam9263.h> #elif defined(CONFIG_AT91SAM9RL) -#include <asm/arch/at91sam9rl.h> -#define AT91_BASE_SPI AT91SAM9RL_BASE_SPI -#define AT91_ID_UHP AT91SAM9RL_ID_UHP +# include <asm/arch/at91sam9rl.h> #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) -#include <asm/arch/at91sam9g45.h> -#define AT91_BASE_EMAC AT91SAM9G45_BASE_EMAC -#define AT91_BASE_SPI AT91SAM9G45_BASE_SPI0 -#define AT91_ID_UHP AT91SAM9G45_ID_UHPHS -#define AT91_PMC_UHP AT91SAM926x_PMC_UHP +# include <asm/arch/at91sam9g45.h> #elif defined(CONFIG_AT91CAP9) -#include <asm/arch/at91cap9.h> -#define AT91_BASE_SPI AT91CAP9_BASE_SPI0 -#define AT91_ID_UHP AT91CAP9_ID_UHP -#define AT91_PMC_UHP AT91CAP9_PMC_UHP +# include <asm/arch/at91cap9.h> #elif defined(CONFIG_AT91X40) -#include <asm/arch/at91x40.h> +# include <asm/arch/at91x40.h> #else -#error "Unsupported AT91 processor" +# error "Unsupported AT91 processor" #endif -/* External Memory Map */ -#define AT91_CHIPSELECT_0 0x10000000 -#define AT91_CHIPSELECT_1 0x20000000 -#define AT91_CHIPSELECT_2 0x30000000 -#define AT91_CHIPSELECT_3 0x40000000 -#define AT91_CHIPSELECT_4 0x50000000 -#define AT91_CHIPSELECT_5 0x60000000 -#define AT91_CHIPSELECT_6 0x70000000 -#define AT91_CHIPSELECT_7 0x80000000 - -/* SDRAM */ -#ifdef CONFIG_DRAM_BASE -#define AT91_SDRAM_BASE CONFIG_DRAM_BASE -#else -#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 -#endif - -/* Clocks */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - -#endif +#endif /* __ASM_ARM_ARCH_HARDWARE_H__ */ diff --git a/arch/arm/include/asm/arch-at91/io.h b/arch/arm/include/asm/arch-at91/io.h deleted file mode 100644 index 38d185eb7c..0000000000 --- a/arch/arm/include/asm/arch-at91/io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * [origin: Linux kernel include/asm-arm/arch-at91/io.h] - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#include <asm/io.h> - -#ifdef CONFIG_AT91_LEGACY - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void *addr = (void *)AT91_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void *addr = (void *)AT91_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif - -#endif diff --git a/arch/arm/include/asm/arch-at91/memory-map.h b/arch/arm/include/asm/arch-at91/memory-map.h deleted file mode 100644 index d489fa2157..0000000000 --- a/arch/arm/include/asm/arch-at91/memory-map.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> - * Lead Tech Design <www.leadtechdesign.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__ -#define __ASM_ARM_ARCH_MEMORYMAP_H__ - -#include <asm/arch/hardware.h> - -#define USART0_BASE AT91_USART0 -#define USART1_BASE AT91_USART1 -#define USART2_BASE AT91_USART2 -#define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) -#define SPI0_BASE AT91_BASE_SPI -#define SPI1_BASE AT91_BASE_SPI1 - -#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 9488c49132..d8e7ebb0be 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -26,4 +26,8 @@ CROSS_COMPILE ?= avr32-linux- CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax -PLATFORM_LDFLAGS += --relax +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections + +LDFLAGS_u-boot = --gc-sections --relax + +LDSCRIPT = $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/avr32/cpu/at32ap700x/clk.c b/arch/avr32/cpu/at32ap700x/clk.c index 742bc6b5a2..b63b9df143 100644 --- a/arch/avr32/cpu/at32ap700x/clk.c +++ b/arch/avr32/cpu/at32ap700x/clk.c @@ -24,7 +24,7 @@ #include <asm/io.h> #include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include <asm/arch/portmux.h> #include "sm.h" diff --git a/arch/avr32/cpu/at32ap700x/portmux.c b/arch/avr32/cpu/at32ap700x/portmux.c index b1f2c6f1ff..e3e38a2a75 100644 --- a/arch/avr32/cpu/at32ap700x/portmux.c +++ b/arch/avr32/cpu/at32ap700x/portmux.c @@ -24,7 +24,7 @@ #include <asm/io.h> #include <asm/arch/chip-features.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include <asm/arch/portmux.h> /* diff --git a/arch/avr32/cpu/at32ap700x/sm.h b/arch/avr32/cpu/at32ap700x/sm.h index b6e4409b22..9a3804efe4 100644 --- a/arch/avr32/cpu/at32ap700x/sm.h +++ b/arch/avr32/cpu/at32ap700x/sm.h @@ -197,8 +197,8 @@ /* Register access macros */ #define sm_readl(reg) \ - readl((void *)SM_BASE + SM_##reg) + readl((void *)ATMEL_BASE_SM + SM_##reg) #define sm_writel(reg,value) \ - writel((value), (void *)SM_BASE + SM_##reg) + writel((value), (void *)ATMEL_BASE_SM + SM_##reg) #endif /* __CPU_AT32AP_SM_H__ */ diff --git a/arch/avr32/cpu/cpu.c b/arch/avr32/cpu/cpu.c index e4489bb2e2..790783767f 100644 --- a/arch/avr32/cpu/cpu.c +++ b/arch/avr32/cpu/cpu.c @@ -27,7 +27,7 @@ #include <asm/sysreg.h> #include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include "hsmc3.h" diff --git a/arch/avr32/cpu/hsdramc.c b/arch/avr32/cpu/hsdramc.c index b6eae667c2..1485494f49 100644 --- a/arch/avr32/cpu/hsdramc.c +++ b/arch/avr32/cpu/hsdramc.c @@ -25,7 +25,7 @@ #include <asm/sdram.h> #include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include "hsdramc1.h" diff --git a/arch/avr32/cpu/hsdramc1.h b/arch/avr32/cpu/hsdramc1.h index 305d2cb5d3..e18e074a7a 100644 --- a/arch/avr32/cpu/hsdramc1.h +++ b/arch/avr32/cpu/hsdramc1.h @@ -136,8 +136,8 @@ /* Register access macros */ #define hsdramc1_readl(reg) \ - readl((void *)HSDRAMC_BASE + HSDRAMC1_##reg) + readl((void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) #define hsdramc1_writel(reg,value) \ - writel((value), (void *)HSDRAMC_BASE + HSDRAMC1_##reg) + writel((value), (void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg) #endif /* __ASM_AVR32_HSDRAMC1_H__ */ diff --git a/arch/avr32/cpu/hsmc3.h b/arch/avr32/cpu/hsmc3.h index ca533b922e..ac472952a2 100644 --- a/arch/avr32/cpu/hsmc3.h +++ b/arch/avr32/cpu/hsmc3.h @@ -119,8 +119,8 @@ /* Register access macros */ #define hsmc3_readl(reg) \ - readl((void *)HSMC_BASE + HSMC3_##reg) + readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg) #define hsmc3_writel(reg,value) \ - writel((value), (void *)HSMC_BASE + HSMC3_##reg) + writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg) #endif /* __CPU_AT32AP_HSMC3_H__ */ diff --git a/arch/avr32/cpu/interrupts.c b/arch/avr32/cpu/interrupts.c index c6d8d16e39..c6ea435c1d 100644 --- a/arch/avr32/cpu/interrupts.c +++ b/arch/avr32/cpu/interrupts.c @@ -27,7 +27,7 @@ #include <asm/processor.h> #include <asm/sysreg.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #define HANDLER_MASK 0x00ffffff #define INTLEV_SHIFT 30 @@ -125,7 +125,7 @@ static int set_interrupt_handler(unsigned int nr, void (*handler)(void), intpr = (handler_addr & HANDLER_MASK); intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT; - writel(intpr, (void *)INTC_BASE + 4 * nr); + writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr); return 0; } diff --git a/arch/avr32/cpu/portmux-gpio.c b/arch/avr32/cpu/portmux-gpio.c index 9acd040d1b..7b64c89a98 100644 --- a/arch/avr32/cpu/portmux-gpio.c +++ b/arch/avr32/cpu/portmux-gpio.c @@ -22,7 +22,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include <asm/arch/gpio.h> void portmux_select_peripheral(void *port, unsigned long pin_mask, diff --git a/arch/avr32/cpu/portmux-pio.c b/arch/avr32/cpu/portmux-pio.c index a29f94e3ba..cb5e96205a 100644 --- a/arch/avr32/cpu/portmux-pio.c +++ b/arch/avr32/cpu/portmux-pio.c @@ -22,7 +22,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include <asm/arch/gpio.h> void portmux_select_peripheral(void *port, unsigned long pin_mask, diff --git a/board/atmel/atstk1000/u-boot.lds b/arch/avr32/cpu/u-boot.lds index 0e532f234e..0e532f234e 100644 --- a/board/atmel/atstk1000/u-boot.lds +++ b/arch/avr32/cpu/u-boot.lds diff --git a/arch/avr32/include/asm/arch-at32ap700x/gpio.h b/arch/avr32/include/asm/arch-at32ap700x/gpio.h index 303e35313a..4322eac1c7 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/gpio.h +++ b/arch/avr32/include/asm/arch-at32ap700x/gpio.h @@ -23,7 +23,7 @@ #define __ASM_AVR32_ARCH_GPIO_H__ #include <asm/arch/chip-features.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #define NR_GPIO_CONTROLLERS 5 @@ -45,15 +45,15 @@ static inline void *pio_pin_to_port(unsigned int pin) { switch (pin >> 5) { case 0: - return (void *)PIOA_BASE; + return (void *)ATMEL_BASE_PIOA; case 1: - return (void *)PIOB_BASE; + return (void *)ATMEL_BASE_PIOB; case 2: - return (void *)PIOC_BASE; + return (void *)ATMEL_BASE_PIOC; case 3: - return (void *)PIOD_BASE; + return (void *)ATMEL_BASE_PIOD; case 4: - return (void *)PIOE_BASE; + return (void *)ATMEL_BASE_PIOE; default: return NULL; } diff --git a/arch/avr32/include/asm/arch-at32ap700x/memory-map.h b/arch/avr32/include/asm/arch-at32ap700x/hardware.h index 6592c039fa..9172eef60f 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/memory-map.h +++ b/arch/avr32/include/asm/arch-at32ap700x/hardware.h @@ -19,8 +19,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __AT32AP7000_MEMORY_MAP_H__ -#define __AT32AP7000_MEMORY_MAP_H__ +#ifndef __AT32AP7000_HARDWARE_H__ +#define __AT32AP7000_HARDWARE_H__ /* Internal and external memories */ #define EBI_SRAM_CS0_BASE 0x00000000 @@ -43,44 +43,44 @@ #define INTERNAL_SRAM_SIZE 0x00008000 /* Devices on the High Speed Bus (HSB) */ -#define LCDC_BASE 0xFF000000 -#define DMAC_BASE 0xFF200000 -#define USB_FIFO 0xFF300000 +#define LCDC_BASE 0xFF000000 +#define DMAC_BASE 0xFF200000 +#define USB_FIFO 0xFF300000 /* Devices on Peripheral Bus A (PBA) */ -#define SPI0_BASE 0xFFE00000 -#define SPI1_BASE 0xFFE00400 -#define TWI_BASE 0xFFE00800 -#define USART0_BASE 0xFFE00C00 -#define USART1_BASE 0xFFE01000 -#define USART2_BASE 0xFFE01400 -#define USART3_BASE 0xFFE01800 -#define SSC0_BASE 0xFFE01C00 -#define SSC1_BASE 0xFFE02000 -#define SSC2_BASE 0xFFE02400 -#define PIOA_BASE 0xFFE02800 -#define PIOB_BASE 0xFFE02C00 -#define PIOC_BASE 0xFFE03000 -#define PIOD_BASE 0xFFE03400 -#define PIOE_BASE 0xFFE03800 -#define PSIF_BASE 0xFFE03C00 +#define ATMEL_BASE_SPI0 0xFFE00000 +#define ATMEL_BASE_SPI1 0xFFE00400 +#define ATMEL_BASE_TWI0 0xFFE00800 +#define ATMEL_BASE_USART0 0xFFE00C00 +#define ATMEL_BASE_USART1 0xFFE01000 +#define ATMEL_BASE_USART2 0xFFE01400 +#define ATMEL_BASE_USART3 0xFFE01800 +#define ATMEL_BASE_SSC0 0xFFE01C00 +#define ATMEL_BASE_SSC1 0xFFE02000 +#define ATMEL_BASE_SSC2 0xFFE02400 +#define ATMEL_BASE_PIOA 0xFFE02800 +#define ATMEL_BASE_PIOB 0xFFE02C00 +#define ATMEL_BASE_PIOC 0xFFE03000 +#define ATMEL_BASE_PIOD 0xFFE03400 +#define ATMEL_BASE_PIOE 0xFFE03800 +#define ATMEL_BASE_PSIF 0xFFE03C00 /* Devices on Peripheral Bus B (PBB) */ -#define SM_BASE 0xFFF00000 -#define INTC_BASE 0xFFF00400 -#define HMATRIX_BASE 0xFFF00800 -#define TIMER0_BASE 0xFFF00C00 -#define TIMER1_BASE 0xFFF01000 -#define PWM_BASE 0xFFF01400 -#define MACB0_BASE 0xFFF01800 -#define MACB1_BASE 0xFFF01C00 -#define DAC_BASE 0xFFF02000 -#define MMCI_BASE 0xFFF02400 -#define AUDIOC_BASE 0xFFF02800 -#define HISI_BASE 0xFFF02C00 -#define USB_BASE 0xFFF03000 -#define HSMC_BASE 0xFFF03400 -#define HSDRAMC_BASE 0xFFF03800 -#define ECC_BASE 0xFFF03C00 +#define ATMEL_BASE_SM 0xFFF00000 +#define ATMEL_BASE_INTC 0xFFF00400 +#define ATMEL_BASE_HMATRIX 0xFFF00800 +#define ATMEL_BASE_TIMER0 0xFFF00C00 +#define ATMEL_BASE_TIMER1 0xFFF01000 +#define ATMEL_BASE_PWM 0xFFF01400 +#define ATMEL_BASE_MACB0 0xFFF01800 +#define ATMEL_BASE_MACB1 0xFFF01C00 +#define ATMEL_BASE_DAC 0xFFF02000 +#define ATMEL_BASE_MMCI 0xFFF02400 +#define ATMEL_BASE_AUDIOC 0xFFF02800 +#define ATMEL_BASE_HISI 0xFFF02C00 +#define ATMEL_BASE_USB 0xFFF03000 +#define ATMEL_BASE_HSMC 0xFFF03400 +#define ATMEL_BASE_HSDRAMC 0xFFF03800 +#define ATMEL_BASE_ECC 0xFFF03C00 -#endif /* __AT32AP7000_MEMORY_MAP_H__ */ +#endif /* __AT32AP7000_HARDWARE_H__ */ diff --git a/arch/avr32/include/asm/arch-at32ap700x/portmux.h b/arch/avr32/include/asm/arch-at32ap700x/portmux.h index 1ba52e5ddb..859c121aa0 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/portmux.h +++ b/arch/avr32/include/asm/arch-at32ap700x/portmux.h @@ -24,11 +24,11 @@ #include <asm/arch/gpio.h> -#define PORTMUX_PORT_A ((void *)PIOA_BASE) -#define PORTMUX_PORT_B ((void *)PIOB_BASE) -#define PORTMUX_PORT_C ((void *)PIOC_BASE) -#define PORTMUX_PORT_D ((void *)PIOD_BASE) -#define PORTMUX_PORT_E ((void *)PIOE_BASE) +#define PORTMUX_PORT_A ((void *)ATMEL_BASE_PIOA) +#define PORTMUX_PORT_B ((void *)ATMEL_BASE_PIOB) +#define PORTMUX_PORT_C ((void *)ATMEL_BASE_PIOC) +#define PORTMUX_PORT_D ((void *)ATMEL_BASE_PIOD) +#define PORTMUX_PORT_E ((void *)ATMEL_BASE_PIOE) void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, unsigned long flags, unsigned long drive_strength); diff --git a/arch/avr32/include/asm/hmatrix-common.h b/arch/avr32/include/asm/hmatrix-common.h index 4b7e6105dd..9a86fe4baa 100644 --- a/arch/avr32/include/asm/hmatrix-common.h +++ b/arch/avr32/include/asm/hmatrix-common.h @@ -117,7 +117,7 @@ struct hmatrix_regs { /* Register access macros */ #define __hmatrix_reg(reg) \ - (((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg) + (((volatile struct hmatrix_regs *)ATMEL_BASE_HMATRIX)->reg) #define hmatrix_read(reg) \ (__hmatrix_reg(reg)) #define hmatrix_write(reg, value) \ diff --git a/arch/avr32/include/asm/setup.h b/arch/avr32/include/asm/setup.h index e6ef8d6b50..7f5d883442 100644 --- a/arch/avr32/include/asm/setup.h +++ b/arch/avr32/include/asm/setup.h @@ -107,6 +107,13 @@ struct tag_ethernet { #define AETH_INVALID_PHY 0xff +/* board information information */ +#define ATAG_BOARDINFO 0x54410008 + +struct tag_boardinfo { + u32 board_number; +}; + struct tag { struct tag_header hdr; union { @@ -115,6 +122,7 @@ struct tag { struct tag_cmdline cmdline; struct tag_clock clock; struct tag_ethernet ethernet; + struct tag_boardinfo boardinfo; } u; }; diff --git a/arch/avr32/lib/bootm.c b/arch/avr32/lib/bootm.c index 8a47cfeb4a..c9a55ffb2c 100644 --- a/arch/avr32/lib/bootm.c +++ b/arch/avr32/lib/bootm.c @@ -165,6 +165,16 @@ static struct tag *setup_ethernet_tags(struct tag *params) return params; } +static struct tag *setup_boardinfo_tag(struct tag *params) +{ + params->hdr.tag = ATAG_BOARDINFO; + params->hdr.size = tag_size(tag_boardinfo); + + params->u.boardinfo.board_number = gd->bd->bi_board_number; + + return tag_next(params); +} + static void setup_end_tag(struct tag *params) { params->hdr.tag = ATAG_NONE; @@ -195,6 +205,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima params = setup_commandline_tag(params, commandline); params = setup_clock_tags(params); params = setup_ethernet_tags(params); + params = setup_boardinfo_tag(params); setup_end_tag(params); printf("\nStarting kernel at %p (params at %p)...\n\n", diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index 49bc03e3ec..59577b8445 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -112,8 +112,8 @@ int board_early_init_r(void) #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bi) { - macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); + macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); return 0; } #endif diff --git a/board/atmel/atngw100/config.mk b/board/atmel/atngw100/config.mk deleted file mode 100644 index ea76d05df8..0000000000 --- a/board/atmel/atngw100/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00000000 -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -PLATFORM_LDFLAGS += --gc-sections diff --git a/board/atmel/atngw100/u-boot.lds b/board/atmel/atngw100/u-boot.lds deleted file mode 100644 index 0a1a8e1653..0000000000 --- a/board/atmel/atngw100/u-boot.lds +++ /dev/null @@ -1,72 +0,0 @@ -/* -*- Fundamental -*- - * - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") -OUTPUT_ARCH(avr32) -ENTRY(_start) - -SECTIONS -{ - . = 0; - _text = .; - .text : { - *(.exception.text) - *(.text) - *(.text.*) - } - _etext = .; - - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - _data = .; - .data : { - *(.data) - *(.data.*) - } - - . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { - KEEP(*(.u_boot_cmd)) - } - __u_boot_cmd_end = .; - - . = ALIGN(4); - _got = .; - .got : { - *(.got) - } - _egot = .; - - . = ALIGN(8); - _edata = .; - - .bss : { - *(.bss) - *(.bss.*) - } - . = ALIGN(8); - __bss_end__ = .; -} diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 8b1e1b57d7..58048a4c3b 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -134,8 +134,8 @@ int board_early_init_r(void) #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bi) { - macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); + macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); return 0; } #endif diff --git a/board/atmel/atstk1000/config.mk b/board/atmel/atstk1000/config.mk deleted file mode 100644 index 284f7ff32e..0000000000 --- a/board/atmel/atstk1000/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -PLATFORM_LDFLAGS += --gc-sections -CONFIG_SYS_TEXT_BASE = 0x00000000 diff --git a/board/earthlcd/favr-32-ezkit/config.mk b/board/earthlcd/favr-32-ezkit/config.mk deleted file mode 100644 index 284f7ff32e..0000000000 --- a/board/earthlcd/favr-32-ezkit/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -PLATFORM_LDFLAGS += --gc-sections -CONFIG_SYS_TEXT_BASE = 0x00000000 diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c index b0eca939b7..0eedee4112 100644 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -104,6 +104,7 @@ int board_early_init_r(void) #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) int board_eth_init(bd_t *bi) { - return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, + bi->bi_phy_id[0]); } #endif diff --git a/board/earthlcd/favr-32-ezkit/u-boot.lds b/board/earthlcd/favr-32-ezkit/u-boot.lds deleted file mode 100644 index 20e363130d..0000000000 --- a/board/earthlcd/favr-32-ezkit/u-boot.lds +++ /dev/null @@ -1,70 +0,0 @@ -/* -*- Fundamental -*- - * - * Copyright (C) 2008 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this project. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place, Suite 330, Boston, MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") -OUTPUT_ARCH(avr32) -ENTRY(_start) - -SECTIONS -{ - . = 0; - _text = .; - .text : { - *(.exception.text) - *(.text) - *(.text.*) - } - _etext = .; - - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - _data = .; - .data : { - *(.data) - *(.data.*) - } - - . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { - KEEP(*(.u_boot_cmd)) - } - __u_boot_cmd_end = .; - - . = ALIGN(4); - _got = .; - .got : { - *(.got) - } - _egot = .; - - . = ALIGN(8); - _edata = .; - - .bss (NOLOAD) : { - *(.bss) - *(.bss.*) - } - . = ALIGN(8); - __bss_end__ = .; -} diff --git a/board/esd/otc570/config.mk b/board/esd/otc570/config.mk deleted file mode 100644 index e554a45007..0000000000 --- a/board/esd/otc570/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 410d8b48a1..15faa1627e 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2010-2011 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -27,7 +27,7 @@ */ #include <common.h> -#include <asm/arch/at91sam9263.h> +#include <asm/io.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> @@ -35,14 +35,14 @@ #include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/hardware.h> -#include <asm/arch/io.h> -#include <atmel_lcdc.h> -#include <lcd.h> #include <netdev.h> -#ifdef CONFIG_LCD_INFO -#include <nand.h> -#include <version.h> +#ifdef CONFIG_LCD +# include <atmel_lcdc.h> +# include <lcd.h> +# ifdef CONFIG_LCD_INFO +# include <nand.h> +# include <version.h> +# endif #endif DECLARE_GLOBAL_DATA_PTR; @@ -73,8 +73,8 @@ int get_hw_rev(void) static void otc570_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -93,8 +93,8 @@ static void otc570_nand_hw_init(void) &smc->cs[3].cycle); writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | - AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); /* Configure RDY/BSY */ @@ -108,9 +108,9 @@ static void otc570_nand_hw_init(void) #ifdef CONFIG_MACB static void otc570_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -123,7 +123,7 @@ static void otc570_macb_hw_init(void) */ static void otc570_ethercat_hw_init(void) { - at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; /* Configure SMC EBI1_CS0 for EtherCAT */ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | @@ -155,7 +155,7 @@ vidinfo_t panel_info = { .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | ATMEL_LCDC_INVFRAME_INVERTED, - .vl_bpix = 3, /* Bits per pixel, 0 = 1bit, 3 = 8bit */ + .vl_bpix = LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */ .vl_tft = 1, /* 0 = passive, 1 = TFT */ .vl_vsync_len = 1, /* Length of vertical sync in NOL */ .vl_upper_margin = 35, /* Idle lines at the frame start */ @@ -164,22 +164,22 @@ vidinfo_t panel_info = { .vl_left_margin = 112, /* Idle cycles at the line beginning */ .vl_right_margin = 1, /* Idle cycles at the end of the line */ - .mmio = AT91SAM9263_LCDC_BASE, + .mmio = ATMEL_BASE_LCDC, }; void lcd_enable(void) { - at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */ + at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */ } void lcd_disable(void) { - at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */ + at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */ } static void otc570_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ @@ -206,8 +206,7 @@ static void otc570_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */ - writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); - gd->fb_base = CONFIG_OTC570_LCD_BASE; + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); } #ifdef CONFIG_LCD_INFO @@ -225,8 +224,7 @@ void lcd_show_board_info(void) nand_size += nand_info[i].size; lcd_printf("\n%s\n", U_BOOT_VERSION); - lcd_printf("%s CPU at %s MHz\n", CONFIG_SYS_AT91_CPU_NAME, - strmhz(temp, get_cpu_clk_rate())); + lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate())); lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); @@ -239,8 +237,9 @@ void lcd_show_board_info(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -248,7 +247,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } @@ -257,13 +256,14 @@ int checkboard(void) { char str[32]; - puts("Board: esd ARM9 HMI Panel - OTC570"); + puts("Board : esd ARM9 HMI Panel - OTC570"); if (getenv_f("serial#", str, sizeof(str)) > 0) { puts(", serial# "); puts(str); } - printf("\nHardware-revision: 1.%d\n", get_hw_rev()); - printf("Mach-type: %lu\n", gd->bd->bi_arch_number); + printf("\n"); + printf("Hardware-revision: 1.%d\n", get_hw_rev()); + printf("Mach-type : %lu\n", gd->bd->bi_arch_number); return 0; } @@ -297,12 +297,12 @@ u32 get_board_rev(void) int misc_init_r(void) { char str[64]; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_pio_output(AT91_PIO_PORTA, 29, 1); at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */ - writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); /* Set USART_MODE = 1 (RS485) */ writel(1, 0xFFF8C004); @@ -325,37 +325,49 @@ int misc_init_r(void) at91_set_pio_output(AT91_PIO_PORTA, 29, 0); } } +#ifdef CONFIG_LCD printf("Display memory address: 0x%08lX\n", gd->fb_base); +#endif return 0; } #endif /* CONFIG_MISC_INIT_R */ -int board_init(void) +int board_early_init_f(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - - /* Peripheral Clock Enable Register */ - writel( 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE | - 1 << AT91SAM9263_ID_TWI | - 1 << AT91SAM9263_ID_SPI0 | - 1 << AT91SAM9263_ID_LCDC | - 1 << AT91SAM9263_ID_UHP, + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + /* enable all clocks */ + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE) | + (1 << ATMEL_ID_TWI) | + (1 << ATMEL_ID_SPI0) | +#ifdef CONFIG_LCD + (1 << ATMEL_ID_LCDC) | +#endif + (1 << ATMEL_ID_UHP), &pmc->pcer); + at91_seriald_hw_init(); + /* arch number of OTC570-Board */ gd->bd->bi_arch_number = MACH_TYPE_OTC570; + return 0; +} + +int board_init(void) +{ + /* initialize ET1100 Controller */ + otc570_ethercat_hw_init(); + /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND otc570_nand_hw_init(); #endif - otc570_ethercat_hw_init(); #ifdef CONFIG_HAS_DATAFLASH at91_spi0_hw_init(1 << 0); #endif diff --git a/board/mimc/mimc200/config.mk b/board/mimc/mimc200/config.mk deleted file mode 100644 index ea76d05df8..0000000000 --- a/board/mimc/mimc200/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00000000 -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -PLATFORM_LDFLAGS += --gc-sections diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 470adba794..38fd35d895 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -221,8 +221,8 @@ void spi_cs_deactivate(struct spi_slave *slave) #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bi) { - macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); - macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); + macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); return 0; } diff --git a/board/mimc/mimc200/u-boot.lds b/board/mimc/mimc200/u-boot.lds deleted file mode 100644 index 0a1a8e1653..0000000000 --- a/board/mimc/mimc200/u-boot.lds +++ /dev/null @@ -1,72 +0,0 @@ -/* -*- Fundamental -*- - * - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") -OUTPUT_ARCH(avr32) -ENTRY(_start) - -SECTIONS -{ - . = 0; - _text = .; - .text : { - *(.exception.text) - *(.text) - *(.text.*) - } - _etext = .; - - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - _data = .; - .data : { - *(.data) - *(.data.*) - } - - . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { - KEEP(*(.u_boot_cmd)) - } - __u_boot_cmd_end = .; - - . = ALIGN(4); - _got = .; - .got : { - *(.got) - } - _egot = .; - - . = ALIGN(8); - _edata = .; - - .bss : { - *(.bss) - *(.bss.*) - } - . = ALIGN(8); - __bss_end__ = .; -} diff --git a/board/miromico/hammerhead/config.mk b/board/miromico/hammerhead/config.mk deleted file mode 100644 index ea76d05df8..0000000000 --- a/board/miromico/hammerhead/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00000000 -PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -PLATFORM_LDFLAGS += --gc-sections diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index 78f4fd405e..911a0b3bdd 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -29,7 +29,7 @@ #include <asm/sdram.h> #include <asm/arch/clk.h> #include <asm/arch/hmatrix.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include <asm/arch/mmu.h> #include <asm/arch/portmux.h> @@ -68,7 +68,8 @@ static const struct sdram_config sdram_config = { #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { - return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]); + return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, + bis->bi_phy_id[0]); } #endif diff --git a/board/miromico/hammerhead/u-boot.lds b/board/miromico/hammerhead/u-boot.lds deleted file mode 100644 index 0a1a8e1653..0000000000 --- a/board/miromico/hammerhead/u-boot.lds +++ /dev/null @@ -1,72 +0,0 @@ -/* -*- Fundamental -*- - * - * Copyright (C) 2005-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") -OUTPUT_ARCH(avr32) -ENTRY(_start) - -SECTIONS -{ - . = 0; - _text = .; - .text : { - *(.exception.text) - *(.text) - *(.text.*) - } - _etext = .; - - .rodata : { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - . = ALIGN(8); - _data = .; - .data : { - *(.data) - *(.data.*) - } - - . = ALIGN(4); - __u_boot_cmd_start = .; - .u_boot_cmd : { - KEEP(*(.u_boot_cmd)) - } - __u_boot_cmd_end = .; - - . = ALIGN(4); - _got = .; - .got : { - *(.got) - } - _egot = .; - - . = ALIGN(8); - _edata = .; - - .bss : { - *(.bss) - *(.bss.*) - } - . = ALIGN(8); - __bss_end__ = .; -} diff --git a/boards.cfg b/boards.cfg index 29e8d44e64..01c620ee45 100644 --- a/boards.cfg +++ b/boards.cfg @@ -74,6 +74,8 @@ omap1510inn arm arm925t - ti aspenite arm arm926ejs - Marvell armada100 afeb9260 arm arm926ejs - - at91 at91cap9adk arm arm926ejs - atmel at91 +snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 +snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M @@ -84,8 +86,10 @@ cpu9G20_128M arm arm926ejs cpu9260 eukrea cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000 top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000 -meesc arm arm926ejs - esd at91 -otc570 arm arm926ejs - esd at91 +meesc arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_NANDFLASH +meesc_dataflash arm arm926ejs meesc esd at91 meesc:AT91SAM9263,SYS_USE_DATAFLASH +otc570 arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_NANDFLASH +otc570_dataflash arm arm926ejs otc570 esd at91 otc570:AT91SAM9263,SYS_USE_DATAFLASH pm9261 arm arm926ejs - ronetix at91 pm9263 arm arm926ejs - ronetix at91 da830evm arm arm926ejs da8xxevm davinci davinci diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index c0a97bc5da..be2a0268e8 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -24,19 +24,29 @@ * MA 02111-1307 USA */ +/* + * WARNING: + * + * As the code is right now, it expects all PIO ports A,B,C,... + * to be evenly spaced in the memory map: + * ATMEL_BASE_PIOA + port * sizeof at91pio_t + * This might not necessaryly be true in future Atmel SoCs. + * This code should be fixed to use a pointer array to the ports. + */ + #include <config.h> #include <common.h> +#include <asm/io.h> #include <asm/sizes.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <asm/arch/at91_pio.h> int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (use_pullup) writel(1 << pin, &pio->port[port].puer); @@ -52,10 +62,10 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) */ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -69,10 +79,10 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -87,10 +97,10 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -106,10 +116,10 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) */ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); @@ -125,10 +135,10 @@ int at91_set_pio_input(unsigned port, u32 pin, int use_pullup) */ int at91_set_pio_output(unsigned port, u32 pin, int value) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; writel(mask, &pio->port[port].idr); writel(mask, &pio->port[port].pudr); @@ -147,10 +157,10 @@ int at91_set_pio_output(unsigned port, u32 pin, int value) */ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (is_on) writel(mask, &pio->port[port].ifer); @@ -166,10 +176,10 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) */ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (is_on) writel(mask, &pio->port[port].mder); @@ -184,10 +194,10 @@ int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on) */ int at91_set_pio_value(unsigned port, unsigned pin, int value) { - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; if (value) writel(mask, &pio->port[port].sodr); @@ -202,11 +212,11 @@ int at91_set_pio_value(unsigned port, unsigned pin, int value) */ int at91_get_pio_value(unsigned port, unsigned pin) { - u32 pdsr = 0; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + u32 pdsr = 0; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; u32 mask; - if ((port < AT91_PIO_PORTS) && (pin < 32)) { + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; pdsr = readl(&pio->port[port].pdsr) & mask; } diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c index 3946ffeebe..0af8d42611 100644 --- a/drivers/mmc/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -28,7 +28,7 @@ #include <asm/errno.h> #include <asm/byteorder.h> #include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include "atmel_mci.h" diff --git a/drivers/mmc/atmel_mci.h b/drivers/mmc/atmel_mci.h index 823a77d91b..90ab6a8a6d 100644 --- a/drivers/mmc/atmel_mci.h +++ b/drivers/mmc/atmel_mci.h @@ -238,8 +238,8 @@ typedef struct atmel_mci { * Register access macros */ #define mmci_readl(reg) \ - readl((void *)MMCI_BASE + MMCI_##reg) + readl((void *)ATMEL_BASE_MMCI + MMCI_##reg) #define mmci_writel(reg,value) \ - writel((value), (void *)MMCI_BASE + MMCI_##reg) + writel((value), (void *)ATMEL_BASE_MMCI + MMCI_##reg) #endif /* __CPU_AT32AP_ATMEL_MCI_H__ */ diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 6577925b8e..f346b244be 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -33,7 +33,7 @@ #include <asm/errno.h> #include <asm/byteorder.h> #include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include "atmel_mci.h" #ifndef CONFIG_SYS_MMC_CLK_OD diff --git a/drivers/net/macb.c b/drivers/net/macb.c index acb8d20b13..72ea1fc11d 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -469,17 +469,19 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ - defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ + defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ + defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9XE) macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else macb_writel(macb, USRIO, 0); #endif #else -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ - defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ + defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ + defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9XE) macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #else macb_writel(macb, USRIO, MACB_BIT(MII)); diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c index de8e30d0d7..ff4acb57e4 100644 --- a/drivers/rtc/at91sam9_rtt.c +++ b/drivers/rtc/at91sam9_rtt.c @@ -38,9 +38,9 @@ #include <common.h> #include <command.h> #include <rtc.h> +#include <asm/io.h> #include <asm/errno.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <asm/arch/at91_rtt.h> #include <asm/arch/at91_gpbr.h> @@ -48,8 +48,8 @@ int rtc_get (struct rtc_time *tmp) { - at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; - at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; + at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong tim; ulong tim2; ulong off; @@ -66,8 +66,8 @@ int rtc_get (struct rtc_time *tmp) int rtc_set (struct rtc_time *tmp) { - at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; - at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; + at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong tim; tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, @@ -85,8 +85,8 @@ int rtc_set (struct rtc_time *tmp) void rtc_reset (void) { - at91_rtt_t *rtt = (at91_rtt_t *) AT91_RTT_BASE; - at91_gpbr_t *gpbr = (at91_gpbr_t *) AT91_GPR_BASE; + at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; + at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; /* clear alarm, set prescaler to 32768, clear counter */ writel(32768+AT91_RTT_RTTRST, &rtt->mr); diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index bfa1f3a8d5..e326b2bcff 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -23,21 +23,7 @@ #include <asm/io.h> #include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> - -#if defined(CONFIG_USART0) -# define USART_ID 0 -# define USART_BASE USART0_BASE -#elif defined(CONFIG_USART1) -# define USART_ID 1 -# define USART_BASE USART1_BASE -#elif defined(CONFIG_USART2) -# define USART_ID 2 -# define USART_BASE USART2_BASE -#elif defined(CONFIG_USART3) -# define USART_ID 3 -# define USART_BASE USART3_BASE -#endif +#include <asm/arch/hardware.h> #include "atmel_usart.h" @@ -45,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; void serial_setbrg(void) { - atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; unsigned long divisor; unsigned long usart_hz; @@ -54,14 +40,14 @@ void serial_setbrg(void) * Baud Rate = -------------- * 16 * CD */ - usart_hz = get_usart_clk_rate(USART_ID); + usart_hz = get_usart_clk_rate(CONFIG_USART_ID); divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; writel(USART3_BF(CD, divisor), &usart->brgr); } int serial_init(void) { - atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr); @@ -80,7 +66,7 @@ int serial_init(void) void serial_putc(char c) { - atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; if (c == '\n') serial_putc('\r'); @@ -97,7 +83,7 @@ void serial_puts(const char *s) int serial_getc(void) { - atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; while (!(readl(&usart->csr) & USART3_BIT(RXRDY))) WATCHDOG_RESET(); @@ -106,6 +92,6 @@ int serial_getc(void) int serial_tstc(void) { - atmel_usart3_t *usart = (atmel_usart3_t*)USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0; } diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 4a5c4aac70..9c991e8cbc 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -21,13 +21,21 @@ #include <common.h> #ifndef CONFIG_AT91_LEGACY -#define CONFIG_AT91_LEGACY -#warning Please update to use C structur SoC access ! +# define CONFIG_ATMEL_LEGACY +# warning Please update to use C structure SoC access ! #endif -#include <asm/arch/hardware.h> +#include <common.h> +#include <spi.h> +#include <malloc.h> + +#include <asm/io.h> + #include <asm/arch/clk.h> +#include <asm/arch/hardware.h> + +#include "atmel_spi.h" + #include <asm/arch/gpio.h> -#include <asm/arch/io.h> #include <asm/arch/at91_pio.h> #include <asm/arch/at91_spi.h> @@ -41,18 +49,18 @@ void AT91F_SpiInit(void) { /* Reset the SPI */ - writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR); /* Configure SPI in Master Mode with No CS selected !!! */ writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, - AT91_BASE_SPI + AT91_SPI_MR); + ATMEL_BASE_SPI0 + AT91_SPI_MR); /* Configure CS0 */ writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(0)); + ATMEL_BASE_SPI0 + AT91_SPI_CSR(0)); #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 /* Configure CS1 */ @@ -60,7 +68,7 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(1)); + ATMEL_BASE_SPI0 + AT91_SPI_CSR(1)); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 /* Configure CS2 */ @@ -68,7 +76,7 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(2)); + ATMEL_BASE_SPI0 + AT91_SPI_CSR(2)); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 /* Configure CS3 */ @@ -76,21 +84,22 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(3)); + ATMEL_BASE_SPI0 + AT91_SPI_CSR(3)); #endif /* SPI_Enable */ - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); - while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS)); + while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS)) + ; /* * Add tempo to get SPI in a safe state. * Should not be needed for new silicon (Rev B) */ udelay(500000); - readl(AT91_BASE_SPI + AT91_SPI_SR); - readl(AT91_BASE_SPI + AT91_SPI_RDR); + readl(ATMEL_BASE_SPI0 + AT91_SPI_SR); + readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR); } @@ -100,33 +109,33 @@ void AT91F_SpiEnable(int cs) switch (cs) { case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + ATMEL_BASE_SPI0 + AT91_SPI_MR); break; case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + ATMEL_BASE_SPI0 + AT91_SPI_MR); break; case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + ATMEL_BASE_SPI0 + AT91_SPI_MR); break; case 3: - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + ATMEL_BASE_SPI0 + AT91_SPI_MR); break; } /* SPI_Enable */ - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); } unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); @@ -134,37 +143,48 @@ unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) { unsigned int timeout; + unsigned int timebase; pDesc->state = BUSY; - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, + ATMEL_BASE_SPI0 + AT91_SPI_PTCR); /* Initialize the Transmit and Receive Pointer */ - writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR); - writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR); + writel((unsigned int)pDesc->rx_cmd_pt, + ATMEL_BASE_SPI0 + AT91_SPI_RPR); + writel((unsigned int)pDesc->tx_cmd_pt, + ATMEL_BASE_SPI0 + AT91_SPI_TPR); /* Intialize the Transmit and Receive Counters */ - writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR); - writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR); + writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR); + writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR); if (pDesc->tx_data_size != 0) { /* Initialize the Next Transmit and Next Receive Pointer */ - writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR); - writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR); + writel((unsigned int)pDesc->rx_data_pt, + ATMEL_BASE_SPI0 + AT91_SPI_RNPR); + writel((unsigned int)pDesc->tx_data_pt, + ATMEL_BASE_SPI0 + AT91_SPI_TNPR); /* Intialize the Next Transmit and Next Receive Counters */ - writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR); - writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR); + writel(pDesc->rx_data_size, + ATMEL_BASE_SPI0 + AT91_SPI_RNCR); + writel(pDesc->tx_data_size, + ATMEL_BASE_SPI0 + AT91_SPI_TNCR); } /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); + timebase = get_timer(0); timeout = 0; - writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR); - while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) && - ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT)); - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, + ATMEL_BASE_SPI0 + AT91_SPI_PTCR); + while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) && + ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT)) + ; + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, + ATMEL_BASE_SPI0 + AT91_SPI_PTCR); pDesc->state = IDLE; if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) { diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index d0de931968..33e38b61b7 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -26,7 +26,7 @@ #include <asm/io.h> #include <asm/arch/clk.h> -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> #include "atmel_spi.h" @@ -48,21 +48,21 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, switch (bus) { case 0: - regs = (void *)SPI0_BASE; + regs = (void *)ATMEL_BASE_SPI0; break; -#ifdef SPI1_BASE +#ifdef ATMEL_BASE_SPI1 case 1: - regs = (void *)SPI1_BASE; + regs = (void *)ATMEL_BASE_SPI1; break; #endif -#ifdef SPI2_BASE +#ifdef ATMEL_BASE_SPI2 case 2: - regs = (void *)SPI2_BASE; + regs = (void *)ATMEL_BASE_SPI2; break; #endif -#ifdef SPI3_BASE +#ifdef ATMEL_BASE_SPI3 case 3: - regs = (void *)SPI3_BASE; + regs = (void *)ATMEL_BASE_SPI3; break; #endif default: diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 64fde68ff5..9532dd9ef6 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -25,14 +25,14 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) +#include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> int usb_cpu_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ @@ -53,11 +53,11 @@ int usb_cpu_init(void) #endif /* Enable USB host clock. */ - writel(1 << AT91_ID_UHP, &pmc->pcer); + writel(1 << ATMEL_ID_UHP, &pmc->pcer); #ifdef CONFIG_AT91SAM9261 - writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); + writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scer); #else - writel(AT91_PMC_UHP, &pmc->scer); + writel(ATMEL_PMC_UHP, &pmc->scer); #endif return 0; @@ -65,14 +65,14 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { - at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; /* Disable USB host clock. */ - writel(1 << AT91_ID_UHP, &pmc->pcdr); + writel(1 << ATMEL_ID_UHP, &pmc->pcdr); #ifdef CONFIG_AT91SAM9261 - writel(AT91_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr); + writel(ATMEL_PMC_UHP | AT91_PMC_HCK0, &pmc->scdr); #else - writel(AT91_PMC_UHP, &pmc->scdr); + writel(ATMEL_PMC_UHP, &pmc->scdr); #endif #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 25afae748d..80dad07d84 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -21,7 +21,7 @@ #include <common.h> #include <watchdog.h> #include <asm/arch/hardware.h> -#include <asm/arch/io.h> +#include <asm/io.h> #include <asm/arch/at91_wdt.h> /* @@ -42,7 +42,7 @@ static int at91_wdt_settimeout(unsigned int timeout) { unsigned int reg; - at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; + at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; /* Check if disabled */ if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { @@ -69,7 +69,7 @@ static int at91_wdt_settimeout(unsigned int timeout) void hw_watchdog_reset(void) { - at91_wdt_t *wd = (at91_wdt_t *) AT91_WDT_BASE; + at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); } diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 92491ca09d..bda6eedcf2 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -24,12 +24,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7000 1 -#define CONFIG_ATNGW100 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_ATNGW100 #define CONFIG_SYS_HZ 1000 @@ -38,8 +38,8 @@ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency * and the PBA bus to run at 1/4 the PLL frequency. */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 20000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 7 @@ -61,14 +61,14 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#define CONFIG_USART1 1 - +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -83,8 +83,8 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" @@ -95,8 +95,8 @@ * should be generated and assigned to the environment variables * "ethaddr" and "eth1addr". This is normally done during production. */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* * BOOTP/DHCP options @@ -123,25 +123,25 @@ #undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_XIMG -#define CONFIG_ATMEL_USART 1 -#define CONFIG_MACB 1 -#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO #define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 -#define CONFIG_ATMEL_SPI 1 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI +#define CONFIG_ATMEL_SPI -#define CONFIG_SPI_FLASH 1 -#define CONFIG_SPI_FLASH_ATMEL 1 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x800000 @@ -149,12 +149,13 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -172,7 +173,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 6416d17091..c17d10718d 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -24,15 +24,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7000 1 -#define CONFIG_ATSTK1002 1 -#define CONFIG_ATSTK1000 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_ATSTK1002 +#define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH 1 +#define CONFIG_ATSTK1000_EXT_FLASH /* * Timer clock frequency. We're using the CPU-internal COUNT register @@ -46,8 +46,8 @@ * PLL frequency. * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 20000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 7 @@ -85,17 +85,15 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#undef CONFIG_USART0 -#define CONFIG_USART1 1 -#undef CONFIG_USART2 -#undef CONFIG_USART3 +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -111,8 +109,8 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" @@ -123,8 +121,8 @@ * should be generated and assigned to the environment variables * "ethaddr" and "eth1addr". This is normally done during production. */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* * BOOTP options @@ -150,13 +148,13 @@ #undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_XIMG -#define CONFIG_ATMEL_USART 1 -#define CONFIG_MACB 1 -#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO #define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 @@ -175,12 +173,13 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -198,7 +197,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index a4d9b0b908..a77d52ef22 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -24,15 +24,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7001 1 -#define CONFIG_ATSTK1003 1 -#define CONFIG_ATSTK1000 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7001 +#define CONFIG_ATSTK1003 +#define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH 1 +#define CONFIG_ATSTK1000_EXT_FLASH /* * Timer clock frequency. We're using the CPU-internal COUNT register @@ -46,8 +46,8 @@ * PLL frequency. * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 20000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 7 @@ -85,17 +85,15 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#undef CONFIG_USART0 -#define CONFIG_USART1 1 -#undef CONFIG_USART2 -#undef CONFIG_USART3 +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -111,8 +109,8 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" @@ -135,11 +133,11 @@ #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_XIMG -#define CONFIG_ATMEL_USART 1 -#define CONFIG_PORTMUX_PIO 1 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 +#define CONFIG_ATMEL_USART +#define CONFIG_PORTMUX_PIO +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 @@ -158,12 +156,13 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -180,7 +179,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 06bb5da8a3..cc00a0a665 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -24,15 +24,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7002 1 -#define CONFIG_ATSTK1004 1 -#define CONFIG_ATSTK1000 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7002 +#define CONFIG_ATSTK1004 +#define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH 1 +#define CONFIG_ATSTK1000_EXT_FLASH /* * Timer clock frequency. We're using the CPU-internal COUNT register @@ -46,8 +46,8 @@ * PLL frequency. * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 20000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 7 @@ -85,17 +85,15 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#undef CONFIG_USART0 -#define CONFIG_USART1 1 -#undef CONFIG_USART2 -#undef CONFIG_USART3 +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -111,8 +109,8 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" @@ -135,11 +133,11 @@ #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_XIMG -#define CONFIG_ATMEL_USART 1 -#define CONFIG_PORTMUX_PIO 1 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 +#define CONFIG_ATMEL_USART +#define CONFIG_PORTMUX_PIO +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 @@ -158,12 +156,13 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -180,7 +179,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index d3cbee6b63..2cff140d44 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -24,15 +24,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7000 1 -#define CONFIG_ATSTK1006 1 -#define CONFIG_ATSTK1000 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_ATSTK1006 +#define CONFIG_ATSTK1000 -#define CONFIG_ATSTK1000_EXT_FLASH 1 +#define CONFIG_ATSTK1000_EXT_FLASH /* * Timer clock frequency. We're using the CPU-internal COUNT register @@ -46,8 +46,8 @@ * PLL frequency. * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 20000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 7 @@ -85,17 +85,15 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#undef CONFIG_USART0 -#define CONFIG_USART1 1 -#undef CONFIG_USART2 -#undef CONFIG_USART3 +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -111,8 +109,8 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" @@ -123,8 +121,8 @@ * should be generated and assigned to the environment variables * "ethaddr" and "eth1addr". This is normally done during production. */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* * BOOTP options @@ -150,13 +148,13 @@ #undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_XIMG -#define CONFIG_ATMEL_USART 1 -#define CONFIG_MACB 1 -#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO #define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 @@ -175,12 +173,13 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -198,7 +197,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000) diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 1c381c76b8..4c30b39bdf 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -22,14 +22,14 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7000 1 -#define CONFIG_FAVR32_EZKIT 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_FAVR32_EZKIT -#define CONFIG_FAVR32_EZKIT_EXT_FLASH 1 +#define CONFIG_FAVR32_EZKIT_EXT_FLASH /* * Timer clock frequency. We're using the CPU-internal COUNT register @@ -43,8 +43,8 @@ * PLL frequency. * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 20000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 7 @@ -82,17 +82,15 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 +#define CONFIG_USART_BASE ATMEL_BASE_USART3 +#define CONFIG_USART_ID 3 /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -108,8 +106,8 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" @@ -120,8 +118,8 @@ * should be generated and assigned to the environment variables * "ethaddr" and "eth1addr". This is normally done during production. */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* * BOOTP options @@ -147,13 +145,13 @@ #undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_XIMG -#define CONFIG_ATMEL_USART 1 -#define CONFIG_MACB 1 -#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO #define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 @@ -172,12 +170,13 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -195,7 +194,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index 8ca04ea480..bfdfc0a8c5 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -24,10 +24,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7000 1 -#define CONFIG_HAMMERHEAD 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_HAMMERHEAD #define CONFIG_SYS_HZ 1000 @@ -36,8 +36,8 @@ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency * and the PBA bus to run at 1/4 the PLL frequency. */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 25000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 5 @@ -59,16 +59,17 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#define CONFIG_USART1 1 +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 #define CONFIG_HOSTNAME hammerhead /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -83,8 +84,8 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 1 -#define CONFIG_AUTOBOOT 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT \ "Press SPACE to abort autoboot in %d seconds\n", bootdelay #define CONFIG_AUTOBOOT_DELAY_STR "d" @@ -95,8 +96,8 @@ * should be generated and assigned to the environment variables * "ethaddr". This is normally done during production. */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* * BOOTP/DHCP options @@ -118,21 +119,21 @@ #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_SETGETDCR -#define CONFIG_ATMEL_USART 1 -#define CONFIG_MACB 1 -#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO #define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI #define CONFIG_SYS_DCACHE_LINESZ 32 #define CONFIG_SYS_ICACHE_LINESZ 32 #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x800000 @@ -140,13 +141,14 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE 0x24000000 #define CONFIG_SYS_INTRAM_SIZE 0x8000 #define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -165,7 +167,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 16e2ec62ee..6c5276920d 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -24,14 +24,14 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/memory-map.h> +#include <asm/arch/hardware.h> -#define CONFIG_AVR32 1 -#define CONFIG_AT32AP 1 -#define CONFIG_AT32AP7000 1 -#define CONFIG_MIMC200 1 +#define CONFIG_AVR32 +#define CONFIG_AT32AP +#define CONFIG_AT32AP7000 +#define CONFIG_MIMC200 -#define CONFIG_MIMC200_EXT_FLASH 1 +#define CONFIG_MIMC200_EXT_FLASH #define CONFIG_SYS_HZ 1000 @@ -40,8 +40,8 @@ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency * and the PBA bus to run at 1/4 the PLL frequency. */ -#define CONFIG_PLL 1 -#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_PLL +#define CONFIG_SYS_POWER_MANAGER #define CONFIG_SYS_OSC0_HZ 10000000 #define CONFIG_SYS_PLL0_DIV 1 #define CONFIG_SYS_PLL0_MUL 15 @@ -63,15 +63,17 @@ */ #define CONFIG_SYS_PLL0_OPT 0x04 -#define CONFIG_USART1 1 +#define CONFIG_USART_BASE ATMEL_BASE_USART1 +#define CONFIG_USART_ID 1 + #define CONFIG_MIMC200_DBGLINK 1 /* User serviceable stuff */ -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_DOS_PARTITION -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_STACKSIZE (2048) @@ -81,9 +83,9 @@ #define CONFIG_BOOTCOMMAND \ "fsload boot/uImage; bootm" -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ -#define CONFIG_DISABLE_CONSOLE 1 /* disable console */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CONFIG_SILENT_CONSOLE /* enable silent startup */ +#define CONFIG_DISABLE_CONSOLE /* disable console */ +#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */ #define CONFIG_LCD 1 @@ -92,16 +94,16 @@ * data on the serial line may interrupt the boot sequence. */ #define CONFIG_BOOTDELAY 0 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 -#define CONFIG_AUTOBOOT 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT /* * After booting the board for the first time, new ethernet addresses * should be generated and assigned to the environment variables * "ethaddr" and "eth1addr". This is normally done during production. */ -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_NET_MULTI /* * BOOTP/DHCP options @@ -122,13 +124,13 @@ #define CONFIG_CMD_MMC #define CONFIG_CMD_NET -#define CONFIG_ATMEL_USART 1 -#define CONFIG_MACB 1 -#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_ATMEL_USART +#define CONFIG_MACB +#define CONFIG_PORTMUX_PIO #define CONFIG_SYS_NR_PIOS 5 -#define CONFIG_SYS_HSDRAMC 1 -#define CONFIG_MMC 1 -#define CONFIG_ATMEL_MCI 1 +#define CONFIG_SYS_HSDRAMC +#define CONFIG_MMC +#define CONFIG_ATMEL_MCI #if defined(CONFIG_LCD) #define CONFIG_CMD_BMP @@ -149,8 +151,8 @@ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_BASE 0x00000000 #define CONFIG_SYS_FLASH_SIZE 0x800000 @@ -158,6 +160,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE @@ -166,7 +169,7 @@ #define CONFIG_SYS_FRAM_BASE 0x08000000 #define CONFIG_SYS_FRAM_SIZE 0x20000 -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SIZE 65536 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) @@ -184,7 +187,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) diff --git a/include/configs/otc570.h b/include/configs/otc570.h index ca3bf26215..9ecb2b0f35 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2010-2011 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -31,101 +31,119 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* Common stuff */ -#define CONFIG_OTC570 1 /* Board is esd OTC570 */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include <asm/hardware.h> + +/* + * Warning: changing CONFIG_SYS_TEXT_BASE requires + * adapting the initial boot program. + * Since the linker has to swallow that define, we must use a pure + * hex number here! + */ +#define CONFIG_SYS_TEXT_BASE 0x20002000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ #define CONFIG_SYS_HZ 1000 /* decrementer freq */ -#define CONFIG_DISPLAY_BOARDINFO 1 -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ -#define CONFIG_PREBOOT /* enable preboot variable */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_SERIAL_TAG 1 -#define CONFIG_REVISION_TAG 1 -#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ +/* Misc CPU related */ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - #define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ + +#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */ +#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ +#define CONFIG_PREBOOT /* enable preboot variable */ /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 + +/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO /* Console output */ -#define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600} #define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* LCD */ -#define CONFIG_LCD 1 -#define LCD_BPP LCD_COLOR8 - +#define CONFIG_LCD #undef CONFIG_SPLASH_SCREEN -#ifndef CONFIG_SPLASH_SCREEN -#define CONFIG_LCD_LOGO 1 -#define CONFIG_LCD_INFO 1 -#undef CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SPLASH_SCREEN */ +#ifdef CONFIG_LCD +# define LCD_BPP LCD_COLOR8 + +# ifndef CONFIG_SPLASH_SCREEN +# define CONFIG_LCD_LOGO +# define CONFIG_LCD_INFO +# undef CONFIG_LCD_INFO_BELOW_LOGO +# endif /* CONFIG_SPLASH_SCREEN */ -#undef LCD_TEST_PATTERN -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_OTC570_LCD_BASE 0x23E00000 /* LCD is in SDRAM */ -#define CONFIG_CMD_BMP 1 +# undef LCD_TEST_PATTERN +# define CONFIG_SYS_WHITE_ON_BLACK +# define CONFIG_ATMEL_LCD +# define CONFIG_SYS_CONSOLE_IS_IN_ENV +# define CONFIG_OTC570_LCD_BASE (CONFIG_SYS_SDRAM_BASE + 0x03fa5000) +# define CONFIG_CMD_BMP +#endif /* CONFIG_LCD */ /* RTC and I2C stuff */ -#define CONFIG_RTC_DS1338 1 +#define CONFIG_RTC_DS1338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C 1 +#define CONFIG_SOFT_I2C #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7F #ifdef CONFIG_SOFT_I2C -#define CONFIG_I2C_CMD_TREE 1 -#define CONFIG_I2C_MULTI_BUS 1 +# define CONFIG_I2C_CMD_TREE +# define CONFIG_I2C_MULTI_BUS /* Configure data and clock pins for pio */ -#define I2C_INIT { \ +# define I2C_INIT { \ at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \ at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \ } -#define I2C_SOFT_DECLARATIONS +# define I2C_SOFT_DECLARATIONS /* Configure data pin as output */ -#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0) +# define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0) /* Configure data pin as input */ -#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0) +# define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0) /* Read data pin */ -#define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4) +# define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4) /* Set data pin */ -#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit) +# define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit) /* Set clock pin */ -#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit) -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +# define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit) +# define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 - /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -135,99 +153,116 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 -#define CONFIG_CMD_I2C 1 -#define CONFIG_CMD_DATE 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE /* LED */ -#define CONFIG_AT91_LED 1 +#define CONFIG_AT91_LED -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */ +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) + +/* + * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, + * leaving the correct space for initial global data structure above + * that address while providing maximum stack area below. + */ +#define CONFIG_SYS_INIT_SP_ADDR \ + (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE) /* DataFlash */ -#define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ -#define AT91_SPI_CLK 15000000 -#define DATAFLASH_TCSS (0x1a << 16) -#define DATAFLASH_TCHS (0x1 << 24) +#ifdef CONFIG_SYS_USE_DATAFLASH +# define CONFIG_ATMEL_DATAFLASH_SPI +# define CONFIG_HAS_DATAFLASH +# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +# define AT91_SPI_CLK 15000000 +# define DATAFLASH_TCSS (0x1a << 16) +# define DATAFLASH_TCHS (0x1 << 24) +#endif /* NOR flash is not populated, disable it */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +# define CONFIG_NAND_ATMEL +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */ +# define CONFIG_SYS_NAND_DBW_8 +# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 +# define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_FIT #define CONFIG_NET_RETRY_COUNT 20 #undef CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#define CONFIG_SYS_USE_DATAFLASH 1 -#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT /* CAN */ -#define CONFIG_AT91_CAN 1 +#define CONFIG_AT91_CAN /* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 +#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */ + +#ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_DATAFLASH 1 -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ +# define CONFIG_ENV_IS_IN_DATAFLASH +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ 0x8400) -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ +# define CONFIG_ENV_OFFSET 0x4200 +# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4200 +# define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#elif CONFIG_SYS_USE_NANDFLASH + +/* bootstrap + u-boot + env + linux in nandflash */ +# define CONFIG_ENV_IS_IN_NAND 1 +# define CONFIG_ENV_OFFSET 0xC0000 +# define CONFIG_ENV_SIZE 0x20000 + +#endif #define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING /* * Size of malloc() pool @@ -238,7 +273,7 @@ #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported +# error CONFIG_USE_IRQ not supported #endif #endif diff --git a/include/dataflash.h b/include/dataflash.h index 63b3bf9634..96ac0975a6 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -34,7 +34,6 @@ #define _DataFlash_h -#include <asm/arch/hardware.h> #include "config.h" /*number of protected area*/ |