diff options
203 files changed, 11520 insertions, 8906 deletions
@@ -42,13 +42,13 @@ $(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild # 2) Generate asm-offsets.h # -ifneq ($(wildcard $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c),) +ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),) offsets-file := include/generated/asm-offsets.h endif always += $(offsets-file) targets += $(offsets-file) -targets += $(CPUDIR)/$(SOC)/asm-offsets.s +targets += arch/$(ARCH)/lib/asm-offsets.s # Default sed regexp - multiline due to syntax constraints @@ -79,9 +79,9 @@ define cmd_offsets endef # We use internal kbuild rules to avoid the "is up to date" message from make -$(CPUDIR)/$(SOC)/asm-offsets.s: $(CPUDIR)/$(SOC)/asm-offsets.c FORCE +arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cc_s_c) -$(obj)/$(offsets-file): $(CPUDIR)/$(SOC)/asm-offsets.s +$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild $(call cmd,offsets) @@ -8,7 +8,7 @@ VERSION = 2014 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = NAME = # *DOCUMENTATION* @@ -124,7 +124,8 @@ ifneq ($(KBUILD_OUTPUT),) # Invoke a second make in the output directory, passing relevant variables # check that the output directory actually exists saved-output := $(KBUILD_OUTPUT) -KBUILD_OUTPUT := $(shell cd $(KBUILD_OUTPUT) && /bin/pwd) +KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \ + && /bin/pwd) $(if $(KBUILD_OUTPUT),, \ $(error output directory "$(saved-output)" does not exist)) @@ -408,7 +409,7 @@ timestamp_h := include/generated/timestamp_autogenerated.h no-dot-config-targets := clean clobber mrproper distclean \ help %docs check% coccicheck \ - ubootversion backup + ubootversion backup tools-only config-targets := 0 mixed-targets := 0 @@ -728,7 +729,7 @@ endif quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ -quiet_cmd_mkimage = UIMAGE $@ +quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) @@ -749,6 +750,9 @@ dtbs dts/dt.dtb: checkdtc u-boot u-boot-dtb.bin: u-boot.bin dts/dt.dtb FORCE $(call if_changed,cat) +%.imx: %.bin + $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ + quiet_cmd_copy = COPY $@ cmd_copy = cp $< $@ @@ -802,9 +806,6 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE $(call if_changed,mkimage) -u-boot.imx: u-boot.bin - $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ - u-boot.sha1: u-boot.bin tools/ubsha1 u-boot.bin @@ -848,6 +849,8 @@ OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE) u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE $(call if_changed,pad_cat) +u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin + $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot-signed.sb u-boot.sb: u-boot.bin spl/u-boot-spl.bin $(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb @@ -1050,11 +1053,11 @@ depend dep: # --------------------------------------------------------------------------- quiet_cmd_cpp_lds = LDS $@ -cmd_cpp_lds = $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ \ - -x assembler-with-cpp -P -o $@ $< +cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ + -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< u-boot.lds: $(LDSCRIPT) prepare FORCE - $(call if_changed,cpp_lds) + $(call if_changed_dep,cpp_lds) PHONY += nand_spl nand_spl: prepare @@ -1127,6 +1130,9 @@ checkarmreloc: u-boot env: scripts_basic $(Q)$(MAKE) $(build)=tools/$@ +tools-only: scripts_basic $(version_h) $(timestamp_h) + $(Q)$(MAKE) $(build)=tools + tools-all: export HOST_TOOLS_ALL=y tools-all: env tools ; @@ -1172,7 +1178,7 @@ MRPROPER_FILES += .config .config.old \ clean: rm-dirs := $(CLEAN_DIRS) clean: rm-files := $(CLEAN_FILES) -clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $f/Makefile),$f)) +clean-dirs := $(foreach f,$(u-boot-alldirs),$(if $(wildcard $(srctree)/$f/Makefile),$f)) clean-dirs := $(addprefix _clean_, $(clean-dirs) doc/DocBook) @@ -566,6 +566,8 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 + CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_761320 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the @@ -1013,7 +1015,7 @@ The following options need to be configured: CONFIG_CMD_CDP * Cisco Discover Protocol support CONFIG_CMD_MFSL * Microblaze FSL support CONFIG_CMD_XIMG Load part of Multi Image - + CONFIG_CMD_UUID * Generate random UUID or GUID string EXAMPLE: If you want all functions except of network support you can write: @@ -1526,6 +1528,16 @@ The following options need to be configured: this to the maximum filesize (in bytes) for the buffer. Default is 4 MiB if undefined. + DFU_DEFAULT_POLL_TIMEOUT + Poll timeout [ms], is the timeout a device can send to the + host. The host must wait for this timeout before sending + a subsequent DFU_GET_STATUS request to the device. + + DFU_MANIFEST_POLL_TIMEOUT + Poll timeout [ms], which the device sends to the host when + entering dfuMANIFEST state. Host waits this timeout, before + sending again an USB request to the device. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV diff --git a/arch/arm/config.mk b/arch/arm/config.mk index f4c2d81044..66ecc2ee4d 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := arm-linux- -endif - ifndef CONFIG_STANDALONE_LOAD_ADDR ifneq ($(CONFIG_OMAP_COMMON),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 @@ -126,6 +122,10 @@ ifndef CONFIG_SPL_BUILD ALL-y += SPL endif else +ifeq ($(CONFIG_OF_SEPARATE),y) +ALL-y += u-boot-dtb.imx +else ALL-y += u-boot.imx endif endif +endif diff --git a/arch/arm/cpu/arm1136/mx35/asm-offsets.c b/arch/arm/cpu/arm1136/mx35/asm-offsets.c deleted file mode 100644 index ebd7575039..0000000000 --- a/arch/arm/cpu/arm1136/mx35/asm-offsets.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/imx-regs.h> - -#include <linux/kbuild.h> - -int main(void) -{ - /* Round up to make sure size gives nice stack alignment */ - DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); - DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); - DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); - DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); - DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); - DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); - DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); - DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); - DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); - DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); - DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); - DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); - DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); - DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); - DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); - DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); - DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); - DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); - DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); - DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); - DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c b/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c deleted file mode 100644 index 5fe8fa204b..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/asm-offsets.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/mb86r0x.h> - -#include <linux/kbuild.h> - -int main(void) -{ - /* ddr2 controller */ - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); - - /* clock reset generator */ - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); - - /* chip control module */ - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); - - /* external bus interface */ - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c deleted file mode 100644 index 0e2e8bf64e..0000000000 --- a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/imx-regs.h> - -#include <linux/kbuild.h> - -int main(void) -{ - /* Clock Control Module */ - DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); - DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); - DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); - DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); - DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); - DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); - - /* Enhanced SDRAM Controller */ - DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); - DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); - DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); - - /* Multi-Layer AHB Crossbar Switch */ - DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); - DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); - DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); - DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); - DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); - DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); - DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); - DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); - DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); - DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); - DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); - DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); - DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); - DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); - DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); - - /* AHB <-> IP-Bus Interface */ - DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); - DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c deleted file mode 100644 index 629b727745..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/imx-regs.h> - -#include <linux/kbuild.h> - -int main(void) -{ - DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); - DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); - - DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); - DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); - DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); - DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); - DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); - DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); - DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); - - DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); - DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); - DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); - DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); - DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); - - DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, gpcr)); - DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, fmcr)); - - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 1eee66111c..6c59494558 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -17,9 +17,69 @@ endif MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg -quiet_cmd_mkimage_mxs = UIMAGE $@ +# Generate HAB-capable IVT +# +# Note on computing the post-IVT size field value for the U-Boot binary. +# The value is the result of adding the following: +# -> The size of U-Boot binary aligned to 64B (u-boot.bin) +# -> The size of IVT block aligned to 64B (u-boot.ivt) +# -> The size of U-Boot signature (u-boot.sig), 3904 B +# -> The 64B hole in front of U-Boot binary for 'struct mxs_spl_data' passing +# +quiet_cmd_mkivt_mxs = MXSIVT $@ +cmd_mkivt_mxs = \ + sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \ + echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \ + tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \ + sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@ + +# Align binary to 64B +quiet_cmd_mkalign_mxs = MXSALGN $@ +cmd_mkalign_mxs = \ + dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \ + mv $@ $^ + +# Assemble the CSF file +quiet_cmd_mkcsfreq_mxs = MXSCSFR $@ +cmd_mkcsfreq_mxs = \ + ivt=$(word 1,$^) ; \ + bin=$(word 2,$^) ; \ + csf=$(word 3,$^) ; \ + sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \ + sed '/^\#\#Blocks/ d' > $@ ; \ + echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \ + echo " $3 0x0 0x40 \"$$ivt\"" >> $@ + +# Sign files +quiet_cmd_mkcst_mxs = MXSCST $@ +cmd_mkcst_mxs = cst -o $@ < $^ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) + +spl/u-boot-spl.ivt: spl/u-boot-spl.bin + $(call if_changed,mkalign_mxs) + $(call if_changed,mkivt_mxs,$(CONFIG_SPL_TEXT_BASE),\ + 0x00008000,0x00008040) + +u-boot.ivt: u-boot.bin + $(call if_changed,mkalign_mxs) + $(call if_changed,mkivt_mxs,$(CONFIG_SYS_TEXT_BASE),\ + 0x40001000,0x40001040) + +spl/u-boot-spl.csf: spl/u-boot-spl.ivt spl/u-boot-spl.bin board/$(VENDOR)/$(BOARD)/sign/u-boot-spl.csf + $(call if_changed,mkcsfreq_mxs,$(CONFIG_SPL_TEXT_BASE),0x8000) + +u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf + $(call if_changed,mkcsfreq_mxs,$(CONFIG_SYS_TEXT_BASE),0x40001000) + +%.sig: %.csf + $(call if_changed,mkcst_mxs) + +quiet_cmd_mkimage_mxs = MKIMAGE $@ cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE $(call if_changed,mkimage_mxs) + +u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE + $(call if_changed,mkimage_mxs) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg new file mode 100644 index 0000000000..1520bba3fb --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg @@ -0,0 +1,10 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x1000 spl/u-boot-spl.bin + LOAD 0x8000 spl/u-boot-spl.ivt + LOAD 0x8040 spl/u-boot-spl.sig + CALL HAB 0x8000 0x0 + LOAD 0x40002000 u-boot.bin + LOAD 0x40001000 u-boot.ivt + LOAD 0x40001040 u-boot.sig + CALL HAB 0x40001000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 811876736c..55510e9cd8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,6 +1,6 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin - CALL 0x14 0x0 - LOAD 0x40000100 u-boot.bin - CALL 0x40000100 0x0 + LOAD 0x1000 spl/u-boot-spl.bin + CALL 0x1000 0x0 + LOAD 0x40002000 u-boot.bin + CALL 0x40002000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index ea772f0c86..bb78cb0c84 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,8 +1,8 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin - LOAD IVT 0x8000 0x14 + LOAD 0x1000 spl/u-boot-spl.bin + LOAD IVT 0x8000 0x1000 CALL HAB 0x8000 0x0 - LOAD 0x40000100 u-boot.bin - LOAD IVT 0x8000 0x40000100 + LOAD 0x40002000 u-boot.bin + LOAD IVT 0x8000 0x40002000 CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 68c30afc48..d3e136991a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -13,9 +13,16 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> +#include <linux/compiler.h> #include "mxs_init.h" +DECLARE_GLOBAL_DATA_PTR; +static gd_t gdata __section(".data"); +#ifdef CONFIG_SPL_SERIAL_SUPPORT +static bd_t bdata __section(".data"); +#endif + /* * This delay function is intended to be used only in early stage of boot, where * clock are not set up yet. The timer used here is reset on every boot and @@ -102,6 +109,28 @@ static uint8_t mxs_get_bootmode_index(void) return i; } +static void mxs_spl_fixup_vectors(void) +{ + /* + * Copy our vector table to 0x0, since due to HAB, we cannot + * be loaded to 0x0. We want to have working vectoring though, + * thus this fixup. Our vectoring table is PIC, so copying is + * fine. + */ + extern uint32_t _start; + memcpy(0x0, &_start, 0x60); +} + +static void mxs_spl_console_init(void) +{ +#ifdef CONFIG_SPL_SERIAL_SUPPORT + gd->bd = &bdata; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#endif +} + void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, const iomux_cfg_t *iomux_setup, const unsigned int iomux_size) @@ -109,8 +138,14 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, struct mxs_spl_data *data = (struct mxs_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); uint8_t bootmode = mxs_get_bootmode_index(); + gd = &gdata; + + mxs_spl_fixup_vectors(); mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size); + + mxs_spl_console_init(); + mxs_power_init(); mxs_mem_init(); diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index d0b482d615..f4bf8ac1dd 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -16,7 +16,7 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; + . = CONFIG_SPL_TEXT_BASE; . = ALIGN(4); .text : diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 2b15a64667..fb44cc8290 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -202,6 +202,7 @@ static void watchdog_disable(void) } #endif +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) void s_init(void) { /* @@ -220,22 +221,19 @@ void s_init(void) #ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) watchdog_disable(); timer_init(); set_uart_mux_conf(); setup_clocks_for_console(); uart_soft_reset(); -#endif #ifdef CONFIG_NOR_BOOT gd->baudrate = CONFIG_BAUDRATE; serial_init(); gd->have_console = 1; -#else +#elif defined(CONFIG_SPL_BUILD) gd = &gdata; preloader_console_init(); #endif -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) prcm_init(); set_mux_conf_regs(); #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) @@ -243,8 +241,8 @@ void s_init(void) rtc32k_enable(); #endif sdram_init(); -#endif } +#endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 645c497370..9edb47502c 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -39,6 +39,9 @@ static void exynos5_uart_config(int peripheral) start = 4; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } for (i = start; i < start + count; i++) { s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); @@ -74,6 +77,9 @@ static void exynos5420_uart_config(int peripheral) start = 4; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } for (i = start; i < start + count; i++) { @@ -110,6 +116,9 @@ static int exynos5_mmc_config(int peripheral, int flags) bank = &gpio1->c4; bank_ext = NULL; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode", @@ -683,6 +692,9 @@ static void exynos4_uart_config(int peripheral) start = 4; count = 2; break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; } for (i = start; i < start + count; i++) { s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); @@ -741,6 +753,21 @@ int exynos_pinmux_config(int peripheral, int flags) } #ifdef CONFIG_OF_CONTROL +static int exynos4_pinmux_decode_periph_id(const void *blob, int node) +{ + int err; + u32 cell[3]; + + err = fdtdec_get_int_array(blob, node, "interrupts", cell, + ARRAY_SIZE(cell)); + if (err) { + debug(" invalid peripheral id\n"); + return PERIPH_ID_NONE; + } + + return cell[1]; +} + static int exynos5_pinmux_decode_periph_id(const void *blob, int node) { int err; @@ -758,6 +785,8 @@ int pinmux_decode_periph_id(const void *blob, int node) { if (cpu_is_exynos5()) return exynos5_pinmux_decode_periph_id(blob, node); + else if (cpu_is_exynos4()) + return exynos4_pinmux_decode_periph_id(blob, node); else return PERIPH_ID_NONE; } diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c deleted file mode 100644 index ddb1898f36..0000000000 --- a/arch/arm/cpu/armv7/mx5/asm-offsets.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * This program is used to generate definitions needed by - * assembly language modules. - * - * We use the technique used in the OSF Mach kernel code: - * generate asm statements containing #defines, - * compile this file to assembler, and then extract the - * #defines from the assembly-language output. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/imx-regs.h> - -#include <linux/kbuild.h> - -int main(void) -{ - - /* Round up to make sure size gives nice stack alignment */ - DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); - DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); - DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); - DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); - DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); - DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); - DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); - DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); - DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); - DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); - DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); - DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); - DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); - DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); - DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); - DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); - DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); - DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); - DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); - DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); - DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); - DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); - DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); - DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); - DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); - DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); - DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); - DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); - DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); - DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); - DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); - DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); - DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); - DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); -#if defined(CONFIG_MX53) - DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); -#endif - - /* DPLL */ - DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); - DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); - DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); - DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); - DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); - DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); - DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); - DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); - - return 0; -} diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3e84a0c9f9..cbe1d406df 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -8,5 +8,5 @@ # obj-y := lowlevel_init.o -obj-y += misc.o timer.o reset_manager.o system_manager.o +obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c new file mode 100644 index 0000000000..23d697dee2 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> + +static const struct socfpga_clock_manager *clock_manager_base = + (void *)SOCFPGA_CLKMGR_ADDRESS; + +#define CLKMGR_BYPASS_ENABLE 1 +#define CLKMGR_BYPASS_DISABLE 0 +#define CLKMGR_STAT_IDLE 0 +#define CLKMGR_STAT_BUSY 1 +#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0 +#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1 +#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0 +#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1 + +#define CLEAR_BGP_EN_PWRDN \ + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ + CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) + +#define VCO_EN_BASE \ + (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ + CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ + CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) + +static inline void cm_wait_for_lock(uint32_t mask) +{ + register uint32_t inter_val; + do { + inter_val = readl(&clock_manager_base->inter) & mask; + } while (inter_val != mask); +} + +/* function to poll in the fsm busy bit */ +static inline void cm_wait_for_fsm(void) +{ + while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) + ; +} + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static inline void cm_write_bypass(uint32_t val) +{ + writel(val, &clock_manager_base->bypass); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static inline void cm_write_ctrl(uint32_t val) +{ + writel(val, &clock_manager_base->ctrl); + cm_wait_for_fsm(); +} + +/* function to write a clock register that has phase information */ +static inline void cm_write_with_phase(uint32_t value, + uint32_t reg_address, uint32_t mask) +{ + /* poll until phase is zero */ + while (readl(reg_address) & mask) + ; + + writel(value, reg_address); + + while (readl(reg_address) & mask) + ; +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + * + * Start by being paranoid and gate all sw managed clocks + * Put all plls in bypass + * Put all plls VCO registers back to reset value (bandgap power down). + * Put peripheral and main pll src to reset value to avoid glitch. + * Delay 5 us. + * Deassert bandgap power down and set numerator and denominator + * Start 7 us timer. + * set internal dividers + * Wait for 7 us timer. + * Enable plls + * Set external dividers while plls are locking + * Wait for pll lock + * Assert/deassert outreset all. + * Take all pll's out of bypass + * Clear safe mode + * set source main and peripheral clocks + * Ungate clocks + */ + +void cm_basic_init(const cm_config_t *cfg) +{ + uint32_t start, timeout; + + /* Start by being paranoid and gate all sw managed clocks */ + + /* + * We need to disable nandclk + * and then do another apb access before disabling + * gatting off the rest of the periperal clocks. + */ + writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & + readl(&clock_manager_base->per_pll_en), + &clock_manager_base->per_pll_en); + + /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ + writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | + CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | + CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, + &clock_manager_base->main_pll_en); + + writel(0, &clock_manager_base->sdr_pll_en); + + /* now we can gate off the rest of the peripheral clocks */ + writel(0, &clock_manager_base->per_pll_en); + + /* Put all plls in bypass */ + cm_write_bypass( + CLKMGR_BYPASS_PERPLLSRC_SET( + CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_SDRPLLSRC_SET( + CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) | + CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) | + CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE)); + + /* + * Put all plls VCO registers back to reset value. + * Some code might have messed with them. + */ + writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE, + &clock_manager_base->main_pll_vco); + writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE, + &clock_manager_base->per_pll_vco); + writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE, + &clock_manager_base->sdr_pll_vco); + + /* + * The clocks to the flash devices and the L4_MAIN clocks can + * glitch when coming out of safe mode if their source values + * are different from their reset value. So the trick it to + * put them back to their reset state, and change input + * after exiting safe mode but before ungating the clocks. + */ + writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, + &clock_manager_base->per_pll_src); + writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, + &clock_manager_base->main_pll_l4src); + + /* read back for the required 5 us delay. */ + readl(&clock_manager_base->main_pll_vco); + readl(&clock_manager_base->per_pll_vco); + readl(&clock_manager_base->sdr_pll_vco); + + + /* + * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN + * with numerator and denominator. + */ + writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN | + CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->main_pll_vco); + + writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN | + CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->per_pll_vco); + + writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | + cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN | + CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->sdr_pll_vco); + + /* + * Time starts here + * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) + */ + reset_timer(); + start = get_timer(0); + /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ + timeout = 7; + + /* main mpu */ + writel(cfg->mpuclk, &clock_manager_base->main_pll_mpuclk); + + /* main main clock */ + writel(cfg->mainclk, &clock_manager_base->main_pll_mainclk); + + /* main for dbg */ + writel(cfg->dbgatclk, &clock_manager_base->main_pll_dbgatclk); + + /* main for cfgs2fuser0clk */ + writel(cfg->cfg2fuser0clk, + &clock_manager_base->main_pll_cfgs2fuser0clk); + + /* Peri emac0 50 MHz default to RMII */ + writel(cfg->emac0clk, &clock_manager_base->per_pll_emac0clk); + + /* Peri emac1 50 MHz default to RMII */ + writel(cfg->emac1clk, &clock_manager_base->per_pll_emac1clk); + + /* Peri QSPI */ + writel(cfg->mainqspiclk, &clock_manager_base->main_pll_mainqspiclk); + + writel(cfg->perqspiclk, &clock_manager_base->per_pll_perqspiclk); + + /* Peri pernandsdmmcclk */ + writel(cfg->pernandsdmmcclk, + &clock_manager_base->per_pll_pernandsdmmcclk); + + /* Peri perbaseclk */ + writel(cfg->perbaseclk, &clock_manager_base->per_pll_perbaseclk); + + /* Peri s2fuser1clk */ + writel(cfg->s2fuser1clk, &clock_manager_base->per_pll_s2fuser1clk); + + /* 7 us must have elapsed before we can enable the VCO */ + while (get_timer(start) < timeout) + ; + + /* Enable vco */ + /* main pll vco */ + writel(cfg->main_vco_base | VCO_EN_BASE, + &clock_manager_base->main_pll_vco); + + /* periferal pll */ + writel(cfg->peri_vco_base | VCO_EN_BASE, + &clock_manager_base->per_pll_vco); + + /* sdram pll vco */ + writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | + cfg->sdram_vco_base | VCO_EN_BASE, + &clock_manager_base->sdr_pll_vco); + + /* L3 MP and L3 SP */ + writel(cfg->maindiv, &clock_manager_base->main_pll_maindiv); + + writel(cfg->dbgdiv, &clock_manager_base->main_pll_dbgdiv); + + writel(cfg->tracediv, &clock_manager_base->main_pll_tracediv); + + /* L4 MP, L4 SP, can0, and can1 */ + writel(cfg->perdiv, &clock_manager_base->per_pll_div); + + writel(cfg->gpiodiv, &clock_manager_base->per_pll_gpiodiv); + +#define LOCKED_MASK \ + (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ + CLKMGR_INTER_PERPLLLOCKED_MASK | \ + CLKMGR_INTER_MAINPLLLOCKED_MASK) + + cm_wait_for_lock(LOCKED_MASK); + + /* write the sdram clock counters before toggling outreset all */ + writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll_ddrdqsclk); + + writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll_ddr2xdqsclk); + + writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, + &clock_manager_base->sdr_pll_ddrdqclk); + + writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, + &clock_manager_base->sdr_pll_s2fuser2clk); + + /* + * after locking, but before taking out of bypass + * assert/deassert outresetall + */ + uint32_t mainvco = readl(&clock_manager_base->main_pll_vco); + + /* assert main outresetall */ + writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll_vco); + + uint32_t periphvco = readl(&clock_manager_base->per_pll_vco); + + /* assert pheriph outresetall */ + writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll_vco); + + /* assert sdram outresetall */ + writel(cfg->sdram_vco_base | VCO_EN_BASE| + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1), + &clock_manager_base->sdr_pll_vco); + + /* deassert main outresetall */ + writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll_vco); + + /* deassert pheriph outresetall */ + writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll_vco); + + /* deassert sdram outresetall */ + writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | + cfg->sdram_vco_base | VCO_EN_BASE, + &clock_manager_base->sdr_pll_vco); + + /* + * now that we've toggled outreset all, all the clocks + * are aligned nicely; so we can change any phase. + */ + cm_write_with_phase(cfg->ddrdqsclk, + (uint32_t)&clock_manager_base->sdr_pll_ddrdqsclk, + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); + + /* SDRAM DDR2XDQSCLK */ + cm_write_with_phase(cfg->ddr2xdqsclk, + (uint32_t)&clock_manager_base->sdr_pll_ddr2xdqsclk, + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); + + cm_write_with_phase(cfg->ddrdqclk, + (uint32_t)&clock_manager_base->sdr_pll_ddrdqclk, + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); + + cm_write_with_phase(cfg->s2fuser2clk, + (uint32_t)&clock_manager_base->sdr_pll_s2fuser2clk, + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); + + /* Take all three PLLs out of bypass when safe mode is cleared. */ + cm_write_bypass( + CLKMGR_BYPASS_PERPLLSRC_SET( + CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_SDRPLLSRC_SET( + CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | + CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) | + CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) | + CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE)); + + /* clear safe mode */ + cm_write_ctrl(readl(&clock_manager_base->ctrl) | + CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK)); + + /* + * now that safe mode is clear with clocks gated + * it safe to change the source mux for the flashes the the L4_MAIN + */ + writel(cfg->persrc, &clock_manager_base->per_pll_src); + writel(cfg->l4src, &clock_manager_base->main_pll_l4src); + + /* Now ungate non-hw-managed clocks */ + writel(~0, &clock_manager_base->main_pll_en); + writel(~0, &clock_manager_base->per_pll_en); + writel(~0, &clock_manager_base->sdr_pll_en); +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 36a00c39b7..2ae88bbd04 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -28,10 +28,99 @@ u32 spl_boot_device(void) void spl_board_init(void) { #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + cm_config_t cm_default_cfg = { + /* main group */ + MAIN_VCO_BASE, + CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT), + CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT), + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT), + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT), + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT), + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET( + CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT), + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) | + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) | + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) | + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET( + CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK), + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET( + CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) | + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET( + CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK), + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET( + CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK), + CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET( + CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) | + CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET( + CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP), + + /* peripheral group */ + PERI_VCO_BASE, + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT), + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT), + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT), + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT), + CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT), + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET( + CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT), + CLKMGR_PERPLLGRP_DIV_USBCLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_USBCLK) | + CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) | + CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) | + CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET( + CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK), + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET( + CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK), + CLKMGR_PERPLLGRP_SRC_QSPI_SET( + CONFIG_HPS_PERPLLGRP_SRC_QSPI) | + CLKMGR_PERPLLGRP_SRC_NAND_SET( + CONFIG_HPS_PERPLLGRP_SRC_NAND) | + CLKMGR_PERPLLGRP_SRC_SDMMC_SET( + CONFIG_HPS_PERPLLGRP_SRC_SDMMC), + + /* sdram pll group */ + SDR_VCO_BASE, + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) | + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT), + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) | + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT), + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) | + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT), + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET( + CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) | + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET( + CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT), + }; + debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + debug("Reconfigure Clock Manager\n"); + /* reconfigure the PLLs */ + cm_basic_init(&cm_default_cfg); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ac1e55a708..27be451a89 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index b6eb6de5e3..7d93f59428 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -13,5 +13,4 @@ obj-y += cache_v8.o obj-y += exceptions.o obj-y += cache.o obj-y += tlb.o -obj-y += gic.o obj-y += transition.o diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 546a83e8f8..4b3ee6ed6f 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -19,23 +19,22 @@ * clean and invalidate one level cache. * * x0: cache level - * x1~x9: clobbered + * x1: 0 flush & invalidate, 1 invalidate only + * x2~x9: clobbered */ ENTRY(__asm_flush_dcache_level) - lsl x1, x0, #1 - msr csselr_el1, x1 /* select cache level */ + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ add x2, x2, #4 /* x2 <- log2(cache line size) */ mov x3, #0x3ff and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ - add w4, w3, w3 - sub w4, w4, 1 /* round up log2(#ways + 1) */ - clz w5, w4 /* bit position of #ways */ + clz w5, w3 /* bit position of #ways */ mov x4, #0x7fff and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ - /* x1 <- cache level << 1 */ + /* x12 <- cache level << 1 */ /* x2 <- line length offset */ /* x3 <- number of cache ways - 1 */ /* x4 <- number of cache sets - 1 */ @@ -45,11 +44,14 @@ loop_set: mov x6, x3 /* x6 <- working copy of #ways */ loop_way: lsl x7, x6, x5 - orr x9, x1, x7 /* map way and level to cisw value */ + orr x9, x12, x7 /* map way and level to cisw value */ lsl x7, x4, x2 orr x9, x9, x7 /* map set number to cisw value */ - dc cisw, x9 /* clean & invalidate by set/way */ - subs x6, x6, #1 /* decrement the way */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ b.ge loop_way subs x4, x4, #1 /* decrement the set */ b.ge loop_set @@ -58,11 +60,14 @@ loop_way: ENDPROC(__asm_flush_dcache_level) /* - * void __asm_flush_dcache_all(void) + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 flush & invalidate, 1 invalidate only * * clean and invalidate all data cache by SET/WAY. */ -ENTRY(__asm_flush_dcache_all) +ENTRY(__asm_dcache_all) + mov x1, x0 dsb sy mrs x10, clidr_el1 /* read clidr_el1 */ lsr x11, x10, #24 @@ -76,13 +81,13 @@ ENTRY(__asm_flush_dcache_all) /* x15 <- return address */ loop_level: - lsl x1, x0, #1 - add x1, x1, x0 /* x0 <- tripled cache level */ - lsr x1, x10, x1 - and x1, x1, #7 /* x1 <- cache type */ - cmp x1, #2 + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 b.lt skip /* skip if no cache or icache */ - bl __asm_flush_dcache_level + bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ skip: add x0, x0, #1 /* increment cache level */ cmp x11, x0 @@ -96,8 +101,24 @@ skip: finished: ret +ENDPROC(__asm_dcache_all) + +ENTRY(__asm_flush_dcache_all) + mov x16, lr + mov x0, #0 + bl __asm_dcache_all + mov lr, x16 + ret ENDPROC(__asm_flush_dcache_all) +ENTRY(__asm_invalidate_dcache_all) + mov x16, lr + mov x0, #0xffff + bl __asm_dcache_all + mov lr, x16 + ret +ENDPROC(__asm_invalidate_dcache_all) + /* * void __asm_flush_dcache_range(start, end) * diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 131fdaba3f..a96ecda7e3 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -45,15 +45,31 @@ static void mmu_setup(void) /* load TTBR0 */ el = current_el(); - if (el == 1) + if (el == 1) { asm volatile("msr ttbr0_el1, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else if (el == 2) + asm volatile("msr tcr_el1, %0" + : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS) + : "memory"); + asm volatile("msr mair_el1, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else if (el == 2) { asm volatile("msr ttbr0_el2, %0" : : "r" (gd->arch.tlb_addr) : "memory"); - else + asm volatile("msr tcr_el2, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el2, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } else { asm volatile("msr ttbr0_el3, %0" : : "r" (gd->arch.tlb_addr) : "memory"); + asm volatile("msr tcr_el3, %0" + : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS) + : "memory"); + asm volatile("msr mair_el3, %0" + : : "r" (MEMORY_ATTRIBUTES) : "memory"); + } /* enable the mmu */ set_sctlr(get_sctlr() | CR_M); @@ -64,7 +80,7 @@ static void mmu_setup(void) */ void invalidate_dcache_all(void) { - __asm_flush_dcache_all(); + __asm_invalidate_dcache_all(); } /* @@ -161,6 +177,7 @@ int dcache_status(void) void icache_enable(void) { + __asm_invalidate_icache_all(); set_sctlr(get_sctlr() | CR_I); } diff --git a/arch/arm/cpu/armv8/gic.S b/arch/arm/cpu/armv8/gic.S deleted file mode 100644 index 599aa8f2ba..0000000000 --- a/arch/arm/cpu/armv8/gic.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * GIC Initialization Routines. - * - * (C) Copyright 2013 - * David Feng <fenghua@phytium.com.cn> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <linux/linkage.h> -#include <asm/macro.h> -#include <asm/gic.h> - - -/************************************************************************* - * - * void gic_init(void) __attribute__((weak)); - * - * Currently, this routine only initialize secure copy of GIC - * with Security Extensions at EL3. - * - *************************************************************************/ -WEAK(gic_init) - branch_if_slave x0, 2f - - /* Initialize Distributor and SPIs */ - ldr x1, =GICD_BASE - mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */ - str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */ - ldr w0, [x1, GICD_TYPER] - and w2, w0, #0x1f /* ITLinesNumber */ - cbz w2, 2f /* No SPIs */ - add x1, x1, (GICD_IGROUPRn + 4) - mov w0, #~0 /* Config SPIs as Grp1 */ -1: str w0, [x1], #0x4 - sub w2, w2, #0x1 - cbnz w2, 1b - - /* Initialize SGIs and PPIs */ -2: ldr x1, =GICD_BASE - mov w0, #~0 /* Config SGIs and PPIs as Grp1 */ - str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */ - mov w0, #0x1 /* Enable SGI 0 */ - str w0, [x1, GICD_ISENABLERn] - - /* Initialize Cpu Interface */ - ldr x1, =GICC_BASE - mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */ - /* Enable Ack Group1 Interrupt & */ - /* EnableGrp0 & EnableGrp1 */ - str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */ - - mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */ - str w0, [x1, GICC_PMR] - - ret -ENDPROC(gic_init) - - -/************************************************************************* - * - * void gic_send_sgi(u64 sgi) __attribute__((weak)); - * - *************************************************************************/ -WEAK(gic_send_sgi) - ldr x1, =GICD_BASE - mov w2, #0x8000 - movk w2, #0x100, lsl #16 - orr w2, w2, w0 - str w2, [x1, GICD_SGIR] - ret -ENDPROC(gic_send_sgi) - - -/************************************************************************* - * - * void wait_for_wakeup(void) __attribute__((weak)); - * - * Wait for SGI 0 from master. - * - *************************************************************************/ -WEAK(wait_for_wakeup) - ldr x1, =GICC_BASE -0: wfi - ldr w0, [x1, GICC_AIAR] - str w0, [x1, GICC_AEOIR] - cbnz w0, 0b - ret -ENDPROC(wait_for_wakeup) - - -/************************************************************************* - * - * void smp_kick_all_cpus(void) __attribute__((weak)); - * - *************************************************************************/ -WEAK(smp_kick_all_cpus) - /* Kick secondary cpus up by SGI 0 interrupt */ - mov x0, xzr /* SGI 0 */ - mov x29, lr /* Save LR */ - bl gic_send_sgi - mov lr, x29 /* Restore LR */ - ret -ENDPROC(smp_kick_all_cpus) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index bcc2603098..33d3f3688a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -50,7 +50,10 @@ reset: */ adr x0, vectors switch_el x1, 3f, 2f, 1f -3: msr vbar_el3, x0 +3: mrs x0, scr_el3 + orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ + msr scr_el3, x0 + msr vbar_el3, x0 msr cptr_el3, xzr /* Enable FP/SIMD */ ldr x0, =COUNTER_FREQUENCY msr cntfrq_el0, x0 /* Initialize CNTFRQ */ @@ -64,10 +67,12 @@ reset: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: - /* Cache/BPB/TLB Invalidate */ - bl __asm_flush_dcache_all /* dCache clean&invalidate */ - bl __asm_invalidate_icache_all /* iCache invalidate */ - bl __asm_invalidate_tlb_all /* invalidate TLBs */ + /* + * Cache/BPB/TLB Invalidate + * i-cache is invalidated before enabled in icache_enable() + * tlb is invalidated before mmu is enabled in dcache_enable() + * d-cache is invalidated before enabled in dcache_enable() + */ /* Processor specific initialization */ bl lowlevel_init @@ -93,63 +98,64 @@ master_cpu: /*-----------------------------------------------------------------------*/ WEAK(lowlevel_init) - /* Initialize GIC Secure Bank Status */ mov x29, lr /* Save LR */ - bl gic_init - branch_if_master x0, x1, 1f +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#if defined(CONFIG_GICV3) + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + + branch_if_master x0, x1, 2f /* * Slave should wait for master clearing spin table. * This sync prevent salves observing incorrect * value of spin table and jumping to wrong place. */ - bl wait_for_wakeup +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) +#ifdef CONFIG_GICV2 + ldr x0, =GICC_BASE +#endif + bl gic_wait_for_interrupt +#endif /* - * All processors will enter EL2 and optionally EL1. + * All slaves will enter EL2 and optionally EL1. */ bl armv8_switch_to_el2 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 bl armv8_switch_to_el1 #endif -1: +2: mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) -/*-----------------------------------------------------------------------*/ - -ENTRY(c_runtime_cpu_setup) - /* If I-cache is enabled invalidate it */ -#ifndef CONFIG_SYS_ICACHE_OFF - ic iallu /* I+BTB cache invalidate */ - isb sy +WEAK(smp_kick_all_cpus) + /* Kick secondary cpus up by SGI 0 interrupt */ + mov x29, lr /* Save LR */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + ldr x0, =GICD_BASE + bl gic_kick_secondary_cpus #endif + mov lr, x29 /* Restore LR */ + ret +ENDPROC(smp_kick_all_cpus) -#ifndef CONFIG_SYS_DCACHE_OFF - /* - * Setup MAIR and TCR. - */ - ldr x0, =MEMORY_ATTRIBUTES - ldr x1, =TCR_FLAGS - - switch_el x2, 3f, 2f, 1f -3: orr x1, x1, TCR_EL3_IPS_BITS - msr mair_el3, x0 - msr tcr_el3, x1 - b 0f -2: orr x1, x1, TCR_EL2_IPS_BITS - msr mair_el2, x0 - msr tcr_el2, x1 - b 0f -1: orr x1, x1, TCR_EL1_IPS_BITS - msr mair_el1, x0 - msr tcr_el1, x1 -0: -#endif +/*-----------------------------------------------------------------------*/ +ENTRY(c_runtime_cpu_setup) /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile index 32ddbdae45..0e4b3fc1dd 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/cpu/tegra20-common/Makefile @@ -9,7 +9,7 @@ # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t +CFLAGS_warmboot_avp.o += -march=armv4t obj-y += clock.o funcmux.o pinmux.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 87c2de22f5..33c1f99fc0 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -102,6 +102,7 @@ SECTIONS .dynamic : { *(.dynamic*) } .plt : { *(.plt*) } .interp : { *(.interp*) } + .gnu.hash : { *(.gnu.hash) } .gnu : { *(.gnu*) } .ARM.exidx : { *(.ARM.exidx*) } .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e2fcca5670..2c3c773306 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,7 +1,13 @@ +dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-universal_c210.dtb \ + exynos4210-trats.dtb \ + exynos4412-trats2.dtb + dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb +dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi new file mode 100644 index 0000000000..71dc7ebf4a --- /dev/null +++ b/arch/arm/dts/exynos4.dtsi @@ -0,0 +1,138 @@ +/* + * Samsung's Exynos4 SoC common device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "skeleton.dtsi" + +/ { + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x3c>; + id = <0>; + }; + + serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x3c>; + id = <1>; + }; + + serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x3c>; + id = <2>; + }; + + serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x3c>; + id = <3>; + }; + + serial@13840000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13840000 0x3c>; + id = <4>; + }; + + i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <0 0 0>; + }; + + i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <1 1 0>; + }; + + i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <2 2 0>; + }; + + i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <3 3 0>; + }; + + i2c@138a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <4 4 0>; + }; + + i2c@138b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <5 5 0>; + }; + + i2c@138c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <6 6 0>; + }; + + i2c@138d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + interrupts = <7 7 0>; + }; + + sdhci@12510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12510000 0x1000>; + interrupts = <0 75 0>; + }; + + sdhci@12520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12520000 0x1000>; + interrupts = <0 76 0>; + }; + + sdhci@12530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12530000 0x1000>; + interrupts = <0 77 0>; + }; + + sdhci@12540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos-mmc"; + reg = <0x12540000 0x1000>; + interrupts = <0 78 0>; + }; + + gpio: gpio { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts new file mode 100644 index 0000000000..5c9d2aed68 --- /dev/null +++ b/arch/arm/dts/exynos4210-origen.dts @@ -0,0 +1,45 @@ +/* + * Samsung's Exynos4210 based Origen board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "exynos4.dtsi" + +/ { + model = "Insignal Origen evaluation board based on Exynos4210"; + compatible = "insignal,origen", "samsung,exynos4210"; + + chosen { + bootargs =""; + }; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc2 = "sdhci@12530000"; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x2008002 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +};
\ No newline at end of file diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts new file mode 100644 index 0000000000..992e0234c9 --- /dev/null +++ b/arch/arm/dts/exynos4210-trats.dts @@ -0,0 +1,120 @@ +/* + * Samsung's Exynos4210 based Trats board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung Trats based on Exynos4210"; + compatible = "samsung,trats", "samsung,exynos4210"; + + config { + samsung,dsim-device-name = "s6e8ax0"; + }; + + aliases { + i2c0 = "/i2c@13860000"; + i2c1 = "/i2c@13870000"; + i2c2 = "/i2c@13880000"; + i2c3 = "/i2c@13890000"; + i2c4 = "/i2c@138a0000"; + i2c5 = "/i2c@138b0000"; + i2c6 = "/i2c@138c0000"; + i2c7 = "/i2c@138d0000"; + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <720>; + samsung,vl-row = <1280>; + samsung,vl-width = <720>; + samsung,vl-height = <1280>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <5>; + samsung,vl-hbpd = <10>; + samsung,vl-hfpd = <10>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <1>; + samsung,vl-vfpd = <13>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,power-on-delay = <30>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <1>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; + + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpio 0x2008002 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x20c6004 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +};
\ No newline at end of file diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts new file mode 100644 index 0000000000..1cdd981d6d --- /dev/null +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -0,0 +1,83 @@ +/* + * Samsung's Exynos4210 based Universal C210 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung Universal C210 based on Exynos4210 rev0"; + compatible = "samsung,universal_c210", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpio 0x2008002 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x20c6004 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <480>; + samsung,vl-row = <800>; + samsung,vl-width = <480>; + samsung,vl-height = <800>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <2>; + samsung,vl-hbpd = <16>; + samsung,vl-hfpd = <16>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <8>; + samsung,vl-vfpd = <8>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,pclk_name = <1>; + samsung,sclk_div = <1>; + + samsung,winid = <0>; + samsung,power-on-delay = <10000>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <0>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; +}; diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts new file mode 100644 index 0000000000..7d32067fdd --- /dev/null +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -0,0 +1,434 @@ +/* + * Samsung's Exynos4412 based Trats2 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung Trats2 based on Exynos4412"; + compatible = "samsung,trats2", "samsung,exynos4412"; + + config { + samsung,dsim-device-name = "s6e8ax0"; + }; + + aliases { + i2c0 = "/i2c@13860000"; + i2c1 = "/i2c@13870000"; + i2c2 = "/i2c@13880000"; + i2c3 = "/i2c@13890000"; + i2c4 = "/i2c@138a0000"; + i2c5 = "/i2c@138b0000"; + i2c6 = "/i2c@138c0000"; + i2c7 = "/i2c@138d0000"; + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + mmc0 = "sdhci@12510000"; + mmc2 = "sdhci@12530000"; + }; + + i2c@138d0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + max77686_pmic@09 { + compatible = "maxim,max77686_pmic"; + interrupts = <7 0>; + reg = <0x09 0 0>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo2_reg: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo3_reg: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo4_reg: ldo4 { + regulator-compatible = "LDO4"; + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo5_reg: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo6_reg: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "VMPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo7_reg: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "VPLL_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-mem-on; + }; + + ldo8_reg: ldo8 { + regulator-compatible = "LDO8"; + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo9_reg: ldo9 { + regulator-compatible = "LDO9"; + regulator-name = "CAM_ISP_MIPI_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo10_reg: ldo10 { + regulator-compatible = "LDO10"; + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo11_reg: ldo11 { + regulator-compatible = "LDO11"; + regulator-name = "VABB1_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo12_reg: ldo12 { + regulator-compatible = "LDO12"; + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-off; + }; + + ldo13_reg: ldo13 { + regulator-compatible = "LDO13"; + regulator-name = "NFC_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo14_reg: ldo14 { + regulator-compatible = "LDO14"; + regulator-name = "VABB2_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo15_reg: ldo15 { + regulator-compatible = "LDO15"; + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-mem-off; + }; + + ldo16_reg: ldo16 { + regulator-compatible = "LDO16"; + regulator-name = "VHSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-off; + }; + + ldo17_reg: ldo17 { + regulator-compatible = "LDO17"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-mem-idle; + }; + + ldo18_reg: ldo18 { + regulator-compatible = "LDO18"; + regulator-name = "CAM_ISP_SEN_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo19_reg: ldo19 { + regulator-compatible = "LDO19"; + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo20_reg: ldo20 { + regulator-compatible = "LDO20"; + regulator-name = "VDDQ_PRE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo21_reg: ldo21 { + regulator-compatible = "LDO21"; + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo22_reg: ldo22 { + regulator-compatible = "LDO22"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-mem-off; + }; + + ldo23_reg: ldo23 { + regulator-compatible = "LDO23"; + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-mem-idle; + }; + + ldo24_reg: ldo24 { + regulator-compatible = "LDO24"; + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-mem-idle; + }; + + ldo25_reg: ldo25 { + regulator-compatible = "LDO25"; + regulator-name = "LCD_VCC_3.3V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-mem-idle; + }; + + ldo26_reg: ldo26 { + regulator-compatible = "LDO26"; + regulator-name = "MOTOR_VCC_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-mem-idle; + }; + + buck1_reg: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck2_reg: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck3_reg: buck3 { + regulator-compatible = "BUCK3"; + regulator-name = "vdd_int"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + regulator-mem-off; + }; + + buck4_reg: buck4 { + regulator-compatible = "BUCK4"; + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-mem-off; + }; + + buck5_reg: buck5 { + regulator-compatible = "BUCK5"; + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck6_reg: buck6 { + regulator-compatible = "BUCK6"; + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: buck7 { + regulator-compatible = "BUCK7"; + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: buck8 { + regulator-compatible = "BUCK8"; + regulator-name = "VMEM_VDDF_3.0V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-mem-off; + }; + + buck9_reg: buck9 { + regulator-compatible = "BUCK9"; + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-mem-off; + }; + }; + }; + }; + + fimd@11c00000 { + compatible = "samsung,exynos-fimd"; + reg = <0x11c00000 0xa4>; + + samsung,vl-freq = <60>; + samsung,vl-col = <720>; + samsung,vl-row = <1280>; + samsung,vl-width = <720>; + samsung,vl-height = <1280>; + + samsung,vl-clkp = <0>; + samsung,vl-oep = <0>; + samsung,vl-hsp = <1>; + samsung,vl-vsp = <1>; + samsung,vl-dp = <1>; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <5>; + samsung,vl-hbpd = <10>; + samsung,vl-hfpd = <10>; + samsung,vl-vspw = <2>; + samsung,vl-vbpd = <1>; + samsung,vl-vfpd = <13>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <0>; + samsung,power-on-delay = <30>; + samsung,interface-mode = <1>; + samsung,mipi-enabled = <1>; + samsung,dp-enabled; + samsung,dual-lcd-enabled; + + samsung,logo-on = <1>; + samsung,resolution = <0>; + samsung,rgb-mode = <0>; + }; + + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; + + sdhci@12510000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + pwr-gpios = <&gpio 0x2004002 0>; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0x20C6004 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts new file mode 100644 index 0000000000..a3c9c91f32 --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto.dts @@ -0,0 +1,13 @@ +/* + + * Copyright 2012 Freescale Semiconductor, Inc. + + * Copyright 2011 Linaro Ltd. + + * + + * SPDX-License-Identifier: GPL-2.0+ + + */ + +/dts-v1/; + +/ { + model = "Freescale i.MX6 Quad SABRE Automotive Board"; + compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +}; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 16809fee5f..b04dfbbcb9 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -32,7 +32,7 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) -quiet_cmd_mkimage = UIMAGE $@ +quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) @@ -42,6 +42,14 @@ MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \ u-boot.imx: u-boot.bin $(IMX_CONFIG) FORCE $(call if_changed,mkimage) +ifeq ($(CONFIG_OF_SEPARATE),y) +MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \ + -e $(CONFIG_SYS_TEXT_BASE) + +u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) FORCE + $(call if_changed,mkimage) +endif + MKIMAGEFLAGS_SPL = -n $(filter-out $< $(PHONY),$^) -T imximage \ -e $(CONFIG_SPL_TEXT_BASE) diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 2df4114580..8543f4399c 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #if defined(CONFIG_TI816X) #define BOOT_DEVICE_XIP 2 diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h index 3e9e6065c7..9aa3f4ab27 100644 --- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h +++ b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h @@ -151,6 +151,7 @@ struct davinci_mmc { uint host_caps; /* Host capabilities */ uint voltages; /* Host supported voltages */ uint version; /* MMC Controller version */ + struct mmc_config cfg; }; enum { diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h index 5aa5d2d019..5afe0d4ba5 100644 --- a/arch/arm/include/asm/arch-davinci/spl.h +++ b/arch/arm/include/asm/arch-davinci/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NAND 1 #define BOOT_DEVICE_SPI 2 diff --git a/arch/arm/include/asm/arch-exynos/board.h b/arch/arm/include/asm/arch-exynos/board.h index 243fb12b76..1b1cd0dd9e 100644 --- a/arch/arm/include/asm/arch-exynos/board.h +++ b/arch/arm/include/asm/arch-exynos/board.h @@ -14,4 +14,16 @@ */ int exynos_init(void); +/* + * Exynos board specific changes for + * board_early_init_f + */ +int exynos_early_init_f(void); + +/* + * Exynos board specific changes for + * board_power_init + */ +int exynos_power_init(void); + #endif /* EXYNOS_BOARD_H */ diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index bccce63f2c..fdf73b507a 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -25,8 +25,9 @@ #define EXYNOS4_SYSTIMER_BASE 0x10050000 #define EXYNOS4_WATCHDOG_BASE 0x10060000 #define EXYNOS4_TZPC_BASE 0x10110000 -#define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_DMC_CTRL_BASE 0x10400000 +#define EXYNOS4_MIU_BASE 0x10600000 +#define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 @@ -48,7 +49,6 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE @@ -68,6 +68,7 @@ #define EXYNOS4X12_TZPC_BASE 0x10110000 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 +#define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 #define EXYNOS4X12_FIMD_BASE 0x11C00000 @@ -87,7 +88,6 @@ #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE @@ -106,7 +106,7 @@ #define EXYNOS5_SYSREG_BASE 0x10050000 #define EXYNOS5_TZPC_BASE 0x10100000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 #define EXYNOS5_GPIO_PART3_BASE 0x10D10000 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h index 40aca71678..50e5c258a9 100644 --- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h +++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h @@ -12,6 +12,7 @@ #include <linux/list.h> #include <linux/fb.h> +#include <lcd.h> #define PANEL_NAME_SIZE (32) @@ -368,8 +369,12 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev); void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd); +void exynos_init_dsim_platform_data(vidinfo_t *vid); /* panel driver init based on mipi dsi interface */ void s6e8ax0_init(void); +#ifdef CONFIG_OF_CONTROL +extern int mipi_power(void); +#endif #endif /* _DSIM_H */ diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h index 98d6530b15..0fb6461c08 100644 --- a/arch/arm/include/asm/arch-exynos/mmc.h +++ b/arch/arm/include/asm/arch-exynos/mmc.h @@ -53,6 +53,8 @@ #define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16) #define SDHCI_CTRL4_DRIVE_SHIFT (16) +#define SDHCI_MAX_HOSTS 4 + int s5p_sdhci_init(u32 regbase, int index, int bus_width); static inline int s5p_mmc_init(int index, int bus_width) @@ -62,4 +64,9 @@ static inline int s5p_mmc_init(int index, int bus_width) return s5p_sdhci_init(base, index, bus_width); } + +#ifdef CONFIG_OF_CONTROL +int exynos_mmc_init(const void *blob); +#endif + #endif diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h index f87c137c98..d0efec21ab 100644 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ b/arch/arm/include/asm/arch-mx35/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index 2ec319c08a..8350532786 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index 551b27df14..fb842a2264 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index 4a279cf052..f70799860f 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ -#define _ASM_SPL_H_ +#define _ASM_ARCH_SPL_H_ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h new file mode 100644 index 0000000000..966add3e91 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_MANAGER_H_ +#define _CLOCK_MANAGER_H_ + +typedef struct { + /* main group */ + uint32_t main_vco_base; + uint32_t mpuclk; + uint32_t mainclk; + uint32_t dbgatclk; + uint32_t mainqspiclk; + uint32_t mainnandsdmmcclk; + uint32_t cfg2fuser0clk; + uint32_t maindiv; + uint32_t dbgdiv; + uint32_t tracediv; + uint32_t l4src; + + /* peripheral group */ + uint32_t peri_vco_base; + uint32_t emac0clk; + uint32_t emac1clk; + uint32_t perqspiclk; + uint32_t pernandsdmmcclk; + uint32_t perbaseclk; + uint32_t s2fuser1clk; + uint32_t perdiv; + uint32_t gpiodiv; + uint32_t persrc; + + /* sdram pll group */ + uint32_t sdram_vco_base; + uint32_t ddrdqsclk; + uint32_t ddr2xdqsclk; + uint32_t ddrdqclk; + uint32_t s2fuser2clk; +} cm_config_t; + +extern void cm_basic_init(const cm_config_t *cfg); + +struct socfpga_clock_manager { + u32 ctrl; + u32 bypass; + u32 inter; + u32 intren; + u32 dbctrl; + u32 stat; + u32 _pad_0x18_0x3f[10]; + u32 mainpllgrp; + u32 perpllgrp; + u32 sdrpllgrp; + u32 _pad_0xe0_0x200[72]; + + u32 main_pll_vco; + u32 main_pll_misc; + u32 main_pll_mpuclk; + u32 main_pll_mainclk; + u32 main_pll_dbgatclk; + u32 main_pll_mainqspiclk; + u32 main_pll_mainnandsdmmcclk; + u32 main_pll_cfgs2fuser0clk; + u32 main_pll_en; + u32 main_pll_maindiv; + u32 main_pll_dbgdiv; + u32 main_pll_tracediv; + u32 main_pll_l4src; + u32 main_pll_stat; + u32 main_pll__pad_0x38_0x40[2]; + + u32 per_pll_vco; + u32 per_pll_misc; + u32 per_pll_emac0clk; + u32 per_pll_emac1clk; + u32 per_pll_perqspiclk; + u32 per_pll_pernandsdmmcclk; + u32 per_pll_perbaseclk; + u32 per_pll_s2fuser1clk; + u32 per_pll_en; + u32 per_pll_div; + u32 per_pll_gpiodiv; + u32 per_pll_src; + u32 per_pll_stat; + u32 per_pll__pad_0x34_0x40[3]; + + u32 sdr_pll_vco; + u32 sdr_pll_ctrl; + u32 sdr_pll_ddrdqsclk; + u32 sdr_pll_ddr2xdqsclk; + u32 sdr_pll_ddrdqclk; + u32 sdr_pll_s2fuser2clk; + u32 sdr_pll_en; + u32 sdr_pll_stat; +}; + +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070) +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030) +#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000) +#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000) +#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8) +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) \ + (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) \ + (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007) +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003) +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c) +#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008) +#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002) +#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007) +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0) +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00) +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001 +#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000) +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff) +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038) +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff) +#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010) +#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004) +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff + +#define MAIN_VCO_BASE \ + (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \ + CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER)) + +#define PERI_VCO_BASE \ + (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \ + CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \ + CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER)) + +#define SDR_VCO_BASE \ + (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \ + CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \ + CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER)) + +#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index 50c4ebd849..f564046bc0 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -11,6 +11,7 @@ #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_UART1_ADDRESS 0xffc03000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index b6896afd96..310bbd7df9 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -11,6 +11,9 @@ #include <fdtdec.h> +/* for mmc_config definition */ +#include <mmc.h> + #define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ #ifndef __ASSEMBLY__ @@ -138,6 +141,7 @@ struct mmc_host { struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */ unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + struct mmc_config cfg; /* mmc configuration */ }; void pad_init_mmc(struct mmc_host *host); diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda9f5..e17c7d1f70 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,57 +55,59 @@ struct ccm_reg { /* Analog components control digital interface (ANADIG) */ struct anadig_reg { + u32 reserved_0x000[4]; u32 pll3_ctrl; - u32 resv0[3]; + u32 reserved_0x014[3]; u32 pll7_ctrl; - u32 resv1[3]; + u32 reserved_0x024[3]; u32 pll2_ctrl; - u32 resv2[3]; + u32 reserved_0x034[3]; u32 pll2_ss; - u32 resv3[3]; + u32 reserved_0x044[3]; u32 pll2_num; - u32 resv4[3]; + u32 reserved_0x054[3]; u32 pll2_denom; - u32 resv5[3]; + u32 reserved_0x064[3]; u32 pll4_ctrl; - u32 resv6[3]; + u32 reserved_0x074[3]; u32 pll4_num; - u32 resv7[3]; + u32 reserved_0x084[3]; u32 pll4_denom; + u32 reserved_0x094[3]; u32 pll6_ctrl; - u32 resv8[3]; + u32 reserved_0x0A4[3]; u32 pll6_num; - u32 resv9[3]; + u32 reserved_0x0B4[3]; u32 pll6_denom; - u32 resv10[3]; + u32 reserved_0x0C4[7]; u32 pll5_ctrl; - u32 resv11[3]; + u32 reserved_0x0E4[3]; u32 pll3_pfd; - u32 resv12[3]; + u32 reserved_0x0F4[3]; u32 pll2_pfd; - u32 resv13[3]; + u32 reserved_0x104[3]; u32 reg_1p1; - u32 resv14[3]; + u32 reserved_0x114[3]; u32 reg_3p0; - u32 resv15[3]; + u32 reserved_0x124[3]; u32 reg_2p5; - u32 resv16[7]; + u32 reserved_0x134[7]; u32 ana_misc0; - u32 resv17[3]; + u32 reserved_0x154[3]; u32 ana_misc1; - u32 resv18[63]; + u32 reserved_0x164[63]; u32 anadig_digprog; - u32 resv19[3]; + u32 reserved_0x264[3]; u32 pll1_ctrl; - u32 resv20[3]; + u32 reserved_0x274[3]; u32 pll1_ss; - u32 resv21[3]; + u32 reserved_0x284[3]; u32 pll1_num; - u32 resv22[3]; + u32 reserved_0x294[3]; u32 pll1_denom; - u32 resv23[3]; + u32 reserved_0x2A4[3]; u32 pll1_pdf; - u32 resv24[3]; + u32 reserved_0x2B4[3]; u32 pll_lock; }; #endif @@ -164,6 +166,7 @@ struct anadig_reg { #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) #define CCM_REG_CTRL_MASK 0xffffffff +#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) @@ -184,6 +187,10 @@ struct anadig_reg { #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1 diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index b8c877f939..c2f9761846 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -85,6 +85,7 @@ #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) +#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) /* MUX mode and PAD ctrl are in one register */ #define CONFIG_IOMUX_SHARE_CONF_REG diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 4a39eb0d60..88807d8db4 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -22,8 +22,11 @@ enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), + VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -33,6 +36,15 @@ enum { VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), + VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h index ac2b2bfbed..bd3a80cdf7 100644 --- a/arch/arm/include/asm/gic.h +++ b/arch/arm/include/asm/gic.h @@ -51,4 +51,60 @@ #define GICC_IIDR 0x00fc #define GICC_DIR 0x1000 +/* ReDistributor Registers for Control and Physical LPIs */ +#define GICR_CTLR 0x0000 +#define GICR_IIDR 0x0004 +#define GICR_TYPER 0x0008 +#define GICR_STATUSR 0x0010 +#define GICR_WAKER 0x0014 +#define GICR_SETLPIR 0x0040 +#define GICR_CLRLPIR 0x0048 +#define GICR_SEIR 0x0068 +#define GICR_PROPBASER 0x0070 +#define GICR_PENDBASER 0x0078 +#define GICR_INVLPIR 0x00a0 +#define GICR_INVALLR 0x00b0 +#define GICR_SYNCR 0x00c0 +#define GICR_MOVLPIR 0x0100 +#define GICR_MOVALLR 0x0110 + +/* ReDistributor Registers for SGIs and PPIs */ +#define GICR_IGROUPRn 0x0080 +#define GICR_ISENABLERn 0x0100 +#define GICR_ICENABLERn 0x0180 +#define GICR_ISPENDRn 0x0200 +#define GICR_ICPENDRn 0x0280 +#define GICR_ISACTIVERn 0x0300 +#define GICR_ICACTIVERn 0x0380 +#define GICR_IPRIORITYRn 0x0400 +#define GICR_ICFGR0 0x0c00 +#define GICR_ICFGR1 0x0c04 +#define GICR_IGROUPMODRn 0x0d00 +#define GICR_NSACRn 0x0e00 + +/* Cpu Interface System Registers */ +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 +#define ICC_DIR_EL1 S3_0_C12_C11_1 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 +#define ICC_SEIEN_EL1 S3_0_C12_C13_0 +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + #endif /* __GIC_H__ */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 4178f8cf7e..74ee9a4df9 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -66,6 +66,7 @@ static inline void set_sctlr(unsigned int val) } void __asm_flush_dcache_all(void); +void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 9fc81cd012..e035d6acc0 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -35,6 +35,7 @@ endif obj-y += sections.o ifdef CONFIG_ARM64 +obj-y += gic_64.o obj-y += interrupts_64.o else obj-y += interrupts.o diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c new file mode 100644 index 0000000000..b0c26e5d68 --- /dev/null +++ b/arch/arm/lib/asm-offsets.c @@ -0,0 +1,248 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/kbuild.h> + +#if defined(CONFIG_MB86R0x) +#include <asm/arch/mb86r0x.h> +#endif +#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ + || defined(CONFIG_MX51) || defined(CONFIG_MX53) +#include <asm/arch/imx-regs.h> +#endif + +int main(void) +{ + /* + * TODO : Check if each entry in this file is really necessary. + * - struct mb86r0x_ddr2 + * - struct mb86r0x_memc + * - struct esdramc_regs + * - struct max_regs + * - struct aips_regs + * - struct aipi_regs + * - struct clkctl + * - struct dpll + * are used only for generating asm-offsets.h. + * It means their offset addresses are referenced only from assembly + * code. Is it better to define the macros directly in headers? + */ + +#if defined(CONFIG_MB86R0x) + /* ddr2 controller */ + DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); + DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); + DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); + DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); + DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); + DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); + DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); + DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); + DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); + DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); + DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); + DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); + DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); + DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); + DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); + + /* clock reset generator */ + DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); + DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); + DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); + DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); + DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); + DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); + + /* chip control module */ + DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); + + /* external bus interface */ + DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); + DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); + DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); + DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); + DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); + DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); + DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); + DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); + DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); +#endif + +#if defined(CONFIG_MX25) + /* Clock Control Module */ + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); + + /* Enhanced SDRAM Controller */ + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); +#endif + +#if defined(CONFIG_MX27) + DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); + DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); + DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); + + DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); + DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); + DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); + DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); + DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); + DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); + DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); + + DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); + DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); + DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); + DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); + DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); + + DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, gpcr)); + DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + + offsetof(struct system_control_regs, fmcr)); +#endif + +#if defined(CONFIG_MX35) + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); + DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); + DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); + DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); + DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); + DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); + DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); + DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); + DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); + DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); + DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); + DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); + DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); + DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); + DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); + DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); + DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); + DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); + DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); + DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39)); +#endif + +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) + /* Round up to make sure size gives nice stack alignment */ + DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); + DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr)); + DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr)); + DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr)); + DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr)); + DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr)); + DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr)); + DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1)); + DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2)); + DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1)); + DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr)); + DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr)); + DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr)); + DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr)); + DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2)); + DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3)); + DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4)); + DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr)); + DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr)); + DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr)); + DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor)); + DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr)); + DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr)); + DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr)); + DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr)); + DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr)); + DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0)); + DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1)); + DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2)); + DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3)); + DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4)); + DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5)); + DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6)); + DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor)); +#if defined(CONFIG_MX53) + DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7)); +#endif + + /* DPLL */ + DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); + DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); + DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); + DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); + DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); + DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); + DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); + DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); +#endif + + return 0; +} diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index a8295bf1f1..47ee070593 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -71,8 +71,7 @@ static void announce_and_cleanup(int fake) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); #ifdef CONFIG_BOOTSTAGE_FDT - if (flag == BOOTM_STATE_OS_FAKE_GO) - bootstage_fdt_add_report(); + bootstage_fdt_add_report(); #endif #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); @@ -199,6 +198,7 @@ static void do_nonsec_virt_switch(void) #ifdef CONFIG_ARM64 smp_kick_all_cpus(); + flush_dcache_all(); /* flush cache before swtiching to EL2 */ armv8_switch_to_el2(); #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 armv8_switch_to_el1(); diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S new file mode 100644 index 0000000000..d56396ea22 --- /dev/null +++ b/arch/arm/lib/gic_64.S @@ -0,0 +1,194 @@ +/* + * GIC Initialization Routines. + * + * (C) Copyright 2013 + * David Feng <fenghua@phytium.com.cn> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/gic.h> + + +/************************************************************************* + * + * void gic_init_secure(DistributorBase); + * + * Initialize secure copy of GIC at EL3. + * + *************************************************************************/ +ENTRY(gic_init_secure) + /* + * Initialize Distributor + * x0: Distributor Base + */ +#if defined(CONFIG_GICV3) + mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */ + /* EnableGrp1S | ARE_S | ARE_NS */ + str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f /* ITLinesNumber */ + cbz w10, 1f /* No SPIs */ + add x11, x0, (GICD_IGROUPRn + 4) + add x12, x0, (GICD_IGROUPMODRn + 4) + mov w9, #~0 +0: str w9, [x11], #0x4 + str wzr, [x12], #0x4 /* Config SPIs as Group1NS */ + sub w10, w10, #0x1 + cbnz w10, 0b +#elif defined(CONFIG_GICV2) + mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */ + str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f /* ITLinesNumber */ + cbz w10, 1f /* No SPIs */ + add x11, x0, (GICD_IGROUPRn + 4) + mov w9, #~0 /* Config SPIs as Grp1 */ +0: str w9, [x11], #0x4 + sub w10, w10, #0x1 + cbnz w10, 0b +#endif +1: + ret +ENDPROC(gic_init_secure) + + +/************************************************************************* + * For Gicv2: + * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase); + * For Gicv3: + * void gic_init_secure_percpu(ReDistributorBase); + * + * Initialize secure copy of GIC at EL3. + * + *************************************************************************/ +ENTRY(gic_init_secure_percpu) +#if defined(CONFIG_GICV3) + /* + * Initialize ReDistributor + * x0: ReDistributor Base + */ + mrs x10, mpidr_el1 + lsr x9, x10, #32 + bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */ + mov x9, x0 +1: ldr x11, [x9, GICR_TYPER] + lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */ + cmp w10, w11 + b.eq 2f + add x9, x9, #(2 << 16) + b 1b + + /* x9: ReDistributor Base Address of Current CPU */ +2: mov w10, #~0x2 + ldr w11, [x9, GICR_WAKER] + and w11, w11, w10 /* Clear ProcessorSleep */ + str w11, [x9, GICR_WAKER] + dsb st + isb +3: ldr w10, [x9, GICR_WAKER] + tbnz w10, #2, 3b /* Wait Children be Alive */ + + add x10, x9, #(1 << 16) /* SGI_Base */ + mov w11, #~0 + str w11, [x10, GICR_IGROUPRn] + str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */ + mov w11, #0x1 /* Enable SGI 0 */ + str w11, [x10, GICR_ISENABLERn] + + /* Initialize Cpu Interface */ + mrs x10, ICC_SRE_EL3 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL2 access to ICC_SRE_EL2 */ + msr ICC_SRE_EL3, x10 + isb + + mrs x10, ICC_SRE_EL2 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL1 access to ICC_SRE_EL1 */ + msr ICC_SRE_EL2, x10 + isb + + mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */ + msr ICC_IGRPEN1_EL3, x10 + isb + + msr ICC_CTLR_EL3, xzr + isb + + msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */ + isb + + mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */ + msr ICC_PMR_EL1, x10 + isb +#elif defined(CONFIG_GICV2) + /* + * Initialize SGIs and PPIs + * x0: Distributor Base + * x1: Cpu Interface Base + */ + mov w9, #~0 /* Config SGIs and PPIs as Grp1 */ + str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */ + mov w9, #0x1 /* Enable SGI 0 */ + str w9, [x0, GICD_ISENABLERn] + + /* Initialize Cpu Interface */ + mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */ + /* Enable Ack Group1 Interrupt & */ + /* EnableGrp0 & EnableGrp1 */ + str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */ + + mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */ + str w9, [x1, GICC_PMR] +#endif + ret +ENDPROC(gic_init_secure_percpu) + + +/************************************************************************* + * For Gicv2: + * void gic_kick_secondary_cpus(DistributorBase); + * For Gicv3: + * void gic_kick_secondary_cpus(void); + * + *************************************************************************/ +ENTRY(gic_kick_secondary_cpus) +#if defined(CONFIG_GICV3) + mov x9, #(1 << 40) + msr ICC_ASGI1R_EL1, x9 + isb +#elif defined(CONFIG_GICV2) + mov w9, #0x8000 + movk w9, #0x100, lsl #16 + str w9, [x0, GICD_SGIR] +#endif + ret +ENDPROC(gic_kick_secondary_cpus) + + +/************************************************************************* + * For Gicv2: + * void gic_wait_for_interrupt(CpuInterfaceBase); + * For Gicv3: + * void gic_wait_for_interrupt(void); + * + * Wait for SGI 0 from master. + * + *************************************************************************/ +ENTRY(gic_wait_for_interrupt) +0: wfi +#if defined(CONFIG_GICV3) + mrs x9, ICC_IAR1_EL1 + msr ICC_EOIR1_EL1, x9 +#elif defined(CONFIG_GICV2) + ldr w9, [x0, GICC_AIAR] + str w9, [x0, GICC_AEOIR] +#endif + cbnz w9, 0b + ret +ENDPROC(gic_wait_for_interrupt) diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 7fba9e2780..5c51cae8ab 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -11,6 +11,7 @@ #include <asm-offsets.h> #include <config.h> #include <linux/linkage.h> +#include <asm/macro.h> /* * void relocate_code (addr_moni) @@ -19,6 +20,9 @@ * x0 holds the destination address. */ ENTRY(relocate_code) + stp x29, x30, [sp, #-32]! /* create a stack frame */ + mov x29, sp + str x0, [sp, #16] /* * Copy u-boot from flash to RAM */ @@ -32,6 +36,7 @@ copy_loop: stp x10, x11, [x0], #16 /* copy to target address [x0] */ cmp x1, x2 /* until source end address [x2] */ b.lo copy_loop + str x0, [sp, #24] /* * Fix .rela.dyn relocations @@ -54,5 +59,19 @@ fixnext: b.lo fixloop relocate_done: + switch_el x1, 3f, 2f, 1f + bl hang +3: mrs x0, sctlr_el3 + b 0f +2: mrs x0, sctlr_el2 + b 0f +1: mrs x0, sctlr_el1 +0: tbz w0, #2, 5f /* skip flushing cache if disabled */ + tbz w0, #12, 4f /* invalide i-cache is enabled */ + ic iallu /* i-cache invalidate all */ + isb sy +4: ldp x0, x1, [sp, #16] + bl __asm_flush_dcache_range +5: ldp x29, x30, [sp],#16 ret ENDPROC(relocate_code) diff --git a/arch/nds32/cpu/n1213/ag101/asm-offsets.c b/arch/nds32/cpu/n1213/ag101/asm-offsets.c deleted file mode 100644 index cfe52d1df4..0000000000 --- a/arch/nds32/cpu/n1213/ag101/asm-offsets.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c - * - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <common.h> - -#include <linux/kbuild.h> - -int main(void) -{ -#ifdef CONFIG_FTSMC020 - OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); - OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); -#endif - BLANK(); -#ifdef CONFIG_FTAHBC020S - OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]); - OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); - OFFSET(FTAHBC020S_CR, ftahbc02s, cr); -#endif - BLANK(); -#ifdef CONFIG_FTPMU010 - OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); -#endif - BLANK(); -#ifdef CONFIG_FTSDMC021 - OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); - OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); - OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); - OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); - OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); - OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); - OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); - OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); -#endif - return 0; -} diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/lib/asm-offsets.c index 4769a9521d..39e3480bd5 100644 --- a/arch/nds32/cpu/n1213/ag102/asm-offsets.c +++ b/arch/nds32/lib/asm-offsets.c @@ -15,16 +15,43 @@ int main(void) { + /* + * TODO : Check if each entry in this file is really necessary. + * - struct ftahbc02s + * - struct ftsdmc021 + * - struct andes_pcu + * - struct dwcddr21mctl + * are used only for generating asm-offsets.h. + * It means their offset addresses are referenced only from assembly + * code. Is it better to define the macros directly in headers? + */ + #ifdef CONFIG_FTSMC020 OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr); OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr); #endif BLANK(); #ifdef CONFIG_FTAHBC020S + OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]); OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]); OFFSET(FTAHBC020S_CR, ftahbc02s, cr); #endif BLANK(); +#ifdef CONFIG_FTPMU010 + OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0); +#endif + BLANK(); +#ifdef CONFIG_FTSDMC021 + OFFSET(FTSDMC021_TP1, ftsdmc021, tp1); + OFFSET(FTSDMC021_TP2, ftsdmc021, tp2); + OFFSET(FTSDMC021_CR1, ftsdmc021, cr1); + OFFSET(FTSDMC021_CR2, ftsdmc021, cr2); + OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr); + OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr); + OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr); + OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr); +#endif + BLANK(); #ifdef CONFIG_ANDES_PCU OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */ #endif @@ -50,5 +77,6 @@ int main(void) OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */ OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */ #endif + return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 9a20b971c5..df44451091 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -734,6 +734,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 @@ -778,6 +780,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + #elif defined(CONFIG_PPC_C29X) #define CONFIG_MAX_CPUS 1 diff --git a/arch/x86/cpu/coreboot/asm-offsets.c b/arch/x86/lib/asm-offsets.c index d65c6ab1b0..d65c6ab1b0 100644 --- a/arch/x86/cpu/coreboot/asm-offsets.c +++ b/arch/x86/lib/asm-offsets.c diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 8aa16bcf80..804765a8de 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -120,7 +120,7 @@ void am33xx_spl_board_init(void) /* power-ON 3V3 via Resetcontroller */ oldspeed = i2c_get_bus_speed(); - if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) { + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { buf = RSTCTRL_FORCE_PWR_NEN; i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, (uint8_t *)&buf, sizeof(buf)); @@ -221,7 +221,7 @@ int board_late_init(void) TPS65217_WLEDCTRL1, 0x09, 0xFF); /* write bootinfo into scratchregister of resetcontroller */ oldspeed = i2c_get_bus_speed(); - if (0 != i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC)) { + if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) { i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, (uint8_t *)&buf, sizeof(buf)); i2c_set_bus_speed(oldspeed); diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h new file mode 100644 index 0000000000..9bd044230b --- /dev/null +++ b/board/altera/socfpga/pll_config.h @@ -0,0 +1,118 @@ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +/* PLL configuration data */ +/* Main PLL */ +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +/* + * To tell where is the clock source: + * 0 = MAINPLL + * 1 = PERIPHPLL + */ +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) + +/* Peripheral PLL */ +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +/* + * To tell where is the clock source: + * 0 = F2S_PERIPH_REF_CLK + * 1 = MAIN_CLK + * 2 = PERIPH_CLK + */ +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +/* SDRAM PLL */ +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz + * This if..else... is not required if generated by tools */ +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) +#else +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#endif /* CONFIG_SOCFPGA_ARRIA5 */ + +/* + * To tell where is the VCOs source: + * 0 = EOSC1 + * 1 = EOSC2 + * 2 = F2S + */ +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +/* Info for driver */ +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#ifdef CONFIG_SOCFPGA_ARRIA5 +/* The if..else... is not required if generated by tools */ +#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000) +#else +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#endif +#define CONFIG_HPS_CLK_EMAC0_HZ (250000000) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (400000000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (100000000) +#define CONFIG_HPS_CLK_CAN1_HZ (100000000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 2dfcb271d3..9e81bf3f3f 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -79,6 +79,8 @@ static void get_eeprom(struct tricorder_eeprom *eeprom) } else { panic("Could not get board revision\n"); } + } else { + memset(eeprom, 0, TRICORDER_EEPROM_SIZE); } } diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile index 655f530f2e..55402981fd 100644 --- a/board/cray/L1/Makefile +++ b/board/cray/L1/Makefile @@ -15,7 +15,7 @@ quiet_cmd_awk = AWK $@ $(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk $(call cmd,awk) -quiet_cmd_mkimage = UIMAGE $@ +quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c index 0f71a168bd..74f95011ad 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/denx/m53evk/m53evk.c @@ -31,24 +31,41 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) { - u32 size1, size2; + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); - gd->ram_size = size1 + size2; + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; return 0; } + void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; } static void setup_iomux_uart(void) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 08dd66fcc6..b32a97ff1a 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -30,24 +30,41 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) { - u32 size1, size2; + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} - size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); - gd->ram_size = size1 + size2; + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; return 0; } + void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; } u32 get_board_rev(void) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 12d8c5664e..d7d932eeb8 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -135,6 +135,16 @@ static void setup_spi(void) imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); } +iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ + MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ +}; + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + iomux_v3_cfg_t const di0_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ @@ -454,6 +464,7 @@ int overwrite_console(void) int board_eth_init(bd_t *bis) { setup_iomux_enet(); + setup_pcie(); return cpu_eth_init(bis); } diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 699ea7f010..4ee74c0198 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -31,7 +31,6 @@ void setup_iomux_ddr(void) { static const iomux_v3_cfg_t ddr_pads[] = { VF610_PAD_DDR_A15__DDR_A_15, - VF610_PAD_DDR_A15__DDR_A_15, VF610_PAD_DDR_A14__DDR_A_14, VF610_PAD_DDR_A13__DDR_A_13, VF610_PAD_DDR_A12__DDR_A_12, diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile new file mode 100644 index 0000000000..e8dab89c65 --- /dev/null +++ b/board/gateworks/gw_ventana/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de> +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Gateworks Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := gw_ventana.o gsc.o + diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README new file mode 100644 index 0000000000..9e697d6199 --- /dev/null +++ b/board/gateworks/gw_ventana/README @@ -0,0 +1,55 @@ +U-Boot for the Gateworks Ventana Product Family boards + +This file contains information for the port of U-Boot to the Gateworks +Ventana Product family boards. + +1. Boot source, boot from NAND +------------------------------ + +The i.MX6 BOOT ROM expects some structures that provide details of NAND layout +and bad block information (referred to as 'bootstreams') which are replicated +multiple times in NAND. The number of replications is configurable through +board strapping options and eFUSE settings. The Freescale 'kobs-ng' +application from the Freescale LTIB BSP, which runs under Linux, must be used +to program the bootstream in order to setup the replicated headers correctly. + +The Gateworks Ventana boards with NAND flash have been factory programmed +such that their eFUSE settings expect 2 copies of the boostream (this is +specified by providing kobs-ng with the --search_exponent=1 argument). Once in +Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream +with: + +kobs-ng init -v -x --search_exponent=1 u-boot.imx + +The kobs-ng application uses an imximage (u-boot.imx) which contains the +Image Vector Table (IVT) and Device Configuration Data (DCD) structures that +the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware +Configuration Block (FCB) and Discovered Bad Block Table (DBBT). + +This information is taken from: + http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH + +More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual. + +2. Build +-------- + +There are several Gateworks Ventana boards that share a simliar design but +vary based on CPU, Memory configuration, and subloaded devices. Although +the subloaded devices are handled dynamically in the bootloader using +factory configured EEPROM data to modify the device-tree, the CPU choice +(IMX6Q vs IMX6DL) and memory configurations are currently compile-time +options. + +The following Gateworks Ventana configurations exist: + gwventanaq1gspi: MX6Q,1GB,SPI FLASH + gwventanaq : MX6Q,512MB,NAND FLASH + gwventanaq1g : MX6Q,1GB,NAND FLASH + gwventanadl : MX6DL,512MB,NAND FLASH + gwventanadl1g : MX6DL,1GB,NAND FLASH + +To build U-Boot for the MX6Q,1GB,NAND FLASH for example: + + make gwventanaq1g_config + make + diff --git a/board/gateworks/gw_ventana/clocks.cfg b/board/gateworks/gw_ventana/clocks.cfg new file mode 100644 index 0000000000..a8118a258e --- /dev/null +++ b/board/gateworks/gw_ventana/clocks.cfg @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c new file mode 100644 index 0000000000..37966abba9 --- /dev/null +++ b/board/gateworks/gw_ventana/gsc.c @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/errno.h> +#include <common.h> +#include <i2c.h> +#include <linux/ctype.h> + +#include "gsc.h" + +#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100) + +/* + * The Gateworks System Controller will fail to ACK a master transaction if + * it is busy, which can occur during its 1HZ timer tick while reading ADC's. + * When this does occur, it will never be busy long enough to fail more than + * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with + * 3 retries. + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_read(chip, addr, alen, buf, len); + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + return ret; +} + +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int retry = 3; + int n = 0; + int ret; + + while (n++ < retry) { + ret = i2c_write(chip, addr, alen, buf, len); + if (!ret) + break; + debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, + n, ret); + if (ret != -ENODEV) + break; + mdelay(10); + } + mdelay(1); + return ret; +} + +#ifdef CONFIG_CMD_GSC +static void read_hwmon(const char *name, uint reg, uint size, uint low, + uint high) +{ + unsigned char buf[3]; + uint ui; + + printf("%-8s:", name); + memset(buf, 0, sizeof(buf)); + if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { + puts("fRD\n"); + } else { + ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); + if (ui == 0xffffff) + printf("invalid"); + else if (ui < low) + printf("%d Failed - Low", ui); + else if (ui > high) + printf("%d Failed - High", ui); + else + printf("%d", ui); + } + puts("\n"); +} + +int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *model = getenv("model"); + + i2c_set_bus_num(0); + read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000); + read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000); + read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500); + read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10)); + read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10)); + read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10)); + read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10)); + read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10)); + read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10)); + + switch (model[3]) { + case '1': /* GW51xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + break; + case '2': /* GW52xx */ + case '3': /* GW53xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + break; + case '4': /* GW54xx */ + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10)); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10)); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + break; + } + return 0; +} + +U_BOOT_CMD(gsc, 1, 1, do_gsc, + "GSC test", + "" +); + +#endif /* CONFIG_CMD_GSC */ diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h new file mode 100644 index 0000000000..da970c39d6 --- /dev/null +++ b/board/gateworks/gw_ventana/gsc.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASSEMBLY__ + +/* i2c slave addresses */ +#define GSC_SC_ADDR 0x20 +#define GSC_RTC_ADDR 0x68 +#define GSC_HWMON_ADDR 0x29 +#define GSC_EEPROM_ADDR 0x51 + +/* System Controller registers */ +enum { + GSC_SC_CTRL0 = 0x00, + GSC_SC_CTRL1 = 0x01, + GSC_SC_STATUS = 0x0a, + GSC_SC_FWVER = 0x0e, +}; + +/* System Controller Control1 bits */ +enum { + GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */ +}; + +/* System Controller Interrupt bits */ +enum { + GSC_SC_IRQ_PB = 0, /* Pushbutton switch */ + GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */ + GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */ + GSC_SC_IRQ_GPIO = 4, /* GPIO change */ + GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */ + GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */ + GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */ +}; + +/* Hardware Monitor registers */ +enum { + GSC_HWMON_TEMP = 0x00, + GSC_HWMON_VIN = 0x02, + GSC_HWMON_VDD_3P3 = 0x05, + GSC_HWMON_VBATT = 0x08, + GSC_HWMON_VDD_5P0 = 0x0b, + GSC_HWMON_VDD_CORE = 0x0e, + GSC_HWMON_VDD_HIGH = 0x14, + GSC_HWMON_VDD_DDR = 0x17, + GSC_HWMON_VDD_SOC = 0x11, + GSC_HWMON_VDD_1P8 = 0x1d, + GSC_HWMON_VDD_2P5 = 0x23, + GSC_HWMON_VDD_1P0 = 0x20, +}; + +/* + * I2C transactions to the GSC are done via these functions which + * perform retries in the case of a busy GSC NAK'ing the transaction + */ +int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); +int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); +#endif + diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c new file mode 100644 index 0000000000..c130e2c1ed --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -0,0 +1,1263 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * Author: Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/sata.h> +#include <jffs2/load_kernel.h> +#include <hwconfig.h> +#include <i2c.h> +#include <linux/ctype.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <mmc.h> +#include <mtd_node.h> +#include <netdev.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include <i2c.h> +#include <fdt_support.h> +#include <jffs2/load_kernel.h> +#include <spi_flash.h> + +#include "gsc.h" +#include "ventana_eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO's common to all baseboards */ +#define GP_PHY_RST IMX_GPIO_NR(1, 30) +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GP_SD3_CD IMX_GPIO_NR(7, 0) +#define GP_RS232_EN IMX_GPIO_NR(2, 11) +#define GP_MSATA_SEL IMX_GPIO_NR(2, 8) + +/* I2C bus numbers */ +#define I2C_GSC 0 +#define I2C_PMIC 1 + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +/* + * EEPROM board info struct populated by read_eeprom so that we only have to + * read it once. + */ +static struct ventana_board_info ventana_info; + +enum { + GW54proto, /* original GW5400-A prototype */ + GW51xx, + GW52xx, + GW53xx, + GW54xx, + GW_UNKNOWN, +}; + +int board_type; + +/* UART1: Function varies per baseboard */ +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* UART2: Serial Console */ +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +/* I2C1: GSC */ +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, + .gp = IMX_GPIO_NR(3, 21) + }, + .sda = { + .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, + .gp = IMX_GPIO_NR(3, 28) + } +}; + +/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +/* I2C3: Misc/Expansion */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* MMC */ +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +/* ENET */ +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* PHY nRST */ + MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* NAND */ +iomux_v3_cfg_t const nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_CMD_NAND +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + /* toggle PHY_RST# */ + gpio_direction_output(GP_PHY_RST, 0); + mdelay(2); + gpio_set_value(GP_PHY_RST, 1); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_USB_EHCI_MX6 +iomux_v3_cfg_t const usb_pads[] = { + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL), + MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL), + MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */ +}; + +int board_ehci_hcd_init(int port) +{ + struct ventana_board_info *info = &ventana_info; + + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB HUB (present on GW54xx/GW53xx) */ + switch (info->model[3]) { + case '3': /* GW53xx */ + imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09| + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 9), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 9), 1); + break; + case '4': /* GW54xx */ + imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 | + MUX_PAD_CTRL(NO_PAD_CTRL)); + gpio_direction_output(IMX_GPIO_NR(1, 16), 0); + mdelay(2); + gpio_set_value(IMX_GPIO_NR(1, 16), 1); + break; + } + + return 0; +} + +int board_ehci_power(int port, int on) +{ + if (port) + return 0; + gpio_set_value(GP_USB_OTG_PWR, on); + return 0; +} +#endif /* CONFIG_USB_EHCI_MX6 */ + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* Card Detect */ + gpio_direction_input(GP_SD3_CD); + return !gpio_get_value(GP_SD3_CD); +} + +int board_mmc_init(bd_t *bis) +{ + /* Only one USDHC controller on Ventana */ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg.max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} +#endif /* CONFIG_FSL_ESDHC */ + +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + /* SS1 */ + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +static void setup_spi(void) +{ + gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + +/* configure eth0 PHY board-specific LED behavior */ +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* Marvel 88E1510 */ + if (phydev->phy_id == 0x1410dd1) { + /* + * Page 3, Register 16: LED[2:0] Function Control Register + * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link + * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity + */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); + val = phy_read(phydev, MDIO_DEVAD_NONE, 16); + val &= 0xff00; + val |= 0x0017; + phy_write(phydev, MDIO_DEVAD_NONE, 16, val); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + +#ifdef CONFIG_FEC_MXC + cpu_eth_init(bis); +#endif + +#ifdef CONFIG_CI_UDC + /* For otg ethernet*/ + usb_eth_initialize(bis); +#endif + + return 0; +} + +/* read ventana EEPROM, check for validity, and return baseboard type */ +static int +read_eeprom(void) +{ + int i; + int chksum; + char baseboard; + int type; + struct ventana_board_info *info = &ventana_info; + unsigned char *buf = (unsigned char *)&ventana_info; + + memset(info, 0, sizeof(ventana_info)); + + /* + * On a board with a missing/depleted backup battery for GSC, the + * board may be ready to probe the GSC before its firmware is + * running. We will wait here indefinately for the GSC/EEPROM. + */ + while (1) { + if (0 == i2c_set_bus_num(I2C_GSC) && + 0 == i2c_probe(GSC_EEPROM_ADDR)) + break; + mdelay(1); + } + + /* read eeprom config section */ + if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) { + puts("EEPROM: Failed to read EEPROM\n"); + info->model[0] = 0; + return GW_UNKNOWN; + } + + /* sanity checks */ + if (info->model[0] != 'G' || info->model[1] != 'W') { + puts("EEPROM: Invalid Model in EEPROM\n"); + info->model[0] = 0; + return GW_UNKNOWN; + } + + /* validate checksum */ + for (chksum = 0, i = 0; i < sizeof(*info)-2; i++) + chksum += buf[i]; + if ((info->chksum[0] != chksum>>8) || + (info->chksum[1] != (chksum&0xff))) { + puts("EEPROM: Failed EEPROM checksum\n"); + info->model[0] = 0; + return GW_UNKNOWN; + } + + /* original GW5400-A prototype */ + baseboard = info->model[3]; + if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0) + baseboard = '0'; + + switch (baseboard) { + case '0': /* original GW5400-A prototype */ + type = GW54proto; + break; + case '1': + type = GW51xx; + break; + case '2': + type = GW52xx; + break; + case '3': + type = GW53xx; + break; + case '4': + type = GW54xx; + break; + default: + printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); + type = GW_UNKNOWN; + break; + } + return type; +} + +/* + * Baseboard specific GPIO + */ + +/* common to add baseboards */ +static iomux_v3_cfg_t const gw_gpio_pads[] = { + /* MSATA_EN */ + MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RS232_EN# */ + MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* prototype */ +static iomux_v3_cfg_t const gwproto_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RS485_EN */ + MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_EN */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* DIOI2C_DIS# */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCICK_SSON */ + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* GPS_SHDN */ + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_PWR */ + MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* MX6_LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPS_SHDN */ + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* USBOTG_SEL */ + MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_PWR */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* MX6_LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPS_SHDN */ + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* VID_EN */ + MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* PANLEDG# */ + MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PANLEDR# */ + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* MX6_LOCLED# */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* MIPI_DIO */ + MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RS485_EN */ + MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_PWREN# */ + MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* IOEXP_IRQ# */ + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* DIOI2C_DIS# */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* DIOI2C_DIS# */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCICK_SSON */ + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* PCI_RST# */ + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* + * each baseboard has 4 user configurable Digital IO lines which can + * be pinmuxed as a GPIO or in some cases a PWM + */ +struct dio_cfg { + iomux_v3_cfg_t gpio_padmux; + unsigned gpio_param; + iomux_v3_cfg_t pwm_padmux; + unsigned pwm_param; +}; + +struct ventana { + /* pinmux */ + iomux_v3_cfg_t const *gpio_pads; + int num_pads; + /* DIO pinmux/val */ + struct dio_cfg dio_cfg[4]; + /* various gpios (0 if non-existent) */ + int leds[3]; + int pcie_rst; + int mezz_pwren; + int mezz_irq; + int rs485en; + int gps_shdn; + int vidin_en; + int dioi2c_en; + int pcie_sson; + int usb_sel; +}; + +struct ventana gpio_cfg[] = { + /* GW5400proto */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9), + MX6_PAD_GPIO_9__PWM1_OUT, 1 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), + MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), + MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(4, 7), + .mezz_irq = IMX_GPIO_NR(4, 9), + .rs485en = IMX_GPIO_NR(3, 24), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + }, + + /* GW51xx */ + { + .gpio_pads = gw51xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw51xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18), + MX6_PAD_SD1_CMD__PWM4_OUT, 4 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 10), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 2), + .vidin_en = IMX_GPIO_NR(5, 20), + }, + + /* GW52xx */ + { + .gpio_pads = gw52xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw52xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), + 0, 0 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + .usb_sel = IMX_GPIO_NR(1, 2), + }, + + /* GW53xx */ + { + .gpio_pads = gw53xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw53xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16), + 0, 0 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), + MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), + 0, 0 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .gps_shdn = IMX_GPIO_NR(1, 27), + .vidin_en = IMX_GPIO_NR(3, 31), + }, + + /* GW54xx */ + { + .gpio_pads = gw54xx_gpio_pads, + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), + .dio_cfg = { + { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9), + MX6_PAD_GPIO_9__PWM1_OUT, 1 }, + { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), + MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, + { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), + MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, + { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), + MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, + }, + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 29), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .rs485en = IMX_GPIO_NR(7, 1), + .vidin_en = IMX_GPIO_NR(3, 31), + .dioi2c_en = IMX_GPIO_NR(4, 5), + .pcie_sson = IMX_GPIO_NR(1, 20), + }, +}; + +/* setup GPIO pinmux and default configuration per baseboard */ +static void setup_board_gpio(int board) +{ + struct ventana_board_info *info = &ventana_info; + const char *s; + char arg[10]; + size_t len; + int i; + int quiet = simple_strtol(getenv("quiet"), NULL, 10); + + if (board >= GW_UNKNOWN) + return; + + /* RS232_EN# */ + gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); + + /* MSATA Enable */ + if (is_cpu_type(MXC_CPU_MX6Q) && + test_bit(EECONFIG_SATA, info->config)) { + gpio_direction_output(GP_MSATA_SEL, + (hwconfig("msata")) ? 1 : 0); + } else { + gpio_direction_output(GP_MSATA_SEL, 0); + } + + /* + * assert PCI_RST# (released by OS when clock is valid) + * TODO: figure out why leaving this de-asserted from PCI scan on boot + * causes linux pcie driver to hang during enumeration + */ + gpio_direction_output(gpio_cfg[board].pcie_rst, 0); + + /* turn off (active-high) user LED's */ + for (i = 0; i < 4; i++) { + if (gpio_cfg[board].leds[i]) + gpio_direction_output(gpio_cfg[board].leds[i], 1); + } + + /* Expansion Mezzanine IO */ + gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); + gpio_direction_input(gpio_cfg[board].mezz_irq); + + /* RS485 Transmit Enable */ + if (gpio_cfg[board].rs485en) + gpio_direction_output(gpio_cfg[board].rs485en, 0); + + /* GPS_SHDN */ + if (gpio_cfg[board].gps_shdn) + gpio_direction_output(gpio_cfg[board].gps_shdn, 1); + + /* Analog video codec power enable */ + if (gpio_cfg[board].vidin_en) + gpio_direction_output(gpio_cfg[board].vidin_en, 1); + + /* DIOI2C_DIS# */ + if (gpio_cfg[board].dioi2c_en) + gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); + + /* PCICK_SSON: disable spread-spectrum clock */ + if (gpio_cfg[board].pcie_sson) + gpio_direction_output(gpio_cfg[board].pcie_sson, 0); + + /* USBOTG Select (PCISKT or FrontPanel) */ + if (gpio_cfg[board].usb_sel) + gpio_direction_output(gpio_cfg[board].usb_sel, 0); + + /* + * Configure DIO pinmux/padctl registers + * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions + */ + for (i = 0; i < 4; i++) { + struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; + unsigned ctrl = DIO_PAD_CTRL; + + sprintf(arg, "dio%d", i); + if (!hwconfig(arg)) + continue; + s = hwconfig_subarg(arg, "padctrl", &len); + if (s) + ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff; + if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { + if (!quiet) { + printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, + (cfg->gpio_param/32)+1, + cfg->gpio_param%32, + cfg->gpio_param); + } + imx_iomux_v3_setup_pad(cfg->gpio_padmux | + MUX_PAD_CTRL(ctrl)); + gpio_direction_input(cfg->gpio_param); + } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && + cfg->pwm_padmux) { + if (!quiet) + printf("DIO%d: pwm%d\n", i, cfg->pwm_param); + imx_iomux_v3_setup_pad(cfg->pwm_padmux | + MUX_PAD_CTRL(ctrl)); + } + } + + if (!quiet) { + if (is_cpu_type(MXC_CPU_MX6Q) && + (test_bit(EECONFIG_SATA, info->config))) { + printf("MSATA: %s\n", (hwconfig("msata") ? + "enabled" : "disabled")); + } + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + } +} + +#if defined(CONFIG_CMD_PCI) +int imx6_pcie_toggle_reset(void) +{ + if (board_type < GW_UNKNOWN) { + gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0); + mdelay(50); + gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1); + } + return 0; +} +#endif /* CONFIG_CMD_PCI */ + +#ifdef CONFIG_SERIAL_TAG +/* + * called when setting up ATAGS before booting kernel + * populate serialnum from the following (in order of priority): + * serial# env var + * eeprom + */ +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial = getenv("serial#"); + + if (serial) { + serialnr->high = 0; + serialnr->low = simple_strtoul(serial, NULL, 10); + } else if (ventana_info.model[0]) { + serialnr->high = 0; + serialnr->low = ventana_info.serial; + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif + +/* + * Board Support + */ + +int board_early_init_f(void) +{ + setup_iomux_uart(); + gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */ + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, + CONFIG_DDR_MB*1024*1024); + + return 0; +} + +int board_init(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUXC_GPR1_OTG_ID_MASK, + IOMUXC_GPR1_OTG_ID_GPIO1); + + /* address of linux boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + /* read Gateworks EEPROM into global struct (used later) */ + board_type = read_eeprom(); + + /* board-specifc GPIO iomux */ + if (board_type < GW_UNKNOWN) { + imx_iomux_v3_setup_multiple_pads(gw_gpio_pads, + ARRAY_SIZE(gw_gpio_pads)); + imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads, + gpio_cfg[board_type].num_pads); + } + + return 0; +} + +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) +/* + * called during late init (after relocation and after board_init()) + * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and + * EEPROM read. + */ +int checkboard(void) +{ + struct ventana_board_info *info = &ventana_info; + unsigned char buf[4]; + const char *p; + int quiet; /* Quiet or minimal output mode */ + + quiet = 0; + p = getenv("quiet"); + if (p) + quiet = simple_strtol(p, NULL, 10); + else + setenv("quiet", "0"); + + puts("\nGateworks Corporation Copyright 2014\n"); + if (info->model[0]) { + printf("Model: %s\n", info->model); + printf("MFGDate: %02x-%02x-%02x%02x\n", + info->mfgdate[0], info->mfgdate[1], + info->mfgdate[2], info->mfgdate[3]); + printf("Serial:%d\n", info->serial); + } else { + puts("Invalid EEPROM - board will not function fully\n"); + } + if (quiet) + return 0; + + /* Display GSC firmware revision/CRC/status */ + i2c_set_bus_num(I2C_GSC); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { + printf("GSC: v%d", buf[0]); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { + printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ + printf(" 0x%02x", buf[0]); /* irq status */ + } + puts("\n"); + } + /* Display RTC */ + if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { + printf("RTC: %d\n", + buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24); + } + + return 0; +} +#endif + +#ifdef CONFIG_CMD_BMODE +/* + * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 + * see Table 8-11 and Table 5-9 + * BOOT_CFG1[7] = 1 (boot from NAND) + * BOOT_CFG1[5] = 0 - raw NAND + * BOOT_CFG1[4] = 0 - default pad settings + * BOOT_CFG1[3:2] = 00 - devices = 1 + * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 + * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 + * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 + * BOOT_CFG2[0] = 0 - Reset time 12ms + */ +static const struct boot_mode board_boot_modes[] = { + /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + { NULL, 0 }, +}; +#endif + +/* late init */ +int misc_init_r(void) +{ + struct ventana_board_info *info = &ventana_info; + unsigned char reg; + + /* set env vars based on EEPROM data */ + if (ventana_info.model[0]) { + char str[16], fdt[36]; + char *p; + const char *cputype = ""; + int i; + + /* + * FDT name will be prefixed with CPU type. Three versions + * will be created each increasingly generic and bootloader + * env scripts will try loading each from most specific to + * least. + */ + if (is_cpu_type(MXC_CPU_MX6Q)) + cputype = "imx6q"; + else if (is_cpu_type(MXC_CPU_MX6DL)) + cputype = "imx6dl"; + memset(str, 0, sizeof(str)); + for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++) + str[i] = tolower(info->model[i]); + if (!getenv("model")) + setenv("model", str); + if (!getenv("fdt_file")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file", fdt); + } + p = strchr(str, '-'); + if (p) { + *p++ = 0; + + setenv("model_base", str); + if (!getenv("fdt_file1")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file1", fdt); + } + str[4] = 'x'; + str[5] = 'x'; + str[6] = 0; + if (!getenv("fdt_file2")) { + sprintf(fdt, "%s-%s.dtb", cputype, str); + setenv("fdt_file2", fdt); + } + } + + /* initialize env from EEPROM */ + if (test_bit(EECONFIG_ETH0, info->config) && + !getenv("ethaddr")) { + eth_setenv_enetaddr("ethaddr", info->mac0); + } + if (test_bit(EECONFIG_ETH1, info->config) && + !getenv("eth1addr")) { + eth_setenv_enetaddr("eth1addr", info->mac1); + } + + /* board serial-number */ + sprintf(str, "%6d", info->serial); + setenv("serial#", str); + } + + /* configure PFUZE100 PMIC (not used on all Ventana baseboards) */ + if ((board_type == GW54xx || board_type == GW54proto) && + !pmic_init(I2C_PMIC)) { + struct pmic *p = pmic_get("PFUZE100_PMIC"); + u32 reg; + if (p && !pmic_probe(p)) { + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set VGEN1 to 1.5V and enable */ + pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); + reg &= ~(LDO_VOL_MASK); + reg |= (LDOA_1_50V | LDO_EN); + pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); + + /* Set SWBST to 5.0V and enable */ + pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); + reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); + reg |= (SWBST_5_00V | SWBST_MODE_AUTO); + pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); + } + } + + /* setup baseboard specific GPIO pinmux and config */ + setup_board_gpio(board_type); + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + /* + * The Gateworks System Controller implements a boot + * watchdog (always enabled) as a workaround for IMX6 boot related + * errata such as: + * ERR005768 - no fix + * ERR006282 - fixed in silicon r1.3 + * ERR007117 - fixed in silicon r1.3 + * ERR007220 - fixed in silicon r1.3 + * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf + * + * Disable the boot watchdog and display/clear the timeout flag if set + */ + i2c_set_bus_num(I2C_GSC); + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) { + reg |= (1 << GSC_SC_CTRL1_WDDIS); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + puts("Error: could not disable GSC Watchdog\n"); + } else { + puts("Error: could not disable GSC Watchdog\n"); + } + if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { + if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ + puts("GSC boot watchdog timeout detected"); + reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ + gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); + } + } + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) + +/* FDT aliases associated with EEPROM config bits */ +const char *fdt_aliases[] = { + "ethernet0", + "ethernet1", + "hdmi_out", + "ahci0", + "pcie", + "ssi0", + "ssi1", + "lcd0", + "lvds0", + "lvds1", + "usb0", + "usb1", + "mmc0", + "mmc1", + "mmc2", + "mmc3", + "uart0", + "uart1", + "uart2", + "uart3", + "uart4", + "ipu0", + "ipu1", + "can0", + "mipi_dsi", + "mipi_csi", + "tzasc0", + "tzasc1", + "i2c0", + "i2c1", + "i2c2", + "vpu", + "csi0", + "csi1", + "caam", + NULL, + NULL, + NULL, + NULL, + NULL, + "spi0", + "spi1", + "spi2", + "spi3", + "spi4", + "spi5", + NULL, + NULL, + "pps", + NULL, + NULL, + NULL, + "hdmi_in", + "cvbs_out", + "cvbs_in", + "nand", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +/* + * called prior to booting kernel or by 'fdt boardsetup' command + * + * unless 'fdt_noauto' env var is set we will update the following in the DTB: + * - mtd partitions based on mtdparts/mtdids env + * - system-serial (board serial num from EEPROM) + * - board (full model from EEPROM) + * - peripherals removed from DTB if not loaded on board (per EEPROM config) + */ +void ft_board_setup(void *blob, bd_t *bd) +{ + int bit; + struct ventana_board_info *info = &ventana_info; + struct node_info nodes[] = { + { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + }; + const char *model = getenv("model"); + + if (getenv("fdt_noauto")) { + puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); + return; + } + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + + if (!model) { + puts("invalid board info: Leaving FDT fully enabled\n"); + return; + } + printf(" Adjusting FDT per EEPROM for %s...\n", model); + + /* board serial number */ + fdt_setprop(blob, 0, "system-serial", getenv("serial#"), + strlen(getenv("serial#") + 1)); + + /* board (model contains model from device-tree) */ + fdt_setprop(blob, 0, "board", info->model, + strlen((const char *)info->model) + 1); + + /* + * Peripheral Config: + * remove nodes by alias path if EEPROM config tells us the + * peripheral is not loaded on the board. + */ + for (bit = 0; bit < 64; bit++) { + if (!test_bit(bit, info->config)) + fdt_del_node_and_alias(blob, fdt_aliases[bit]); + } +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ + diff --git a/board/gateworks/gw_ventana/gw_ventana.cfg b/board/gateworks/gw_ventana/gw_ventana.cfg new file mode 100644 index 0000000000..27f09745c1 --- /dev/null +++ b/board/gateworks/gw_ventana/gw_ventana.cfg @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd, nand, sata + */ +#ifdef CONFIG_SPI_FLASH +BOOT_FROM spi +#else +BOOT_FROM nand +#endif + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +/* Memory configuration (size is overridden via eeprom config) */ +#include "../../boundary/nitrogen6x/ddr-setup.cfg" +#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024 + #include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg" +#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024 + #include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg" +#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512 + #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" +#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512 + #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" +#else + #error "Unsupported CPU/Memory configuration" +#endif +#include "clocks.cfg" diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h new file mode 100644 index 0000000000..d310bfd994 --- /dev/null +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _VENTANA_EEPROM_ +#define _VENTANA_EEPROM_ + +struct ventana_board_info { + u8 mac0[6]; /* 0x00: MAC1 */ + u8 mac1[6]; /* 0x06: MAC2 */ + u8 res0[12]; /* 0x0C: reserved */ + u32 serial; /* 0x18: Serial Number (read only) */ + u8 res1[4]; /* 0x1C: reserved */ + u8 mfgdate[4]; /* 0x20: MFG date (read only) */ + u8 res2[7]; /* 0x24 */ + /* sdram config */ + u8 sdram_size; /* 0x2B: enum (512,1024,2048) MB */ + u8 sdram_speed; /* 0x2C: enum (100,133,166,200,267,333,400) MHz */ + u8 sdram_width; /* 0x2D: enum (32,64) bit */ + /* cpu config */ + u8 cpu_speed; /* 0x2E: enum (800,1000,1200) MHz */ + u8 cpu_type; /* 0x2F: enum (imx6q,imx6d,imx6dl,imx6s) */ + u8 model[16]; /* 0x30: model string */ + /* FLASH config */ + u8 nand_flash_size; /* 0x40: enum (4,8,16,32,64,128) MB */ + u8 spi_flash_size; /* 0x41: enum (4,8,16,32,64,128) MB */ + + /* Config1: SoC Peripherals */ + u8 config[8]; /* 0x42: loading options */ + + u8 res3[4]; /* 0x4A */ + + u8 chksum[2]; /* 0x4E */ +}; + +/* config bits */ +enum { + EECONFIG_ETH0, + EECONFIG_ETH1, + EECONFIG_HDMI_OUT, + EECONFIG_SATA, + EECONFIG_PCIE, + EECONFIG_SSI0, + EECONFIG_SSI1, + EECONFIG_LCD, + EECONFIG_LVDS0, + EECONFIG_LVDS1, + EECONFIG_USB0, + EECONFIG_USB1, + EECONFIG_SD0, + EECONFIG_SD1, + EECONFIG_SD2, + EECONFIG_SD3, + EECONFIG_UART0, + EECONFIG_UART1, + EECONFIG_UART2, + EECONFIG_UART3, + EECONFIG_UART4, + EECONFIG_IPU0, + EECONFIG_IPU1, + EECONFIG_FLEXCAN, + EECONFIG_MIPI_DSI, + EECONFIG_MIPI_CSI, + EECONFIG_TZASC0, + EECONFIG_TZASC1, + EECONFIG_I2C0, + EECONFIG_I2C1, + EECONFIG_I2C2, + EECONFIG_VPU, + EECONFIG_CSI0, + EECONFIG_CSI1, + EECONFIG_CAAM, + EECONFIG_MEZZ, + EECONFIG_RES1, + EECONFIG_RES2, + EECONFIG_RES3, + EECONFIG_RES4, + EECONFIG_ESPCI0, + EECONFIG_ESPCI1, + EECONFIG_ESPCI2, + EECONFIG_ESPCI3, + EECONFIG_ESPCI4, + EECONFIG_ESPCI5, + EECONFIG_RES5, + EECONFIG_RES6, + EECONFIG_GPS, + EECONFIG_SPIFL0, + EECONFIG_SPIFL1, + EECONFIG_GSPBATT, + EECONFIG_HDMI_IN, + EECONFIG_VID_OUT, + EECONFIG_VID_IN, + EECONFIG_NAND, + EECONFIG_RES8, + EECONFIG_RES9, + EECONFIG_RES10, + EECONFIG_RES11, + EECONFIG_RES12, + EECONFIG_RES13, + EECONFIG_RES14, + EECONFIG_RES15, +}; + +#endif diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index b5987fde39..9ed2837a78 100644 --- a/board/matrix_vision/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile @@ -8,7 +8,7 @@ obj-y := mvblm7.o pci.o fpga.o extra-y := bootscript.img -quiet_cmd_mkimage = UIMAGE $@ +quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile index fae7ec23b9..a9c794e21a 100644 --- a/board/matrix_vision/mvsmr/Makefile +++ b/board/matrix_vision/mvsmr/Makefile @@ -12,7 +12,7 @@ obj-y := mvsmr.o fpga.o extra-y := bootscript.img -quiet_cmd_mkimage = UIMAGE $@ +quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 8c05a1517c..9dcd5e42af 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -132,8 +132,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, OUTPUT), /* I2C3 pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* VI pinmux */ VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), @@ -145,8 +145,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { VI_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTD pinmux */ DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), @@ -224,8 +224,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW9, UARTA, NORMAL, NORMAL, OUTPUT), /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* SYSCLK pinmux */ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), @@ -252,8 +252,8 @@ static struct pingroup_config tegra114_pinmux_common[] = { DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTB pinmux */ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index 50868e6488..b3d68d589a 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -124,12 +124,12 @@ static struct pingroup_config tegra124_pinmux_common[] = { DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT), /* I2C3 (TPM) pinmux */ - I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* I2C2 pinmux */ - I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTD pinmux (UART4 on Servo board, unused) */ DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT), @@ -198,8 +198,8 @@ static struct pingroup_config tegra124_pinmux_common[] = { DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT), /* I2CPWR pinmux (I2C5) */ - I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* RTCK pinmux */ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT), @@ -223,8 +223,8 @@ static struct pingroup_config tegra124_pinmux_common[] = { DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), /* I2C1 pinmux */ - I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), - I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), /* UARTB, GPS */ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index fb4acf3641..2804d9133d 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -76,7 +76,7 @@ int board_init(void) { /* LED (PTG) */ - outw((inw(PGCR) & ~0xFF) | 0x66, PGCR); + outw((inw(PGCR) & ~0xFF) | 0x55, PGCR); outw((inw(HIZCRA) & ~0x02), HIZCRA); debug_led(1 << 0); @@ -97,7 +97,7 @@ int board_init(void) /* USB host */ outw((inw(PBCR) & ~0x300) | 0x100, PBCR); outb((inb(PBDR) & ~0x10) | 0x10, PBDR); - outl(inl(MSTPCR2) & 0x100000, MSTPCR2); + outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); outw(0x0600, UPONCR0); debug_led(1 << 3); diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 3866495259..de154e0f64 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -22,10 +22,25 @@ #include <asm/arch/power.h> #include <power/pmic.h> #include <asm/arch/sromc.h> -#include <power/max77686_pmic.h> +#include <lcd.h> +#include <samsung/misc.h> DECLARE_GLOBAL_DATA_PTR; +int __exynos_early_init_f(void) +{ + return 0; +} +int exynos_early_init_f(void) + __attribute__((weak, alias("__exynos_early_init_f"))); + +int __exynos_power_init(void) +{ + return 0; +} +int exynos_power_init(void) + __attribute__((weak, alias("__exynos_power_init"))); + #if defined CONFIG_EXYNOS_TMU /* Boot Time Thermal Analysis for SoC temperature threshold breach */ static void boot_temp_check(void) @@ -133,139 +148,21 @@ int board_early_init_f(void) board_i2c_init(gd->fdt_blob); #endif - return err; + return exynos_early_init_f(); } #endif #if defined(CONFIG_POWER) -#ifdef CONFIG_POWER_MAX77686 -static int pmic_reg_update(struct pmic *p, int reg, uint regval) -{ - u32 val; - int ret = 0; - - ret = pmic_reg_read(p, reg, &val); - if (ret) { - debug("%s: PMIC %d register read failed\n", __func__, reg); - return -1; - } - val |= regval; - ret = pmic_reg_write(p, reg, val); - if (ret) { - debug("%s: PMIC %d register write failed\n", __func__, reg); - return -1; - } - return 0; -} - -static int max77686_init(void) -{ - struct pmic *p; - - if (pmic_init(I2C_PMIC)) - return -1; - - p = pmic_get("MAX77686_PMIC"); - if (!p) - return -ENODEV; - - if (pmic_probe(p)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) - return -1; - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, - MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) - return -1; - - /* VDD_MIF */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, - MAX77686_BUCK1OUT_1V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK1OUT); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, - MAX77686_BUCK1CTRL_EN)) - return -1; - - /* VDD_ARM */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, - MAX77686_BUCK2DVS1_1_3V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK2DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, - MAX77686_BUCK2CTRL_ON)) - return -1; - - /* VDD_INT */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, - MAX77686_BUCK3DVS1_1_0125V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK3DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_G3D */ - if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, - MAX77686_BUCK4DVS1_1_2V)) { - debug("%s: PMIC %d register write failed\n", __func__, - MAX77686_REG_PMIC_BUCK4DVS1); - return -1; - } - - if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, - MAX77686_BUCK3CTRL_ON)) - return -1; - - /* VDD_LDO2 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, - MAX77686_LD02CTRL1_1_5V | EN_LDO)) - return -1; - - /* VDD_LDO3 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, - MAX77686_LD03CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO5 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, - MAX77686_LD05CTRL1_1_8V | EN_LDO)) - return -1; - - /* VDD_LDO10 */ - if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, - MAX77686_LD10CTRL1_1_8V | EN_LDO)) - return -1; - - return 0; -} -#endif - int power_init_board(void) { - int ret = 0; - set_ps_hold_ctrl(); -#ifdef CONFIG_POWER_MAX77686 - ret = max77686_init(); -#endif - - return ret; + return exynos_power_init(); } #endif #ifdef CONFIG_OF_CONTROL +#ifdef CONFIG_SMC911X static int decode_sromc(const void *blob, struct fdt_sromc *config) { int err; @@ -289,6 +186,7 @@ static int decode_sromc(const void *blob, struct fdt_sromc *config) } return 0; } +#endif int board_eth_init(bd_t *bis) { @@ -346,15 +244,35 @@ int board_mmc_init(bd_t *bis) { int ret; +#ifdef CONFIG_SDHCI + /* mmc initializattion for available channels */ + ret = exynos_mmc_init(gd->fdt_blob); + if (ret) + debug("mmc init failed\n"); +#endif +#ifdef CONFIG_DWMMC /* dwmmc initializattion for available channels */ ret = exynos_dwmmc_init(gd->fdt_blob); if (ret) debug("dwmmc init failed\n"); +#endif return ret; } #endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + const char *board_name; + + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + printf("Board: %s\n", board_name ? board_name : "unknown"); + + return 0; +} #endif +#endif /* CONFIG_OF_CONTROL */ #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) @@ -386,3 +304,21 @@ int arch_early_init_r(void) return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + set_board_info(); +#endif +#ifdef CONFIG_LCD_MENU + keys_init(); + check_boot_mode(); +#endif +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index 15f77cacbd..d502f02d3d 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -11,129 +11,35 @@ #include <asm/arch/mmc.h> #include <asm/arch/periph.h> #include <asm/arch/pinmux.h> +#include <usb.h> DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; -int board_init(void) +u32 get_board_rev(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } -static int board_uart_init(void) +int exynos_init(void) { - int err; - - err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); - if (err) { - debug("UART0 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); - if (err) { - debug("UART1 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); - if (err) { - debug("UART2 not configured\n"); - return err; - } - - err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - if (err) { - debug("UART3 not configured\n"); - return err; - } - return 0; } -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - int err; - err = board_uart_init(); - if (err) { - debug("UART init failed\n"); - return err; - } - return err; -} -#endif - -int dram_init(void) +int board_usb_init(int index, enum usb_init_type init) { - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) - + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) - + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) - + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ - PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ - PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ - PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ - PHYS_SDRAM_4_SIZE); -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) +#ifdef CONFIG_USB_CABLE_CHECK +int usb_cable_connected(void) { - printf("\nBoard: ORIGEN\n"); return 0; } #endif -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) +#ifdef CONFIG_BOARD_EARLY_INIT_F +int exynos_early_init_f(void) { - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPK2[0] SD_2_CLK(2) - * GPK2[1] SD_2_CMD(2) - * GPK2[2] SD_2_CDn - * GPK2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); - - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); - } - - err = s5p_mmc_init(2, 4); - return err; + return 0; } #endif diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index c83b0341c5..379a45cc23 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -44,21 +44,6 @@ int exynos_init(void) return 0; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); - - return 0; -} -#endif - #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index a69f73d5e8..28a6d9e718 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -147,6 +147,131 @@ void board_i2c_init(const void *blob) } } +#if defined(CONFIG_POWER) +#ifdef CONFIG_POWER_MAX77686 +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + +static int max77686_init(void) +{ + struct pmic *p; + + if (pmic_init(I2C_PMIC)) + return -1; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; +} +#endif /* CONFIG_POWER_MAX77686 */ + +int exynos_power_init(void) +{ + int ret = 0; + +#ifdef CONFIG_POWER_MAX77686 + ret = max77686_init(); +#endif + return ret; +} +#endif /* CONFIG_POWER */ + #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 3ad2ad0e56..e4606ecd2a 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -142,18 +142,3 @@ int board_get_revision(void) { return 0; } - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - const char *board_name; - - board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (board_name == NULL) - printf("\nUnknown Board\n"); - else - printf("\nBoard: %s\n", board_name); - - return 0; -} -#endif diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index b72550538a..7c79e7b73a 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -12,23 +12,20 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/clock.h> -#include <asm/arch/clk.h> #include <asm/arch/mipi_dsim.h> #include <asm/arch/watchdog.h> #include <asm/arch/power.h> #include <power/pmic.h> #include <usb/s3c_udc.h> #include <power/max8997_pmic.h> -#include <libtizen.h> #include <power/max8997_muic.h> #include <power/battery.h> #include <power/max17042_fg.h> +#include <libtizen.h> #include <usb.h> #include <usb_mass_storage.h> -#include <samsung/misc.h> #include "setup.h" @@ -46,10 +43,8 @@ u32 get_board_rev(void) static void check_hw_revision(void); struct s3c_plat_otg_data s5pc210_otg_data; -int board_init(void) +int exynos_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR; - check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); @@ -281,7 +276,7 @@ static int pmic_init_max8997(void) return 0; } -int power_init_board(void) +int exynos_power_init(void) { int chrg, ret; struct power_battery *pb; @@ -350,28 +345,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -} - static unsigned int get_hw_revision(void) { struct exynos4_gpio_part1 *gpio = @@ -404,55 +377,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tTRATS\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int err; - - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ - s5p_gpio_direction_output(&gpio->k0, 2, 1); - s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE); - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; -} -#endif #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) @@ -599,38 +523,22 @@ static void board_power_init(void) writel(0, (unsigned int)&pwr->arm_core1_configuration); } -static void board_uart_init(void) +static void exynos_uart_init(void) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - int i; - - /* - * UART2 GPIOs - * GPA1CON[0] = UART_2_RXD(2) - * GPA1CON[1] = UART_2_TXD(2) - * GPA1CON[2] = I2C_3_SDA (3) - * GPA1CON[3] = I2C_3_SCL (3) - */ - - for (i = 0; i < 4; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); - } /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); s5p_gpio_direction_output(&gpio2->y4, 7, 1); } -int board_early_init_f(void) +int exynos_early_init_f(void) { wdt_stop(); pmic_reset(); board_clock_init(); - board_uart_init(); + exynos_uart_init(); board_power_init(); return 0; @@ -648,7 +556,7 @@ void exynos_reset_lcd(void) s5p_gpio_direction_output(&gpio2->y4, 5, 1); } -static int lcd_power(void) +int lcd_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -671,46 +579,7 @@ static int lcd_power(void) return 0; } -static struct mipi_dsim_config dsim_config = { - .e_interface = DSIM_VIDEO, - .e_virtual_ch = DSIM_VIRTUAL_CH_0, - .e_pixel_format = DSIM_24BPP_888, - .e_burst_mode = DSIM_BURST_SYNC_EVENT, - .e_no_data_lane = DSIM_DATA_LANE_4, - .e_byte_clk = DSIM_PLL_OUT_DIV8, - .hfp = 1, - - .p = 3, - .m = 120, - .s = 1, - - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ - .pll_stable_time = 500, - - /* escape clk : 10MHz */ - .esc_clk = 20 * 1000000, - - /* stop state holding counter after bta change count 0 ~ 0xfff */ - .stop_holding_cnt = 0x7ff, - /* bta timeout 0 ~ 0xff */ - .bta_timeout = 0xff, - /* lp rx timeout 0 ~ 0xffff */ - .rx_timeout = 0xffff, -}; - -static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { - .lcd_panel_info = NULL, - .dsim_config = &dsim_config, -}; - -static struct mipi_dsim_lcd_device mipi_lcd_device = { - .name = "s6e8ax0", - .id = -1, - .bus_id = 0, - .platform_data = (void *)&s6e8ax0_platform_data, -}; - -static int mipi_power(void) +int mipi_power(void) { int ret = 0; struct pmic *p = pmic_get("MAX8997_PMIC"); @@ -733,75 +602,13 @@ static int mipi_power(void) return 0; } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 720, - .vl_row = 1280, - .vl_width = 720, - .vl_height = 1280, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ - - /* s6e8ax0 Panel infomation */ - .vl_hspw = 5, - .vl_hbpd = 10, - .vl_hfpd = 10, - - .vl_vspw = 2, - .vl_vbpd = 1, - .vl_vfpd = 13, - .vl_cmd_allow_len = 0xf, - - .win_id = 3, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 0, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 1, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_misc_init(vidinfo_t *vid) { - vid->logo_on = 1, - vid->resolution = HD_RESOLUTION, - vid->rgb_mode = MODE_RGB_P, - #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif - mipi_lcd_device.reverse_panel = 1; - - strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); - s6e8ax0_platform_data.lcd_power = lcd_power; - s6e8ax0_platform_data.mipi_power = mipi_power; - s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; - s6e8ax0_platform_data.lcd_panel_info = (void *)vid; - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); +#ifdef CONFIG_S6E8AX0 s6e8ax0_init(); - exynos_set_dsim_platform_data(&s6e8ax0_platform_data); - setenv("lcdinfo", "lcd=s6e8ax0"); -} - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif -#ifdef CONFIG_LCD_MENU - keys_init(); - check_boot_mode(); #endif -#ifdef CONFIG_CMD_BMP - if (panel_info.logo_on) - draw_logo(); -#endif - return 0; } -#endif diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index c17c24d60a..f558ef97a9 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -8,15 +8,9 @@ #include <common.h> #include <lcd.h> -#include <asm/io.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> -#include <asm/arch/power.h> -#include <asm/arch/clk.h> -#include <asm/arch/clock.h> -#include <asm/arch/mipi_dsim.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> +#include <asm/arch/mipi_dsim.h> #include <power/pmic.h> #include <power/max77686_pmic.h> #include <power/battery.h> @@ -28,7 +22,6 @@ #include <usb.h> #include <usb/s3c_udc.h> #include <usb_mass_storage.h> -#include <samsung/misc.h> DECLARE_GLOBAL_DATA_PTR; @@ -69,16 +62,6 @@ static void check_hw_revision(void) board_rev = modelrev << 8; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tTRATS2\n"); - printf("HW Revision:\t0x%04x\n", board_rev); - - return 0; -} -#endif - u32 get_board_rev(void) { return board_rev; @@ -156,33 +139,37 @@ int get_soft_i2c_sda_pin(void) } #endif -int board_early_init_f(void) +int exynos_early_init_f(void) { - check_hw_revision(); board_external_gpio_init(); - gd->flags |= GD_FLG_DISABLE_CONSOLE; - return 0; } static int pmic_init_max77686(void); -int board_init(void) +int exynos_init(void) { struct exynos4_power *pwr = (struct exynos4_power *)samsung_get_base_power(); - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + check_hw_revision(); + printf("HW Revision:\t0x%04x\n", board_rev); - /* workaround: clear INFORM4..5 */ - writel(0, (unsigned int)&pwr->inform4); - writel(0, (unsigned int)&pwr->inform5); + /* + * First bootloader on the TRATS2 platform uses + * INFORM4 and INFORM5 registers for recovery + * + * To indicate correct boot chain - those two + * registers must be cleared out + */ + writel(0, &pwr->inform4); + writel(0, &pwr->inform5); return 0; } -int power_init_board(void) +int exynos_power_init(void) { int chrg; struct power_battery *pb; @@ -248,90 +235,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - u32 size_mb; - - size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20; - - gd->ram_size = size_mb << 20; - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; -} - -int board_mmc_init(bd_t *bis) -{ - int err0, err2 = 0; - - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ - s5p_gpio_direction_output(&gpio2->k0, 2, 1); - s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); - - /* - * eMMC GPIO: - * SDR 8-bit@48MHz at MMC0 - * GPK0[0] SD_0_CLK(2) - * GPK0[1] SD_0_CMD(2) - * GPK0[2] SD_0_CDn -> Not used - * GPK0[3:6] SD_0_DATA[0:3](2) - * GPK1[3:6] SD_0_DATA[0:3](3) - * - * DDR 4-bit@26MHz at MMC4 - * GPK0[0] SD_4_CLK(3) - * GPK0[1] SD_4_CMD(3) - * GPK0[2] SD_4_CDn -> Not used - * GPK0[3:6] SD_4_DATA[0:3](3) - * GPK1[3:6] SD_4_DATA[4:7](4) - */ - - err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - if (err0) - debug("SDMMC0 not configured\n"); - else - err0 = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err2) - debug("SDMMC2 not configured\n"); - else - err2 = s5p_mmc_init(2, 4); - } - - return err0 & err2; -} - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { @@ -479,46 +382,7 @@ static int pmic_init_max77686(void) */ #ifdef CONFIG_LCD -static struct mipi_dsim_config dsim_config = { - .e_interface = DSIM_VIDEO, - .e_virtual_ch = DSIM_VIRTUAL_CH_0, - .e_pixel_format = DSIM_24BPP_888, - .e_burst_mode = DSIM_BURST_SYNC_EVENT, - .e_no_data_lane = DSIM_DATA_LANE_4, - .e_byte_clk = DSIM_PLL_OUT_DIV8, - .hfp = 1, - - .p = 3, - .m = 120, - .s = 1, - - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ - .pll_stable_time = 500, - - /* escape clk : 10MHz */ - .esc_clk = 20 * 1000000, - - /* stop state holding counter after bta change count 0 ~ 0xfff */ - .stop_holding_cnt = 0x7ff, - /* bta timeout 0 ~ 0xff */ - .bta_timeout = 0xff, - /* lp rx timeout 0 ~ 0xffff */ - .rx_timeout = 0xffff, -}; - -static struct exynos_platform_mipi_dsim dsim_platform_data = { - .lcd_panel_info = NULL, - .dsim_config = &dsim_config, -}; - -static struct mipi_dsim_lcd_device mipi_lcd_device = { - .name = "s6e8ax0", - .id = -1, - .bus_id = 0, - .platform_data = (void *)&dsim_platform_data, -}; - -static int mipi_power(void) +int mipi_power(void) { struct pmic *p = pmic_get("MAX77686_PMIC"); @@ -556,77 +420,13 @@ void exynos_reset_lcd(void) s5p_gpio_set_value(&gpio1->f2, 1, 1); } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 720, - .vl_row = 1280, - .vl_width = 720, - .vl_height = 1280, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */ - - /* s6e8ax0 Panel infomation */ - .vl_hspw = 5, - .vl_hbpd = 10, - .vl_hfpd = 10, - - .vl_vspw = 2, - .vl_vbpd = 1, - .vl_vfpd = 13, - .vl_cmd_allow_len = 0xf, - .mipi_enabled = 1, - - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 25, - .reset_delay = 0, - .interface_mode = FIMD_RGB_INTERFACE, -}; - -void init_panel_info(vidinfo_t *vid) +void exynos_lcd_misc_init(vidinfo_t *vid) { - vid->logo_on = 1; - vid->resolution = HD_RESOLUTION; - vid->rgb_mode = MODE_RGB_P; - - vid->power_on_delay = 30; - - mipi_lcd_device.reverse_panel = 1; - #ifdef CONFIG_TIZEN get_tizen_logo_info(vid); #endif - - strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name); - dsim_platform_data.mipi_power = mipi_power; - dsim_platform_data.phy_enable = set_mipi_phy_ctrl; - dsim_platform_data.lcd_panel_info = (void *)vid; - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); - +#ifdef CONFIG_S6E8AX0 s6e8ax0_init(); - - exynos_set_dsim_platform_data(&dsim_platform_data); -} -#endif /* LCD */ - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif -#ifdef CONFIG_LCD_MENU - keys_init(); - check_boot_mode(); #endif -#ifdef CONFIG_CMD_BMP - if (panel_info.logo_on) - draw_logo(); -#endif - return 0; } -#endif +#endif /* LCD */ diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 96da7e0861..f9d71b617d 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -13,16 +13,17 @@ #include <asm/gpio.h> #include <asm/arch/adc.h> #include <asm/arch/gpio.h> -#include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> #include <asm/arch/watchdog.h> -#include <libtizen.h> #include <ld9040.h> #include <power/pmic.h> +#include <usb.h> #include <usb/s3c_udc.h> #include <asm/arch/cpu.h> #include <power/max8998_pmic.h> +#include <libtizen.h> #include <samsung/misc.h> +#include <usb_mass_storage.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,7 +43,7 @@ static int get_hwrev(void) static void init_pmic_lcd(void); -int power_init_board(void) +int exynos_power_init(void) { int ret; @@ -59,22 +60,6 @@ int power_init_board(void) return 0; } -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; -} - static unsigned short get_adc_value(int channel) { struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); @@ -159,71 +144,6 @@ static void check_hw_revision(void) board_rev |= hwrev; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - puts("Board:\tUniversal C210\n"); - return 0; -} -#endif - -#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) -{ - int err; - - switch (get_hwrev()) { - case 0: - /* - * Set the low to enable LDO_EN - * But when you use the test board for eMMC booting - * you should set it HIGH since it removes the inverter - */ - /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - s5p_gpio_direction_output(&gpio1->e3, 6, 0); - break; - default: - /* - * Default reset state is High and there's no inverter - * But set it as HIGH to ensure - */ - /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - s5p_gpio_direction_output(&gpio1->e1, 3, 1); - break; - } - - /* - * MMC device init - * mmc0 : eMMC (8-bit buswidth) - * mmc2 : SD card (4-bit buswidth) - */ - err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); - if (err) - debug("SDMMC0 not configured\n"); - else - err = s5p_mmc_init(0, 8); - - /* T-flash detect */ - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); - - /* - * Check the T-flash detect pin - * GPX3[4] T-flash detect pin - */ - if (!s5p_gpio_get_value(&gpio2->x3, 4)) { - err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); - if (err) - debug("SDMMC2 not configured\n"); - else - err = s5p_mmc_init(2, 4); - } - - return err; - -} -#endif - #ifdef CONFIG_USB_GADGET static int s5pc210_phy_control(int on) { @@ -271,7 +191,20 @@ struct s3c_plat_otg_data s5pc210_otg_data = { }; #endif -int board_early_init_f(void) +int board_usb_init(int index, enum usb_init_type init) +{ + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc210_otg_data); +} + +#ifdef CONFIG_USB_CABLE_CHECK +int usb_cable_connected(void) +{ + return 0; +} +#endif + +int exynos_early_init_f(void) { wdt_stop(); @@ -412,6 +345,11 @@ void exynos_cfg_lcd_gpio(void) spi_init(); } +int mipi_power(void) +{ + return 0; +} + void exynos_reset_lcd(void) { s5p_gpio_set_value(&gpio2->y4, 5, 1); @@ -436,39 +374,6 @@ void exynos_lcd_power_on(void) pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON); } -vidinfo_t panel_info = { - .vl_freq = 60, - .vl_col = 480, - .vl_row = 800, - .vl_width = 480, - .vl_height = 800, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_hsp = CONFIG_SYS_HIGH, - .vl_vsp = CONFIG_SYS_HIGH, - .vl_dp = CONFIG_SYS_HIGH, - - .vl_bpix = 4, /* Bits per pixel */ - - /* LD9040 LCD Panel */ - .vl_hspw = 2, - .vl_hbpd = 16, - .vl_hfpd = 16, - - .vl_vspw = 2, - .vl_vbpd = 8, - .vl_vfpd = 8, - .vl_cmd_allow_len = 0xf, - - .win_id = 0, - .dual_lcd_enabled = 0, - - .init_delay = 0, - .power_on_delay = 10000, - .reset_delay = 10000, - .interface_mode = FIMD_RGB_INTERFACE, - .mipi_enabled = 0, -}; - void exynos_cfg_ldo(void) { ld9040_cfg_ldo(); @@ -479,30 +384,32 @@ void exynos_enable_ldo(unsigned int onoff) ld9040_enable_ldo(onoff); } -void init_panel_info(vidinfo_t *vid) -{ - vid->logo_on = 1; - vid->resolution = HD_RESOLUTION; - vid->rgb_mode = MODE_RGB_P; - -#ifdef CONFIG_TIZEN - get_tizen_logo_info(vid); -#endif - - /* for LD9040. */ - vid->pclk_name = 1; /* MPLL */ - vid->sclk_div = 1; - - setenv("lcdinfo", "lcd=ld9040"); -} - -int board_init(void) +int exynos_init(void) { gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + switch (get_hwrev()) { + case 0: + /* + * Set the low to enable LDO_EN + * But when you use the test board for eMMC booting + * you should set it HIGH since it removes the inverter + */ + /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ + s5p_gpio_direction_output(&gpio1->e3, 6, 0); + break; + default: + /* + * Default reset state is High and there's no inverter + * But set it as HIGH to ensure + */ + /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ + s5p_gpio_direction_output(&gpio1->e1, 3, 1); + break; + } #ifdef CONFIG_SOFT_SPI soft_spi_init(); @@ -513,20 +420,15 @@ int board_init(void) return 0; } -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) +void exynos_lcd_misc_init(vidinfo_t *vid) { -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - set_board_info(); -#endif -#ifdef CONFIG_LCD_MENU - keys_init(); - check_boot_mode(); -#endif -#ifdef CONFIG_CMD_BMP - if (panel_info.logo_on) - draw_logo(); +#ifdef CONFIG_TIZEN + get_tizen_logo_info(vid); #endif - return 0; + + /* for LD9040. */ + vid->pclk_name = 1; /* MPLL */ + vid->sclk_div = 1; + + setenv("lcdinfo", "lcd=ld9040"); } -#endif diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 217237900e..38ac93d795 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -232,13 +232,6 @@ int board_eth_init(bd_t *bis) factoryset_setenv(); - /* Reset SMSC LAN9303 switch for default configuration */ - gpio_request(GPIO_LAN9303_NRST, "nRST"); - gpio_direction_output(GPIO_LAN9303_NRST, 0); - /* assert active low reset for 200us */ - udelay(200); - gpio_set_value(GPIO_LAN9303_NRST, 1); - /* Set rgmii mode and enable rmii clock to be sourced from chip */ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); @@ -249,6 +242,25 @@ int board_eth_init(bd_t *bis) n += rv; return n; } + +static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + /* Reset SMSC LAN9303 switch for default configuration */ + gpio_request(GPIO_LAN9303_NRST, "nRST"); + gpio_direction_output(GPIO_LAN9303_NRST, 0); + /* assert active low reset for 200us */ + udelay(200); + gpio_set_value(GPIO_LAN9303_NRST, 1); + + return 0; +}; + +U_BOOT_CMD( + switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset, + "Reset LAN9303 switch via its reset pin", + "" +); #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c index 8672803871..c7f90c4400 100644 --- a/board/synopsys/axs101/nand.c +++ b/board/synopsys/axs101/nand.c @@ -107,6 +107,10 @@ static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf, writel(bbstate.bounce_buffer, &bd->buffer_ptr0); writel(0, &bd->buffer_ptr1); + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)bd, + (unsigned long)bd + sizeof(struct nand_bd)); + /* Issue "write" command */ NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1)); @@ -137,6 +141,10 @@ static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) writel(bbstate.bounce_buffer, &bd->buffer_ptr0); writel(0, &bd->buffer_ptr1); + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)bd, + (unsigned long)bd + sizeof(struct nand_bd)); + /* Issue "read" command */ NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1)); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7609a18368..554398f346 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -573,8 +573,22 @@ static struct cpsw_platform_data cpsw_data = { }; #endif -#if defined(CONFIG_DRIVER_TI_CPSW) || \ - (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +/* + * This function will: + * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr + * in the environment + * Perform fixups to the PHY present on certain boards. We only need this + * function in: + * - SPL with either CPSW or USB ethernet support + * - Full U-Boot, with either CPSW or USB ethernet + * Build in only these cases to avoid warnings about unused variables + * when we build an SPL that has neither option but full U-Boot will. + */ +#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ + && defined(CONFIG_SPL_BUILD)) || \ + ((defined(CONFIG_DRIVER_TI_CPSW) || \ + defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ + !defined(CONFIG_SPL_BUILD)) int board_eth_init(bd_t *bis) { int rv, n = 0; diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index ceb20226ff..a9e3d34df9 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -118,6 +118,7 @@ SECTIONS .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } .hash : { *(.hash*) } + .gnu.hash : { *(.gnu.hash) } .plt : { *(.plt*) } .interp : { *(.interp*) } .gnu : { *(.gnu*) } diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README index 2fdaeac31e..533da01a34 100644 --- a/board/ti/dra7xx/README +++ b/board/ti/dra7xx/README @@ -23,3 +23,4 @@ U-Boot # tftp ${loadaddr} dra7xx/u-boot.img U-Boot # mmc write ${loadaddr} 300 400 U-Boot # mmc bootbus 1 2 0 2 U-Boot # mmc partconf 1 1 1 0 +U-Boot # mmc rst-function 1 1 diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 050845777d..f1951dc5ef 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -25,6 +25,8 @@ #include <miiphy.h> #include <netdev.h> #include <linux/fb.h> +#include <phy.h> +#include <input.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,7 +57,7 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const usdhc1_pads[] = { +static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), diff --git a/boards.cfg b/boards.cfg index 69c893630a..b4203f1b57 100644 --- a/boards.cfg +++ b/boards.cfg @@ -322,6 +322,11 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com> +Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com> Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com> Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com> Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com> diff --git a/common/Makefile b/common/Makefile index c49a0af28d..7c853ae442 100644 --- a/common/Makefile +++ b/common/Makefile @@ -160,6 +160,9 @@ obj-$(CONFIG_CMD_UBI) += cmd_ubi.o obj-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o obj-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o obj-$(CONFIG_CMD_UNZIP) += cmd_unzip.o +ifdef CONFIG_LZMA +obj-$(CONFIG_CMD_LZMADEC) += cmd_lzmadec.o +endif ifdef CONFIG_CMD_USB obj-y += cmd_usb.o obj-y += usb.o usb_hub.o diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index 39248054f8..fad462fb34 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -389,8 +389,13 @@ void eeprom_init (void) #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) spi_init_f (); #endif -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) || \ + defined(CONFIG_SYS_I2C) +#ifdef CONFIG_SYS_I2C + i2c_init_all(); +#else + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif #endif } diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c index 1f12e6deb6..e38422d792 100644 --- a/common/cmd_gpt.c +++ b/common/cmd_gpt.c @@ -29,30 +29,53 @@ * * @return - zero on successful expand and env is set */ -static char extract_env(const char *str, char **env) +static int extract_env(const char *str, char **env) { + int ret = -1; char *e, *s; +#ifdef CONFIG_RANDOM_UUID + char uuid_str[UUID_STR_LEN + 1]; +#endif if (!str || strlen(str) < 4) return -1; - if ((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}')) { - s = strdup(str); - if (s == NULL) - return -1; - memset(s + strlen(s) - 1, '\0', 1); - memmove(s, s + 2, strlen(s) - 1); + if (!((strncmp(str, "${", 2) == 0) && (str[strlen(str) - 1] == '}'))) + return -1; + + s = strdup(str); + if (s == NULL) + return -1; + + memset(s + strlen(s) - 1, '\0', 1); + memmove(s, s + 2, strlen(s) - 1); + + e = getenv(s); + if (e == NULL) { +#ifdef CONFIG_RANDOM_UUID + debug("%s unset. ", str); + gen_rand_uuid_str(uuid_str, UUID_STR_FORMAT_STD); + setenv(s, uuid_str); + e = getenv(s); - free(s); - if (e == NULL) { - printf("Environmental '%s' not set\n", str); - return -1; /* env not set */ + if (e) { + debug("Set to random.\n"); + ret = 0; + } else { + debug("Can't get random UUID.\n"); } - *env = e; - return 0; +#else + debug("%s unset.\n", str); +#endif + } else { + debug("%s get from environment.\n", str); + ret = 0; } - return -1; + *env = e; + free(s); + + return ret; } /** @@ -299,8 +322,16 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_FAILURE; } - if (gpt_default(blk_dev_desc, argv[4])) + puts("Writing GPT: "); + + ret = gpt_default(blk_dev_desc, argv[4]); + if (!ret) { + puts("success!\n"); + return CMD_RET_SUCCESS; + } else { + puts("error!\n"); return CMD_RET_FAILURE; + } } else { return CMD_RET_USAGE; } diff --git a/common/cmd_lzmadec.c b/common/cmd_lzmadec.c new file mode 100644 index 0000000000..7b0b3fdd90 --- /dev/null +++ b/common/cmd_lzmadec.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2013 Patrice Bouchand <pbfwdlist_gmail_com> + * lzma uncompress command in Uboot + * + * made from existing cmd_unzip.c file of Uboot + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include <lzma/LzmaTools.h> + +static int do_lzmadec(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long src, dst; + unsigned long src_len = ~0UL, dst_len = ~0UL; + int ret; + + switch (argc) { + case 4: + dst_len = simple_strtoul(argv[3], NULL, 16); + /* fall through */ + case 3: + src = simple_strtoul(argv[1], NULL, 16); + dst = simple_strtoul(argv[2], NULL, 16); + break; + default: + return CMD_RET_USAGE; + } + + ret = lzmaBuffToBuffDecompress(map_sysmem(dst, dst_len), &src_len, + map_sysmem(src, 0), dst_len); + + if (ret != SZ_OK) + return 1; + printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len); + setenv_hex("filesize", src_len); + + return 0; +} + +U_BOOT_CMD( + lzmadec, 4, 1, do_lzmadec, + "lzma uncompress a memory region", + "srcaddr dstaddr [dstsize]" +); diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 2d51927060..c1916c9b56 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -79,7 +79,7 @@ enum mmc_state { }; static void print_mmcinfo(struct mmc *mmc) { - printf("Device: %s\n", mmc->name); + printf("Device: %s\n", mmc->cfg->name); printf("Manufacturer ID: %x\n", mmc->cid[0] >> 24); printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff); printf("Name: %c%c%c%c%c \n", mmc->cid[0] & 0xff, @@ -330,6 +330,40 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("EMMC boot partition Size change Failed.\n"); return 1; } + } else if (strcmp(argv[1], "rst-function") == 0) { + /* + * Set the RST_n_ENABLE bit of RST_n_FUNCTION + * The only valid values are 0x0, 0x1 and 0x2 and writing + * a value of 0x1 or 0x2 sets the value permanently. + */ + int dev; + struct mmc *mmc; + u8 enable; + + if (argc == 4) { + dev = simple_strtoul(argv[2], NULL, 10); + enable = simple_strtoul(argv[3], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + if (enable > 2 || enable < 0) { + puts("Invalid RST_n_ENABLE value\n"); + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + + if (IS_SD(mmc)) { + puts("RST_n_FUNCTION only exists on eMMC\n"); + return 1; + } + + return mmc_set_rst_n_function(mmc, enable); #endif /* CONFIG_SUPPORT_EMMC_BOOT */ } @@ -436,6 +470,9 @@ U_BOOT_CMD( " - Change sizes of boot and RPMB partitions of specified device\n" "mmc partconf dev boot_ack boot_partition partition_access\n" " - Change the bits of the PARTITION_CONFIG field of the specified device\n" + "mmc rst-function dev value\n" + " - Change the RST_n_FUNCTION field of the specified device\n" + " WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.\n" #endif "mmc setdsr - set DSR register value\n" ); diff --git a/common/cmd_mmc_spi.c b/common/cmd_mmc_spi.c index 98cd788c76..a2138b8650 100644 --- a/common/cmd_mmc_spi.c +++ b/common/cmd_mmc_spi.c @@ -72,7 +72,7 @@ static int do_mmc_spi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Failed to create MMC Device\n"); return 1; } - printf("%s: %d at %u:%u hz %u mode %u\n", mmc->name, mmc->block_dev.dev, + printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, mmc->block_dev.dev, bus, cs, speed, mode); mmc_init(mmc); return 0; diff --git a/common/main.c b/common/main.c index 8b6f274fa2..e54f63b956 100644 --- a/common/main.c +++ b/common/main.c @@ -427,6 +427,12 @@ void main_loop(void) bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); +#ifndef CONFIG_SYS_GENERIC_BOARD + puts("Warning: Your board does not use generic board. Please read\n"); + puts("doc/README.generic-board and take action. Boards not\n"); + puts("upgraded by the late 2014 may break or be removed.\n"); +#endif + #ifdef CONFIG_MODEM_SUPPORT debug("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init); if (do_mdm_init) { diff --git a/disk/part_efi.c b/disk/part_efi.c index 733d5bde94..216a2920c2 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -63,26 +63,6 @@ static char *print_efiname(gpt_entry *pte) return name; } -static void uuid_string(unsigned char *uuid, char *str) -{ - static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, - 12, 13, 14, 15}; - int i; - - for (i = 0; i < 16; i++) { - sprintf(str, "%02x", uuid[le[i]]); - str += 2; - switch (i) { - case 3: - case 5: - case 7: - case 9: - *str++ = '-'; - break; - } - } -} - static efi_guid_t system_guid = PARTITION_SYSTEM_GUID; static inline int is_bootable(gpt_entry *p) @@ -103,6 +83,7 @@ void print_part_efi(block_dev_desc_t * dev_desc) gpt_entry *gpt_pte = NULL; int i = 0; char uuid[37]; + unsigned char *uuid_bin; if (!dev_desc) { printf("%s: Invalid Argument(s)\n", __func__); @@ -119,8 +100,8 @@ void print_part_efi(block_dev_desc_t * dev_desc) printf("Part\tStart LBA\tEnd LBA\t\tName\n"); printf("\tAttributes\n"); - printf("\tType UUID\n"); - printf("\tPartition UUID\n"); + printf("\tType GUID\n"); + printf("\tPartition GUID\n"); for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) { /* Stop at the first non valid PTE */ @@ -132,10 +113,12 @@ void print_part_efi(block_dev_desc_t * dev_desc) le64_to_cpu(gpt_pte[i].ending_lba), print_efiname(&gpt_pte[i])); printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw); - uuid_string(gpt_pte[i].partition_type_guid.b, uuid); + uuid_bin = (unsigned char *)gpt_pte[i].partition_type_guid.b; + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); printf("\ttype:\t%s\n", uuid); - uuid_string(gpt_pte[i].unique_partition_guid.b, uuid); - printf("\tuuid:\t%s\n", uuid); + uuid_bin = (unsigned char *)gpt_pte[i].unique_partition_guid.b; + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); + printf("\tguid:\t%s\n", uuid); } /* Remember to free pte */ @@ -182,7 +165,8 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, sprintf((char *)info->type, "U-Boot"); info->bootable = is_bootable(&gpt_pte[part - 1]); #ifdef CONFIG_PARTITION_UUIDS - uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid); + uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid, + UUID_STR_FORMAT_GUID); #endif debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__, @@ -237,60 +221,6 @@ static int set_protective_mbr(block_dev_desc_t *dev_desc) return 0; } -/** - * string_uuid(); Convert UUID stored as string to bytes - * - * @param uuid - UUID represented as string - * @param dst - GUID buffer - * - * @return return 0 on successful conversion - */ -static int string_uuid(char *uuid, u8 *dst) -{ - efi_guid_t guid; - u16 b, c, d; - u64 e; - u32 a; - u8 *p; - u8 i; - - const u8 uuid_str_len = 36; - - /* The UUID is written in text: */ - /* 1 9 14 19 24 */ - /* xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx */ - - debug("%s: uuid: %s\n", __func__, uuid); - - if (strlen(uuid) != uuid_str_len) - return -1; - - for (i = 0; i < uuid_str_len; i++) { - if ((i == 8) || (i == 13) || (i == 18) || (i == 23)) { - if (uuid[i] != '-') - return -1; - } else { - if (!isxdigit(uuid[i])) - return -1; - } - } - - a = (u32)simple_strtoul(uuid, NULL, 16); - b = (u16)simple_strtoul(uuid + 9, NULL, 16); - c = (u16)simple_strtoul(uuid + 14, NULL, 16); - d = (u16)simple_strtoul(uuid + 19, NULL, 16); - e = (u64)simple_strtoull(uuid + 24, NULL, 16); - - p = (u8 *) &e; - guid = EFI_GUID(a, b, c, d >> 8, d & 0xFF, - *(p + 5), *(p + 4), *(p + 3), - *(p + 2), *(p + 1) , *p); - - memcpy(dst, guid.b, sizeof(efi_guid_t)); - - return 0; -} - int write_gpt_table(block_dev_desc_t *dev_desc, gpt_header *gpt_h, gpt_entry *gpt_e) { @@ -358,6 +288,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, size_t efiname_len, dosname_len; #ifdef CONFIG_PARTITION_UUIDS char *str_uuid; + unsigned char *bin_uuid; #endif for (i = 0; i < parts; i++) { @@ -391,7 +322,9 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e, #ifdef CONFIG_PARTITION_UUIDS str_uuid = partitions[i].uuid; - if (string_uuid(str_uuid, gpt_e[i].unique_partition_guid.b)) { + bin_uuid = gpt_e[i].unique_partition_guid.b; + + if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_STD)) { printf("Partition no. %d: invalid guid: %s\n", i, str_uuid); return -1; @@ -438,7 +371,7 @@ int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h, gpt_h->header_crc32 = 0; gpt_h->partition_entry_array_crc32 = 0; - if (string_uuid(str_guid, gpt_h->disk_guid.b)) + if (uuid_str_to_bin(str_guid, gpt_h->disk_guid.b, UUID_STR_FORMAT_GUID)) return -1; return 0; diff --git a/doc/README.generic-board b/doc/README.generic-board new file mode 100644 index 0000000000..50d3a26849 --- /dev/null +++ b/doc/README.generic-board @@ -0,0 +1,189 @@ +# +# (C) Copyright 2014 Google, Inc +# Simon Glass <sjg@chromium.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +DEPRECATION NOTICE FOR arch/<arch>/lib/board.c + +For board maintainers: Please submit patches for boards you maintain before +July 2014, to make them use generic board. + +For architecture maintainers: Please submit patches to remove your +architecture-specific board.c file before October 2014. + + +Background +---------- + +U-Boot has tranditionally had a board.c file for each architecture. This has +introduced quite a lot of duplication, with each architecture tending to do +initialisation slightly differently. To address this, a new 'generic board +init' feature was introduced a year ago in March 2013 (further motivation is +provided in the cover letter below). + + +What has changed? +----------------- + +The main change is that the arch/<arch>/lib/board.c file is being removed in +favour of common/board_f.c (for pre-relocation init) and common/board_r.c +(for post-relocation init). + +Related to this, the global_data and bd_t structures now have a core set of +fields which are common to all architectures. Architecture-specific fields +have been moved to separate structures. + + +Supported Arcthitectures +------------------------ + +If you are unlucky then your architecture may not support generic board. +The following architectures are supported at the time of writing: + + arc + arm + powerpc + sandbox + x86 + +If your architecture is not supported, you need to adjust your +arch/<arch>/config.mk file to include: + + __HAVE_ARCH_GENERIC_BOARD := y + +and test it with a suitable board, as follows. + + +Adding Support for your Board +----------------------------- + +To enable generic board for your board, define CONFIG_SYS_GENERIC_BOARD in +your board config header file. + +Test that U-Boot still functions correctly on your board, and fix any +problems you find. Don't be surprised if there are no problems - generic +board has had a reasonable amount of testing with common boards. + + +DeadLine +-------- + +Please don't take this the wrong way - there is no intent to make your life +miserable, and we have the greatest respect and admiration for U-Boot users. +However, with any migration there has to be a period where the old way is +deprecated and removed. Every patch to the deprecated code introduces a +potential breakage in the new unused code. Therefore: + +Boards or architectures not converted over to general board by the +end of 2014 may be forcibly changed over (potentially causing run-time +breakage) or removed. + + + +Further Background +------------------ + +The full text of the original generic board series is reproduced below. + +--8<------------- + +This series creates a generic board.c implementation which contains +the essential functions of the major arch/xxx/lib/board.c files. + +What is the motivation for this change? + +1. There is a lot of repeated code in the board.c files. Any change to +things like setting up the baud rate requires a change in 10 separate +places. + +2. Since there are 10 separate files, adding a new feature which requires +initialisation is painful since it must be independently added in 10 +places. + +3. As time goes by the architectures naturely diverge since there is limited +pressure to compare features or even CONFIG options against simiilar things +in other board.c files. + +4. New architectures must implement all the features all over again, and +sometimes in subtley different ways. This places an unfair burden on getting +a new architecture fully functional and running with U-Boot. + +5. While it is a bit of a tricky change, I believe it is worthwhile and +achievable. There is no requirement that all code be common, only that +the code that is common should be located in common/board.c rather than +arch/xxx/lib/board.c. + +All the functions of board_init_f() and board_init_r() are broken into +separate function calls so that they can easily be included or excluded +for a particular architecture. It also makes it easier to adopt Graeme's +initcall proposal when it is ready. + +http://lists.denx.de/pipermail/u-boot/2012-January/114499.html + +This series removes the dependency on generic relocation. So relocation +happens as one big chunk and is still completely arch-specific. See the +relocation series for a proposed solution to this for ARM: + +http://lists.denx.de/pipermail/u-boot/2011-December/112928.html + +or Graeme's recent x86 series v2: + +http://lists.denx.de/pipermail/u-boot/2012-January/114467.html + +Instead of moving over a whole architecture, this series takes the approach +of simply enabling generic board support for an architecture. It is then up +to each board to opt in by defining CONFIG_SYS_GENERIC_BOARD in the board +config file. If this is not done, then the code will be generated as +before. This allows both sets of code to co-exist until we are comfortable +with the generic approach, and enough boards run. + +ARM is a relatively large board.c file and one which I can test, therefore +I think it is a good target for this series. On the other hand, x86 is +relatively small and simple, but different enough that it introduces a +few issues to be solved. So I have chosen both ARM and x86 for this series. +After a suggestion from Wolfgang I have added PPC also. This is the +largest and most feature-full board, so hopefully we have all bases +covered in this RFC. + +A generic global_data structure is also required. This might upset a few +people. Here is my basic reasoning: most fields are the same, all +architectures include and need it, most global_data.h files already have +#ifdefs to select fields for a particular SOC, so it is hard to +see why architecures are different in this area. We can perhaps add a +way to put architecture-specific fields into a separate header file, but +for now I have judged that to be counter-productive. + +Similarly we need a generic bd_info structure, since generic code will +be accessing it. I have done this in the same way as global_data and the +same comments apply. + +There was dicussion on the list about passing gd_t around as a parameter +to pre-relocation init functions. I think this makes sense, but it can +be done as a separate change, and this series does not require it. + +While this series needs to stand on its own (as with the link script +cleanup series and the generic relocation series) the goal is the +unification of the board init code. So I hope we can address issues with +this in mind, rather than focusing too narrowly on particular ARM, x86 or +PPC issues. + +I have run-tested ARM on Tegra Seaboard only. To try it out, define +CONFIG_SYS_GENERIC_BOARD in your board file and rebuild. Most likely on +x86 and PPC at least it will hang, but if you are lucky it will print +something first :-) + +I have run this though MAKEALL with CONFIG_SYS_GENERIC_BOARD on for all +ARM, PPC and x86 boards. There are a few failures due to errors in +the board config, which I have sent patches for. The main issue is +just the difference between __bss_end and __bss_end__. + +Note: the first group of commits are required for this series to build, +but could be separated out if required. I have included them here for +convenience. + +------------->8-- + +Simon Glass, sjg@chromium.org +March 2014 diff --git a/doc/README.gpt b/doc/README.gpt index 5c133f3321..f822894709 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -132,8 +132,8 @@ of the Primary. ---------------------- Offset Size Description - 0 16 B Partition type GUID - 16 16 B Unique partition GUID + 0 16 B Partition type GUID (Big Endian) + 16 16 B Unique partition GUID in (Big Endian) 32 8 B First LBA (Little Endian) 40 8 B Last LBA (inclusive) 48 8 B Attribute flags [+] @@ -160,6 +160,9 @@ To restore GUID partition table one needs to: Fields 'name', 'size' and 'uuid' are mandatory for every partition. The field 'start' is optional. + option: CONFIG_RANDOM_UUID + If any partition "UUID" no exists then it is randomly generated. + 2. Define 'CONFIG_EFI_PARTITION' and 'CONFIG_CMD_GPT' 2. From u-boot prompt type: @@ -168,11 +171,20 @@ To restore GUID partition table one needs to: Useful info: ============ -Two programs, namely: 'fdisk' and 'parted' are recommended to work with GPT -recovery. Parted is able to handle GUID partitions. Unfortunately the 'fdisk' -hasn't got such ability. +Two programs, namely: 'gdisk' and 'parted' are recommended to work with GPT +recovery. Both are able to handle GUID partitions. Please, pay attention at -l switch for parted. "uuid" program is recommended to generate UUID string. Moreover it can decode (-d switch) passed in UUID string. It can be used to generate partitions UUID passed to u-boot environment variables. +If optional CONFIG_RANDOM_UUID is defined then for any partition which environment +uuid is unset, uuid is randomly generated and stored in correspond environment +variable. + +note: +Each string block of UUID generated by program "uuid" is in big endian and it is +also stored in big endian in disk GPT. +Partitions layout can be printed by typing "mmc part". Note that each partition +GUID has different byte order than UUID generated before, this is because first +three blocks of GUID string are in Little Endian. diff --git a/doc/device-tree-bindings/video/exynos_mipi_dsi.txt b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt new file mode 100644 index 0000000000..4938ea01ec --- /dev/null +++ b/doc/device-tree-bindings/video/exynos_mipi_dsi.txt @@ -0,0 +1,82 @@ +Exynos MIPI-DSIM Controller +========================= + +Required properties: +SOC specific: + compatible: should be "samsung,exynos-mipi-dsi" + reg: Base address of MIPI-DSIM IP. + +Board specific: + samsung,dsim-config-e-interface: interface to be used (RGB interface + for main display or CPU interface for main or sub display). + samsung,dsim-config-e-virtual-ch: virtual channel number that main + or sub display uses. + samsung,dsim-config-e-pixel-format: pixel stream format for main + or sub display. + samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode. + in Non-burst mode, RGB data area is filled with RGB data and + NULL packets, according to input bandwidth of RGB interface. + samsung,dsim-config-e-no-data-lane: data lane count used by Master. + samsung,dsim-config-e-byte-clk: select byte clock source. + It must be DSIM_PLL_OUT_DIV8. + DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported. + samsung,dsim-config-hfp: HFP disable mode. + If set, DSI master ignores HFP area in VIDEO mode. + In command mode, this variable is ignored. + samsung,dsim-config-p: P value for PMS setting. + samsung,dsim-config-m: M value for PMS setting. + samsung,dsim-config-s: S value for PMS setting. + samsung,dsim-config-pll-stable-time: the PLL Timer for stability + of the ganerated clock. + samsung,dsim-config-esc-clk: escape clock frequency for getting + the escape clock prescaler value. + samsung,dsim-config-stop-holding-cnt: the interval value between + transmitting read packet (or write "set_tear_on" command) + and BTA request. After transmitting read packet or write + "set_tear_on" command, BTA requests to D-PHY automatically. + This counter value specifies the interval between them. + samsung,dsim-config-bta-timeout: the timer for BTA. This register + specifies time out from BTA request to change the direction + with respect to Tx escape clock. + samsung,dsim-config-rx-timeout: the timer for LP Rx mode timeout. + this register specifies time out on how long RxValid deasserts, + after RxLpdt asserts with respect to Tx escape clock. + - RxValid specifies Rx data valid indicator. + - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode + - RxValid and RxLpdt specifies signal from D-PHY. + samsung,dsim-device-name: name of the device. + samsung,dsim-device-id: unique device id. + samsung,dsim-device-bus_id: bus id for identifing connected bus + and this bus id should be same as id of mipi_dsim_device. + +Optional properties: + samsung,dsim-device-reverse-panel: reverse panel. + +Example: + mipidsi@11c80000 { + compatible = "samsung,exynos-mipi-dsi"; + reg = <0x11c80000 0x5c>; + + samsung,dsim-config-e-interface = <1>; + samsung,dsim-config-e-virtual-ch = <0>; + samsung,dsim-config-e-pixel-format = <7>; + samsung,dsim-config-e-burst-mode = <1>; + samsung,dsim-config-e-no-data-lane = <3>; + samsung,dsim-config-e-byte-clk = <0>; + samsung,dsim-config-hfp = <1>; + + samsung,dsim-config-p = <3>; + samsung,dsim-config-m = <120>; + samsung,dsim-config-s = <1>; + + samsung,dsim-config-pll-stable-time = <500>; + samsung,dsim-config-esc-clk = <20000000>; + samsung,dsim-config-stop-holding-cnt = <0x7ff>; + samsung,dsim-config-bta-timeout = <0xff>; + samsung,dsim-config-rx-timeout = <0xffff>; + + samsung,dsim-device-id = <0xffffffff>; + samsung,dsim-device-bus-id = <0>; + + samsung,dsim-device-reverse-panel = <1>; + }; diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index a409f63770..c8f65739e9 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -623,6 +623,7 @@ static int ata_scsiop_inquiry(ccb *pccb) 95 - 4, }; u8 fis[20]; + u16 *idbuf; ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); u8 port; @@ -649,17 +650,25 @@ static int ata_scsiop_inquiry(ccb *pccb) return -EIO; } - if (ataid[port]) - free(ataid[port]); - ataid[port] = tmpid; - ata_swap_buf_le16(tmpid, ATA_ID_WORDS); + if (!ataid[port]) { + ataid[port] = malloc(ATA_ID_WORDS * 2); + if (!ataid[port]) { + printf("%s: No memory for ataid[port]\n", __func__); + return -ENOMEM; + } + } + + idbuf = ataid[port]; + + memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); + ata_swap_buf_le16(idbuf, ATA_ID_WORDS); memcpy(&pccb->pdata[8], "ATA ", 8); - ata_id_strcpy((u16 *) &pccb->pdata[16], &tmpid[ATA_ID_PROD], 16); - ata_id_strcpy((u16 *) &pccb->pdata[32], &tmpid[ATA_ID_FW_REV], 4); + ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); + ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); #ifdef DEBUG - ata_dump_id(tmpid); + ata_dump_id(idbuf); #endif return 0; } diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c index acbafde97c..ed4f541823 100644 --- a/drivers/crypto/ace_sha.c +++ b/drivers/crypto/ace_sha.c @@ -5,10 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include "ace_sha.h" + +#ifdef CONFIG_SHA_HW_ACCEL #include <sha256.h> #include <sha1.h> #include <asm/errno.h> -#include "ace_sha.h" /* SHA1 value for the message of zero length */ static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = { @@ -111,3 +113,72 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1)) debug("ACE was not setup properly or it is faulty\n"); } +#endif /* CONFIG_SHA_HW_ACCEL */ + +#ifdef CONFIG_LIB_HW_RAND +static unsigned int seed_done; + +void srand(unsigned int seed) +{ + struct exynos_ace_sfr *reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + int i, status; + + /* Seed data */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + writel(seed << i, ®->hash_seed[i]); + + /* Wait for seed setup done */ + while (1) { + status = readl(®->hash_status); + if ((status & ACE_HASH_SEEDSETTING_MASK) || + (status & ACE_HASH_PRNGERROR_MASK)) + break; + } + + seed_done = 1; +} + +unsigned int rand(void) +{ + struct exynos_ace_sfr *reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + int i, status; + unsigned int seed = (unsigned int)&status; + unsigned int ret = 0; + + if (!seed_done) + srand(seed); + + /* Start PRNG */ + writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, ®->hash_control); + + /* Wait for PRNG done */ + while (1) { + status = readl(®->hash_status); + if (status & ACE_HASH_PRNGDONE_MASK) + break; + if (status & ACE_HASH_PRNGERROR_MASK) { + seed_done = 0; + return 0; + } + } + + /* Clear Done IRQ */ + writel(ACE_HASH_PRNGDONE_MASK, ®->hash_status); + + /* Read a PRNG result */ + for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++) + ret += readl(®->hash_prng[i]); + + seed_done = 0; + return ret; +} + +unsigned int rand_r(unsigned int *seedp) +{ + srand(*seedp); + + return rand(); +} +#endif /* CONFIG_LIB_HW_RAND */ diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h index a426d52372..f1097f72dc 100644 --- a/drivers/crypto/ace_sha.h +++ b/drivers/crypto/ace_sha.h @@ -72,9 +72,10 @@ struct exynos_ace_sfr { unsigned char res12[0x30]; unsigned int hash_result[8]; unsigned char res13[0x20]; - unsigned int hash_seed[8]; - unsigned int hash_prng[8]; - unsigned char res14[0x180]; + unsigned int hash_seed[5]; + unsigned char res14[12]; + unsigned int hash_prng[5]; + unsigned char res15[0x18c]; unsigned int pka_sfr[5]; /* base + 0x700 */ }; @@ -291,6 +292,7 @@ struct exynos_ace_sfr { #define ACE_HASH_PRNGERROR_MASK (1 << 7) #define ACE_HASH_PRNGERROR_OFF (0 << 7) #define ACE_HASH_PRNGERROR_ON (1 << 7) +#define ACE_HASH_PRNG_REG_NUM 5 #define ACE_SHA_TYPE_SHA1 1 #define ACE_SHA_TYPE_SHA256 2 diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 07011e99a8..8a09aafbf2 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -19,6 +19,7 @@ static bool dfu_reset_request; static LIST_HEAD(dfu_list); static int dfu_alt_num; +static int alt_num_cnt; bool dfu_reset(void) { @@ -126,6 +127,28 @@ static int dfu_write_buffer_drain(struct dfu_entity *dfu) return ret; } +int dfu_flush(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) +{ + int ret = 0; + + if (dfu->flush_medium) + ret = dfu->flush_medium(dfu); + + printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); + + /* clear everything */ + dfu_free_buf(); + dfu->crc = 0; + dfu->offset = 0; + dfu->i_blk_seq_num = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf; + dfu->i_buf = dfu->i_buf_start; + dfu->inited = 0; + + return ret; +} + int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { int ret = 0; @@ -196,26 +219,6 @@ int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) ret = tret; } - /* end? */ - if (size == 0) { - /* Now try and flush to the medium if needed. */ - if (dfu->flush_medium) - ret = dfu->flush_medium(dfu); - printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); - - /* clear everything */ - dfu_free_buf(); - dfu->crc = 0; - dfu->offset = 0; - dfu->i_blk_seq_num = 0; - dfu->i_buf_start = dfu_buf; - dfu->i_buf_end = dfu_buf; - dfu->i_buf = dfu->i_buf_start; - - dfu->inited = 0; - - } - return ret = 0 ? size : ret; } @@ -377,6 +380,8 @@ void dfu_free_entities(void) if (t) free(t); INIT_LIST_HEAD(&dfu_list); + + alt_num_cnt = 0; } int dfu_config_entities(char *env, char *interface, int num) @@ -394,11 +399,12 @@ int dfu_config_entities(char *env, char *interface, int num) for (i = 0; i < dfu_alt_num; i++) { s = strsep(&env, ";"); - ret = dfu_fill_entity(&dfu[i], s, i, interface, num); + ret = dfu_fill_entity(&dfu[i], s, alt_num_cnt, interface, num); if (ret) return -1; list_add_tail(&dfu[i].list, &dfu_list); + alt_num_cnt++; } return 0; diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 0816f46bad..651cfff5b3 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -12,6 +12,7 @@ #include <errno.h> #include <div64.h> #include <dfu.h> +#include <mmc.h> static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; @@ -20,8 +21,8 @@ static long dfu_file_buf_len; static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, u64 offset, void *buf, long *len) { - char cmd_buf[DFU_CMD_BUF_SIZE]; - u32 blk_start, blk_count; + struct mmc *mmc = find_mmc_device(dfu->dev_num); + u32 blk_start, blk_count, n = 0; /* * We must ensure that we work in lba_blk_size chunks, so ALIGN @@ -38,12 +39,28 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, return -EINVAL; } - sprintf(cmd_buf, "mmc %s %p %x %x", - op == DFU_OP_READ ? "read" : "write", - buf, blk_start, blk_count); + debug("%s: %s dev: %d start: %d cnt: %d buf: 0x%p\n", __func__, + op == DFU_OP_READ ? "MMC READ" : "MMC WRITE", dfu->dev_num, + blk_start, blk_count, buf); + switch (op) { + case DFU_OP_READ: + n = mmc->block_dev.block_read(dfu->dev_num, blk_start, + blk_count, buf); + break; + case DFU_OP_WRITE: + n = mmc->block_dev.block_write(dfu->dev_num, blk_start, + blk_count, buf); + break; + default: + error("Operation not supported\n"); + } - debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); - return run_command(cmd_buf, 0); + if (n != blk_count) { + error("MMC operation failed"); + return -EIO; + } + + return 0; } static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c deleted file mode 100644 index 675f4171ce..0000000000 --- a/drivers/i2c/adi_i2c.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * i2c.c - driver for ADI TWI/I2C - * - * Copyright (c) 2006-2013 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <i2c.h> - -#include <asm/clock.h> -#include <asm/twi.h> -#include <asm/io.h> - -/* Every register is 32bit aligned, but only 16bits in size */ -#define ureg(name) u16 name; u16 __pad_##name; -struct twi_regs { - ureg(clkdiv); - ureg(control); - ureg(slave_ctl); - ureg(slave_stat); - ureg(slave_addr); - ureg(master_ctl); - ureg(master_stat); - ureg(master_addr); - ureg(int_stat); - ureg(int_mask); - ureg(fifo_ctl); - ureg(fifo_stat); - char __pad[0x50]; - ureg(xmt_data8); - ureg(xmt_data16); - ureg(rcv_data8); - ureg(rcv_data16); -}; -#undef ureg - -/* U-Boot I2C framework allows only one active device at a time. */ -#ifdef TWI_CLKDIV -#define TWI0_CLKDIV TWI_CLKDIV -#endif -static struct twi_regs *twi = (void *)TWI0_CLKDIV; - -#ifdef DEBUG -# define dmemset(s, c, n) memset(s, c, n) -#else -# define dmemset(s, c, n) -#endif -#define debugi(fmt, args...) \ - debug( \ - "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \ - twi->master_stat, twi->fifo_stat, twi->int_stat, \ - __func__, __LINE__, ## args) - -#ifdef CONFIG_TWICLK_KHZ -# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED -#endif - -/* - * The way speed is changed into duty often results in integer truncation - * with 50% duty, so we'll force rounding up to the next duty by adding 1 - * to the max. In practice this will get us a speed of something like - * 385 KHz. The other limit is easy to handle as it is only 8 bits. - */ -#define I2C_SPEED_MAX 400000 -#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) -#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) -#define I2C_DUTY_MIN 0xff /* 8 bit limited */ -#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) -/* Note: duty is inverse of speed, so the comparisons below are correct */ -#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN -# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" -#endif - -/* All transfers are described by this data structure */ -struct i2c_msg { - u8 flags; -#define I2C_M_COMBO 0x4 -#define I2C_M_STOP 0x2 -#define I2C_M_READ 0x1 - int len; /* msg length */ - u8 *buf; /* pointer to msg data */ - int alen; /* addr length */ - u8 *abuf; /* addr buffer */ -}; - -/* Allow msec timeout per ~byte transfer */ -#define I2C_TIMEOUT 10 - -/** - * wait_for_completion - manage the actual i2c transfer - * @msg: the i2c msg - */ -static int wait_for_completion(struct i2c_msg *msg) -{ - u16 int_stat, ctl; - ulong timebase = get_timer(0); - - do { - int_stat = readw(&twi->int_stat); - - if (int_stat & XMTSERV) { - debugi("processing XMTSERV"); - writew(XMTSERV, &twi->int_stat); - if (msg->alen) { - writew(*(msg->abuf++), &twi->xmt_data8); - --msg->alen; - } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - writew(*(msg->buf++), &twi->xmt_data8); - --msg->len; - } else { - ctl = readw(&twi->master_ctl); - if (msg->flags & I2C_M_COMBO) - writew(ctl | RSTART | MDIR, - &twi->master_ctl); - else - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & RCVSERV) { - debugi("processing RCVSERV"); - writew(RCVSERV, &twi->int_stat); - if (msg->len) { - *(msg->buf++) = readw(&twi->rcv_data8); - --msg->len; - } else if (msg->flags & I2C_M_STOP) { - ctl = readw(&twi->master_ctl); - writew(ctl | STOP, &twi->master_ctl); - } - } - if (int_stat & MERR) { - debugi("processing MERR"); - writew(MERR, &twi->int_stat); - return msg->len; - } - if (int_stat & MCOMP) { - debugi("processing MCOMP"); - writew(MCOMP, &twi->int_stat); - if (msg->flags & I2C_M_COMBO && msg->len) { - ctl = readw(&twi->master_ctl); - ctl = (ctl & ~RSTART) | - (min(msg->len, 0xff) << 6) | MEN | MDIR; - writew(ctl, &twi->master_ctl); - } else - break; - } - - /* If we were able to do something, reset timeout */ - if (int_stat) - timebase = get_timer(0); - - } while (get_timer(timebase) < I2C_TIMEOUT); - - return msg->len; -} - -/** - * i2c_transfer - setup an i2c transfer - * @return: 0 if things worked, non-0 if things failed - * - * Here we just get the i2c stuff all prepped and ready, and then tail off - * into wait_for_completion() for all the bits to go. - */ -static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, - int len, u8 flags) -{ - int ret; - u16 ctl; - uchar addr_buffer[] = { - (addr >> 0), - (addr >> 8), - (addr >> 16), - }; - struct i2c_msg msg = { - .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), - .buf = buffer, - .len = len, - .abuf = addr_buffer, - .alen = alen, - }; - - dmemset(buffer, 0xff, len); - debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i ", - chip, addr, alen, buffer[0], len); - debugi("flags=0x%02x[%s] ", flags, - (flags & I2C_M_READ ? "rd" : "wr")); - - /* wait for things to settle */ - while (readw(&twi->master_stat) & BUSBUSY) - if (ctrlc()) - return 1; - - /* Set Transmit device address */ - writew(chip, &twi->master_addr); - - /* Clear the FIFO before starting things */ - writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); - writew(0, &twi->fifo_ctl); - - /* prime the pump */ - if (msg.alen) { - len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; - debugi("first byte=0x%02x", *msg.abuf); - writew(*(msg.abuf++), &twi->xmt_data8); - --msg.alen; - } else if (!(msg.flags & I2C_M_READ) && msg.len) { - debugi("first byte=0x%02x", *msg.buf); - writew(*(msg.buf++), &twi->xmt_data8); - --msg.len; - } - - /* clear int stat */ - writew(-1, &twi->master_stat); - writew(-1, &twi->int_stat); - writew(0, &twi->int_mask); - - /* Master enable */ - ctl = readw(&twi->master_ctl); - ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0); - writew(ctl, &twi->master_ctl); - - /* process the rest */ - ret = wait_for_completion(&msg); - debugi("ret=%d", ret); - - if (ret) { - ctl = readw(&twi->master_ctl) & ~MEN; - writew(ctl, &twi->master_ctl); - ctl = readw(&twi->control) & ~TWI_ENA; - writew(ctl, &twi->control); - ctl = readw(&twi->control) | TWI_ENA; - writew(ctl, &twi->control); - } - - return ret; -} - -/** - * i2c_set_bus_speed - set i2c bus speed - * @speed: bus speed (in HZ) - */ -int i2c_set_bus_speed(unsigned int speed) -{ - u16 clkdiv = I2C_SPEED_TO_DUTY(speed); - - /* Set TWI interface clock */ - if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) - return -1; - clkdiv = (clkdiv << 8) | (clkdiv & 0xff); - writew(clkdiv, &twi->clkdiv); - - /* Don't turn it on */ - writew(speed > 100000 ? FAST : 0, &twi->master_ctl); - - return 0; -} - -/** - * i2c_get_bus_speed - get i2c bus speed - * @speed: bus speed (in HZ) - */ -unsigned int i2c_get_bus_speed(void) -{ - u16 clkdiv = readw(&twi->clkdiv) & 0xff; - /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ - return 5000000 / clkdiv; -} - -/** - * i2c_init - initialize the i2c bus - * @speed: bus speed (in HZ) - * @slaveaddr: address of device in slave mode (0 - not slave) - * - * Slave mode isn't actually implemented. It'll stay that way until - * we get a real request for it. - */ -void i2c_init(int speed, int slaveaddr) -{ - u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; - - /* Set TWI internal clock as 10MHz */ - writew(prescale, &twi->control); - - /* Set TWI interface clock as specified */ - i2c_set_bus_speed(speed); - - /* Enable it */ - writew(TWI_ENA | prescale, &twi->control); - - debugi("CONTROL:0x%04x CLKDIV:0x%04x", readw(&twi->control), - readw(&twi->clkdiv)); - -#if CONFIG_SYS_I2C_SLAVE -# error I2C slave support not tested/supported -#endif -} - -/** - * i2c_probe - test if a chip exists at a given i2c address - * @chip: i2c chip addr to search for - * @return: 0 if found, non-0 if not found - */ -int i2c_probe(uchar chip) -{ - u8 byte; - return i2c_read(chip, 0, 0, &byte, 1); -} - -/** - * i2c_read - read data from an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer to store data read from chip - * @len: how many bytes to read - * @return: 0 on success, non-0 on failure - */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, - len, (alen ? I2C_M_COMBO : I2C_M_READ)); -} - -/** - * i2c_write - write data to an i2c device - * @chip: i2c chip addr - * @addr: memory (register) address in the chip - * @alen: byte size of address - * @buffer: buffer holding data to write to chip - * @len: how many bytes to write - * @return: 0 on success, non-0 on failure - */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - return i2c_transfer(chip, addr, alen, buffer, len, 0); -} - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - switch (bus) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case 0: - twi = (void *)TWI0_CLKDIV; - return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case 1: - twi = (void *)TWI1_CLKDIV; - return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case 2: - twi = (void *)TWI2_CLKDIV; - return 0; -#endif - default: return -1; - } -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - switch ((unsigned long)twi) { -#if CONFIG_SYS_MAX_I2C_BUS > 0 - case TWI0_CLKDIV: - return 0; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 1 - case TWI1_CLKDIV: - return 1; -#endif -#if CONFIG_SYS_MAX_I2C_BUS > 2 - case TWI2_CLKDIV: - return 2; -#endif - default: return -1; - } -} diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index cc19100750..e7e96921d2 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -269,7 +269,9 @@ static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, static int sh_i2c_probe(struct i2c_adapter *adap, u8 dev) { - return sh_i2c_read(adap, dev, 0, 0, NULL, 0); + u8 dummy[1]; + + return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy); } static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index c25e92d17b..2f2e48f979 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_FSL_IIM) += fsl_iim.o obj-$(CONFIG_GPIO_LED) += gpio_led.o obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o +obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_PDSP188x) += pdsp188x.o obj-$(CONFIG_STATUS_LED) += status_led.o diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c new file mode 100644 index 0000000000..545d3ebf52 --- /dev/null +++ b/drivers/misc/mxs_ocotp.c @@ -0,0 +1,311 @@ +/* + * Freescale i.MX28 OCOTP Driver + * + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Note: The i.MX23/i.MX28 OCOTP block is a predecessor to the OCOTP block + * used in i.MX6 . While these blocks are very similar at the first + * glance, by digging deeper, one will notice differences (like the + * tight dependence on MXS power block, some completely new registers + * etc.) which would make common driver an ifdef nightmare :-( + */ + +#include <common.h> +#include <fuse.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MXS_OCOTP_TIMEOUT 100000 + +static struct mxs_ocotp_regs *ocotp_regs = + (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; +static struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; +static struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + +static int mxs_ocotp_wait_busy_clear(void) +{ + uint32_t reg; + int timeout = MXS_OCOTP_TIMEOUT; + + while (--timeout) { + reg = readl(&ocotp_regs->hw_ocotp_ctrl); + if (!(reg & OCOTP_CTRL_BUSY)) + break; + udelay(10); + } + + if (!timeout) + return -EINVAL; + + /* Wait a little as per FSL datasheet's 'write postamble' section. */ + udelay(10); + + return 0; +} + +static void mxs_ocotp_clear_error(void) +{ + writel(OCOTP_CTRL_ERROR, &ocotp_regs->hw_ocotp_ctrl_clr); +} + +static int mxs_ocotp_read_bank_open(bool open) +{ + int ret = 0; + + if (open) { + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_set); + + /* + * Wait before polling the BUSY bit, since the BUSY bit might + * be asserted only after a few HCLK cycles and if we were to + * poll immediatelly, we could miss the busy bit. + */ + udelay(10); + ret = mxs_ocotp_wait_busy_clear(); + } else { + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_clr); + } + + return ret; +} + +static void mxs_ocotp_scale_vddio(bool enter, uint32_t *val) +{ + uint32_t scale_val; + + if (enter) { + /* + * Enter the fuse programming VDDIO voltage setup. We start + * scaling the voltage from it's current value down to 2.8V + * which is the one and only correct voltage for programming + * the OCOTP fuses (according to datasheet). + */ + scale_val = readl(&power_regs->hw_power_vddioctrl); + scale_val &= POWER_VDDIOCTRL_TRG_MASK; + + /* Return the original voltage. */ + *val = scale_val; + + /* + * Start scaling VDDIO down to 0x2, which is 2.8V . Actually, + * the value 0x0 should be 2.8V, but that's not the case on + * most designs due to load etc., so we play safe. Undervolt + * can actually cause incorrect programming of the fuses and + * or reboots of the board. + */ + while (scale_val > 2) { + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, --scale_val); + udelay(500); + } + } else { + /* Start scaling VDDIO up to original value . */ + for (scale_val = 2; scale_val <= *val; scale_val++) { + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, scale_val); + udelay(500); + } + } + + mdelay(10); +} + +static int mxs_ocotp_wait_hclk_ready(void) +{ + uint32_t reg, timeout = MXS_OCOTP_TIMEOUT; + + while (--timeout) { + reg = readl(&clkctrl_regs->hw_clkctrl_hbus); + if (!(reg & CLKCTRL_HBUS_ASM_BUSY)) + break; + } + + if (!timeout) + return -EINVAL; + + return 0; +} + +static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val) +{ + uint32_t scale_val; + int ret; + + ret = mxs_ocotp_wait_hclk_ready(); + if (ret) + return ret; + + /* Set CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + if (enter) { + /* Return the original HCLK clock speed. */ + *val = readl(&clkctrl_regs->hw_clkctrl_hbus); + *val &= CLKCTRL_HBUS_DIV_MASK; + + /* Scale the HCLK to 454/19 = 23.9 MHz . */ + scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET; + scale_val &= CLKCTRL_HBUS_DIV_MASK; + } else { + /* Scale the HCLK back to original frequency. */ + scale_val = (~(*val)) << CLKCTRL_HBUS_DIV_OFFSET; + scale_val &= CLKCTRL_HBUS_DIV_MASK; + } + + writel(CLKCTRL_HBUS_DIV_MASK, + &clkctrl_regs->hw_clkctrl_hbus_set); + writel(scale_val, + &clkctrl_regs->hw_clkctrl_hbus_clr); + + mdelay(10); + + ret = mxs_ocotp_wait_hclk_ready(); + if (ret) + return ret; + + /* Disable CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); + + mdelay(10); + + return 0; +} + +static int mxs_ocotp_write_fuse(uint32_t addr, uint32_t mask) +{ + uint32_t hclk_val, vddio_val; + int ret; + + /* Make sure the banks are closed for reading. */ + ret = mxs_ocotp_read_bank_open(0); + if (ret) { + puts("Failed closing banks for reading!\n"); + return ret; + } + + ret = mxs_ocotp_scale_hclk(1, &hclk_val); + if (ret) { + puts("Failed scaling down the HCLK!\n"); + return ret; + } + mxs_ocotp_scale_vddio(1, &vddio_val); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + goto fail; + } + + /* Program the fuse address */ + writel(addr | OCOTP_CTRL_WR_UNLOCK_KEY, &ocotp_regs->hw_ocotp_ctrl); + + /* Program the data. */ + writel(mask, &ocotp_regs->hw_ocotp_data); + + udelay(10); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + goto fail; + } + +fail: + mxs_ocotp_scale_vddio(0, &vddio_val); + ret = mxs_ocotp_scale_hclk(0, &hclk_val); + if (ret) { + puts("Failed scaling up the HCLK!\n"); + return ret; + } + + return ret; +} + +static int mxs_ocotp_read_fuse(uint32_t reg, uint32_t *val) +{ + int ret; + + /* Register offset from CUST0 */ + reg = ((uint32_t)&ocotp_regs->hw_ocotp_cust0) + (reg << 4); + + ret = mxs_ocotp_wait_busy_clear(); + if (ret) { + puts("Failed waiting for ready state!\n"); + return ret; + } + + mxs_ocotp_clear_error(); + + ret = mxs_ocotp_read_bank_open(1); + if (ret) { + puts("Failed opening banks for reading!\n"); + return ret; + } + + *val = readl(reg); + + ret = mxs_ocotp_read_bank_open(0); + if (ret) { + puts("Failed closing banks for reading!\n"); + return ret; + } + + return ret; +} + +static int mxs_ocotp_valid(u32 bank, u32 word) +{ + if (bank > 4) + return -EINVAL; + if (word > 7) + return -EINVAL; + return 0; +} + +/* + * The 'fuse' command API + */ +int fuse_read(u32 bank, u32 word, u32 *val) +{ + int ret; + + ret = mxs_ocotp_valid(bank, word); + if (ret) + return ret; + + return mxs_ocotp_read_fuse((bank << 3) | word, val); +} + +int fuse_prog(u32 bank, u32 word, u32 val) +{ + int ret; + + ret = mxs_ocotp_valid(bank, word); + if (ret) + return ret; + + return mxs_ocotp_write_fuse((bank << 3) | word, val); +} + +int fuse_sense(u32 bank, u32 word, u32 *val) +{ + /* We do not support sensing :-( */ + return -EINVAL; +} + +int fuse_override(u32 bank, u32 word, u32 val) +{ + /* We do not support overriding :-( */ + return -EINVAL; +} diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index 5a55fe73b7..5ef7ff7ff2 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -287,9 +287,9 @@ static void host_set_ios(struct mmc *dev) u32 clkdiv = 0; u32 tmp_clock; - if (dev->clock >= dev->f_max) { + if (dev->clock >= dev->cfg->f_max) { clkdiv = 0; - dev->clock = dev->f_max; + dev->clock = dev->cfg->f_max; } else { clkdiv = (host->clock_in / dev->clock) - 2; } @@ -335,6 +335,12 @@ static void host_set_ios(struct mmc *dev) udelay(CLK_CHANGE_DELAY); } +static const struct mmc_ops arm_pl180_mmci_ops = { + .send_cmd = host_request, + .set_ios = host_set_ios, + .init = mmc_host_reset, +}; + /* * mmc_host_init - initialize the mmc controller. * Set initial clock and power for mmc slot. @@ -342,16 +348,9 @@ static void host_set_ios(struct mmc *dev) */ int arm_pl180_mmci_init(struct pl180_mmc_host *host) { - struct mmc *dev; + struct mmc *mmc; u32 sdi_u32; - dev = malloc(sizeof(struct mmc)); - if (!dev) - return -ENOMEM; - - memset(dev, 0, sizeof(struct mmc)); - dev->priv = host; - writel(host->pwr_init, &host->base->power); writel(host->clkdiv_init, &host->base->clock); udelay(CLK_CHANGE_DELAY); @@ -359,19 +358,24 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host) /* Disable mmc interrupts */ sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK; writel(sdi_u32, &host->base->mask0); - strncpy(dev->name, host->name, sizeof(dev->name)); - dev->send_cmd = host_request; - dev->set_ios = host_set_ios; - dev->init = mmc_host_reset; - dev->getcd = NULL; - dev->getwp = NULL; - dev->host_caps = host->caps; - dev->voltages = host->voltages; - dev->f_min = host->clock_min; - dev->f_max = host->clock_max; - dev->b_max = host->b_max; - mmc_register(dev); - debug("registered mmc interface number is:%d\n", dev->block_dev.dev); + + host->cfg.name = host->name; + host->cfg.ops = &arm_pl180_mmci_ops; + /* TODO remove the duplicates */ + host->cfg.host_caps = host->caps; + host->cfg.voltages = host->voltages; + host->cfg.f_min = host->clock_min; + host->cfg.f_max = host->clock_max; + if (host->b_max != 0) + host->cfg.b_max = host->b_max; + else + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&host->cfg, host); + if (mmc == NULL) + return -1; + + debug("registered mmc interface number is:%d\n", mmc->block_dev.dev); return 0; } diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h index 72344498d6..f23bd391ee 100644 --- a/drivers/mmc/arm_pl180_mmci.h +++ b/drivers/mmc/arm_pl180_mmci.h @@ -13,6 +13,9 @@ #ifndef __ARM_PL180_MMCI_H__ #define __ARM_PL180_MMCI_H__ +/* need definition of struct mmc_config */ +#include <mmc.h> + #define COMMAND_REG_DELAY 300 #define DATA_REG_DELAY 1000 #define CLK_CHANGE_DELAY 2000 @@ -184,6 +187,7 @@ struct pl180_mmc_host { unsigned int clkdiv_init; unsigned int pwr_init; int version2; + struct mmc_config cfg; }; int arm_pl180_mmci_init(struct pl180_mmc_host *); diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index bd9b641135..bcd6a3e52f 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -274,30 +274,30 @@ static int bfin_sdh_init(struct mmc *mmc) return 0; } +static const struct mmc_ops bfin_mmc_ops = { + .send_cmd = bfin_sdh_request, + .set_ios = bfin_sdh_set_ios, + .init = bfin_sdh_init, +}; + +static struct mmc_config bfin_mmc_cfg = { + .name = "Blackfin SDH", + .ops = &bfin_mmc_ops, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; int bfin_mmc_init(bd_t *bis) { - struct mmc *mmc = NULL; + struct mmc *mmc; - mmc = malloc(sizeof(struct mmc)); + bfin_mmc_cfg.f_max = get_sclk(); + bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9; - if (!mmc) - return -ENOMEM; - sprintf(mmc->name, "Blackfin SDH"); - mmc->send_cmd = bfin_sdh_request; - mmc->set_ios = bfin_sdh_set_ios; - mmc->init = bfin_sdh_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_4BIT; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = get_sclk(); - mmc->f_min = mmc->f_max >> 9; - - mmc->b_max = 0; - - mmc_register(mmc); + mmc = mmc_create(&bfin_mmc_cfg, NULL); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index b380961188..aae00e9dab 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -30,10 +30,10 @@ static void dmmc_set_clock(struct mmc *mmc, uint clock) struct davinci_mmc_regs *regs = host->reg_base; uint clkrt, sysclk2, act_clock; - if (clock < mmc->f_min) - clock = mmc->f_min; - if (clock > mmc->f_max) - clock = mmc->f_max; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; + if (clock > mmc->cfg->f_max) + clock = mmc->cfg->f_max; set_val(®s->mmcclk, 0); sysclk2 = host->input_clk; @@ -363,32 +363,27 @@ static void dmmc_set_ios(struct mmc *mmc) dmmc_set_clock(mmc, mmc->clock); } +static const struct mmc_ops dmmc_ops = { + .send_cmd = dmmc_send_cmd, + .set_ios = dmmc_set_ios, + .init = dmmc_init, +}; + /* Called from board_mmc_init during startup. Can be called multiple times * depending on the number of slots available on board and controller */ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) { - struct mmc *mmc; - - mmc = malloc(sizeof(struct mmc)); - memset(mmc, 0, sizeof(struct mmc)); - - sprintf(mmc->name, "davinci"); - mmc->priv = host; - mmc->send_cmd = dmmc_send_cmd; - mmc->set_ios = dmmc_set_ios; - mmc->init = dmmc_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - - mmc->f_min = 200000; - mmc->f_max = 25000000; - mmc->voltages = host->voltages; - mmc->host_caps = host->host_caps; + host->cfg.name = "davinci"; + host->cfg.ops = &dmmc_ops; + host->cfg.f_min = 200000; + host->cfg.f_max = 25000000; + host->cfg.voltages = host->voltages; + host->cfg.host_caps = host->host_caps; - mmc->b_max = DAVINCI_MAX_BLOCKS; + host->cfg.b_max = DAVINCI_MAX_BLOCKS; - mmc_register(mmc); + mmc_create(&host->cfg, host); return 0; } diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index d45c15cfa4..eb4e2be514 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -107,7 +107,7 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host, static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + struct dwmci_host *host = mmc->priv; ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data ? DIV_ROUND_UP(data->blocks, 8) : 0); int flags = 0, i; @@ -284,7 +284,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) static void dwmci_set_ios(struct mmc *mmc) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + struct dwmci_host *host = mmc->priv; u32 ctype; debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); @@ -310,7 +310,7 @@ static void dwmci_set_ios(struct mmc *mmc) static int dwmci_init(struct mmc *mmc) { - struct dwmci_host *host = (struct dwmci_host *)mmc->priv; + struct dwmci_host *host = mmc->priv; if (host->board_init) host->board_init(host); @@ -323,7 +323,7 @@ static int dwmci_init(struct mmc *mmc) } /* Enumerate at 400KHz */ - dwmci_setup_bus(host, mmc->f_min); + dwmci_setup_bus(host, mmc->cfg->f_min); dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); dwmci_writel(host, DWMCI_INTMASK, 0); @@ -343,41 +343,37 @@ static int dwmci_init(struct mmc *mmc) return 0; } +static const struct mmc_ops dwmci_ops = { + .send_cmd = dwmci_send_cmd, + .set_ios = dwmci_set_ios, + .init = dwmci_init, +}; + int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) { - struct mmc *mmc; - int err = 0; - - mmc = calloc(sizeof(struct mmc), 1); - if (!mmc) { - printf("mmc calloc fail!\n"); - return -1; - } - - mmc->priv = host; - host->mmc = mmc; + host->cfg.name = host->name; + host->cfg.ops = &dwmci_ops; + host->cfg.f_min = min_clk; + host->cfg.f_max = max_clk; - sprintf(mmc->name, "%s", host->name); - mmc->send_cmd = dwmci_send_cmd; - mmc->set_ios = dwmci_set_ios; - mmc->init = dwmci_init; - mmc->f_min = min_clk; - mmc->f_max = max_clk; + host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - - mmc->host_caps = host->caps; + host->cfg.host_caps = host->caps; if (host->buswidth == 8) { - mmc->host_caps |= MMC_MODE_8BIT; - mmc->host_caps &= ~MMC_MODE_4BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps &= ~MMC_MODE_4BIT; } else { - mmc->host_caps |= MMC_MODE_4BIT; - mmc->host_caps &= ~MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_4BIT; + host->cfg.host_caps &= ~MMC_MODE_8BIT; } - mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; + host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC; + + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - err = mmc_register(mmc); + host->mmc = mmc_create(&host->cfg, host); + if (host->mmc == NULL) + return -1; - return err; + return 0; } diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 7b146a3604..4c3b93d413 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -172,7 +172,7 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) { int timeout; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO uint wml_value; @@ -221,16 +221,16 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) * 2)Timeout period should be minimum 0.250sec as per SD Card spec * So, Number of SD Clock cycles for 0.25sec should be minimum * (SD Clock/sec * 0.25 sec) SD Clock cycles - * = (mmc->tran_speed * 1/4) SD Clock cycles + * = (mmc->clock * 1/4) SD Clock cycles * As 1) >= 2) - * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * => (2^(timeout+13)) >= mmc->clock * 1/4 * Taking log2 both the sides - * => timeout + 13 >= log2(mmc->tran_speed/4) + * => timeout + 13 >= log2(mmc->clock/4) * Rounding up to next power of 2 - * => timeout + 13 = log2(mmc->tran_speed/4) + 1 - * => timeout + 13 = fls(mmc->tran_speed/4) + * => timeout + 13 = log2(mmc->clock/4) + 1 + * => timeout + 13 = fls(mmc->clock/4) */ - timeout = fls(mmc->tran_speed/4); + timeout = fls(mmc->clock/4); timeout -= 13; if (timeout > 14) @@ -244,6 +244,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) timeout++; #endif +#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE + timeout = 0xE; +#endif esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); return 0; @@ -265,9 +268,10 @@ static void check_and_invalidate_dcache_range static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { + int err = 0; uint xfertyp; uint irqstat; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -296,8 +300,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Set up for a data transfer if we have one */ if (data) { - int err; - err = esdhc_setup_data(mmc, data); if(err) return err; @@ -325,27 +327,15 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = esdhc_read32(®s->irqstat); - /* Reset CMD and DATA portions on error */ - if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { - esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | - SYSCTL_RSTC); - while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) - ; - - if (data) { - esdhc_write32(®s->sysctl, - esdhc_read32(®s->sysctl) | - SYSCTL_RSTD); - while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) - ; - } + if (irqstat & CMD_ERR) { + err = COMM_ERR; + goto out; } - if (irqstat & CMD_ERR) - return COMM_ERR; - - if (irqstat & IRQSTAT_CTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_CTOE) { + err = TIMEOUT; + goto out; + } /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { @@ -360,7 +350,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (timeout <= 0) { printf("Timeout waiting for DAT0 to go high!\n"); - return TIMEOUT; + err = TIMEOUT; + goto out; } } @@ -387,32 +378,53 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) do { irqstat = esdhc_read32(®s->irqstat); - if (irqstat & IRQSTAT_DTOE) - return TIMEOUT; + if (irqstat & IRQSTAT_DTOE) { + err = TIMEOUT; + goto out; + } - if (irqstat & DATA_ERR) - return COMM_ERR; + if (irqstat & DATA_ERR) { + err = COMM_ERR; + goto out; + } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); #endif if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); } +out: + /* Reset CMD and DATA portions on error */ + if (err) { + esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | + SYSCTL_RSTC); + while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + esdhc_write32(®s->sysctl, + esdhc_read32(®s->sysctl) | + SYSCTL_RSTD); + while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) + ; + } + } + esdhc_write32(®s->irqstat, -1); - return 0; + return err; } static void set_sysctl(struct mmc *mmc, uint clock) { int div, pre_div; - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int sdhc_clk = cfg->sdhc_clk; uint clk; - if (clock < mmc->f_min) - clock = mmc->f_min; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; if (sdhc_clk / 16 > clock) { for (pre_div = 2; pre_div < 256; pre_div *= 2) @@ -443,7 +455,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) static void esdhc_set_ios(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; /* Set the clock speed */ @@ -461,7 +473,7 @@ static void esdhc_set_ios(struct mmc *mmc) static int esdhc_init(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; @@ -496,7 +508,7 @@ static int esdhc_init(struct mmc *mmc) static int esdhc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; @@ -524,6 +536,13 @@ static void esdhc_reset(struct fsl_esdhc *regs) printf("MMC/SD: Reset never completed.\n"); } +static const struct mmc_ops esdhc_ops = { + .send_cmd = esdhc_send_cmd, + .set_ios = esdhc_set_ios, + .init = esdhc_init, + .getcd = esdhc_getcd, +}; + int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) { struct fsl_esdhc *regs; @@ -533,12 +552,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (!cfg) return -1; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - return -ENOMEM; - - memset(mmc, 0, sizeof(struct mmc)); - sprintf(mmc->name, "FSL_SDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; /* First reset the eSDHC controller */ @@ -547,12 +560,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); - mmc->priv = cfg; - mmc->send_cmd = esdhc_send_cmd; - mmc->set_ios = esdhc_set_ios; - mmc->init = esdhc_init; - mmc->getcd = esdhc_getcd; - mmc->getwp = NULL; + memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; caps = regs->hostcapblt; @@ -574,38 +582,43 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (caps & ESDHC_HOSTCAPBLT_VS33) voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->cfg.name = "FSL_SDHC"; + cfg->cfg.ops = &esdhc_ops; #ifdef CONFIG_SYS_SD_VOLTAGE - mmc->voltages = CONFIG_SYS_SD_VOLTAGE; + cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; #else - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; #endif - if ((mmc->voltages & voltage_caps) == 0) { + if ((cfg->cfg.voltages & voltage_caps) == 0) { printf("voltage not supported by controller\n"); return -1; } - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; + cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) - mmc->host_caps &= ~MMC_MODE_8BIT; + cfg->cfg.host_caps &= ~MMC_MODE_8BIT; if (cfg->max_bus_width < 4) - mmc->host_caps &= ~MMC_MODE_4BIT; + cfg->cfg.host_caps &= ~MMC_MODE_4BIT; } if (caps & ESDHC_HOSTCAPBLT_HSS) - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) - mmc->host_caps &= ~MMC_MODE_8BIT; + cfg->cfg.host_caps &= ~MMC_MODE_8BIT; #endif - mmc->f_min = 400000; - mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000); + cfg->cfg.f_min = 400000; + cfg->cfg.f_max = MIN(gd->arch.sdhc_clk, 52000000); - mmc->b_max = 0; - mmc_register(mmc); + cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + mmc = mmc_create(&cfg->cfg, cfg); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 7600d5ce55..a620678e5f 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -27,6 +27,7 @@ struct ftsdc010_chip { uint32_t sclk; /* FTSDC010 source clock in Hz */ uint32_t fifo; /* fifo depth in bytes */ uint32_t acmd; + struct mmc_config cfg; /* mmc configuration */ }; static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) @@ -123,14 +124,6 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) } } -static inline int ftsdc010_is_ro(struct mmc *mmc) -{ - struct ftsdc010_chip *chip = mmc->priv; - const uint8_t *csd = (const uint8_t *)mmc->csd; - - return chip->wprot || (csd[1] & 0x30); -} - static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) { int ret = TIMEOUT; @@ -316,6 +309,12 @@ static int ftsdc010_init(struct mmc *mmc) return 0; } +static const struct mmc_ops ftsdc010_ops = { + .send_cmd = ftsdc010_request, + .set_ios = ftsdc010_set_ios, + .init = ftsdc010_init, +}; + int ftsdc010_mmc_init(int devid) { struct mmc *mmc; @@ -331,50 +330,44 @@ int ftsdc010_mmc_init(int devid) regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20)); #endif - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - return -ENOMEM; - memset(mmc, 0, sizeof(struct mmc)); - chip = malloc(sizeof(struct ftsdc010_chip)); - if (!chip) { - free(mmc); + if (!chip) return -ENOMEM; - } memset(chip, 0, sizeof(struct ftsdc010_chip)); chip->regs = regs; - mmc->priv = chip; - - sprintf(mmc->name, "ftsdc010"); - mmc->send_cmd = ftsdc010_request; - mmc->set_ios = ftsdc010_set_ios; - mmc->init = ftsdc010_init; +#ifdef CONFIG_SYS_CLK_FREQ + chip->sclk = CONFIG_SYS_CLK_FREQ; +#else + chip->sclk = clk_get_rate("SDC"); +#endif - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; + chip->cfg.name = "ftsdc010"; + chip->cfg.ops = &ftsdc010_ops; + chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { case FTSDC010_BWR_CAPS_4BIT: - mmc->host_caps |= MMC_MODE_4BIT; + chip->cfg.host_caps |= MMC_MODE_4BIT; break; case FTSDC010_BWR_CAPS_8BIT: - mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; + chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; break; default: break; } -#ifdef CONFIG_SYS_CLK_FREQ - chip->sclk = CONFIG_SYS_CLK_FREQ; -#else - chip->sclk = clk_get_rate("SDC"); -#endif + chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + chip->cfg.f_max = chip->sclk / 2; + chip->cfg.f_min = chip->sclk / 0x100; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = chip->sclk / 2; - mmc->f_min = chip->sclk / 0x100; - mmc->block_dev.part_type = PART_TYPE_DOS; + chip->cfg.part_type = PART_TYPE_DOS; + chip->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc_register(mmc); + mmc = mmc_create(&chip->cfg, chip); + if (mmc == NULL) { + free(chip); + return -ENOMEM; + } return 0; } diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index c11dcd0f97..acca0269e5 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -55,7 +55,7 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) /* Setup for MCI Clock and Block Size */ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; u32 bus_hz = get_mci_clk_rate(); u32 clkdiv = 255; @@ -165,7 +165,7 @@ io_fail: static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; u32 cmdr; u32 error_flags = 0; u32 status; @@ -289,7 +289,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Entered into mmc structure during driver init */ static void mci_set_ios(struct mmc *mmc) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; @@ -325,7 +325,7 @@ static void mci_set_ios(struct mmc *mmc) /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { - atmel_mci_t *mci = (atmel_mci_t *)mmc->priv; + atmel_mci_t *mci = mmc->priv; /* Initialize controller */ writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ @@ -344,6 +344,12 @@ static int mci_init(struct mmc *mmc) return 0; } +static const struct mmc_ops atmel_mci_ops = { + .send_cmd = mci_send_cmd, + .set_ios = mci_set_ios, + .init = mci_init, +}; + /* * This is the only exported function * @@ -351,40 +357,45 @@ static int mci_init(struct mmc *mmc) */ int atmel_mci_init(void *regs) { - struct mmc *mmc = malloc(sizeof(struct mmc)); + struct mmc *mmc; + struct mmc_config *cfg; struct atmel_mci *mci; unsigned int version; - if (!mmc) + cfg = malloc(sizeof(*cfg)); + if (cfg == NULL) return -1; + memset(cfg, 0, sizeof(*cfg)); + + mci = (struct atmel_mci *)regs; - strcpy(mmc->name, "mci"); - mmc->priv = regs; - mmc->send_cmd = mci_send_cmd; - mmc->set_ios = mci_set_ios; - mmc->init = mci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; + cfg->name = "mci"; + cfg->ops = &atmel_mci_ops; /* need to be able to pass these in on a board by board basis */ - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mci = (struct atmel_mci *)mmc->priv; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; version = atmel_mci_get_version(mci); if ((version & 0xf00) >= 0x300) - mmc->host_caps = MMC_MODE_8BIT; + cfg->host_caps = MMC_MODE_8BIT; - mmc->host_caps |= MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_4BIT; /* * min and max frequencies determined by * max and min of clock divider */ - mmc->f_min = get_mci_clk_rate() / (2*256); - mmc->f_max = get_mci_clk_rate() / (2*1); + cfg->f_min = get_mci_clk_rate() / (2*256); + cfg->f_max = get_mci_clk_rate() / (2*1); + + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc->b_max = 0; + mmc = mmc_create(cfg, regs); - mmc_register(mmc); + if (mmc == NULL) { + free(cfg); + return -1; + } + /* NOTE: possibly leaking the cfg structure */ return 0; } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 8ab0bc948f..16051e52ff 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -17,11 +17,6 @@ #include <div64.h> #include "mmc_private.h" -/* Set block count limit because of 16 bit register limit on some hardware*/ -#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 -#endif - static struct list_head mmc_devices; static int cur_dev_num = -1; @@ -37,8 +32,8 @@ int mmc_getwp(struct mmc *mmc) wp = board_mmc_getwp(mmc); if (wp < 0) { - if (mmc->getwp) - wp = mmc->getwp(mmc); + if (mmc->cfg->ops->getwp) + wp = mmc->cfg->ops->getwp(mmc); else wp = 0; } @@ -63,7 +58,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) printf("CMD_SEND:%d\n", cmd->cmdidx); printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); - ret = mmc->send_cmd(mmc, cmd, data); + ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); switch (cmd->resp_type) { case MMC_RSP_NONE: printf("\t\tMMC_RSP_NONE\n"); @@ -106,7 +101,7 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) break; } #else - ret = mmc->send_cmd(mmc, cmd, data); + ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); #endif return ret; } @@ -253,7 +248,8 @@ static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) return 0; do { - cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo; + cur = (blocks_todo > mmc->cfg->b_max) ? + mmc->cfg->b_max : blocks_todo; if(mmc_read_blocks(mmc, dst, start, cur) != cur) return 0; blocks_todo -= cur; @@ -312,7 +308,7 @@ static int sd_send_op_cond(struct mmc *mmc) * specified. */ cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : - (mmc->voltages & 0xff8000); + (mmc->cfg->voltages & 0xff8000); if (mmc->version == SD_VERSION_2) cmd.cmdarg |= OCR_HCS; @@ -361,11 +357,11 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, cmd->cmdarg = 0; if (use_arg && !mmc_host_is_spi(mmc)) { cmd->cmdarg = - (mmc->voltages & + (mmc->cfg->voltages & (mmc->op_cond_response & OCR_VOLTAGE_MASK)) | (mmc->op_cond_response & OCR_ACCESS_MODE); - if (mmc->host_caps & MMC_MODE_HC) + if (mmc->cfg->host_caps & MMC_MODE_HC) cmd->cmdarg |= OCR_HCS; } err = mmc_send_cmd(mmc, cmd, NULL); @@ -578,8 +574,8 @@ int mmc_getcd(struct mmc *mmc) cd = board_mmc_getcd(mmc); if (cd < 0) { - if (mmc->getcd) - cd = mmc->getcd(mmc); + if (mmc->cfg->ops->getcd) + cd = mmc->cfg->ops->getcd(mmc); else cd = 1; } @@ -703,8 +699,8 @@ retry_scr: * This can avoid furthur problem when the card runs in different * mode between the host. */ - if (!((mmc->host_caps & MMC_MODE_HS_52MHz) && - (mmc->host_caps & MMC_MODE_HS))) + if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && + (mmc->cfg->host_caps & MMC_MODE_HS))) return 0; err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); @@ -751,16 +747,17 @@ static const int multipliers[] = { static void mmc_set_ios(struct mmc *mmc) { - mmc->set_ios(mmc); + if (mmc->cfg->ops->set_ios) + mmc->cfg->ops->set_ios(mmc); } void mmc_set_clock(struct mmc *mmc, uint clock) { - if (clock > mmc->f_max) - clock = mmc->f_max; + if (clock > mmc->cfg->f_max) + clock = mmc->cfg->f_max; - if (clock < mmc->f_min) - clock = mmc->f_min; + if (clock < mmc->cfg->f_min) + clock = mmc->cfg->f_min; mmc->clock = clock; @@ -1026,7 +1023,7 @@ static int mmc_startup(struct mmc *mmc) return err; /* Restrict card's capabilities by what the host can do */ - mmc->card_caps &= mmc->host_caps; + mmc->card_caps &= mmc->cfg->host_caps; if (IS_SD(mmc)) { if (mmc->card_caps & MMC_MODE_4BIT) { @@ -1081,7 +1078,7 @@ static int mmc_startup(struct mmc *mmc) * this bus width, if it's more than 1 */ if (extw != EXT_CSD_BUS_WIDTH_1 && - !(mmc->host_caps & ext_to_hostcaps[extw])) + !(mmc->cfg->host_caps & ext_to_hostcaps[extw])) continue; err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, @@ -1154,7 +1151,7 @@ static int mmc_send_if_cond(struct mmc *mmc) cmd.cmdidx = SD_CMD_SEND_IF_COND; /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ - cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa; + cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; cmd.resp_type = MMC_RSP_R7; err = mmc_send_cmd(mmc, &cmd, NULL); @@ -1170,8 +1167,33 @@ static int mmc_send_if_cond(struct mmc *mmc) return 0; } -int mmc_register(struct mmc *mmc) +/* not used any more */ +int __deprecated mmc_register(struct mmc *mmc) +{ +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + printf("%s is deprecated! use mmc_create() instead.\n", __func__); +#endif + return -1; +} + +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) { + struct mmc *mmc; + + /* quick validation */ + if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || + cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) + return NULL; + + mmc = calloc(1, sizeof(*mmc)); + if (mmc == NULL) + return NULL; + + mmc->cfg = cfg; + mmc->priv = priv; + + /* the following chunk was mmc_register() */ + /* Setup dsr related values */ mmc->dsr_imp = 0; mmc->dsr = 0xffffffff; @@ -1182,14 +1204,21 @@ int mmc_register(struct mmc *mmc) mmc->block_dev.block_read = mmc_bread; mmc->block_dev.block_write = mmc_bwrite; mmc->block_dev.block_erase = mmc_berase; - if (!mmc->b_max) - mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - INIT_LIST_HEAD (&mmc->link); + /* setup initial part type */ + mmc->block_dev.part_type = mmc->cfg->part_type; - list_add_tail (&mmc->link, &mmc_devices); + INIT_LIST_HEAD(&mmc->link); - return 0; + list_add_tail(&mmc->link, &mmc_devices); + + return mmc; +} + +void mmc_destroy(struct mmc *mmc) +{ + /* only freeing memory for now */ + free(mmc); } #ifdef CONFIG_PARTITIONS @@ -1207,7 +1236,8 @@ int mmc_start_init(struct mmc *mmc) { int err; - if (mmc_getcd(mmc) == 0) { + /* we pretend there's no card when init is NULL */ + if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { mmc->has_init = 0; #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC: no card present\n"); @@ -1218,7 +1248,8 @@ int mmc_start_init(struct mmc *mmc) if (mmc->has_init) return 0; - err = mmc->init(mmc); + /* made sure it's not NULL earlier */ + err = mmc->cfg->ops->init(mmc); if (err) return err; @@ -1320,7 +1351,7 @@ void print_mmc_devices(char separator) list_for_each(entry, &mmc_devices) { m = list_entry(entry, struct mmc, link); - printf("%s: %d", m->name, m->block_dev.dev); + printf("%s: %d", m->cfg->name, m->block_dev.dev); if (entry->next != &mmc_devices) printf("%c ", separator); @@ -1482,4 +1513,16 @@ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) return err; return 0; } + +/* + * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value + * for enable. Note that this is a write-once field for non-zero values. + * + * Returns 0 on success. + */ +int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) +{ + return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, + enable); +} #endif diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index fe6a5a166d..5b5b33a4b2 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -92,7 +92,7 @@ static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf, spi_xfer(spi, 2 * 8, NULL, &crc, 0); #ifdef CONFIG_MMC_SPI_CRC_ON if (swab16(cyg_crc16(buf, bsize)) != crc) { - debug("%s: CRC error\n", mmc->name); + debug("%s: CRC error\n", mmc->cfg->name); r1 = R1_SPI_COM_CRC; break; } @@ -238,6 +238,7 @@ done: static void mmc_spi_set_ios(struct mmc *mmc) { struct spi_slave *spi = mmc->priv; + debug("%s: clock %u\n", __func__, mmc->clock); if (mmc->clock) spi_set_speed(spi, mmc->clock); @@ -246,7 +247,6 @@ static void mmc_spi_set_ios(struct mmc *mmc) static int mmc_spi_init_p(struct mmc *mmc) { struct spi_slave *spi = mmc->priv; - mmc->clock = 0; spi_set_speed(spi, MMC_SPI_MIN_CLOCK); spi_claim_bus(spi); /* cs deactivated for 100+ clock */ @@ -255,33 +255,37 @@ static int mmc_spi_init_p(struct mmc *mmc) return 0; } +static const struct mmc_ops mmc_spi_ops = { + .send_cmd = mmc_spi_request, + .set_ios = mmc_spi_set_ios, + .init = mmc_spi_init_p, +}; + +static struct mmc_config mmc_spi_cfg = { + .name = "MMC_SPI", + .ops = &mmc_spi_ops, + .host_caps = MMC_MODE_SPI, + .voltages = MMC_SPI_VOLTAGE, + .f_min = MMC_SPI_MIN_CLOCK, + .part_type = PART_TYPE_DOS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode) { struct mmc *mmc; + struct spi_slave *spi; - mmc = malloc(sizeof(*mmc)); - if (!mmc) - return NULL; - memset(mmc, 0, sizeof(*mmc)); - mmc->priv = spi_setup_slave(bus, cs, speed, mode); - if (!mmc->priv) { - free(mmc); + spi = spi_setup_slave(bus, cs, speed, mode); + if (spi == NULL) return NULL; - } - sprintf(mmc->name, "MMC_SPI"); - mmc->send_cmd = mmc_spi_request; - mmc->set_ios = mmc_spi_set_ios; - mmc->init = mmc_spi_init_p; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_SPI; - - mmc->voltages = MMC_SPI_VOLTAGE; - mmc->f_max = speed; - mmc->f_min = MMC_SPI_MIN_CLOCK; - mmc->block_dev.part_type = PART_TYPE_DOS; - mmc_register(mmc); + mmc_spi_cfg.f_max = speed; + mmc = mmc_create(&mmc_spi_cfg, spi); + if (mmc == NULL) { + spi_free_slave(spi); + return NULL; + } return mmc; } diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index aa2fdefa75..3db9669c82 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -167,7 +167,8 @@ ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src) return 0; do { - cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo; + cur = (blocks_todo > mmc->cfg->b_max) ? + mmc->cfg->b_max : blocks_todo; if (mmc_write_blocks(mmc, start, cur, src) != cur) return 0; blocks_todo -= cur; diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index 4f99617b9a..561b204598 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -122,6 +122,8 @@ struct mxcmci_host { }; static struct mxcmci_host mxcmci_host; + +/* maintainer note: do we really want to have a global host pointer? */ static struct mxcmci_host *host = &mxcmci_host; static inline int mxcmci_use_dma(struct mxcmci_host *host) @@ -485,35 +487,30 @@ static int mxcmci_init(struct mmc *mmc) return 0; } -static int mxcmci_initialize(bd_t *bis) -{ - struct mmc *mmc = NULL; - - mmc = malloc(sizeof(struct mmc)); - - if (!mmc) - return -ENOMEM; +static const struct mmc_ops mxcmci_ops = { + .send_cmd = mxcmci_request, + .set_ios = mxcmci_set_ios, + .init = mxcmci_init, +}; - sprintf(mmc->name, "MXC MCI"); - mmc->send_cmd = mxcmci_request; - mmc->set_ios = mxcmci_set_ios; - mmc->init = mxcmci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->host_caps = MMC_MODE_4BIT; +static struct mmc_config mxcmci_cfg = { + .name = "MXC MCI", + .ops = &mxcmci_ops, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; +static int mxcmci_initialize(bd_t *bis) +{ host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE; - mmc->priv = host; - host->mmc = mmc; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - - mmc->f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7; - mmc->f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1; - mmc->b_max = 0; + mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7; + mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1; - mmc_register(mmc); + host->mmc = mmc_create(&mxcmci_cfg, host); + if (host->mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 245f9d0c67..2fa4eeef44 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -35,6 +35,7 @@ struct mxsmmc_priv { int (*mmc_is_wp)(int); int (*mmc_cd)(int); struct mxs_dma_desc *desc; + struct mmc_config cfg; /* mmc configuration */ }; #define MXSMMC_MAX_TIMEOUT 10000 @@ -134,7 +135,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; uint32_t reg; int timeout; @@ -305,7 +306,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) static void mxsmmc_set_ios(struct mmc *mmc) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; /* Set the clock speed */ @@ -334,7 +335,7 @@ static void mxsmmc_set_ios(struct mmc *mmc) static int mxsmmc_init(struct mmc *mmc) { - struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv; + struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; /* Reset SSP */ @@ -363,6 +364,12 @@ static int mxsmmc_init(struct mmc *mmc) return 0; } +static const struct mmc_ops mxsmmc_ops = { + .send_cmd = mxsmmc_send_cmd, + .set_ios = mxsmmc_set_ios, + .init = mxsmmc_init, +}; + int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) { struct mmc *mmc = NULL; @@ -373,20 +380,13 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) if (!mxs_ssp_bus_id_valid(id)) return -ENODEV; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - return -ENOMEM; - priv = malloc(sizeof(struct mxsmmc_priv)); - if (!priv) { - free(mmc); + if (!priv) return -ENOMEM; - } priv->desc = mxs_dma_desc_alloc(); if (!priv->desc) { free(priv); - free(mmc); return -ENOMEM; } @@ -399,17 +399,12 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) priv->id = id; priv->regs = mxs_ssp_regs_by_bus(id); - sprintf(mmc->name, "MXS MMC"); - mmc->send_cmd = mxsmmc_send_cmd; - mmc->set_ios = mxsmmc_set_ios; - mmc->init = mxsmmc_init; - mmc->getcd = NULL; - mmc->getwp = NULL; - mmc->priv = priv; + priv->cfg.name = "MXS MMC"; + priv->cfg.ops = &mxsmmc_ops; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | + priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; @@ -419,10 +414,15 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)) * CLOCK_DIVIDE has to be an even value from 2 to 254, and * CLOCK_RATE could be any integer from 0 to 255. */ - mmc->f_min = 400000; - mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; - mmc->b_max = 0x20; + priv->cfg.f_min = 400000; + priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2; + priv->cfg.b_max = 0x20; - mmc_register(mmc); + mmc = mmc_create(&priv->cfg, priv); + if (mmc == NULL) { + mxs_dma_desc_free(priv->desc); + free(priv); + return -ENOMEM; + } return 0; } diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index d3a8b5303d..17cbb0983d 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -24,6 +24,7 @@ #include <config.h> #include <common.h> +#include <malloc.h> #include <mmc.h> #include <part.h> #include <i2c.h> @@ -35,14 +36,25 @@ #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> +/* simplify defines to OMAP_HSMMC_USE_GPIO */ +#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +#define OMAP_HSMMC_USE_GPIO +#else +#undef OMAP_HSMMC_USE_GPIO +#endif + /* common definitions for all OMAPs */ #define SYSCTL_SRC (1 << 25) #define SYSCTL_SRD (1 << 26) struct omap_hsmmc_data { struct hsmmc *base_addr; + struct mmc_config cfg; +#ifdef OMAP_HSMMC_USE_GPIO int cd_gpio; int wp_gpio; +#endif }; /* If we fail after 1 second wait, something is really bad */ @@ -51,11 +63,8 @@ struct omap_hsmmc_data { static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); -static struct mmc hsmmc_dev[3]; -static struct omap_hsmmc_data hsmmc_dev_data[3]; -#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) +#ifdef OMAP_HSMMC_USE_GPIO static int omap_mmc_setup_gpio_in(int gpio, const char *label) { if (!gpio_is_valid(gpio)) @@ -69,26 +78,6 @@ static int omap_mmc_setup_gpio_in(int gpio, const char *label) return gpio; } - -static int omap_mmc_getcd(struct mmc *mmc) -{ - int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio; - return gpio_get_value(cd_gpio); -} - -static int omap_mmc_getwp(struct mmc *mmc) -{ - int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio; - return gpio_get_value(wp_gpio); -} -#else -static inline int omap_mmc_setup_gpio_in(int gpio, const char *label) -{ - return -1; -} - -#define omap_mmc_getcd NULL -#define omap_mmc_getwp NULL #endif #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER) @@ -158,7 +147,7 @@ unsigned char mmc_board_init(struct mmc *mmc) &t2_base->devconf1); /* Change from default of 52MHz to 26MHz if necessary */ - if (!(mmc->host_caps & MMC_MODE_HS_52MHz)) + if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz)) writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, &t2_base->ctl_prog_io1); @@ -213,7 +202,7 @@ void mmc_init_stream(struct hsmmc *mmc_base) } -static int mmc_init_setup(struct mmc *mmc) +static int omap_hsmmc_init_setup(struct mmc *mmc) { struct hsmmc *mmc_base; unsigned int reg_val; @@ -322,7 +311,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) } } -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct hsmmc *mmc_base; @@ -552,7 +541,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, return 0; } -static void mmc_set_ios(struct mmc *mmc) +static void omap_hsmmc_set_ios(struct mmc *mmc) { struct hsmmc *mmc_base; unsigned int dsor = 0; @@ -606,19 +595,58 @@ static void mmc_set_ios(struct mmc *mmc) writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); } +#ifdef OMAP_HSMMC_USE_GPIO +static int omap_hsmmc_getcd(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv_data = mmc->priv; + int cd_gpio; + + /* if no CD return as 1 */ + cd_gpio = priv_data->cd_gpio; + if (cd_gpio < 0) + return 1; + + return gpio_get_value(cd_gpio); +} + +static int omap_hsmmc_getwp(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv_data = mmc->priv; + int wp_gpio; + + /* if no WP return as 0 */ + wp_gpio = priv_data->wp_gpio; + if (wp_gpio < 0) + return 0; + + return gpio_get_value(wp_gpio); +} +#endif + +static const struct mmc_ops omap_hsmmc_ops = { + .send_cmd = omap_hsmmc_send_cmd, + .set_ios = omap_hsmmc_set_ios, + .init = omap_hsmmc_init_setup, +#ifdef OMAP_HSMMC_USE_GPIO + .getcd = omap_hsmmc_getcd, + .getwp = omap_hsmmc_getwp, +#endif +}; + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio) { - struct mmc *mmc = &hsmmc_dev[dev_index]; - struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index]; - uint host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | - MMC_MODE_HC; + struct mmc *mmc; + struct omap_hsmmc_data *priv_data; + struct mmc_config *cfg; + uint host_caps_val; - sprintf(mmc->name, "OMAP SD/MMC"); - mmc->send_cmd = mmc_send_cmd; - mmc->set_ios = mmc_set_ios; - mmc->init = mmc_init_setup; - mmc->priv = priv_data; + priv_data = malloc(sizeof(*priv_data)); + if (priv_data == NULL) + return -1; + + host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | + MMC_MODE_HC; switch (dev_index) { case 0: @@ -647,42 +675,46 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE; return 1; } +#ifdef OMAP_HSMMC_USE_GPIO + /* on error gpio values are set to -1, which is what we want */ priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); - if (priv_data->cd_gpio != -1) - mmc->getcd = omap_mmc_getcd; - priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); - if (priv_data->wp_gpio != -1) - mmc->getwp = omap_mmc_getwp; +#endif + + cfg = &priv_data->cfg; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->host_caps = host_caps_val & ~host_caps_mask; + cfg->name = "OMAP SD/MMC"; + cfg->ops = &omap_hsmmc_ops; - mmc->f_min = 400000; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->host_caps = host_caps_val & ~host_caps_mask; + + cfg->f_min = 400000; if (f_max != 0) - mmc->f_max = f_max; + cfg->f_max = f_max; else { - if (mmc->host_caps & MMC_MODE_HS) { - if (mmc->host_caps & MMC_MODE_HS_52MHz) - mmc->f_max = 52000000; + if (cfg->host_caps & MMC_MODE_HS) { + if (cfg->host_caps & MMC_MODE_HS_52MHz) + cfg->f_max = 52000000; else - mmc->f_max = 26000000; + cfg->f_max = 26000000; } else - mmc->f_max = 20000000; + cfg->f_max = 20000000; } - mmc->b_max = 0; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; #if defined(CONFIG_OMAP34XX) /* * Silicon revs 2.1 and older do not support multiblock transfers. */ if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) - mmc->b_max = 1; + cfg->b_max = 1; #endif - - mmc_register(mmc); + mmc = mmc_create(cfg, priv_data); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 29f3eaf30b..1f297571e5 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -52,7 +52,7 @@ struct pxa_mmc_priv { /* Wait for bit to be set */ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; unsigned int timeout = PXA_MMC_TIMEOUT; @@ -71,7 +71,7 @@ static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask) static int pxa_mmc_stop_clock(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; unsigned int timeout = PXA_MMC_TIMEOUT; @@ -100,7 +100,7 @@ static int pxa_mmc_stop_clock(struct mmc *mmc) static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, uint32_t cmdat) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; int ret; @@ -143,7 +143,7 @@ static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd, static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t a, b, c; int i; @@ -185,7 +185,7 @@ static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd) static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t len; uint32_t *buf = (uint32_t *)data->dest; @@ -221,7 +221,7 @@ static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data) static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t len; uint32_t *buf = (uint32_t *)data->src; @@ -264,7 +264,7 @@ static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data) static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t cmdat = 0; int ret; @@ -317,7 +317,7 @@ static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, static void pxa_mmc_set_ios(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; uint32_t tmp; uint32_t pxa_mmc_clock; @@ -335,7 +335,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc) /* Set clock to the card the usual way. */ pxa_mmc_clock = 0; - tmp = mmc->f_max / mmc->clock; + tmp = mmc->cfg->f_max / mmc->clock; tmp += tmp % 2; while (tmp > 1) { @@ -348,7 +348,7 @@ static void pxa_mmc_set_ios(struct mmc *mmc) static int pxa_mmc_init(struct mmc *mmc) { - struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv; + struct pxa_mmc_priv *priv = mmc->priv; struct pxa_mmc_regs *regs = priv->regs; /* Make sure the clock are stopped */ @@ -366,6 +366,22 @@ static int pxa_mmc_init(struct mmc *mmc) return 0; } +static const struct mmc_ops pxa_mmc_ops = { + .send_cmd = pxa_mmc_request, + .set_ios = pxa_mmc_set_ios, + .init = pxa_mmc_init, +}; + +static struct mmc_config pxa_mmc_cfg = { + .name = "PXA MMC", + .ops = &pxa_mmc_ops, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .f_max = PXAMMC_MAX_SPEED, + .f_min = PXAMMC_MIN_SPEED, + .host_caps = PXAMMC_HOST_CAPS, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + int pxa_mmc_register(int card_index) { struct mmc *mmc; @@ -373,13 +389,11 @@ int pxa_mmc_register(int card_index) uint32_t reg; int ret = -ENOMEM; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - goto err0; - priv = malloc(sizeof(struct pxa_mmc_priv)); if (!priv) - goto err1; + goto err0; + + memset(priv, 0, sizeof(*priv)); switch (card_index) { case 0: @@ -389,26 +403,12 @@ int pxa_mmc_register(int card_index) priv->regs = (struct pxa_mmc_regs *)MMC1_BASE; break; default: + ret = -EINVAL; printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n", card_index); - goto err2; + goto err1; } - mmc->priv = priv; - - sprintf(mmc->name, "PXA MMC"); - mmc->send_cmd = pxa_mmc_request; - mmc->set_ios = pxa_mmc_set_ios; - mmc->init = pxa_mmc_init; - mmc->getcd = NULL; - - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->f_max = PXAMMC_MAX_SPEED; - mmc->f_min = PXAMMC_MIN_SPEED; - mmc->host_caps = PXAMMC_HOST_CAPS; - - mmc->b_max = 0; - #ifndef CONFIG_CPU_MONAHANS /* PXA2xx */ reg = readl(CKEN); reg |= CKEN12_MMC; @@ -419,14 +419,14 @@ int pxa_mmc_register(int card_index) writel(reg, CKENA); #endif - mmc_register(mmc); + mmc = mmc_create(&pxa_mmc_cfg, priv); + if (mmc == NULL) + goto err1; return 0; -err2: - free(priv); err1: - free(mmc); + free(priv); err0: return ret; } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 40ff8739bf..ccae4ccae1 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -8,8 +8,15 @@ #include <common.h> #include <malloc.h> #include <sdhci.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <asm/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/clk.h> +#include <errno.h> +#ifdef CONFIG_OF_CONTROL +#include <asm/arch/pinmux.h> +#endif static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) @@ -86,3 +93,125 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) return add_sdhci(host, 52000000, 400000); } + +#ifdef CONFIG_OF_CONTROL +struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; + +static int do_sdhci_init(struct sdhci_host *host) +{ + int dev_id, flag; + int err = 0; + + flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + dev_id = host->index + PERIPH_ID_SDMMC0; + + if (fdt_gpio_isvalid(&host->pwr_gpio)) { + gpio_direction_output(host->pwr_gpio.gpio, 1); + err = exynos_pinmux_config(dev_id, flag); + if (err) { + debug("MMC not configured\n"); + return err; + } + } + + if (fdt_gpio_isvalid(&host->cd_gpio)) { + gpio_direction_output(host->cd_gpio.gpio, 0xf); + if (gpio_get_value(host->cd_gpio.gpio)) + return -ENODEV; + + err = exynos_pinmux_config(dev_id, flag); + if (err) { + printf("external SD not configured\n"); + return err; + } + } + + host->name = S5P_NAME; + + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | + SDHCI_QUIRK_WAIT_SEND_CMD; + host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + host->set_control_reg = &s5p_sdhci_set_control_reg; + host->set_clock = set_mmc_clk; + + host->host_caps = MMC_MODE_HC; + + return add_sdhci(host, 52000000, 400000); +} + +static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) +{ + int bus_width, dev_id; + unsigned int base; + + /* Get device id */ + dev_id = pinmux_decode_periph_id(blob, node); + if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) { + debug("MMC: Can't get device id\n"); + return -1; + } + host->index = dev_id - PERIPH_ID_SDMMC0; + + /* Get bus width */ + bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (bus_width <= 0) { + debug("MMC: Can't get bus-width\n"); + return -1; + } + host->bus_width = bus_width; + + /* Get the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("MMC: Can't get base address\n"); + return -1; + } + host->ioaddr = (void *)base; + + fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio); + fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio); + + return 0; +} + +static int process_nodes(const void *blob, int node_list[], int count) +{ + struct sdhci_host *host; + int i, node; + + debug("%s: count = %d\n", __func__, count); + + /* build sdhci_host[] for each controller */ + for (i = 0; i < count; i++) { + node = node_list[i]; + if (node <= 0) + continue; + + host = &sdhci_host[i]; + + if (sdhci_get_config(blob, node, host)) { + printf("%s: failed to decode dev %d\n", __func__, i); + return -1; + } + do_sdhci_init(host); + } + return 0; +} + +int exynos_mmc_init(const void *blob) +{ + int count; + int node_list[SDHCI_MAX_HOSTS]; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + COMPAT_SAMSUNG_EXYNOS_MMC, node_list, + SDHCI_MAX_HOSTS); + + process_nodes(blob, node_list, count); + + return 1; +} +#endif diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 1e86b92bee..3125d13ba3 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -127,7 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; unsigned int stat = 0; int ret = 0; int trans_bytes = 0, is_aligned = 1; @@ -268,7 +268,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; unsigned int div, clk, timeout; sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); @@ -278,18 +278,18 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { /* Version 3.00 divisors must be a multiple of 2. */ - if (mmc->f_max <= clock) + if (mmc->cfg->f_max <= clock) div = 1; else { for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { - if ((mmc->f_max / div) <= clock) + if ((mmc->cfg->f_max / div) <= clock) break; } } } else { /* Version 2.00 divisors must be a power of 2. */ for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { - if ((mmc->f_max / div) <= clock) + if ((mmc->cfg->f_max / div) <= clock) break; } } @@ -358,7 +358,7 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) void sdhci_set_ios(struct mmc *mmc) { u32 ctrl; - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; if (host->set_control_reg) host->set_control_reg(host); @@ -395,7 +395,7 @@ void sdhci_set_ios(struct mmc *mmc) int sdhci_init(struct mmc *mmc) { - struct sdhci_host *host = (struct sdhci_host *)mmc->priv; + struct sdhci_host *host = mmc->priv; if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { aligned_buffer = memalign(8, 512*1024); @@ -406,7 +406,7 @@ int sdhci_init(struct mmc *mmc) } } - sdhci_set_power(host, fls(mmc->voltages) - 1); + sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); if (host->quirks & SDHCI_QUIRK_NO_CD) { unsigned int status; @@ -430,26 +430,19 @@ int sdhci_init(struct mmc *mmc) return 0; } + +static const struct mmc_ops sdhci_ops = { + .send_cmd = sdhci_send_command, + .set_ios = sdhci_set_ios, + .init = sdhci_init, +}; + int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) { - struct mmc *mmc; unsigned int caps; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) { - printf("%s: mmc malloc fail!\n", __func__); - return -1; - } - - mmc->priv = host; - host->mmc = mmc; - - sprintf(mmc->name, "%s", host->name); - mmc->send_cmd = sdhci_send_command; - mmc->set_ios = sdhci_set_ios; - mmc->init = sdhci_init; - mmc->getcd = NULL; - mmc->getwp = NULL; + host->cfg.name = host->name; + host->cfg.ops = &sdhci_ops; caps = sdhci_readl(host, SDHCI_CAPABILITIES); #ifdef CONFIG_MMC_SDMA @@ -461,51 +454,60 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) #endif if (max_clk) - mmc->f_max = max_clk; + host->cfg.f_max = max_clk; else { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) + host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; else - mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK) + host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; - mmc->f_max *= 1000000; + host->cfg.f_max *= 1000000; } - if (mmc->f_max == 0) { + if (host->cfg.f_max == 0) { printf("%s: Hardware doesn't specify base clock frequency\n", __func__); return -1; } if (min_clk) - mmc->f_min = min_clk; + host->cfg.f_min = min_clk; else { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; + host->cfg.f_min = host->cfg.f_max / + SDHCI_MAX_DIV_SPEC_300; else - mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; + host->cfg.f_min = host->cfg.f_max / + SDHCI_MAX_DIV_SPEC_200; } - mmc->voltages = 0; + host->cfg.voltages = 0; if (caps & SDHCI_CAN_VDD_330) - mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; if (caps & SDHCI_CAN_VDD_300) - mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; if (caps & SDHCI_CAN_VDD_180) - mmc->voltages |= MMC_VDD_165_195; + host->cfg.voltages |= MMC_VDD_165_195; if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) - mmc->voltages |= host->voltages; + host->cfg.voltages |= host->voltages; - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; + host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { if (caps & SDHCI_CAN_DO_8BIT) - mmc->host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; } if (host->host_caps) - mmc->host_caps |= host->host_caps; + host->cfg.host_caps |= host->host_caps; + + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; sdhci_reset(host, SDHCI_RESET_ALL); - mmc_register(mmc); + + host->mmc = mmc_create(&host->cfg, host); + if (host->mmc == NULL) { + printf("%s: mmc create fail!\n", __func__); + return -1; + } return 0; } diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 011d4f3e63..ed83a14c2d 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -20,11 +20,6 @@ #define DRIVER_NAME "sh_mmcif" -static void *mmc_priv(struct mmc *mmc) -{ - return (void *)mmc->priv; -} - static int sh_mmcif_intr(void *dev_id) { struct sh_mmcif_host *host = dev_id; @@ -522,7 +517,7 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; int ret; WATCHDOG_RESET(); @@ -550,7 +545,7 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, static void sh_mmcif_set_ios(struct mmc *mmc) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; if (mmc->clock) sh_mmcif_clock_control(host, mmc->clock); @@ -567,44 +562,48 @@ static void sh_mmcif_set_ios(struct mmc *mmc) static int sh_mmcif_init(struct mmc *mmc) { - struct sh_mmcif_host *host = mmc_priv(mmc); + struct sh_mmcif_host *host = mmc->priv; sh_mmcif_sync_reset(host); sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); return 0; } +static const struct mmc_ops sh_mmcif_ops = { + .send_cmd = sh_mmcif_request, + .set_ios = sh_mmcif_set_ios, + .init = sh_mmcif_init, +}; + +static struct mmc_config sh_mmcif_cfg = { + .name = DRIVER_NAME, + .ops = &sh_mmcif_ops, + .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | + MMC_MODE_8BIT | MMC_MODE_HC, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .f_min = CLKDEV_MMC_INIT, + .f_max = CLKDEV_EMMC_DATA, + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, +}; + int mmcif_mmc_init(void) { - int ret = 0; struct mmc *mmc; struct sh_mmcif_host *host = NULL; - mmc = malloc(sizeof(struct mmc)); - if (!mmc) - ret = -ENOMEM; - memset(mmc, 0, sizeof(*mmc)); host = malloc(sizeof(struct sh_mmcif_host)); if (!host) - ret = -ENOMEM; + return -ENOMEM; memset(host, 0, sizeof(*host)); - mmc->f_min = CLKDEV_MMC_INIT; - mmc->f_max = CLKDEV_EMMC_DATA; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; - mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | - MMC_MODE_8BIT | MMC_MODE_HC; - memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME)); - mmc->send_cmd = sh_mmcif_request; - mmc->set_ios = sh_mmcif_set_ios; - mmc->init = sh_mmcif_init; - mmc->getcd = NULL; - mmc->getwp = NULL; host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; host->clk = CONFIG_SH_MMCIF_CLK; - mmc->priv = host; - mmc_register(mmc); + mmc = mmc_create(&sh_mmcif_cfg, host); + if (mmc == NULL) { + free(host); + return -ENOMEM; + } - return ret; + return 0; } diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index 3d1ce1263c..ed67eec252 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -18,7 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct mmc mmc_dev[MAX_HOSTS]; struct mmc_host mmc_host[MAX_HOSTS]; #ifndef CONFIG_OF_CONTROL @@ -145,7 +144,7 @@ static int mmc_wait_inhibit(struct mmc_host *host, static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data, struct bounce_buffer *bbstate) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; int flags, i; int result; unsigned int mask = 0; @@ -314,7 +313,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, return 0; } -static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { void *buf; @@ -396,7 +395,7 @@ out: host->clock = clock; } -static void mmc_set_ios(struct mmc *mmc) +static void tegra_mmc_set_ios(struct mmc *mmc) { struct mmc_host *host = mmc->priv; unsigned char ctrl; @@ -456,7 +455,7 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc) } /* Set SD bus voltage & enable bus power */ - mmc_set_power(host, fls(mmc->voltages) - 1); + mmc_set_power(host, fls(mmc->cfg->voltages) - 1); debug("%s: power control = %02X, host control = %02X\n", __func__, readb(&host->reg->pwrcon), readb(&host->reg->hostctl)); @@ -464,9 +463,9 @@ static void mmc_reset(struct mmc_host *host, struct mmc *mmc) pad_init_mmc(host); } -static int mmc_core_init(struct mmc *mmc) +static int tegra_mmc_core_init(struct mmc *mmc) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; unsigned int mask; debug(" mmc_core_init called\n"); @@ -511,7 +510,7 @@ static int mmc_core_init(struct mmc *mmc) int tegra_mmc_getcd(struct mmc *mmc) { - struct mmc_host *host = (struct mmc_host *)mmc->priv; + struct mmc_host *host = mmc->priv; debug("tegra_mmc_getcd called\n"); @@ -521,6 +520,13 @@ int tegra_mmc_getcd(struct mmc *mmc) return 1; } +static const struct mmc_ops tegra_mmc_ops = { + .send_cmd = tegra_mmc_send_cmd, + .set_ios = tegra_mmc_set_ios, + .init = tegra_mmc_core_init, + .getcd = tegra_mmc_getcd, +}; + static int do_mmc_init(int dev_index) { struct mmc_host *host; @@ -554,23 +560,18 @@ static int do_mmc_init(int dev_index) debug(" CD GPIO name = %s\n", host->cd_gpio.name); } - mmc = &mmc_dev[dev_index]; + memset(&host->cfg, 0, sizeof(host->cfg)); - sprintf(mmc->name, "Tegra SD/MMC"); - mmc->priv = host; - mmc->send_cmd = mmc_send_cmd; - mmc->set_ios = mmc_set_ios; - mmc->init = mmc_core_init; - mmc->getcd = tegra_mmc_getcd; - mmc->getwp = NULL; + host->cfg.name = "Tegra SD/MMC"; + host->cfg.ops = &tegra_mmc_ops; - mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - mmc->host_caps = 0; + host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + host->cfg.host_caps = 0; if (host->width == 8) - mmc->host_caps |= MMC_MODE_8BIT; + host->cfg.host_caps |= MMC_MODE_8BIT; if (host->width >= 4) - mmc->host_caps |= MMC_MODE_4BIT; - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; + host->cfg.host_caps |= MMC_MODE_4BIT; + host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; /* * min freq is for card identification, and is the highest @@ -578,10 +579,14 @@ static int do_mmc_init(int dev_index) * max freq is highest HS eMMC clock as per the SD/MMC spec * (actually 52MHz) */ - mmc->f_min = 375000; - mmc->f_max = 48000000; + host->cfg.f_min = 375000; + host->cfg.f_max = 48000000; + + host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc_register(mmc); + mmc = mmc_create(&host->cfg, host); + if (mmc == NULL) + return -1; return 0; } diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index dd6c26a7fb..bd5fba21ce 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -941,11 +941,7 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) { struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv; struct phy_device *phydev; - u32 supported = (SUPPORTED_10baseT_Half | - SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | - SUPPORTED_100baseT_Full | - SUPPORTED_1000baseT_Full); + u32 supported = PHY_GBIT_FEATURES; phydev = phy_connect(priv->bus, slave->data->phy_addr, diff --git a/drivers/net/designware.h b/drivers/net/designware.h index afeaccec19..382b0c7f0a 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -110,7 +110,7 @@ struct dmamacdescr { u32 dmamac_cntl; void *dmamac_addr; struct dmamacdescr *dmamac_next; -} __aligned(16); +} __aligned(ARCH_DMA_MINALIGN); /* * txrx_status definitions diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 1f600aaec4..c48737e6c9 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -451,6 +451,17 @@ static int imx6_pcie_init_phy(void) return 0; } +__weak int imx6_pcie_toggle_power(void) +{ +#ifdef CONFIG_PCIE_IMX_POWER_GPIO + gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); + mdelay(20); + gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); + mdelay(20); +#endif + return 0; +} + __weak int imx6_pcie_toggle_reset(void) { /* @@ -496,7 +507,7 @@ static int imx6_pcie_deassert_core_reset(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - /* FIXME: Power-up GPIO goes here. */ + imx6_pcie_toggle_power(); /* Enable PCIe */ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 0b45ffad67..4129bdabfb 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -9,5 +9,6 @@ obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o +obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c new file mode 100644 index 0000000000..22c1f15eeb --- /dev/null +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> + +int pmic_init(unsigned char bus) +{ + static const char name[] = "PFUZE100_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index a3ad056473..651e46e4bd 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -260,8 +260,9 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp, } /* wait to finish of transfer */ - while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & - OMAP3_MCSPI_CHSTAT_EOT)); + while ((readl(&ds->regs->channel[ds->slave.cs].chstat) & + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) != + (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)); /* Disable the channel otherwise the next immediate RX will get affected */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index a045864d73..de75ff1339 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -164,9 +164,14 @@ static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req) dfu_write(dfu_get_entity(f_dfu->altsetting), req->buf, req->length, f_dfu->blk_seq_num); +} - if (req->length == 0) - puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n"); +static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req) +{ + struct f_dfu *f_dfu = req->context; + + dfu_flush(dfu_get_entity(f_dfu->altsetting), req->buf, + req->length, f_dfu->blk_seq_num); } static void handle_getstatus(struct usb_request *req) @@ -174,19 +179,22 @@ static void handle_getstatus(struct usb_request *req) struct dfu_status *dstat = (struct dfu_status *)req->buf; struct f_dfu *f_dfu = req->context; + dfu_set_poll_timeout(dstat, 0); + switch (f_dfu->dfu_state) { case DFU_STATE_dfuDNLOAD_SYNC: case DFU_STATE_dfuDNBUSY: f_dfu->dfu_state = DFU_STATE_dfuDNLOAD_IDLE; break; case DFU_STATE_dfuMANIFEST_SYNC: + f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; break; + case DFU_STATE_dfuMANIFEST: + dfu_set_poll_timeout(dstat, DFU_MANIFEST_POLL_TIMEOUT); default: break; } - dfu_set_poll_timeout(dstat, 0); - if (f_dfu->poll_timeout) if (!(f_dfu->blk_seq_num % (dfu_get_buf_size() / DFU_USB_BUFSIZ))) @@ -446,10 +454,11 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu, switch (ctrl->bRequest) { case USB_REQ_DFU_GETSTATUS: /* We're MainfestationTolerant */ - f_dfu->dfu_state = DFU_STATE_dfuIDLE; + f_dfu->dfu_state = DFU_STATE_dfuMANIFEST; handle_getstatus(req); f_dfu->blk_seq_num = 0; value = RET_STAT_LEN; + req->complete = dnload_request_flush; break; case USB_REQ_DFU_GETSTATE: handle_getstate(req); @@ -463,6 +472,33 @@ static int state_dfu_manifest_sync(struct f_dfu *f_dfu, return value; } +static int state_dfu_manifest(struct f_dfu *f_dfu, + const struct usb_ctrlrequest *ctrl, + struct usb_gadget *gadget, + struct usb_request *req) +{ + int value = 0; + + switch (ctrl->bRequest) { + case USB_REQ_DFU_GETSTATUS: + /* We're MainfestationTolerant */ + f_dfu->dfu_state = DFU_STATE_dfuIDLE; + handle_getstatus(req); + f_dfu->blk_seq_num = 0; + value = RET_STAT_LEN; + puts("DOWNLOAD ... OK\nCtrl+C to exit ...\n"); + break; + case USB_REQ_DFU_GETSTATE: + handle_getstate(req); + break; + default: + f_dfu->dfu_state = DFU_STATE_dfuERROR; + value = RET_STALL; + break; + } + return value; +} + static int state_dfu_upload_idle(struct f_dfu *f_dfu, const struct usb_ctrlrequest *ctrl, struct usb_gadget *gadget, @@ -539,7 +575,7 @@ static dfu_state_fn dfu_state[] = { state_dfu_dnbusy, /* DFU_STATE_dfuDNBUSY */ state_dfu_dnload_idle, /* DFU_STATE_dfuDNLOAD_IDLE */ state_dfu_manifest_sync, /* DFU_STATE_dfuMANIFEST_SYNC */ - NULL, /* DFU_STATE_dfuMANIFEST */ + state_dfu_manifest, /* DFU_STATE_dfuMANIFEST */ NULL, /* DFU_STATE_dfuMANIFEST_WAIT_RST */ state_dfu_upload_idle, /* DFU_STATE_dfuUPLOAD_IDLE */ state_dfu_error /* DFU_STATE_dfuERROR */ diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 00a0a11ed4..e1e0d802f6 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -104,6 +104,13 @@ void __exynos_backlight_reset(void) void exynos_backlight_reset(void) __attribute__((weak, alias("__exynos_backlight_reset"))); +int __exynos_lcd_misc_init(vidinfo_t *vid) +{ + return 0; +} +int exynos_lcd_misc_init(vidinfo_t *vid) + __attribute__((weak, alias("__exynos_lcd_misc_init"))); + static void lcd_panel_on(vidinfo_t *vid) { udelay(vid->init_delay); @@ -281,10 +288,15 @@ void lcd_ctrl_init(void *lcdbase) #ifdef CONFIG_OF_CONTROL if (exynos_fimd_parse_dt(gd->fdt_blob)) debug("Can't get proper panel info\n"); +#ifdef CONFIG_EXYNOS_MIPI_DSIM + exynos_init_dsim_platform_data(&panel_info); +#endif + exynos_lcd_misc_init(&panel_info); #else /* initialize parameters which is specific to panel. */ init_panel_info(&panel_info); #endif + panel_width = panel_info.vl_width; panel_height = panel_info.vl_height; diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos_mipi_dsi.c index 8bb8feaa9c..7dd4652931 100644 --- a/drivers/video/exynos_mipi_dsi.c +++ b/drivers/video/exynos_mipi_dsi.c @@ -9,6 +9,8 @@ #include <common.h> #include <malloc.h> +#include <fdtdec.h> +#include <libfdt.h> #include <linux/err.h> #include <asm/arch/dsim.h> #include <asm/arch/mipi_dsim.h> @@ -22,7 +24,14 @@ #define master_to_driver(a) (a->dsim_lcd_drv) #define master_to_device(a) (a->dsim_lcd_dev) +DECLARE_GLOBAL_DATA_PTR; + static struct exynos_platform_mipi_dsim *dsim_pd; +#ifdef CONFIG_OF_CONTROL +static struct mipi_dsim_config dsim_config_dt; +static struct exynos_platform_mipi_dsim dsim_platform_data_dt; +static struct mipi_dsim_lcd_device mipi_lcd_device_dt; +#endif struct mipi_dsim_ddi { int bus_id; @@ -238,3 +247,90 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd) dsim_pd = pd; } + +#ifdef CONFIG_OF_CONTROL +int exynos_dsim_config_parse_dt(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI); + if (node <= 0) { + printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n"); + return -ENODEV; + } + + dsim_config_dt.e_interface = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-interface", 0); + + dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-virtual-ch", 0); + + dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-pixel-format", 0); + + dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-burst-mode", 0); + + dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-no-data-lane", 0); + + dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-byte-clk", 0); + + dsim_config_dt.hfp = fdtdec_get_int(blob, node, + "samsung,dsim-config-hfp", 0); + + dsim_config_dt.p = fdtdec_get_int(blob, node, + "samsung,dsim-config-p", 0); + dsim_config_dt.m = fdtdec_get_int(blob, node, + "samsung,dsim-config-m", 0); + dsim_config_dt.s = fdtdec_get_int(blob, node, + "samsung,dsim-config-s", 0); + + dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node, + "samsung,dsim-config-pll-stable-time", 0); + + dsim_config_dt.esc_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-esc-clk", 0); + + dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node, + "samsung,dsim-config-stop-holding-cnt", 0); + + dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-bta-timeout", 0); + + dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-rx-timeout", 0); + + mipi_lcd_device_dt.name = fdtdec_get_config_string(blob, + "samsung,dsim-device-name"); + + mipi_lcd_device_dt.id = fdtdec_get_int(blob, node, + "samsung,dsim-device-id", 0); + + mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node, + "samsung,dsim-device-bus_id", 0); + + mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node, + "samsung,dsim-device-reverse-panel", 0); + + return 0; +} + +void exynos_init_dsim_platform_data(vidinfo_t *vid) +{ + if (exynos_dsim_config_parse_dt(gd->fdt_blob)) + debug("Can't get proper dsim config.\n"); + + strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name); + dsim_platform_data_dt.dsim_config = &dsim_config_dt; + dsim_platform_data_dt.mipi_power = mipi_power; + dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl; + dsim_platform_data_dt.lcd_panel_info = (void *)vid; + + mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt; + exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt); + + dsim_pd = &dsim_platform_data_dt; +} +#endif diff --git a/dts/Makefile b/dts/Makefile index 9907463fc6..e59550c9d2 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -44,4 +44,4 @@ dtbs: $(obj)/dt.dtb clean-files := dt.dtb.S # Let clean descend into dts directories -subdir- += ../arch/*/dts +subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/sandbox/dts ../arch/x86/dts diff --git a/include/common.h b/include/common.h index 5c9bd08f45..cbd3c9e043 100644 --- a/include/common.h +++ b/include/common.h @@ -822,8 +822,7 @@ void udelay (unsigned long); void mdelay(unsigned long); /* lib/uuid.c */ -void uuid_str_to_bin(const char *uuid, unsigned char *out); -int uuid_str_valid(const char *uuid); +#include <uuid.h> /* lib/vsprintf.c */ #include <vsprintf.h> @@ -835,9 +834,7 @@ char * strmhz(char *buf, unsigned long hz); #include <u-boot/crc.h> /* lib/rand.c */ -#if defined(CONFIG_RANDOM_MACADDR) || \ - defined(CONFIG_BOOTP_RANDOM_DELAY) || \ - defined(CONFIG_CMD_LINK_LOCAL) +#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND) #define RAND_MAX -1U void srand(unsigned int seed); unsigned int rand(void); diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index d8339b26cc..e6fb47be0b 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -55,6 +55,22 @@ #define HAVE_BLOCK_DEVICE #endif +#if (defined(CONFIG_PARTITION_UUIDS) || \ + defined(CONFIG_EFI_PARTITION) || \ + defined(CONFIG_RANDOM_UUID) || \ + defined(CONFIG_CMD_UUID) || \ + defined(CONFIG_BOOTP_PXE)) && \ + !defined(CONFIG_LIB_UUID) +#define CONFIG_LIB_UUID +#endif + +#if (defined(CONFIG_RANDOM_UUID) || \ + defined(CONFIG_CMD_UUID)) && \ + (!defined(CONFIG_LIB_RAND) && \ + !defined(CONFIG_LIB_HW_RAND)) +#define CONFIG_LIB_RAND +#endif + #ifndef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "=> " #endif diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h index 930699ba6d..19ea3167af 100644 --- a/include/configs/MERGERBOX.h +++ b/include/configs/MERGERBOX.h @@ -312,6 +312,7 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_RANDOM_DELAY #define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_LIB_RAND /* * Command line configuration. diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 99e4e9051f..036396c781 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -104,6 +104,7 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_RANDOM_DELAY #define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_LIB_RAND /* * Autoboot diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 30af691c5a..27c2fa011d 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -227,6 +227,7 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_RANDOM_DELAY #define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_LIB_RAND /* USB */ #define CONFIG_SYS_USB_HOST diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h index bb565b602e..ad15506fad 100644 --- a/include/configs/MVSMR.h +++ b/include/configs/MVSMR.h @@ -92,6 +92,7 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTP_VENDOREX +#define CONFIG_LIB_RAND /* * Autoboot diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index 1e65cd1465..205adfd8ce 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -58,6 +58,7 @@ #define CONFIG_BOOTP_SERVERIP #define CONFIG_NET_RETRY_COUNT 3 #define CONFIG_CMD_LINK_LOCAL +#define CONFIG_LIB_RAND #define CONFIG_NETCONSOLE #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_CMD_PING diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 2020e7f814..ea9e758a69 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -208,9 +208,6 @@ #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_BOOTCOUNT_AM33XX -/* CPSW support */ -#define CONFIG_SPL_ETH_SUPPORT - /* USB gadget RNDIS */ #define CONFIG_SPL_MUSB_NEW_SUPPORT @@ -442,6 +439,8 @@ #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reduce SPL size by removing unlikey targets */ +#undef CONFIG_SPL_SPI_SUPPORT #ifdef CONFIG_NOR_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 08ccce0b9a..ea9acf69d1 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -17,6 +17,7 @@ # define CONFIG_BOOTP_DNS # define CONFIG_BOOTP_NTPSERVER # define CONFIG_BOOTP_RANDOM_DELAY +# define CONFIG_LIB_RAND # define CONFIG_KEEP_SERVERADDR # define CONFIG_CMD_DNS # define CONFIG_CMD_PING diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 7bbe5964ae..7adc8c0fd7 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -22,7 +22,7 @@ /* Timer information */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ - +#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */ #define CONFIG_SPL_POWER_SUPPORT #define CONFIG_POWER_TPS65217 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index cfc4f9bb8e..aae05e0333 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -158,6 +158,8 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define GPMC_NAND_ECC_LP_x8_LAYOUT + /* Environment information */ #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h new file mode 100644 index 0000000000..2040bf7784 --- /dev/null +++ b/include/configs/exynos4-dt.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ +#define CONFIG_S5P /* S5P Family */ +#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_COMMON + +/* Enable fdt support */ +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +#include <linux/sizes.h> + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_S5P_SDHCI +#define CONFIG_SDHCI +#define CONFIG_MMC_SDMA +#define CONFIG_MMC_DEFAULT_DEV 0 + +/* PWM */ +#define CONFIG_PWM + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_ONENAND +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT +#define CONFIG_CMD_PMIC +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* FAT */ +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE + +/* EXT4 */ +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_MANUFACTURER "Samsung" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USB_CABLE_CHECK + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +/* Enable devicetree support */ +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h new file mode 100644 index 0000000000..33983907f2 --- /dev/null +++ b/include/configs/gw_ventana.h @@ -0,0 +1,425 @@ +/* + * Copyright (C) 2013 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO /* display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO_LATE /* display board info (after reloc) */ + +#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> + +/* ATAGs */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SERIAL_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* Init Functions */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +/* GPIO */ +#define CONFIG_MXC_GPIO + +/* Serial */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +#ifdef CONFIG_SPI_FLASH + +/* SPI */ +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF + #define CONFIG_MXC_SPI + #define CONFIG_SPI_FLASH_MTD + #define CONFIG_SPI_FLASH_BAR + #define CONFIG_SPI_FLASH_WINBOND + #define CONFIG_SF_DEFAULT_BUS 0 + #define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8)) + /* GPIO 3-19 (21248) */ + #define CONFIG_SF_DEFAULT_SPEED 30000000 + #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + +#else +/* Enable NAND support */ +#define CONFIG_CMD_TIME +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_MXS + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_NAND_5_ADDR_CYCLE + #define CONFIG_SYS_NAND_ONFI_DETECTION + + /* DMA stuff, needed for GPMI/MXS NAND support */ + #define CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_BURST + #define CONFIG_APBH_DMA_BURST8 +#endif + +#endif /* CONFIG_SPI_FLASH */ + +/* Flattened Image Tree Suport */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +/* Filesystem support */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_UBIFS +#define CONFIG_DOS_PARTITION + +/* Network config - Allow larger/faster download for TFTP/NFS */ +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 +#define CONFIG_NFS_READ_SIZE 4096 + +/* + * SATA Configs + */ +#define CONFIG_CMD_SATA +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + +/* + * PCI express + */ +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#endif + +/* + * PMIC + */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* Various command support */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */ +#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GSC +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_FUSE /* eFUSE read/write support */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + + +/* Ethernet support */ +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_ARP_TIMEOUT 200UL + +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_CDC +#define CONFIG_NETCONSOLE +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200 + +/* serial console (ttymxc1,115200) */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Ventana > " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_HWCONFIG + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Memory configuration */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH /* no NOR flash */ + +/* + * MTD Command for mtdparts + */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#ifdef CONFIG_SPI_FLASH +#define MTDIDS_DEFAULT "nor0=nor" +#define MTDPARTS_DEFAULT \ + "mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)" +#else +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" +#endif + +/* Persistent Environment Config */ +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#else +#define CONFIG_ENV_IS_IN_NAND +#endif +#if defined(CONFIG_ENV_IS_IN_MMC) + #define CONFIG_ENV_OFFSET (6 * 64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_NAND) + #define CONFIG_ENV_OFFSET (16 << 20) + #define CONFIG_ENV_SECT_SIZE (128 << 10) + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE (64 * 1024) + #define CONFIG_ENV_SIZE (8 * 1024) + #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS + #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS + #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE + #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* Environment */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.146 +#define HWCONFIG_DEFAULT \ + "hwconfig=rs232;" \ + "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "console=ttymxc1\0" \ + "bootdevs=usb mmc sata flash\0" \ + HWCONFIG_DEFAULT \ + "video=\0" \ + \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x18000000\0" \ + "loadfdt=" \ + "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ + "echo Loaded DTB from boot/${fdt_file}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \ + "echo Loaded DTB from boot/${fdt_file1}; " \ + "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \ + "echo Loaded DTB from boot/${fdt_file2}; " \ + "fi\0" \ + \ + "script=boot/6x_bootscript-ventana\0" \ + "loadscript=" \ + "if ${fsload} ${loadaddr} ${script}; then " \ + "source; " \ + "fi\0" \ + \ + "uimage=boot/uImage\0" \ + "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \ + "mmc_boot=" \ + "setenv fsload 'ext2load mmc 0:1'; " \ + "mmc dev 0 && mmc rescan && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mmcblk0p1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + \ + "sata_boot=" \ + "setenv fsload 'ext2load sata 0:1'; sata init && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" \ + "usb_boot=" \ + "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/sda1 rootfstype=ext4 " \ + "rootwait rw ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "bootm; " \ + "fi; " \ + "fi\0" + +#ifdef CONFIG_SPI_FLASH + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ + "image_uboot=ventana/u-boot_spi.imx\0" \ + \ + "spi_koffset=0x90000\0" \ + "spi_klen=0x200000\0" \ + \ + "spi_updateuboot=echo Updating uboot from " \ + "${serverip}:${image_uboot}...; " \ + "tftpboot ${loadaddr} ${image_uboot} && " \ + "sf probe && sf erase 0 80000 && " \ + "sf write ${loadaddr} 400 ${filesize}\0" \ + "spi_update=echo Updating OS from ${serverip}:${image_os} " \ + "to ${spi_koffset} ...; " \ + "tftp ${loadaddr} ${image_os} && " \ + "sf probe && " \ + "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ + \ + "flash_boot=" \ + "if sf probe && " \ + "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=/dev/mtdblock3 " \ + "rootfstype=squashfs,jffs2 " \ + "${video} ${extra}; " \ + "bootm; " \ + "fi\0" +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ + \ + "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ + "tftp ${loadaddr} ${image_rootfs} && " \ + "nand erase.part rootfs && " \ + "nand write ${loadaddr} rootfs ${filesize}\0" \ + \ + "flash_boot=" \ + "setenv fsload 'ubifsload'; " \ + "ubi part rootfs && ubifsmount ubi0:rootfs; " \ + "run loadscript; " \ + "if ${fsload} ${loadaddr} ${uimage}; then " \ + "setenv bootargs console=${console},${baudrate} " \ + "root=ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=ubifs ${video} ${extra}; " \ + "if run loadfdt && fdt addr ${fdt_addr}; then " \ + "ubifsumount; " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "ubifsumount; bootm; " \ + "fi; " \ + "fi\0" +#endif + +#define CONFIG_BOOTCOMMAND \ + "for btype in ${bootdevs}; do " \ + "echo; echo Attempting ${btype} boot...; " \ + "if run ${btype}_boot; then; fi; " \ + "done" + +/* Device Tree Support */ +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_LIBFDT +#define CONFIG_FDT_FIXUP_PARTITIONS + +#ifndef CONFIG_SYS_DCACHE_OFF + #define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 4d11c7d08c..5a13ad1139 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -15,6 +15,7 @@ #define CONFIG_KZM_A9_GT #define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G +#define CONFIG_SYS_GENERIC_BOARD #include <asm/arch/rmobile.h> diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 2ae8a2700d..96a889fe87 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -37,6 +37,7 @@ #define CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_RANDOM_MACADDR +#define CONFIG_LIB_RAND #define CONFIG_KIRKWOOD_GPIO #define CONFIG_OF_LIBFDT diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 16546c28b4..f401470251 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -46,13 +46,13 @@ */ #define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) #define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0xaff00000 +#define CONFIG_SYS_MEMTEST_END 0x8ff00000 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index af6aafaf1c..aff2419f85 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -62,6 +62,7 @@ /* No NOR flash present */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_MMC @@ -69,7 +70,7 @@ /* U-Boot general configuration */ #define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ /* Print buffer sz */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -132,12 +133,104 @@ #define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_DEFAULT_FDT_FILE "imx25-pdk.dtb" + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x82000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd=run netargs; dhcp ${uimage}; bootm\0" \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #endif /* __CONFIG_H */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 1415584463..5859f360e0 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -194,11 +194,11 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index eb107d312a..8a8920f6cc 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -20,6 +20,8 @@ #define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 +#define CONFIG_ARM_ERRATA_794072 +#define CONFIG_ARM_ERRATA_761320 #define CONFIG_BOARD_POSTCLK_INIT #ifndef CONFIG_SYS_L2CACHE_OFF diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index dbbb6f0311..bd0144f5cb 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -41,4 +41,7 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_OF_SEPARATE +#define CONFIG_DEFAULT_DEVICE_TREE imx6q-sabreauto + #endif /* __MX6QSABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 4919f53328..5d02d23ec7 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -48,4 +48,14 @@ #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_IMX_HDMI +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) +#endif + #endif /* __MX6QSABRESD_CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 55ecef92a9..ba55177e72 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -80,8 +80,16 @@ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot * binary. In case there was more of this mess, 0x100 bytes are skipped. + * + * In case of a HAB boot, we cannot for some weird reason use the first 4KiB + * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST + * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. + * + * As for the SPL, we must avoid the first 4 KiB as well, but we load the + * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +#define CONFIG_SYS_TEXT_BASE 0x40002000 +#define CONFIG_SPL_TEXT_BASE 0x00001000 /* U-Boot general configuration */ #define CONFIG_SYS_LONGHELP @@ -174,6 +182,11 @@ #define CONFIG_SYS_NAND_5_ADDR_CYCLE #endif +/* OCOTP */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXS_OCOTP +#endif + /* SPI */ #ifdef CONFIG_CMD_SPI #define CONFIG_HARD_SPI diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f2db8c515b..f7e7315a9b 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -356,7 +356,6 @@ /* * PCI express */ -#define CONFIG_CMD_PCI #ifdef CONFIG_CMD_PCI #define CONFIG_PCI #define CONFIG_PCI_PNP diff --git a/include/configs/origen.h b/include/configs/origen.h index f46b833b53..82583382f7 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -6,115 +6,71 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_ORIGEN_H +#define __CONFIG_ORIGEN_H + +#include <configs/exynos4-dt.h> + +#define CONFIG_SYS_PROMPT "ORIGEN # " + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-origen /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ -#include <asm/arch/cpu.h> /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - #define CONFIG_SYS_DCACHE_OFF 1 +/* ORIGEN has 4 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* input clock of PLL: ORIGEN has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_TEXT_BASE 0x43E00000 #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ -#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ +#define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 -#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000 -#define CONFIG_SKIP_LOWLEVEL_INIT +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ -/* PWM */ -#define CONFIG_PWM 1 +#define CONFIG_SYS_MONITOR_BASE 0x00000000 -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include <config_cmd_default.h> +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 #undef CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* MMC SPL */ #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 - #define CONFIG_SPL_TEXT_BASE 0x02021410 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "ORIGEN # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -/* ORIGEN has 4 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 4 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for ORIGEN" #define CONFIG_CLK_1000_400_200 @@ -122,13 +78,12 @@ /* MIU (Memory Interleaving Unit) */ #define CONFIG_MIU_2BIT_21_7_INTERLEAVED -#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -140,7 +95,4 @@ #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 67921e900b..2da887109d 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -7,78 +7,56 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_UNIVERSAL_H +#define __CONFIG_UNIVERSAL_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */ -#define CONFIG_UNIVERSAL 1 /* working with Universal */ -#define CONFIG_TIZEN 1 /* TIZEN lib */ +#include <configs/exynos4-dt.h> + +#define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */ -#include <asm/arch/cpu.h> /* get chip and board defs */ +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-universal_c210 -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TIZEN /* TIZEN lib */ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_L2CACHE_OFF 1 +/* Universal has 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x44800000 - -/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ -#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ -#define CONFIG_BAUDRATE 115200 - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH 1 - -/* Command definition */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_ONENAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT - -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + +#define CONFIG_SYS_TEXT_BASE 0x44800000 #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS @@ -106,24 +84,21 @@ ",100M(swap)"\ ",-(UMS)\0" -#define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - #define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" #define CONFIG_BOOTBLOCK "10" #define CONFIG_UBIBLOCK "9" +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + #define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " #define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ "${mtdparts}" #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -187,47 +162,10 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "Universal # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -/* Universal has 2 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #define CONFIG_USE_ONENAND_BOARD_INIT #define CONFIG_SAMSUNG_ONENAND #define CONFIG_SYS_ONENAND_BASE 0x0C000000 -#define CONFIG_ENV_IS_IN_MMC 1 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */ - -#define CONFIG_DOS_PARTITION 1 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include <asm/arch/gpio.h> /* * I2C Settings @@ -235,6 +173,8 @@ #define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) #define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) +#define CONFIG_CMD_I2C + #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ #define CONFIG_SYS_I2C_SOFT_SPEED 50000 @@ -307,8 +247,10 @@ int universal_spi_read(void); #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP #define CONFIG_LD9040 -#define CONFIG_EXYNOS_MIPI_DSIM #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) +#define LCD_XRES 480 +#define LCD_YRES 800 + #endif /* __CONFIG_H */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 0a694fb1be..b5064ab37c 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -457,6 +457,7 @@ #endif /* CONFIG_BOOT_ROOT_NFS */ #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ +#define CONFIG_LIB_RAND /* * BOOTP options diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 04171bdfd6..fa62cb6cd5 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -169,4 +169,6 @@ #define CONFIG_TPM_TIS_SANDBOX +#define CONFIG_CMD_LZMADEC + #endif diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 98b6e7206d..721c4e6bad 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -265,6 +265,7 @@ #define CONFIG_DFU_NAND #define CONFIG_CMD_DFU #define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) +#define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 608578ad2c..0254249751 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/pll_config.h" /* * High level configuration diff --git a/include/configs/trats.h b/include/configs/trats.h index 7cea2592ff..5d8bd60583 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -7,25 +7,19 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_TRATS_H +#define __CONFIG_TRATS_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* which is in a S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */ -#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */ -#define CONFIG_TRATS /* working with TRATS */ -#define CONFIG_TIZEN /* TIZEN lib */ +#include <configs/exynos4-dt.h> + +#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */ + +#define CONFIG_TRATS -#include <asm/arch/cpu.h> /* get chip and board defs */ +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-trats -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_TIZEN /* TIZEN lib */ #define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF @@ -33,130 +27,93 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif +/* TRATS has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_TEXT_BASE 0x63300000 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) -/* MACH_TYPE_TRATS macro will be removed once added to mach-types */ -#define MACH_TYPE_TRATS 3928 -#define CONFIG_MACH_TYPE MACH_TYPE_TRATS +#define CONFIG_SYS_TEXT_BASE 0x63300000 #include <linux/sizes.h> /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ -#define CONFIG_SERIAL2 /* use SERIAL 2 */ +#define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI -#define CONFIG_MMC_SDMA - -/* PWM */ -#define CONFIG_PWM - -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH - -/* Command definition */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE -#undef CONFIG_CMD_ONENAND -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_SETEXPR - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET - -/* TIZEN THOR downloader support */ -#define CONFIG_CMD_THOR_DOWNLOAD -#define CONFIG_THOR_FUNCTION - -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_MANUFACTURER "Samsung" - -#define CONFIG_BOOTDELAY 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* MACH_TYPE_TRATS macro will be removed once added to mach-types */ +#define MACH_TYPE_TRATS 3928 +#define CONFIG_MACH_TYPE MACH_TYPE_TRATS + #define CONFIG_BOOTARGS "Please use defined boot" #define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_BOOTBLOCK "10" #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" -#define PARTS_BOOTLOADER "u-boot" #define PARTS_BOOT "boot" +#define PARTS_QBOOT "qboot" +#define PARTS_CSC "csc" #define PARTS_ROOT "platform" #define PARTS_DATA "data" -#define PARTS_CSC "csc" #define PARTS_UMS "ums" #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ - "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOTLOADER",size=60MiB," \ - "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ - "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ + "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ #define CONFIG_DFU_ALT \ "u-boot mmc 80 400;" \ "uImage ext4 0 2;" \ + "modem.bin ext4 0 2;" \ "exynos4210-trats.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ "params.bin mmc 0x38 0x8\0" -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ "run loaduimage;" \ @@ -226,59 +183,17 @@ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "TRATS # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -/* TRATS has 4 banks of DRAM */ -#define CONFIG_NR_DRAM_BANKS 4 -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE /* Falcon mode definitions */ #define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100 +#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 /* GPT */ -#define CONFIG_EFI_PARTITION -#define CONFIG_PARTITION_UUIDS +#define CONFIG_RANDOM_UUID + +/* I2C */ +#include <asm/arch/gpio.h> -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_S3C24X0 @@ -291,12 +206,11 @@ #define CONFIG_SOFT_I2C_READ_REPEATED_START #define CONFIG_SYS_I2C_INIT_BOARD -#include <asm/arch/gpio.h> - /* I2C FG */ #define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) #define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) +/* POWER */ #define CONFIG_POWER #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX8997 @@ -307,11 +221,10 @@ #define CONFIG_POWER_MUIC_MAX8997 #define CONFIG_POWER_BATTERY #define CONFIG_POWER_BATTERY_TRATS -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 -#define CONFIG_USB_CABLE_CHECK + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -351,10 +264,7 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_GADGET_MASS_STORAGE - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 +#define LCD_XRES 720 +#define LCD_YRES 1280 #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 6d389df9df..53d449c291 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -8,27 +8,17 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_TRATS2_H +#define __CONFIG_TRATS2_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* which is in a S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */ -#define CONFIG_TIZEN /* TIZEN lib */ +#include <configs/exynos4-dt.h> -#include <asm/arch/cpu.h> /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ -#define CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2 -#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_TIZEN /* TIZEN lib */ #define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF @@ -36,33 +26,17 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif -#define CONFIG_NR_DRAM_BANKS 4 -#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */ -#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */ -#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */ -#define PHYS_SDRAM_END 0x80000000 - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_TEXT_BASE 0x78100000 - -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG - -/* MACH_TYPE_TRATS2 */ -#define MACH_TYPE_TRATS2 3765 -#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2 +/* TRATS2 has 4 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) -#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_SYS_TEXT_BASE 0x43e00000 #include <linux/sizes.h> /* Size of malloc() pool */ @@ -70,95 +44,37 @@ /* select serial console configuration */ #define CONFIG_SERIAL2 +#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_CMDLINE_EDITING +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" -#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) -/* It should define before config_cmd_default.h */ -#define CONFIG_SYS_NO_FLASH - -/*********************************************************** - * Command definition - ***********************************************************/ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_ECHO -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NAND -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_XIMG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_PMIC - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_EXT4_WRITE - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC - -/* TIZEN THOR downloader support */ -#define CONFIG_CMD_THOR_DOWNLOAD -#define CONFIG_THOR_FUNCTION - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_MANUFACTURER "Samsung" - -/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */ -#undef CONFIG_CMD_NET - -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_S5P_SDHCI -#define CONFIG_SDHCI -#define CONFIG_MMC_SDMA -#define CONFIG_MMC_DEFAULT_DEV 0 - -/* PWM */ -#define CONFIG_PWM - -#define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* Tizen - partitions definitions */ -#define PARTS_CSA "csa" +#define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" -#define PARTS_MODEM "modem" +#define PARTS_QBOOT "qboot" #define PARTS_CSC "csc" #define PARTS_ROOT "platform" #define PARTS_DATA "data" @@ -167,18 +83,22 @@ #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \ + "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ + "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ + "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ #define CONFIG_DFU_ALT \ "u-boot mmc 80 800;" \ "uImage ext4 0 2;" \ + "modem.bin ext4 0 2;" \ "exynos4412-trats2.dtb ext4 0 2;" \ + ""PARTS_CSA" part 0 1;" \ ""PARTS_BOOT" part 0 2;" \ + ""PARTS_QBOOT" part 0 3;" \ + ""PARTS_CSC" part 0 4;" \ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ @@ -246,49 +166,14 @@ "setenv spl_addr_tmp;\0" \ "fdtaddr=40800000\0" \ -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - -/* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ -#define CONFIG_EFI_PARTITION -#define CONFIG_PARTITION_UUIDS - -#define CONFIG_BOARD_EARLY_INIT_F +/* GPT */ +#define CONFIG_RANDOM_UUID /* I2C */ #include <asm/arch/gpio.h> +#define CONFIG_CMD_I2C + #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 @@ -318,11 +203,10 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_POWER_MUIC_MAX77693 #define CONFIG_POWER_FG_MAX77693 #define CONFIG_POWER_BATTERY_TRATS2 -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 -#define CONFIG_USB_CABLE_CHECK + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND /* Common misc for Samsung */ #define CONFIG_MISC_COMMON @@ -362,10 +246,7 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_GADGET_MASS_STORAGE - -/* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 +#define LCD_XRES 720 +#define LCD_YRES 1280 #endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 62f97d24fb..80985a2655 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -63,6 +63,9 @@ /* GPIO support */ #define CONFIG_OMAP_GPIO +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ + /* LED support */ #define CONFIG_STATUS_LED #define CONFIG_BOARD_SPECIFIC_LED @@ -365,11 +368,12 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\ - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ - 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\ - 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\ - 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ + 33, 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 44, 45, 46, 47, 48, 49, 50, 51, \ + 52, 53, 54, 55, 56} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index e8517027e7..dff6adcc7c 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -12,6 +12,8 @@ #define CONFIG_REMAKE_ELF +#define CONFIG_GICV3 + /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ /*#define CONFIG_SYS_GENERIC_BOARD*/ @@ -93,8 +95,13 @@ #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ /* Generic Interrupt Controller Definitions */ +#ifdef CONFIG_GICV3 +#define GICD_BASE (0x2f000000) +#define GICR_BASE (0x2f100000) +#else #define GICD_BASE (0x2C001000) #define GICC_BASE (0x2C002000) +#endif #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h index 10e1d170ba..437472f3ed 100644 --- a/include/configs/woodburn_sd.h +++ b/include/configs/woodburn_sd.h @@ -17,8 +17,6 @@ /* Set TEXT in RAM */ #define CONFIG_SYS_TEXT_BASE 0x82000000 -#define CONFIG_BOOT_INTERNAL - /* * SPL */ diff --git a/include/dfu.h b/include/dfu.h index f973426aa9..6c71ecbe35 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -80,6 +80,9 @@ static inline unsigned int get_mmc_blk_size(int dev) #ifndef DFU_DEFAULT_POLL_TIMEOUT #define DFU_DEFAULT_POLL_TIMEOUT 0 #endif +#ifndef DFU_MANIFEST_POLL_TIMEOUT +#define DFU_MANIFEST_POLL_TIMEOUT DFU_DEFAULT_POLL_TIMEOUT +#endif struct dfu_entity { char name[DFU_NAME_SIZE]; @@ -138,6 +141,7 @@ unsigned long dfu_get_buf_size(void); int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num); int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num); +int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num); /* Device specific */ #ifdef CONFIG_DFU_MMC extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s); diff --git a/include/dwmmc.h b/include/dwmmc.h index b64155851d..c9bdf51a67 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -143,6 +143,8 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); unsigned int (*get_mmc_clk)(struct dwmci_host *host); + + struct mmc_config cfg; }; struct dwmci_idmac { diff --git a/include/fdtdec.h b/include/fdtdec.h index 6e859ce64c..3196cf6683 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -79,8 +79,10 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ + COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */ + COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89bcbd1700..a6e3a5dc9a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -13,6 +13,9 @@ #include <asm/errno.h> #include <asm/byteorder.h> +/* needed for the mmc_cfg definition */ +#include <mmc.h> + /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 @@ -155,6 +158,7 @@ struct fsl_esdhc_cfg { u32 esdhc_base; u32 sdhc_clk; u8 max_bus_width; + struct mmc_config cfg; }; /* Select the correct accessors depending on endianess */ diff --git a/include/linux/fb.h b/include/linux/fb.h index 111372c9fd..652cf3bab7 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -612,6 +612,8 @@ struct fb_videomode { u32 flag; }; +int board_video_skip(void); + #endif /* __KERNEL__ */ #endif /* _LINUX_FB_H */ diff --git a/include/mmc.h b/include/mmc.h index e95a2376d2..42d01251b5 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -150,6 +150,7 @@ #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ #define EXT_CSD_RPMB_MULT 168 /* RO */ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ #define EXT_CSD_BOOT_BUS_WIDTH 177 @@ -250,20 +251,40 @@ struct mmc_data { uint blocksize; }; +/* forward decl. */ +struct mmc; + +struct mmc_ops { + int (*send_cmd)(struct mmc *mmc, + struct mmc_cmd *cmd, struct mmc_data *data); + void (*set_ios)(struct mmc *mmc); + int (*init)(struct mmc *mmc); + int (*getcd)(struct mmc *mmc); + int (*getwp)(struct mmc *mmc); +}; + +struct mmc_config { + const char *name; + const struct mmc_ops *ops; + uint host_caps; + uint voltages; + uint f_min; + uint f_max; + uint b_max; + unsigned char part_type; +}; + +/* TODO struct mmc should be in mmc_private but it's hard to fix right now */ struct mmc { struct list_head link; - char name[32]; - void *priv; - uint voltages; + const struct mmc_config *cfg; /* provided configuration */ uint version; + void *priv; uint has_init; - uint f_min; - uint f_max; int high_capacity; uint bus_width; uint clock; uint card_caps; - uint host_caps; uint ocr; uint dsr; uint dsr_imp; @@ -283,13 +304,6 @@ struct mmc { u64 capacity_rpmb; u64 capacity_gp[4]; block_dev_desc_t block_dev; - int (*send_cmd)(struct mmc *mmc, - struct mmc_cmd *cmd, struct mmc_data *data); - void (*set_ios)(struct mmc *mmc); - int (*init)(struct mmc *mmc); - int (*getcd)(struct mmc *mmc); - int (*getwp)(struct mmc *mmc); - uint b_max; char op_cond_pending; /* 1 if we are waiting on an op_cond command */ char init_in_progress; /* 1 if we have done mmc_start_init() */ char preinit; /* start init as early as possible */ @@ -297,6 +311,8 @@ struct mmc { }; int mmc_register(struct mmc *mmc); +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); +void mmc_destroy(struct mmc *mmc); int mmc_initialize(bd_t *bis); int mmc_init(struct mmc *mmc); int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); @@ -317,6 +333,8 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); +/* Function to modify the RST_n_FUNCTION field of EXT_CSD */ +int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); /** * Start device initialization and return immediately; it does not block on @@ -345,7 +363,7 @@ void mmc_set_preinit(struct mmc *mmc, int preinit); #ifdef CONFIG_GENERIC_MMC #ifdef CONFIG_MMC_SPI -#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI) +#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) #else #define mmc_host_is_spi(mmc) 0 #endif @@ -354,4 +372,11 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); int mmc_legacy_init(int verbose); #endif +int board_mmc_init(bd_t *bis); + +/* Set block count limit because of 16 bit register limit on some hardware*/ +#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 +#endif + #endif /* _MMC_H_ */ diff --git a/include/phy.h b/include/phy.h index 1f22fa180c..d3ecd6378b 100644 --- a/include/phy.h +++ b/include/phy.h @@ -234,6 +234,8 @@ int phy_smsc_init(void); int phy_teranetics_init(void); int phy_vitesse_init(void); +int board_phy_config(struct phy_device *phydev); + /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_TN2020 0x00a19410 diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h new file mode 100644 index 0000000000..2a9032a1f9 --- /dev/null +++ b/include/power/pfuze100_pmic.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey <tharvey@gateworks.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PFUZE100_PMIC_H_ +#define __PFUZE100_PMIC_H_ + +/* PFUZE100 registers */ +enum { + PFUZE100_DEVICEID = 0x00, + PFUZE100_REVID = 0x03, + PFUZE100_FABID = 0x04, + + PFUZE100_SW1ABVOL = 0x20, + PFUZE100_SW1CVOL = 0x2e, + PFUZE100_SW2VOL = 0x35, + PFUZE100_SW3AVOL = 0x3c, + PFUZE100_SW3BVOL = 0x43, + PFUZE100_SW4VOL = 0x4a, + PFUZE100_SWBSTCON1 = 0x66, + PFUZE100_VREFDDRCON = 0x6a, + PFUZE100_VSNVSVOL = 0x6b, + PFUZE100_VGEN1VOL = 0x6c, + PFUZE100_VGEN2VOL = 0x6d, + PFUZE100_VGEN3VOL = 0x6e, + PFUZE100_VGEN4VOL = 0x6f, + PFUZE100_VGEN5VOL = 0x70, + PFUZE100_VGEN6VOL = 0x71, + + PMIC_NUM_OF_REGS = 0x7f, +}; + +/* + * LDO Configuration + */ + +/* VGEN1/2 Voltage Configuration */ +#define LDOA_0_80V 0 +#define LDOA_0_85V 1 +#define LDOA_0_90V 2 +#define LDOA_0_95V 3 +#define LDOA_1_00V 4 +#define LDOA_1_05V 5 +#define LDOA_1_10V 6 +#define LDOA_1_15V 7 +#define LDOA_1_20V 8 +#define LDOA_1_25V 9 +#define LDOA_1_30V 10 +#define LDOA_1_35V 11 +#define LDOA_1_40V 12 +#define LDOA_1_45V 13 +#define LDOA_1_50V 14 +#define LDOA_1_55V 15 + +/* VGEN3/4/5/6 Voltage Configuration */ +#define LDOB_1_80V 0 +#define LDOB_1_90V 1 +#define LDOB_2_00V 2 +#define LDOB_2_10V 3 +#define LDOB_2_20V 4 +#define LDOB_2_30V 5 +#define LDOB_2_40V 6 +#define LDOB_2_50V 7 +#define LDOB_2_60V 8 +#define LDOB_2_70V 9 +#define LDOB_2_80V 10 +#define LDOB_2_90V 11 +#define LDOB_3_00V 12 +#define LDOB_3_10V 13 +#define LDOB_3_20V 14 +#define LDOB_3_30V 15 + +#define LDO_VOL_MASK 0xf +#define LDO_EN 4 + +/* + * Boost Regulator + */ + +/* SWBST Output Voltage */ +#define SWBST_5_00V 0 +#define SWBST_5_05V 1 +#define SWBST_5_10V 2 +#define SWBST_5_15V 3 + +#define SWBST_VOL_MASK 0x3 +#define SWBST_MODE_MASK 0x6 +#define SWBST_MODE_OFF (2 << 0) +#define SWBST_MODE_PFM (2 << 1) +#define SWBST_MODE_AUTO (2 << 2) +#define SWBST_MODE_APS (2 << 3) + +#endif diff --git a/include/sdhci.h b/include/sdhci.h index 74d06ae18a..aa4a0e9654 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -12,6 +12,7 @@ #include <asm/io.h> #include <mmc.h> +#include <fdtdec.h> /* * Controller registers @@ -244,9 +245,15 @@ struct sdhci_host { const struct sdhci_ops *ops; int index; + int bus_width; + struct fdt_gpio_state pwr_gpio; /* Power GPIO */ + struct fdt_gpio_state cd_gpio; /* Card Detect GPIO */ + void (*set_control_reg)(struct sdhci_host *host); void (*set_clock)(int dev_index, unsigned int div); uint voltages; + + struct mmc_config cfg; }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS diff --git a/include/uuid.h b/include/uuid.h new file mode 100644 index 0000000000..93027c1b28 --- /dev/null +++ b/include/uuid.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __UUID_H__ +#define __UUID_H__ + +/* This is structure is in big-endian */ +struct uuid { + unsigned int time_low; + unsigned short time_mid; + unsigned short time_hi_and_version; + unsigned char clock_seq_hi_and_reserved; + unsigned char clock_seq_low; + unsigned char node[6]; +} __packed; + +enum { + UUID_STR_FORMAT_STD, + UUID_STR_FORMAT_GUID +}; + +#define UUID_STR_LEN 36 +#define UUID_BIN_LEN sizeof(struct uuid) + +#define UUID_VERSION_MASK 0xf000 +#define UUID_VERSION_SHIFT 12 +#define UUID_VERSION 0x4 + +#define UUID_VARIANT_MASK 0xc0 +#define UUID_VARIANT_SHIFT 7 +#define UUID_VARIANT 0x1 + +int uuid_str_valid(const char *uuid); +int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format); +void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format); +void gen_rand_uuid(unsigned char *uuid_bin); +void gen_rand_uuid_str(char *uuid_str, int str_format); +#endif diff --git a/lib/Makefile b/lib/Makefile index 8814ff9671..27e4f78bfd 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -60,10 +60,8 @@ obj-$(CONFIG_REGEX) += slre.o obj-y += string.o obj-y += time.o obj-$(CONFIG_TRACE) += trace.o -obj-$(CONFIG_BOOTP_PXE) += uuid.o +obj-$(CONFIG_LIB_UUID) += uuid.o obj-y += vsprintf.o -obj-$(CONFIG_RANDOM_MACADDR) += rand.o -obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o -obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o +obj-$(CONFIG_LIB_RAND) += rand.o subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2 diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 8da2d74041..8ecb80f162 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -53,8 +53,10 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"), COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"), + COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"), COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"), COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"), + COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"), COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), COMPAT(GENERIC_SPI_FLASH, "spi-flash"), diff --git a/lib/tizen/tizen_logo_16bpp.h b/lib/tizen/tizen_logo_16bpp.h index 9a0b6fa354..0057c11f0b 100644 --- a/lib/tizen/tizen_logo_16bpp.h +++ b/lib/tizen/tizen_logo_16bpp.h @@ -8,18 +8,18 @@ #ifndef __TIZEN_LOGO_16BPP__ #define __TIZEN_LOGO_16BPP__ -#define TIZEN_LOGO_16BPP_WIDTH 500 -#define TIZEN_LOGO_16BPP_HEIGHT 160 +#define TIZEN_LOGO_16BPP_WIDTH 452 +#define TIZEN_LOGO_16BPP_HEIGHT 140 /* Center align offsets for word "TIZEN" */ -#define TIZEN_LOGO_16BPP_X_OFFSET (30) -#define TIZEN_LOGO_16BPP_Y_OFFSET (-26) +#define TIZEN_LOGO_16BPP_X_OFFSET (16) +#define TIZEN_LOGO_16BPP_Y_OFFSET (-20) -/* Format: BMP RGB565 16BPP 500x160 */ +/* Format: BMP RGB565 16BPP 452x140 */ unsigned char tizen_logo_16bpp[] = { -0x42,0x4d,0x46,0x71,0x02,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00, -0x00,0x00,0xf4,0x01,0x00,0x00,0xa0,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00, -0x00,0x00,0x00,0x71,0x02,0x00,0x13,0x0b,0x00,0x00,0x13,0x0b,0x00,0x00,0x00,0x00, +0x42,0x4d,0xa6,0xee,0x01,0x00,0x00,0x00,0x00,0x00,0x46,0x00,0x00,0x00,0x38,0x00, +0x00,0x00,0xc4,0x01,0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x10,0x00,0x03,0x00, +0x00,0x00,0x60,0xee,0x01,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,0x00,0x00,0xe0,0x07,0x00,0x00,0x1f,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -181,6 +181,7 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x21,0x08,0x86,0x31,0x65,0x29,0x41,0x08,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -229,10 +230,15 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08,0x20,0x00,0x20,0x08,0x20,0x00, +0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x08,0x20,0x00,0x20,0x00,0x20,0x00, +0x20,0x00,0x21,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52,0x34,0xa5,0xb6,0xb5, +0x96,0xb5,0x34,0xa5,0xd2,0x94,0xef,0x7b,0xeb,0x5a,0x08,0x42,0x04,0x21,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -248,1900 +254,162 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0xf3,0x9c,0xf3,0x9c,0x13,0x9d,0x14,0xa5,0x14,0xa5,0x34,0xa5,0x34,0xa5,0x34,0xa5, +0x54,0xa5,0x55,0xad,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x24,0x21,0xd6,0xb5,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x17,0xc6,0x18,0xc6, +0x17,0xc6,0x18,0xc6,0x18,0xbe,0x18,0xc6,0x17,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, +0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x38,0xc6,0x75,0xad,0x41,0x08,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -6668,7 +3733,17 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0xd7,0xbd,0xd7,0xbd,0x96,0xb5,0x45,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -6680,19 +3755,33 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xb5,0xd7,0xbd,0xd6,0xb5,0xb7,0xbd,0xd6,0xb5, +0xd7,0xbd,0xd6,0xbd,0xd7,0xb5,0xd7,0xbd,0xd7,0xb5,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd, +0xd7,0xb5,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -6700,14 +3789,19 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf3,0x9c,0x18,0xc6,0x17,0xbe, +0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd, +0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0x17,0xbe,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, +0xf7,0xbd,0x17,0xbe,0xd3,0x9c,0x92,0x94,0xb3,0x94,0xf3,0x9c,0x14,0xa5,0x34,0xa5, +0x54,0xa5,0x55,0xad,0x75,0xad,0x96,0xad,0x96,0xb5,0xb6,0xb5,0xb6,0xb5,0xd6,0xb5, +0xd7,0xb5,0xd6,0xbd,0xf7,0xbd,0xef,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x14,0xa5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd, +0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, +0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd6,0xbd,0x96,0xb5,0x45,0x29, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x91,0x03,0xdf,0x06,0x7f,0x06,0x3e,0x06,0x1e,0x06,0xfe,0x05,0xdd,0x05, -0xbd,0x05,0x9d,0x05,0x7d,0x05,0x5d,0x05,0x3c,0x05,0xfc,0x04,0x1d,0x05,0x1c,0x0d, -0xb1,0x4b,0xa2,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xf3,0x03,0x5f,0x07,0x9f,0x06,0x6b,0x02,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -6717,10 +3811,17 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8e,0x73,0xf7,0xbd,0xd6,0xb5,0xd6,0xbd, +0xd6,0xb5,0xd6,0xbd,0xd7,0xb5,0xd6,0xb5,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, +0xd7,0xbd,0xd7,0xbd,0xd6,0xb5,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd,0xd6,0xbd,0xd7,0xbd, +0xf7,0xbd,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0x10,0x84,0x10,0x84,0x10,0x84, +0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x10,0x84,0x30,0x84,0x30,0x84, +0x30,0x84,0x51,0x8c,0x51,0x8c,0x51,0x8c,0x71,0x8c,0x71,0x8c,0x92,0x94,0x92,0x94, +0xb2,0x94,0xd2,0x94,0xd3,0x9c,0xf3,0x9c,0x14,0xa5,0xd3,0x9c,0x24,0x21,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xa3,0x18,0xb6,0xb5,0x38,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, +0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6,0x18,0xc6, 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@@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x30,0x84,0xd7,0xbd,0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xb5, +0xd6,0xb5,0xb6,0xb5,0xd6,0xb5,0xb6,0xbd,0xd6,0xb5,0xd7,0xb5,0xd6,0xb5,0xb6,0xbd, +0xd6,0xb5,0xd6,0xbd,0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xb5,0xd7,0xb5,0xd6,0xbd, +0xd6,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, +0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, +0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd, +0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd, +0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xd7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd, 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-0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x92,0x03, -0xff,0x05,0xbf,0x05,0x7e,0x05,0x5e,0x05,0x1d,0x05,0xdc,0x04,0x9b,0x04,0x5a,0x04, -0xd9,0x03,0x79,0x2c,0x3d,0xd7,0xff,0xff,0xde,0xf7,0xfe,0xff,0xfe,0xff,0xfe,0xff, -0xbe,0xf7,0xf7,0xbd,0x28,0x4a,0x00,0x00,0xae,0x02,0xde,0x05,0xde,0x05,0x9d,0x05, -0x9d,0x05,0x9d,0x05,0x9d,0x05,0x9d,0x05,0x9d,0x05,0x7d,0x05,0xff,0x05,0x35,0x0c, -0xa3,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7224,6 +5147,8 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x21, +0x66,0x31,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7232,7 +5157,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0xd6,0x33,0x99,0x44,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x44,0x98,0x4c,0x99,0x54, +0x78,0x54,0xb5,0x3b,0x6f,0x1a,0x28,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00, +0x69,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7266,11 +5195,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x00,0x36,0x04,0xb9,0x04,0x99,0x04,0x58,0x04, -0x38,0x04,0xf7,0x03,0xb6,0x03,0x75,0x03,0xf4,0x02,0xd6,0x2b,0xfc,0xce,0xfe,0xff, -0xbe,0xf7,0xfe,0xff,0xfe,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0x37,0xd6,0x6f,0x3b, -0xb9,0x04,0xdf,0x05,0x7d,0x05,0x7d,0x05,0x7d,0x05,0x7d,0x05,0x7d,0x05,0x7d,0x05, -0x7d,0x05,0x5d,0x05,0x9e,0x05,0xd9,0x04,0x67,0x09,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7289,7 +5213,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x12,0x99,0x44,0x99,0x44,0x99,0x44, +0x99,0x44,0x79,0x44,0x99,0x44,0xda,0x4c,0x1b,0x5d,0x3c,0x65,0xfb,0x4c,0x79,0x34, +0xb5,0x23,0xcb,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x23,0x79,0x3c,0xc6,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7328,12 +5256,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x70,0x94, -0x55,0x95,0x2a,0x1a,0xc5,0x00,0x06,0x01,0x06,0x01,0x06,0x01,0xe6,0x00,0xc5,0x00, -0x84,0x00,0xe9,0x29,0x9a,0xce,0xff,0xff,0x9d,0xf7,0xde,0xf7,0xde,0xf7,0xfe,0xff, -0xfe,0xff,0xff,0xff,0xfa,0xee,0x95,0x44,0x1c,0x05,0x7d,0x05,0x5d,0x05,0x5d,0x05, -0x5d,0x05,0x5d,0x05,0x5d,0x05,0x5d,0x05,0x5d,0x05,0x5d,0x05,0x7e,0x05,0x1b,0x1d, -0xe9,0x19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7348,7 +5270,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x12,0x23,0xb9,0x44,0x79,0x44,0x79,0x44,0x78,0x44,0x79,0x44,0x78,0x44, +0x99,0x4c,0xfa,0x5c,0x1b,0x65,0xfb,0x54,0x9a,0x3c,0x59,0x24,0xd1,0x22,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x0a,0x79,0x3c, +0x79,0x3c,0x4e,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7391,11 +5317,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x82,0x10,0x0c,0x63,0xf7,0xbd,0xff,0xff,0xff,0xff,0x50,0x94,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x29,0x58,0xce,0xff,0xff, -0x7d,0xef,0xbd,0xf7,0xbe,0xf7,0xbe,0xf7,0xff,0xff,0xff,0xff,0xee,0x83,0x26,0x01, -0x58,0x04,0x9e,0x05,0x3c,0x05,0x3d,0x05,0x3d,0x05,0x3c,0x05,0x3c,0x05,0x3d,0x05, -0x3c,0x05,0x3c,0x05,0x3d,0x05,0x1b,0x1d,0xe9,0x19,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7405,7 +5326,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xf6,0x33,0x99,0x44, +0x78,0x44,0x79,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x99,0x44,0xda,0x54,0x1b,0x5d, +0xfb,0x54,0x9a,0x3c,0x59,0x24,0x72,0x3b,0x20,0x08,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xa6,0x00,0x37,0x34,0x79,0x3c,0x79,0x3c,0xb5,0x2b,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7453,17 +5378,16 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xe7,0x39,0xd2,0x9c,0xfb,0xde,0xde,0xf7,0xfe,0xff, -0xff,0xff,0xde,0xf7,0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x45,0x29,0x58,0xc6,0xff,0xff,0x5c,0xef,0x9d,0xef,0x9d,0xef,0xbe,0xf7, -0xff,0xff,0x96,0xb5,0x61,0x10,0x00,0x00,0x73,0x03,0x9f,0x05,0x1c,0x05,0x1c,0x05, -0x1c,0x05,0x1c,0x05,0x1c,0x05,0x1c,0x05,0x1c,0x05,0xfc,0x04,0x1d,0x05,0x98,0x14, -0x86,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x07,0x01,0x58,0x44,0x79,0x44,0x78,0x44,0x78,0x44,0x78,0x44, +0x58,0x44,0x58,0x3c,0x78,0x44,0xb9,0x4c,0x1b,0x5d,0x1b,0x5d,0xba,0x44,0x79,0x2c, +0xb2,0x5b,0xa1,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x95,0x2b,0x79,0x3c,0x58,0x3c, +0x79,0x3c,0x58,0x3c,0xc6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7515,13 +5439,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe3,0x18,0x8e,0x73,0x17,0xc6, -0x7d,0xef,0xde,0xf7,0xfe,0xff,0xfe,0xff,0xbe,0xf7,0xff,0xff,0xba,0xd6,0x86,0x31, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0x38,0xc6,0xde,0xff, -0x5c,0xe7,0x7d,0xef,0x7d,0xef,0xff,0xff,0xba,0xd6,0xa6,0x31,0x00,0x00,0x00,0x00, -0x4d,0x02,0x1c,0x05,0xfc,0x04,0xfc,0x04,0xfc,0x04,0xfc,0x04,0xdc,0x04,0xdc,0x04, -0xdb,0x04,0xbb,0x04,0x3e,0x05,0xd3,0x23,0x81,0x10,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x12, +0x99,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x3c,0x58,0x44, +0x99,0x4c,0xfa,0x5c,0x1b,0x5d,0xba,0x44,0x78,0x4c,0xf0,0x7b,0x24,0x29,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0xb0,0x1a,0x79,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x99,0x3c,0x6f,0x12,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7574,15 +5496,14 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x23,0x99,0x44,0x58,0x44,0x78,0x44, +0x58,0x44,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x79,0x44,0xda,0x54,0x1b,0x5d, +0xda,0x4c,0xd5,0x84,0x50,0x8c,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x8a,0x01,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, +0x58,0x3c,0x79,0x3c,0xb5,0x2b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x08, -0x89,0x4a,0x34,0xa5,0xda,0xde,0x9d,0xef,0xde,0xf7,0xfe,0xff,0xfe,0xff,0xde,0xff, -0xbe,0xf7,0xbd,0xf7,0xff,0xff,0x55,0xad,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0x38,0xc6,0xbe,0xf7,0x3c,0xe7,0x5c,0xe7,0xde,0xf7,0x7d,0xef, -0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x01,0x17,0x04,0xfc,0x04,0x9b,0x04, -0xbb,0x04,0xbb,0x04,0x9b,0x04,0x9b,0x04,0x7a,0x04,0x5b,0x04,0xfa,0x2c,0x8b,0x3a, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7632,6 +5553,10 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0x00,0xd6,0x33,0x79,0x44,0x58,0x44,0x58,0x44,0x58,0x44,0x58,0x3c,0x58,0x3c, +0x58,0x3c,0x58,0x3c,0x79,0x44,0xda,0x54,0x1b,0x5d,0x18,0x85,0x13,0xa5,0x71,0x8c, +0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x44,0x00,0xf6,0x33, +0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x79,0x3c,0x58,0x34,0xa6,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7640,12 +5565,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x85,0x39,0x30,0x8c,0x58,0xce,0x5c,0xe7,0x9d,0xef,0xde,0xf7, -0xfe,0xff,0xfe,0xff,0xde,0xff,0xde,0xf7,0xbe,0xf7,0x9d,0xef,0x9d,0xf7,0xbe,0xf7, -0xef,0x7b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0x18,0xc6,0xbe,0xf7, -0x1b,0xdf,0x7d,0xef,0xde,0xf7,0x71,0x8c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x12,0x03,0xbc,0x04,0x5a,0x04,0x5a,0x04,0x5a,0x04,0x3a,0x04,0xf9,0x03, -0xd9,0x03,0xfb,0x34,0x52,0x6c,0xa2,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7690,6 +5609,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x01,0x37,0x3c,0x58,0x44, +0x58,0x44,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x44, +0xba,0x4c,0x59,0x8d,0x96,0xb5,0x14,0xa5,0x92,0x94,0xeb,0x5a,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x33,0x23,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, +0x58,0x3c,0x58,0x3c,0x58,0x34,0xed,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7702,12 +5626,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0xe3,0x20,0x2c,0x5b,0x75,0xa5,0xfb,0xd6, -0xbd,0xf7,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,0xf7,0xde,0xf7,0xbe,0xf7,0xbd,0xf7, -0x9d,0xf7,0x9d,0xef,0x5c,0xef,0xde,0xf7,0x3c,0xe7,0xaa,0x52,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0xf7,0xbd,0x9d,0xef,0x1c,0xe7,0x9d,0xf7,0x75,0xad,0x82,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xec,0x01,0x39,0x04,0x19,0x04, -0xd8,0x03,0x98,0x03,0xb8,0x03,0x18,0x14,0x39,0x5d,0x18,0xae,0xca,0x62,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7748,6 +5666,10 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x2d,0x12,0x78,0x44,0x78,0x44,0x58,0x44,0x58,0x3c,0x58,0x3c, +0x58,0x3c,0x58,0x44,0x58,0x3c,0x58,0x3c,0x79,0x34,0x59,0x85,0x58,0xce,0xd6,0xb5, +0x34,0xa5,0xb2,0x94,0x6d,0x6b,0x20,0x00,0x00,0x00,0x2e,0x12,0x58,0x3c,0x58,0x3c, +0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x78,0x3c,0x58,0x34,0x38,0x2c,0xf2,0x12, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7764,13 +5686,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x6b,0x32, -0x75,0x54,0x59,0x55,0x7a,0x5d,0x7a,0x65,0xfb,0x8d,0xdc,0xbe,0x7e,0xdf,0xfe,0xff, -0xff,0xff,0xff,0xff,0xde,0xf7,0x9d,0xef,0x7d,0xef,0x7d,0xef,0x7c,0xef,0x5c,0xe7, -0xde,0xf7,0x18,0xc6,0x45,0x29,0x00,0x00,0x00,0x00,0x25,0x21,0xf7,0xbd,0x7d,0xef, -0x7d,0xef,0x79,0xce,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x84,0x00,0xd4,0x02,0xb9,0x03,0xd7,0x0b,0x59,0x24,0x3a,0x5d,0x7b,0xae, -0x5c,0xef,0x33,0xad,0x04,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7807,6 +5722,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8f,0x1a, +0x74,0x2b,0x94,0x2b,0xb5,0x33,0xb5,0x33,0xd5,0x33,0xd6,0x33,0xf6,0x33,0xf6,0x33, +0xd6,0x23,0xf7,0x7c,0x9a,0xd6,0x59,0xce,0xd7,0xbd,0x55,0xad,0xd3,0x9c,0xae,0x73, +0xa8,0x21,0xf7,0x33,0x38,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, +0x58,0x3c,0x38,0x34,0xf7,0x23,0x74,0x1b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7827,12 +5747,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xe4,0x18,0xf3,0x33,0x3c,0x1d,0xdc,0x04,0x7b,0x04,0x3a,0x04,0xf9,0x03, -0xb8,0x03,0xb8,0x03,0x99,0x34,0xdb,0x7d,0x9c,0xb6,0x1c,0xd7,0xbe,0xf7,0xff,0xff, -0xde,0xff,0x7d,0xef,0x3c,0xe7,0x3c,0xe7,0x3c,0xe7,0xbe,0xf7,0xd3,0x9c,0x41,0x08, -0x00,0x00,0x04,0x21,0x59,0xce,0xff,0xff,0x3c,0xe7,0x0c,0x63,0x00,0x00,0x00,0x00, -0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x73,0x2b,0x5b,0x55, -0x3b,0x96,0x7e,0xdf,0xfe,0xff,0xbd,0xff,0x1b,0xe7,0x8e,0x73,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7865,6 +5779,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x00,0x00,0x00,0x00,0x00,0x00, +0x01,0x00,0x02,0x00,0x23,0x00,0x23,0x00,0x01,0x00,0xec,0x5a,0xba,0xd6,0x9a,0xd6, +0x79,0xce,0xf7,0xbd,0x75,0xad,0xd3,0x9c,0x51,0x84,0x36,0x4c,0x38,0x34,0x58,0x3c, +0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x17,0x2c,0xf7,0x1b,0x95,0x23, +0x64,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7889,13 +5808,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x14,0x2c,0x9f,0x0d,0x1d,0x05, -0xdc,0x04,0x9b,0x04,0x7b,0x04,0x5a,0x04,0x19,0x04,0xd8,0x03,0x98,0x03,0x98,0x03, -0xb8,0x03,0xef,0x32,0x6d,0x73,0x34,0xa5,0x99,0xce,0x7d,0xef,0xff,0xff,0x9d,0xef, -0x3c,0xe7,0x3c,0xe7,0x7d,0xef,0x4d,0x6b,0x00,0x00,0x41,0x08,0x8e,0x73,0xf7,0xbd, -0x30,0x84,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x61,0x08,0x86,0x31, -0x0c,0x63,0xd2,0x9c,0xfb,0xde,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0x9d,0xf7, -0xd6,0xbd,0xe7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7923,6 +5835,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0xec,0x5a, +0x30,0x84,0x8e,0x73,0x20,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xe7,0x39,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x99,0xce,0x18,0xc6,0x96,0xb5, +0xd2,0x9c,0xd4,0x43,0x38,0x34,0x38,0x3c,0x38,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c, +0x58,0x34,0x17,0x24,0xd6,0x1b,0xb5,0x23,0x85,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7951,13 +5868,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08, -0x0f,0x23,0x9e,0x0d,0x5e,0x05,0x1c,0x05,0xfc,0x04,0xfc,0x04,0xdb,0x04,0xbb,0x04, -0x7a,0x04,0x5a,0x04,0x19,0x04,0x1a,0x04,0x97,0x03,0x85,0x00,0x00,0x00,0x00,0x00, -0xc7,0x39,0x6d,0x6b,0xf3,0x9c,0x18,0xc6,0x5c,0xe7,0xdf,0xff,0xde,0xf7,0xae,0x73, -0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x41,0x08,0x00,0x00,0x00,0x00,0x62,0x10, -0xc7,0x39,0x0c,0x63,0xb2,0x94,0xba,0xd6,0xfe,0xff,0xff,0xff,0xfe,0xff,0xfe,0xff, -0xff,0xff,0xff,0xff,0xbd,0xf7,0x5c,0xe7,0x71,0x8c,0x21,0x08,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -7982,6 +5892,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x69,0x4a,0x0f,0x7c,0x71,0x8c,0xd3,0x9c,0x55,0xad,0xb2,0x94,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x42,0xba,0xd6,0x9a,0xd6, +0x9a,0xd6,0x9a,0xd6,0x99,0xd6,0x59,0xce,0x0f,0x84,0xcc,0x01,0x58,0x3c,0x38,0x3c, +0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x37,0x2c,0xf6,0x23,0xb5,0x13,0x53,0x23, +0x43,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8014,13 +5929,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x10,0xd9,0x14,0xbf,0x05,0x5d,0x05,0x3c,0x05, -0x3c,0x05,0x1c,0x05,0xfc,0x04,0xfc,0x04,0xbb,0x04,0x9b,0x04,0x7a,0x04,0x7b,0x04, -0x13,0x03,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31, -0x4d,0x6b,0xf3,0x9c,0x51,0x8c,0xe4,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xe4,0x20,0x2d,0x6b,0xf3,0x9c,0x99,0xce,0xbe,0xf7,0xde,0xf7,0xbe,0xf7, -0xbe,0xf7,0xbe,0xf7,0xbe,0xf7,0xde,0xf7,0xfe,0xff,0xff,0xff,0xbd,0xf7,0x99,0xd6, -0xaa,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8040,6 +5948,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x39,0xae,0x73,0x51,0x8c,0xb2,0x94,0x14,0xa5, +0x75,0xad,0xf7,0xbd,0x79,0xce,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xe7,0x39,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x38,0xc6, +0xc3,0x18,0x24,0x00,0x17,0x34,0x58,0x34,0x58,0x3c,0x58,0x3c,0x58,0x3c,0x58,0x34, +0x17,0x2c,0xd6,0x1b,0x95,0x13,0xd0,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8076,13 +5989,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcd,0x1a, -0x9d,0x0d,0x7e,0x05,0x5d,0x05,0x5d,0x05,0x5d,0x05,0x3c,0x05,0x1c,0x05,0x1c,0x05, -0xfc,0x04,0xdb,0x04,0xbc,0x04,0xbc,0x04,0x0c,0x02,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x63,0xbe,0xf7,0xff,0xff, -0x7d,0xef,0x5c,0xe7,0x5d,0xef,0x7d,0xef,0x7d,0xef,0x9d,0xef,0xbe,0xf7,0xde,0xf7, -0xfe,0xff,0xff,0xff,0xbe,0xf7,0x75,0xad,0xe3,0x18,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8098,6 +6004,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x29,0x6d,0x6b,0x51,0x8c, +0x92,0x94,0xf3,0x9c,0x55,0xad,0xd6,0xb5,0x38,0xc6,0x79,0xce,0x9a,0xd6,0xba,0xd6, +0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc7,0x39,0x9a,0xd6,0x9a,0xd6, +0x99,0xd6,0x9a,0xd6,0x9a,0xd6,0x8a,0x52,0x00,0x00,0x00,0x00,0x74,0x23,0x58,0x3c, +0x58,0x3c,0x58,0x3c,0x58,0x3c,0x38,0x34,0xf7,0x23,0xd6,0x13,0x94,0x1b,0xa9,0x21, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8139,12 +6050,7 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x15,0x0c,0x1f,0x06,0x7d,0x05,0x7d,0x05,0x7d,0x05, -0x5d,0x05,0x5d,0x05,0x3d,0x05,0x3c,0x05,0x1c,0x05,0xfc,0x04,0x1d,0x05,0x9b,0x04, -0x27,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x6d,0x6b,0xbe,0xf7,0xde,0xf7,0x7d,0xef,0x7d,0xef,0x5d,0xef,0x7d,0xef, -0x7d,0xef,0x9d,0xf7,0xbe,0xf7,0xde,0xf7,0xff,0xff,0xff,0xff,0x5c,0xe7,0xcf,0x7b, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8154,6 +6060,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0x10, +0xeb,0x5a,0x30,0x84,0x71,0x94,0xd3,0x9c,0x34,0xa5,0x96,0xb5,0xf7,0xbd,0x79,0xce, +0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x79,0xce,0xa6,0x31,0x00,0x00,0x00,0x00, +0x00,0x00,0xc7,0x39,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x51,0x8c,0x00,0x00, +0x00,0x00,0x00,0x00,0x0d,0x12,0x58,0x3c,0x58,0x34,0x58,0x3c,0x58,0x3c,0x37,0x2c, +0xd6,0x0b,0x95,0x03,0xd2,0x5b,0x41,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8201,17 +6113,15 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x01,0x1a,0x05, -0x1f,0x06,0x9d,0x05,0x9d,0x05,0x9d,0x05,0x7d,0x05,0x7d,0x05,0x5d,0x05,0x5d,0x05, -0x3c,0x05,0x3d,0x05,0x5e,0x05,0xd5,0x03,0xa3,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x08,0x42,0x10,0x84,0x6d,0x6b,0x82,0x10, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0x10,0x84,0x18,0xc6, -0x5d,0xef,0xbe,0xf7,0xbe,0xf7,0xde,0xf7,0xbe,0xf7,0xbe,0xf7,0xbe,0xf7,0xde,0xff, -0xff,0xff,0xff,0xff,0x58,0xce,0xe7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x08,0x8a,0x4a,0x11,0x74,0x72,0x84,0xb3,0x8c,0x14,0x9d,0x75,0xb5, +0xf7,0xbd,0x58,0xce,0x99,0xce,0x9a,0xd6,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6, +0xba,0xd6,0xd7,0xbd,0x41,0x08,0x00,0x00,0x00,0x00,0x86,0x31,0x79,0xce,0x9a,0xd6, +0xba,0xd6,0x96,0xb5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x85,0x00,0x17,0x34, +0x58,0x3c,0x58,0x34,0x38,0x24,0xd7,0x03,0x16,0x3c,0xb5,0x84,0x6d,0x6b,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8263,13 +6173,13 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2c,0x22,0x15,0x4c,0x78,0x4c,0xb9,0x4c, +0xfa,0x54,0xfa,0x64,0xf9,0x64,0x39,0x85,0xd9,0xad,0x39,0xc6,0xba,0xd6,0xda,0xd6, +0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x9a,0xd6,0xda,0xd6,0xd3,0x9c,0x00,0x00, +0x00,0x00,0x86,0x31,0x79,0xce,0xba,0xd6,0x59,0xce,0x65,0x29,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x13,0x58,0x2c,0x78,0x4c,0xf8,0x74,0x78,0x95, +0xb7,0xb5,0x54,0xad,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xce,0x02,0xfe,0x05,0xde,0x05,0xbd,0x05,0xbd,0x05,0x9d,0x05, -0x9d,0x05,0x7d,0x05,0x7d,0x05,0x7d,0x05,0x5d,0x05,0x5d,0x05,0x9f,0x05,0x6e,0x02, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0x08,0x42,0x0f,0x84,0x75,0xad, -0x79,0xce,0x9d,0xef,0x9e,0xf7,0x2c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x20,0x00,0x24,0x21,0x49,0x4a,0xef,0x7b,0x17,0xbe,0x7d,0xef, -0xde,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0x9c,0x41,0x08, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8319,6 +6229,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa5,0x00,0xb5,0x33, +0x79,0x2c,0x9a,0x2c,0xdb,0x44,0xfb,0x54,0xfb,0x54,0xda,0x54,0xda,0x4c,0xba,0x4c, +0x99,0x44,0xc8,0x21,0xe8,0x41,0x92,0x94,0xd7,0xbd,0x9a,0xd6,0xda,0xd6,0xba,0xd6, +0xba,0xd6,0x9a,0xd6,0xba,0xd6,0x2c,0x63,0x00,0x00,0xe4,0x20,0xf7,0xbd,0xba,0xd6, +0x0c,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x91,0x5b, +0xb9,0x9d,0x59,0xbe,0x9a,0xd6,0x59,0xce,0xd7,0xbd,0x10,0x84,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8326,13 +6242,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x35,0x04,0x9f,0x06, -0xdd,0x05,0xde,0x05,0xdd,0x05,0xbd,0x05,0xbd,0x05,0x9d,0x05,0x9d,0x05,0x7d,0x05, -0x7d,0x05,0xdf,0x05,0x3c,0x05,0x27,0x01,0x00,0x00,0x62,0x08,0x08,0x42,0x50,0x8c, -0xf7,0xbd,0xda,0xd6,0x7d,0xef,0xde,0xf7,0x7d,0xef,0x3c,0xe7,0xde,0xf7,0xef,0x7b, -0x00,0x00,0x00,0x00,0xaa,0x52,0x14,0xa5,0x8e,0x73,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0xe3,0x18,0x28,0x42,0x30,0x84,0x38,0xc6,0x9d,0xf7,0xff,0xff, -0xff,0xff,0x1b,0xef,0x69,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8377,6 +6286,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x85,0x00,0xf7,0x2b,0x9a,0x2c,0xba,0x44,0xfb,0x54,0xfb,0x5c,0xfa,0x54, +0xda,0x54,0xda,0x54,0xba,0x54,0xda,0x54,0xf6,0x3b,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xa7,0x39,0xcf,0x7b,0x96,0xb5,0x59,0xce,0xba,0xd6,0xdb,0xde,0x96,0xb5, +0x00,0x00,0x00,0x00,0xe3,0x18,0xc7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x29,0x4a,0x92,0x94,0xf7,0xbd,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x79,0xce,0x18,0xbe, +0x75,0xad,0xe7,0x39,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8389,12 +6304,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x46,0x01,0x5a,0x05,0x7f,0x06,0xfe,0x05,0xfe,0x05,0xfe,0x05,0xde,0x05, -0xbd,0x05,0xbe,0x05,0xff,0x05,0x1f,0x06,0x1f,0x06,0xdf,0x05,0x15,0x04,0xab,0x42, -0x50,0x94,0x58,0xc6,0x1b,0xe7,0xbe,0xf7,0xff,0xff,0xde,0xf7,0x5c,0xef,0x1b,0xe7, -0x1c,0xe7,0xbe,0xf7,0x96,0xb5,0x04,0x21,0x00,0x00,0xe4,0x20,0xd6,0xb5,0xff,0xff, -0xfb,0xde,0x69,0x4a,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x20,0x00,0xc3,0x18,0xe7,0x41,0xef,0x8b,0x37,0xce,0x13,0x9d,0xa3,0x10,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8433,6 +6342,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb5,0x2b,0xbb,0x3c,0xdb,0x4c, +0x1b,0x5d,0xfb,0x5c,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54, +0x8e,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x45,0x29,0x4d,0x6b,0x34,0xa5,0x08,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x08,0x42,0x92,0x94,0xf7,0xbd,0xba,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6, +0x9a,0xd6,0x9a,0xd6,0x59,0xce,0xf7,0xbd,0x92,0x94,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8451,14 +6366,7 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xee,0x02,0x7f,0x06,0x5f,0x06, -0x1e,0x06,0xfd,0x05,0xfd,0x05,0x1e,0x06,0x3f,0x06,0x3f,0x06,0xdd,0x05,0x5b,0x05, -0x77,0x04,0x8e,0x02,0x6e,0x53,0xfa,0xde,0xff,0xff,0xff,0xff,0xff,0xff,0xde,0xff, -0x9d,0xef,0x7d,0xef,0x7d,0xef,0x3c,0xe7,0x9d,0xef,0x99,0xd6,0xe7,0x39,0x00,0x00, -0x00,0x00,0x45,0x29,0x38,0xc6,0xbe,0xf7,0x9e,0xf7,0x38,0xc6,0x65,0x29,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0xae,0x12,0x98,0x0c,0x93,0x03,0x0a,0x02,0xc4,0x00,0x21,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8491,7 +6399,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x8f,0x1a,0xfb,0x4c,0x1b,0x5d,0x1b,0x5d,0xfa,0x5c,0xfa,0x54,0xda,0x54,0xda,0x54, +0xda,0x54,0xda,0x54,0xda,0x54,0x99,0x4c,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x86,0x31,0x9a,0xd6,0xba,0xd6,0xba,0xd6, +0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0x99,0xce,0x38,0xc6,0xb6,0xb5, +0xab,0x5a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8514,14 +6427,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x75,0x04,0xff,0x06,0x3e,0x06,0x5f,0x06,0x9f,0x06,0x9f,0x06,0x1e,0x06, -0x7b,0x05,0x96,0x04,0xef,0x02,0x46,0x01,0x01,0x00,0x00,0x00,0xaa,0x5a,0x7c,0xef, -0xff,0xff,0xfe,0xff,0xde,0xf7,0xbe,0xf7,0x9d,0xf7,0x7d,0xef,0x5c,0xef,0x9d,0xef, -0x5d,0xef,0x4d,0x6b,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0xf7,0xbd,0x9d,0xef, -0x3c,0xe7,0xbe,0xf7,0x34,0xa5,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x62,0x00,0xb0,0x02,0xba,0x04,0x5d,0x05,0xbe,0x05,0xbd,0x05, -0x1a,0x05,0xb3,0x03,0x2a,0x02,0xe5,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8550,7 +6455,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x22,0x00,0xb9,0x54,0x3b,0x5d,0x1b,0x5d,0xfa,0x54, +0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xb5,0x3b, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x45,0x29,0x38,0xc6,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0x9a,0xd6, +0x9a,0xd6,0x79,0xce,0xf7,0xbd,0x14,0xa5,0x61,0x08,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8576,14 +6486,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa8,0x01,0xfc,0x05,0x5f,0x07,0xff,0x06, -0x7f,0x06,0xbb,0x05,0x96,0x04,0x0f,0x03,0x47,0x01,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x86,0x31,0x17,0xbe,0xff,0xff,0xfe,0xff,0xde,0xff,0xde,0xf7, -0xbd,0xf7,0x9d,0xef,0x7d,0xef,0xde,0xf7,0xd2,0x94,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x21,0x18,0xc6,0xbe,0xf7,0x1b,0xdf,0x7d,0xef,0x9d,0xef,0xcf,0x7b, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x27,0x01,0xd6,0x03,0x5e,0x05, -0x7e,0x05,0x7d,0x05,0x9e,0x05,0xff,0x05,0x1f,0x06,0x1f,0x06,0x1e,0x06,0x9b,0x05, -0x14,0x04,0x6b,0x02,0x26,0x01,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8609,6 +6511,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xad,0x22, +0x3c,0x5d,0x1b,0x5d,0xfa,0x54,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54, +0xda,0x54,0xda,0x54,0xda,0x54,0x0b,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0xa6,0x31,0xae,0x73,0xb6,0xb5,0x79,0xce,0x8e,0x73, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x20,0xeb,0x5a,0x34,0xa5, +0x38,0xc6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0x58,0xc6,0xb6,0xb5,0x8d,0x6b, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8639,14 +6547,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x6b,0x02,0x5d,0x06,0xfc,0x05,0xd6,0x04,0x4f,0x03,0x67,0x01,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x10,0xf3,0x9c, -0xde,0xff,0xfe,0xff,0xfe,0xff,0xde,0xf7,0xbe,0xf7,0x9d,0xef,0xff,0xff,0x38,0xc6, -0x24,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x24,0x21,0x38,0xc6,0xde,0xf7, -0x3c,0xe7,0x5c,0xe7,0xde,0xf7,0x1b,0xdf,0x69,0x4a,0x00,0x00,0x00,0x00,0x21,0x00, -0x0c,0x02,0x39,0x04,0x3d,0x05,0x3d,0x05,0x3c,0x05,0x5d,0x05,0x7d,0x05,0x9d,0x05, -0xbd,0x05,0xfe,0x05,0x3f,0x06,0x5f,0x06,0x7f,0x06,0x7f,0x06,0xdc,0x05,0x55,0x04, -0xcd,0x02,0x66,0x01,0x62,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8668,6 +6568,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x37,0x4c,0x1b,0x5d,0xfb,0x54,0xfa,0x54,0xda,0x54, +0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0x78,0x4c,0x02,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x41,0x30,0x84,0xd7,0xb5,0x9a,0xd6, +0xda,0xd6,0xba,0xd6,0xdb,0xde,0x75,0xad,0x00,0x00,0x00,0x00,0x8a,0x52,0x8e,0x73, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc3,0x18,0xaa,0x52,0xf3,0x9c,0x18,0xc6, +0x9a,0xd6,0x38,0xc6,0x55,0xad,0x24,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8701,14 +6607,7 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x01,0xac,0x02,0xa8,0x01,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0x9d,0xef,0xde,0xf7,0xfe,0xff,0xfe,0xff, -0xbe,0xf7,0xff,0xff,0x1b,0xe7,0x69,0x52,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x24,0x29,0x38,0xc6,0xde,0xff,0x5c,0xe7,0x7d,0xef,0x7d,0xef,0xff,0xff, -0x38,0xc6,0x04,0x21,0x22,0x00,0xb0,0x02,0x5a,0x04,0xbc,0x04,0xdb,0x04,0xfc,0x04, -0x1c,0x05,0x3d,0x05,0x5d,0x05,0x7d,0x05,0x9d,0x05,0xbd,0x05,0xdd,0x05,0xfe,0x05, -0x3f,0x06,0x7f,0x06,0x9f,0x06,0xdf,0x06,0xff,0x06,0x1c,0x06,0x74,0x04,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8725,6 +6624,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x01,0xfb,0x5c, +0xfb,0x5c,0xfb,0x54,0xfb,0x54,0xfa,0x54,0xfa,0x54,0xfa,0x54,0xda,0x54,0xfa,0x54, +0xfb,0x54,0xba,0x54,0xaf,0x22,0x00,0x00,0x00,0x00,0x49,0x4a,0x92,0x94,0x38,0xc6, +0xba,0xd6,0xda,0xd6,0xba,0xd6,0xba,0xd6,0x9a,0xd6,0xba,0xd6,0x79,0xce,0x86,0x31, +0x00,0x00,0x45,0x29,0x9a,0xd6,0xdb,0xde,0x10,0x84,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x82,0x10,0x08,0x42,0x10,0x7c,0x32,0x74,0x01,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8765,13 +6670,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaa,0x52, -0xba,0xd6,0xde,0xf7,0xfe,0xff,0xfe,0xff,0xfe,0xff,0xff,0xff,0xb3,0x7c,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x29,0x58,0xce,0xff,0xff, -0x7c,0xef,0x9d,0xef,0x9d,0xef,0xbe,0xf7,0xfe,0xff,0x56,0x9d,0xf2,0x02,0xd9,0x03, -0x3a,0x04,0x5a,0x04,0x9b,0x04,0xdc,0x04,0x1c,0x05,0x3c,0x05,0x5d,0x05,0x7d,0x05, -0x9d,0x05,0xbd,0x05,0xbd,0x05,0xde,0x05,0xfe,0x05,0x1e,0x06,0x3e,0x06,0x9f,0x06, -0x3f,0x07,0xdf,0x06,0x95,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8783,6 +6681,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x10,0x2b,0x1b,0x5d,0xfb,0x5c,0xfb,0x5c,0xfb,0x5c,0xfb,0x5c, +0x1b,0x55,0xfb,0x54,0x98,0x4c,0xb5,0x3b,0x4d,0x1a,0xc5,0x00,0x00,0x00,0x00,0x00, +0x10,0x84,0xf7,0xbd,0xba,0xd6,0xfb,0xde,0xdb,0xde,0xba,0xd6,0x9a,0xd6,0x9a,0xd6, +0xba,0xd6,0xba,0xd6,0x6d,0x6b,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6, +0xba,0xd6,0x69,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x45,0x00,0x54,0x23,0x58,0x34,0xf6,0x33,0xf2,0x22,0x69,0x01,0x02,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8828,17 +6732,18 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0x96,0xb5,0xbd,0xf7,0xde,0xf7,0xff,0xff, -0xff,0xff,0xbc,0xae,0x75,0x0b,0xac,0x01,0x42,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x25,0x29,0x79,0xce,0xff,0xff,0x7d,0xef,0xbd,0xf7,0xbe,0xf7,0xbd,0xf7, -0xfe,0xff,0xff,0xff,0x9b,0x6d,0x78,0x03,0xd8,0x03,0x3a,0x04,0x9b,0x04,0xdb,0x04, -0xfc,0x04,0x1c,0x05,0x5d,0x05,0x5d,0x05,0x7d,0x05,0x9d,0x05,0xbd,0x05,0xde,0x05, -0xfe,0x05,0x1e,0x06,0x5f,0x06,0xff,0x06,0x1d,0x06,0x2f,0x03,0x62,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x57,0x4c,0x1b,0x5d, +0x1b,0x5d,0x1b,0x5d,0xfb,0x5c,0x58,0x4c,0x53,0x33,0xea,0x11,0x43,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xcf,0x7b,0x96,0xb5,0x59,0xce,0xdb,0xde, +0xdb,0xde,0xba,0xd6,0x9a,0xd6,0x9a,0xd6,0xdb,0xd6,0x34,0xa5,0x00,0x00,0x00,0x00, +0x00,0x00,0x65,0x29,0x79,0xce,0xba,0xd6,0xba,0xd6,0x58,0xc6,0x45,0x29,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x4e,0x12,0x38,0x3c,0x99,0x44,0x79,0x44,0x99,0x44, +0x99,0x44,0x99,0x44,0x17,0x3c,0x12,0x23,0x89,0x01,0x02,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8889,14 +6794,13 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x18,0xc6,0xe3,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6, +0x9a,0xd6,0xba,0xd6,0xb6,0xb5,0x00,0x00,0x00,0x00,0x85,0x00,0x74,0x2b,0x99,0x44, +0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x79,0x44,0x99,0x44,0xba,0x44, +0xb9,0x44,0x17,0x3c,0x12,0x23,0x89,0x01,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -8946,19 +6850,20 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0xea,0x11,0xc5,0x00, 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xae,0x73,0x1b,0xdf,0xdd,0xff,0xfe,0xff, -0x5a,0x65,0x77,0x03,0xd8,0x03,0x3a,0x04,0x9c,0x04,0x18,0x04,0xeb,0x01,0x00,0x00, -0x00,0x00,0x24,0x29,0x99,0xd6,0xff,0xff,0xde,0xf7,0xfe,0xff,0xfe,0xff,0xfe,0xff, -0xfe,0xff,0xff,0xff,0xff,0xff,0xdc,0xbe,0x18,0x1c,0x98,0x03,0x5a,0x04,0xbb,0x04, -0xdc,0x04,0x1c,0x05,0x3c,0x05,0x5d,0x05,0x7d,0x05,0x7d,0x05,0x9d,0x05,0xde,0x05, -0x5f,0x06,0x1e,0x06,0xb2,0x03,0xc4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9004,6 +6909,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x41,0x08,0xb2,0x94,0xd7,0xb5,0x79,0xce,0xfb,0xde,0xdb,0xde,0xda,0xde,0x10,0x84, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x66,0x31,0x79,0xce,0xba,0xd6, +0x9a,0xd6,0x9a,0xd6,0x9a,0xd6,0xba,0xd6,0x59,0x85,0x79,0x34,0x79,0x44,0x79,0x44, +0x99,0x44,0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44, +0x99,0x44,0x99,0x44,0x99,0x44,0x9a,0x44,0xda,0x44,0x79,0x44,0x07,0x01,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9016,11 +6926,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x8a,0x52,0x78,0xce,0xbd,0xff,0x3b,0x9e,0xb8,0x03,0xb8,0x03,0x39,0x04,0x7a,0x04, -0x9b,0x04,0x1d,0x05,0xdc,0x04,0x11,0x03,0x22,0x00,0xe3,0x28,0xfa,0xde,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xfe,0xff,0xfe,0xff, -0x3b,0x9e,0xf8,0x0b,0xd9,0x03,0x7a,0x04,0xdb,0x04,0xfc,0x04,0x1c,0x05,0x3d,0x05, -0x5d,0x05,0x7d,0x05,0xde,0x05,0x3f,0x06,0x3a,0x05,0x6c,0x02,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9060,6 +6965,12 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x84,0x96,0xb5,0x59,0xce, +0xdb,0xde,0xfb,0xde,0x3a,0xbe,0xc9,0x19,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x65,0x29,0x79,0xce,0xda,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6, +0x9a,0xce,0xf9,0x6c,0x59,0x34,0x79,0x44,0x79,0x44,0x99,0x44,0x99,0x44,0x99,0x44, +0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0x99,0x44,0xba,0x44,0xba,0x44, +0xb5,0x2b,0xa5,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9078,12 +6989,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x65,0x29,0xb5,0xbd,0x1c,0xdf,0x78,0x2c, -0xb8,0x03,0x3a,0x04,0x7a,0x04,0xbb,0x04,0xdb,0x04,0xfc,0x04,0x5d,0x05,0x7e,0x05, -0xd5,0x03,0x8c,0x22,0x58,0xce,0xff,0xff,0xbe,0xf7,0xde,0xf7,0xde,0xf7,0xde,0xff, -0xfe,0xff,0xde,0xf7,0xbe,0xf7,0xde,0xff,0xbd,0xf7,0x3b,0x9e,0x7a,0x1c,0x5b,0x04, -0xbb,0x04,0xfc,0x04,0x1d,0x05,0x3d,0x05,0x9e,0x05,0xdf,0x05,0xde,0x0d,0x55,0x0c, -0x46,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9117,6 +7022,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x2c,0x63,0x75,0xad,0x18,0xc6,0xda,0xde,0xdb,0xd6,0x3a,0x75,0x99,0x44, +0x6d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x29,0xba,0xd6,0x1c,0xe7, +0xfb,0xde,0xfb,0xde,0xfb,0xde,0xdb,0xde,0xfb,0xde,0x7a,0xc6,0x98,0x4c,0x38,0x2c, +0x58,0x34,0x58,0x34,0x58,0x34,0x79,0x3c,0x79,0x3c,0x79,0x3c,0x79,0x3c,0x79,0x3c, +0x99,0x3c,0x9a,0x44,0x79,0x44,0xb0,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9141,11 +7051,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x61,0x10,0xb2,0x9c,0x1a,0x9e,0x18,0x0c,0x19,0x04,0x9a,0x04,0xbb,0x04,0xdc,0x04, -0xfc,0x04,0x1c,0x05,0x3c,0x05,0x5d,0x05,0xbf,0x05,0xb9,0x04,0x6e,0x53,0x0f,0x8c, -0xb2,0x94,0x13,0x9d,0x55,0xad,0xd6,0xb5,0xf7,0xbd,0xf7,0xbd,0xf7,0xbd,0x38,0xc6, -0x78,0xd6,0x78,0xd6,0xb8,0x8d,0xf9,0x34,0xbb,0x0c,0xfc,0x0c,0x5d,0x0d,0x5d,0x05, -0x7d,0x0d,0xf9,0x1c,0xad,0x1a,0x62,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9173,6 +7078,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe7,0x39,0x55,0xad,0xf7,0xbd, +0xba,0xd6,0xda,0x9d,0xba,0x44,0xda,0x54,0xda,0x54,0x73,0x33,0x02,0x00,0x00,0x00, +0x00,0x00,0x65,0x29,0xda,0xde,0x1c,0xe7,0x1b,0xdf,0x1c,0xe7,0x1b,0xdf,0x1c,0xdf, +0x1c,0xe7,0x3c,0xe7,0x1a,0xb6,0xd6,0x13,0xd6,0x13,0xf6,0x23,0xf7,0x23,0x17,0x24, +0x17,0x24,0x17,0x24,0x17,0x24,0x38,0x2c,0x38,0x2c,0xb5,0x23,0x28,0x01,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9203,11 +7113,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xae,0x73,0x39,0x55,0x3a,0x04, -0x7a,0x04,0xbb,0x04,0xfc,0x04,0x1c,0x05,0x1c,0x05,0x3c,0x05,0x5d,0x05,0x5d,0x05, -0xbe,0x05,0x3b,0x05,0x26,0x01,0x00,0x08,0x82,0x08,0x82,0x10,0xa2,0x10,0xc3,0x18, -0x04,0x21,0x45,0x29,0x66,0x31,0xc7,0x39,0x08,0x42,0x69,0x52,0xca,0x5a,0x0c,0x53, -0x50,0x3b,0xd3,0x2b,0x15,0x2c,0xb2,0x23,0x6c,0x1a,0xe4,0x10,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9230,6 +7135,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0xa3,0x18,0xf3,0x9c,0xd7,0xbd,0xd9,0xa5,0xba,0x4c,0xda,0x4c,0xda,0x54, +0xda,0x54,0xda,0x54,0x37,0x44,0x07,0x01,0x00,0x00,0xa7,0x39,0x59,0xce,0x79,0xce, +0x99,0xce,0x9a,0xd6,0xba,0xd6,0xba,0xd6,0xba,0xd6,0xdb,0xde,0xfb,0xde,0x58,0x95, +0x74,0x03,0x95,0x03,0x95,0x1b,0x95,0x1b,0xb5,0x1b,0xb5,0x1b,0xd6,0x1b,0xd6,0x1b, +0x6f,0x0a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9266,10 +7176,7 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xaa,0x52,0x78,0x1c,0x7b,0x04,0xdb,0x04,0xfc,0x04,0x1c,0x05,0x3c,0x05, -0x3c,0x05,0x5d,0x05,0x5d,0x05,0x7d,0x05,0xdf,0x05,0x5b,0x05,0xe5,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x40,0x10,0x41,0x08,0x41,0x08,0x41,0x08, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9284,6 +7191,11 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x51,0x8c,0x96,0xad, +0x98,0x54,0x99,0x3c,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0x99,0x4c, +0x48,0x01,0x00,0x00,0x0c,0x63,0x8e,0x73,0x30,0x84,0x92,0x94,0xf3,0x9c,0x34,0xa5, +0x75,0xad,0xb6,0xb5,0x18,0xbe,0x58,0xc6,0x16,0x95,0x93,0x3b,0x33,0x0b,0x53,0x13, +0x53,0x13,0x73,0x1b,0xd0,0x1a,0xe7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9328,9 +7240,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa7,0x31,0x58,0x0c,0xdc,0x04, -0xfc,0x04,0x1c,0x05,0x3c,0x05,0x3d,0x05,0x5d,0x05,0x5d,0x05,0x7d,0x05,0x9d,0x05, -0xff,0x05,0x5b,0x05,0x26,0x01,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9339,6 +7248,10 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x8d,0x73,0xf6,0x8c,0x17,0x0c,0x99,0x44,0xda,0x54,0xda,0x54, +0xda,0x54,0xda,0x54,0xda,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0xe4,0x20,0x86,0x31,0x08,0x42, +0xeb,0x5a,0xcc,0x52,0x4c,0x32,0x4d,0x1a,0x0c,0x1a,0xe6,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9391,9 +7304,9 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0xa3,0x10,0x77,0x14,0x3d,0x05,0xfc,0x04,0x3c,0x05,0x5d,0x05,0x5d,0x05, -0x7d,0x05,0x7d,0x05,0x9d,0x05,0xbd,0x05,0x1f,0x06,0x7b,0x05,0x26,0x01,0x00,0x00, -0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x69,0x52,0x55,0x64, +0xf7,0x03,0x79,0x3c,0xda,0x4c,0xfa,0x54,0xda,0x54,0xda,0x54,0xda,0x54,0xfa,0x54, +0xaf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9448,14 +7361,13 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x45,0x29,0xf5,0x4b,0xf7,0x03,0x58,0x34,0xda,0x4c,0xda,0x54, +0xda,0x54,0xda,0x54,0xfa,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x91,0x33,0x5d,0x0d, -0x3d,0x05,0x5d,0x05,0x5d,0x05,0x7d,0x05,0x7d,0x05,0x9d,0x05,0xbd,0x05,0xde,0x05, -0x3f,0x06,0x7c,0x05,0x26,0x01,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9505,6 +7417,9 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x41,0x08,0x52,0x33, +0xd6,0x0b,0x38,0x2c,0xba,0x4c,0xfa,0x54,0xfa,0x54,0xfa,0x54,0xda,0x54,0xfb,0x54, +0xaf,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9516,9 +7431,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x66,0x21,0xf9,0x1c,0xbf,0x05,0x5d,0x05,0x7d,0x05,0x9d,0x05, -0x9d,0x05,0xbd,0x05,0xbd,0x05,0xde,0x05,0x3f,0x06,0x9c,0x05,0x26,0x01,0x00,0x00, -0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9562,6 +7474,8 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0xd0,0x2a,0xd6,0x13,0x18,0x24,0x99,0x44,0xfb,0x54, +0xfb,0x54,0xfb,0x54,0xfa,0x54,0xfb,0x54,0xcf,0x22,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9578,9 +7492,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6b,0x22, -0x9d,0x0d,0xdf,0x05,0x9d,0x05,0x9d,0x05,0xbd,0x05,0xbd,0x05,0xde,0x05,0xfe,0x05, -0x5f,0x06,0xbc,0x05,0x26,0x01,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9619,6 +7530,9 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x89,0x11, +0xd6,0x23,0x17,0x1c,0x79,0x3c,0xfa,0x54,0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x55, +0x8e,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9641,9 +7555,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8c,0x12,0x7b,0x15,0x1f,0x06,0xde,0x05, -0xbd,0x05,0xde,0x05,0xfe,0x05,0x1e,0x06,0x7f,0x06,0xdc,0x05,0x46,0x01,0x00,0x00, -0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9676,6 +7587,8 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb0,0x22,0x18,0x1c,0x79,0x34,0xda,0x54, +0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x5d,0x8d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9704,8 +7617,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x08,0xc9,0x11,0xb8,0x04,0x3f,0x06,0x1f,0x06,0xfe,0x05,0x1e,0x06,0x3e,0x06, -0x9f,0x06,0xdc,0x05,0x46,0x01,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9733,6 +7644,8 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x12,0x1b,0x59,0x2c,0xda,0x4c,0xfb,0x54,0xfb,0x54,0xfb,0x54,0x1b,0x55, +0x8d,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9766,9 +7679,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe4,0x00,0xb3,0x03, -0x1f,0x06,0x7f,0x06,0x3f,0x06,0x3e,0x06,0xbf,0x06,0xfc,0x05,0x46,0x01,0x00,0x00, -0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9790,6 +7700,8 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd1,0x1a,0xda,0x4c, +0x1b,0x55,0xfb,0x5c,0xfb,0x54,0x1b,0x5d,0x6c,0x1a,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9829,8 +7741,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x21,0x00,0xad,0x02,0x9b,0x05,0xdf,0x06,0x9f,0x06, -0xdf,0x06,0x1c,0x06,0x46,0x01,0x00,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9847,6 +7757,8 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x1a,0xda,0x54,0x1b,0x5d,0xfb,0x54,0x1b,0x5d, +0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9892,8 +7804,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x87,0x01,0xd7,0x04,0xdf,0x06,0x5f,0x07,0x5e,0x06,0x66,0x01,0x00,0x00, -0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9904,6 +7814,7 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x67,0x09,0x78,0x4c,0x3c,0x5d,0x1c,0x5d,0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -9954,13 +7865,13 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,0x00,0xb1,0x03, -0xbf,0x06,0x3d,0x06,0x46,0x01,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x73,0x33,0x3c,0x5d, +0x2b,0x1a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -10017,7 +7928,6 @@ unsigned char tizen_logo_16bpp[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xad,0x02,0xb1,0x03,0xc3,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/lib/tizen/tizen_logo_16bpp_gzip.h b/lib/tizen/tizen_logo_16bpp_gzip.h index a8af64612f..b05498df4e 100644 --- a/lib/tizen/tizen_logo_16bpp_gzip.h +++ b/lib/tizen/tizen_logo_16bpp_gzip.h @@ -8,720 +8,641 @@ #ifndef __TIZEN_LOGO_16BPP_GZIP__ #define __TIZEN_LOGO_16BPP_GZIP__ -/* Format: GZIP: BMP RGB565 16BPP 500x160 */ +/* Format: GZIP: BMP RGB565 16BPP 452x140 */ unsigned char tizen_logo_16bpp_gzip[] = { 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+0xfc,0x50,0x70,0x28,0x24,0xd4,0x1c,0xfd,0xdd,0xa1,0xdd,0xf1,0xee,0x49,0x94,0x41, +0xa3,0xfb,0xcc,0x1f,0x09,0x0e,0x85,0x84,0x9a,0xa4,0x0b,0x87,0x76,0x53,0x28,0xa3, +0x54,0xf7,0x99,0xc3,0x82,0x43,0x21,0xa1,0xa6,0xe9,0x0f,0x7f,0xe9,0xe2,0xf8,0xf0, +0x99,0xa7,0x05,0x87,0x42,0x42,0x4d,0x55,0x47,0x68,0xf6,0xe8,0xb0,0xe0,0x50,0x48, +0xa8,0xed,0xf5,0xff,0x01,0xd1,0x0a,0xff,0xc9,0xa6,0xee,0x01,0x00}; #endif diff --git a/lib/uuid.c b/lib/uuid.c index c48bf38362..f6b4423551 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -4,21 +4,58 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <linux/ctype.h> -#include "common.h" +#include <errno.h> +#include <common.h> +#include <asm/io.h> +#include <part_efi.h> +#include <malloc.h> /* - * This is what a UUID string looks like. + * UUID - Universally Unique IDentifier - 128 bits unique number. + * There are 5 versions and one variant of UUID defined by RFC4122 + * specification. A UUID contains a set of fields. The set varies + * depending on the version of the UUID, as shown below: + * - time, MAC address(v1), + * - user ID(v2), + * - MD5 of name or URL(v3), + * - random data(v4), + * - SHA-1 of name or URL(v5), * - * x is a hexadecimal character. fields are separated by '-'s. When converting - * to a binary UUID, le means the field should be converted to little endian, - * and be means it should be converted to big endian. + * Layout of UUID: + * timestamp - 60-bit: time_low, time_mid, time_hi_and_version + * version - 4 bit (bit 4 through 7 of the time_hi_and_version) + * clock seq - 14 bit: clock_seq_hi_and_reserved, clock_seq_low + * variant: - bit 6 and 7 of clock_seq_hi_and_reserved + * node - 48 bit + * + * source: https://www.ietf.org/rfc/rfc4122.txt + * + * UUID binary format (16 bytes): + * + * 4B-2B-2B-2B-6B (big endian - network byte order) + * + * UUID string is 36 length of characters (36 bytes): * * 0 9 14 19 24 * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx + * be be be be be + * + * where x is a hexadecimal character. Fields are separated by '-'s. + * When converting to a binary UUID, le means the field should be converted + * to little endian and be means it should be converted to big endian. + * + * UUID is also used as GUID (Globally Unique Identifier) with the same binary + * format but it differs in string format like below. + * + * GUID: + * 0 9 14 19 24 + * xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx * le le le be be + * + * GUID is used e.g. in GPT (GUID Partition Table) as a partiions unique id. */ - int uuid_str_valid(const char *uuid) { int i, valid; @@ -37,33 +74,182 @@ int uuid_str_valid(const char *uuid) } } - if (i != 36 || !valid) + if (i != UUID_STR_LEN || !valid) return 0; return 1; } -void uuid_str_to_bin(const char *uuid, unsigned char *out) +/* + * uuid_str_to_bin() - convert string UUID or GUID to big endian binary data. + * + * @param uuid_str - pointer to UUID or GUID string [37B] + * @param uuid_bin - pointer to allocated array for big endian output [16B] + * @str_format - UUID string format: 0 - UUID; 1 - GUID + */ +int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format) { uint16_t tmp16; uint32_t tmp32; uint64_t tmp64; - if (!uuid || !out) - return; + if (!uuid_str_valid(uuid_str)) + return -EINVAL; - tmp32 = cpu_to_le32(simple_strtoul(uuid, NULL, 16)); - memcpy(out, &tmp32, 4); + if (str_format == UUID_STR_FORMAT_STD) { + tmp32 = cpu_to_be32(simple_strtoul(uuid_str, NULL, 16)); + memcpy(uuid_bin, &tmp32, 4); - tmp16 = cpu_to_le16(simple_strtoul(uuid + 9, NULL, 16)); - memcpy(out + 4, &tmp16, 2); + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 9, NULL, 16)); + memcpy(uuid_bin + 4, &tmp16, 2); - tmp16 = cpu_to_le16(simple_strtoul(uuid + 14, NULL, 16)); - memcpy(out + 6, &tmp16, 2); + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 14, NULL, 16)); + memcpy(uuid_bin + 6, &tmp16, 2); + } else { + tmp32 = cpu_to_le32(simple_strtoul(uuid_str, NULL, 16)); + memcpy(uuid_bin, &tmp32, 4); - tmp16 = cpu_to_be16(simple_strtoul(uuid + 19, NULL, 16)); - memcpy(out + 8, &tmp16, 2); + tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 9, NULL, 16)); + memcpy(uuid_bin + 4, &tmp16, 2); - tmp64 = cpu_to_be64(simple_strtoull(uuid + 24, NULL, 16)); - memcpy(out + 10, (char *)&tmp64 + 2, 6); + tmp16 = cpu_to_le16(simple_strtoul(uuid_str + 14, NULL, 16)); + memcpy(uuid_bin + 6, &tmp16, 2); + } + + tmp16 = cpu_to_be16(simple_strtoul(uuid_str + 19, NULL, 16)); + memcpy(uuid_bin + 8, &tmp16, 2); + + tmp64 = cpu_to_be64(simple_strtoull(uuid_str + 24, NULL, 16)); + memcpy(uuid_bin + 10, (char *)&tmp64 + 2, 6); + + return 0; } + +/* + * uuid_bin_to_str() - convert big endian binary data to string UUID or GUID. + * + * @param uuid_bin - pointer to binary data of UUID (big endian) [16B] + * @param uuid_str - pointer to allocated array for output string [37B] + * @str_format - UUID string format: 0 - UUID; 1 - GUID + */ +void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format) +{ + const u8 uuid_char_order[UUID_BIN_LEN] = {0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15}; + const u8 guid_char_order[UUID_BIN_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8, + 9, 10, 11, 12, 13, 14, 15}; + const u8 *char_order; + int i; + + /* + * UUID and GUID bin data - always in big endian: + * 4B-2B-2B-2B-6B + * be be be be be + */ + if (str_format == UUID_STR_FORMAT_STD) + char_order = uuid_char_order; + else + char_order = guid_char_order; + + for (i = 0; i < 16; i++) { + sprintf(uuid_str, "%02x", uuid_bin[char_order[i]]); + uuid_str += 2; + switch (i) { + case 3: + case 5: + case 7: + case 9: + *uuid_str++ = '-'; + break; + } + } +} + +/* + * gen_rand_uuid() - this function generates a random binary UUID version 4. + * In this version all fields beside 4 bits of version and + * 2 bits of variant are randomly generated. + * + * @param uuid_bin - pointer to allocated array [16B]. Output is in big endian. +*/ +#if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID) +void gen_rand_uuid(unsigned char *uuid_bin) +{ + struct uuid uuid; + unsigned int *ptr = (unsigned int *)&uuid; + int i; + + /* Set all fields randomly */ + for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++) + *(ptr + i) = cpu_to_be32(rand()); + + clrsetbits_be16(&uuid.time_hi_and_version, + UUID_VERSION_MASK, + UUID_VERSION << UUID_VERSION_SHIFT); + + clrsetbits_8(&uuid.clock_seq_hi_and_reserved, + UUID_VARIANT_MASK, + UUID_VARIANT << UUID_VARIANT_SHIFT); + + memcpy(uuid_bin, &uuid, sizeof(struct uuid)); +} + +/* + * gen_rand_uuid_str() - this function generates UUID v4 (random) in two string + * formats UUID or GUID. + * + * @param uuid_str - pointer to allocated array [37B]. + * @param - uuid output type: UUID - 0, GUID - 1 + */ +void gen_rand_uuid_str(char *uuid_str, int str_format) +{ + unsigned char uuid_bin[UUID_BIN_LEN]; + + /* Generate UUID (big endian) */ + gen_rand_uuid(uuid_bin); + + /* Convert UUID bin to UUID or GUID formated STRING */ + uuid_bin_to_str(uuid_bin, uuid_str, str_format); +} + +#ifdef CONFIG_CMD_UUID +int do_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char uuid[UUID_STR_LEN + 1]; + int str_format; + + if (!strcmp(argv[0], "uuid")) + str_format = UUID_STR_FORMAT_STD; + else + str_format = UUID_STR_FORMAT_GUID; + + if (argc > 2) + return CMD_RET_USAGE; + + gen_rand_uuid_str(uuid, str_format); + + if (argc == 1) + printf("%s\n", uuid); + else + setenv(argv[1], uuid); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(uuid, CONFIG_SYS_MAXARGS, 1, do_uuid, + "UUID - generate random Universally Unique Identifier", + "[<varname>]\n" + "Argument:\n" + "varname: for set result in a environment variable\n" + "e.g. uuid uuid_env" +); + +U_BOOT_CMD(guid, CONFIG_SYS_MAXARGS, 1, do_uuid, + "GUID - generate Globally Unique Identifier based on random UUID", + "[<varname>]\n" + "Argument:\n" + "varname: for set result in a environment variable\n" + "e.g. guid guid_env" +); +#endif /* CONFIG_CMD_UUID */ +#endif /* CONFIG_RANDOM_UUID || CONFIG_CMD_UUID */ diff --git a/net/bootp.c b/net/bootp.c index 4300f1c2f1..189a003835 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -439,7 +439,7 @@ static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID, *e++ = 17; *e++ = 0; /* type 0 - UUID */ - uuid_str_to_bin(uuid, e); + uuid_str_to_bin(uuid, e, UUID_STR_FORMAT_STD); e += 16; } else { printf("Invalid pxeuuid: %s\n", uuid); diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean index 5cd0f51770..d6dcd47f6f 100644 --- a/scripts/Makefile.clean +++ b/scripts/Makefile.clean @@ -39,7 +39,8 @@ subdir-ymn := $(addprefix $(obj)/,$(subdir-ymn)) # Temporal work-around for U-Boot -subdir-ymn := $(foreach f, $(subdir-ymn), $(if $(wildcard $f/Makefile),$f)) +subdir-ymn := $(foreach f, $(subdir-ymn), \ + $(if $(wildcard $(srctree)/$f/Makefile),$f)) # build a list of files to remove, usually relative to the current # directory diff --git a/spl/Makefile b/spl/Makefile index be5fd3b53a..6fec2522a8 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -171,7 +171,7 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -quiet_cmd_mkimage = UIMAGE $@ +quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) @@ -231,11 +231,11 @@ $(u-boot-spl-dirs): $(Q)$(MAKE) $(build)=$@ quiet_cmd_cpp_lds = LDS $@ -cmd_cpp_lds = $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ \ - -x assembler-with-cpp -P -o $@ $< +cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ + -D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $< $(obj)/u-boot-spl.lds: $(LDSCRIPT) FORCE - $(call if_changed,cpp_lds) + $(call if_changed_dep,cpp_lds) # read all saved command lines diff --git a/tools/patman/README b/tools/patman/README index 59f1776f54..b3aba136b8 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -217,8 +217,10 @@ Series-changes: n to update the log there and then, knowing that the script will do the rest. - Cc: Their Name <email> - This copies a single patch to another email address. +Patch-cc: Their Name <email> + This copies a single patch to another email address. Note that the + Cc: used by git send-email is ignored by patman, but will be + interpreted by git send-email if you use it. Series-process-log: sort, uniq This tells patman to sort and/or uniq the change logs. It is @@ -246,8 +248,9 @@ Where Patches Are Sent Once the patches are created, patman sends them using git send-email. The whole series is sent to the recipients in Series-to: and Series-cc. -You can Cc individual patches to other people with the Cc: tag. Tags in the -subject are also picked up to Cc patches. For example, a commit like this: +You can Cc individual patches to other people with the Patch-cc: tag. Tags +in the subject are also picked up to Cc patches. For example, a commit like +this: >>>> commit 10212537b85ff9b6e09c82045127522c0f0db981 @@ -258,16 +261,16 @@ Date: Mon Nov 7 23:18:44 2011 -0500 This should make sending out e-mails to the right people easier. - Cc: sandbox, mikef, ag - Cc: afleming + Patch-cc: sandbox, mikef, ag + Patch-cc: afleming <<<< will create a patch which is copied to x86, arm, sandbox, mikef, ag and afleming. -If you have a cover letter it will get sent to the union of the CC lists of -all of the other patches. If you want to sent it to additional people you -can add a tag: +If you have a cover letter it will get sent to the union of the Patch-cc +lists of all of the other patches. If you want to sent it to additional +people you can add a tag: Cover-letter-cc: <list of addresses> diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index 684204c63f..c4017e0e6d 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -36,7 +36,7 @@ re_series_tag = re.compile('^Series-([a-z-]*): *(.*)') re_commit_tag = re.compile('^Commit-([a-z-]*): *(.*)') # Commit tags that we want to collect and keep -re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)') +re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Patch-cc): (.*)') # The start of a new commit in the git log re_commit = re.compile('^commit ([0-9a-f]*)$') @@ -267,7 +267,7 @@ class PatchStream: if (tag_match.group(1) == 'Tested-by' and tag_match.group(2).find(os.getenv('USER') + '@') != -1): self.warn.append("Ignoring %s" % line) - elif tag_match.group(1) == 'Cc': + elif tag_match.group(1) == 'Patch-cc': self.commit.AddCc(tag_match.group(2).split(',')) else: self.tags.append(line); |