diff options
| -rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 6 | ||||
| -rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 5 | ||||
| -rw-r--r-- | drivers/spi/rk_spi.c | 10 |
3 files changed, 19 insertions, 2 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5a8c084255..eb49a6c11c 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -546,6 +546,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, (long long)instr->len); + if (!instr->len) + return 0; + div_u64_rem(instr->len, mtd->erasesize, &rem); if (rem) return -EINVAL; @@ -1226,6 +1229,9 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); + if (!len) + return 0; + for (i = 0; i < len; ) { ssize_t written; loff_t addr = to + i; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index d3b84574ac..973b6f86c9 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -108,6 +108,11 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { + INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index c04535ac44..95eeb8307a 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -27,6 +27,12 @@ /* Change to 1 to output registers at the start of each transaction */ #define DEBUG_RK_SPI 0 +/* + * ctrlr1 is 16-bits, so we should support lengths of 0xffff + 1. However, + * the controller seems to hang when given 0x10000, so stick with this for now. + */ +#define ROCKCHIP_SPI_MAX_TRANLEN 0xffff + struct rockchip_spi_params { /* RXFIFO overruns and TXFIFO underruns stop the master clock */ bool master_manages_fifo; @@ -367,7 +373,7 @@ static inline int rockchip_spi_16bit_reader(struct udevice *dev, * represented in CTRLR1. */ if (data && data->master_manages_fifo) - max_chunk_size = 0x10000; + max_chunk_size = ROCKCHIP_SPI_MAX_TRANLEN; // rockchip_spi_configure(dev, mode, size) rkspi_enable_chip(regs, false); @@ -451,7 +457,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, /* This is the original 8bit reader/writer code */ while (len > 0) { - int todo = min(len, 0x10000); + int todo = min(len, ROCKCHIP_SPI_MAX_TRANLEN); rkspi_enable_chip(regs, false); writel(todo - 1, ®s->ctrlr1); |