diff options
42 files changed, 829 insertions, 240 deletions
diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts index 191e12af6a..c7553208ad 100644 --- a/arch/arm/dts/exynos5250-spring.dts +++ b/arch/arm/dts/exynos5250-spring.dts @@ -40,9 +40,46 @@ reg = <0x40000000 0x80000000>; }; + iram { + reg = <0x02020000 0x60000>; + }; + + config { + samsung,bl1-offset = <0x1400>; + samsung,bl2-offset = <0x3400>; + u-boot-memory = "/memory"; + u-boot-offset = <0x3e00000 0x100000>; + }; + flash@0 { - spl { /* spl size override */ - size = <0x8000>; + reg = <0 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + pre-boot { + label = "bl1 pre-boot"; + reg = <0 0x2000>; + read-only; + filename = "e5250.nbl1.bin"; + type = "blob exynos-bl1"; + required; + }; + + spl { + label = "bl2 spl"; + reg = <0x2000 0x8000>; + read-only; + filename = "bl2.bin"; + type = "blob exynos-bl2 boot,dtb"; + payload = "/flash/ro-boot"; + required; + }; + + ro-boot { + label = "u-boot"; + reg = <0xa000 0xb0000>; + read-only; + type = "blob boot,dtb"; + required; }; }; @@ -93,6 +130,22 @@ samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; }; + sound { + compatible = "google,spring-audio-max98088"; + + samsung,model = "Spring-I2S-MAX98088"; + samsung,audio-codec = <&max98088>; + codec-enable-gpio = <&gpx1 7 0>; + + cpu { + sound-dai = <&i2s1 0>; + }; + + codec { + sound-dai = <&max98088 0>; + }; + }; + spi@12d30000 { spi-max-frequency = <50000000>; firmware_storage_spi: flash@0 { @@ -638,27 +691,11 @@ }; }; - max98095: soundcodec@10 { + max98088: soundcodec@10 { reg = <0x10>; - compatible = "maxim,max98095"; + compatible = "maxim,max98088"; #sound-dai-cells = <1>; }; - - sound { - compatible = "google,spring-audio-max98095"; - - samsung,model = "Spring-I2S-MAX98095"; - samsung,audio-codec = <&max98095>; - - cpu { - sound-dai = <&i2s0 0>; - }; - - codec { - sound-dai = <&max98095 0>; - }; - }; - }; #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index ed04369cfa..3807770362 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -8,6 +8,8 @@ config ARCH_EXYNOS4 bool "Exynos4 SoC family" select BOARD_EARLY_INIT_F select CPU_V7A + select BLK + select DM_MMC help Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There are multiple SoCs in this family including Exynos4210, Exynos4412, @@ -24,6 +26,9 @@ config ARCH_EXYNOS5 imply USB_ETHER_ASIX imply USB_ETHER_RTL8152 imply USB_ETHER_SMSC95XX + select BLK + select DM_MMC + help Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs @@ -33,6 +38,8 @@ config ARCH_EXYNOS7 bool "Exynos7 SoC family" select ARM64 select BOARD_EARLY_INIT_F + select BLK + select DM_MMC help Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or Cortex-A53 CPU (and some in a big.LITTLE configuration). There are diff --git a/arch/arm/mach-exynos/include/mach/mmc.h b/arch/arm/mach-exynos/include/mach/mmc.h index ca4e7eda34..eece44ea1a 100644 --- a/arch/arm/mach-exynos/include/mach/mmc.h +++ b/arch/arm/mach-exynos/include/mach/mmc.h @@ -64,6 +64,4 @@ static inline int s5p_mmc_init(int index, int bus_width) return s5p_sdhci_init(base, index, bus_width); } -int exynos_mmc_init(const void *blob); - #endif diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig index 04acdaad79..8cffced551 100644 --- a/arch/arm/mach-s5pc1xx/Kconfig +++ b/arch/arm/mach-s5pc1xx/Kconfig @@ -7,6 +7,8 @@ choice config TARGET_S5P_GONI bool "S5P Goni board" select OF_CONTROL + select BLK + select DM_MMC config TARGET_SMDKC100 bool "Support smdkc100 board" diff --git a/arch/arm/mach-s5pc1xx/Makefile b/arch/arm/mach-s5pc1xx/Makefile index a4be3fcbda..ab804604d5 100644 --- a/arch/arm/mach-s5pc1xx/Makefile +++ b/arch/arm/mach-s5pc1xx/Makefile @@ -10,3 +10,4 @@ obj-y = cache.o obj-y += reset.o obj-y += clock.o +obj-y += pinmux.o diff --git a/arch/arm/mach-s5pc1xx/pinmux.c b/arch/arm/mach-s5pc1xx/pinmux.c new file mode 100644 index 0000000000..818d75164d --- /dev/null +++ b/arch/arm/mach-s5pc1xx/pinmux.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Dummy functions to keep s5p_goni building (although it won't work) + * + * Copyright 2018 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <common.h> +#include <asm/arch/pinmux.h> + +int exynos_pinmux_config(int peripheral, int flags) +{ + return 0; +} + +int pinmux_decode_periph_id(const void *blob, int node) +{ + return 0; +} diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 6fd26a3a91..96228a86a1 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -249,56 +249,16 @@ int board_eth_init(bd_t *bis) return 0; } -#ifdef CONFIG_MMC -static int init_mmc(void) -{ -#ifdef CONFIG_MMC_SDHCI - return exynos_mmc_init(gd->fdt_blob); -#else - return 0; -#endif -} - -static int init_dwmmc(void) -{ -#ifdef CONFIG_MMC_DW - return exynos_dwmmc_init(gd->fdt_blob); -#else - return 0; -#endif -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - - if (get_boot_mode() == BOOT_MODE_SD) { - ret = init_mmc(); - ret |= init_dwmmc(); - } else { - ret = init_dwmmc(); - ret |= init_mmc(); - } - - if (ret) - debug("mmc init failed\n"); - - return ret; -} -#endif - #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - const char *board_info; + if (IS_ENABLED(CONFIG_BOARD_TYPES)) { + const char *board_info = get_board_type(); + + if (board_info) + printf("Type: %s\n", board_info); + } - board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - printf("Board: %s\n", board_info ? board_info : "unknown"); -#ifdef CONFIG_BOARD_TYPES - board_info = get_board_type(); - if (board_info) - printf("Type: %s\n", board_info); -#endif return 0; } #endif diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index c183965b92..87eb381345 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -34,37 +34,8 @@ DECLARE_GLOBAL_DATA_PTR; -static void board_enable_audio_codec(void) -{ - int node, ret; - struct gpio_desc en_gpio; - - node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_SAMSUNG_EXYNOS5_SOUND); - if (node <= 0) - return; - - ret = gpio_request_by_name_nodev(offset_to_ofnode(node), - "codec-enable-gpio", 0, &en_gpio, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - if (ret == -FDT_ERR_NOTFOUND) - return; - - /* Turn on the GPIO which connects to the codec's "enable" line. */ - gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE); - -#ifdef CONFIG_SOUND_MAX98095 - /* Enable MAX98095 Codec */ - gpio_request(EXYNOS5_GPIO_X17, "max98095_enable"); - gpio_direction_output(EXYNOS5_GPIO_X17, 1); - gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); -#endif -} - int exynos_init(void) { - board_enable_audio_codec(); - return 0; } diff --git a/common/Kconfig b/common/Kconfig index 8f9d2959ba..0a14bdedaa 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -656,6 +656,14 @@ config BOUNCE_BUFFER A second possible use of bounce buffers is their ability to provide aligned buffers for DMA operations. +config BOARD_TYPES + bool "Call get_board_type() to get and display the board type" + help + If this option is enabled, checkboard() will call get_board_type() + to get a string containing the board type and this will be + displayed immediately after the model is shown on the console + early in boot. + menu "Start-up hooks" config ARCH_EARLY_INIT_R diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index b77ecc1781..6ef6616554 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -8,6 +8,7 @@ CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" +CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index f42b694ca7..2208bdb9be 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -8,6 +8,7 @@ CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" +CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 11796e5bdf..f6f05b2948 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS5=y +CONFIG_BOARD_TYPES=y CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2" CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=8 diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index cdb033ba78..184bb62c1c 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_EXYNOS=y CONFIG_SYS_TEXT_BASE=0x43e00000 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_ODROID=y +CONFIG_BOARD_TYPES=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=8 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/spring_defconfig b/configs/spring_defconfig index 5c5569acd2..c0084289d9 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_S5P=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y +CONFIG_SOUND_MAX98088=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y CONFIG_EXYNOS_SPI=y diff --git a/doc/driver-model/of-plat.txt b/doc/driver-model/of-plat.txt index 732bc34f06..0109ec56c3 100644 --- a/doc/driver-model/of-plat.txt +++ b/doc/driver-model/of-plat.txt @@ -64,17 +64,24 @@ strictly necessary. Notable problems include: normally also supports device tree it must use #ifdef to separate out this code, since the structures are only available in SPL. + - Correct relations between nodes are not implemented. This means that + parent/child relations (like bus device iteration) do not work yet. + Some phandles (those that are recognised as such) are converted into + a pointer to platform data. This pointer can potentially be used to + access the referenced device (by searching for the pointer value). + This feature is not yet implemented, however. + How it works ------------ -The feature is enabled by CONFIG SPL_OF_PLATDATA. This is only available -in SPL and should be tested with: +The feature is enabled by CONFIG OF_PLATDATA. This is only available in +SPL/TPL and should be tested with: - #if CONFIG_IS_ENABLED(SPL_OF_PLATDATA) + #if CONFIG_IS_ENABLED(OF_PLATDATA) A new tool called 'dtoc' converts a device tree file either into a set of -struct declarations, one for each compatible node, or a set of +struct declarations, one for each compatible node, and a set of U_BOOT_DEVICE() declarations along with the actual platform data for each device. As an example, consider this MMC node: @@ -156,6 +163,13 @@ This avoids the code overhead of converting the device tree data to platform data in the driver. The ofdata_to_platdata() method should therefore do nothing in such a driver. +Note that for the platform data to be matched with a driver, the 'name' +property of the U_BOOT_DEVICE() declaration has to match a driver declared +via U_BOOT_DRIVER(). This effectively means that a U_BOOT_DRIVER() with a +'name' corresponding to the devicetree 'compatible' string (after converting +it to a valid name for C) is needed, so a dedicated driver is required for +each 'compatible' string. + Where a node has multiple compatible strings, a #define is used to make them equivalent, e.g.: @@ -165,8 +179,8 @@ equivalent, e.g.: Converting of-platdata to a useful form --------------------------------------- -Of course it would be possible use the of-platdata directly in your driver -whenever configuration information is required. However this meands that the +Of course it would be possible to use the of-platdata directly in your driver +whenever configuration information is required. However this means that the driver will not be able to support device tree, since the of-platdata structure is not available when device tree is used. It would make no sense to use this structure if device tree were available, since the structure has @@ -282,11 +296,6 @@ prevents them being used inadvertently. All usage must be bracketed with The dt-platdata.c file contains the device declarations and is is built in spl/dt-platdata.c. -Some phandles (thsoe that are recognised as such) are converted into -points to platform data. This pointer can potentially be used to access the -referenced device (by searching for the pointer value). This feature is not -yet implemented, however. - The beginnings of a libfdt Python module are provided. So far this only implements a subset of the features. diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index f240cda5c0..55381edc98 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -68,4 +68,7 @@ int misc_set_enabled(struct udevice *dev, bool val) UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .post_bind = dm_scan_fdt_dev, +#endif }; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index b11c71cae7..826a39fad7 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -471,21 +471,21 @@ static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV) return 0; /* Disable PBIAS */ - ret = regulator_set_enable(priv->pbias_supply, false); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(priv->pbias_supply, false); + if (ret) return ret; /* Turn off IO voltage */ - ret = regulator_set_enable(mmc->vqmmc_supply, false); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false); + if (ret) return ret; /* Program a new IO voltage value */ ret = regulator_set_value(mmc->vqmmc_supply, uV); if (ret) return ret; /* Turn on IO voltage */ - ret = regulator_set_enable(mmc->vqmmc_supply, true); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true); + if (ret) return ret; /* Program PBIAS voltage*/ @@ -493,8 +493,8 @@ static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV) if (ret && ret != -ENOSYS) return ret; /* Enable PBIAS */ - ret = regulator_set_enable(priv->pbias_supply, true); - if (ret && ret != -ENOSYS) + ret = regulator_set_enable_if_allowed(priv->pbias_supply, true); + if (ret) return ret; return 0; diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 591a3bce08..9dd0b865eb 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -118,9 +118,6 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width) return s5p_sdhci_core_init(host); } -#if CONFIG_IS_ENABLED(OF_CONTROL) -struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS]; - static int do_sdhci_init(struct sdhci_host *host) { int dev_id, flag, ret; @@ -191,53 +188,6 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) return 0; } -static int process_nodes(const void *blob, int node_list[], int count) -{ - struct sdhci_host *host; - int i, node, ret; - int failed = 0; - - debug("%s: count = %d\n", __func__, count); - - /* build sdhci_host[] for each controller */ - for (i = 0; i < count; i++) { - node = node_list[i]; - if (node <= 0) - continue; - - host = &sdhci_host[i]; - - ret = sdhci_get_config(blob, node, host); - if (ret) { - printf("%s: failed to decode dev %d (%d)\n", __func__, i, ret); - failed++; - continue; - } - - ret = do_sdhci_init(host); - if (ret && ret != -ENODEV) { - printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret); - failed++; - } - } - - /* we only consider it an error when all nodes fail */ - return (failed == count ? -1 : 0); -} - -int exynos_mmc_init(const void *blob) -{ - int count; - int node_list[SDHCI_MAX_HOSTS]; - - count = fdtdec_find_aliases_for_id(blob, "mmc", - COMPAT_SAMSUNG_EXYNOS_MMC, node_list, - SDHCI_MAX_HOSTS); - - return process_nodes(blob, node_list, count); -} -#endif - #ifdef CONFIG_DM_MMC static int s5p_sdhci_probe(struct udevice *dev) { diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 39e46279d5..6f355b969a 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -113,11 +113,22 @@ int regulator_set_enable(struct udevice *dev, bool enable) uc_pdata = dev_get_uclass_platdata(dev); if (!enable && uc_pdata->always_on) - return 0; + return -EACCES; return ops->set_enable(dev, enable); } +int regulator_set_enable_if_allowed(struct udevice *dev, bool enable) +{ + int ret; + + ret = regulator_set_enable(dev, enable); + if (ret == -ENOSYS || ret == -EACCES) + return 0; + + return ret; +} + int regulator_get_mode(struct udevice *dev) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 22e379681d..40f4f7598a 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -32,7 +32,7 @@ config I2S_ROCKCHIP config I2S_SAMSUNG bool "Enable I2C support for Samsung SoCs" - depends on SOUND + depends on I2S help Samsung Exynos SoCs support an I2S interface for sending audio data to an audio codec. This option enables support for this, @@ -40,9 +40,17 @@ config I2S_SAMSUNG option provides an implementation for sound_init() and sound_play(). +config SOUND_MAX98088 + bool "Support Maxim max98088 audio codec" + depends on I2S + help + Enable the max98088 audio codec. This is connected via I2S for + audio data and I2C for codec control. At present it only works + with the Samsung I2S driver. + config SOUND_MAX98090 bool "Support Maxim max98090 audio codec" - depends on I2S_SAMSUNG + depends on I2S help Enable the max98090 audio codec. This is connected via I2S for audio data and I2C for codec control. At present it only works @@ -50,7 +58,7 @@ config SOUND_MAX98090 config SOUND_MAX98095 bool "Support Maxim max98095 audio codec" - depends on I2S_SAMSUNG + depends on I2S help Enable the max98095 audio codec. This is connected via I2S for audio data and I2C for codec control. At present it only works diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index d0bf51bab6..170e06ad53 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -12,5 +12,6 @@ obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o obj-$(CONFIG_I2S_ROCKCHIP) += rockchip_i2s.o rockchip_sound.o obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o +obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98095) += max98095.o maxim_codec.o diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c new file mode 100644 index 0000000000..332254d5aa --- /dev/null +++ b/drivers/sound/max98088.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * max98088.c -- MAX98088 ALSA SoC Audio driver + * + * Copyright 2010 Maxim Integrated Products + * + * Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org), + * following the changes made in max98095.c + */ + +#include <common.h> +#include <audio_codec.h> +#include <div64.h> +#include <dm.h> +#include <i2c.h> +#include <i2s.h> +#include <sound.h> +#include <asm/gpio.h> +#include "maxim_codec.h" +#include "max98088.h" + +/* codec mclk clock divider coefficients. Index 0 is reserved. */ +static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, + 44100, 48000, 88200, 96000}; + +/* + * codec mclk clock divider coefficients based on sampling rate + * + * @param rate sampling rate + * @param value address of indexvalue to be stored + * + * @return 0 for success or negative error code. + */ +static int rate_value(int rate, u8 *value) +{ + int i; + + for (i = 1; i < ARRAY_SIZE(rate_table); i++) { + if (rate_table[i] >= rate) { + *value = i; + return 0; + } + } + *value = 1; + + return -EINVAL; +} + +/* + * Sets hw params for max98088 + * + * @priv: max98088 information pointer + * @rate: Sampling rate + * @bits_per_sample: Bits per sample + * + * @return -EIO for error, 0 for success. + */ +int max98088_hw_params(struct maxim_priv *priv, unsigned int rate, + unsigned int bits_per_sample) +{ + int error; + u8 regval; + + switch (bits_per_sample) { + case 16: + error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT, + M98088_DAI_WS, 0); + break; + case 24: + error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT, + M98088_DAI_WS, M98088_DAI_WS); + break; + default: + debug("%s: Illegal bits per sample %d.\n", + __func__, bits_per_sample); + return -EINVAL; + } + + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0); + + if (rate_value(rate, ®val)) { + debug("%s: Failed to set sample rate to %d.\n", + __func__, rate); + return -EIO; + } + + error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE, + M98088_CLKMODE_MASK, regval << 4); + priv->rate = rate; + + /* Update sample rate mode */ + if (rate < 50000) + error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS, + M98088_DAI_DHF, 0); + else + error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS, + M98088_DAI_DHF, M98088_DAI_DHF); + + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, + M98088_SHDNRUN); + + if (error < 0) { + debug("%s: Error setting hardware params.\n", __func__); + return -EIO; + } + priv->rate = rate; + + return 0; +} + +/* + * Configures Audio interface system clock for the given frequency + * + * @priv: max98088 information + * @freq: Sampling frequency in Hz + * + * @return -EIO for error, 0 for success. + */ +int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq) +{ + int error = 0; + u8 pwr; + + /* Requested clock frequency is already setup */ + if (freq == priv->sysclk) + return 0; + + /* + * Setup clocks for slave mode, and using the PLL + * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) + * 0x02 (when master clk is 20MHz to 30MHz).. + */ + if (freq >= 10000000 && freq < 20000000) { + error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10); + } else if ((freq >= 20000000) && (freq < 30000000)) { + error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20); + } else { + debug("%s: Invalid master clock frequency\n", __func__); + return -EIO; + } + + error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr); + if (pwr & M98088_SHDNRUN) { + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, + M98088_SHDNRUN, 0); + error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, + M98088_SHDNRUN, M98088_SHDNRUN); + } + + debug("%s: Clock at %uHz\n", __func__, freq); + if (error < 0) + return -EIO; + + priv->sysclk = freq; + + return 0; +} + +/* + * Sets Max98090 I2S format + * + * @priv: max98088 information + * @fmt: i2S format - supports a subset of the options defined in i2s.h. + * + * @return -EIO for error, 0 for success. + */ +int max98088_set_fmt(struct maxim_priv *priv, int fmt) +{ + u8 reg15val; + u8 reg14val = 0; + int error = 0; + + if (fmt == priv->fmt) + return 0; + + priv->fmt = fmt; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* Slave mode PLL */ + error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI, + 0x80); + error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO, + 0x00); + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* Set to master mode */ + reg14val |= M98088_DAI_MAS; + break; + case SND_SOC_DAIFMT_CBS_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + default: + debug("%s: Clock mode unsupported\n", __func__); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + reg14val |= M98088_DAI_DLY; + break; + case SND_SOC_DAIFMT_LEFT_J: + break; + default: + debug("%s: Unrecognized format.\n", __func__); + return -EINVAL; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_NB_IF: + reg14val |= M98088_DAI_WCI; + break; + case SND_SOC_DAIFMT_IB_NF: + reg14val |= M98088_DAI_BCI; + break; + case SND_SOC_DAIFMT_IB_IF: + reg14val |= M98088_DAI_BCI | M98088_DAI_WCI; + break; + default: + debug("%s: Unrecognized inversion settings.\n", __func__); + return -EINVAL; + } + + error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT, + M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | + M98088_DAI_WCI, reg14val); + reg15val = M98088_DAI_BSEL64; + error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val); + + if (error < 0) { + debug("%s: Error setting i2s format.\n", __func__); + return -EIO; + } + + return 0; +} + +/* + * max98088_reset() - reset the audio codec + * + * @priv: max98088 information + * @return -EIO for error, 0 for success. + */ +static int max98088_reset(struct maxim_priv *priv) +{ + int ret, i; + u8 val; + + /* + * Reset to hardware default for registers, as there is not a soft + * reset hardware control register. + */ + for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) { + switch (i) { + case M98088_REG_BIAS_CNTL: + val = 0xf0; + break; + case M98088_REG_DAC_BIAS2: + val = 0x0f; + break; + default: + val = 0; + } + ret = maxim_i2c_write(priv, i, val); + if (ret < 0) { + debug("%s: Failed to reset: %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +/** + * max98088_device_init() - Initialise max98088 codec device + * + * @priv: max98088 information + * + * @return -EIO for error, 0 for success. + */ +static int max98088_device_init(struct maxim_priv *priv) +{ + unsigned char id; + int error = 0; + + /* reset the codec, the DSP core, and disable all interrupts */ + error = max98088_reset(priv); + if (error != 0) { + debug("Reset\n"); + return error; + } + + /* initialize private data */ + priv->sysclk = -1U; + priv->rate = -1U; + priv->fmt = -1U; + + error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id); + if (error < 0) { + debug("%s: Failure reading hardware revision: %d\n", + __func__, id); + return -EIO; + } + debug("%s: Hardware revision: %d\n", __func__, id); + + return 0; +} + +static int max98088_setup_interface(struct maxim_priv *priv) +{ + int error; + + /* Reading interrupt status to clear them */ + error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV); + error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00); + + /* + * initialize registers to hardware default configuring audio + * interface2 to DAI1 + */ + error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC, + M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR); + error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0); + error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F); + error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG, + M98088_S2NORMAL | M98088_SDATA); + + /* + * route DACL and DACR output to headphone and speakers + * Ordering: DACL, DACR, DACL, DACR + */ + error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1); + error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1); + error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1); + error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1); + + /* set volume: -12db */ + error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f); + error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f); + + /* set volume: -22db */ + error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d); + error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d); + + /* power enable */ + error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT, + M98088_HPLEN | M98088_HPREN | M98088_SPLEN | + M98088_SPREN | M98088_DALEN | M98088_DAREN); + if (error < 0) + return -EIO; + + return 0; +} + +static int max98088_do_init(struct maxim_priv *priv, int sampling_rate, + int mclk_freq, int bits_per_sample) +{ + int ret = 0; + + ret = max98088_setup_interface(priv); + if (ret < 0) { + debug("%s: max98088 setup interface failed\n", __func__); + return ret; + } + + ret = max98088_set_sysclk(priv, mclk_freq); + if (ret < 0) { + debug("%s: max98088 codec set sys clock failed\n", __func__); + return ret; + } + + ret = max98088_hw_params(priv, sampling_rate, bits_per_sample); + + if (ret == 0) { + ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS); + } + + return ret; +} + +static int max98088_set_params(struct udevice *dev, int interface, int rate, + int mclk_freq, int bits_per_sample, + uint channels) +{ + struct maxim_priv *priv = dev_get_priv(dev); + + return max98088_do_init(priv, rate, mclk_freq, bits_per_sample); +} + +static int max98088_probe(struct udevice *dev) +{ + struct maxim_priv *priv = dev_get_priv(dev); + int ret; + + priv->dev = dev; + ret = max98088_device_init(priv); + if (ret < 0) { + debug("%s: max98088 codec chip init failed\n", __func__); + return ret; + } + + return 0; +} + +static const struct audio_codec_ops max98088_ops = { + .set_params = max98088_set_params, +}; + +static const struct udevice_id max98088_ids[] = { + { .compatible = "maxim,max98088" }, + { } +}; + +U_BOOT_DRIVER(max98088) = { + .name = "max98088", + .id = UCLASS_AUDIO_CODEC, + .of_match = max98088_ids, + .probe = max98088_probe, + .ops = &max98088_ops, + .priv_auto_alloc_size = sizeof(struct maxim_priv), +}; diff --git a/drivers/sound/max98088.h b/drivers/sound/max98088.h new file mode 100644 index 0000000000..127d2bda30 --- /dev/null +++ b/drivers/sound/max98088.h @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * max98088.h -- MAX98088 ALSA SoC Audio driver + * + * Copyright 2010 Maxim Integrated Products + */ + +#ifndef _MAX98088_H +#define _MAX98088_H + +/* MAX98088 Registers Definition */ +#define M98088_REG_IRQ_STATUS 0x00 +#define M98088_REG_MIC_STATUS 0x01 +#define M98088_REG_JACK_STAUS 0x02 +#define M98088_REG_BATTERY_VOLTAGE 0x03 +#define M98088_REG_IRQ_ENABLE 0x0f +#define M98088_REG_SYS_CLK 0X10 +#define M98088_REG_DAI1_CLKMODE 0x11 +#define M98088_REG_DAI1_CLKCFG_HI 0x12 +#define M98088_REG_DAI1_CLKCFG_LO 0x13 +#define M98088_REG_DAI1_FORMAT 0x14 +#define M98088_REG_DAI1_CLOCK 0x15 +#define M98088_REG_DAI1_IOCFG 0x16 +#define M98088_REG_DAI1_TDM 0X17 +#define M98088_REG_DAI1_FILTERS 0x18 +#define M98088_REG_DAI2_CLKMODE 0x19 +#define M98088_REG_DAI2_CLKCFG_HI 0x1a +#define M98088_REG_DAI2_CLKCFG_LO 0x1b +#define M98088_REG_DAI2_FORMAT 0x1c +#define M98088_REG_DAI2_CLOCK 0x1d +#define M98088_REG_DAI2_IOCFG 0x1e +#define M98088_REG_DAI2_TDM 0X1f +#define M98088_REG_DAI2_FILTERS 0x20 +#define M98088_REG_SRC 0X21 +#define M98088_REG_MIX_DAC 0X22 +#define M98088_REG_MIX_ADC_LEFT 0x23 +#define M98088_REG_MIX_ADC_RIGHT 0x24 +#define M98088_REG_MIX_HP_LEFT 0x25 +#define M98088_REG_MIX_HP_RIGHT 0x26 +#define M98088_REG_MIX_HP_CNTL 0x27 +#define M98088_REG_MIX_REC_LEFT 0x28 +#define M98088_REG_MIX_REC_RIGHT 0x29 +#define M98088_REG_MIC_REC_CNTL 0x2a +#define M98088_REG_MIX_SPK_LEFT 0x2b +#define M98088_REG_MIX_SPK_RIGHT 0x2c +#define M98088_REG_MIX_SPK_CNTL 0x2d +#define M98088_REG_LVL_SIDETONE 0x2e +#define M98088_REG_LVL_DAI1_PLAY 0x2f +#define M98088_REG_LVL_DAI1_PLAY_EQ 0x30 +#define M98088_REG_LVL_DAI2_PLAY 0x31 +#define M98088_REG_LVL_DAI2_PLAY_EQ 0x32 +#define M98088_REG_LVL_ADC_L 0X33 +#define M98088_REG_LVL_ADC_R 0X34 +#define M98088_REG_LVL_MIC1 0X35 +#define M98088_REG_LVL_MIC2 0X36 +#define M98088_REG_LVL_INA 0X37 +#define M98088_REG_LVL_INB 0X38 +#define M98088_REG_LVL_HP_L 0X39 +#define M98088_REG_LVL_HP_R 0X3a +#define M98088_REG_LVL_REC_L 0X3b +#define M98088_REG_LVL_REC_R 0X3c +#define M98088_REG_LVL_SPK_L 0X3d +#define M98088_REG_LVL_SPK_R 0X3e +#define M98088_REG_MICAGC_CFG 0x3f +#define M98088_REG_MICAGC_THRESH 0x40 +#define M98088_REG_SPKDHP 0X41 +#define M98088_REG_SPKDHP_THRESH 0x42 +#define M98088_REG_SPKALC_COMP 0x43 +#define M98088_REG_PWRLMT_CFG 0x44 +#define M98088_REG_PWRLMT_TIME 0x45 +#define M98088_REG_THDLMT_CFG 0x46 +#define M98088_REG_CFG_AUDIO_IN 0x47 +#define M98088_REG_CFG_MIC 0X48 +#define M98088_REG_CFG_LEVEL 0X49 +#define M98088_REG_CFG_BYPASS 0x4a +#define M98088_REG_CFG_JACKDET 0x4b +#define M98088_REG_PWR_EN_IN 0X4c +#define M98088_REG_PWR_EN_OUT 0x4d +#define M98088_REG_BIAS_CNTL 0X4e +#define M98088_REG_DAC_BIAS1 0X4f +#define M98088_REG_DAC_BIAS2 0X50 +#define M98088_REG_PWR_SYS 0X51 +#define M98088_REG_DAI1_EQ_BASE 0x52 +#define M98088_REG_DAI2_EQ_BASE 0x84 +#define M98088_REG_DAI1_BIQUAD_BASE 0xb6 +#define M98088_REG_DAI2_BIQUAD_BASE 0xc0 +#define M98088_REG_REV_ID 0xff + +#define M98088_REG_CNT (0xff + 1) + +/* MAX98088 Registers Bit Fields */ + +/* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */ +#define M98088_CLKMODE_MASK 0xFF + +/* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */ +#define M98088_DAI_MAS BIT(7) +#define M98088_DAI_WCI BIT(6) +#define M98088_DAI_BCI BIT(5) +#define M98088_DAI_DLY BIT(4) +#define M98088_DAI_TDM BIT(2) +#define M98088_DAI_FSW BIT(1) +#define M98088_DAI_WS BIT(0) + +/* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */ +#define M98088_DAI_BSEL64 BIT(0) +#define M98088_DAI_OSR64 BIT(6) + +/* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */ +#define M98088_S1NORMAL BIT(6) +#define M98088_S2NORMAL (2 << 6) +#define M98088_SDATA (3 << 0) + +/* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */ +#define M98088_DAI_DHF BIT(3) + +/* M98088_REG_22_MIX_DAC */ +#define M98088_DAI1L_TO_DACL BIT(7) +#define M98088_DAI1R_TO_DACL BIT(6) +#define M98088_DAI2L_TO_DACL BIT(5) +#define M98088_DAI2R_TO_DACL BIT(4) +#define M98088_DAI1L_TO_DACR BIT(3) +#define M98088_DAI1R_TO_DACR BIT(2) +#define M98088_DAI2L_TO_DACR BIT(1) +#define M98088_DAI2R_TO_DACR BIT(0) + +/* M98088_REG_2A_MIC_REC_CNTL */ +#define M98088_REC_LINEMODE BIT(7) +#define M98088_REC_LINEMODE_MASK BIT(7) + +/* M98088_REG_2D_MIX_SPK_CNTL */ +#define M98088_MIX_SPKR_GAIN_MASK (3 << 2) +#define M98088_MIX_SPKR_GAIN_SHIFT 2 +#define M98088_MIX_SPKL_GAIN_MASK (3 << 0) +#define M98088_MIX_SPKL_GAIN_SHIFT 0 + +/* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */ +#define M98088_DAI_MUTE BIT(7) +#define M98088_DAI_MUTE_MASK BIT(7) +#define M98088_DAI_VOICE_GAIN_MASK (3 << 4) +#define M98088_DAI_ATTENUATION_MASK (0xf << 0) +#define M98088_DAI_ATTENUATION_SHIFT 0 + +/* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */ +#define M98088_MICPRE_MASK (3 << 5) +#define M98088_MICPRE_SHIFT 5 + +/* M98088_REG_3A_LVL_HP_R */ +#define M98088_HP_MUTE BIT(7) + +/* M98088_REG_3C_LVL_REC_R */ +#define M98088_REC_MUTE BIT(7) + +/* M98088_REG_3E_LVL_SPK_R */ +#define M98088_SP_MUTE BIT(7) + +/* M98088_REG_48_CFG_MIC */ +#define M98088_EXTMIC_MASK (3 << 0) +#define M98088_DIGMIC_L BIT(5) +#define M98088_DIGMIC_R BIT(4) + +/* M98088_REG_49_CFG_LEVEL */ +#define M98088_VSEN BIT(6) +#define M98088_ZDEN BIT(5) +#define M98088_EQ2EN BIT(1) +#define M98088_EQ1EN BIT(0) + +/* M98088_REG_4C_PWR_EN_IN */ +#define M98088_INAEN BIT(7) +#define M98088_INBEN BIT(6) +#define M98088_MBEN BIT(3) +#define M98088_ADLEN BIT(1) +#define M98088_ADREN BIT(0) + +/* M98088_REG_4D_PWR_EN_OUT */ +#define M98088_HPLEN BIT(7) +#define M98088_HPREN BIT(6) +#define M98088_HPEN (BIT(7) | BIT(6)) +#define M98088_SPLEN BIT(5) +#define M98088_SPREN BIT(4) +#define M98088_RECEN BIT(3) +#define M98088_DALEN BIT(1) +#define M98088_DAREN BIT(0) + +/* M98088_REG_51_PWR_SYS */ +#define M98088_SHDNRUN BIT(7) +#define M98088_PERFMODE BIT(3) +#define M98088_HPPLYBACK BIT(2) +#define M98088_PWRSV8K BIT(1) +#define M98088_PWRSV BIT(0) + +#endif diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c index 346ff5ffbe..5505c35166 100644 --- a/drivers/sound/max98090.c +++ b/drivers/sound/max98090.c @@ -13,10 +13,6 @@ #include <i2s.h> #include <sound.h> #include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/cpu.h> -#include <asm/arch/power.h> #include "maxim_codec.h" #include "max98090.h" @@ -240,9 +236,6 @@ int max98090_device_init(struct maxim_priv *priv) unsigned char id; int error = 0; - /* Enable codec clock */ - set_xclkout(); - /* reset the codec, the DSP core, and disable all interrupts */ error = max98090_reset(priv); if (error != 0) { diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index 99c0e996b4..9e08e96670 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -15,10 +15,6 @@ #include <i2c.h> #include <sound.h> #include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/cpu.h> -#include <asm/arch/power.h> #include "i2s.h" #include "max98095.h" @@ -306,9 +302,6 @@ static int max98095_device_init(struct maxim_priv *priv) unsigned char id; int ret; - /* Enable codec clock */ - set_xclkout(); - /* reset the codec, the DSP core, and disable all interrupts */ ret = max98095_reset(priv); if (ret != 0) { diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c index dcaf081988..5480dce108 100644 --- a/drivers/sound/maxim_codec.c +++ b/drivers/sound/maxim_codec.c @@ -12,9 +12,6 @@ #include <sound.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clk.h> -#include <asm/arch/cpu.h> -#include <asm/arch/power.h> #include "maxim_codec.h" /* diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c index c19e08e7e3..104584073a 100644 --- a/drivers/sound/samsung-i2s.c +++ b/drivers/sound/samsung-i2s.c @@ -24,7 +24,7 @@ /* * Sets the frame size for I2S LR clock * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param rfs Frame Size */ static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs) @@ -54,7 +54,7 @@ static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs) /* * Sets the i2s transfer control * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param on 1 enable tx , 0 disable tx transfer */ static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) @@ -77,7 +77,7 @@ static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) /* * set the bit clock frame size (in multiples of LRCLK) * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param bfs bit Frame Size */ static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) @@ -108,7 +108,7 @@ static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) /* * flushes the i2stx fifo * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param flush Tx fifo flush command (0x00 - do not flush * 0x80 - flush tx fifo) */ @@ -122,7 +122,7 @@ static void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush) /* * Set System Clock direction * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param dir Clock direction * * @return int value 0 for success, -1 in case of error @@ -145,7 +145,7 @@ static int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir) * Sets I2S Clcok format * * @param fmt i2s clock properties - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * * @return int value 0 for success, -1 in case of error */ @@ -222,7 +222,7 @@ static int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) * Sets the sample width in bits * * @param blc samplewidth (size of sample in bits) - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * * @return int value 0 for success, -1 in case of error */ @@ -294,7 +294,7 @@ int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, return 0; } -int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) +static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) { int ret; struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address; diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c index 1d711c8732..b6952675bd 100644 --- a/drivers/sound/samsung_sound.c +++ b/drivers/sound/samsung_sound.c @@ -10,6 +10,7 @@ #include <i2s.h> #include <sound.h> #include <asm/gpio.h> +#include <asm/arch/power.h> static int samsung_sound_setup(struct udevice *dev) { @@ -79,6 +80,9 @@ static int samsung_sound_probe(struct udevice *dev) debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name, uc_priv->codec->name, uc_priv->i2s->name); + /* Enable codec clock */ + set_xclkout(); + return 0; } @@ -89,7 +93,7 @@ static const struct sound_ops samsung_sound_ops = { static const struct udevice_id samsung_sound_ids[] = { { .compatible = "google,snow-audio-max98095" }, - { .compatible = "google,spring-audio-max98095" }, + { .compatible = "google,spring-audio-max98088" }, { .compatible = "samsung,smdk5420-audio-wm8994" }, { .compatible = "google,peach-audio-max98090" }, { } diff --git a/dts/Kconfig b/dts/Kconfig index 8917f42444..3e85914d11 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -265,8 +265,7 @@ config SPL_OF_PLATDATA This option works by generating C structure declarations for each compatible string, then adding platform data and U_BOOT_DEVICE - declarations for each node. See README.platdata for more - information. + declarations for each node. See of-plat.txt for more information. config TPL_OF_PLATDATA bool "Generate platform data for use in TPL" @@ -287,8 +286,7 @@ config TPL_OF_PLATDATA This option works by generating C structure declarations for each compatible string, then adding platform data and U_BOOT_DEVICE - declarations for each node. See README.platdata for more - information. + declarations for each node. See of-plat.txt for more information. endmenu diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index e128d1c08b..0f4d78a594 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -32,11 +32,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* - * This board might be of different versions so handle it - */ -#define CONFIG_BOARD_TYPES - -/* * NAND Flash configuration */ #define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 9af1d12701..7735cc1720 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -33,11 +33,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* - * This board might be of different versions so handle it - */ -#define CONFIG_BOARD_TYPES - -/* * UART configuration */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/odroid.h b/include/configs/odroid.h index c3520bb15f..b8809c8dcc 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -186,7 +186,6 @@ * TODO: Add Odroid X support */ #define CONFIG_MISC_COMMON -#define CONFIG_BOARD_TYPES #undef CONFIG_REVISION_TAG diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 0337c26475..f178549a72 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -87,7 +87,6 @@ /* Set soc_rev, soc_id, board_rev, boardname, fdtfile */ #define CONFIG_ODROID_REV_AIN 9 #define CONFIG_REVISION_TAG -#define CONFIG_BOARD_TYPES #undef CONFIG_SYS_BOARD #define CONFIG_SYS_BOARD "odroid" diff --git a/include/fdtdec.h b/include/fdtdec.h index f1bcbf837f..2a8ad96026 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -133,21 +133,14 @@ enum fdt_compat_id { /* Tegra210 XUSB pad controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ - COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ - COMPAT_SAMSUNG_EXYNOS5_SOUND, /* Exynos Sound */ - COMPAT_WOLFSON_WM8994_CODEC, /* Wolfson WM8994 Sound Codec */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */ COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ - COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ - COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */ - COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_INTEL_MICROCODE, /* Intel microcode update */ - COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */ COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */ diff --git a/include/i2s.h b/include/i2s.h index 28f6184811..7760aab7c4 100644 --- a/include/i2s.h +++ b/include/i2s.h @@ -78,7 +78,7 @@ struct i2s_reg { /* This structure stores the i2s related information */ struct i2s_uc_priv { unsigned int rfs; /* LR clock frame size */ - unsigned int bfs; /* Bit slock frame size */ + unsigned int bfs; /* Bit clock frame size */ unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ unsigned int samplingrate; /* sampling rate */ unsigned int bitspersample; /* bits per sample */ @@ -123,13 +123,4 @@ int i2s_tx_data(struct udevice *dev, void *data, uint data_size); int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, uint data_size); -/* - * Initialise i2s transmiter - * - * @param pi2s_tx pointer of i2s transmitter parameter structure. - * - * @return int value 0 for success, -1 in case of error - */ -int i2s_tx_init(struct i2s_uc_priv *pi2s_tx); - #endif /* __I2S_H__ */ diff --git a/include/power/regulator.h b/include/power/regulator.h index 5318ab3ace..314160a894 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -304,6 +304,17 @@ int regulator_get_enable(struct udevice *dev); int regulator_set_enable(struct udevice *dev, bool enable); /** + * regulator_set_enable_if_allowed: set regulator enable state if allowed by + * regulator + * + * @dev - pointer to the regulator device + * @enable - set true or false + * @return - 0 on success or if enabling is not supported + * -errno val if fails. + */ +int regulator_set_enable_if_allowed(struct udevice *dev, bool enable); + +/** * regulator_get_mode: get active operation mode id of a given regulator * * @dev - pointer to the regulator device diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 0f957dc367..017560c256 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -32,9 +32,7 @@ void draw_logo(void); char *get_dfu_alt_system(char *interface, char *devstr); char *get_dfu_alt_boot(char *interface, char *devstr); #endif -#ifdef CONFIG_BOARD_TYPES void set_board_type(void); const char *get_board_type(void); -#endif #endif /* __SAMSUNG_MISC_COMMON_H__ */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 18663ce6bd..fd0ad6ea84 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -40,21 +40,14 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"), - COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"), - COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"), - COMPAT(WOLFSON_WM8994_CODEC, "wolfson,wm8994-codec"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"), COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"), COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"), - COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"), COMPAT(GENERIC_SPI_FLASH, "spi-flash"), - COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"), - COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"), COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"), COMPAT(INTEL_MICROCODE, "intel,microcode"), - COMPAT(AMS_AS3722, "ams,as3722"), COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"), COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"), COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"), diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 38c7f01fad..2b3572568b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -129,7 +129,6 @@ CONFIG_BOARD_POSTCLK_INIT CONFIG_BOARD_REVISION_TAG CONFIG_BOARD_SIZE_LIMIT CONFIG_BOARD_TAURUS -CONFIG_BOARD_TYPES CONFIG_BOOGER CONFIG_BOOTBLOCK CONFIG_BOOTFILE diff --git a/test/dm/regulator.c b/test/dm/regulator.c index 5d11e946b2..e510539542 100644 --- a/test/dm/regulator.c +++ b/test/dm/regulator.c @@ -175,6 +175,27 @@ static int dm_test_power_regulator_set_get_enable(struct unit_test_state *uts) } DM_TEST(dm_test_power_regulator_set_get_enable, DM_TESTF_SCAN_FDT); +/* Test regulator set and get enable if allowed method */ +static +int dm_test_power_regulator_set_enable_if_allowed(struct unit_test_state *uts) +{ + const char *platname; + struct udevice *dev, *dev_autoset; + bool val_set = false; + + /* Get BUCK1 - always on regulator */ + platname = regulator_names[BUCK1][PLATNAME]; + ut_assertok(regulator_autoset_by_name(platname, &dev_autoset)); + ut_assertok(regulator_get_by_platname(platname, &dev)); + + /* Try disabling always-on regulator */ + ut_assertok(regulator_set_enable_if_allowed(dev, val_set)); + ut_asserteq(regulator_get_enable(dev), !val_set); + + return 0; +} +DM_TEST(dm_test_power_regulator_set_enable_if_allowed, DM_TESTF_SCAN_FDT); + /* Test regulator set and get mode method */ static int dm_test_power_regulator_set_get_mode(struct unit_test_state *uts) { diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 6b156f152d..8a9d47cd5e 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -322,6 +322,9 @@ class BuilderThread(threading.Thread): # Write out the image and function size information and an objdump env = result.toolchain.MakeEnvironment(self.builder.full_path) + with open(os.path.join(build_dir, 'env'), 'w') as fd: + for var in sorted(env.keys()): + print >>fd, '%s="%s"' % (var, env[var]) lines = [] for fname in ['u-boot', 'spl/u-boot-spl']: cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname] diff --git a/tools/buildman/control.py b/tools/buildman/control.py index 27916d3c35..fcf531c5f1 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -99,7 +99,7 @@ def CheckOutputDir(output_dir): cwd_path = os.path.realpath('.') while True: if os.path.realpath(path) == cwd_path: - Print("Cannot use output directory '%s' since it is within the current directtory '%s'" % + Print("Cannot use output directory '%s' since it is within the current directory '%s'" % (path, cwd_path)) sys.exit(1) parent = os.path.dirname(path) |