diff options
| -rw-r--r-- | cpu/arm_cortexa8/omap3/mem.c | 2 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/omap3/sys_info.c | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap3/mem.h | 11 |
3 files changed, 4 insertions, 11 deletions
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 8b8cd6d617..2c2d4f7b4b 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -161,7 +161,7 @@ void do_sdrc_init(u32 cs, u32 early) writel(0, &sdrc_base->sysconfig); /* setup sdrc to ball mux */ - writel(SDP_SDRC_SHARING, &sdrc_base->sharing); + writel(SDRC_SHARING, &sdrc_base->sharing); /* Disable Power Down of CKE cuz of 1 CKE on combo part */ writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power); diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 31b20033cc..08fb32eaae 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -109,7 +109,7 @@ u32 get_cpu_rev(void) ****************************************************/ u32 is_mem_sdr(void) { - if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR) + if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) return 1; return 0; } diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h index 5b9ac753e8..5496a618c6 100644 --- a/include/asm-arm/arch-omap3/mem.h +++ b/include/asm-arm/arch-omap3/mem.h @@ -40,11 +40,8 @@ enum { #define EARLY_INIT 1 /* Slower full frequency range default timings for x32 operation*/ -#define SDP_SDRC_SHARING 0x00000100 -#define SDP_SDRC_MR_0_SDR 0x00000031 - -/* optimized timings good for current shipping parts */ -#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDRC_SHARING 0x00000100 +#define SDRC_MR_0_SDR 0x00000031 #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 @@ -91,10 +88,6 @@ enum { #define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ (TXP_165 << 8) | (TWTR_165 << 16)) -#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 -#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz - /* * GPMC settings - * Definitions is as per the following format |