diff options
543 files changed, 8744 insertions, 4835 deletions
@@ -4,39 +4,47 @@ # 1) Generate generic-asm-offsets.h # 2) Generate asm-offsets.h -##### -# 1) Generate generic-asm-offsets.h - -generic-offsets-file := include/generated/generic-asm-offsets.h - -always := $(generic-offsets-file) -targets := $(generic-offsets-file) lib/asm-offsets.s +# Default sed regexp - multiline due to syntax constraints +define sed-y + "s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \ + /^->/{s:->#\(.*\):/* \1 */:; \ + s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ + s:->::; p;}" +endef -quiet_cmd_generic-offsets = GEN $@ -define cmd_generic-offsets +# Use filechk to avoid rebuilds when a header changes, but the resulting file +# does not +define filechk_offsets (set -e; \ - echo "#ifndef __GENERIC_ASM_OFFSETS_H__"; \ - echo "#define __GENERIC_ASM_OFFSETS_H__"; \ + echo "#ifndef $2"; \ + echo "#define $2"; \ echo "/*"; \ echo " * DO NOT MODIFY."; \ echo " *"; \ echo " * This file was generated by Kbuild"; \ - echo " *"; \ echo " */"; \ echo ""; \ - sed -ne $(sed-y) $<; \ + sed -ne $(sed-y); \ echo ""; \ - echo "#endif" ) > $@ + echo "#endif" ) endef +##### +# 1) Generate generic-asm-offsets.h + +generic-offsets-file := include/generated/generic-asm-offsets.h + +always := $(generic-offsets-file) +targets := $(generic-offsets-file) lib/asm-offsets.s + # We use internal kbuild rules to avoid the "is up to date" message from make lib/asm-offsets.s: lib/asm-offsets.c FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cc_s_c) -$(obj)/$(generic-offsets-file): lib/asm-offsets.s Kbuild - $(Q)mkdir -p $(dir $@) - $(call cmd,generic-offsets) +$(obj)/$(generic-offsets-file): lib/asm-offsets.s FORCE + $(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__) ##### # 2) Generate asm-offsets.h @@ -50,39 +58,12 @@ always += $(offsets-file) targets += $(offsets-file) targets += arch/$(ARCH)/lib/asm-offsets.s - -# Default sed regexp - multiline due to syntax constraints -define sed-y - "s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \ - /^->/{s:->#\(.*\):/* \1 */:; \ - s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \ - s:->::; p;}" -endef - CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY -quiet_cmd_offsets = GEN $@ -define cmd_offsets - (set -e; \ - echo "#ifndef __ASM_OFFSETS_H__"; \ - echo "#define __ASM_OFFSETS_H__"; \ - echo "/*"; \ - echo " * DO NOT MODIFY."; \ - echo " *"; \ - echo " * This file was generated by Kbuild"; \ - echo " *"; \ - echo " */"; \ - echo ""; \ - sed -ne $(sed-y) $<; \ - echo ""; \ - echo "#endif" ) > $@ -endef - # We use internal kbuild rules to avoid the "is up to date" message from make arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cc_s_c) -$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s Kbuild - $(call cmd,offsets) +$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s FORCE + $(call filechk,offsets,__ASM_OFFSETS_H__) @@ -54,7 +54,7 @@ config CC_OPTIMIZE_FOR_SIZE config SYS_MALLOC_F bool "Enable malloc() pool before relocation" - default 0x400 + default y if DM help Before relocation memory is very limited on many platforms. Still, we can provide a small malloc() pool if needed. Driver model in @@ -184,7 +184,7 @@ config SYS_TEXT_BASE TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture config SYS_CLK_FREQ - depends on ARC + depends on ARC || ARCH_SUNXI int "CPU clock frequency" help TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture diff --git a/MAINTAINERS b/MAINTAINERS index 26780f406e..26d0d27479 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -151,10 +151,10 @@ ARM TI M: Tom Rini <trini@konsulko.com> S: Maintained T: git git://git.denx.de/u-boot-ti.git -F: arch/arm/cpu/arm926ejs/davinci/ +F: arch/arm/mach-davinci/ +F: arch/arm/mach-keystone/ F: arch/arm/cpu/arm926ejs/omap/ F: arch/arm/cpu/armv7/omap*/ -F: arch/arm/include/asm/arch-davinci/ F: arch/arm/include/asm/arch-omap*/ F: arch/arm/include/asm/ti-common/ @@ -551,13 +551,7 @@ get_target_maintainers() { get_target_arch() { local target=$1 - # Automatic mode - local line=`awk '\$7 == "'"$target"'" { print \$0 }' boards.cfg` - - if [ -z "${line}" ] ; then echo "" ; return ; fi - - set ${line} - echo "$2" + awk '$7 == "'$target'" { print $2 }' boards.cfg } list_target() { @@ -1,7 +1,7 @@ VERSION = 2015 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* @@ -469,10 +469,10 @@ KBUILD_DEFCONFIG := sandbox_defconfig export KBUILD_DEFCONFIG KBUILD_KCONFIG config: scripts_basic outputmakefile FORCE - +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@ + $(Q)$(MAKE) $(build)=scripts/kconfig $@ %config: scripts_basic outputmakefile FORCE - +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@ + $(Q)$(MAKE) $(build)=scripts/kconfig $@ else # =========================================================================== @@ -496,6 +496,15 @@ $(KCONFIG_CONFIG) include/config/auto.conf.cmd: ; # we execute the config step to be sure to catch updated Kconfig files include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd $(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig + @# If the following part fails, include/config/auto.conf should be + @# deleted so "make silentoldconfig" will be re-run on the next build. + $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.autoconf || \ + { rm -f include/config/auto.conf; false; } + @# include/config.h has been updated after "make silentoldconfig". + @# We need to touch include/config/auto.conf so it gets newer + @# than include/config.h. + @# Otherwise, 'make silentoldconfig' would be invoked twice. + $(Q)touch include/config/auto.conf -include include/autoconf.mk -include include/autoconf.mk.dep @@ -504,12 +513,16 @@ include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd # is up-to-date. When we switch to a different board configuration, old CONFIG # macros are still remaining in include/config/auto.conf. Without the following # gimmick, wrong config.mk would be included leading nasty warnings/errors. -autoconf_is_current := $(if $(wildcard $(KCONFIG_CONFIG)),$(shell find . \ - -path ./include/config/auto.conf -newer $(KCONFIG_CONFIG))) -ifneq ($(autoconf_is_current),) +ifneq ($(wildcard $(KCONFIG_CONFIG)),) +ifneq ($(wildcard include/config/auto.conf),) +autoconf_is_old := $(shell find . -path ./$(KCONFIG_CONFIG) -newer \ + include/config/auto.conf) +ifeq ($(autoconf_is_old),) include $(srctree)/config.mk include $(srctree)/arch/$(ARCH)/Makefile endif +endif +endif # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use # that (or fail if absent). Otherwise, search for a linker script in a @@ -896,6 +909,26 @@ OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) + +lpc32xx-spl.img: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-0.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) + +lpc32xx-boot-1.bin: lpc32xx-spl.img + $(call if_changed,objcopy) + +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img + $(call if_changed,cat) + +CLEAN_FILES += lpc32xx-* + OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ --pad-to=$(CONFIG_TPL_PAD_TO) tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE @@ -1154,7 +1187,7 @@ prepare2: prepare3 outputmakefile prepare1: prepare2 $(version_h) $(timestamp_h) \ include/config/auto.conf -ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) +ifeq ($(CONFIG_HAVE_GENERIC_BOARD),) ifeq ($(CONFIG_SYS_GENERIC_BOARD),y) @echo >&2 " Your architecture does not support generic board." @echo >&2 " Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file." @@ -3483,9 +3483,6 @@ FIT uImage format: Adds the MTD partitioning infrastructure from the Linux kernel. Needed for UBI support. - CONFIG_MTD_NAND_VERIFY_WRITE - verify if the written data is correct reread. - - UBI support CONFIG_CMD_UBI @@ -3610,6 +3607,16 @@ FIT uImage format: CONFIG_SPL_STACK Adress of the start of the stack SPL will use + CONFIG_SPL_PANIC_ON_RAW_IMAGE + When defined, SPL will panic() if the image it has + loaded does not have a signature. + Defining this is useful when code which loads images + in SPL cannot guarantee that absolutely all read errors + will be caught. + An example is the LPC32XX MLC NAND driver, which will + consider that a completely unreadable NAND block is bad, + and thus should be skipped silently. + CONFIG_SPL_RELOC_STACK Adress of the start of the stack SPL will use after relocation. If unspecified, this is equal to @@ -4190,9 +4197,9 @@ Configuration Settings: to this new framework over time. Defining this will disable the arch/foo/lib/board.c file and use common/board_f.c and common/board_r.c instead. To use this option your architecture - must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in - its config.mk file). If you find problems enabling this option on - your board please report the problem and send patches! + must support it (i.e. must select HAVE_GENERIC_BOARD in arch/Kconfig). + If you find problems enabling this option on your board please report + the problem and send patches! - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) This is set by OMAP boards for the max time that reset should diff --git a/arch/Kconfig b/arch/Kconfig index 3d419bca3e..2ca530525e 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1,3 +1,10 @@ +config HAVE_GENERIC_BOARD + bool + +config SYS_GENERIC_BOARD + bool + depends on HAVE_GENERIC_BOARD + choice prompt "Architecture select" default SANDBOX @@ -5,34 +12,49 @@ choice config ARC bool "ARC architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD + select SUPPORT_OF_CONTROL config ARM bool "ARM architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD select SUPPORT_OF_CONTROL config AVR32 bool "AVR32 architecture" + select HAVE_GENERIC_BOARD config BLACKFIN bool "Blackfin architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config M68K bool "M68000 architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config MICROBLAZE bool "MicroBlaze architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config MIPS bool "MIPS architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config NDS32 bool "NDS32 architecture" config NIOS2 bool "Nios II architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config OPENRISC bool "OpenRISC architecture" @@ -40,10 +62,13 @@ config OPENRISC config PPC bool "PowerPC architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD select SUPPORT_OF_CONTROL config SANDBOX bool "Sandbox" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config SH @@ -56,6 +81,8 @@ config SPARC config X86 bool "x86 architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL endchoice diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 24f5c02c76..c044ad4de6 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -123,7 +123,7 @@ config ARC_CACHE_LINE_SHIFT int "Cache Line Length (as power of 2)" range 5 7 default "6" - depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF + depends on !SYS_DCACHE_OFF || !SYS_ICACHE_OFF help Starting with ARC700 4.9, Cache line length is configurable, This option specifies "N", with Line-len = 2 power N @@ -133,6 +133,14 @@ config ARC_CACHE_LINE_SHIFT choice prompt "Target select" +config TARGET_DUMMY + bool "Dummy target" + help + Please select one of real target boards below! + This target is only meant to force "makedefconfig" to put + TARGET_xxx in defconfig even this is the first target from the list + below. + config TARGET_TB100 bool "Support tb100" diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 4fcd4076c4..04c034b637 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -57,6 +57,3 @@ LDFLAGS_FINAL += -pie # Load address for standalone apps CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 - -# Support generic board on ARC -__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/arc/cpu/arcv1/Makefile b/arch/arc/cpu/arcv1/Makefile index 3704ebeeae..6d17ab2886 100644 --- a/arch/arc/cpu/arcv1/Makefile +++ b/arch/arc/cpu/arcv1/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += start.o +obj-y += ivt.o diff --git a/arch/arc/cpu/arcv1/ivt.S b/arch/arc/cpu/arcv1/ivt.S new file mode 100644 index 0000000000..7df47a2127 --- /dev/null +++ b/arch/arc/cpu/arcv1/ivt.S @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.section .ivt, "ax",@progbits +.align 4 +_ivt: + /* Critical system events */ + j _start /* 0 - 0x000 */ + j memory_error /* 1 - 0x008 */ + j instruction_error /* 2 - 0x010 */ + + /* Device interrupts */ +.rept 29 + j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.endr + /* Exceptions */ + j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ + j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ + j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ + j EV_TLBProtV /* 0x118, Protection Violation (0x23) + or Misaligned Access */ + j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ + j EV_Trap /* 0x128, Trap exception (0x25) */ + j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ diff --git a/arch/arc/cpu/arcv1/start.S b/arch/arc/cpu/arcv1/start.S deleted file mode 100644 index 01cfba4933..0000000000 --- a/arch/arc/cpu/arcv1/start.S +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <asm/arcregs.h> - -/* - * Note on the LD/ST addressing modes with address register write-back - * - * LD.a same as LD.aw - * - * LD.a reg1, [reg2, x] => Pre Incr - * Eff Addr for load = [reg2 + x] - * - * LD.ab reg1, [reg2, x] => Post Incr - * Eff Addr for load = [reg2] - */ - -.macro PUSH reg - st.a \reg, [%sp, -4] -.endm - -.macro PUSHAX aux - lr %r9, [\aux] - PUSH %r9 -.endm - -.macro SAVE_R1_TO_R24 - PUSH %r1 - PUSH %r2 - PUSH %r3 - PUSH %r4 - PUSH %r5 - PUSH %r6 - PUSH %r7 - PUSH %r8 - PUSH %r9 - PUSH %r10 - PUSH %r11 - PUSH %r12 - PUSH %r13 - PUSH %r14 - PUSH %r15 - PUSH %r16 - PUSH %r17 - PUSH %r18 - PUSH %r19 - PUSH %r20 - PUSH %r21 - PUSH %r22 - PUSH %r23 - PUSH %r24 -.endm - -.macro SAVE_ALL_SYS - /* saving %r0 to reg->r0 in advance since we read %ecr into it */ - st %r0, [%sp, -8] - lr %r0, [%ecr] /* all stack addressing is manual so far */ - st %r0, [%sp] - st %sp, [%sp, -4] - /* now move %sp to reg->r0 position so we can do "push" automatically */ - sub %sp, %sp, 8 - - SAVE_R1_TO_R24 - PUSH %r25 - PUSH %gp - PUSH %fp - PUSH %blink - PUSHAX %eret - PUSHAX %erstatus - PUSH %lp_count - PUSHAX %lp_end - PUSHAX %lp_start - PUSHAX %erbta -.endm - -.macro SAVE_EXCEPTION_SOURCE -#ifdef CONFIG_MMU - /* If MMU exists exception faulting address is loaded in EFA reg */ - lr %r0, [%efa] -#else - /* Otherwise in ERET (exception return) reg */ - lr %r0, [%eret] -#endif -.endm - -.section .ivt, "ax",@progbits -.align 4 -_ivt: - /* Critical system events */ - j _start /* 0 - 0x000 */ - j memory_error /* 1 - 0x008 */ - j instruction_error /* 2 - 0x010 */ - - /* Device interrupts */ -.rept 29 - j interrupt_handler /* 3:31 - 0x018:0xF8 */ -.endr - /* Exceptions */ - j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ - j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ - j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ - j EV_TLBProtV /* 0x118, Protection Violation (0x23) - or Misaligned Access */ - j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ - j EV_Trap /* 0x128, Trap exception (0x25) */ - j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ - -.text -.globl _start -_start: - /* Setup interrupt vector base that matches "__text_start" */ - sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] - - /* Setup stack pointer */ - mov %sp, CONFIG_SYS_INIT_SP_ADDR - mov %fp, %sp - - /* Clear bss */ - mov %r0, __bss_start - mov %r1, __bss_end - -clear_bss: - st.ab 0, [%r0, 4] - brlt %r0, %r1, clear_bss - - /* Zero the one and only argument of "board_init_f" */ - mov_s %r0, 0 - j board_init_f - -memory_error: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_memory_error - -instruction_error: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_instruction_error - -interrupt_handler: - /* Todo - save and restore CPU context when interrupts will be in use */ - bl do_interrupt_handler - rtie - -EV_MachineCheck: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_machine_check_fault - -EV_TLBMissI: - SAVE_ALL_SYS - mov %r0, %sp - j do_itlb_miss - -EV_TLBMissD: - SAVE_ALL_SYS - mov %r0, %sp - j do_dtlb_miss - -EV_TLBProtV: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_tlb_prot_violation - -EV_PrivilegeV: - SAVE_ALL_SYS - mov %r0, %sp - j do_privilege_violation - -EV_Trap: - SAVE_ALL_SYS - mov %r0, %sp - j do_trap - -EV_Extension: - SAVE_ALL_SYS - mov %r0, %sp - j do_extension - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r0 = start_addr_sp - * r1 = new__gd - * r2 = relocaddr - */ -.align 4 -.globl relocate_code -relocate_code: - /* - * r0-r12 might be clobbered by C functions - * so we use r13-r16 for storage here - */ - mov %r13, %r0 /* save addr_sp */ - mov %r14, %r1 /* save addr of gd */ - mov %r15, %r2 /* save addr of destination */ - - mov %r16, %r2 /* %r9 - relocation offset */ - sub %r16, %r16, __image_copy_start - -/* Set up the stack */ -stack_setup: - mov %sp, %r13 - mov %fp, %sp - -/* Check if monitor is loaded right in place for relocation */ - mov %r0, __image_copy_start - cmp %r0, %r15 /* skip relocation if code loaded */ - bz do_board_init_r /* in target location already */ - -/* Copy data (__image_copy_start - __image_copy_end) to new location */ - mov %r1, %r15 - mov %r2, __image_copy_end - sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */ - asr %r2, %r2, 2 /* r3 <- amount of words to copy */ - mov %lp_count, %r2 - lp copy_end - ld.ab %r2,[%r0,4] - st.ab %r2,[%r1,4] -copy_end: - -/* Fix relocations related issues */ - bl do_elf_reloc_fixups -#ifndef CONFIG_SYS_ICACHE_OFF - bl invalidate_icache_all -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - bl flush_dcache_all -#endif - -/* Update position of intterupt vector table */ - lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */ - add %r0, %r0, %r16 /* Update address */ - sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */ - -do_board_init_r: -/* Prepare for exection of "board_init_r" in relocated monitor */ - mov %r2, board_init_r /* old address of "board_init_r()" */ - add %r2, %r2, %r16 /* new address of "board_init_r()" */ - mov %r0, %r14 /* 1-st parameter: gd_t */ - mov %r1, %r15 /* 2-nd parameter: dest_addr */ - j [%r2] diff --git a/arch/arc/cpu/arcv2/Makefile b/arch/arc/cpu/arcv2/Makefile index cc69e5a17e..e338a0ae56 100644 --- a/arch/arc/cpu/arcv2/Makefile +++ b/arch/arc/cpu/arcv2/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += start.o +obj-y += ivt.o diff --git a/arch/arc/cpu/arcv2/ivt.S b/arch/arc/cpu/arcv2/ivt.S new file mode 100644 index 0000000000..d110b5bba5 --- /dev/null +++ b/arch/arc/cpu/arcv2/ivt.S @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.section .ivt, "a",@progbits +.align 4 + /* Critical system events */ +.word _start /* 0 - 0x000 */ +.word memory_error /* 1 - 0x008 */ +.word instruction_error /* 2 - 0x010 */ + + /* Exceptions */ +.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ +.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ +.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ +.word EV_TLBProtV /* 0x118, Protection Violation (0x23) + or Misaligned Access */ +.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ +.word EV_Trap /* 0x128, Trap exception (0x25) */ +.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ + + /* Device interrupts */ +.rept 29 + j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.endr diff --git a/arch/arc/cpu/arcv2/start.S b/arch/arc/cpu/arcv2/start.S deleted file mode 100644 index 3ce689675f..0000000000 --- a/arch/arc/cpu/arcv2/start.S +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <config.h> -#include <asm/arcregs.h> - -/* - * Note on the LD/ST addressing modes with address register write-back - * - * LD.a same as LD.aw - * - * LD.a reg1, [reg2, x] => Pre Incr - * Eff Addr for load = [reg2 + x] - * - * LD.ab reg1, [reg2, x] => Post Incr - * Eff Addr for load = [reg2] - */ - -.macro PUSH reg - st.a \reg, [%sp, -4] -.endm - -.macro PUSHAX aux - lr %r9, [\aux] - PUSH %r9 -.endm - -.macro SAVE_R1_TO_R24 - PUSH %r1 - PUSH %r2 - PUSH %r3 - PUSH %r4 - PUSH %r5 - PUSH %r6 - PUSH %r7 - PUSH %r8 - PUSH %r9 - PUSH %r10 - PUSH %r11 - PUSH %r12 - PUSH %r13 - PUSH %r14 - PUSH %r15 - PUSH %r16 - PUSH %r17 - PUSH %r18 - PUSH %r19 - PUSH %r20 - PUSH %r21 - PUSH %r22 - PUSH %r23 - PUSH %r24 -.endm - -.macro SAVE_ALL_SYS - /* saving %r0 to reg->r0 in advance since weread %ecr into it */ - st %r0, [%sp, -8] - lr %r0, [%ecr] /* all stack addressing is manual so far */ - st %r0, [%sp] - st %sp, [%sp, -4] - /* now move %sp to reg->r0 position so we can do "push" automatically */ - sub %sp, %sp, 8 - - SAVE_R1_TO_R24 - PUSH %r25 - PUSH %gp - PUSH %fp - PUSH %blink - PUSHAX %eret - PUSHAX %erstatus - PUSH %lp_count - PUSHAX %lp_end - PUSHAX %lp_start - PUSHAX %erbta -.endm - -.macro SAVE_EXCEPTION_SOURCE -#ifdef CONFIG_MMU - /* If MMU exists exception faulting address is loaded in EFA reg */ - lr %r0, [%efa] -#else - /* Otherwise in ERET (exception return) reg */ - lr %r0, [%eret] -#endif -.endm - -.section .ivt, "a",@progbits -.align 4 - /* Critical system events */ -.word _start /* 0 - 0x000 */ -.word memory_error /* 1 - 0x008 */ -.word instruction_error /* 2 - 0x010 */ - - /* Exceptions */ -.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ -.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ -.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ -.word EV_TLBProtV /* 0x118, Protection Violation (0x23) - or Misaligned Access */ -.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ -.word EV_Trap /* 0x128, Trap exception (0x25) */ -.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ - - /* Device interrupts */ -.rept 29 - j interrupt_handler /* 3:31 - 0x018:0xF8 */ -.endr - -.text -.globl _start -_start: - /* Setup interrupt vector base that matches "__text_start" */ - sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] - - /* Setup stack pointer */ - mov %sp, CONFIG_SYS_INIT_SP_ADDR - mov %fp, %sp - - /* Clear bss */ - mov %r0, __bss_start - mov %r1, __bss_end - -clear_bss: - st.ab 0, [%r0, 4] - brlt %r0, %r1, clear_bss - - /* Zero the one and only argument of "board_init_f" */ - mov_s %r0, 0 - j board_init_f - -memory_error: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_memory_error - -instruction_error: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_instruction_error - -interrupt_handler: - /* Todo - save and restore CPU context when interrupts will be in use */ - bl do_interrupt_handler - rtie - -EV_MachineCheck: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_machine_check_fault - -EV_TLBMissI: - SAVE_ALL_SYS - mov %r0, %sp - j do_itlb_miss - -EV_TLBMissD: - SAVE_ALL_SYS - mov %r0, %sp - j do_dtlb_miss - -EV_TLBProtV: - SAVE_ALL_SYS - SAVE_EXCEPTION_SOURCE - mov %r1, %sp - j do_tlb_prot_violation - -EV_PrivilegeV: - SAVE_ALL_SYS - mov %r0, %sp - j do_privilege_violation - -EV_Trap: - SAVE_ALL_SYS - mov %r0, %sp - j do_trap - -EV_Extension: - SAVE_ALL_SYS - mov %r0, %sp - j do_extension - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * r0 = start_addr_sp - * r1 = new__gd - * r2 = relocaddr - */ -.align 4 -.globl relocate_code -relocate_code: - /* - * r0-r12 might be clobbered by C functions - * so we use r13-r16 for storage here - */ - mov %r13, %r0 /* save addr_sp */ - mov %r14, %r1 /* save addr of gd */ - mov %r15, %r2 /* save addr of destination */ - - mov %r16, %r2 /* %r9 - relocation offset */ - sub %r16, %r16, __image_copy_start - -/* Set up the stack */ -stack_setup: - mov %sp, %r13 - mov %fp, %sp - -/* Check if monitor is loaded right in place for relocation */ - mov %r0, __image_copy_start - cmp %r0, %r15 /* skip relocation if code loaded */ - bz do_board_init_r /* in target location already */ - -/* Copy data (__image_copy_start - __image_copy_end) to new location */ - mov %r1, %r15 - mov %r2, __image_copy_end - sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */ - asr %r2, %r2, 2 /* r3 <- amount of words to copy */ - mov %lp_count, %r2 - lp copy_end - ld.ab %r2,[%r0,4] - st.ab %r2,[%r1,4] -copy_end: - -/* Fix relocations related issues */ - bl do_elf_reloc_fixups -#ifndef CONFIG_SYS_ICACHE_OFF - bl invalidate_icache_all -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - bl flush_dcache_all -#endif - -/* Update position of intterupt vector table */ - lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */ - add %r0, %r0, %r16 /* Update address */ - sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */ - -do_board_init_r: -/* Prepare for exection of "board_init_r" in relocated monitor */ - mov %r2, board_init_r /* old address of "board_init_r()" */ - add %r2, %r2, %r16 /* new address of "board_init_r()" */ - mov %r0, %r14 /* 1-st parameter: gd_t */ - mov %r1, %r15 /* 2-nd parameter: dest_addr */ - j [%r2] diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds index ccddbf7dc9..693df74061 100644 --- a/arch/arc/cpu/u-boot.lds +++ b/arch/arc/cpu/u-boot.lds @@ -13,6 +13,7 @@ SECTIONS .text : { *(.__text_start) *(.__image_copy_start) + arch/arc/lib/start.o (.text*) *(.text*) } diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile new file mode 100644 index 0000000000..5bc6f44c1a --- /dev/null +++ b/arch/arc/dts/Makefile @@ -0,0 +1,12 @@ +dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb +dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/arc/dts/abilis_tb100.dts b/arch/arc/dts/abilis_tb100.dts new file mode 100644 index 0000000000..cf395c4011 --- /dev/null +++ b/arch/arc/dts/abilis_tb100.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &uart0; + }; + + uart0: serial@ff100000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff100000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + }; +}; diff --git a/arch/arc/dts/arcangel4.dts b/arch/arc/dts/arcangel4.dts new file mode 100644 index 0000000000..bfcb9d8369 --- /dev/null +++ b/arch/arc/dts/arcangel4.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + console = &arcuart0; + }; + + arcuart0: serial@0xc0fc1000 { + compatible = "snps,arc-uart"; + reg = <0xc0fc1000 0x100>; + clock-frequency = <80000000>; + }; + +}; diff --git a/arch/arc/dts/skeleton.dtsi b/arch/arc/dts/skeleton.dtsi new file mode 100644 index 0000000000..b41d241de2 --- /dev/null +++ b/arch/arc/dts/skeleton.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 6a36a81c0f..0e11dcced5 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -46,6 +46,10 @@ #define ARC_AUX_DC_PTAG 0x5C #endif #define ARC_BCR_DC_BUILD 0x72 +#define ARC_BCR_SLC 0xce +#define ARC_AUX_SLC_CONTROL 0x903 +#define ARC_AUX_SLC_FLUSH 0x904 +#define ARC_AUX_SLC_INVALIDATE 0x905 #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 8a77cd93af..0b3ebd9f58 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -27,4 +27,15 @@ #define CONFIG_ARC_MMU_VER 4 #endif +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_ISA_ARCV2 +void slc_enable(void); +void slc_disable(void); +void slc_flush(void); +void slc_invalidate(void); +#endif + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h index b4e9099fb1..d2d791988e 100644 --- a/arch/arc/include/asm/config.h +++ b/arch/arc/include/asm/config.h @@ -7,8 +7,6 @@ #ifndef __ASM_ARC_CONFIG_H_ #define __ASM_ARC_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_ARCH_EARLY_INIT_R diff --git a/arch/arc/include/asm/init_helpers.h b/arch/arc/include/asm/init_helpers.h new file mode 100644 index 0000000000..7607e19561 --- /dev/null +++ b/arch/arc/include/asm/init_helpers.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARC_INIT_HELPERS_H +#define _ASM_ARC_INIT_HELPERS_H + +int init_cache_f_r(void); + +#endif /* _ASM_ARC_INIT_HELPERS_H */ diff --git a/arch/arc/include/asm/relocate.h b/arch/arc/include/asm/relocate.h new file mode 100644 index 0000000000..4c5f923416 --- /dev/null +++ b/arch/arc/include/asm/relocate.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARC_RELOCATE_H +#define _ASM_ARC_RELOCATE_H + +#include <common.h> + +int copy_uboot_to_ram(void); +int clear_bss(void); +int do_elf_reloc_fixups(void); + +#endif /* _ASM_ARC_RELOCATE_H */ diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h index 0c0e8e661d..a56ccf1b5d 100644 --- a/arch/arc/include/asm/u-boot-arc.h +++ b/arch/arc/include/asm/u-boot-arc.h @@ -9,4 +9,7 @@ int arch_early_init_r(void); +void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); +void board_init_f_r(void) __attribute__ ((noreturn)); + #endif /* __ASM_ARC_U_BOOT_ARC_H__ */ diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index b8028c91e1..e592802907 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -4,6 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +extra-y = start.o +head-y := start.o obj-y += cache.o obj-y += cpu.o obj-y += interrupts.o @@ -18,6 +20,8 @@ obj-y += memcpy-700.o obj-y += memset.o obj-y += reset.o obj-y += timer.o +obj-y += ints_low.o +obj-y += init_helpers.o obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index a2277231ba..e369e5a856 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -16,6 +16,7 @@ #define DC_CTRL_INV_MODE_FLUSH (1 << 6) #define DC_CTRL_FLUSH_STATUS (1 << 8) #define CACHE_VER_NUM_MASK 0xF +#define SLC_CTRL_SB (1 << 2) int icache_status(void) { @@ -49,10 +50,12 @@ void icache_disable(void) void invalidate_icache_all(void) { -#ifndef CONFIG_SYS_ICACHE_OFF + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)) + return; + /* Any write to IC_IVIC register triggers invalidation of entire I$ */ write_aux_reg(ARC_AUX_IC_IVIC, 1); -#endif /* CONFIG_SYS_ICACHE_OFF */ } int dcache_status(void) @@ -156,13 +159,60 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) void invalidate_dcache_all(void) { -#ifndef CONFIG_SYS_DCACHE_OFF + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return; + /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */ write_aux_reg(ARC_AUX_DC_IVDC, 1); -#endif /* CONFIG_SYS_DCACHE_OFF */ } void flush_cache(unsigned long start, unsigned long size) { flush_dcache_range(start, start + size); } + +#ifdef CONFIG_ISA_ARCV2 +void slc_enable(void) +{ + /* If SLC ver = 0, no SLC present in CPU */ + if (!(read_aux_reg(ARC_BCR_SLC) & 0xff)) + return; + + write_aux_reg(ARC_AUX_SLC_CONTROL, + read_aux_reg(ARC_AUX_SLC_CONTROL) & ~1); +} + +void slc_disable(void) +{ + /* If SLC ver = 0, no SLC present in CPU */ + if (!(read_aux_reg(ARC_BCR_SLC) & 0xff)) + return; + + write_aux_reg(ARC_AUX_SLC_CONTROL, + read_aux_reg(ARC_AUX_SLC_CONTROL) | 1); +} + +void slc_flush(void) +{ + /* If SLC ver = 0, no SLC present in CPU */ + if (!(read_aux_reg(ARC_BCR_SLC) & 0xff)) + return; + + write_aux_reg(ARC_AUX_SLC_FLUSH, 1); + + /* Wait flush end */ + while (read_aux_reg(ARC_AUX_SLC_CONTROL) & SLC_CTRL_SB) + ; +} + +void slc_invalidate(void) +{ + /* If SLC ver = 0, no SLC present in CPU */ + if (!(read_aux_reg(ARC_BCR_SLC) & 0xff)) + return; + + write_aux_reg(ARC_AUX_SLC_INVALIDATE, 1); +} + +#endif /* CONFIG_ISA_ARCV2 */ diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 50634b860f..3c930bcbeb 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -12,19 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; int arch_cpu_init(void) { -#ifdef CONFIG_SYS_ICACHE_OFF - icache_disable(); -#else - icache_enable(); - invalidate_icache_all(); -#endif - - flush_dcache_all(); -#ifdef CONFIG_SYS_DCACHE_OFF - dcache_disable(); -#else - dcache_enable(); -#endif timer_init(); /* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */ diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c new file mode 100644 index 0000000000..25690ee16e --- /dev/null +++ b/arch/arc/lib/init_helpers.c @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int init_cache_f_r(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF + icache_enable(); + /* Make sure no stale entries persist from before we disabled cache */ + invalidate_icache_all(); +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); + /* Make sure no stale entries persist from before we disabled cache */ + invalidate_dcache_all(); +#endif + return 0; +} diff --git a/arch/arc/lib/ints_low.S b/arch/arc/lib/ints_low.S new file mode 100644 index 0000000000..161cf37dc4 --- /dev/null +++ b/arch/arc/lib/ints_low.S @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +/* + * Note on the LD/ST addressing modes with address register write-back + * + * LD.a same as LD.aw + * + * LD.a reg1, [reg2, x] => Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] => Post Incr + * Eff Addr for load = [reg2] + */ + +.macro PUSH reg + st.a \reg, [%sp, -4] +.endm + +.macro PUSHAX aux + lr %r9, [\aux] + PUSH %r9 +.endm + +.macro SAVE_R1_TO_R24 + PUSH %r1 + PUSH %r2 + PUSH %r3 + PUSH %r4 + PUSH %r5 + PUSH %r6 + PUSH %r7 + PUSH %r8 + PUSH %r9 + PUSH %r10 + PUSH %r11 + PUSH %r12 + PUSH %r13 + PUSH %r14 + PUSH %r15 + PUSH %r16 + PUSH %r17 + PUSH %r18 + PUSH %r19 + PUSH %r20 + PUSH %r21 + PUSH %r22 + PUSH %r23 + PUSH %r24 +.endm + +.macro SAVE_ALL_SYS + /* saving %r0 to reg->r0 in advance since we read %ecr into it */ + st %r0, [%sp, -8] + lr %r0, [%ecr] /* all stack addressing is manual so far */ + st %r0, [%sp] + st %sp, [%sp, -4] + /* now move %sp to reg->r0 position so we can do "push" automatically */ + sub %sp, %sp, 8 + + SAVE_R1_TO_R24 + PUSH %r25 + PUSH %gp + PUSH %fp + PUSH %blink + PUSHAX %eret + PUSHAX %erstatus + PUSH %lp_count + PUSHAX %lp_end + PUSHAX %lp_start + PUSHAX %erbta +.endm + +.macro SAVE_EXCEPTION_SOURCE +#ifdef CONFIG_MMU + /* If MMU exists exception faulting address is loaded in EFA reg */ + lr %r0, [%efa] +#else + /* Otherwise in ERET (exception return) reg */ + lr %r0, [%eret] +#endif +.endm + +ENTRY(memory_error) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_memory_error +ENDPROC(memory_error) + +ENTRY(instruction_error) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_instruction_error +ENDPROC(instruction_error) + +ENTRY(interrupt_handler) + /* Todo - save and restore CPU context when interrupts will be in use */ + bl do_interrupt_handler + rtie +ENDPROC(interrupt_handler) + +ENTRY(EV_MachineCheck) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_machine_check_fault +ENDPROC(EV_MachineCheck) + +ENTRY(EV_TLBMissI) + SAVE_ALL_SYS + mov %r0, %sp + j do_itlb_miss +ENDPROC(EV_TLBMissI) + +ENTRY(EV_TLBMissD) + SAVE_ALL_SYS + mov %r0, %sp + j do_dtlb_miss +ENDPROC(EV_TLBMissD) + +ENTRY(EV_TLBProtV) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_tlb_prot_violation +ENDPROC(EV_TLBProtV) + +ENTRY(EV_PrivilegeV) + SAVE_ALL_SYS + mov %r0, %sp + j do_privilege_violation +ENDPROC(EV_PrivilegeV) + +ENTRY(EV_Trap) + SAVE_ALL_SYS + mov %r0, %sp + j do_trap +ENDPROC(EV_Trap) + +ENTRY(EV_Extension) + SAVE_ALL_SYS + mov %r0, %sp + j do_extension +ENDPROC(EV_Extension) diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c index 7797782563..5c2c2d1930 100644 --- a/arch/arc/lib/relocate.c +++ b/arch/arc/lib/relocate.c @@ -10,6 +10,25 @@ DECLARE_GLOBAL_DATA_PTR; +int copy_uboot_to_ram(void) +{ + size_t len = (size_t)&__image_copy_end - (size_t)&__image_copy_start; + + memcpy((void *)gd->relocaddr, (void *)&__image_copy_start, len); + + return 0; +} + +int clear_bss(void) +{ + ulong dst_addr = (ulong)&__bss_start + gd->reloc_off; + size_t len = (size_t)&__bss_end - (size_t)&__bss_start; + + memset((void *)dst_addr, 0x00, len); + + return 0; +} + /* * Base functionality is taken from x86 version with added ARC-specifics */ diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S new file mode 100644 index 0000000000..e1ef19cb88 --- /dev/null +++ b/arch/arc/lib/start.S @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/arcregs.h> + +ENTRY(_start) + /* Setup interrupt vector base that matches "__text_start" */ + sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] + + /* Setup stack- and frame-pointers */ + mov %sp, CONFIG_SYS_INIT_SP_ADDR + mov %fp, %sp + + /* Unconditionally disable caches */ +#ifdef CONFIG_ISA_ARCV2 + bl slc_flush + bl slc_disable +#endif + bl flush_dcache_all + bl dcache_disable + bl icache_disable + + /* Allocate and zero GD, update SP */ + mov %r0, %sp + bl board_init_f_mem + + /* Update stack- and frame-pointers */ + mov %sp, %r0 + mov %fp, %sp + + /* Zero the one and only argument of "board_init_f" */ + mov_s %r0, 0 + j board_init_f +ENDPROC(_start) + +/* + * void board_init_f_r_trampoline(stack-pointer address) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r0 = new stack-pointer + */ +ENTRY(board_init_f_r_trampoline) + /* Set up the stack- and frame-pointers */ + mov %sp, %r0 + mov %fp, %sp + + /* Update position of intterupt vector table */ + lr %r0, [ARC_AUX_INTR_VEC_BASE] + ld %r1, [%r25, GD_RELOC_OFF] + add %r0, %r0, %r1 + sr %r0, [ARC_AUX_INTR_VEC_BASE] + + /* Re-enter U-Boot by calling board_init_f_r */ + j board_init_f_r +ENDPROC(board_init_f_r_trampoline) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 06b8e58a32..7ed0e20521 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -132,6 +132,11 @@ config TARGET_DEVKIT3250 bool "Support devkit3250" select CPU_ARM926EJS +config TARGET_WORK_92105 + bool "Support work_92105" + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_MX25PDK bool "Support mx25pdk" select CPU_ARM926EJS @@ -286,13 +291,8 @@ config TARGET_MX35PDK bool "Support mx35pdk" select CPU_ARM1136 -config TARGET_RPI - bool "Support rpi" - select CPU_ARM1176 - -config TARGET_RPI_2 - bool "Support rpi_2" - select CPU_V7 +config ARCH_BCM283X + bool "Broadcom BCM283X family" config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" @@ -731,9 +731,9 @@ endchoice source "arch/arm/mach-at91/Kconfig" -source "arch/arm/mach-davinci/Kconfig" +source "arch/arm/mach-bcm283x/Kconfig" -source "arch/arm/cpu/arm1176/bcm2835/Kconfig" +source "arch/arm/mach-davinci/Kconfig" source "arch/arm/cpu/armv7/exynos/Kconfig" @@ -848,8 +848,6 @@ source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/pxa255_idp/Kconfig" -source "board/raspberrypi/rpi/Kconfig" -source "board/raspberrypi/rpi_2/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" @@ -885,6 +883,7 @@ source "board/vpac270/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" source "board/woodburn/Kconfig" +source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" source "board/xilinx/zynqmp/Kconfig" source "board/zipitz2/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 08946de244..bd4749c55e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -2,9 +2,47 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) +CONFIG_CPU_V7= +CONFIG_CPU_ARM720T=y +endif + +# This selects which instruction set is used. +arch-$(CONFIG_CPU_ARM720T) =-march=armv4 +arch-$(CONFIG_CPU_ARM920T) =-march=armv4 +arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te +arch-$(CONFIG_CPU_ARM946ES) =-march=armv4 +arch-$(CONFIG_CPU_SA1100) =-march=armv4 +arch-$(CONFIG_CPU_PXA) = +arch-$(CONFIG_CPU_ARM1136) =-march=armv5 +arch-$(CONFIG_CPU_ARM1176) =-march=armv5t +arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, -march=armv5) +arch-$(CONFIG_ARM64) =-march=armv8-a + +# Evaluate arch cc-option calls now +arch-y := $(arch-y) + +# This selects how we optimise for the processor. +tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi +tune-$(CONFIG_CPU_ARM920T) = +tune-$(CONFIG_CPU_ARM926EJS) = +tune-$(CONFIG_CPU_ARM946ES) = +tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100 +tune-$(CONFIG_CPU_PXA) =-mcpu=xscale +tune-$(CONFIG_CPU_ARM1136) = +tune-$(CONFIG_CPU_ARM1176) = +tune-$(CONFIG_CPU_V7) = +tune-$(CONFIG_ARM64) = + +# Evaluate tune cc-option calls now +tune-y := $(tune-y) + +PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) + # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. machine-$(CONFIG_ARCH_AT91) += at91 +machine-$(CONFIG_ARCH_BCM283X) += bcm283x machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 0667984b69..c005ce4905 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -19,9 +19,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -# Support generic board on ARM -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_CPPFLAGS += -D__ARM__ # Choose between ARM/Thumb instruction sets diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk deleted file mode 100644 index a82c6cec9c..0000000000 --- a/arch/arm/cpu/arm1136/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v6. -PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 1cfcca9fa6..1ec79a6f35 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -14,7 +14,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index 480e130489..deec427447 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -10,5 +10,3 @@ extra-y = start.o obj-y = cpu.o - -obj-$(CONFIG_BCM2835) += bcm2835/ diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig deleted file mode 100644 index 73cc72b411..0000000000 --- a/arch/arm/cpu/arm1176/bcm2835/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RPI || TARGET_RPI_2 - -config DM - default y - -config DM_SERIAL - default y - -config DM_GPIO - default y - -endif diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk deleted file mode 100644 index 5dc2ebb27b..0000000000 --- a/arch/arm/cpu/arm1176/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v6. -PLATFORM_CPPFLAGS += -march=armv5t diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ac937bf5b0..4c0ab4d0ee 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -16,7 +16,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #ifndef CONFIG_SYS_PHY_UBOOT_BASE #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk deleted file mode 100644 index 772fb413e8..0000000000 --- a/arch/arm/cpu/arm720t/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 01c85be64b..ec8e88d4b3 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -9,7 +9,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/hardware.h> /* diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk deleted file mode 100644 index 799afff028..0000000000 --- a/arch/arm/cpu/arm920t/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk deleted file mode 100644 index bdb3da183e..0000000000 --- a/arch/arm/cpu/arm926ejs/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv5te diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile index 314f004eba..48373776ff 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile @@ -6,3 +6,5 @@ # obj-y = cpu.o clk.o devices.o timer.o + +obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c index b7a44d59da..1ef8a36669 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c @@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void) return get_hclk_pll_rate() / get_periph_clk_div(); } +unsigned int get_sdram_clk_rate(void) +{ + unsigned int src_clk; + + if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) + return get_sys_clk_rate(); + + src_clk = get_hclk_pll_rate(); + + if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) { + /* using DDR */ + switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) { + case CLK_HCLK_DDRAM_HALF: + return src_clk/2; + case CLK_HCLK_DDRAM_NOMINAL: + return src_clk; + default: + return 0; + } + } else { + /* using SDR */ + switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) { + case CLK_HCLK_ARM_PLL_DIV_4: + return src_clk/4; + case CLK_HCLK_ARM_PLL_DIV_2: + return src_clk/2; + case CLK_HCLK_ARM_PLL_DIV_1: + return src_clk; + default: + return 0; + } + } +} + int get_serial_clock(void) { return get_periph_clk_rate(); diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c index 35095a9583..f757474076 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -5,9 +5,11 @@ */ #include <common.h> +#include <netdev.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/wdt.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; @@ -55,3 +57,11 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_LPC32XX_ETH +int cpu_eth_init(bd_t *bis) +{ + lpc32xx_eth_initialize(bis); + return 0; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index b5676578fd..5a453e303d 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -8,10 +8,13 @@ #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/uart.h> +#include <asm/arch/mux.h> #include <asm/io.h> +#include <dm.h> static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; +static struct mux_regs *mux = (struct mux_regs *)MUX_BASE; void lpc32xx_uart_init(unsigned int uart_id) { @@ -37,3 +40,43 @@ void lpc32xx_uart_init(unsigned int uart_id) writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1), &clk->u3clk + (uart_id - 3)); } + +void lpc32xx_mac_init(void) +{ + /* Enable MAC interface */ + writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER + | CLK_MAC_MII, &clk->macclk_ctrl); +} + +void lpc32xx_mlc_nand_init(void) +{ + /* Enable NAND interface */ + writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); +} + +void lpc32xx_i2c_init(unsigned int devnum) +{ + /* Enable I2C interface */ + uint32_t ctrl = readl(&clk->i2cclk_ctrl); + if (devnum == 1) + ctrl |= CLK_I2C1_ENABLE; + if (devnum == 2) + ctrl |= CLK_I2C2_ENABLE; + writel(ctrl, &clk->i2cclk_ctrl); +} + +U_BOOT_DEVICE(lpc32xx_gpios) = { + .name = "gpio_lpc32xx" +}; + +/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */ + +#define P_MUX_SET_SSP0 0x1600 + +void lpc32xx_ssp_init(void) +{ + /* Enable SSP0 interface */ + writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl); + /* Mux SSP0 pins */ + writel(P_MUX_SET_SSP0, &mux->p_mux_set); +} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/dram.c b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c new file mode 100644 index 0000000000..1eea8e2bbf --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c @@ -0,0 +1,77 @@ +/* + * LPC32xx dram init + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * This is called by SPL to gain access to the SDR DRAM. + * + * This code runs from SRAM. + * + * Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided + * by the board configuration file. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/wdt.h> +#include <asm/arch/emc.h> +#include <asm/io.h> + +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; + +void ddr_init(struct emc_dram_settings *dram) +{ + uint32_t ck; + + /* Enable EMC interface and choose little endian mode */ + writel(1, &emc->ctrl); + writel(0, &emc->config); + /* Select maximum EMC Dynamic Memory Refresh Time */ + writel(0x7FF, &emc->refresh); + /* Determine CLK */ + ck = get_sdram_clk_rate(); + /* Configure SDRAM */ + writel(dram->cmddelay, &clk->sdramclk_ctrl); + writel(dram->config0, &emc->config0); + writel(dram->rascas0, &emc->rascas0); + writel(dram->rdconfig, &emc->read_config); + /* Set timings */ + writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); + writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); + writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); + writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); + writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); + writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc); + writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); + writel(dram->trrd, &emc->t_rrd); + writel(dram->tmrd, &emc->t_mrd); + writel(dram->tcdlr, &emc->t_cdlr); + /* Dynamic refresh */ + writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); + udelay(10); + /* Force all clocks, enable inverted ck, issue NOP command */ + writel(0x00000193, &emc->control); + udelay(100); + /* Keep all clocks enabled, issue a PRECHARGE ALL command */ + writel(0x00000113, &emc->control); + /* Fast dynamic refresh for at least a few SDRAM ck cycles */ + writel((((128) >> 4) & 0x7FF), &emc->refresh); + udelay(10); + /* set correct dynamic refresh timing */ + writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); + udelay(10); + /* set normal mode to CAS=3 */ + writel(0x00000093, &emc->control); + readl(EMC_DYCS0_BASE | dram->mode); + /* set extended mode to all zeroes */ + writel(0x00000093, &emc->control); + readl(EMC_DYCS0_BASE | dram->emode); + /* stop forcing clocks, keep inverted clock, issue normal mode */ + writel(0x00000010, &emc->control); +} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S new file mode 100644 index 0000000000..4b8053e3f9 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S @@ -0,0 +1,45 @@ +/* + * WORK Microwave work_92105 board low level init + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Low level init is called from SPL to set up the clocks. + * On entry, the LPC3250 is in Direct Run mode with all clocks + * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is + * 104 MHz and PCLK is 13 MHz. + * + * This code must run from SRAM so that the clock changes do + * not prevent it from executing. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl lowlevel_init + +lowlevel_init: + + /* Set ARM, HCLK, PCLK dividers for normal mode */ + ldr r0, =0x0000003D + ldr r1, =0x40004040 + str r0, [r1] + + /* Start HCLK PLL for 208 MHz */ + ldr r0, =0x0001401E + ldr r1, =0x40004058 + str r0, [r1] + + /* wait for HCLK PLL to lock */ +1: + ldr r0, [r1] + ands r0, r0, #1 + beq 1b + + /* switch to normal mode */ + ldr r1, =0x40004044 + ldr r0, [r1] + orr r0, #0x00000004 + str r0, [r1] + + /* Return to U-boot via saved link register */ + mov pc, lr diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 9b60436539..48abcd5260 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -22,7 +22,6 @@ #include <asm-offsets.h> #include <config.h> #include <common.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 8eb249475e..82cc1c9477 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -18,7 +18,6 @@ #include <asm-offsets.h> #include <config.h> #include <common.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk deleted file mode 100644 index 438668d6ff..0000000000 --- a/arch/arm/cpu/arm946es/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 41123716a7..b55395aa53 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -17,7 +17,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 1312a9db9e..21fc03b97e 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -39,7 +39,6 @@ endif obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ -obj-$(CONFIG_BCM2835) += bcm2835/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 85cceae152..f5b16b4b72 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -164,9 +164,9 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); } /** diff --git a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S index 1febd7bac5..69da7fe7af 100644 --- a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S +++ b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S @@ -3,11 +3,10 @@ */ #include <config.h> -#include <version.h> #include <linux/linkage.h> ENTRY(save_boot_params) - bx lr + b save_boot_params_ret ENDPROC(save_boot_params) /* diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile deleted file mode 100644 index ed1ee4753d..0000000000 --- a/arch/arm/cpu/armv7/bcm2835/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# SPDX-License-Identifier: GPL-2.0+ -# - -src_dir := ../../arm1176/bcm2835/ - -obj-y := -obj-y += $(src_dir)/init.o -obj-y += $(src_dir)/reset.o -obj-y += $(src_dir)/timer.o -obj-y += $(src_dir)/mbox.o diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 6c82c3b537..63591d4a29 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -5,11 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# If armv7-a is not supported by GCC fall-back to armv5, which is -# supported by more tool-chains -PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) - # On supported platforms we set the bit which causes us to trap on unaligned # memory access. This is the opposite of what the compiler expects to be # the default so we must pass in -mno-unaligned-access so that it is aware diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index eb86a7fe7d..bd7540ac61 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -80,12 +80,6 @@ config DM_SPI_FLASH config DM_GPIO default y -config SYS_MALLOC_F - default y - -config SYS_MALLOC_F_LEN - default 0x400 - source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index c6455c2f3c..df4d4739ff 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -14,7 +14,6 @@ #define PLL_DIV_1024 1024 #define PLL_DIV_65535 65535 #define PLL_DIV_65536 65536 - /* * * This structure is to store the src bit, div bit and prediv bit * positions of the peripheral clocks of the src and div registers @@ -423,8 +422,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral) case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: src = EXYNOS_SRC_MPLL; - div = readl(&clk->div_top0); - sub_div = readl(&clk->div_top1); + div = readl(&clk->div_top1); + sub_div = readl(&clk->div_top0); break; default: debug("%s: invalid peripheral %d", __func__, peripheral); @@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; } +static unsigned long exynos5800_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_DISP10 + * CLKMUX_FIMD1 [6:4] + */ + sel = (readl(&clk->src_disp10) >> 4) & 0x7; + + if (sel) { + /* + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into + * PLLs. The first element is a placeholder to bypass the + * default settig. + */ + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, + RPLL}; + sclk = get_pll_clk(reg_map[sel]); + } else + sclk = CONFIG_SYS_CLK_FREQ; + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10) & 0xf; + + return sclk / (ratio + 1); +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); } +void exynos5800_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * Use RPLL for pixel clock + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] + * ================== + * 111: SCLK_RPLL + */ + cfg = readl(&clk->src_disp10) | (0x7 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); + else if (proid_is_exynos5800()) + return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); } @@ -1660,8 +1717,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420() || proid_is_exynos5800()) + else if (proid_is_exynos5420()) exynos5420_set_lcd_clk(); + else + exynos5800_set_lcd_clk(); } } diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c index 31610909f8..584e4bac09 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c @@ -25,7 +25,6 @@ #include <common.h> #include <config.h> -#include <version.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 0aff3d0d0c..0200fd154f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, - /* RPLL @70.5Mhz */ + /* RPLL @141Mhz */ .rpll_mdiv = 0x5E, .rpll_pdiv = 0x2, - .rpll_sdiv = 0x4, + .rpll_sdiv = 0x3, .direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, diff --git a/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h index b633e56603..9f29d94c10 100644 --- a/arch/arm/cpu/armv7/exynos/exynos4_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h @@ -10,7 +10,6 @@ #define _ORIGEN_SETUP_H #include <config.h> -#include <version.h> #include <asm/arch/cpu.h> #ifdef CONFIG_CLK_800_330_165 diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 65da6e2c17..1f96498fb8 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -106,12 +106,6 @@ config DM_GPIO config DM_SERIAL default y if DM -config SYS_MALLOC_F - default y if DM - -config SYS_MALLOC_F_LEN - default 0x400 if DM - config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 7a691519bb..249761308e 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -12,7 +12,6 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/mem.h> #include <asm/arch/clocks_omap3.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index afed773c63..b4d0627871 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> /* Set up the platform, once the cpu has been initialized */ .globl lowlevel_init diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index bd9f338301..6a8c15d91f 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -8,7 +8,6 @@ #include <asm/io.h> #include <asm/u-boot.h> #include <asm/utils.h> -#include <version.h> #include <image.h> #include <asm/arch/reset_manager.h> #include <spl.h> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5050021e02..5ed0f45a26 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -15,7 +15,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/system.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 49f4032e9c..c3e04af36d 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -100,22 +100,23 @@ static struct { unsigned int freq; } pll1_para[] = { /* This array must be ordered by frequency. */ - { PLL1_CFG(16, 0, 0, 0), 384000000 }, - { PLL1_CFG(16, 1, 0, 0), 768000000 }, - { PLL1_CFG(20, 1, 0, 0), 960000000 }, - { PLL1_CFG(21, 1, 0, 0), 1008000000}, - { PLL1_CFG(22, 1, 0, 0), 1056000000}, - { PLL1_CFG(23, 1, 0, 0), 1104000000}, - { PLL1_CFG(24, 1, 0, 0), 1152000000}, - { PLL1_CFG(25, 1, 0, 0), 1200000000}, - { PLL1_CFG(26, 1, 0, 0), 1248000000}, - { PLL1_CFG(27, 1, 0, 0), 1296000000}, - { PLL1_CFG(28, 1, 0, 0), 1344000000}, - { PLL1_CFG(29, 1, 0, 0), 1392000000}, - { PLL1_CFG(30, 1, 0, 0), 1440000000}, { PLL1_CFG(31, 1, 0, 0), 1488000000}, - /* Final catchall entry */ - { PLL1_CFG(31, 1, 0, 0), ~0}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(19, 1, 0, 0), 912000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + /* Final catchall entry 384MHz*/ + { PLL1_CFG(16, 0, 0, 0), 0 }, + }; void clock_set_pll1(unsigned int hz) @@ -126,10 +127,12 @@ void clock_set_pll1(unsigned int hz) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Find target frequency */ - while (pll1_para[i].freq < hz) + while (pll1_para[i].freq > hz) i++; hz = pll1_para[i].freq; + if (! hz) + hz = 384000000; /* Calculate system clock divisors */ axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 5be497b7be..e0a524e10c 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -37,7 +37,7 @@ .arch_extension sec -#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000) +#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) #define TEN_MS (10 * ONE_MS) #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c index 14de9f98bd..524f25ce83 100644 --- a/arch/arm/cpu/armv7/sunxi/usbc.c +++ b/arch/arm/cpu/armv7/sunxi/usbc.c @@ -182,6 +182,13 @@ static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable) return; } +void sunxi_usbc_enable_squelch_detect(int index, int enable) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + + usb_phy_write(sunxi_usbc, 0x3c, enable ? 0 : 2, 2); +} + int sunxi_usbc_request_resources(int index) { struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index fa447bce16..d846236500 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -9,7 +9,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/macro.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk index f5b95591af..685025881c 100644 --- a/arch/arm/cpu/armv8/config.mk +++ b/arch/arm/cpu/armv8/config.mk @@ -6,7 +6,5 @@ # PLATFORM_RELFLAGS += -fno-common -ffixed-x18 -PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a) PF_NO_UNALIGNED := $(call cc-option, -mstrict-align) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8) PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED) diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index b91a1b662f..baf9401e64 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/ptrace.h> #include <asm/macro.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index b4eab0b0f2..e5f2766a4a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S index f840b04df5..945445bc37 100644 --- a/arch/arm/cpu/armv8/tlb.S +++ b/arch/arm/cpu/armv8/tlb.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index ade1cdead8..253a39bd11 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index 525f5d33b7..7fb5316d8f 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -mcpu=xscale - # # !WARNING! # The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index c77d51e6d8..879390be2d 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -21,7 +21,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk deleted file mode 100644 index 3afa685b3f..0000000000 --- a/arch/arm/cpu/sa1100/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 78e0cb8868..eebff661f8 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -11,7 +11,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cbe5b86755..f897e6d969 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -24,7 +24,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-trimslice.dtb \ tegra20-ventana.dtb \ tegra20-whistler.dtb \ - tegra20-colibri_t20_iris.dtb \ + tegra20-colibri.dtb \ tegra30-apalis.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index b801de9787..3ad4728138 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -67,6 +67,8 @@ edp-lvds-bridge@48 { compatible = "parade,ps8625"; reg = <0x48>; + sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index 916cf3a5b6..31fabb190e 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -168,6 +168,7 @@ fimd@14400000 { /* sysmmu is not used in U-Boot */ samsung,disable-sysmmu; + samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>; }; dp@145b0000 { diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index e4bc100995..494f7641e7 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -144,10 +144,13 @@ samsung,vl-vfpd = <10>; samsung,vl-cmd-allow-len = <0xf>; + samsung,power-on-delay = <30000>; samsung,winid = <3>; samsung,interface-mode = <1>; samsung,dp-enabled = <1>; samsung,dual-lcd-enabled = <0>; + + samsung,bl-en-gpio = <&gpx2 2 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri.dts index 3131b9201b..3131b9201b 100644 --- a/arch/arm/dts/tegra20-colibri_t20_iris.dts +++ b/arch/arm/dts/tegra20-colibri.dts diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 2a17dfc6de..d20b7d2ae3 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10 #define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) #define MASK_RATIO(x) (0xf << (x << 4)) diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 92f6c15f20..94498695a0 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -71,6 +71,7 @@ struct clk_pm_regs { }; /* HCLK Divider Control Register bits */ +#define CLK_HCLK_DDRAM_MASK (0x3 << 7) #define CLK_HCLK_DDRAM_HALF (0x2 << 7) #define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) #define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) @@ -123,6 +124,10 @@ struct clk_pm_regs { #define CLK_MAC_SLAVE (1 << 1) #define CLK_MAC_REG (1 << 0) +/* I2C Clock Control Register bits */ +#define CLK_I2C2_ENABLE (1 << 1) +#define CLK_I2C1_ENABLE (1 << 0) + /* Timer Clock Control1 Register bits */ #define CLK_TIMCLK_MOTOR (1 << 6) #define CLK_TIMCLK_TIMER3 (1 << 5) @@ -147,11 +152,22 @@ struct clk_pm_regs { /* DMA Clock Control Register bits */ #define CLK_DMA_ENABLE (1 << 0) +/* NAND Clock Control Register bits */ +#define CLK_NAND_MLC (1 << 1) +#define CLK_NAND_MLC_INT (1 << 5) + +/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0) + +/* SDRAMCLK register bits */ +#define CLK_SDRAM_DDR_SEL (1 << 1) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); unsigned int get_hclk_clk_rate(void); unsigned int get_periph_clk_div(void); unsigned int get_periph_clk_rate(void); +unsigned int get_sdram_clk_rate(void); #endif /* _LPC32XX_CLK_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 564441cbfa..d57bc4877e 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -52,6 +52,9 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } +/* Ethernet */ +#define LPC32XX_ETH_BASE ETHERNET_BASE + /* NOR Flash */ #if defined(CONFIG_SYS_FLASH_CFI) #define CONFIG_FLASH_CFI_DRIVER diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h index 199b4a026b..0b5dca11b8 100644 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -27,6 +27,7 @@ #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ #define RTC_BASE 0x40024000 /* RTC registers base */ #define GPIO_BASE 0x40028000 /* GPIO registers base */ +#define MUX_BASE 0x40028100 /* MUX registers base */ #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ @@ -37,6 +38,8 @@ #define UART4_BASE 0x40088000 /* UART 4 registers base */ #define UART5_BASE 0x40090000 /* UART 5 registers base */ #define UART6_BASE 0x40098000 /* UART 6 registers base */ +#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ +#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */ /* External SDRAM Memory Bank base addresses */ #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h index 82d9bcce50..1a2bab251f 100644 --- a/arch/arm/include/asm/arch-lpc32xx/emc.h +++ b/arch/arm/include/asm/arch-lpc32xx/emc.h @@ -76,4 +76,25 @@ struct emc_regs { #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) +/* EMC settings for DRAM */ +struct emc_dram_settings { + u32 cmddelay; + u32 config0; + u32 rascas0; + u32 rdconfig; + u32 trp; + u32 tras; + u32 tsrex; + u32 twr; + u32 trc; + u32 trfc; + u32 txsr; + u32 trrd; + u32 tmrd; + u32 tcdlr; + u32 refresh; + u32 mode; + u32 emode; +}; + #endif /* _LPC32XX_EMC_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h new file mode 100644 index 0000000000..3bd94e31a5 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h @@ -0,0 +1,43 @@ +/* + * LPC32xx GPIO interface + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/** + * GPIO Register map for LPC32xx + */ + +struct gpio_regs { + u32 p3_inp_state; + u32 p3_outp_set; + u32 p3_outp_clr; + u32 p3_outp_state; + /* Watch out! the following are shared between p2 and p3 */ + u32 p2_p3_dir_set; + u32 p2_p3_dir_clr; + u32 p2_p3_dir_state; + /* Now back to 'one register for one port' */ + u32 p2_inp_state; + u32 p2_outp_set; + u32 p2_outp_clr; + u32 reserved1[6]; + u32 p0_inp_state; + u32 p0_outp_set; + u32 p0_outp_clr; + u32 p0_outp_state; + u32 p0_dir_set; + u32 p0_dir_clr; + u32 p0_dir_state; + u32 reserved2; + u32 p1_inp_state; + u32 p1_outp_set; + u32 p1_outp_clr; + u32 p1_outp_state; + u32 p1_dir_set; + u32 p1_dir_clr; + u32 p1_dir_state; +}; diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h new file mode 100644 index 0000000000..dc1b5bcdfd --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/mux.h @@ -0,0 +1,18 @@ +/* + * LPC32xx MUX interface + * + * (C) Copyright 2015 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/** + * MUX register map for LPC32xx + */ + +struct mux_regs { + u32 p_mux_set; + u32 p_mux_clr; + u32 p_mux_state; +}; diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 28812be3cb..c3d890dde4 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -7,6 +7,14 @@ #ifndef _LPC32XX_SYS_PROTO_H #define _LPC32XX_SYS_PROTO_H -void lpc32xx_uart_init(unsigned int uart_id); +#include <asm/arch/emc.h> +void lpc32xx_uart_init(unsigned int uart_id); +void lpc32xx_mac_init(void); +void lpc32xx_mlc_nand_init(void); +void lpc32xx_i2c_init(unsigned int devnum); +void lpc32xx_ssp_init(void); +#if defined(CONFIG_SPL_BUILD) +void ddr_init(const struct emc_dram_settings *dram); +#endif #endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h index cb538cdc7d..133073321b 100644 --- a/arch/arm/include/asm/arch-sunxi/usbc.h +++ b/arch/arm/include/asm/arch-sunxi/usbc.h @@ -20,3 +20,4 @@ void sunxi_usbc_enable(int index); void sunxi_usbc_disable(int index); void sunxi_usbc_vbus_enable(int index); void sunxi_usbc_vbus_disable(int index); +void sunxi_usbc_enable_squelch_detect(int index, int enable); diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 4212e57699..3cc52dd773 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -170,6 +170,16 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, int len); +struct pmux_pingrp_desc { + u8 funcs[4]; +#if defined(CONFIG_TEGRA20) + u8 ctl_id; + u8 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; + #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS #define PMUX_SLWF_MIN 0 @@ -219,14 +229,20 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ -struct pmux_pingrp_desc { - u8 funcs[4]; -#if defined(CONFIG_TEGRA20) - u8 ctl_id; - u8 pull_id; -#endif /* CONFIG_TEGRA20 */ +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS +struct pmux_mipipadctrlgrp_config { + u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ + u32 func:8; /* function to assign PMUX_FUNC_... */ }; -extern const struct pmux_pingrp_desc *tegra_soc_pingroups; +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len); + +struct pmux_mipipadctrlgrp_desc { + u8 funcs[2]; +}; + +extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ #endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 78bc9e6f17..9fcbb0f80b 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -246,6 +246,11 @@ enum pmux_drvgrp { PMUX_DRVGRP_COUNT, }; +enum pmux_mipipadctrlgrp { + PMUX_MIPIPADCTRLGRP_DSI_B, + PMUX_MIPIPADCTRLGRP_COUNT, +}; + enum pmux_func { PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, @@ -255,6 +260,7 @@ enum pmux_func { PMUX_FUNC_CLK, PMUX_FUNC_CLK12, PMUX_FUNC_CPU, + PMUX_FUNC_CSI, PMUX_FUNC_DAP, PMUX_FUNC_DAP1, PMUX_FUNC_DAP2, @@ -263,6 +269,7 @@ enum pmux_func { PMUX_FUNC_DISPLAYA_ALT, PMUX_FUNC_DISPLAYB, PMUX_FUNC_DP, + PMUX_FUNC_DSI_B, PMUX_FUNC_DTV, PMUX_FUNC_EXTPERIPH1, PMUX_FUNC_EXTPERIPH2, @@ -336,8 +343,10 @@ enum pmux_func { }; #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS #define TEGRA_PMX_GRPS_HAVE_LPMD #define TEGRA_PMX_GRPS_HAVE_SCHMT #define TEGRA_PMX_GRPS_HAVE_HSM diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index be80434dee..7a34a0186c 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -7,10 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#ifdef __aarch64__ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA -#endif - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index d4a447b2b8..c424a22442 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -936,7 +936,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CWME9210 3320 #define MACH_TYPE_CWME9210JS 3321 #define MACH_TYPE_PGS_SITARA 3322 -#define MACH_TYPE_COLIBRI_TEGRA2 3323 +#define MACH_TYPE_COLIBRI_T20 3323 #define MACH_TYPE_W21 3324 #define MACH_TYPE_POLYSAT1 3325 #define MACH_TYPE_DATAWAY 3326 @@ -12197,16 +12197,16 @@ extern unsigned int __machine_arch_type; # define machine_is_pgs_v1() (0) #endif -#ifdef CONFIG_MACH_COLIBRI_TEGRA2 +#ifdef CONFIG_MACH_COLIBRI_T20 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_COLIBRI_TEGRA2 +# define machine_arch_type MACH_TYPE_COLIBRI_T20 # endif -# define machine_is_colibri_tegra2() (machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2) +# define machine_is_colibri_t20() (machine_arch_type == MACH_TYPE_COLIBRI_T20) #else -# define machine_is_colibri_tegra2() (0) +# define machine_is_colibri_t20() (0) #endif #ifdef CONFIG_MACH_W21 diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h deleted file mode 100644 index 835ca7e4b6..0000000000 --- a/arch/arm/include/asm/semihosting.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2014 Broadcom Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SEMIHOSTING_H__ -#define __SEMIHOSTING_H__ - -/* - * ARM semihosting functions for loading images to memory. See the source - * code for more information. - */ -int smh_load(const char *fname, void *memp, int avail, int verbose); -long smh_len(const char *fname); - -#endif /* __SEMIHOSTING_H__ */ diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 77563967e5..1654011432 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -62,9 +62,18 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) - sub x0, x0, #GD_SIZE /* allocate one GD above SP */ + sub x18, x0, #GD_SIZE /* allocate one GD above SP */ + bic x18, x18, #0x7 /* 8-byte alignment for GD */ +zero_gd: + sub x0, x0, #0x8 + str xzr, [x0] + cmp x0, x18 + b.gt zero_gd +#if defined(CONFIG_SYS_MALLOC_F_LEN) + sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN + str x0, [x18, #GD_MALLOC_BASE] +#endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - mov x18, sp /* GD is above SP */ mov x0, #0 bl board_init_f diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index fd6d8573f5..c3e964eabc 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -13,7 +13,7 @@ * for them. */ #include <common.h> -#include <asm/semihosting.h> +#include <command.h> #define SYSOPEN 0x01 #define SYSCLOSE 0x02 @@ -26,7 +26,7 @@ /* * Call the handler */ -static long smh_trap(unsigned int sysnum, void *addr) +static noinline long smh_trap(unsigned int sysnum, void *addr) { register long result asm("r0"); #if defined(CONFIG_ARM64) @@ -144,93 +144,71 @@ static long smh_len_fd(long fd) return ret; } -/* - * Open, load a file into memory, and close it. Check that the available space - * is sufficient to store the entire file. Return the bytes actually read from - * the file as seen by the read function. The verbose flag enables some extra - * printing of successful read status. - */ -int smh_load(const char *fname, void *memp, int avail, int verbose) +static int smh_load_file(const char * const name, ulong load_addr, + ulong *end_addr) { - long ret; long fd; - size_t len; - - ret = -1; - - debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname, - avail, memp); + long len; + long ret; - /* Open the file */ - fd = smh_open(fname, "rb"); + fd = smh_open(name, "rb"); if (fd == -1) return -1; - /* Get the file length */ - ret = smh_len_fd(fd); - if (ret == -1) { - smh_close(fd); - return -1; - } - - /* Check that the file will fit in the supplied buffer */ - if (ret > avail) { - printf("%s: ERROR ret %ld, avail %u\n", __func__, ret, - avail); + len = smh_len_fd(fd); + if (len < 0) { smh_close(fd); return -1; } - len = ret; + ret = smh_read(fd, (void *)load_addr, len); + smh_close(fd); - /* Read the file into the buffer */ - ret = smh_read(fd, memp, len); if (ret == 0) { - /* Print successful load information if requested */ - if (verbose) { - printf("\n%s\n", fname); - printf(" 0x%8p dest\n", memp); - printf(" 0x%08lx size\n", len); - printf(" 0x%08x avail\n", avail); - } + *end_addr = load_addr + len - 1; + printf("loaded file %s from %08lX to %08lX, %08lX bytes\n", + name, + load_addr, + *end_addr, + len); + } else { + printf("read failed\n"); + return 0; } - /* Close the file */ - smh_close(fd); - - return ret; + return 0; } -/* - * Get the file length from the filename - */ -long smh_len(const char *fname) +static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - long ret; - long fd; - long len; - - debug("%s: file \'%s\'\n", __func__, fname); - - /* Open the file */ - fd = smh_open(fname, "rb"); - if (fd < 0) - return fd; - - /* Get the file length */ - len = smh_len_fd(fd); - if (len < 0) { - smh_close(fd); - return len; + if (argc == 3 || argc == 4) { + ulong load_addr; + ulong end_addr = 0; + ulong ret; + char end_str[64]; + + load_addr = simple_strtoul(argv[2], NULL, 16); + if (!load_addr) + return -1; + + ret = smh_load_file(argv[1], load_addr, &end_addr); + if (ret < 0) + return 1; + + /* Optionally save returned end to the environment */ + if (argc == 4) { + sprintf(end_str, "0x%08lx", end_addr); + setenv(argv[3], end_str); + } + } else { + return CMD_RET_USAGE; } - - /* Close the file */ - ret = smh_close(fd); - if (ret < 0) - return ret; - - debug("%s: returning len %ld\n", __func__, len); - - /* Return the file length (or -1 error indication) */ - return len; + return 0; } + +U_BOOT_CMD(smhload, 4, 0, do_smhload, "load a file using semihosting", + "<file> 0x<address> [end var]\n" + " - load a semihosted file to the address specified\n" + " if the optional [end var] is specified, the end\n" + " address of the file will be stored in this environment\n" + " variable.\n"); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 30945c101b..30c4e17ec9 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -66,6 +66,7 @@ config TARGET_STAMP9G20 config TARGET_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK board" select CPU_ARM926EJS + select SUPPORT_SPL config TARGET_PM9G45 bool "Ronetix pm9g45 board" @@ -74,6 +75,7 @@ config TARGET_PM9G45 config TARGET_AT91SAM9N12EK bool "Atmel AT91SAM9N12-EK board" select CPU_ARM926EJS + select SUPPORT_SPL config TARGET_AT91SAM9RLEK bool "Atmel at91sam9rl reference board" @@ -82,6 +84,7 @@ config TARGET_AT91SAM9RLEK config TARGET_AT91SAM9X5EK bool "Atmel AT91SAM9X5-EK board" select CPU_ARM926EJS + select SUPPORT_SPL config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index e596ba6ce8..0d3ee48493 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -2,6 +2,8 @@ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o ifneq ($(CONFIG_SPL_BUILD),) obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o +obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o +obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o obj-y += spl.o diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index f363982d03..8d6934e324 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -195,50 +195,52 @@ int at91_clock_init(unsigned long main_clock) void at91_plla_init(u32 pllar) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; writel(pllar, &pmc->pllar); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } + while (!(readl(&pmc->sr) & AT91_PMC_LOCKA)) + ; } void at91_pllb_init(u32 pllbr) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; writel(pllbr, &pmc->pllbr); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } + while (!(readl(&pmc->sr) & AT91_PMC_LOCKB)) + ; } void at91_mck_init(u32 mckr) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; u32 tmp; tmp = readl(&pmc->mckr); - tmp &= ~(AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); + tmp &= ~AT91_PMC_MCKR_PRES_MASK; + tmp |= mckr & AT91_PMC_MCKR_PRES_MASK; writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { - timeout--; - if (timeout == 0) - break; - } + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_MDIV_MASK; + tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK; + tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_MCKR_CSS_MASK; + tmp |= mckr & AT91_PMC_MCKR_CSS_MASK; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; } void at91_periph_clk_enable(int id) diff --git a/arch/arm/mach-at91/arm926ejs/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c index b0b7fb93fb..31ce646260 100644 --- a/arch/arm/mach-at91/arm926ejs/timer.c +++ b/arch/arm/mach-at91/arm926ejs/timer.c @@ -33,22 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define TIMER_LOAD_VAL 0xfffff -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - /* * Use the PITC in full 32 bit incrementing mode */ @@ -64,54 +48,11 @@ int timer_init(void) writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; - gd->arch.tbu = gd->arch.tbl = 0; return 0; } /* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; - - ulong now = readl(&pit->piir); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* * Return the number of timer ticks per second. */ ulong get_tbclk(void) diff --git a/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds new file mode 100644 index 0000000000..acadd1d4c4 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/u-boot-spl.lds @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2015 Atmel Corporation + * Bo Shen <voice.shen@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/arm926ejs/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .end : + { + *(.__end) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} diff --git a/arch/arm/mach-at91/armv7/timer.c b/arch/arm/mach-at91/armv7/timer.c index 19bf80ba7e..a4a3817aa6 100644 --- a/arch/arm/mach-at91/armv7/timer.c +++ b/arch/arm/mach-at91/armv7/timer.c @@ -36,22 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #define TIMER_LOAD_VAL 0xfffff -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - /* * Use the PITC in full 32 bit incrementing mode */ @@ -67,55 +51,10 @@ int timer_init(void) gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; - gd->arch.tbu = 0; - gd->arch.tbl = 0; - return 0; } /* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; - - ulong now = readl(&pit->piir); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* * Return the number of timer ticks per second. */ ulong get_tbclk(void) diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 65691aba01..ebb7decd22 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -97,7 +97,8 @@ typedef struct at91_pmc { #define AT91_PMC_MCKR_CSS_PLLB 0x00000003 #define AT91_PMC_MCKR_CSS_MASK 0x00000003 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_PRES_1 0x00000000 #define AT91_PMC_MCKR_PRES_2 0x00000010 #define AT91_PMC_MCKR_PRES_4 0x00000020 @@ -126,7 +127,8 @@ typedef struct at91_pmc { #else #define AT91_PMC_MCKR_MDIV_1 0x00000000 #define AT91_PMC_MCKR_MDIV_2 0x00000100 -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) #define AT91_PMC_MCKR_MDIV_3 0x00000300 #endif #define AT91_PMC_MCKR_MDIV_4 0x00000200 diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 8950d67409..1a4e84b050 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -133,6 +133,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 6dfcf4c0c8..914a3b0460 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -117,6 +117,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index 64a3888e22..71675abf82 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -132,6 +132,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 6df8cdb56d..cf1c73f3d9 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -136,6 +136,9 @@ #define ATMEL_BASE_CS6 0x70000000 #define ATMEL_BASE_CS7 0x80000000 +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 3a8e6d62ce..70bbf4edaa 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -116,6 +116,9 @@ #define ATMEL_BASE_CS4 0x50000000 /* Compact Flash Slot 0 */ #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 36a5cdf476..8100ebed4b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -124,6 +124,16 @@ #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ #endif +/* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 + /* 9x5 series chip id definitions */ #define ARCH_ID_AT91SAM9X5 0x819a05a0 #define ARCH_ID_VERSION_MASK 0x1f @@ -154,6 +164,9 @@ #define ATMEL_CPU_NAME get_cpu_name() #endif +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c + /* * Other misc defines */ diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 227ba80825..b749cb3359 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -189,6 +189,9 @@ #define PIO_SCDR_DIV 0x3fff #define CPU_HAS_PCR +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c + /* * PMECC table in ROM */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index f30cb5fed1..7773ace439 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -193,6 +193,9 @@ #define cpu_is_sama5d44() (cpu_is_sama5d4() && \ (get_extension_chip_id() == ARCH_EXID_SAMA5D44)) +/* Timer */ +#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c + /* * No PMECC Galois table in ROM */ diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index beec13db8c..e2b6a49eb9 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -19,7 +19,8 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address) static int ddr2_decodtype_is_seq(u32 cr) { -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \ + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) return 0; #endif diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c index aaa5eec2e6..27a405a42b 100644 --- a/arch/arm/mach-at91/spl.c +++ b/arch/arm/mach-at91/spl.c @@ -29,7 +29,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; #elif CONFIG_SYS_USE_NANDFLASH return BOOT_DEVICE_NAND; -#elif CONFIG_SYS_USE_SERIALFLASH +#elif CONFIG_SYS_USE_SERIALFLASH || CONFIG_SYS_USE_SPIFLASH return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_NONE; diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index 89f588be45..a79a9dce75 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -71,7 +71,11 @@ void __weak at91_spl_board_init(void) { } -void spl_board_init(void) +void __weak spl_board_init(void) +{ +} + +void board_init_f(ulong dummy) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; @@ -111,9 +115,14 @@ void spl_board_init(void) timer_init(); /* enable clocks for all PIOs */ +#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) + at91_periph_clk_enable(ATMEL_ID_PIOAB); + at91_periph_clk_enable(ATMEL_ID_PIOCD); +#else at91_periph_clk_enable(ATMEL_ID_PIOA); at91_periph_clk_enable(ATMEL_ID_PIOB); at91_periph_clk_enable(ATMEL_ID_PIOC); +#endif /* init console */ at91_seriald_hw_init(); preloader_console_init(); diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 9cc1111234..8ac53353e6 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -70,8 +70,13 @@ __weak void redirect_int_from_saic_to_aic(void) /* This only be used for sama5d4 soc now */ } +/* empty stub to satisfy current lowlevel_init, can be removed any time */ void s_init(void) { +} + +void board_init_f(ulong dummy) +{ switch_to_main_crystal_osc(); /* disable watchdog */ @@ -93,4 +98,9 @@ void s_init(void) preloader_console_init(); mem_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); } diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig new file mode 100644 index 0000000000..b43f2d91fd --- /dev/null +++ b/arch/arm/mach-bcm283x/Kconfig @@ -0,0 +1,40 @@ +menu "Broadcom BCM283X family" + depends on ARCH_BCM283X + +choice + prompt "Broadcom BCM283X board select" + +config TARGET_RPI + bool "Raspberry Pi" + select CPU_ARM1176 + +config TARGET_RPI_2 + bool "Raspberry Pi 2" + select CPU_V7 + +endchoice + +config DM + default y + +config DM_SERIAL + default y + +config DM_GPIO + default y + +config SYS_BOARD + default "rpi" if TARGET_RPI + default "rpi_2" if TARGET_RPI_2 + +config SYS_VENDOR + default "raspberrypi" + +config SYS_SOC + default "bcm283x" + +config SYS_CONFIG_NAME + default "rpi" if TARGET_RPI + default "rpi_2" if TARGET_RPI_2 + +endmenu diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/mach-bcm283x/Makefile index 7e5dbe1fde..2505428bab 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/mach-bcm283x/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := lowlevel_init.o +obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o obj-y += init.o reset.o timer.o mbox.o diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h index c8ef8f528a..c8ef8f528a 100644 --- a/arch/arm/include/asm/arch-bcm2835/gpio.h +++ b/arch/arm/mach-bcm283x/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 04bf480a54..54d369c46c 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h @@ -132,7 +132,7 @@ struct bcm2835_mbox_tag_hdr { * 0x2..0xf from: * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733 - * 0x10, 0x11 from swarren's testing + * http://git.drogon.net/?p=wiringPi;a=blob_plain;f=wiringPi/wiringPi.c;hb=5edd177112c99416f68ba3e8c6c4db6ed942e796 */ #define BCM2835_BOARD_REV_B_I2C0_2 0x2 #define BCM2835_BOARD_REV_B_I2C0_3 0x3 @@ -148,6 +148,8 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_BOARD_REV_B_PLUS 0x10 #define BCM2835_BOARD_REV_CM 0x11 #define BCM2835_BOARD_REV_A_PLUS 0x12 +#define BCM2835_BOARD_REV_B_PLUS_13 0x13 +#define BCM2835_BOARD_REV_CM_14 0x14 #endif struct bcm2835_mbox_tag_get_board_rev { diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h index 2a21ccbf66..2a21ccbf66 100644 --- a/arch/arm/include/asm/arch-bcm2835/sdhci.h +++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h index fc7aec7b7c..fc7aec7b7c 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/mach-bcm283x/include/mach/timer.h diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h index beb6a08206..beb6a08206 100644 --- a/arch/arm/include/asm/arch-bcm2835/wdog.h +++ b/arch/arm/mach-bcm283x/include/mach/wdog.h diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/mach-bcm283x/init.c index e90d3bba1f..e90d3bba1f 100644 --- a/arch/arm/cpu/arm1176/bcm2835/init.c +++ b/arch/arm/mach-bcm283x/init.c diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/mach-bcm283x/lowlevel_init.S index c7b0843281..c7b0843281 100644 --- a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S +++ b/arch/arm/mach-bcm283x/lowlevel_init.S diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/mach-bcm283x/mbox.c index 3b17a31eac..3b17a31eac 100644 --- a/arch/arm/cpu/arm1176/bcm2835/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/mach-bcm283x/reset.c index 8c37ad9fd4..8c37ad9fd4 100644 --- a/arch/arm/cpu/arm1176/bcm2835/reset.c +++ b/arch/arm/mach-bcm283x/reset.c diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/mach-bcm283x/timer.c index 017907cfb8..017907cfb8 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/mach-bcm283x/timer.c diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fccfd79648..fce1c1dc87 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -17,9 +17,6 @@ config TEGRA124 endchoice -config SYS_MALLOC_F - default y - config SYS_MALLOC_F_LEN default 0x1800 diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S index a211bb3b1a..4bc0a3f5a1 100644 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ b/arch/arm/mach-tegra/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> #include <linux/linkage.h> .align 5 diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 912f65e98b..b4a1432afc 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -108,6 +108,8 @@ #define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4)) +#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4)) + /* * We could force arch-tegraNN/pinmux.h to define all of these. However, * that's a lot of defines, and for now it's manageable to just put a @@ -695,4 +697,59 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, for (i = 0; i < len; i++) pinmux_config_drvgrp(&config[i]); } -#endif /* TEGRA_PMX_HAS_DRVGRPS */ +#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ + +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS + +#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT)) + +static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp, + enum pmux_func func) +{ + u32 *reg = MIPIPADCTRL_REG(grp); + int i, mux = -1; + u32 val; + + if (func == PMUX_FUNC_DEFAULT) + return; + + /* Error check grp and func */ + assert(pmux_mipipadctrlgrp_isvalid(grp)); + assert(pmux_func_isvalid(func)); + + if (func >= PMUX_FUNC_RSVD1) { + mux = (func - PMUX_FUNC_RSVD1) & 1; + } else { + /* Search for the appropriate function */ + for (i = 0; i < 2; i++) { + if (tegra_soc_mipipadctrl_groups[grp].funcs[i] + == func) { + mux = i; + break; + } + } + } + assert(mux != -1); + + val = readl(reg); + val &= ~(1 << 1); + val |= (mux << 1); + writel(val, reg); +} + +static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config) +{ + enum pmux_mipipadctrlgrp grp = config->grp; + + pinmux_mipipadctrl_set_func(grp, config->func); +} + +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_mipipadctrlgrp(&config[i]); +} +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c index c6685eaae1..4629b4676c 100644 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ b/arch/arm/mach-tegra/tegra124/pinmux.c @@ -304,3 +304,20 @@ static const struct pmux_pingrp_desc tegra124_pingroups[] = { PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4), }; const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups; + +#define MIPIPADCTRL_GRP(grp, f0, f1) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + }, \ + } + +#define MIPIPADCTRL_RESERVED {} + +static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = { + /* pin, f0, f1 */ + /* Offset 0x820 */ + MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B), +}; +const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index a354e2ad1f..7f09f819cc 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -30,7 +30,7 @@ config TARGET_VENTANA config TARGET_WHISTLER bool "NVIDIA Tegra20 Whistler evaluation board" -config TARGET_COLIBRI_T20_IRIS +config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" endchoice @@ -47,6 +47,6 @@ source "board/avionic-design/tec/Kconfig" source "board/compulab/trimslice/Kconfig" source "board/nvidia/ventana/Kconfig" source "board/nvidia/whistler/Kconfig" -source "board/toradex/colibri_t20_iris/Kconfig" +source "board/toradex/colibri_t20/Kconfig" endif diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 0df4a0738d..44a85c5f1d 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c @@ -252,12 +252,14 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCB); pinmux_tristate_disable(PMUX_PINGRP_KBCC); pinmux_tristate_disable(PMUX_PINGRP_KBCD); pinmux_tristate_disable(PMUX_PINGRP_KBCE); diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c index a29c76b1fa..a29c76b1fa 100644 --- a/arch/arm/cpu/tegra210-common/pinmux.c +++ b/arch/arm/mach-tegra/tegra210/pinmux.c diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 8335685e32..288e6aba79 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -1,9 +1,6 @@ menu "Panasonic UniPhier platform" depends on ARCH_UNIPHIER -config SYS_SOC - default "uniphier" - config SYS_CONFIG_NAME default "uniphier" @@ -48,12 +45,6 @@ config DCC_MICRO_SUPPORT_CARD endchoice -config SYS_MALLOC_F - default y - -config SYS_MALLOC_F_LEN - default 0x400 - config CMD_PINMON bool "Enable boot mode pins monitor command" default y diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index e7a801b2ac..24591d6ee5 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -12,6 +12,7 @@ obj-y += ddrphy_training.o else +obj-y += late_lowlevel_init.o obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o @@ -21,7 +22,6 @@ obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o obj-y += cache_uniphier.o -obj-$(CONFIG_UNIPHIER_SMP) += smp.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index 52f3c7c7a6..d8b8228853 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -119,36 +120,7 @@ void v7_outer_cache_disable(void) writel(tmp, SSCC); } -void wakeup_secondary(void); - void enable_caches(void) { - uint32_t reg; - -#ifdef CONFIG_UNIPHIER_SMP - /* - * The secondary CPU must move to DDR, - * before L2 disable. - * On SPL, the Page Table is located on the L2. - */ - wakeup_secondary(); -#endif - /* - * UniPhier SoCs must use L2 cache for init stack pointer. - * We disable L2 and L1 in this order. - * If CONFIG_SYS_DCACHE_OFF is not defined, - * caches are enabled again with a new page table. - */ - - /* L2 disable */ - v7_outer_cache_disable(); - - /* L1 disable */ - reg = get_cr(); - reg &= ~(CR_C | CR_M); - set_cr(reg); - -#ifndef CONFIG_SYS_DCACHE_OFF dcache_enable(); -#endif } diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S index 2638bcd779..ac2959a17d 100644 --- a/arch/arm/mach-uniphier/init_page_table.S +++ b/arch/arm/mach-uniphier/init_page_table.S @@ -1,3 +1,11 @@ +/* + * Copyright (C) 2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #include <config.h> #include <linux/linkage.h> @@ -8,7 +16,7 @@ #define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ #define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT)) -#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT)) +#define STACK_SECTION ((CONFIG_SPL_STACK) >> (SECTION_SHIFT)) .section ".rodata" .align 14 diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S new file mode 100644 index 0000000000..1363364c80 --- /dev/null +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <mach/ssc-regs.h> + +ENTRY(lowlevel_init) + ldr r1, = SSCC + ldr r0, [r1] + bic r0, r0, #SSCC_ON @ L2 disable + str r0, [r1] + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 92299fe64d..825b160762 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -1,6 +1,7 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -24,8 +25,8 @@ ENTRY(lowlevel_init) * First we need to turn on MMU and Dcache again to get back * data access to L2. */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) - orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) + orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 #ifdef CONFIG_DEBUG_LL @@ -40,13 +41,32 @@ ENTRY(lowlevel_init) ldr r3, =init_page_table @ page table must be 16KB aligned /* Disable MMU and Dcache before switching Page Table */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 bl enable_mmu #ifdef CONFIG_UNIPHIER_SMP +secondary_startup: + /* + * Entry point for secondary CPUs + * + * The Boot ROM has already enabled MMU for the secondary CPUs as well + * as for the primary one. The MMU table embedded in the Boot ROM + * prohibits the DRAM access, so it is impossible to bring the + * secondary CPUs into DRAM directly. They must jump here into SPL, + * which is run on L2 cache. + * + * Boot Sequence + * [primary CPU] [secondary CPUs] + * start from Boot ROM start from Boot ROM + * jump to SPL sleep in Boot ROM + * kick secondaries ---(sev)---> jump to SPL + * jump to U-Boot main sleep in SPL + * jump to Linux + * kick secondaries ---(sev)---> jump to Linux + */ /* * ACTLR (Auxiliary Control Register) for Cortex-A9 * bit[9] Parity on @@ -54,7 +74,7 @@ ENTRY(lowlevel_init) * bit[7] EXCL (Exclusive cache bit) * bit[6] SMP * bit[3] Write full line of zeros mode - * bit[2] L1 Prefetch enable + * bit[2] L1 prefetch enable * bit[1] L2 prefetch enable * bit[0] FW (Cache and TLB maintenance broadcast) */ @@ -67,20 +87,31 @@ ENTRY(lowlevel_init) and r0, r0, #0x3 cmp r0, #0x0 beq primary_cpu - ldr r1, =ROM_BOOT_ROMRSV2 + /* only for secondary CPUs */ + ldr r1, =ROM_BOOT_ROMRSV2 @ The last data access to L2 cache + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) + orr r0, r0, #CR_I @ Enable ICache + bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache must be disabled + mcr p15, 0, r0, c1, c0, 0 @ before jumping to Linux mov r0, #0 str r0, [r1] -0: wfe - ldr r0, [r1] + b 1f + /* + * L2 cache is shared among all the CPUs and it might be disabled by + * the primary one. Before that, the following 5 lines must be cached + * on the Icaches of the secondary CPUs. + */ +0: wfe @ kicked by Linux +1: ldr r0, [r1] cmp r0, #0 - beq 0b - bx r0 @ r0: entry point of U-Boot main for the secondary CPU + bxne r0 @ r0: Linux entry for secondary CPUs + b 0b primary_cpu: ldr r1, =ROM_BOOT_ROMRSV2 - ldr r0, =_start @ entry for the secondary CPU + ldr r0, =secondary_startup str r0, [r1] ldr r0, [r1] @ make sure str is complete before sev - sev @ kick the sedoncary CPU + sev @ kick the secondary CPU mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register bfc r1, #0, #13 @ clear bit 12-0 mov r0, #-1 @@ -117,7 +148,7 @@ ENTRY(enable_mmu) * TLBs was already invalidated in "../start.S" * So, we don't need to invalidate it here. */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable mcr p15, 0, r0, c1, c0, 0 @@ -142,7 +173,7 @@ ENTRY(setup_init_ram) ldr r0, = 0x00408006 @ touch to zero with address range ldr r1, = SSCOQM str r0, [r1] - ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address + ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address ldr r1, = SSCOQAD str r0, [r1] ldr r0, = BOOT_RAM_SIZE @@ -154,7 +185,7 @@ ENTRY(setup_init_ram) ldr r1, = SSCOPPQSEF ldr r0, [r1] cmp r0, #0 @ check if the command is successfully set - bne 0b @ try again if an error occurres + bne 0b @ try again if an error occurs ldr r1, = SSCOLPQS 1: diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile index 5ce3d8a520..af815c3260 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/Makefile +++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile @@ -5,12 +5,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_SPL_DM) += platdevice.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c new file mode 100644 index 0000000000..e5e86bb363 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ + sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ + + sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ + sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ + + sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ + sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c index 15d81ebb3d..3074d0a8d2 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -14,20 +14,6 @@ void pin_init(void) /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ - sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ - - sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ - sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ - - sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ - sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */ sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */ diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile index b88525c82d..f6a584e1f0 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/Makefile +++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile @@ -5,12 +5,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_SPL_DM) += platdevice.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c new file mode 100644 index 0000000000..85bb6a0b9c --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ + sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ + sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ + sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ + sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ + sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ + sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c index f382ef4842..4df9098ef0 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -12,17 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ - sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ - sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ - sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ - sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ - sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ - sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */ sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */ diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile index 5ce3d8a520..8eb575e1d3 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/Makefile +++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile @@ -1,16 +1 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o -obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o -endif - -obj-y += boot-mode.o +include $(src)/../ph1-ld4/Makefile diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c new file mode 100644 index 0000000000..28cc4296fc --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ + sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ + + sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ + + sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ + sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c index 4c494ffa40..57a8093048 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -12,20 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ - sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ - - sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ - - sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ - sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_SYS_I2C_UNIPHIER { u32 tmp; diff --git a/arch/arm/mach-uniphier/smp.S b/arch/arm/mach-uniphier/smp.S deleted file mode 100644 index 18e3a9d21e..0000000000 --- a/arch/arm/mach-uniphier/smp.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2013 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/linkage.h> -#include <asm/system.h> -#include <mach/led.h> -#include <mach/sbc-regs.h> - -/* Entry point of U-Boot main program for the secondary CPU */ -LENTRY(secondary_entry) - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) - bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable - mcr p15, 0, r0, c1, c0, 0 - mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs - mcr p15, 0, r0, c7, c5, 0 @ invalidate icache - dsb - led_write(C,0,,) - ldr r1, =ROM_BOOT_ROMRSV2 - mov r0, #0 - str r0, [r1] -0: wfe - ldr r4, [r1] @ r4: entry point for secondary CPUs - cmp r4, #0 - beq 0b - led_write(C, P, U, 1) - bx r4 @ secondary CPUs jump to linux -ENDPROC(secondary_entry) - -ENTRY(wakeup_secondary) - ldr r1, =ROM_BOOT_ROMRSV2 -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - - /* set entry address and send event to the secondary CPU */ - ldr r0, =secondary_entry - str r0, [r1] - ldr r0, [r1] @ make sure store is complete - mov r0, #0x100 -0: subs r0, r0, #1 @ I don't know the reason, but without this wait - bne 0b @ fails to wake up the secondary CPU - sev - - /* wait until the secondary CPU reach to secondary_entry */ -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - bx lr -ENDPROC(wakeup_secondary) diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c index c3d90d03d0..a34d3a167c 100644 --- a/arch/arm/mach-uniphier/spl.c +++ b/arch/arm/mach-uniphier/spl.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2013-2015 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,6 +21,7 @@ void pll_init(void); void pin_init(void); void memconf_init(void); void early_clkrst_init(void); +void early_pin_init(void); int umc_init(void); void enable_dpll_ssc(void); @@ -47,6 +49,16 @@ void spl_board_init(void) led_write(L, 2, , ); + early_pin_init(); + + led_write(L, 3, , ); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_write(L, 4, , ); + { int res; @@ -56,9 +68,9 @@ void spl_board_init(void) ; } } - led_write(L, 3, , ); + led_write(L, 5, , ); enable_dpll_ssc(); - led_write(L, 4, , ); + led_write(L, 6, , ); } diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c index e7b4158636..77cc794e61 100644 --- a/arch/arm/mach-uniphier/support_card.c +++ b/arch/arm/mach-uniphier/support_card.c @@ -1,6 +1,7 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -94,7 +95,7 @@ void support_card_init(void) /* * After power on, we need to keep the LAN controller in reset state * for a while. (200 usec) - * Fortunatelly, enough wait time is already inserted in pll_init() + * Fortunately, enough wait time is already inserted in pll_init() * function. So we do not have to wait here. */ support_card_reset_deassert(); @@ -213,11 +214,11 @@ static void detect_num_flash_banks(void) debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); } -#else /* ONFIG_SYS_NO_FLASH */ +#else /* CONFIG_SYS_NO_FLASH */ void detect_num_flash_banks(void) { }; -#endif /* ONFIG_SYS_NO_FLASH */ +#endif /* CONFIG_SYS_NO_FLASH */ void support_card_late_init(void) { diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 8252f598c3..469185e8b4 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -9,9 +9,6 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := avr32-linux- endif -# avr32 has generic board support -__HAVE_ARCH_GENERIC_BOARD := y - CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 584b38b17a..7b17b75743 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -20,9 +20,6 @@ CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%)) endif CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%)) -# Support generic board on Blackfin -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic LDFLAGS_FINAL += --gc-sections diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 73cbfa2cc8..d2cf71bfaf 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -174,7 +174,6 @@ } #endif -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO #define CONFIG_ARCH_MISC_INIT diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 53c4aabe1e..69cb0f73eb 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -4,71 +4,200 @@ menu "M68000 architecture" config SYS_ARCH default "m68k" +# processor family +config MCF520x + bool + +config MCF52x2 + bool + +config MCF523x + bool + +config MCF530x + bool + +config MCF5301x + bool + +config MCF532x + bool + +config MCF537x + bool + +config MCF5441x + bool + +config MCF5445x + bool + +config MCF5227x + bool + +config MCF547x_8x + bool + +# processor type +config M5208 + bool + select MCF520x + +config M5235 + bool + select MCF523x + +config M5249 + bool + select MCF52x2 + +config M5253 + bool + select MCF52x2 + +config M5271 + bool + select MCF52x2 + +config M5272 + bool + select MCF52x2 + +config M5275 + bool + select MCF52x2 + +config M5282 + bool + select MCF52x2 + +config M5307 + bool + select MCF530x + +config M53015 + bool + select MCF5301x + +config M5329 + bool + select MCF532x + +config M5373 + bool + select MCF532x + select MCF537x + +config M54418 + bool + select MCF5441x + +config M54451 + bool + select MCF5445x + +config M54455 + bool + select MCF5445x + +config M52277 + bool + select MCF5227x + +config M547x + bool + select MCF547x_8x + +config M548x + bool + select MCF547x_8x + choice prompt "Target select" config TARGET_M52277EVB bool "Support M52277EVB" + select M52277 config TARGET_M5235EVB bool "Support M5235EVB" + select M5235 config TARGET_COBRA5272 bool "Support cobra5272" + select M5272 config TARGET_EB_CPU5282 bool "Support eb_cpu5282" + select M5282 config TARGET_M5208EVBE bool "Support M5208EVBE" + select M5208 config TARGET_M5249EVB bool "Support M5249EVB" + select M5249 config TARGET_M5253DEMO bool "Support M5253DEMO" + select M5253 config TARGET_M5253EVBE bool "Support M5253EVBE" + select M5253 config TARGET_M5272C3 bool "Support M5272C3" + select M5272 config TARGET_M5275EVB bool "Support M5275EVB" + select M5275 config TARGET_M5282EVB bool "Support M5282EVB" + select M5282 config TARGET_ASTRO_MCF5373L bool "Support astro_mcf5373l" + select M5373 config TARGET_M53017EVB bool "Support M53017EVB" + select M53015 config TARGET_M5329EVB bool "Support M5329EVB" + select M5329 config TARGET_M5373EVB bool "Support M5373EVB" + select M5373 config TARGET_M54418TWR bool "Support M54418TWR" + select M54418 config TARGET_M54451EVB bool "Support M54451EVB" + select M54451 config TARGET_M54455EVB bool "Support M54455EVB" + select M54455 config TARGET_M5475EVB bool "Support M5475EVB" + select M547x config TARGET_M5485EVB bool "Support M5485EVB" + select M548x config TARGET_AMCORE bool "Support AMCORE" + select M5307 endchoice diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index aa3d2fae63..e6f3b482c3 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -6,3 +6,32 @@ head-y := arch/m68k/cpu/$(CPU)/start.o libs-y += arch/m68k/cpu/$(CPU)/ libs-y += arch/m68k/lib/ + +cpuflags-$(CONFIG_M5208) := -mcpu=5208 +cpuflags-$(CONFIG_M5235) := -mcpu=5235 -fPIC +cpuflags-$(CONFIG_M52277) := -mcpu=52277 -fPIC +cpuflags-$(CONFIG_M5249) := -mcpu=5249 +cpuflags-$(CONFIG_M5253) := -mcpu=5253 +cpuflags-$(CONFIG_M5271) := -mcpu=5271 +cpuflags-$(CONFIG_M5272) := -mcpu=5272 +cpuflags-$(CONFIG_M5275) := -mcpu=5275 +cpuflags-$(CONFIG_M5282) := -mcpu=5282 +cpuflags-$(CONFIG_M5307) := -mcpu=5307 +cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC +cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC +cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC +cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC +cpuflags-$(CONFIG_MCF547x_8x) := -mcpu=5485 -fPIC + +PLATFORM_CPPFLAGS += $(cpuflags-y) + + +ldflags-$(CONFIG_MCF5441x) := --got=single +ldflags-$(CONFIG_MCF5445x) := --got=single +ldflags-$(CONFIG_MCF547x_8x) := --got=single + +ifneq (,$(findstring -linux-,$(shell $(CC) --version))) +ifneq (,$(findstring GOT,$(shell $(LD) --help))) +PLATFORM_LDFLAGS += $(ldflags-y) +endif +endif diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index a629b68d61..3b3a7e88ab 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -11,9 +11,6 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 -# Support generic board on m68k -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_CPPFLAGS += -D__M68K__ PLATFORM_LDFLAGS += -n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/m68k/cpu/mcf5227x/config.mk b/arch/m68k/cpu/mcf5227x/config.mk deleted file mode 100644 index b5c26e4e5b..0000000000 --- a/arch/m68k/cpu/mcf5227x/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC diff --git a/arch/m68k/cpu/mcf523x/config.mk b/arch/m68k/cpu/mcf523x/config.mk deleted file mode 100644 index c9435ab99b..0000000000 --- a/arch/m68k/cpu/mcf523x/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC diff --git a/arch/m68k/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk deleted file mode 100644 index f66000b331..0000000000 --- a/arch/m68k/cpu/mcf52x2/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5208:=$(shell grep CONFIG_M5208 $(cfg)) -is5249:=$(shell grep CONFIG_M5249 $(cfg)) -is5253:=$(shell grep CONFIG_M5253 $(cfg)) -is5271:=$(shell grep CONFIG_M5271 $(cfg)) -is5272:=$(shell grep CONFIG_M5272 $(cfg)) -is5275:=$(shell grep CONFIG_M5275 $(cfg)) -is5282:=$(shell grep CONFIG_M5282 $(cfg)) - -ifneq (,$(findstring CONFIG_M5208,$(is5208))) -PLATFORM_CPPFLAGS += -mcpu=5208 -endif -ifneq (,$(findstring CONFIG_M5249,$(is5249))) -PLATFORM_CPPFLAGS += -mcpu=5249 -endif -ifneq (,$(findstring CONFIG_M5253,$(is5253))) -PLATFORM_CPPFLAGS += -mcpu=5253 -endif -ifneq (,$(findstring CONFIG_M5271,$(is5271))) -PLATFORM_CPPFLAGS += -mcpu=5271 -endif -ifneq (,$(findstring CONFIG_M5272,$(is5272))) -PLATFORM_CPPFLAGS += -mcpu=5272 -endif -ifneq (,$(findstring CONFIG_M5275,$(is5275))) -PLATFORM_CPPFLAGS += -mcpu=5275 -endif -ifneq (,$(findstring CONFIG_M5282,$(is5282))) -PLATFORM_CPPFLAGS += -mcpu=5282 -endif diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk deleted file mode 100644 index aef72d70c5..0000000000 --- a/arch/m68k/cpu/mcf530x/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5307:=$(shell grep CONFIG_M5307 $(cfg)) - -ifneq (,$(findstring CONFIG_M5307,$(is5307))) -PLATFORM_CPPFLAGS += -mcpu=5307 -endif diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk deleted file mode 100644 index 2efb60f04a..0000000000 --- a/arch/m68k/cpu/mcf532x/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5301x:=$(shell grep CONFIG_MCF5301x $(cfg)) -is532x:=$(shell grep CONFIG_MCF532x $(cfg)) - -ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) -PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC -endif -ifneq (,$(findstring CONFIG_MCF532x,$(is532x))) -PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC -endif diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk deleted file mode 100644 index 13f8a9f57b..0000000000 --- a/arch/m68k/cpu/mcf5445x/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright 2011-2012 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5441x:=$(shell grep CONFIG_MCF5441x $(cfg)) - -ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x))) -PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC -else -PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC -endif - -ifneq (,$(findstring -linux-,$(shell $(CC) --version))) -ifneq (,$(findstring GOT,$(shell $(LD) --help))) -PLATFORM_LDFLAGS += --got=single -endif -endif diff --git a/arch/m68k/cpu/mcf547x_8x/config.mk b/arch/m68k/cpu/mcf547x_8x/config.mk deleted file mode 100644 index 825f6ccebe..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC - -ifneq (,$(findstring -linux-,$(shell $(CC) --version))) -ifneq (,$(findstring GOT,$(shell $(LD) --help))) -PLATFORM_LDFLAGS += --got=single -endif -endif diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index 7590842881..e1458acd2c 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_NEEDS_MANUAL_RELOC diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index d0e1a845dd..73d40bda8b 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -5,9 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SYS_GENERIC_BOARD -obj-y += board.o -endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += interrupts.o diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c deleted file mode 100644 index 9caff73505..0000000000 --- a/arch/m68k/lib/board.c +++ /dev/null @@ -1,642 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner <josef.baumgartner@telex.de> - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <malloc.h> -#include <stdio_dev.h> -#include <linux/compiler.h> - -#include <asm/immap.h> - -#if defined(CONFIG_CMD_IDE) -#include <ide.h> -#endif -#if defined(CONFIG_CMD_SCSI) -#include <scsi.h> -#endif -#if defined(CONFIG_CMD_KGDB) -#include <kgdb.h> -#endif -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif -#include <net.h> -#include <serial.h> -#ifdef CONFIG_SYS_ALLOC_DPRAM -#include <commproc.h> -#endif -#include <version.h> - -#if defined(CONFIG_HARD_I2C) || \ - defined(CONFIG_SYS_I2C) -#include <i2c.h> -#endif - -#ifdef CONFIG_CMD_SPI -#include <spi.h> -#endif - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -#include <nand.h> - -DECLARE_GLOBAL_DATA_PTR; - -static char *failed = "*** failed ***\n"; - -#include <environment.h> - -extern ulong __init_end; -extern ulong __bss_end; - -#if defined(CONFIG_WATCHDOG) -# undef INIT_FUNC_WATCHDOG_INIT -# define INIT_FUNC_WATCHDOG_INIT watchdog_init, -# define WATCHDOG_DISABLE watchdog_disable - -extern int watchdog_init(void); -extern int watchdog_disable(void); -#else -# define INIT_FUNC_WATCHDOG_INIT /* undef */ -# define WATCHDOG_DISABLE /* undef */ -#endif /* CONFIG_WATCHDOG */ - -ulong monitor_flash_len; - -/************************************************************************ - * Utilities * - ************************************************************************ - */ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -/************************************************************************ - * Init Utilities - ************************************************************************ - * Some of this code should be moved into the core functions, - * but let's get it working (again) first... - */ - -static int init_baudrate (void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - -/***********************************************************************/ - -static int init_func_ram (void) -{ - int board_type = 0; /* use dummy arg */ - puts ("DRAM: "); - - if ((gd->ram_size = initdram (board_type)) > 0) { - print_size (gd->ram_size, "\n"); - return (0); - } - puts (failed); - return (1); -} - -/***********************************************************************/ - -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) -static int init_func_i2c (void) -{ - puts ("I2C: "); -#ifdef CONFIG_SYS_I2C - i2c_init_all(); -#else - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - puts ("ready\n"); - return (0); -} -#endif - -#if defined(CONFIG_HARD_SPI) -static int init_func_spi (void) -{ - puts ("SPI: "); - spi_init (); - puts ("ready\n"); - return (0); -} -#endif - -/***********************************************************************/ - -/************************************************************************ - * Initialization sequence * - ************************************************************************ - */ - -init_fnc_t *init_sequence[] = { - get_clocks, - env_init, - init_baudrate, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) - init_func_i2c, -#endif -#if defined(CONFIG_HARD_SPI) - init_func_spi, -#endif - init_func_ram, -#if defined(CONFIG_SYS_DRAM_TEST) - testdram, -#endif /* CONFIG_SYS_DRAM_TEST */ - INIT_FUNC_WATCHDOG_INIT - NULL, /* Terminate this list */ -}; - - -/************************************************************************ - * - * This is the first part of the initialization sequence that is - * implemented in C, but still running from ROM. - * - * The main purpose is to provide a (serial) console interface as - * soon as possible (so we can see any error messages), and to - * initialize the RAM so that we can relocate the monitor code to - * RAM. - * - * Be aware of the restrictions: global data is read-only, BSS is not - * initialized, and stack space is limited to a few kB. - * - ************************************************************************ - */ - -void -board_init_f (ulong bootflag) -{ - bd_t *bd; - ulong len, addr, addr_sp; - ulong *paddr; - gd_t *id; - init_fnc_t **init_fnc_ptr; -#ifdef CONFIG_PRAM - ulong reg; -#endif - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr)() != 0) { - hang (); - } - } - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - protected RAM - * - LCD framebuffer - * - monitor code - * - board info struct - */ - len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; - - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; - -#ifdef CONFIG_LOGBUFFER - /* reserve kernel log buffer */ - addr -= (LOGBUFF_RESERVE); - debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); -#endif - -#ifdef CONFIG_PRAM - /* - * reserve protected RAM - */ - reg = getenv_ulong("pram", 10, CONFIG_PRAM); - addr -= (reg << 10); /* size is in kB */ - debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); -#endif /* CONFIG_PRAM */ - - /* round down to next 4 kB limit */ - addr &= ~(4096 - 1); - debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); - -#ifdef CONFIG_LCD -#ifdef CONFIG_FB_ADDR - gd->fb_base = CONFIG_FB_ADDR; -#else - /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem (addr); - gd->fb_base = addr; -#endif /* CONFIG_FB_ADDR */ -#endif /* CONFIG_LCD */ - - /* - * reserve memory for U-Boot code, data & bss - * round down to next 4 kB limit - */ - addr -= len; - addr &= ~(4096 - 1); - - debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - - /* - * reserve memory for malloc() arena - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug ("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof (bd_t); - bd = (bd_t *) addr_sp; - gd->bd = bd; - debug ("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof (bd_t), addr_sp); - addr_sp -= sizeof (gd_t); - id = (gd_t *) addr_sp; - debug ("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof (gd_t), addr_sp); - - /* Reserve memory for boot params. */ - addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN; - bd->bi_boot_params = addr_sp; - debug ("Reserving %dk for boot parameters at: %08lx\n", - CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - - paddr = (ulong *)addr_sp; - *paddr-- = 0; - *paddr-- = 0; - addr_sp = (ulong)paddr; - - debug ("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */ - bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ -#ifdef CONFIG_SYS_INIT_RAM_ADDR - bd->bi_sramstart = CONFIG_SYS_INIT_RAM_ADDR; /* start of SRAM memory */ - bd->bi_sramsize = CONFIG_SYS_INIT_RAM_SIZE; /* size of SRAM memory */ -#endif - bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ - - bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ - - WATCHDOG_RESET (); - bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ - bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ -#ifdef CONFIG_PCI - bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */ -#endif -#ifdef CONFIG_EXTRA_CLOCK - bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ - bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ - bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ -#endif - -#ifdef CONFIG_SYS_EXTBDINFO - strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); - strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); -#endif - - WATCHDOG_RESET (); - -#ifdef CONFIG_POST - post_bootmode_init(); - post_run (NULL, POST_ROM | post_bootmode_get(0)); -#endif - - WATCHDOG_RESET(); - - memcpy (id, (void *)gd, sizeof (gd_t)); - - debug ("Start relocate of code from %08x to %08lx\n", CONFIG_SYS_MONITOR_BASE, addr); - relocate_code (addr_sp, id, addr); - - /* NOTREACHED - jump_to_ram() does not return */ -} - -/************************************************************************ - * - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - * - ************************************************************************ - */ -void board_init_r (gd_t *id, ulong dest_addr) -{ - char *s __maybe_unused; - bd_t *bd; - -#ifndef CONFIG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif -#ifndef CONFIG_SYS_NO_FLASH - ulong flash_size; -#endif - gd = id; /* initialize RAM version of global data */ - bd = gd->bd; - - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - WATCHDOG_RESET (); - - gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; - - serial_initialize(); - - debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - monitor_flash_len = (ulong)&__init_end - dest_addr; - -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - /* - * We have to relocate the command table manually - */ - fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), - ll_entry_count(cmd_tbl_t, cmd)); -#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ - - /* there are some other pointer constants we must deal with */ -#ifndef CONFIG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - - WATCHDOG_RESET (); - -#ifdef CONFIG_LOGBUFFER - logbuff_init_ptrs (); -#endif -#ifdef CONFIG_POST - post_output_backlog (); - post_reloc (); -#endif - WATCHDOG_RESET(); - -#if 0 - /* instruction cache enabled in cpu_init_f() for faster relocation */ - icache_enable (); /* it's time to enable the instruction cache */ -#endif - - /* - * Setup trap handlers - */ - trap_init (CONFIG_SYS_SDRAM_BASE); - - /* The Malloc area is immediately below the monitor copy in DRAM */ - mem_malloc_init (CONFIG_SYS_MONITOR_BASE + gd->reloc_off - - TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); - -#if !defined(CONFIG_SYS_NO_FLASH) - puts ("Flash: "); - - if ((flash_size = flash_init ()) > 0) { -# ifdef CONFIG_SYS_FLASH_CHECKSUM - print_size (flash_size, ""); - /* - * Compute and print flash CRC if flashchecksum is set to 'y' - * - * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX - */ - if (getenv_yesno("flashchecksum") == 1) { - printf (" CRC: %08X", - crc32 (0, - (const unsigned char *) CONFIG_SYS_FLASH_BASE, - flash_size) - ); - } - putc ('\n'); -# else /* !CONFIG_SYS_FLASH_CHECKSUM */ - print_size (flash_size, "\n"); -# endif /* CONFIG_SYS_FLASH_CHECKSUM */ - } else { - puts (failed); - hang (); - } - - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */ - bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ - bd->bi_flashoffset = 0; -#else /* CONFIG_SYS_NO_FLASH */ - bd->bi_flashsize = 0; - bd->bi_flashstart = 0; - bd->bi_flashoffset = 0; -#endif /* !CONFIG_SYS_NO_FLASH */ - - WATCHDOG_RESET (); - - /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r (); - - WATCHDOG_RESET (); - -#ifdef CONFIG_SPI -# if !defined(CONFIG_ENV_IS_IN_EEPROM) - spi_init_f (); -# endif - spi_init_r (); -#endif - -#if defined(CONFIG_SYS_I2C) - /* Adjust I2C subsystem pointers after relocation */ - i2c_reloc_fixup(); -#endif - - /* relocate environment function pointers etc. */ - env_relocate (); - - WATCHDOG_RESET (); - -#if defined(CONFIG_PCI) - /* - * Do pci configuration - */ - pci_init (); -#endif - - /** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize stdio devices */ - stdio_init (); - - /* Initialize the jump table for applications */ - jumptable_init (); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r (); - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r (); -#endif - -#if defined(CONFIG_CMD_KGDB) - WATCHDOG_RESET (); - puts ("KGDB: "); - kgdb_init (); -#endif - - debug ("U-Boot relocated to %08lx\n", dest_addr); - - /* - * Enable Interrupts - */ - interrupt_init (); - - /* Must happen after interrupts are initialized since - * an irq handler gets installed - */ - timer_init(); - -#ifdef CONFIG_STATUS_LED - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - udelay (20); - - /* Insert function pointers now that we have relocated the code */ - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - - WATCHDOG_RESET (); - -#if defined(CONFIG_CMD_DOC) - WATCHDOG_RESET (); - puts ("DOC: "); - doc_init (); -#endif - -#if defined(CONFIG_CMD_NAND) - WATCHDOG_RESET (); - puts ("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - WATCHDOG_RESET(); -#if defined(FEC_ENET) - eth_init(bd); -#endif - puts ("Net: "); - eth_initialize (bd); -#endif - -#ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); -#endif - -#if defined(CONFIG_CMD_PCMCIA) \ - && !defined(CONFIG_CMD_IDE) - WATCHDOG_RESET (); - puts ("PCMCIA:"); - pcmcia_init (); -#endif - -#if defined(CONFIG_CMD_IDE) - WATCHDOG_RESET (); - puts ("IDE: "); - ide_init (); -#endif - -#ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET (); - /* - * Some parts can be only initialized if all others (like - * Interrupts) are up and running (i.e. the PC-style ISA - * keyboard). - */ - last_stage_init (); -#endif - -#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) - /* - * Export available size of memory for Linux, - * taking into account the protected RAM at top of memory - */ - { - ulong pram = 0; - char memsz[32]; - -#ifdef CONFIG_PRAM - pram = getenv_ulong("pram", 10, CONFIG_PRAM); -#endif -#ifdef CONFIG_LOGBUFFER - /* Also take the logbuffer into account (pram is in kB) */ - pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; -#endif - sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram); - setenv ("mem", memsz); - } -#endif - -#ifdef CONFIG_WATCHDOG - /* disable watchdog if environment is set */ - if ((s = getenv ("watchdog")) != NULL) { - if (strncmp (s, "off", 3) == 0) { - WATCHDOG_DISABLE (); - } - } -#endif /* CONFIG_WATCHDOG*/ - - - /* Initialization complete - start the monitor */ - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } - - /* NOTREACHED - no way out of command loop except booting */ -} diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 2b817be61a..e7a347738a 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -19,4 +19,3 @@ PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC endif -__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index 2cc0a2da89..f4bb0915c5 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -9,7 +9,6 @@ #include <common.h> #include <image.h> #include <spl.h> -#include <version.h> #include <asm/io.h> #include <asm/u-boot.h> diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 32fd636b61..4af408a761 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -12,6 +12,5 @@ #endif #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_GENERIC_BOARD #endif diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 4dc88f4d51..52e28f2ca5 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -43,8 +43,6 @@ PLATFORM_CPPFLAGS += $(cpuflags-y) PLATFORM_CPPFLAGS += -D__MIPS__ -__HAVE_ARCH_GENERIC_BOARD := y - # # From Linux arch/mips/Makefile # diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 34db79dd5c..0d96c52cd5 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -13,7 +13,6 @@ #include <config.h> #include <common.h> #include <asm/macro.h> -#include <version.h> /* * Jump vector table for EVIC mode diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 9b7c56dc85..82bd887961 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -17,5 +17,3 @@ PLATFORM_CPPFLAGS += -G0 LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections - -__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c index 5024682088..79f72aa12f 100644 --- a/arch/nios2/cpu/fdt.c +++ b/arch/nios2/cpu/fdt.c @@ -34,7 +34,5 @@ void ft_cpu_setup(void *blob, bd_t *bd) * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob); - - return 0; } #endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */ diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h index 476a32bdc6..9c13848ea2 100644 --- a/arch/nios2/include/asm/config.h +++ b/arch/nios2/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_GLOBAL_DATA #endif diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index fec02f2b82..83b49b58c5 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -12,13 +12,11 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections LDFLAGS_FINAL += --bss-plt -PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \ - -meabi -PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -PLATFORM_LDFLAGS += -n +PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \ +-fdata-sections -mcall-linux -# Support generic board on PPC -__HAVE_ARCH_GENERIC_BOARD := y +PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32 +PLATFORM_LDFLAGS += -m32 -melf32ppclinux # # When cross-compiling on NetBSD, we have to define __PPC__ or else we diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S index 1432344bcc..bc9c62852c 100644 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ b/arch/powerpc/cpu/mpc8260/kgdb.S @@ -7,7 +7,6 @@ #include <config.h> #include <command.h> #include <mpc8260.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index a2c0ad4244..0e0daf5a44 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -8,7 +8,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc85xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S index 0bb058b043..536d9b9d73 100644 --- a/arch/powerpc/cpu/mpc86xx/cache.S +++ b/arch/powerpc/cpu/mpc86xx/cache.S @@ -1,6 +1,5 @@ #include <config.h> #include <mpc86xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc86xx/release.S b/arch/powerpc/cpu/mpc86xx/release.S index 461f6ec7df..3977049dc3 100644 --- a/arch/powerpc/cpu/mpc86xx/release.S +++ b/arch/powerpc/cpu/mpc86xx/release.S @@ -6,7 +6,6 @@ */ #include <config.h> #include <mpc86xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index e774d1e70a..0ea1a06c7a 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -7,7 +7,6 @@ #include <config.h> #include <command.h> #include <mpc8xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index f274c5d564..31abd69896 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -7,7 +7,6 @@ #include <config.h> #include <command.h> #include <asm/ppc4xx.h> -#include <version.h> #define CONFIG_405GP 1 /* needed for Linux kernel header files */ diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 7b84f02a0a..b05a90fb18 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE -PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD +PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM PLATFORM_LIBS += -lrt # Define this to avoid linking with SDL, which requires SDL libraries @@ -16,9 +16,6 @@ PLATFORM_CPPFLAGS += $(shell sdl-config --cflags) endif endif -# Support generic board on sandbox -__HAVE_ARCH_GENERIC_BOARD := y - cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \ -Wl,--start-group $(u-boot-main) -Wl,--end-group \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S index 5b92a01571..ebf731a3ab 100644 --- a/arch/sh/cpu/sh2/start.S +++ b/arch/sh/cpu/sh2/start.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> .text .align 2 diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S index c26a0b6a2c..7a934e24d4 100644 --- a/arch/sh/cpu/sh3/start.S +++ b/arch/sh/cpu/sh3/start.S @@ -10,7 +10,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> .text .align 2 diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S index 238aa43662..21644b5e67 100644 --- a/arch/sh/cpu/sh4/start.S +++ b/arch/sh/cpu/sh4/start.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> .text .align 2 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 35d24e4aca..da271158f1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -76,9 +76,6 @@ config DM_GPIO config DM_SERIAL default y -config SYS_MALLOC_F - default y - config SYS_MALLOC_F_LEN default 0x800 diff --git a/arch/x86/config.mk b/arch/x86/config.mk index bb2da4637e..999143e9df 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -17,9 +17,6 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm PLATFORM_CPPFLAGS += -march=i386 -m32 -# Support generic board on x86 -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386 diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c index 372815d8c1..db601e4efb 100644 --- a/arch/x86/cpu/quark/hte.c +++ b/arch/x86/cpu/quark/hte.c @@ -20,9 +20,9 @@ */ static void hte_enable_all_errors(void) { - msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF); - msg_port_write(HTE, 0x000200A3, 0x000000FF); - msg_port_write(HTE, 0x000200A4, 0x00000000); + msg_port_write(HTE, 0x000200a2, 0xffffffff); + msg_port_write(HTE, 0x000200a3, 0x000000ff); + msg_port_write(HTE, 0x000200a4, 0x00000000); } /** @@ -32,7 +32,7 @@ static void hte_enable_all_errors(void) */ static u32 hte_check_errors(void) { - return msg_port_read(HTE, 0x000200A7); + return msg_port_read(HTE, 0x000200a7); } /** @@ -44,11 +44,11 @@ static void hte_wait_for_complete(void) ENTERFN(); - do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0); + do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0); tmp = msg_port_read(HTE, 0x00020011); - tmp |= BIT9; - tmp &= ~(BIT12 | BIT13); + tmp |= (1 << 9); + tmp &= ~((1 << 12) | (1 << 13)); msg_port_write(HTE, 0x00020011, tmp); LEAVEFN(); @@ -65,9 +65,9 @@ static void hte_clear_error_regs(void) * Clear all HTE errors and enable error checking * for burst and chunk. */ - tmp = msg_port_read(HTE, 0x000200A1); - tmp |= BIT8; - msg_port_write(HTE, 0x000200A1, tmp); + tmp = msg_port_read(HTE, 0x000200a1); + tmp |= (1 << 8); + msg_port_write(HTE, 0x000200a1, tmp); } /** @@ -91,25 +91,25 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, u32 offset; if (first_run) { - msg_port_write(HTE, 0x00020020, 0x01B10021); + msg_port_write(HTE, 0x00020020, 0x01b10021); msg_port_write(HTE, 0x00020021, 0x06000000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020062, 0x00800015); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020061, 0x00030008); if (mode == WRITE_TRAIN) - pattern = 0xC33C0000; + pattern = 0xc33c0000; else /* READ_TRAIN */ - pattern = 0xAA5555AA; + pattern = 0xaa5555aa; - for (offset = 0x80; offset <= 0x8F; offset++) + for (offset = 0x80; offset <= 0x8f; offset++) msg_port_write(HTE, offset, pattern); } - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); msg_port_write(HTE, 0x00020011, 0x00011000); msg_port_write(HTE, 0x00020011, 0x00011100); @@ -119,7 +119,7 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for * any bytelane errors. */ - return (hte_check_errors() >> 8) & 0xFF; + return (hte_check_errors() >> 8) & 0xff; } /** @@ -153,7 +153,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, msg_port_write(HTE, 0x00020024, 0x06070000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020025, addr >> 6); - msg_port_write(HTE, 0x00020062, 0x0000002A); + msg_port_write(HTE, 0x00020062, 0x0000002a); msg_port_write(HTE, 0x00020063, seed_victim); msg_port_write(HTE, 0x00020064, seed_aggressor); msg_port_write(HTE, 0x00020065, seed_victim); @@ -163,21 +163,21 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, * * Start with bit0 */ - for (offset = 0x80; offset <= 0x8F; offset++) { + for (offset = 0x80; offset <= 0x8f; offset++) { if ((offset % 8) == victim_bit) msg_port_write(HTE, offset, 0x55555555); else - msg_port_write(HTE, offset, 0xCCCCCCCC); + msg_port_write(HTE, offset, 0xcccccccc); } msg_port_write(HTE, 0x00020061, 0x00000000); msg_port_write(HTE, 0x00020066, 0x03440000); - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); } tmp = 0x10001000 | (loop_cnt << 16); msg_port_write(HTE, 0x00020011, tmp); - msg_port_write(HTE, 0x00020011, tmp | BIT8); + msg_port_write(HTE, 0x00020011, tmp | (1 << 8)); hte_wait_for_complete(); @@ -185,7 +185,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for * any bytelane errors. */ - return (hte_check_errors() >> 8) & 0xFF; + return (hte_check_errors() >> 8) & 0xff; } /** @@ -219,14 +219,14 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) msg_port_write(HTE, 0x00020062, 0x00000015); - for (offset = 0x80; offset <= 0x8F; offset++) - msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5)); + for (offset = 0x80; offset <= 0x8f; offset++) + msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5)); msg_port_write(HTE, 0x00020021, 0x00000000); msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020066, 0x03000000); switch (flag) { @@ -243,7 +243,7 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) break; default: DPF(D_INFO, "Unknown parameter for flag: %d\n", flag); - return 0xFFFFFFFF; + return 0xffffffff; } DPF(D_INFO, "hte_mem_init"); @@ -379,16 +379,16 @@ void hte_mem_op(u32 addr, u8 first_run, u8 is_write) msg_port_write(HTE, 0x00020021, 0x06000000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020062, 0x00800015); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020061, 0x00030008); - for (offset = 0x80; offset <= 0x8F; offset++) - msg_port_write(HTE, offset, 0xC33C0000); + for (offset = 0x80; offset <= 0x8f; offset++) + msg_port_write(HTE, offset, 0xc33c0000); } - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); msg_port_write(HTE, 0x00020011, 0x00011000); msg_port_write(HTE, 0x00020011, 0x00011100); diff --git a/arch/x86/cpu/quark/hte.h b/arch/x86/cpu/quark/hte.h index 6577796fd6..e98c7ef41d 100644 --- a/arch/x86/cpu/quark/hte.h +++ b/arch/x86/cpu/quark/hte.h @@ -29,10 +29,10 @@ enum { #define HTE_LOOP_CNT 5 /* random seed for victim */ -#define HTE_LFSR_VICTIM_SEED 0xF294BA21 +#define HTE_LFSR_VICTIM_SEED 0xf294ba21 /* random seed for aggressor */ -#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D +#define HTE_LFSR_AGRESSOR_SEED 0xeba7492d u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag); u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr, diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c index 7eb34c5302..6e774cbcd8 100644 --- a/arch/x86/cpu/quark/mrc.c +++ b/arch/x86/cpu/quark/mrc.c @@ -34,6 +34,7 @@ */ #include <common.h> +#include <version.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> #include "mrc_util.h" @@ -105,8 +106,8 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * Column: 11 for 8Gbx8, else 10 */ mrc_params->column_bits[0] = - ((dram_params[0].density == 4) && - (dram_width == X8)) ? (11) : (10); + (dram_params[0].density == 4) && + (dram_width == X8) ? 11 : 10; /* * Determine row bits: @@ -117,9 +118,9 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * 4Gbx16=15 4Gbx8=16 * 8Gbx16=16 8Gbx8=16 */ - mrc_params->row_bits[0] = 12 + (dram_params[0].density) + - (((dram_params[0].density < 4) && - (dram_width == X8)) ? (1) : (0)); + mrc_params->row_bits[0] = 12 + dram_params[0].density + + (dram_params[0].density < 4) && + (dram_width == X8) ? 1 : 0; /* * Determine per-channel memory size: @@ -137,7 +138,7 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * 4Gb x16 0x040000000 (1024MB) * 4Gb x8 0x080000000 (2048MB) */ - mrc_params->channel_size[0] = (1 << dram_params[0].density); + mrc_params->channel_size[0] = 1 << dram_params[0].density; mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1; mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1; mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2; @@ -192,7 +193,7 @@ void mrc_init(struct mrc_params *mrc_params) ENTERFN(); DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION, - __DATE__, __TIME__); + U_BOOT_DATE, U_BOOT_TIME); /* Set up the data structures used by mrc_mem_init() */ mrc_adjust_params(mrc_params); diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 3a79ae551b..49d803d794 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -18,14 +18,14 @@ static const uint8_t vref_codes[64] = { /* lowest to highest */ - 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38, + 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, - 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28, + 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f }; void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask) @@ -80,7 +80,7 @@ void select_mem_mgr(void) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT28; + dco &= ~DCO_PMICTL; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -94,7 +94,7 @@ void select_hte(void) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco |= BIT28; + dco |= DCO_PMICTL; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -151,26 +151,25 @@ void set_rcvn(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : - (BIT11 | BIT10 | BIT9 | BIT8); - temp = (byte_lane & BIT0) ? ((pi_count / HALF_CLK) << 20) : - ((pi_count / HALF_CLK) << 8); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf00000 : 0xf00; + temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 : + (pi_count / HALF_CLK) << 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f000000; temp = pi_count << 24; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -179,25 +178,25 @@ void set_rcvn(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[08/11] (+1 select) * BL0/1 -> B01DBCTL1[02/05] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT5 : BIT2; + msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT11 : BIT8; + msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe0); } @@ -224,11 +223,11 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? 20 : 8; - temp &= 0xF; + temp >>= (byte_lane & 1) ? 20 : 8; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -238,12 +237,12 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -275,10 +274,10 @@ void set_rdqs(uint8_t channel, uint8_t rank, * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) */ - reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x7f; temp = pi_count << 0; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -310,13 +309,13 @@ uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) */ - reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); /* Adjust PI_COUNT */ - pi_count = temp & 0x7F; + pi_count = temp & 0x7f; LEAVEFN(); @@ -346,26 +345,25 @@ void set_wdqs(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT19 | BIT18 | BIT17 | BIT16) : - (BIT7 | BIT6 | BIT5 | BIT4); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf0000 : 0xf0; temp = pi_count / HALF_CLK; - temp <<= (byte_lane & BIT0) ? 16 : 4; + temp <<= (byte_lane & 1) ? 16 : 4; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f0000; temp = pi_count << 16; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -374,25 +372,25 @@ void set_wdqs(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[07/10] (+1 select) * BL0/1 -> B01DBCTL1[01/04] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT4 : BIT1; + msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT10 : BIT7; + msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe2); } @@ -419,11 +417,11 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? 16 : 4; - temp &= 0xF; + temp >>= (byte_lane & 1) ? 16 : 4; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = (temp * HALF_CLK); @@ -433,12 +431,12 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 16; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -471,26 +469,25 @@ void set_wdq(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT15 | BIT14 | BIT13 | BIT12) : - (BIT3 | BIT2 | BIT1 | BIT0); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf000 : 0xf; temp = pi_count / HALF_CLK; - temp <<= (byte_lane & BIT0) ? 12 : 0; + temp <<= (byte_lane & 1) ? 12 : 0; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f00; temp = pi_count << 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -499,25 +496,25 @@ void set_wdq(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[06/09] (+1 select) * BL0/1 -> B01DBCTL1[00/03] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT3 : BIT0; + msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT9 : BIT6; + msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe3); } @@ -544,11 +541,11 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? (12) : (0); - temp &= 0xF; + temp >>= (byte_lane & 1) ? 12 : 0; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -558,12 +555,12 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 8; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -589,14 +586,14 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * RDPTR (1/2 MCLK, 64 PIs) * CMDPTRREG[11:08] (0x0-0xF) */ - reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT11 | BIT10 | BIT9 | BIT8); + reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xf00; temp = pi_count / HALF_CLK; temp <<= 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) @@ -609,18 +606,13 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) */ - reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); - - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); - + reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; + msk = 0x3f3f3f3f; temp = (pi_count << 24) | (pi_count << 16) | (pi_count << 8) | (pi_count << 0); mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); /* PO */ + reg = CMDDLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; /* PO */ mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* @@ -628,24 +620,24 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * CMDCFGREG0[17] (+1 select) * CMDCFGREG0[16] (enable) */ - reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDCFGREG0 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= BIT16; + msk |= (1 << 16); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= BIT17; + msk |= (1 << 17); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe4); LEAVEFN(); @@ -667,10 +659,10 @@ uint32_t get_wcmd(uint8_t channel) * RDPTR (1/2 MCLK, 64 PIs) * CMDPTRREG[11:08] (0x0-0xF) */ - reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 8; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -686,10 +678,10 @@ uint32_t get_wcmd(uint8_t channel) * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) */ - reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 16; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -716,13 +708,13 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCPTRREG[15:12] -> CLK1 (0x0-0xF) * CCPTRREG[11:08] -> CLK0 (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xff00; temp = ((pi_count / HALF_CLK) << 12) | ((pi_count / HALF_CLK) << 8); mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) @@ -731,16 +723,18 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) */ reg = rank ? ECCB1DLLPICODER0 : ECCB1DLLPICODER0; reg += (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + msk = 0x3f3f00; temp = (pi_count << 16) | (pi_count << 8); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER1 : ECCB1DLLPICODER1; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER2 : ECCB1DLLPICODER2; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER3 : ECCB1DLLPICODER3; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -750,24 +744,24 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCCFGREG1[11:08] (+1 select) * CCCFGREG1[03:00] (enable) */ - reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (BIT3 | BIT2 | BIT1 | BIT0); + msk |= 0xf; if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (BIT11 | BIT10 | BIT9 | BIT8); + msk |= 0xf00; if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe5); LEAVEFN(); @@ -790,10 +784,10 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank) * CCPTRREG[15:12] -> CLK1 (0x0-0xF) * CCPTRREG[11:08] -> CLK0 (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= rank ? 12 : 8; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -807,7 +801,7 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank) reg += (channel * DDRIOCCC_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= rank ? 16 : 8; - temp &= 0x3F; + temp &= 0x3f; pi_count += temp; @@ -835,28 +829,31 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCPTRREG[31:28] (0x0-0xF) * CCPTRREG[27:24] (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xff000000; temp = ((pi_count / HALF_CLK) << 28) | ((pi_count / HALF_CLK) << 24); mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) */ - reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; + msk = 0x3f000000; temp = (pi_count << 24); mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER2 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER2 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER3 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER3 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* @@ -864,24 +861,24 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCCFGREG1[13:12] (+1 select) * CCCFGREG1[05:04] (enable) */ - reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (BIT5 | BIT4); + msk |= 0x30; if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (BIT13 | BIT12); + msk |= 0x3000; if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe6); LEAVEFN(); @@ -906,10 +903,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) * CCPTRREG[31:28] (0x0-0xF) * CCPTRREG[27:24] (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -919,10 +916,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) */ - reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); + reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -938,17 +935,16 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) */ void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting) { - uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL); + uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; ENTERFN(); DPF(D_TRN, "Vref ch%d ln%d : val=%03X\n", channel, byte_lane, setting); - mrc_alt_write_mask(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) + - ((byte_lane >> 1) * DDRIODQ_BL_OFFSET)), - (vref_codes[setting] << 2), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + mrc_alt_write_mask(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + + (byte_lane >> 1) * DDRIODQ_BL_OFFSET, + vref_codes[setting] << 2, 0xfc); /* * need to wait ~300ns for Vref to settle @@ -969,15 +965,15 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane) { uint8_t j; uint32_t ret_val = sizeof(vref_codes) / 2; - uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL); + uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; uint32_t temp; ENTERFN(); - temp = msg_port_alt_read(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) + - ((byte_lane >> 1) * DDRIODQ_BL_OFFSET))); + temp = msg_port_alt_read(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + + (byte_lane >> 1) * DDRIODQ_BL_OFFSET); temp >>= 2; - temp &= 0x3F; + temp &= 0x3f; for (j = 0; j < sizeof(vref_codes); j++) { if (vref_codes[j] == temp) { @@ -997,7 +993,7 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane) */ uint32_t get_addr(uint8_t channel, uint8_t rank) { - uint32_t offset = 0x02000000; /* 32MB */ + uint32_t offset = 32 * 1024 * 1024; /* 32MB */ /* Begin product specific code */ if (channel > 0) { @@ -1040,8 +1036,8 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, uint32_t address = get_addr(channel, rank); /* initialise msk[] */ - msk[0] = rcvn ? BIT1 : BIT9; /* BL0 */ - msk[1] = rcvn ? BIT0 : BIT8; /* BL1 */ + msk[0] = rcvn ? (1 << 1) : (1 << 9); /* BL0 */ + msk[1] = rcvn ? (1 << 0) : (1 << 8); /* BL1 */ /* cycle through each byte lane group */ for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { @@ -1056,9 +1052,9 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, * DQTRAINSTS register */ sampled_val[j] = msg_port_alt_read(DDRPHY, - (DQTRAINSTS + - (bl_grp * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET))); + DQTRAINSTS + + bl_grp * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); } /* @@ -1076,7 +1072,7 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, num_0s++; } if (num_1s > num_0s) - ret_val |= (1 << (bl + (bl_grp * 2))); + ret_val |= (1 << (bl + bl_grp * 2)); } } @@ -1116,10 +1112,10 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], /* increase sample delay by 26 PI (0.2 CLK) */ if (rcvn) { set_rcvn(channel, rank, bl, - delay[bl] + (sample * SAMPLE_DLY)); + delay[bl] + sample * SAMPLE_DLY); } else { set_wdqs(channel, rank, bl, - delay[bl] + (sample * SAMPLE_DLY)); + delay[bl] + sample * SAMPLE_DLY); } } @@ -1129,7 +1125,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], DPF(D_TRN, "Find rising edge %s ch%d rnk%d: #%d dly=%d dqs=%02X\n", - (rcvn ? "RCVN" : "WDQS"), channel, rank, sample, + rcvn ? "RCVN" : "WDQS", channel, rank, sample, sample * SAMPLE_DLY, sample_result[sample]); } @@ -1137,7 +1133,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], * This pattern will help determine where we landed and ultimately * how to place RCVEN/WDQS. */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* build transition_pattern (MSB is 1st sample) */ transition_pattern = 0; for (sample = 0; sample < SAMPLE_CNT; sample++) { @@ -1202,7 +1198,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], /* take a sample */ temp = sample_dqs(mrc_params, channel, rank, rcvn); /* check all each byte lane for proper edge */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (temp & (1 << bl)) { /* sampled "1" */ if (direction[bl] == BACKWARD) { @@ -1340,10 +1336,10 @@ void lfsr32(uint32_t *lfsr_ptr) lfsr = *lfsr_ptr; for (i = 0; i < 32; i++) { - bit = 1 ^ (lfsr & BIT0); - bit = bit ^ ((lfsr & BIT1) >> 1); - bit = bit ^ ((lfsr & BIT2) >> 2); - bit = bit ^ ((lfsr & BIT22) >> 22); + bit = 1 ^ (lfsr & 1); + bit = bit ^ ((lfsr & 2) >> 1); + bit = bit ^ ((lfsr & 4) >> 2); + bit = bit ^ ((lfsr & 0x400000) >> 22); lfsr = ((lfsr >> 1) | (bit << 31)); } @@ -1362,16 +1358,16 @@ void clear_pointers(void) for (channel = 0; channel < NUM_CHANNELS; channel++) { for (bl = 0; bl < NUM_BYTE_LANES; bl++) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (channel * DDRIODQ_CH_OFFSET) + - ((bl >> 1) * DDRIODQ_BL_OFFSET)), - ~BIT8, BIT8); + B01PTRCTL1 + + channel * DDRIODQ_CH_OFFSET + + (bl >> 1) * DDRIODQ_BL_OFFSET, + ~(1 << 8), (1 << 8)); mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (channel * DDRIODQ_CH_OFFSET) + - ((bl >> 1) * DDRIODQ_BL_OFFSET)), - BIT8, BIT8); + B01PTRCTL1 + + channel * DDRIODQ_CH_OFFSET + + (bl >> 1) * DDRIODQ_BL_OFFSET, + (1 << 8), (1 << 8)); } } @@ -1412,7 +1408,7 @@ static void print_timings_internal(uint8_t algo, uint8_t channel, uint8_t rank, break; } - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { switch (algo) { case RCVN: DPF(D_INFO, " %03d", get_rcvn(channel, rank, bl)); diff --git a/arch/x86/cpu/quark/mrc_util.h b/arch/x86/cpu/quark/mrc_util.h index f0ddbce3c5..a63d1f91e9 100644 --- a/arch/x86/cpu/quark/mrc_util.h +++ b/arch/x86/cpu/quark/mrc_util.h @@ -41,40 +41,6 @@ #define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__) #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__) -/* Generic Register Bits */ -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - /* Message Bus Port */ #define MEM_CTLR 0x01 #define HOST_BRIDGE 0x03 diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index dccf7ac5f5..25edcf71cb 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -6,6 +6,8 @@ #include <common.h> #include <mmc.h> +#include <netdev.h> +#include <phy.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/post.h> @@ -116,3 +118,20 @@ int cpu_mmc_init(bd_t *bis) return pci_mmc_init("Quark SDHCI", mmc_supported, ARRAY_SIZE(mmc_supported)); } + +int cpu_eth_init(bd_t *bis) +{ + u32 base; + int ret0, ret1; + + pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base); + ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); + + pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base); + ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); + + if (ret0 < 0 && ret1 < 0) + return -1; + else + return 0; +} diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index e34bec4c80..3ffe92b67b 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -60,7 +60,7 @@ void clear_self_refresh(struct mrc_params *mrc_params) ENTERFN(); /* clear the PMSTS Channel Self Refresh bits */ - mrc_write_mask(MEM_CTLR, PMSTS, BIT0, BIT0); + mrc_write_mask(MEM_CTLR, PMSTS, PMSTS_DISR, PMSTS_DISR); LEAVEFN(); } @@ -101,47 +101,47 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) wl = 5 + mrc_params->ddr_speed; - dtr0 &= ~(BIT0 | BIT1); + dtr0 &= ~DTR0_DFREQ_MASK; dtr0 |= mrc_params->ddr_speed; - dtr0 &= ~(BIT12 | BIT13 | BIT14); + dtr0 &= ~DTR0_TCL_MASK; tmp1 = tcl - 5; dtr0 |= ((tcl - 5) << 12); - dtr0 &= ~(BIT4 | BIT5 | BIT6 | BIT7); + dtr0 &= ~DTR0_TRP_MASK; dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ - dtr0 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr0 &= ~DTR0_TRCD_MASK; dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ - dtr1 &= ~(BIT0 | BIT1 | BIT2); + dtr1 &= ~DTR1_TWCL_MASK; tmp2 = wl - 3; dtr1 |= (wl - 3); - dtr1 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr1 &= ~DTR1_TWTP_MASK; dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ - dtr1 &= ~(BIT28 | BIT29 | BIT30); + dtr1 &= ~DTR1_TRTP_MASK; dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT24 | BIT25); + dtr1 &= ~DTR1_TRRD_MASK; dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT4 | BIT5); + dtr1 &= ~DTR1_TCMD_MASK; dtr1 |= (1 << 4); - dtr1 &= ~(BIT20 | BIT21 | BIT22 | BIT23); + dtr1 &= ~DTR1_TRAS_MASK; dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ - dtr1 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr1 &= ~DTR1_TFAW_MASK; dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ /* Set 4 Clock CAS to CAS delay (multi-burst) */ - dtr1 &= ~(BIT12 | BIT13); + dtr1 &= ~DTR1_TCCD_MASK; - dtr2 &= ~(BIT0 | BIT1 | BIT2); + dtr2 &= ~DTR2_TRRDR_MASK; dtr2 |= 1; - dtr2 &= ~(BIT8 | BIT9 | BIT10); + dtr2 &= ~DTR2_TWWDR_MASK; dtr2 |= (2 << 8); - dtr2 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr2 &= ~DTR2_TRWDR_MASK; dtr2 |= (2 << 16); - dtr3 &= ~(BIT0 | BIT1 | BIT2); + dtr3 &= ~DTR3_TWRDR_MASK; dtr3 |= 2; - dtr3 &= ~(BIT4 | BIT5 | BIT6); + dtr3 &= ~DTR3_TXXXX_MASK; dtr3 |= (2 << 4); - dtr3 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr3 &= ~DTR3_TRWSR_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) { /* Extended RW delay (+1) */ dtr3 |= ((tcl - 5 + 1) << 8); @@ -150,24 +150,24 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) dtr3 |= ((tcl - 5 + 1) << 8); } - dtr3 &= ~(BIT13 | BIT14 | BIT15 | BIT16); + dtr3 &= ~DTR3_TWRSR_MASK; dtr3 |= ((4 + wl + twtr - 11) << 13); - dtr3 &= ~(BIT22 | BIT23); + dtr3 &= ~DTR3_TXP_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) dtr3 |= ((MMAX(0, 1 - 1)) << 22); else dtr3 |= ((MMAX(0, 2 - 1)) << 22); - dtr4 &= ~(BIT0 | BIT1); + dtr4 &= ~DTR4_WRODTSTRT_MASK; dtr4 |= 1; - dtr4 &= ~(BIT4 | BIT5 | BIT6); + dtr4 &= ~DTR4_WRODTSTOP_MASK; dtr4 |= (1 << 4); - dtr4 &= ~(BIT8 | BIT9 | BIT10); + dtr4 &= ~DTR4_XXXX1_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); - dtr4 &= ~(BIT12 | BIT13 | BIT14); + dtr4 &= ~DTR4_XXXX2_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); - dtr4 &= ~(BIT15 | BIT16); + dtr4 &= ~(DTR4_ODTDIS | DTR4_TRGSTRDIS); msg_port_write(MEM_CTLR, DTR0, dtr0); msg_port_write(MEM_CTLR, DTR1, dtr1); @@ -191,25 +191,25 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) /* Disable power saving features */ dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT24 | BIT25); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); - dpmc0 &= ~BIT23; + dpmc0 |= (DPMC0_CLKGTDIS | DPMC0_DISPWRDN); + dpmc0 &= ~DPMC0_PCLSTO_MASK; + dpmc0 &= ~DPMC0_DYNSREN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* Disable out of order transactions */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= (BIT8 | BIT12); + dsch |= (DSCH_OOODIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); /* Disable issuing the REF command */ drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; msg_port_write(MEM_CTLR, DRFC, drfc); /* Disable ZQ calibration short */ dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); - dcal &= ~(BIT12 | BIT13); + dcal &= ~DCAL_ZQCINT_MASK; + dcal &= ~DCAL_SRXZQCL_MASK; msg_port_write(MEM_CTLR, DCAL, dcal); /* @@ -218,9 +218,9 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) */ drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; msg_port_write(MEM_CTLR, DRP, drp); LEAVEFN(); @@ -238,14 +238,14 @@ void perform_ddr_reset(struct mrc_params *mrc_params) ENTERFN(); /* Set COLDWAKE bit before sending the WAKE message */ - mrc_write_mask(MEM_CTLR, DRMC, BIT16, BIT16); + mrc_write_mask(MEM_CTLR, DRMC, DRMC_COLDWAKE, DRMC_COLDWAKE); /* Send wake command to DUNIT (MUST be done before JEDEC) */ dram_wake_command(); /* Set default value */ msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0); LEAVEFN(); } @@ -263,7 +263,7 @@ void ddrphy_init(struct mrc_params *mrc_params) uint8_t bl_grp; /* byte lane group counter (2 BLs per module) */ uint8_t bl_divisor = 1; /* byte lane divisor */ /* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */ - uint8_t speed = mrc_params->ddr_speed & (BIT1 | BIT0); + uint8_t speed = mrc_params->ddr_speed & 3; uint8_t cas; uint8_t cwl; @@ -286,21 +286,21 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Deassert DDRPHY Initialization Complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT20, BIT20); /* SPID_INIT_COMPLETE=0 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 20), 1 << 20); /* SPID_INIT_COMPLETE=0 */ /* Deassert IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT2, BIT2); /* IOBUFACTRST_N=0 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 2), 1 << 2); /* IOBUFACTRST_N=0 */ /* Disable WRPTR */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT0, BIT0); /* WRPTRENABLE=0 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 0), 1 << 0); /* WRPTRENABLE=0 */ } } /* Put PHY in reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, 1); /* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */ @@ -310,14 +310,14 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* Analog MUX select - IO2xCLKSEL */ mrc_alt_write_mask(DDRPHY, - (DQOBSCKEBBCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((bl_grp) ? (0x00) : (BIT22)), (BIT22)); + DQOBSCKEBBCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 0 : (1 << 22), 1 << 22); /* ODT Strength */ switch (mrc_params->rd_odt_value) { @@ -337,20 +337,20 @@ void ddrphy_init(struct mrc_params *mrc_params) /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* Dynamic ODT/DIFFAMP */ - temp = (((cas) << 24) | ((cas) << 16) | - ((cas) << 8) | ((cas) << 0)); + temp = (cas << 24) | (cas << 16) | + (cas << 8) | (cas << 0); switch (speed) { case 0: temp -= 0x01010101; @@ -368,247 +368,199 @@ void ddrphy_init(struct mrc_params *mrc_params) /* Launch Time: ODT, DIFFAMP, ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B01LATCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + B01LATCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x1f1f1f1f); switch (speed) { /* HSD#234715 */ case 0: - temp = ((0x06 << 16) | (0x07 << 8)); + temp = (0x06 << 16) | (0x07 << 8); break; /* 800 */ case 1: - temp = ((0x07 << 16) | (0x08 << 8)); + temp = (0x07 << 16) | (0x08 << 8); break; /* 1066 */ case 2: - temp = ((0x09 << 16) | (0x0A << 8)); + temp = (0x09 << 16) | (0x0a << 8); break; /* 1333 */ case 3: - temp = ((0x0A << 16) | (0x0B << 8)); + temp = (0x0a << 16) | (0x0b << 8); break; /* 1600 */ } /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B0ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B0ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B1ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B1ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); switch (mrc_params->rd_odt_value) { case 0: /* override DIFFAMP=on, ODT=off */ - temp = ((0x3F << 16) | (0x3f << 10)); + temp = (0x3f << 16) | (0x3f << 10); break; default: /* override DIFFAMP=on, ODT=on */ - temp = ((0x3F << 16) | (0x2A << 10)); + temp = (0x3f << 16) | (0x2a << 10); break; } /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B1OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* DLL Setup */ /* 1xCLK Domain Timings: tEDP,RCVEN,WDQS (PO) */ mrc_alt_write_mask(DDRPHY, - (B0LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B0LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); mrc_alt_write_mask(DDRPHY, - (B1LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B1LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); /* RCVEN Bypass (PO) */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); /* TX */ mrc_alt_write_mask(DDRPHY, - (DQCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT16), (BIT16)); + DQCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 16, 1 << 16); mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT8), (BIT8)); + B01PTRCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); /* RX (PO) */ /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B0VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B0VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B1VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B1VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); } /* CLKEBB */ mrc_alt_write_mask(DDRPHY, - (CMDOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT23)); + CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 23); /* Enable tristate control of cmd/address bus */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT1 | BIT0)); + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0, 0x03); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CMDRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 5) | (0x03 << 0)), - (BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 5) | (0x03 << 0), 0x3ff); /* CMDPM* registers must be programmed in this order */ /* Turn On Delays: SFR (regulator), MPLL */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG4 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFFFU << 16) | (0xFFFF << 0)), - 0xFFFFFFFF); + CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* * Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, * VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT * for_PM_MSG_gt0, MDLL Turn On */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG3 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFU << 28) | (0xFFF << 16) | (0xF << 12) | - (0x616 << 0)), 0xFFFFFFFF); + CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, + 0xfffff616, 0xffffffff); /* MPLL Divider Reset Delays */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn Off Delays: VREG, Staggered MDLL, MDLL, PI */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Allow PUnit signals */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x6 << 8) | BIT6 | (0x4 << 0)), - (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | - BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT11 | - BIT10 | BIT9 | BIT8 | BIT6 | BIT3 | BIT2 | - BIT1 | BIT0)); + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + (0x6 << 8) | (0x1 << 6) | (0x4 << 0), + 0xffe00f4f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, BIT24); /* CLKEBB */ + CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 24); /* CLKEBB */ /* Buffer Enable: CS,CKE,ODT,CLK */ mrc_alt_write_mask(DDRPHY, - (CCCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x0 << 16) | (0x0 << 12) | (0x0 << 8) | - (0xF << 4) | BIT0), - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT7 | BIT6 | BIT5 | BIT4 | BIT0)); + CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x1f, 0x000ffff1); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CCRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), 0x00001f1f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* * COMP (RON channel specific) @@ -618,66 +570,43 @@ void ddrphy_init(struct mrc_params *mrc_params) */ /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CMDVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0F << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0F << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CTLVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* DQS Swapped Input Enable */ mrc_alt_write_mask(DDRPHY, - (COMPEN1CH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT19 | BIT17), - (BIT31 | BIT30 | BIT19 | BIT17 | - BIT15 | BIT14)); + COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 19) | (1 << 17), 0xc00ac000); /* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */ /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0E << 8) | (0x05 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0E << 8) | (0x05 << 0), 0x00003f3f); /* * Slew rate settings are frequency specific, @@ -685,273 +614,227 @@ void ddrphy_init(struct mrc_params *mrc_params) * - DQ/DQS/DM/CLK SR: 4V/ns, * - CTRL/CMD SR: 1.5V/ns */ - temp = (0x0E << 16) | (0x0E << 12) | (0x08 << 8) | - (0x0B << 4) | (0x0B << 0); + temp = (0x0e << 16) | (0x0e << 12) | (0x08 << 8) | + (0x0b << 4) | (0x0b << 0); /* DCOMP Delay Select: CTL,CMD,CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (DLYSELCH0 + (ch * DDRCOMP_CH_OFFSET)), - temp, - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | - BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, + temp, 0x000fffff); /* TCO Vref CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (TCOVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x05 << 16) | (0x05 << 8) | (0x05 << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT5 | BIT4 | BIT3 | BIT2 | - BIT1 | BIT0)); + TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x05 << 16) | (0x05 << 8) | (0x05 << 0), + 0x003f3f3f); /* ODTCOMP CMD/CTL PU/PD */ mrc_alt_write_mask(DDRPHY, - (CCBUFODTCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), + 0x00001f1f); /* COMP */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - 0, (BIT31 | BIT30 | BIT8)); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 0, 0xc0000100); #ifdef BACKUP_COMPS /* DQ COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* DQS COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CLK COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CMD COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* CTL COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); #else /* DQ TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* DQS TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* CLK TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); #endif /* program STATIC delays */ @@ -962,7 +845,7 @@ void ddrphy_init(struct mrc_params *mrc_params) #endif for (rk = 0; rk < NUM_RANKS; rk++) { - if (mrc_params->rank_enables & (1<<rk)) { + if (mrc_params->rank_enables & (1 << rk)) { set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); #ifdef BACKUP_WCTL set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); @@ -976,86 +859,80 @@ void ddrphy_init(struct mrc_params *mrc_params) /* COMP (non channel specific) */ /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPDCTL, 1 << 30, 1 << 30); /* TCOCOMP: Pulse Count */ - mrc_alt_write_mask(DDRPHY, (TCOCNTCTRL), (0x1 << 0), (BIT1 | BIT0)); + mrc_alt_write_mask(DDRPHY, TCOCNTCTRL, 1, 3); /* ODT: CMD/CTL PD/PU */ - mrc_alt_write_mask(DDRPHY, - (CHNLBUFSTATIC), ((0x03 << 24) | (0x03 << 16)), - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16)); + mrc_alt_write_mask(DDRPHY, CHNLBUFSTATIC, + (0x03 << 24) | (0x03 << 16), 0x1f1f0000); /* Set 1us counter */ - mrc_alt_write_mask(DDRPHY, - (MSCNTR), (0x64 << 0), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); - mrc_alt_write_mask(DDRPHY, - (LATCH1CTL), (0x1 << 28), - (BIT30 | BIT29 | BIT28)); + mrc_alt_write_mask(DDRPHY, MSCNTR, 0x64, 0xff); + mrc_alt_write_mask(DDRPHY, LATCH1CTL, 0x1 << 28, 0x70000000); /* Release PHY from reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, BIT0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 1, 1); /* STEP1 */ mrc_post_code(0x03, 0x11); @@ -1064,30 +941,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT13), - (BIT13)); /* Enable VREG */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 13, + 1 << 13); /* Enable VREG */ delay_n(3); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT13), (BIT13)); /* Enable VREG */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); } } @@ -1100,30 +977,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT17), - (BIT17)); /* Enable MCDLL */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 17, + 1 << 17); /* Enable MCDLL */ delay_n(50); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT17), (BIT17)); /* Enable MCDLL */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 17, 1 << 17); /* Enable MCDLL */ delay_n(50); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); } } @@ -1136,54 +1013,47 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { #ifdef FORCE_16BIT_DDRIO - temp = ((bl_grp) && + temp = (bl_grp && (mrc_params->channel_width == X16)) ? - ((0x1 << 12) | (0x1 << 8) | - (0xF << 4) | (0xF << 0)) : - ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + 0x11ff : 0xffff; #else - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + temp = 0xffff; #endif /* Enable TXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLTXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, 0xFFFF); + DQDLLTXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0xffff); delay_n(3); /* Enable RXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLRXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQDLLRXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); delay_n(3); /* Enable RXDLL Overrides BL0 */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); } /* ECC */ - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); - mrc_alt_write_mask(DDRPHY, (ECCDLLTXCTL), - temp, 0xFFFF); + temp = 0xffff; + mrc_alt_write_mask(DDRPHY, ECCDLLTXCTL, + temp, 0xffff); delay_n(3); /* CMD (PO) */ mrc_alt_write_mask(DDRPHY, - (CMDDLLTXCTL + (ch * DDRIOCCC_CH_OFFSET)), - temp, 0xFFFF); + CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, + temp, 0xffff); delay_n(3); } } @@ -1195,94 +1065,85 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Host To Memory Clock Alignment (HMC) for 800/1066 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* CLK_ALIGN_MOD_ID */ mrc_alt_write_mask(DDRPHY, - (DQCLKALIGNREG2 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (bl_grp) ? (0x3) : (0x1), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQCLKALIGNREG2 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 3 : 1, + 0xf); } mrc_alt_write_mask(DDRPHY, - (ECCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x0, - (BIT3 | BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x0, 0xf); mrc_alt_write_mask(DDRPHY, - (CCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - (0x2 << 4), (BIT5 | BIT4)); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x20, 0x30); /* * NUM_SAMPLES, MAX_SAMPLES, * MACRO_PI_STEP, MICRO_PI_STEP */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x18 << 16) | (0x10 << 8) | - (0x8 << 2) | (0x1 << 0)), - (BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, + (0x18 << 16) | (0x10 << 8) | + (0x8 << 2) | (0x1 << 0), + 0x007f7fff); /* TOTAL_NUM_MODULES, FIRST_U_PARTITION */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x10 << 16) | (0x4 << 8) | (0x2 << 4)), - (BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | - BIT5 | BIT4)); + CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, + (0x10 << 16) | (0x4 << 8) | (0x2 << 4), + 0x001f0ff0); #ifdef HMC_TEST /* START_CLK_ALIGN=1 */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT24, BIT24); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 24, 1 << 24); while (msg_port_alt_read(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET))) & - BIT24) + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & + (1 << 24)) ; /* wait for START_CLK_ALIGN=0 */ #endif /* Set RD/WR Pointer Seperation & COUNTEN & FIFOPTREN */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - BIT0, BIT0); /* WRPTRENABLE=1 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + 1, 1); /* WRPTRENABLE=1 */ /* COMP initial */ /* enable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 5, 1 << 5); /* Initial COMP Enable */ - mrc_alt_write_mask(DDRPHY, (CMPCTRL), - (BIT0), (BIT0)); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 1, 1); /* wait for Initial COMP Enable = 0 */ - while (msg_port_alt_read(DDRPHY, (CMPCTRL)) & BIT0) + while (msg_port_alt_read(DDRPHY, CMPCTRL) & 1) ; /* disable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - ~BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + ~(1 << 5), 1 << 5); /* IOBUFACT */ /* STEP4a */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT2, BIT2); /* IOBUFACTRST_N=1 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 2, 1 << 2); /* IOBUFACTRST_N=1 */ /* DDRPHY initialization complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT20, BIT20); /* SPID_INIT_COMPLETE=1 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 20, 1 << 20); /* SPID_INIT_COMPLETE=1 */ } } @@ -1308,13 +1169,13 @@ void perform_jedec_init(struct mrc_params *mrc_params) mrc_post_code(0x04, 0x00); /* DDR3_RESET_SET=0, DDR3_RESET_RESET=1 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT1, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 2, 0x102); /* Assert RESET# for 200us */ delay_u(200); /* DDR3_RESET_SET=1, DDR3_RESET_RESET=0 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT8, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 0x100, 0x102); dtr0 = msg_port_read(MEM_CTLR, DTR0); @@ -1327,8 +1188,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) drp &= 0x3; drmc = msg_port_read(MEM_CTLR, DRMC); - drmc &= 0xFFFFFFFC; - drmc |= (BIT4 | drp); + drmc &= 0xfffffffc; + drmc |= (DRMC_CKEMODE | drp); msg_port_write(MEM_CTLR, DRMC, drmc); @@ -1341,7 +1202,7 @@ void perform_jedec_init(struct mrc_params *mrc_params) } msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + (mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0)); /* * setup for emrs 2 @@ -1392,12 +1253,12 @@ void perform_jedec_init(struct mrc_params *mrc_params) * 1** --> RESERVED */ emrs1_cmd |= (1 << 3); - emrs1_cmd &= ~BIT6; + emrs1_cmd &= ~(1 << 6); if (mrc_params->ron_value == 0) - emrs1_cmd |= BIT7; + emrs1_cmd |= (1 << 7); else - emrs1_cmd &= ~BIT7; + emrs1_cmd &= ~(1 << 7); if (mrc_params->rtt_nom_value == 0) emrs1_cmd |= (DDR3_EMRS1_RTTNOM_40 << 6); @@ -1432,8 +1293,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) * BIT[02:02] "0" if oem_tCAS <= 11 (1866?) * BIT[06:04] use oem_tCAS-4 */ - mrs0_cmd |= BIT14; - mrs0_cmd |= BIT18; + mrs0_cmd |= (1 << 14); + mrs0_cmd |= (1 << 18); mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10); tck = t_ck[mrc_params->ddr_speed]; @@ -1480,8 +1341,8 @@ void set_ddr_init_complete(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -1577,7 +1438,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* need separate burst to sample DQS preamble */ dtr1 = msg_port_read(MEM_CTLR, DTR1); dtr1_save = dtr1; - dtr1 |= BIT12; + dtr1 |= DTR1_TCCD_12CLK; msg_port_write(MEM_CTLR, DTR1, dtr1); #endif @@ -1596,7 +1457,7 @@ void rcvn_cal(struct mrc_params *mrc_params) * POST_CODE here indicates the current * channel and rank being calibrated */ - mrc_post_code(0x05, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_RCVN /* et hard-coded timing values */ @@ -1606,10 +1467,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* enable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - 0, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 1 << 8); } /* initialize the starting delay to 128 PI (cas +1 CLK) */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1638,11 +1499,11 @@ void rcvn_cal(struct mrc_params *mrc_params) } else { /* not enough delay */ training_message(ch, rk, bl); - mrc_post_code(0xEE, 0x50); + mrc_post_code(0xee, 0x50); } } } - } while (temp & 0xFF); + } while (temp & 0xff); #ifdef R2R_SHARING /* increment "num_ranks_enabled" */ @@ -1653,7 +1514,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* add "delay[]" values to "final_delay[][]" for rolling average */ final_delay[ch][bl] += delay[bl]; /* set timing based on rolling average values */ - set_rcvn(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); } #else /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */ @@ -1666,10 +1527,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* disable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - BIT8, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); } #endif } @@ -1742,12 +1603,12 @@ void wr_level(struct mrc_params *mrc_params) * POST_CODE here indicates the current * rank and channel being calibrated */ - mrc_post_code(0x06, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_WDQS for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); - set_wdq(ch, rk, bl, (ddr_wdqs[PLATFORM_ID] - QRTR_CLK)); + set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); } #else /* @@ -1760,7 +1621,7 @@ void wr_level(struct mrc_params *mrc_params) * enable Write Levelling Mode * (EMRS1 w/ Write Levelling Mode Enable) */ - dram_init_command(DCMD_MRS1(rk, 0x0082)); + dram_init_command(DCMD_MRS1(rk, 0x82)); /* * set ODT DRAM Full Time Termination @@ -1769,24 +1630,24 @@ void wr_level(struct mrc_params *mrc_params) dtr4 = msg_port_read(MEM_CTLR, DTR4); dtr4_save = dtr4; - dtr4 |= BIT15; + dtr4 |= DTR4_ODTDIS; msg_port_write(MEM_CTLR, DTR4, dtr4); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* * Enable Sandy Bridge Mode (WDQ Tri-State) & * Ensure 5 WDQS pulses during Write Leveling */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT28 | BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x10000154, + 0x100003fc); } /* Write Leveling Mode enabled in IO */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - BIT16, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 1 << 16, 1 << 16); /* Initialize the starting delay to WCLK */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1804,15 +1665,15 @@ void wr_level(struct mrc_params *mrc_params) /* disable Write Levelling Mode */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - 0, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 0, 1 << 16); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Disable Sandy Bridge Mode & Ensure 4 WDQS pulses during normal operation */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x00000154, + 0x100003fc); } /* restore original DTR4 */ @@ -1830,7 +1691,7 @@ void wr_level(struct mrc_params *mrc_params) */ dram_init_command(DCMD_PREA(rk)); - mrc_post_code(0x06, (0x30 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); /* * COARSE WRITE LEVEL: @@ -1863,13 +1724,13 @@ void wr_level(struct mrc_params *mrc_params) coarse_result = check_rw_coarse(mrc_params, address); /* check for failures and margin the byte lane back 128 PI (1 CLK) */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (coarse_result & (coarse_result_mask << bl)) { all_edges_found = false; delay[bl] -= FULL_CLK; set_wdqs(ch, rk, bl, delay[bl]); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); + set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); } } } while (!all_edges_found); @@ -1878,11 +1739,11 @@ void wr_level(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; /* accumulate "final_delay[][]" values from "delay[]" values for rolling average */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { final_delay[ch][bl] += delay[bl]; - set_wdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled) - QRTR_CLK); + set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); } #endif #endif @@ -1901,9 +1762,9 @@ void prog_page_ctrl(struct mrc_params *mrc_params) ENTERFN(); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); } @@ -1966,7 +1827,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); } @@ -1981,7 +1842,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* x_coordinate */ x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; @@ -2011,7 +1872,7 @@ void rd_train(struct mrc_params *mrc_params) /* look for passing coordinates */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x10 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x10 + side_y * 2 + side_x); /* find passing values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2021,7 +1882,7 @@ void rd_train(struct mrc_params *mrc_params) (0x1 << rk)) { /* set x/y_coordinate search starting settings */ for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); @@ -2041,9 +1902,9 @@ void rd_train(struct mrc_params *mrc_params) result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { /* adjust the RDQS values accordingly */ @@ -2072,13 +1933,13 @@ void rd_train(struct mrc_params *mrc_params) (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { /* VREF_EYE collapsed below MIN_VREF_EYE */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x70 + (side_y * 2) + (side_x))); + mrc_post_code(0xEE, 0x70 + side_y * 2 + side_x); } else { /* update the VREF setting */ set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); /* reset the X coordinate to begin the search at the new VREF */ x_coordinate[side_x][side_y][ch][rk][bl] = - (side_x == L) ? (RDQS_MIN) : (RDQS_MAX); + (side_x == L) ? RDQS_MIN : RDQS_MAX; } } @@ -2087,7 +1948,7 @@ void rd_train(struct mrc_params *mrc_params) } } } - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2147,23 +2008,23 @@ void rd_train(struct mrc_params *mrc_params) /* perform an eye check */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x30 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x30 + side_y * 2 + side_x); /* update the settings for the eye check */ for (ch = 0; ch < NUM_CHANNELS; ch++) { if (mrc_params->channel_enables & (1 << ch)) { for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (side_x == L) - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); else - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); if (side_y == B) - set_vref(ch, bl, (y_center[ch][bl] - (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); else - set_vref(ch, bl, (y_center[ch][bl] + (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); } } } @@ -2174,9 +2035,9 @@ void rd_train(struct mrc_params *mrc_params) mrc_params->hte_setup = 1; /* check the eye */ - if (check_bls_ex(mrc_params, address) & 0xFF) { + if (check_bls_ex(mrc_params, address) & 0xff) { /* one or more byte lanes failed */ - mrc_post_code(0xEE, (0x74 + (side_x * 2) + (side_y))); + mrc_post_code(0xee, 0x74 + side_x * 2 + side_y); } } } @@ -2197,7 +2058,7 @@ void rd_train(struct mrc_params *mrc_params) /* x_coordinate */ #ifdef R2R_SHARING final_delay[ch][bl] += x_center[ch][rk][bl]; - set_rdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); #else set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); #endif @@ -2258,7 +2119,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); } @@ -2273,7 +2134,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* * want to start with @@ -2303,7 +2164,7 @@ void wr_train(struct mrc_params *mrc_params) * until no failures are observed, then repeat for the RIGHT side. */ for (side = L; side <= R; side++) { - mrc_post_code(0x08, (0x10 + (side))); + mrc_post_code(0x08, 0x10 + side); /* set starting values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2312,7 +2173,7 @@ void wr_train(struct mrc_params *mrc_params) if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); } @@ -2338,9 +2199,9 @@ void wr_train(struct mrc_params *mrc_params) /* result[07:00] == failing byte lane (MAX 8) */ result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { if (side == L) @@ -2362,13 +2223,13 @@ void wr_train(struct mrc_params *mrc_params) * notify the user and halt */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x80 + side)); + mrc_post_code(0xee, 0x80 + side); } } } } /* stop when all byte lanes pass */ - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2384,7 +2245,7 @@ void wr_train(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; #endif - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { DPF(D_INFO, "WDQ eye rank%d lane%d : %d-%d\n", rk, bl, @@ -2396,7 +2257,7 @@ void wr_train(struct mrc_params *mrc_params) #ifdef R2R_SHARING final_delay[ch][bl] += temp; set_wdq(ch, rk, bl, - ((final_delay[ch][bl]) / num_ranks_enabled)); + final_delay[ch][bl] / num_ranks_enabled); #else set_wdq(ch, rk, bl, temp); #endif @@ -2470,7 +2331,7 @@ void enable_scrambling(struct mrc_params *mrc_params) * get seed from system clock * and make sure it is not all 1's */ - lfsr = rdtsc() & 0x0FFFFFFF; + lfsr = rdtsc() & 0x0fffffff; } else { /* * Need to replace scrambler @@ -2491,10 +2352,10 @@ void enable_scrambling(struct mrc_params *mrc_params) * In cold boot, we have the last 32bit LFSR which is the new seed. */ lfsr32(&lfsr); /* shift to next value */ - msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003FFFF)); + msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003ffff)); for (i = 0; i < 2; i++) - msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xAAAAAAAA)); + msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xaaaaaaaa)); LEAVEFN(); } @@ -2511,20 +2372,20 @@ void prog_ddr_control(struct mrc_params *mrc_params) ENTERFN(); dsch = msg_port_read(MEM_CTLR, DSCH); - dsch &= ~(BIT8 | BIT9 | BIT12); + dsch &= ~(DSCH_OOODIS | DSCH_OOOST3DIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~BIT25; + dpmc0 &= ~DPMC0_DISPWRDN; dpmc0 |= (mrc_params->power_down_disable << 25); - dpmc0 &= ~BIT24; - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_CLKGTDIS; + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */ - mrc_write_mask(MEM_CTLR, DPMC1, 2 << 4, BIT4 | BIT5); + mrc_write_mask(MEM_CTLR, DPMC1, 0x20, 0x30); LEAVEFN(); } @@ -2542,14 +2403,14 @@ void prog_dra_drb(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT31; + dco &= ~DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; if (mrc_params->dram_width == X16) { drp |= (1 << 4); drp |= (1 << 9); @@ -2570,8 +2431,8 @@ void prog_dra_drb(struct mrc_params *mrc_params) msg_port_write(MEM_CTLR, DRP, drp); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -2600,18 +2461,18 @@ void change_refresh_period(struct mrc_params *mrc_params) ENTERFN(); drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; drfc |= (mrc_params->refresh_rate << 12); - drfc |= BIT21; + drfc |= DRFC_REFDBTCLR; msg_port_write(MEM_CTLR, DRFC, drfc); dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); + dcal &= ~DCAL_ZQCINT_MASK; dcal |= (3 << 8); /* 63ms */ msg_port_write(MEM_CTLR, DCAL, dcal); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT23 | BIT29); + dpmc0 |= (DPMC0_DYNSREN | DPMC0_ENPHYCLKGATE); msg_port_write(MEM_CTLR, DPMC0, dpmc0); LEAVEFN(); @@ -2638,36 +2499,32 @@ void set_auto_refresh(struct mrc_params *mrc_params) for (channel = 0; channel < NUM_CHANNELS; channel++) { if (mrc_params->channel_enables & (1 << channel)) { /* Enable Periodic RCOMPS */ - mrc_alt_write_mask(DDRPHY, CMPCTRL, BIT1, BIT1); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 2, 2); /* Enable Dynamic DiffAmp & Set Read ODT Value */ switch (mrc_params->rd_odt_value) { case 0: - temp = 0x3F; /* OFF */ + temp = 0x3f; /* OFF */ break; default: temp = 0x00; /* Auto */ break; } - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B0OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B1OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); } /* Issue ZQCS command */ @@ -2702,18 +2559,18 @@ void ecc_enable(struct mrc_params *mrc_params) /* Configuration required in ECC mode */ drp = msg_port_read(MEM_CTLR, DRP); - drp &= ~(BIT14 | BIT15); - drp |= BIT15; - drp |= BIT13; + drp &= ~DRP_ADDRMAP_MASK; + drp |= DRP_ADDRMAP_MAP1; + drp |= DRP_PRI64BSPLITEN; msg_port_write(MEM_CTLR, DRP, drp); /* Disable new request bypass */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= BIT12; + dsch |= DSCH_NEWBYPDIS; msg_port_write(MEM_CTLR, DSCH, dsch); /* Enable ECC */ - ecc_ctrl = (BIT0 | BIT1 | BIT17); + ecc_ctrl = (DECCCTRL_SBEEN | DECCCTRL_DBEEN | DECCCTRL_ENCBGEN); msg_port_write(MEM_CTLR, DECCCTRL, ecc_ctrl); /* Assume 8 bank memory, one bank is gone for ECC */ @@ -2756,8 +2613,8 @@ void lock_registers(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~(BIT28 | BIT29); - dco |= (BIT0 | BIT8); + dco &= ~(DCO_PMICTL | DCO_PMIDIS); + dco |= (DCO_DRPLOCK | DCO_CPGCLOCK); msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); diff --git a/arch/x86/cpu/quark/smc.h b/arch/x86/cpu/quark/smc.h index 46017a1ccb..1582b87e10 100644 --- a/arch/x86/cpu/quark/smc.h +++ b/arch/x86/cpu/quark/smc.h @@ -24,46 +24,133 @@ #define DPMC1 0x07 #define DRFC 0x08 #define DSCH 0x09 -#define DCAL 0x0A -#define DRMC 0x0B -#define PMSTS 0x0C -#define DCO 0x0F +#define DCAL 0x0a +#define DRMC 0x0b +#define PMSTS 0x0c +#define DCO 0x0f #define DSTAT 0x20 -#define SSKPD0 0x4A -#define SSKPD1 0x4B +#define SSKPD0 0x4a +#define SSKPD1 0x4b #define DECCCTRL 0x60 #define DECCSTAT 0x61 #define DECCSBECNT 0x62 #define DECCSBECA 0x68 #define DECCSBECS 0x69 -#define DECCDBECA 0x6A -#define DECCDBECS 0x6B +#define DECCDBECA 0x6a +#define DECCDBECS 0x6b #define DFUSESTAT 0x70 #define SCRMSEED 0x80 #define SCRMLO 0x81 #define SCRMHI 0x82 +/* DRP register defines */ +#define DRP_RKEN0 (1 << 0) +#define DRP_RKEN1 (1 << 1) +#define DRP_PRI64BSPLITEN (1 << 13) +#define DRP_ADDRMAP_MAP0 (1 << 14) +#define DRP_ADDRMAP_MAP1 (1 << 15) +#define DRP_ADDRMAP_MASK 0x0000c000 + +/* DTR0 register defines */ +#define DTR0_DFREQ_MASK 0x00000003 +#define DTR0_TRP_MASK 0x000000f0 +#define DTR0_TRCD_MASK 0x00000f00 +#define DTR0_TCL_MASK 0x00007000 + +/* DTR1 register defines */ +#define DTR1_TWCL_MASK 0x00000007 +#define DTR1_TCMD_MASK 0x00000030 +#define DTR1_TWTP_MASK 0x00000f00 +#define DTR1_TCCD_12CLK (1 << 12) +#define DTR1_TCCD_18CLK (1 << 13) +#define DTR1_TCCD_MASK 0x00003000 +#define DTR1_TFAW_MASK 0x000f0000 +#define DTR1_TRAS_MASK 0x00f00000 +#define DTR1_TRRD_MASK 0x03000000 +#define DTR1_TRTP_MASK 0x70000000 + +/* DTR2 register defines */ +#define DTR2_TRRDR_MASK 0x00000007 +#define DTR2_TWWDR_MASK 0x00000700 +#define DTR2_TRWDR_MASK 0x000f0000 + +/* DTR3 register defines */ +#define DTR3_TWRDR_MASK 0x00000007 +#define DTR3_TXXXX_MASK 0x00000070 +#define DTR3_TRWSR_MASK 0x00000f00 +#define DTR3_TWRSR_MASK 0x0001e000 +#define DTR3_TXP_MASK 0x00c00000 + +/* DTR4 register defines */ +#define DTR4_WRODTSTRT_MASK 0x00000003 +#define DTR4_WRODTSTOP_MASK 0x00000070 +#define DTR4_XXXX1_MASK 0x00000700 +#define DTR4_XXXX2_MASK 0x00007000 +#define DTR4_ODTDIS (1 << 15) +#define DTR4_TRGSTRDIS (1 << 16) + +/* DPMC0 register defines */ +#define DPMC0_PCLSTO_MASK 0x00070000 +#define DPMC0_PREAPWDEN (1 << 21) +#define DPMC0_DYNSREN (1 << 23) +#define DPMC0_CLKGTDIS (1 << 24) +#define DPMC0_DISPWRDN (1 << 25) +#define DPMC0_ENPHYCLKGATE (1 << 29) + +/* DRFC register defines */ +#define DRFC_TREFI_MASK 0x00007000 +#define DRFC_REFDBTCLR (1 << 21) + +/* DSCH register defines */ +#define DSCH_OOODIS (1 << 8) +#define DSCH_OOOST3DIS (1 << 9) +#define DSCH_NEWBYPDIS (1 << 12) + +/* DCAL register defines */ +#define DCAL_ZQCINT_MASK 0x00000700 +#define DCAL_SRXZQCL_MASK 0x00003000 + +/* DRMC register defines */ +#define DRMC_CKEMODE (1 << 4) +#define DRMC_ODTMODE (1 << 12) +#define DRMC_COLDWAKE (1 << 16) + +/* PMSTS register defines */ +#define PMSTS_DISR (1 << 0) + +/* DCO register defines */ +#define DCO_DRPLOCK (1 << 0) +#define DCO_CPGCLOCK (1 << 8) +#define DCO_PMICTL (1 << 28) +#define DCO_PMIDIS (1 << 29) +#define DCO_IC (1 << 31) + +/* DECCCTRL register defines */ +#define DECCCTRL_SBEEN (1 << 0) +#define DECCCTRL_DBEEN (1 << 1) +#define DECCCTRL_ENCBGEN (1 << 17) + /* DRAM init command */ #define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6)) #define DCMD_REF(rnk) (1 | ((rnk) << 22)) #define DCMD_PRE(rnk) (2 | ((rnk) << 22)) -#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (BIT10 << 6)) +#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6)) #define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6)) #define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6)) #define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6)) #define DCMD_ZQCS(rnk) (6 | ((rnk) << 22)) -#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (BIT10 << 6)) +#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6)) #define DCMD_NOP(rnk) (7 | ((rnk) << 22)) -#define DDR3_EMRS1_DIC_40 (0) -#define DDR3_EMRS1_DIC_34 (1) +#define DDR3_EMRS1_DIC_40 0 +#define DDR3_EMRS1_DIC_34 1 -#define DDR3_EMRS1_RTTNOM_0 (0) -#define DDR3_EMRS1_RTTNOM_60 (0x04) -#define DDR3_EMRS1_RTTNOM_120 (0x40) -#define DDR3_EMRS1_RTTNOM_40 (0x44) -#define DDR3_EMRS1_RTTNOM_20 (0x200) -#define DDR3_EMRS1_RTTNOM_30 (0x204) +#define DDR3_EMRS1_RTTNOM_0 0 +#define DDR3_EMRS1_RTTNOM_60 0x04 +#define DDR3_EMRS1_RTTNOM_120 0x40 +#define DDR3_EMRS1_RTTNOM_40 0x44 +#define DDR3_EMRS1_RTTNOM_20 0x200 +#define DDR3_EMRS1_RTTNOM_30 0x204 #define DDR3_EMRS2_RTTWR_60 (1 << 9) #define DDR3_EMRS2_RTTWR_120 (1 << 10) @@ -80,87 +167,87 @@ #define DQOBSCKEBBCTL 0x0000 #define DQDLLTXCTL 0x0004 #define DQDLLRXCTL 0x0008 -#define DQMDLLCTL 0x000C +#define DQMDLLCTL 0x000c #define B0RXIOBUFCTL 0x0010 #define B0VREFCTL 0x0014 #define B0RXOFFSET1 0x0018 -#define B0RXOFFSET0 0x001C +#define B0RXOFFSET0 0x001c #define B1RXIOBUFCTL 0x0020 #define B1VREFCTL 0x0024 #define B1RXOFFSET1 0x0028 -#define B1RXOFFSET0 0x002C +#define B1RXOFFSET0 0x002c #define DQDFTCTL 0x0030 #define DQTRAINSTS 0x0034 #define B1DLLPICODER0 0x0038 -#define B0DLLPICODER0 0x003C +#define B0DLLPICODER0 0x003c #define B1DLLPICODER1 0x0040 #define B0DLLPICODER1 0x0044 #define B1DLLPICODER2 0x0048 -#define B0DLLPICODER2 0x004C +#define B0DLLPICODER2 0x004c #define B1DLLPICODER3 0x0050 #define B0DLLPICODER3 0x0054 #define B1RXDQSPICODE 0x0058 -#define B0RXDQSPICODE 0x005C +#define B0RXDQSPICODE 0x005c #define B1RXDQPICODER32 0x0060 #define B1RXDQPICODER10 0x0064 #define B0RXDQPICODER32 0x0068 -#define B0RXDQPICODER10 0x006C +#define B0RXDQPICODER10 0x006c #define B01PTRCTL0 0x0070 #define B01PTRCTL1 0x0074 #define B01DBCTL0 0x0078 -#define B01DBCTL1 0x007C +#define B01DBCTL1 0x007c #define B0LATCTL0 0x0080 #define B1LATCTL0 0x0084 #define B01LATCTL1 0x0088 -#define B0ONDURCTL 0x008C +#define B0ONDURCTL 0x008c #define B1ONDURCTL 0x0090 #define B0OVRCTL 0x0094 #define B1OVRCTL 0x0098 -#define DQCTL 0x009C -#define B0RK2RKCHGPTRCTRL 0x00A0 -#define B1RK2RKCHGPTRCTRL 0x00A4 -#define DQRK2RKCTL 0x00A8 -#define DQRK2RKPTRCTL 0x00AC -#define B0RK2RKLAT 0x00B0 -#define B1RK2RKLAT 0x00B4 -#define DQCLKALIGNREG0 0x00B8 -#define DQCLKALIGNREG1 0x00BC -#define DQCLKALIGNREG2 0x00C0 -#define DQCLKALIGNSTS0 0x00C4 -#define DQCLKALIGNSTS1 0x00C8 -#define DQCLKGATE 0x00CC -#define B0COMPSLV1 0x00D0 -#define B1COMPSLV1 0x00D4 -#define B0COMPSLV2 0x00D8 -#define B1COMPSLV2 0x00DC -#define B0COMPSLV3 0x00E0 -#define B1COMPSLV3 0x00E4 -#define DQVISALANECR0TOP 0x00E8 -#define DQVISALANECR1TOP 0x00EC -#define DQVISACONTROLCRTOP 0x00F0 -#define DQVISALANECR0BL 0x00F4 -#define DQVISALANECR1BL 0x00F8 -#define DQVISACONTROLCRBL 0x00FC -#define DQTIMINGCTRL 0x010C +#define DQCTL 0x009c +#define B0RK2RKCHGPTRCTRL 0x00a0 +#define B1RK2RKCHGPTRCTRL 0x00a4 +#define DQRK2RKCTL 0x00a8 +#define DQRK2RKPTRCTL 0x00ac +#define B0RK2RKLAT 0x00b0 +#define B1RK2RKLAT 0x00b4 +#define DQCLKALIGNREG0 0x00b8 +#define DQCLKALIGNREG1 0x00bc +#define DQCLKALIGNREG2 0x00c0 +#define DQCLKALIGNSTS0 0x00c4 +#define DQCLKALIGNSTS1 0x00c8 +#define DQCLKGATE 0x00cc +#define B0COMPSLV1 0x00d0 +#define B1COMPSLV1 0x00d4 +#define B0COMPSLV2 0x00d8 +#define B1COMPSLV2 0x00dc +#define B0COMPSLV3 0x00e0 +#define B1COMPSLV3 0x00e4 +#define DQVISALANECR0TOP 0x00e8 +#define DQVISALANECR1TOP 0x00ec +#define DQVISACONTROLCRTOP 0x00f0 +#define DQVISALANECR0BL 0x00f4 +#define DQVISALANECR1BL 0x00f8 +#define DQVISACONTROLCRBL 0x00fc +#define DQTIMINGCTRL 0x010c /* CH0-ECC */ #define ECCDLLTXCTL 0x2004 #define ECCDLLRXCTL 0x2008 -#define ECCMDLLCTL 0x200C +#define ECCMDLLCTL 0x200c #define ECCB1DLLPICODER0 0x2038 #define ECCB1DLLPICODER1 0x2040 #define ECCB1DLLPICODER2 0x2048 #define ECCB1DLLPICODER3 0x2050 #define ECCB01DBCTL0 0x2078 -#define ECCB01DBCTL1 0x207C -#define ECCCLKALIGNREG0 0x20B8 -#define ECCCLKALIGNREG1 0x20BC -#define ECCCLKALIGNREG2 0x20C0 +#define ECCB01DBCTL1 0x207c +#define ECCCLKALIGNREG0 0x20b8 +#define ECCCLKALIGNREG1 0x20bc +#define ECCCLKALIGNREG2 0x20c0 /* CH0-CMD */ #define CMDOBSCKEBBCTL 0x4800 #define CMDDLLTXCTL 0x4808 -#define CMDDLLRXCTL 0x480C +#define CMDDLLRXCTL 0x480c #define CMDMDLLCTL 0x4810 #define CMDRCOMPODT 0x4814 #define CMDDLLPICODER0 0x4820 @@ -170,30 +257,30 @@ #define CMDCLKALIGNREG0 0x4850 #define CMDCLKALIGNREG1 0x4854 #define CMDCLKALIGNREG2 0x4858 -#define CMDPMCONFIG0 0x485C +#define CMDPMCONFIG0 0x485c #define CMDPMDLYREG0 0x4860 #define CMDPMDLYREG1 0x4864 #define CMDPMDLYREG2 0x4868 -#define CMDPMDLYREG3 0x486C +#define CMDPMDLYREG3 0x486c #define CMDPMDLYREG4 0x4870 #define CMDCLKALIGNSTS0 0x4874 #define CMDCLKALIGNSTS1 0x4878 -#define CMDPMSTS0 0x487C +#define CMDPMSTS0 0x487c #define CMDPMSTS1 0x4880 #define CMDCOMPSLV 0x4884 -#define CMDBONUS0 0x488C +#define CMDBONUS0 0x488c #define CMDBONUS1 0x4890 #define CMDVISALANECR0 0x4894 #define CMDVISALANECR1 0x4898 -#define CMDVISACONTROLCR 0x489C -#define CMDCLKGATE 0x48A0 -#define CMDTIMINGCTRL 0x48A4 +#define CMDVISACONTROLCR 0x489c +#define CMDCLKGATE 0x48a0 +#define CMDTIMINGCTRL 0x48a4 /* CH0-CLK-CTL */ #define CCOBSCKEBBCTL 0x5800 #define CCRCOMPIO 0x5804 #define CCDLLTXCTL 0x5808 -#define CCDLLRXCTL 0x580C +#define CCDLLRXCTL 0x580c #define CCMDLLCTL 0x5810 #define CCRCOMPODT 0x5814 #define CCDLLPICODER0 0x5820 @@ -205,123 +292,123 @@ #define CCCLKALIGNREG0 0x5850 #define CCCLKALIGNREG1 0x5854 #define CCCLKALIGNREG2 0x5858 -#define CCPMCONFIG0 0x585C +#define CCPMCONFIG0 0x585c #define CCPMDLYREG0 0x5860 #define CCPMDLYREG1 0x5864 #define CCPMDLYREG2 0x5868 -#define CCPMDLYREG3 0x586C +#define CCPMDLYREG3 0x586c #define CCPMDLYREG4 0x5870 #define CCCLKALIGNSTS0 0x5874 #define CCCLKALIGNSTS1 0x5878 -#define CCPMSTS0 0x587C +#define CCPMSTS0 0x587c #define CCPMSTS1 0x5880 #define CCCOMPSLV1 0x5884 #define CCCOMPSLV2 0x5888 -#define CCCOMPSLV3 0x588C +#define CCCOMPSLV3 0x588c #define CCBONUS0 0x5894 #define CCBONUS1 0x5898 -#define CCVISALANECR0 0x589C -#define CCVISALANECR1 0x58A0 -#define CCVISACONTROLCR 0x58A4 -#define CCCLKGATE 0x58A8 -#define CCTIMINGCTL 0x58AC +#define CCVISALANECR0 0x589c +#define CCVISALANECR1 0x58a0 +#define CCVISACONTROLCR 0x58a4 +#define CCCLKGATE 0x58a8 +#define CCTIMINGCTL 0x58ac /* COMP */ #define CMPCTRL 0x6800 #define SOFTRSTCNTL 0x6804 #define MSCNTR 0x6808 -#define NMSCNTRL 0x680C +#define NMSCNTRL 0x680c #define LATCH1CTL 0x6814 -#define COMPVISALANECR0 0x681C +#define COMPVISALANECR0 0x681c #define COMPVISALANECR1 0x6820 #define COMPVISACONTROLCR 0x6824 #define COMPBONUS0 0x6830 -#define TCOCNTCTRL 0x683C +#define TCOCNTCTRL 0x683c #define DQANAODTPUCTL 0x6840 #define DQANAODTPDCTL 0x6844 #define DQANADRVPUCTL 0x6848 -#define DQANADRVPDCTL 0x684C +#define DQANADRVPDCTL 0x684c #define DQANADLYPUCTL 0x6850 #define DQANADLYPDCTL 0x6854 #define DQANATCOPUCTL 0x6858 -#define DQANATCOPDCTL 0x685C +#define DQANATCOPDCTL 0x685c #define CMDANADRVPUCTL 0x6868 -#define CMDANADRVPDCTL 0x686C +#define CMDANADRVPDCTL 0x686c #define CMDANADLYPUCTL 0x6870 #define CMDANADLYPDCTL 0x6874 #define CLKANAODTPUCTL 0x6880 #define CLKANAODTPDCTL 0x6884 #define CLKANADRVPUCTL 0x6888 -#define CLKANADRVPDCTL 0x688C +#define CLKANADRVPDCTL 0x688c #define CLKANADLYPUCTL 0x6890 #define CLKANADLYPDCTL 0x6894 #define CLKANATCOPUCTL 0x6898 -#define CLKANATCOPDCTL 0x689C -#define DQSANAODTPUCTL 0x68A0 -#define DQSANAODTPDCTL 0x68A4 -#define DQSANADRVPUCTL 0x68A8 -#define DQSANADRVPDCTL 0x68AC -#define DQSANADLYPUCTL 0x68B0 -#define DQSANADLYPDCTL 0x68B4 -#define DQSANATCOPUCTL 0x68B8 -#define DQSANATCOPDCTL 0x68BC -#define CTLANADRVPUCTL 0x68C8 -#define CTLANADRVPDCTL 0x68CC -#define CTLANADLYPUCTL 0x68D0 -#define CTLANADLYPDCTL 0x68D4 -#define CHNLBUFSTATIC 0x68F0 -#define COMPOBSCNTRL 0x68F4 -#define COMPBUFFDBG0 0x68F8 -#define COMPBUFFDBG1 0x68FC +#define CLKANATCOPDCTL 0x689c +#define DQSANAODTPUCTL 0x68a0 +#define DQSANAODTPDCTL 0x68a4 +#define DQSANADRVPUCTL 0x68a8 +#define DQSANADRVPDCTL 0x68ac +#define DQSANADLYPUCTL 0x68b0 +#define DQSANADLYPDCTL 0x68b4 +#define DQSANATCOPUCTL 0x68b8 +#define DQSANATCOPDCTL 0x68bc +#define CTLANADRVPUCTL 0x68c8 +#define CTLANADRVPDCTL 0x68cc +#define CTLANADLYPUCTL 0x68d0 +#define CTLANADLYPDCTL 0x68d4 +#define CHNLBUFSTATIC 0x68f0 +#define COMPOBSCNTRL 0x68f4 +#define COMPBUFFDBG0 0x68f8 +#define COMPBUFFDBG1 0x68fc #define CFGMISCCH0 0x6900 #define COMPEN0CH0 0x6904 #define COMPEN1CH0 0x6908 -#define COMPEN2CH0 0x690C +#define COMPEN2CH0 0x690c #define STATLEGEN0CH0 0x6910 #define STATLEGEN1CH0 0x6914 #define DQVREFCH0 0x6918 -#define CMDVREFCH0 0x691C +#define CMDVREFCH0 0x691c #define CLKVREFCH0 0x6920 #define DQSVREFCH0 0x6924 #define CTLVREFCH0 0x6928 -#define TCOVREFCH0 0x692C +#define TCOVREFCH0 0x692c #define DLYSELCH0 0x6930 #define TCODRAMBUFODTCH0 0x6934 #define CCBUFODTCH0 0x6938 -#define RXOFFSETCH0 0x693C +#define RXOFFSETCH0 0x693c #define DQODTPUCTLCH0 0x6940 #define DQODTPDCTLCH0 0x6944 #define DQDRVPUCTLCH0 0x6948 -#define DQDRVPDCTLCH0 0x694C +#define DQDRVPDCTLCH0 0x694c #define DQDLYPUCTLCH0 0x6950 #define DQDLYPDCTLCH0 0x6954 #define DQTCOPUCTLCH0 0x6958 -#define DQTCOPDCTLCH0 0x695C +#define DQTCOPDCTLCH0 0x695c #define CMDDRVPUCTLCH0 0x6968 -#define CMDDRVPDCTLCH0 0x696C +#define CMDDRVPDCTLCH0 0x696c #define CMDDLYPUCTLCH0 0x6970 #define CMDDLYPDCTLCH0 0x6974 #define CLKODTPUCTLCH0 0x6980 #define CLKODTPDCTLCH0 0x6984 #define CLKDRVPUCTLCH0 0x6988 -#define CLKDRVPDCTLCH0 0x698C +#define CLKDRVPDCTLCH0 0x698c #define CLKDLYPUCTLCH0 0x6990 #define CLKDLYPDCTLCH0 0x6994 #define CLKTCOPUCTLCH0 0x6998 -#define CLKTCOPDCTLCH0 0x699C -#define DQSODTPUCTLCH0 0x69A0 -#define DQSODTPDCTLCH0 0x69A4 -#define DQSDRVPUCTLCH0 0x69A8 -#define DQSDRVPDCTLCH0 0x69AC -#define DQSDLYPUCTLCH0 0x69B0 -#define DQSDLYPDCTLCH0 0x69B4 -#define DQSTCOPUCTLCH0 0x69B8 -#define DQSTCOPDCTLCH0 0x69BC -#define CTLDRVPUCTLCH0 0x69C8 -#define CTLDRVPDCTLCH0 0x69CC -#define CTLDLYPUCTLCH0 0x69D0 -#define CTLDLYPDCTLCH0 0x69D4 -#define FNLUPDTCTLCH0 0x69F0 +#define CLKTCOPDCTLCH0 0x699c +#define DQSODTPUCTLCH0 0x69a0 +#define DQSODTPDCTLCH0 0x69a4 +#define DQSDRVPUCTLCH0 0x69a8 +#define DQSDRVPDCTLCH0 0x69ac +#define DQSDLYPUCTLCH0 0x69b0 +#define DQSDLYPDCTLCH0 0x69b4 +#define DQSTCOPUCTLCH0 0x69b8 +#define DQSTCOPDCTLCH0 0x69bc +#define CTLDRVPUCTLCH0 0x69c8 +#define CTLDRVPDCTLCH0 0x69cc +#define CTLDLYPUCTLCH0 0x69d0 +#define CTLDLYPDCTLCH0 0x69d4 +#define FNLUPDTCTLCH0 0x69f0 /* PLL */ #define MPLLCTRL0 0x7800 @@ -332,17 +419,17 @@ #define MPLLDFT 0x7828 #define MPLLMON0CTL 0x7830 #define MPLLMON1CTL 0x7838 -#define MPLLMON2CTL 0x783C +#define MPLLMON2CTL 0x783c #define SFRTRIM 0x7850 #define MPLLDFTOUT0 0x7858 -#define MPLLDFTOUT1 0x785C +#define MPLLDFTOUT1 0x785c #define MASTERRSTN 0x7880 #define PLLLOCKDEL 0x7884 #define SFRDEL 0x7888 -#define CRUVISALANECR0 0x78F0 -#define CRUVISALANECR1 0x78F4 -#define CRUVISACONTROLCR 0x78F8 -#define IOSFVISALANECR0 0x78FC +#define CRUVISALANECR0 0x78f0 +#define CRUVISALANECR1 0x78f4 +#define CRUVISACONTROLCR 0x78f8 +#define IOSFVISALANECR0 0x78fc #define IOSFVISALANECR1 0x7900 #define IOSFVISACONTROLCR 0x7904 @@ -350,7 +437,7 @@ /* DRAM Specific Message Bus OpCodes */ #define MSG_OP_DRAM_INIT 0x68 -#define MSG_OP_DRAM_WAKE 0xCA +#define MSG_OP_DRAM_WAKE 0xca #define SAMPLE_SIZE 6 @@ -377,9 +464,9 @@ /* offset into "vref_codes[]" for minimum allowed VREF setting */ #define VREF_MIN 0x00 /* offset into "vref_codes[]" for maximum allowed VREF setting */ -#define VREF_MAX 0x3F +#define VREF_MAX 0x3f #define RDQS_MIN 0x00 /* minimum RDQS delay value */ -#define RDQS_MAX 0x3F /* maximum RDQS delay value */ +#define RDQS_MAX 0x3f /* maximum RDQS delay value */ /* how many WDQ codes to jump while margining */ #define WDQ_STEP 1 diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index f51f1121d0..2e5f9da756 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -11,7 +11,6 @@ */ #include <config.h> -#include <version.h> #include <asm/global_data.h> #include <asm/post.h> #include <asm/processor.h> diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index ff15828a71..3a891ba627 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index 39afbba7db..e4896fba14 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -16,10 +16,9 @@ int load_lcdtiming(struct am335x_lcdpanel *panel); void br_summaryscreen(void); -void blink(u32 blinks, u32 intervall, u32 pin); void pmicsetup(u32 mpupll); void enable_uart0_pin_mux(void); -void enable_i2c0_pin_mux(void); +void enable_i2c_pin_mux(void); void enable_board_pin_mux(void); int board_eth_init(bd_t *bis); diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 5ff8a7e0ae..ccaa9c6845 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -441,30 +441,12 @@ void lcd_enable(void) #error "LCD-support with a suitable FB-Driver is mandatory !" #endif /* CONFIG_LCD */ -void blink(u32 blinks, u32 intervall, u32 pin) -{ - gpio_direction_output(pin, 0); - int val = 0; - - do { - val ^= 0x01; - gpio_set_value(pin, val); - mdelay(intervall); - } while (blinks--); - - gpio_set_value(pin, 0); -} - #ifdef CONFIG_SPL_BUILD void pmicsetup(u32 mpupll) { int mpu_vdd; int usb_cur_lim; - /* setup I2C */ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (i2c_probe(TPS65217_CHIP_PM)) { puts("PMIC (0x24) not found! skip further initalization.\n"); return; diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c index 892311e6ee..6eed7e0d7f 100644 --- a/board/BuR/kwb/board.c +++ b/board/BuR/kwb/board.c @@ -124,7 +124,8 @@ void am33xx_spl_board_init(void) gpio_direction_output(LCD_PWR, 0); /* setup I2C */ - enable_i2c0_pin_mux(); + enable_i2c_pin_mux(); + i2c_set_bus_num(0); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); /* power-ON 3V3 via Resetcontroller */ diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c index 9f89b5e53d..2b1d8d3b1d 100644 --- a/board/BuR/kwb/mux.c +++ b/board/BuR/kwb/mux.c @@ -180,7 +180,7 @@ void enable_uart0_pin_mux(void) configure_module_pin_mux(uart0_pin_mux); } -void enable_i2c0_pin_mux(void) +void enable_i2c_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c index 9402aa4205..89e989f246 100644 --- a/board/BuR/tseries/board.c +++ b/board/BuR/tseries/board.c @@ -123,6 +123,10 @@ void am33xx_spl_board_init(void) /* setup LCD-Pixel Clock */ writel(0x2, &cmdpll->clklcdcpixelclk); /* clock comes from perPLL M2 */ + /* setup I2C */ + enable_i2c_pin_mux(); + i2c_set_bus_num(0); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); pmicsetup(0); } diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c index 2c87a63b85..ac7e885f61 100644 --- a/board/BuR/tseries/mux.c +++ b/board/BuR/tseries/mux.c @@ -226,7 +226,7 @@ void enable_uart0_pin_mux(void) configure_module_pin_mux(uart0_pin_mux); } -void enable_i2c0_pin_mux(void) +void enable_i2c_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S index d5900a8c99..0c40a3ce4d 100644 --- a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S +++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S @@ -5,7 +5,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig index 033deaf7d6..7c0ef534ab 100644 --- a/board/amcc/acadia/Kconfig +++ b/board/amcc/acadia/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "acadia" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig index c0bd40aee7..d44a36a573 100644 --- a/board/amcc/bamboo/Kconfig +++ b/board/amcc/bamboo/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "bamboo" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig index 540d9b6235..fc40f6ed96 100644 --- a/board/amcc/bubinga/Kconfig +++ b/board/amcc/bubinga/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "bubinga" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index 848e08fbba..46efa7a79f 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -39,12 +39,4 @@ config DM config DM_SERIAL default y -config SYS_MALLOC_F - bool - default y - -config SYS_MALLOC_F_LEN - hex - default 0x400 - endif diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig index 62394b68fa..ba73148f7f 100644 --- a/board/amcc/ebony/Kconfig +++ b/board/amcc/ebony/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ebony" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig index fc606cff1c..59d3ef5883 100644 --- a/board/amcc/katmai/Kconfig +++ b/board/amcc/katmai/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "katmai" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig index 3f2f434827..5dfd9ebe3f 100644 --- a/board/amcc/kilauea/Kconfig +++ b/board/amcc/kilauea/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "kilauea" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig index 3df90af484..36b44fffa9 100644 --- a/board/amcc/luan/Kconfig +++ b/board/amcc/luan/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "luan" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig index 31ce5f10c6..7f8498a533 100644 --- a/board/amcc/makalu/Kconfig +++ b/board/amcc/makalu/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "makalu" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/ocotea/Kconfig b/board/amcc/ocotea/Kconfig index 18c1a15ef4..489e8a4da3 100644 --- a/board/amcc/ocotea/Kconfig +++ b/board/amcc/ocotea/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ocotea" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig index d710590998..fee644146e 100644 --- a/board/amcc/redwood/Kconfig +++ b/board/amcc/redwood/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "redwood" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig index 67ee3ca2eb..6e6e408ed5 100644 --- a/board/amcc/sequoia/Kconfig +++ b/board/amcc/sequoia/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "sequoia" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/taihu/Kconfig b/board/amcc/taihu/Kconfig index fc5cb1de7e..faafb08941 100644 --- a/board/amcc/taihu/Kconfig +++ b/board/amcc/taihu/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "taihu" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/taishan/Kconfig b/board/amcc/taishan/Kconfig index abd07f570d..9ad8a4ce64 100644 --- a/board/amcc/taishan/Kconfig +++ b/board/amcc/taishan/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "taishan" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig index 94e3dc9e78..d4c451dc07 100644 --- a/board/amcc/walnut/Kconfig +++ b/board/amcc/walnut/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "walnut" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig index dfa10687c2..ec51236306 100644 --- a/board/amcc/yosemite/Kconfig +++ b/board/amcc/yosemite/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "yosemite" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig index 61d95891e4..338b6a90c9 100644 --- a/board/amcc/yucca/Kconfig +++ b/board/amcc/yucca/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "yucca" +config DISPLAY_BOARDINFO + bool + default y + endif diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S index 4293cb1080..2f795e460a 100644 --- a/board/armadeus/apf27/lowlevel_init.S +++ b/board/armadeus/apf27/lowlevel_init.S @@ -6,7 +6,6 @@ #include <config.h> #include <generated/asm-offsets.h> -#include <version.h> #include <asm/macro.h> #include <asm/arch/imx-regs.h> #include "apf27.h" diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S index 0fb42adc6f..b50ba9878c 100644 --- a/board/armltd/integrator/lowlevel_init.S +++ b/board/armltd/integrator/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> /* Reset using CM control register */ .global reset_cpu diff --git a/board/armltd/versatile/lowlevel_init.S b/board/armltd/versatile/lowlevel_init.S index 902d646efb..539ba41e66 100644 --- a/board/armltd/versatile/lowlevel_init.S +++ b/board/armltd/versatile/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> /* Set up the platform, once the cpu has been initialized */ .globl lowlevel_init diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 7d5e7bee8b..f5693aebac 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -1,16 +1,3 @@ -if TARGET_VEXPRESS64_AEMV8A - -config SYS_BOARD - default "vexpress64" - -config SYS_VENDOR - default "armltd" - -config SYS_CONFIG_NAME - default "vexpress_aemv8a" - -endif - if TARGET_VEXPRESS64_BASE_FVP config SYS_BOARD diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index de6286435d..13dd667436 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -11,10 +11,22 @@ #include <netdev.h> #include <asm/io.h> #include <linux/compiler.h> -#include <asm/semihosting.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_pl01x.h> DECLARE_GLOBAL_DATA_PTR; +static const struct pl01x_serial_platdata serial_platdata = { + .base = V2M_UART0, + .type = TYPE_PL011, + .clock = 2400 * 1000, +}; + +U_BOOT_DEVICE(vexpress_serials) = { + .name = "serial_pl01x", + .platdata = &serial_platdata, +}; + int board_init(void) { return 0; @@ -33,101 +45,6 @@ void reset_cpu(ulong addr) { } -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_SEMIHOSTING - /* - * Please refer to doc/README.semihosting for a more complete - * description. - * - * We require that the board include file defines these env variables: - * - kernel_name - * - kernel_addr_r - * - initrd_name - * - initrd_addr_r - * - fdt_name - * - fdt_addr_r - * - * For the "fdt chosen" startup macro, this code will then define: - * - initrd_end (based on initrd_addr_r plus actual initrd_size) - * - * We will then load the kernel, initrd, and fdt into the specified - * locations in memory in a similar way that the ATF fastmodel code - * uses semihosting calls to load other boot stages and u-boot itself. - */ - - /* Env variable strings */ - char *kernel_name = getenv("kernel_name"); - char *kernel_addr_str = getenv("kernel_addr_r"); - char *initrd_name = getenv("initrd_name"); - char *initrd_addr_str = getenv("initrd_addr_r"); - char *fdt_name = getenv("fdt_name"); - char *fdt_addr_str = getenv("fdt_addr_r"); - char initrd_end_str[64]; - - /* Actual addresses converted from env variables */ - void *kernel_addr_r; - void *initrd_addr_r; - void *fdt_addr_r; - - /* Actual initrd base and size */ - unsigned long initrd_base; - unsigned long initrd_size; - - /* Space available */ - int avail; - - /* Make sure the environment variables needed are set */ - if (!(kernel_addr_str && initrd_addr_str && fdt_addr_str)) { - printf("%s: Define {kernel/initrd/fdt}_addr_r\n", __func__); - return -1; - } - if (!(kernel_name && initrd_name && fdt_name)) { - printf("%s: Define {kernel/initrd/fdt}_name\n", __func__); - return -1; - } - - /* Get exact initrd_size */ - initrd_size = smh_len(initrd_name); - if (initrd_size == -1) { - printf("%s: Can't get file size for \'%s\'\n", __func__, - initrd_name); - return -1; - } - - /* Set initrd_end */ - initrd_base = simple_strtoul(initrd_addr_str, NULL, 16); - initrd_addr_r = (void *)initrd_base; - sprintf(initrd_end_str, "0x%lx", initrd_base + initrd_size - 1); - setenv("initrd_end", initrd_end_str); - - /* Load kernel to memory */ - fdt_addr_r = (void *)simple_strtoul(fdt_addr_str, NULL, 16); - kernel_addr_r = (void *)simple_strtoul(kernel_addr_str, NULL, 16); - - /* - * The kernel must be lower in memory than fdt and loading the - * kernel must not trample the fdt or vice versa. - */ - avail = fdt_addr_r - kernel_addr_r; - if (avail < 0) { - printf("%s: fdt must be after kernel\n", __func__); - return -1; - } - smh_load(kernel_name, kernel_addr_r, avail, 1); - - /* Load fdt to memory */ - smh_load(fdt_name, fdt_addr_r, 0x20000, 1); - - /* Load initrd to memory */ - smh_load(initrd_name, initrd_addr_r, initrd_size, 1); - -#endif /* CONFIG_SEMIHOSTING */ - return 0; -} -#endif /* CONFIG_BOARD_LATE_INIT */ - /* * Board specific ethernet initialization routine. */ diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index b807ef9a42..4289179ee6 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -8,6 +8,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/clk.h> #include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> @@ -15,6 +16,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> +#include <linux/mtd/nand.h> #include <atmel_lcdc.h> #include <atmel_mci.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -71,6 +73,84 @@ void at91sam9m10g45ek_nand_hw_init(void) } #endif +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ + /* + * On the at91sam9m10g45ek board, the chip wm9711 stays in the + * test mode, so it needs do some action to exit test mode. + */ + at91_periph_clk_enable(ATMEL_ID_PIODE); + at91_set_gpio_output(AT91_PIN_PD7, 0); + at91_set_gpio_output(AT91_PIN_PD8, 0); + at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); + at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); + +#ifdef CONFIG_SYS_USE_MMC + at91_mci_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + at91sam9m10g45ek_nand_hw_init(); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_DQMS_SHARED | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3); + + ddr2->rtr = 0x24b; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ + 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ + 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(0x4, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&mat->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; + writel(csa, &mat->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_CS6, &ddr2); +} +#endif + #ifdef CONFIG_CMD_USB static void at91sam9m10g45ek_usb_hw_init(void) { diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 9adc9920b4..4f46a03533 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -257,3 +257,76 @@ int dram_init(void) CONFIG_SYS_SDRAM_SIZE); return 0; } + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + at91_mci_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + at91sam9n12ek_nand_hw_init(); +#elif CONFIG_SYS_USE_SPIFLASH + at91_spi0_hw_init(1 << 4); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(0x4, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_CS1, &ddr2); +} +#endif diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 17a2a40b4b..114ac5c85a 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -293,3 +293,77 @@ int dram_init(void) CONFIG_SYS_SDRAM_SIZE); return 0; } + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> +#include <nand.h> + +void at91_spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + at91_mci_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + at91sam9x5ek_nand_hw_init(); +#elif CONFIG_SYS_USE_SPIFLASH + at91_spi0_hw_init(1 << 4); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_13 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); + + ddr2->rtr = 0x411; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(0x4, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_DBPU_OFF; + csa |= AT91_MATRIX_EBI_DBPD_OFF; + csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; + writel(csa, &matrix->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_CS1, &ddr2); +} +#endif diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index e7f225a155..7d447fe76b 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -24,6 +24,7 @@ #include <netdev.h> #include <nand.h> #include <spi.h> +#include <version.h> DECLARE_GLOBAL_DATA_PTR; @@ -179,6 +180,7 @@ void lcd_show_board_info(void) int i; char temp[32]; + lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("2014 ATMEL Corp\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 46e504131c..e9bbb4b1c8 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -24,6 +24,7 @@ #include <netdev.h> #include <nand.h> #include <spi.h> +#include <version.h> DECLARE_GLOBAL_DATA_PTR; @@ -174,6 +175,7 @@ void lcd_show_board_info(void) int i; char temp[32]; + lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("2014 ATMEL Corp\n"); lcd_printf("at91@atmel.com\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), diff --git a/board/birdland/bav335x/board.h b/board/birdland/bav335x/board.h index b598ce1e82..1ea681ec44 100644 --- a/board/birdland/bav335x/board.h +++ b/board/birdland/bav335x/board.h @@ -33,7 +33,7 @@ struct board_eeconfig { unsigned int magic; char name[HDR_NAME_LEN]; /* BAV3354 */ char version[4]; /* 0B20 - Rev.B2 */ - char serial[12]; + char serial[16]; char config[32]; char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; }; diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S index c1d09663d4..ec9fb883f5 100644 --- a/board/espt/lowlevel_init.S +++ b/board/espt/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index de8d09bf66..b1cae59890 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -13,8 +13,6 @@ SECTIONS .text : { arch/m68k/cpu/mcf532x/start.o (.text*) - arch/m68k/cpu/mcf532x/built-in.o (.text*) - arch/m68k/lib/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text*) diff --git a/board/htkw/mcx/MAINTAINERS b/board/htkw/mcx/MAINTAINERS index c5f88733d2..513d19daa7 100644 --- a/board/htkw/mcx/MAINTAINERS +++ b/board/htkw/mcx/MAINTAINERS @@ -1,5 +1,5 @@ MCX BOARD -M: Ilya Yanok <yanok@emcraft.com> +M: Anatolij Gustschin <agust@denx.de> S: Maintained F: board/htkw/mcx/ F: include/configs/mcx.h diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S index c286d0dfe1..9cb702f30f 100644 --- a/board/logicpd/imx27lite/lowlevel_init.S +++ b/board/logicpd/imx27lite/lowlevel_init.S @@ -10,7 +10,6 @@ #include <config.h> -#include <version.h> #include <asm/macro.h> #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index ee9b7a9d3e..c0d6cc8923 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -13,8 +13,6 @@ #include <config.h> -#include <version.h> - /* register definitions */ diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index db859f48ad..a62404fdc1 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -11,7 +11,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index c02306fb24..d61640df6c 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -10,7 +10,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 25480e481d..2d07001800 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,7 +20,7 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ - gpio_request(GPIO_PI3, NULL); + gpio_request(GPIO_PI3, "uart_en"); gpio_direction_output(GPIO_PI3, 0); } #endif diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 5427de5634..ca40cea9ad 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -93,19 +93,6 @@ static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - if (buf[i] != readb(&(alpr_ndfc->data))) - return i; - - return 0; -} -#endif - static int alpr_nand_dev_ready(struct mtd_info *mtd) { /* @@ -130,9 +117,6 @@ int board_nand_init(struct nand_chip *nand) nand->read_byte = alpr_nand_read_byte; nand->write_buf = alpr_nand_write_buf; nand->read_buf = alpr_nand_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = alpr_nand_verify_buf; -#endif nand->dev_ready = alpr_nand_dev_ready; return 0; diff --git a/board/raspberrypi/rpi/Kconfig b/board/raspberrypi/rpi/Kconfig deleted file mode 100644 index 6a538cfac5..0000000000 --- a/board/raspberrypi/rpi/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_RPI - -config SYS_BOARD - default "rpi" - -config SYS_VENDOR - default "raspberrypi" - -config SYS_SOC - default "bcm2835" - -config SYS_CONFIG_NAME - default "rpi" - -endif diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 50a699bb9e..96fe870645 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -165,6 +165,16 @@ static const struct { "bcm2835-rpi-a-plus.dtb", false, }, + [BCM2835_BOARD_REV_B_PLUS_13] = { + "Model B+", + "bcm2835-rpi-b-plus.dtb", + true, + }, + [BCM2835_BOARD_REV_CM_14] = { + "Compute Module", + "bcm2835-rpi-cm.dtb", + false, + }, #endif }; @@ -278,10 +288,17 @@ static void get_board_rev(void) * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282 * (a few posts down) + * + * For the RPi 1, bit 24 is the "warranty bit", so we mask off just the + * lower byte to use as the board rev: + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=98367&start=250 + * http://www.raspberrypi.org/forums/viewtopic.php?f=31&t=20594 */ rpi_board_rev = msg->get_board_rev.body.resp.rev; if (rpi_board_rev & 0x800000) rpi_board_rev = (rpi_board_rev >> 4) & 0xff; + else + rpi_board_rev &= 0xff; if (rpi_board_rev >= ARRAY_SIZE(models)) { printf("RPI: Board rev %u outside known range\n", rpi_board_rev); diff --git a/board/raspberrypi/rpi_2/Kconfig b/board/raspberrypi/rpi_2/Kconfig deleted file mode 100644 index 032184d5ad..0000000000 --- a/board/raspberrypi/rpi_2/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_RPI_2 - -config SYS_BOARD - default "rpi_2" - -config SYS_VENDOR - default "raspberrypi" - -config SYS_SOC - default "bcm2835" - -config SYS_CONFIG_NAME - default "rpi_2" - -endif diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index 63ea70aa37..322e17779e 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -11,7 +11,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index ead5310a4b..867ca51225 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S index e4c40c8616..ab604c7fef 100644 --- a/board/renesas/ecovec/lowlevel_init.S +++ b/board/renesas/ecovec/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> #include <configs/ecovec.h> diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S index 62668a76b9..c2fa5656a4 100644 --- a/board/renesas/r0p7734/lowlevel_init.S +++ b/board/renesas/r0p7734/lowlevel_init.S @@ -5,7 +5,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index f3392f097d..33f6e07826 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S index 471af1d967..b27fe29143 100644 --- a/board/renesas/r7780mp/lowlevel_init.S +++ b/board/renesas/r7780mp/lowlevel_init.S @@ -7,7 +7,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index c8494ccf38..ee472a42ba 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -5,7 +5,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/rsk7264/lowlevel_init.S b/board/renesas/rsk7264/lowlevel_init.S index 1a7d27d179..eae270377f 100644 --- a/board/renesas/rsk7264/lowlevel_init.S +++ b/board/renesas/rsk7264/lowlevel_init.S @@ -8,7 +8,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S index a2b174bbc1..120bc6b325 100644 --- a/board/renesas/rsk7269/lowlevel_init.S +++ b/board/renesas/rsk7269/lowlevel_init.S @@ -9,7 +9,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S index 5643a697eb..cc8b8c0aca 100644 --- a/board/renesas/sh7752evb/lowlevel_init.S +++ b/board/renesas/sh7752evb/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S index 21987a51e8..98551e1055 100644 --- a/board/renesas/sh7753evb/lowlevel_init.S +++ b/board/renesas/sh7753evb/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S index e4c5ea815e..6db26d9450 100644 --- a/board/renesas/sh7757lcr/lowlevel_init.S +++ b/board/renesas/sh7757lcr/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index e45fbbe9c7..e8e3d6fae3 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -9,7 +9,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 8b729ac392..4bda38cfad 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -4,7 +4,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index d52bc09f8d..fdb83e457a 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <asm/arch/power.h> diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S index 5de04f10e9..c3f41875de 100644 --- a/board/samsung/smdk2410/lowlevel_init.S +++ b/board/samsung/smdk2410/lowlevel_init.S @@ -13,8 +13,6 @@ #include <config.h> -#include <version.h> - /* some parameters for the board */ diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index 1423f83995..a26ea689f2 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -8,3 +8,9 @@ F: include/configs/smdk5420.h F: configs/smdk5420_defconfig F: include/configs/peach-pi.h F: configs/peach-pi_defconfig + +ODROID-XU3 BOARD +M: Przemyslaw Marczak <p.marczak@samsung.com> +S: Maintained +F: board/samsung/smdk5420/ +F: include/configs/odroid_xu3.h diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index 1aca9fabd9..82f607b24d 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -58,16 +58,6 @@ void exynos_lcd_power_on(void) mdelay(5); - /* TODO(ajaykumar.rs@samsung.com): Use device tree */ - gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#"); - gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */ - mdelay(10); - gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#"); - gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */ - gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd"); - gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ - gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE); - if (has_edp_bridge()) if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__); @@ -75,11 +65,6 @@ void exynos_lcd_power_on(void) void exynos_backlight_on(unsigned int onoff) { - /* For PWM */ - gpio_request(EXYNOS5420_GPIO_B20, "backlight_on"); - gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1)); - gpio_set_value(EXYNOS5420_GPIO_B20, 1); - #ifdef CONFIG_POWER_TPS65090 tps65090_fet_enable(1); #endif diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 65e6b7a73a..91e5357691 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -7,7 +7,6 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/cpu.h> #include <asm/arch/power.h> diff --git a/board/samsung/trats/setup.h b/board/samsung/trats/setup.h index 2f5ccb14c6..990e5e2dff 100644 --- a/board/samsung/trats/setup.h +++ b/board/samsung/trats/setup.h @@ -11,7 +11,6 @@ #define _TRATS_SETUP_H #include <config.h> -#include <version.h> #include <asm/arch/cpu.h> /* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */ diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S index 2475ae8efb..d5727248db 100644 --- a/board/scb9328/lowlevel_init.S +++ b/board/scb9328/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/imx-regs.h> .globl lowlevel_init diff --git a/board/shmin/lowlevel_init.S b/board/shmin/lowlevel_init.S index 35c0945196..53b3123849 100644 --- a/board/shmin/lowlevel_init.S +++ b/board/shmin/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> #include <asm/processor.h> #include <asm/macro.h> diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 73944780bf..15e6ea6944 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -18,9 +18,6 @@ static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); static u_char sc_nand_read_byte(struct mtd_info *mtd); static u16 sc_nand_read_word(struct mtd_info *mtd); static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); -#endif static int sc_nand_device_ready(struct mtd_info *mtdinfo); #define FPGA_NAND_CMD_MASK (0x7 << 28) @@ -102,25 +99,6 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) } } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/** - * sc_nand_verify_buf - Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - */ -static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - if (buf[i] != sc_nand_read_byte(mtd)); - return -EFAULT; - } - return 0; -} -#endif - /** * sc_nand_device_ready - Check the NAND device is ready for next command. * @mtd: MTD device structure @@ -178,9 +156,6 @@ int board_nand_init(struct nand_chip *nand) nand->read_word = sc_nand_read_word; nand->write_buf = sc_nand_write_buf; nand->read_buf = sc_nand_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = sc_nand_verify_buf; -#endif return 0; } diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 9d0eb91977..2fcab602db 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -132,6 +132,10 @@ endchoice endif +config SYS_CLK_FREQ + default 912000000 if MACH_SUN7I + default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I + config SYS_CONFIG_NAME default "sun4i" if MACH_SUN4I default "sun5i" if MACH_SUN5I diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index ef3c93711b..be4821360f 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -21,6 +21,7 @@ F: configs/A13-OLinuXinoM_defconfig F: configs/Auxtek-T004_defconfig F: configs/mk802_a10s_defconfig F: configs/r7-tv-dongle_defconfig +F: configs/UTOO_P66_defconfig F: include/configs/sun6i.h F: configs/CSQ_CS908_defconfig F: configs/Mele_M9_defconfig diff --git a/board/sunxi/board.c b/board/sunxi/board.c index e1891d198e..808bf82b65 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -215,7 +215,7 @@ void sunxi_board_init(void) * assured it's being powered with suitable core voltage */ if (!power_failed) - clock_set_pll1(CONFIG_CLK_FULL_SPEED); + clock_set_pll1(CONFIG_SYS_CLK_FREQ); else printf("Failed to set core voltage! Can't set CPU frequency\n"); } diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c index d1271ffcca..8c16410944 100644 --- a/board/synopsys/axs101/axs101.c +++ b/board/synopsys/axs101/axs101.c @@ -9,6 +9,7 @@ #include <malloc.h> #include <netdev.h> #include <phy.h> +#include "axs10x.h" DECLARE_GLOBAL_DATA_PTR; @@ -27,9 +28,9 @@ int board_mmc_init(bd_t *bis) host->ioaddr = (void *)ARC_DWMMC_BASE; host->buswidth = 4; host->dev_index = 0; - host->bus_hz = 25000000; + host->bus_hz = 50000000; - add_dwmci(host, 52000000, 400000); + add_dwmci(host, host->bus_hz, 400000); return 0; } @@ -42,3 +43,16 @@ int board_eth_init(bd_t *bis) return 0; } + + +#define AXS_MB_CREG 0xE0011000 + +int board_early_init_f(void) +{ + if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28)) + gd->board_type = AXS_MB_V3; + else + gd->board_type = AXS_MB_V2; + + return 0; +} diff --git a/board/synopsys/axs101/axs10x.h b/board/synopsys/axs101/axs10x.h new file mode 100644 index 0000000000..8e8c41f865 --- /dev/null +++ b/board/synopsys/axs101/axs10x.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_SYNOPSYS_AXS10X_H +#define _BOARD_SYNOPSYS_AXS10X_H + +enum { + AXS_MB_V2, + AXS_MB_V3 +}; + +#endif /* _BOARD_SYNOPSYS_AXS10X_H */ + diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c index ff35286c6e..4be52e22c0 100644 --- a/board/synopsys/axs101/nand.c +++ b/board/synopsys/axs101/nand.c @@ -9,6 +9,9 @@ #include <malloc.h> #include <nand.h> #include <asm/io.h> +#include "axs10x.h" + +DECLARE_GLOBAL_DATA_PTR; #define BUS_WIDTH 8 /* AXI data bus width in bytes */ @@ -232,5 +235,9 @@ int board_nand_init(struct nand_chip *nand) nand->write_buf = axs101_nand_write_buf; nand->read_buf = axs101_nand_read_buf; + /* MBv3 has NAND IC with 16-bit data bus */ + if (gd->board_type == AXS_MB_V3) + nand->options |= NAND_BUSWIDTH_16; + return 0; } diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index 722f9d57c4..7cb006f99c 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -47,10 +47,4 @@ config DM_GPIO config DM_SERIAL default y if DM -config SYS_MALLOC_F - default y if DM - -config SYS_MALLOC_F_LEN - default 0x400 if DM - endif diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.h b/board/toradex/colibri_t20-common/colibri_t20-common.h deleted file mode 100644 index 1fe53f6073..0000000000 --- a/board/toradex/colibri_t20-common/colibri_t20-common.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (C) 2012 Lucas Stach - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void colibri_t20_common_pin_mux_usb(void); diff --git a/board/toradex/colibri_t20_iris/Kconfig b/board/toradex/colibri_t20/Kconfig index 4bf727809e..7f373b2d26 100644 --- a/board/toradex/colibri_t20_iris/Kconfig +++ b/board/toradex/colibri_t20/Kconfig @@ -1,12 +1,12 @@ -if TARGET_COLIBRI_T20_IRIS +if TARGET_COLIBRI_T20 config SYS_BOARD - default "colibri_t20_iris" + default "colibri_t20" config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "colibri_t20_iris" + default "colibri_t20" endif diff --git a/board/toradex/colibri_t20/MAINTAINERS b/board/toradex/colibri_t20/MAINTAINERS new file mode 100644 index 0000000000..b251c000fe --- /dev/null +++ b/board/toradex/colibri_t20/MAINTAINERS @@ -0,0 +1,7 @@ +COLIBRI_T20 +M: Lucas Stach <dev@lynxeye.de> +S: Maintained +F: board/toradex/colibri_t20/ +F: include/configs/colibri_t20.h +F: configs/colibri_t20_defconfig +F: arch/arm/dts/tegra20-colibri.dtb diff --git a/board/toradex/colibri_t20/Makefile b/board/toradex/colibri_t20/Makefile new file mode 100644 index 0000000000..86f78d9d9d --- /dev/null +++ b/board/toradex/colibri_t20/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2012 Lucas Stach +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(srctree)/board/nvidia/common/common.mk + +obj-y += colibri_t20.o diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20/colibri_t20.c index 58a9916f0a..8ae9ccf538 100644 --- a/board/toradex/colibri_t20-common/colibri_t20-common.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -9,27 +9,57 @@ #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/board.h> +#include <asm/gpio.h> -#include "colibri_t20-common.h" +#ifdef CONFIG_TEGRA_MMC +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + pinmux_tristate_disable(PMUX_PINGRP_GMB); +} +#endif + +#ifdef CONFIG_TEGRA_NAND +void pin_mux_nand(void) +{ + funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); + + /* + * configure pingroup ATC to something unrelated to + * avoid ATC overriding KBC + */ + pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); +} +#endif #ifdef CONFIG_USB_EHCI_TEGRA -void colibri_t20_common_pin_mux_usb(void) +void pin_mux_usb(void) { /* module internal USB bus to connect ethernet chipset */ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); + /* ULPI reference clock output */ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); pinmux_tristate_disable(PMUX_PINGRP_CDEV2); + /* PHY reset GPIO */ pinmux_tristate_disable(PMUX_PINGRP_UAC); + /* VBus GPIO */ pinmux_tristate_disable(PMUX_PINGRP_DTE); -} -#endif -#ifdef CONFIG_TEGRA_NAND -void pin_mux_nand(void) -{ - funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); + /* Reset ASIX using LAN_RESET */ + gpio_request(GPIO_PV4, "LAN_RESET"); + gpio_direction_output(GPIO_PV4, 0); + pinmux_tristate_disable(PMUX_PINGRP_GPV); + udelay(5); + gpio_set_value(GPIO_PV4, 1); + + /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ + pinmux_tristate_disable(PMUX_PINGRP_SPIG); } #endif diff --git a/board/toradex/colibri_t20_iris/MAINTAINERS b/board/toradex/colibri_t20_iris/MAINTAINERS deleted file mode 100644 index c68955bfa9..0000000000 --- a/board/toradex/colibri_t20_iris/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -COLIBRI_T20_IRIS BOARD -M: Lucas Stach <dev@lynxeye.de> -S: Maintained -F: board/toradex/colibri_t20_iris/ -F: include/configs/colibri_t20_iris.h -F: configs/colibri_t20_iris_defconfig diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile deleted file mode 100644 index ebeac70ea1..0000000000 --- a/board/toradex/colibri_t20_iris/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2012 Lucas Stach -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ../../nvidia/common/board.o -obj-y += ../colibri_t20-common/colibri_t20-common.o -obj-y += colibri_t20_iris.o diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c deleted file mode 100644 index 49c74f34f1..0000000000 --- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2012 Lucas Stach - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> -#include <asm/arch-tegra/board.h> - -#include "../colibri_t20-common/colibri_t20-common.h" - -#ifdef CONFIG_USB_EHCI_TEGRA -void pin_mux_usb(void) -{ - colibri_t20_common_pin_mux_usb(); - - /* USB 1 aka Tegra USB port 3 VBus*/ - pinmux_tristate_disable(PMUX_PINGRP_SPIG); -} -#endif - -#ifdef CONFIG_TEGRA_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); - pinmux_tristate_disable(PMUX_PINGRP_GMB); -} -#endif diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig new file mode 100644 index 0000000000..74f004f53c --- /dev/null +++ b/board/work-microwave/work_92105/Kconfig @@ -0,0 +1,15 @@ +if TARGET_WORK_92105 + +config SYS_BOARD + default "work_92105" + +config SYS_VENDOR + default "work-microwave" + +config SYS_SOC + default "lpc32xx" + +config SYS_CONFIG_NAME + default "work_92105" + +endif diff --git a/board/work-microwave/work_92105/MAINTAINERS b/board/work-microwave/work_92105/MAINTAINERS new file mode 100644 index 0000000000..29a92c5ffe --- /dev/null +++ b/board/work-microwave/work_92105/MAINTAINERS @@ -0,0 +1,6 @@ +WORK_92105 BOARD +M: Albert ARIBAUD <albert.aribaud@3adev.fr> +S: Maintained +F: board/work-microwave/work_92105/ +F: include/configs/work_92105.h +F: configs/work_92105_defconfig diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile new file mode 100644 index 0000000000..ba31c8e4f4 --- /dev/null +++ b/board/work-microwave/work_92105/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2014 DENX Software Engineering GmbH +# Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := work_92105.o work_92105_display.o + +obj-$(CONFIG_SPL_BUILD) += work_92105_spl.o diff --git a/board/work-microwave/work_92105/README b/board/work-microwave/work_92105/README new file mode 100644 index 0000000000..3c256e0b2c --- /dev/null +++ b/board/work-microwave/work_92105/README @@ -0,0 +1,91 @@ +Work_92105 from Work Microwave is an LPC3250- based board with the +following features: + + - 64MB SDR DRAM + - 1 GB SLC NAND, managed through MLC controller. + - Ethernet + - Ethernet + PHY SMSC8710 + - I2C: + - EEPROM (24M01-compatible) + - RTC (DS1374-compatible) + - Temperature sensor (DS620) + - DACs (2 x MAX518) + - SPI (through SSP interface) + - Port expander MAX6957 + - LCD display (HD44780-compatible), controlled + through the port expander and DACs + +Standard SPL and U-Boot binaries +-------------------------------- + +The default 'make' (or the 'make all') command will produce the +following files: + +1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0. + This file can be loaded in SRAM through a JTAG + debugger or through the LPC32XX Service Boot + mechanism. + +2. u-boot.bin The raw U-Boot image, which can be loaded in + DDR through a JTAG debugger (for instance by + breaking SPL after DDR init), or by a running + U-Boot through e.g. 'loady' or 'tftp' and then + executed with 'go'. + +3. u-boot.img A U-Boot image with a mkimage header prepended. + SPL assumes (even when loaded through JTAG or + Service Boot) that such an image will be found + at offset 0x00040000 in NAND. + +NAND cold-boot binaries +----------------------- + +The board can boot entirely from power-on with only SPL and U-Boot in +NAND. The LPC32XX-specific 'make lpc32xx-full.bin' command will produce +(in addition to spl/u-boot-spl.bin and u-boot.img if they were not made +already) the following files: + +4. lpc32xx-spl.img spl/u-boot-spl.bin, with a LPC32XX boot header + prepended. This header is required for the ROM + code to load SPL into SRAM and branch into it. + The content of this file is expected to reside + in NAND at addresses 0x00000000 and 0x00020000 + (two copies). + +5. lpc32xx-boot-0.bin lpc32xx-spl.img, padded with 0xFF bytes to a + size of 0x20000 bytes. This file covers exactly + the reserved area for the first bootloader copy + in NAND. + +6. lpc32xx-boot-1.bin Same as lpc32xx-boot-0.bin. This is intended to + be used as the second bootloader copy. + +7. lpc32xx-full.bin lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and + u-boot.img concatenated. This file represents + the content of whole bootloader as present in + NAND at offset 00x00000000. + +Flashing instructions +--------------------- + +The following assumes a working U-Boot on the target, with the ability +to load files into DDR. + +To update the whole bootloader: + + nand erase 0x00000000 0x80000 + (load lpc32xx-full.bin at location $loadaddr) + nand write $loadaddr 0x00000000 $filesize + +To update SPL only (note the double nand write) : + + nand erase 0x00000000 0x40000 + (load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr) + nand write $loadaddr 0x00000000 $filesize + nand write $loadaddr 0x00020000 $filesize + +To update U-Boot only: + + nand erase 0x00040000 0x40000 + (load u-boot.img at location $loadaddr) + nand write $loadaddr 0x00040000 $filesize diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c new file mode 100644 index 0000000000..f782284d60 --- /dev/null +++ b/board/work-microwave/work_92105/work_92105.c @@ -0,0 +1,77 @@ +/* + * WORK Microwave work_92105 board support + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/emc.h> +#include <asm/arch/wdt.h> +#include <asm/gpio.h> +#include <spl.h> +#include "work_92105_display.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; + +void reset_periph(void) +{ + setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); + writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); + udelay(150); + writel(0, &wdt->mctrl); + clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); +} + +int board_early_init_f(void) +{ + /* initialize serial port for console */ + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + /* enable I2C, SSP, MAC, NAND */ + lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ + lpc32xx_ssp_init(); + lpc32xx_mac_init(); + lpc32xx_mlc_nand_init(); + /* Display must wait until after relocation and devices init */ + return 0; +} + +#define GPO_19 115 + +int board_early_init_r(void) +{ + /* Set NAND !WP to 1 through GPO_19 */ + gpio_request(GPO_19, "NAND_nWP"); + gpio_direction_output(GPO_19, 1); + + /* initialize display */ + work_92105_display_init(); + + return 0; +} + +int board_init(void) +{ + reset_periph(); + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c new file mode 100644 index 0000000000..c8b10131f9 --- /dev/null +++ b/board/work-microwave/work_92105/work_92105_display.c @@ -0,0 +1,349 @@ +/* + * work_92105 display support + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * The work_92105 display is a HD44780-compatible module + * controlled through a MAX6957AAX SPI port expander, two + * MAX518 I2C DACs and native LPC32xx GPO 15. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> +#include <asm/arch/emc.h> +#include <asm/gpio.h> +#include <spi.h> +#include <i2c.h> +#include <version.h> +#include <vsprintf.h> + +/* + * GPO 15 in port 3 is gpio 3*32+15 = 111 + */ + +#define GPO_15 111 + +/** + * MAX6957AAX registers that we will be using + */ + +#define MAX6957_CONF 0x04 + +#define MAX6957_CONF_08_11 0x0A +#define MAX6957_CONF_12_15 0x0B +#define MAX6957_CONF_16_19 0x0C + +/** + * Individual gpio ports (one per gpio) to HD44780 + */ + +#define MAX6957AAX_HD44780_RS 0x29 +#define MAX6957AAX_HD44780_R_W 0x2A +#define MAX6957AAX_HD44780_EN 0x2B +#define MAX6957AAX_HD44780_DATA 0x4C + +/** + * Display controller instructions + */ + +/* Function set: eight bits, two lines, 8-dot font */ +#define HD44780_FUNCTION_SET 0x38 + +/* Display ON / OFF: turn display on */ +#define HD44780_DISPLAY_ON_OFF_CONTROL 0x0C + +/* Entry mode: increment */ +#define HD44780_ENTRY_MODE_SET 0x06 + +/* Clear */ +#define HD44780_CLEAR_DISPLAY 0x01 + +/* Set DDRAM addr (to be ORed with exact address) */ +#define HD44780_SET_DDRAM_ADDR 0x80 + +/* Set CGRAM addr (to be ORed with exact address) */ +#define HD44780_SET_CGRAM_ADDR 0x40 + +/** + * Default value for contrats + */ + +#define CONTRAST_DEFAULT 25 + +/** + * Define slave as a module-wide local to save passing it around, + * plus we will need it after init for the "hd44780" command. + */ + +static struct spi_slave *slave; + +/* + * Write a value into a MAX6957AAX register. + */ + +static void max6957aax_write(uint8_t reg, uint8_t value) +{ + uint8_t dout[2]; + + dout[0] = reg; + dout[1] = value; + gpio_set_value(GPO_15, 0); + /* do SPI read/write (passing din==dout is OK) */ + spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END); + gpio_set_value(GPO_15, 1); +} + +/* + * Read a value from a MAX6957AAX register. + * + * According to the MAX6957AAX datasheet, we should release the chip + * select halfway through the read sequence, when the actual register + * value is read; but the WORK_92105 hardware prevents the MAX6957AAX + * SPI OUT from reaching the LPC32XX SIP MISO if chip is not selected. + * so let's release the CS an hold it again while reading the result. + */ + +static uint8_t max6957aax_read(uint8_t reg) +{ + uint8_t dout[2], din[2]; + + /* send read command */ + dout[0] = reg | 0x80; /* set bit 7 to indicate read */ + dout[1] = 0; + gpio_set_value(GPO_15, 0); + /* do SPI read/write (passing din==dout is OK) */ + spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END); + /* latch read command */ + gpio_set_value(GPO_15, 1); + /* read register -- din = noop on xmit, din[1] = reg on recv */ + din[0] = 0; + din[1] = 0; + gpio_set_value(GPO_15, 0); + /* do SPI read/write (passing din==dout is OK) */ + spi_xfer(slave, 16, din, din, SPI_XFER_BEGIN | SPI_XFER_END); + /* end of read. */ + gpio_set_value(GPO_15, 1); + return din[1]; +} + +static void hd44780_instruction(unsigned long instruction) +{ + max6957aax_write(MAX6957AAX_HD44780_RS, 0); + max6957aax_write(MAX6957AAX_HD44780_R_W, 0); + max6957aax_write(MAX6957AAX_HD44780_EN, 1); + max6957aax_write(MAX6957AAX_HD44780_DATA, instruction); + max6957aax_write(MAX6957AAX_HD44780_EN, 0); + /* HD44780 takes 37 us for most instructions, 1520 for clear */ + if (instruction == HD44780_CLEAR_DISPLAY) + udelay(2000); + else + udelay(100); +} + +static void hd44780_write_char(char c) +{ + max6957aax_write(MAX6957AAX_HD44780_RS, 1); + max6957aax_write(MAX6957AAX_HD44780_R_W, 0); + max6957aax_write(MAX6957AAX_HD44780_EN, 1); + max6957aax_write(MAX6957AAX_HD44780_DATA, c); + max6957aax_write(MAX6957AAX_HD44780_EN, 0); + /* HD44780 takes 37 us to write to DDRAM or CGRAM */ + udelay(100); +} + +static void hd44780_write_str(char *s) +{ + max6957aax_write(MAX6957AAX_HD44780_RS, 1); + max6957aax_write(MAX6957AAX_HD44780_R_W, 0); + while (*s) { + max6957aax_write(MAX6957AAX_HD44780_EN, 1); + max6957aax_write(MAX6957AAX_HD44780_DATA, *s); + max6957aax_write(MAX6957AAX_HD44780_EN, 0); + s++; + /* HD44780 takes 37 us to write to DDRAM or CGRAM */ + udelay(100); + } +} + +/* + * Existing user code might expect these custom characters to be + * recognized and displayed on the LCD + */ + +static u8 char_gen_chars[] = { + /* #8, empty rectangle */ + 0x1F, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x1F, + /* #9, filled right arrow */ + 0x10, 0x18, 0x1C, 0x1E, 0x1C, 0x18, 0x10, 0x00, + /* #10, filled left arrow */ + 0x01, 0x03, 0x07, 0x0F, 0x07, 0x03, 0x01, 0x00, + /* #11, up and down arrow */ + 0x04, 0x0E, 0x1F, 0x00, 0x00, 0x1F, 0x0E, 0x04, + /* #12, plus/minus */ + 0x04, 0x04, 0x1F, 0x04, 0x04, 0x00, 0x1F, 0x00, + /* #13, fat exclamation mark */ + 0x06, 0x06, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00, + /* #14, empty square */ + 0x00, 0x1F, 0x11, 0x11, 0x11, 0x1F, 0x00, 0x00, + /* #15, struck out square */ + 0x00, 0x1F, 0x19, 0x15, 0x13, 0x1F, 0x00, 0x00, +}; + +static void hd44780_init_char_gen(void) +{ + int i; + + hd44780_instruction(HD44780_SET_CGRAM_ADDR); + + for (i = 0; i < sizeof(char_gen_chars); i++) + hd44780_write_char(char_gen_chars[i]); + + hd44780_instruction(HD44780_SET_DDRAM_ADDR); +} + +void work_92105_display_init(void) +{ + int claim_err; + char *display_contrast_str; + uint8_t display_contrast = CONTRAST_DEFAULT; + uint8_t enable_backlight = 0x96; + + slave = spi_setup_slave(0, 0, 500000, 0); + + if (!slave) { + printf("Failed to set up SPI slave\n"); + return; + } + + claim_err = spi_claim_bus(slave); + + if (claim_err) + debug("Failed to claim SPI bus: %d\n", claim_err); + + /* enable backlight */ + i2c_write(0x2c, 0x01, 1, &enable_backlight, 1); + + /* set display contrast */ + display_contrast_str = getenv("fwopt_dispcontrast"); + if (display_contrast_str) + display_contrast = simple_strtoul(display_contrast_str, + NULL, 10); + i2c_write(0x2c, 0x00, 1, &display_contrast, 1); + + /* request GPO_15 as an output initially set to 1 */ + gpio_request(GPO_15, "MAX6957_nCS"); + gpio_direction_output(GPO_15, 1); + + /* enable MAX6957 portexpander */ + max6957aax_write(MAX6957_CONF, 0x01); + /* configure pin 8 as input, pins 9..19 as outputs */ + max6957aax_write(MAX6957_CONF_08_11, 0x56); + max6957aax_write(MAX6957_CONF_12_15, 0x55); + max6957aax_write(MAX6957_CONF_16_19, 0x55); + + /* initialize HD44780 */ + max6957aax_write(MAX6957AAX_HD44780_EN, 0); + hd44780_instruction(HD44780_FUNCTION_SET); + hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL); + hd44780_instruction(HD44780_ENTRY_MODE_SET); + + /* write custom character glyphs */ + hd44780_init_char_gen(); + + /* Show U-Boot version, date and time as a sign-of-life */ + hd44780_instruction(HD44780_CLEAR_DISPLAY); + hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0); + hd44780_write_str(U_BOOT_VERSION); + hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64); + hd44780_write_str(U_BOOT_DATE); + hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20); + hd44780_write_str(U_BOOT_TIME); +} + +#ifdef CONFIG_CMD_MAX6957 + +static int do_max6957aax(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int reg, val; + + if (argc != 3) + return CMD_RET_USAGE; + switch (argv[1][0]) { + case 'r': + case 'R': + reg = simple_strtoul(argv[2], NULL, 0); + val = max6957aax_read(reg); + printf("MAX6957 reg 0x%02x read 0x%02x\n", reg, val); + return 0; + default: + reg = simple_strtoul(argv[1], NULL, 0); + val = simple_strtoul(argv[2], NULL, 0); + max6957aax_write(reg, val); + printf("MAX6957 reg 0x%02x wrote 0x%02x\n", reg, val); + return 0; + } + return 1; +} + +#ifdef CONFIG_SYS_LONGHELP +static char max6957aax_help_text[] = + "max6957aax - write or read display register:\n" + "\tmax6957aax R|r reg - read display register;\n" + "\tmax6957aax reg val - write display register."; +#endif + +U_BOOT_CMD( + max6957aax, 6, 1, do_max6957aax, + "SPI MAX6957 display write/read", + max6957aax_help_text +); +#endif /* CONFIG_CMD_MAX6957 */ + +#ifdef CONFIG_CMD_HD44760 + +/* + * We need the HUSH parser because we need string arguments, and + * only HUSH can understand them. + */ + +#if !defined(CONFIG_SYS_HUSH_PARSER) +#error CONFIG_CMD_HD44760 requires CONFIG_SYS_HUSH_PARSER +#endif + +static int do_hd44780(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + char *cmd; + + if (argc != 3) + return CMD_RET_USAGE; + + cmd = argv[1]; + + if (strcasecmp(cmd, "cmd") == 0) + hd44780_instruction(simple_strtol(argv[2], NULL, 0)); + else if (strcasecmp(cmd, "data") == 0) + hd44780_write_char(simple_strtol(argv[2], NULL, 0)); + else if (strcasecmp(cmd, "str") == 0) + hd44780_write_str(argv[2]); + return 0; +} + +#ifdef CONFIG_SYS_LONGHELP +static char hd44780_help_text[] = + "hd44780 - control LCD driver:\n" + "\thd44780 cmd <val> - send command <val> to driver;\n" + "\thd44780 data <val> - send data <val> to driver;\n" + "\thd44780 str \"<text>\" - send \"<text>\" to driver."; +#endif + +U_BOOT_CMD( + hd44780, 6, 1, do_hd44780, + "HD44780 LCD driver control", + hd44780_help_text +); +#endif /* CONFIG_CMD_HD44780 */ diff --git a/board/work-microwave/work_92105/work_92105_display.h b/board/work-microwave/work_92105/work_92105_display.h new file mode 100644 index 0000000000..dd6e768eaf --- /dev/null +++ b/board/work-microwave/work_92105/work_92105_display.h @@ -0,0 +1,14 @@ +/* + * work_92105 display support interface + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * The work_92105 display is a HD44780-compatible module + * controlled through a MAX6957AAX SPI port expander, two + * MAX518 I2C DACs and native LPC32xx GPO 15. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void work_92105_display_init(void); diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c new file mode 100644 index 0000000000..282a6dd3a7 --- /dev/null +++ b/board/work-microwave/work_92105/work_92105_spl.c @@ -0,0 +1,85 @@ +/* + * WORK Microwave work_92105 board support + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> +#include <asm/arch/emc.h> +#include <asm/gpio.h> +#include <spl.h> +#include "work_92105_display.h" + +struct emc_dram_settings dram_64mb = { + .cmddelay = 0x0001C000, + .config0 = 0x00005682, + .rascas0 = 0x00000302, + .rdconfig = 0x00000011, + .trp = 52631578, + .tras = 20833333, + .tsrex = 12500000, + .twr = 66666666, + .trc = 13888888, + .trfc = 10256410, + .txsr = 12500000, + .trrd = 1, + .tmrd = 1, + .tcdlr = 0, + .refresh = 128000, + .mode = 0x00018000, + .emode = 0x02000000 +}; + +const struct emc_dram_settings dram_128mb = { + .cmddelay = 0x0001C000, + .config0 = 0x00005882, + .rascas0 = 0x00000302, + .rdconfig = 0x00000011, + .trp = 52631578, + .tras = 22222222, + .tsrex = 8333333, + .twr = 66666666, + .trc = 14814814, + .trfc = 10256410, + .txsr = 8333333, + .trrd = 1, + .tmrd = 1, + .tcdlr = 0, + .refresh = 128000, + .mode = 0x00030000, + .emode = 0x02000000 +}; + +void spl_board_init(void) +{ + /* initialize serial port for console */ + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + /* initialize console */ + preloader_console_init(); + /* init DDR and NAND to chainload U-Boot */ + ddr_init(&dram_128mb); + /* + * If this is actually a 64MB module, then the highest column + * bit in any address will be ignored, and thus address 0x80000000 + * should be mirrored at address 0x80000800. Test this. + */ + writel(0x31415926, 0x80000000); /* write Pi at 0x80000000 */ + writel(0x16180339, 0x80000800); /* write Phi at 0x80000800 */ + if (readl(0x80000000) == 0x16180339) /* check 0x80000000 */ { + /* actually 64MB mirrored: reconfigure controller */ + ddr_init(&dram_64mb); + } + /* initialize NAND controller to load U-Boot from NAND */ + lpc32xx_mlc_nand_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NAND; +} diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS index 382e921e70..e0dc4fed48 100644 --- a/board/xilinx/zynq/MAINTAINERS +++ b/board/xilinx/zynq/MAINTAINERS @@ -1,6 +1,5 @@ ZYNQ BOARD M: Michal Simek <monstr@monstr.eu> -M: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> S: Maintained F: board/xilinx/zynq/ F: include/configs/zynq*.h diff --git a/common/Kconfig b/common/Kconfig index e662774304..4cde4b0048 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -193,6 +193,12 @@ config CMD_FLASH erase - FLASH memory protect - enable or disable FLASH write protection +config CMD_ARMFLASH + depends on FLASH_CFI_DRIVER + bool "armflash" + help + ARM Ltd reference designs flash partition access + config CMD_NAND bool "nand" help diff --git a/common/Makefile b/common/Makefile index 7216a13922..252fbf194b 100644 --- a/common/Makefile +++ b/common/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o # command obj-$(CONFIG_CMD_AES) += cmd_aes.o obj-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o +obj-$(CONFIG_CMD_ARMFLASH) += cmd_armflash.o obj-$(CONFIG_SOURCE) += cmd_source.o obj-$(CONFIG_CMD_SOURCE) += cmd_source.o obj-$(CONFIG_CMD_BDI) += cmd_bdinfo.o diff --git a/common/board_f.c b/common/board_f.c index 55ede07537..cb956b853c 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -47,7 +47,7 @@ #include <asm/errno.h> #include <asm/io.h> #include <asm/sections.h> -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARC) #include <asm/init_helpers.h> #include <asm/relocate.h> #endif @@ -494,7 +494,7 @@ static int reserve_trace(void) #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ - !defined(CONFIG_BLACKFIN) + !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) static int reserve_video(void) { /* reserve memory for video display (always full pages) */ @@ -761,7 +761,7 @@ static int jump_to_copy(void) * similarly for all archs. When we do generic relocation, hopefully * we can make all archs enable the dcache prior to relocation. */ -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARC) /* * SDRAM and console are now initialised. The final stack can now * be setup in SDRAM. Code execution will continue in Flash, but @@ -968,7 +968,7 @@ static init_fnc_t init_sequence_f[] = { /* TODO: Why the dependency on CONFIG_8xx? */ #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ - !defined(CONFIG_BLACKFIN) + !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) reserve_video, #endif #if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_NIOS2) @@ -997,7 +997,7 @@ static init_fnc_t init_sequence_f[] = { INIT_FUNC_WATCHDOG_RESET reloc_fdt, setup_reloc, -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARC) copy_uboot_to_ram, clear_bss, do_elf_reloc_fixups, @@ -1041,7 +1041,7 @@ void board_init_f(ulong boot_flags) #endif } -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) || defined(CONFIG_ARC) /* * For now this code is only used on x86. * @@ -1080,7 +1080,9 @@ void board_init_f_r(void) /* NOTREACHED - board_init_r() does not return */ hang(); } -#else +#endif /* CONFIG_X86 */ + +#ifndef CONFIG_X86 ulong board_init_f_mem(ulong top) { /* Leave space for the stack we are running with now */ @@ -1098,4 +1100,4 @@ ulong board_init_f_mem(ulong top) return top; } -#endif /* CONFIG_X86 */ +#endif /* !CONFIG_X86 */ diff --git a/common/cmd_armflash.c b/common/cmd_armflash.c new file mode 100644 index 0000000000..1db92b0599 --- /dev/null +++ b/common/cmd_armflash.c @@ -0,0 +1,278 @@ +/* + * (C) Copyright 2015 + * Linus Walleij, Linaro + * + * Support for ARM Flash Partitions + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#define MAX_REGIONS 4 +#define MAX_IMAGES 32 + +struct afs_region { + u32 load_address; + u32 size; + u32 offset; +}; + +struct afs_image { + flash_info_t *flinfo; + const char *name; + u32 version; + u32 entrypoint; + u32 attributes; + u32 region_count; + struct afs_region regions[MAX_REGIONS]; + ulong flash_mem_start; + ulong flash_mem_end; +}; + +static struct afs_image afs_images[MAX_IMAGES]; +static int num_afs_images; + +static u32 compute_crc(ulong start, u32 len) +{ + u32 sum = 0; + int i; + + if (len % 4 != 0) { + printf("bad checksumming\n"); + return 0; + } + + for (i = 0; i < len; i += 4) { + u32 val; + + val = readl((void *)start + i); + if (val > ~sum) + sum++; + sum += val; + } + return ~sum; +} + +static void parse_bank(ulong bank) +{ + int i; + ulong flstart, flend; + flash_info_t *info; + + info = &flash_info[bank]; + if (info->flash_id != FLASH_MAN_CFI) { + printf("Bank %lu: missing or unknown FLASH type\n", bank); + return; + } + if (!info->sector_count) { + printf("Bank %lu: no FLASH sectors\n", bank); + return; + } + + flstart = info->start[0]; + flend = flstart + info->size; + + for (i = 0; i < info->sector_count; ++i) { + ulong secend; + u32 foot1, foot2; + + if (ctrlc()) + break; + + if (i == info->sector_count-1) + secend = flend; + else + secend = info->start[i+1]; + + /* Check for v1 header */ + foot1 = readl((void *)secend - 0x0c); + if (foot1 == 0xA0FFFF9FU) { + struct afs_image *afi = &afs_images[num_afs_images]; + ulong imginfo; + + afi->flinfo = info; + afi->version = 1; + afi->flash_mem_start = readl((void *)secend - 0x10); + afi->flash_mem_end = readl((void *)secend - 0x14); + afi->attributes = readl((void *)secend - 0x08); + /* Adjust to even address */ + imginfo = afi->flash_mem_end + afi->flash_mem_end % 4; + /* Record as a single region */ + afi->region_count = 1; + afi->regions[0].offset = readl((void *)imginfo + 0x04); + afi->regions[0].load_address = + readl((void *)imginfo + 0x08); + afi->regions[0].size = readl((void *)imginfo + 0x0C); + afi->entrypoint = readl((void *)imginfo + 0x10); + afi->name = (const char *)imginfo + 0x14; + num_afs_images++; + } + + /* Check for v2 header */ + foot1 = readl((void *)secend - 0x04); + foot2 = readl((void *)secend - 0x08); + /* This makes up the string "HSLFTOOF" flash footer */ + if (foot1 == 0x464F4F54U && foot2 == 0x464C5348U) { + struct afs_image *afi = &afs_images[num_afs_images]; + ulong imginfo; + u32 block_start, block_end; + int j; + + afi->flinfo = info; + afi->version = readl((void *)secend - 0x0c); + imginfo = secend - 0x30 - readl((void *)secend - 0x10); + afi->name = (const char *)secend - 0x30; + + afi->entrypoint = readl((void *)imginfo+0x08); + afi->attributes = readl((void *)imginfo+0x0c); + afi->region_count = readl((void *)imginfo+0x10); + block_start = readl((void *)imginfo+0x54); + block_end = readl((void *)imginfo+0x58); + afi->flash_mem_start = afi->flinfo->start[block_start]; + afi->flash_mem_end = afi->flinfo->start[block_end]; + + /* + * Check footer CRC, the algorithm saves the inverse + * checksum as part of the summed words, and thus + * the result should be zero. + */ + if (compute_crc(imginfo + 8, 0x88) != 0) { + printf("BAD CRC on ARM image info\n"); + printf("(continuing anyway)\n"); + } + + /* Parse regions */ + for (j = 0; j < afi->region_count; j++) { + afi->regions[j].load_address = + readl((void *)imginfo+0x14 + j*0x10); + afi->regions[j].size = + readl((void *)imginfo+0x18 + j*0x10); + afi->regions[j].offset = + readl((void *)imginfo+0x1c + j*0x10); + /* + * At offset 0x20 + j*0x10 there is a region + * checksum which seems to be the running + * sum + 3, however since we anyway checksum + * the entire footer this is skipped over for + * checking here. + */ + } + num_afs_images++; + } + } +} + +static void parse_flash(void) +{ + ulong bank; + + /* We have already parsed the images in flash */ + if (num_afs_images > 0) + return; + for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) + parse_bank(bank); +} + +static void load_image(const char * const name, const ulong address) +{ + struct afs_image *afi = NULL; + int i; + + parse_flash(); + for (i = 0; i < num_afs_images; i++) { + struct afs_image *tmp = &afs_images[i]; + + if (!strcmp(tmp->name, name)) { + afi = tmp; + break; + } + } + if (!afi) { + printf("image \"%s\" not found in flash\n", name); + return; + } + + for (i = 0; i < afi->region_count; i++) { + ulong from, to; + + from = afi->flash_mem_start + afi->regions[i].offset; + if (address) { + to = address; + } else if (afi->regions[i].load_address) { + to = afi->regions[i].load_address; + } else { + printf("no valid load address\n"); + return; + } + + memcpy((void *)to, (void *)from, afi->regions[i].size); + + printf("loaded region %d from %08lX to %08lX, %08X bytes\n", + i, + from, + to, + afi->regions[i].size); + } +} + +static void print_images(void) +{ + int i; + + parse_flash(); + for (i = 0; i < num_afs_images; i++) { + struct afs_image *afi = &afs_images[i]; + int j; + + printf("Image: \"%s\" (v%d):\n", afi->name, afi->version); + printf(" Entry point: 0x%08X\n", afi->entrypoint); + printf(" Attributes: 0x%08X: ", afi->attributes); + if (afi->attributes == 0x01) + printf("ARM executable"); + if (afi->attributes == 0x08) + printf("ARM backup"); + printf("\n"); + printf(" Flash mem start: 0x%08lX\n", + afi->flash_mem_start); + printf(" Flash mem end: 0x%08lX\n", + afi->flash_mem_end); + for (j = 0; j < afi->region_count; j++) { + printf(" region %d\n" + " load address: %08X\n" + " size: %08X\n" + " offset: %08X\n", + j, + afi->regions[j].load_address, + afi->regions[j].size, + afi->regions[j].offset); + } + } +} + +static int do_afs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc == 1) { + print_images(); + } else if (argc == 3 && !strcmp(argv[1], "load")) { + load_image(argv[2], 0x0); + } else if (argc == 4 && !strcmp(argv[1], "load")) { + ulong load_addr; + + load_addr = simple_strtoul(argv[3], NULL, 16); + load_image(argv[2], load_addr); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD(afs, 4, 0, do_afs, "show AFS partitions", + "no arguments\n" + " - list images in flash\n" + "load <image>\n" + " - load an image to the location indicated in the header\n" + "load <image> 0x<address>\n" + " - load an image to the location specified\n"); diff --git a/common/cmd_mem.c b/common/cmd_mem.c index bcb3ee325a..3f85c1aa85 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -999,10 +999,10 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, { ulong start, end; vu_long *buf, *dummy; - int iteration_limit; + ulong iteration_limit = 0; int ret; ulong errs = 0; /* number of errors, or -1 if interrupted */ - ulong pattern; + ulong pattern = 0; int iteration; #if defined(CONFIG_SYS_ALT_MEMTEST) const int alt_test = 1; @@ -1010,25 +1010,29 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, const int alt_test = 0; #endif + start = CONFIG_SYS_MEMTEST_START; + end = CONFIG_SYS_MEMTEST_END; + if (argc > 1) - start = simple_strtoul(argv[1], NULL, 16); - else - start = CONFIG_SYS_MEMTEST_START; + if (strict_strtoul(argv[1], 16, &start) < 0) + return CMD_RET_USAGE; if (argc > 2) - end = simple_strtoul(argv[2], NULL, 16); - else - end = CONFIG_SYS_MEMTEST_END; + if (strict_strtoul(argv[2], 16, &end) < 0) + return CMD_RET_USAGE; if (argc > 3) - pattern = (ulong)simple_strtoul(argv[3], NULL, 16); - else - pattern = 0; + if (strict_strtoul(argv[3], 16, &pattern) < 0) + return CMD_RET_USAGE; if (argc > 4) - iteration_limit = (ulong)simple_strtoul(argv[4], NULL, 16); - else - iteration_limit = 0; + if (strict_strtoul(argv[4], 16, &iteration_limit) < 0) + return CMD_RET_USAGE; + + if (end < start) { + printf("Refusing to do empty test\n"); + return -1; + } printf("Testing %08x ... %08x:\n", (uint)start, (uint)end); debug("%s:%d: start %#08lx end %#08lx\n", __func__, __LINE__, @@ -1079,7 +1083,7 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, ret = errs != 0; } - return ret; /* not reached */ + return ret; } #endif /* CONFIG_CMD_MEMTEST */ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 7f962dcb25..17fa7ea6bd 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -419,10 +419,13 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count, .mode = MTD_OPS_RAW }; - if (read) + if (read) { ret = mtd_read_oob(nand, off, &ops); - else + } else { ret = mtd_write_oob(nand, off, &ops); + if (!ret) + ret = nand_verify_page_oob(nand, &ops, off); + } if (ret) { printf("%s: error at offset %llx, ret %d\n", @@ -690,7 +693,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else ret = nand_write_skip_bad(nand, off, &rwsize, NULL, maxsize, - (u_char *)addr, 0); + (u_char *)addr, + WITH_WR_VERIFY); #ifdef CONFIG_CMD_NAND_TRIMFFS } else if (!strcmp(s, ".trimffs")) { if (read) { @@ -699,17 +703,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } ret = nand_write_skip_bad(nand, off, &rwsize, NULL, maxsize, (u_char *)addr, - WITH_DROP_FFS); -#endif -#ifdef CONFIG_CMD_NAND_YAFFS - } else if (!strcmp(s, ".yaffs")) { - if (read) { - printf("Unknown nand command suffix '%s'.\n", s); - return 1; - } - ret = nand_write_skip_bad(nand, off, &rwsize, NULL, - maxsize, (u_char *)addr, - WITH_YAFFS_OOB); + WITH_DROP_FFS | WITH_WR_VERIFY); #endif } else if (!strcmp(s, ".oob")) { /* out-of-band data */ @@ -853,11 +847,6 @@ static char nand_help_text[] = " 'addr', skipping bad blocks and dropping any pages at the end\n" " of eraseblocks that contain only 0xFF\n" #endif -#ifdef CONFIG_CMD_NAND_YAFFS - "nand write.yaffs - addr off|partition size\n" - " write 'size' bytes starting at offset 'off' with yaffs format\n" - " from memory address 'addr', skipping bad blocks.\n" -#endif "nand erase[.spread] [clean] off size - erase 'size' bytes " "from offset 'off'\n" " With '.spread', erase enough for given file size, otherwise,\n" diff --git a/common/cmd_part.c b/common/cmd_part.c index c99f52735f..d04588ec22 100644 --- a/common/cmd_part.c +++ b/common/cmd_part.c @@ -53,29 +53,57 @@ static int do_part_list(int argc, char * const argv[]) { int ret; block_dev_desc_t *desc; + char *var = NULL; + bool bootable = false; + int i; - if (argc < 2 || argc > 3) + if (argc < 2) return CMD_RET_USAGE; + if (argc > 2) { + for (i = 2; i < argc ; i++) { + if (argv[i][0] == '-') { + if (!strcmp(argv[i], "-bootable")) { + bootable = true; + } else { + printf("Unknown option %s\n", argv[i]); + return CMD_RET_USAGE; + } + } else { + var = argv[i]; + break; + } + } + + /* Loops should have been exited at the last argument, which + * as it contained the variable */ + if (argc != i + 1) + return CMD_RET_USAGE; + } + ret = get_device(argv[0], argv[1], &desc); if (ret < 0) return 1; - if (argc == 3) { + if (var != NULL) { int p; - char str[512] = { 0, }; + char str[512] = { '\0', }; disk_partition_t info; for (p = 1; p < 128; p++) { + char t[5]; int r = get_partition_info(desc, p, &info); - if (r == 0) { - char t[5]; - sprintf(t, "%s%d", str[0] ? " " : "", p); - strcat(str, t); - } + if (r != 0) + continue; + + if (bootable && !info.bootable) + continue; + + sprintf(t, "%s%d", str[0] ? " " : "", p); + strcat(str, t); } - setenv(argv[2], str); + setenv(var, str); return 0; } @@ -98,7 +126,7 @@ static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - part, 5, 1, do_part, + part, CONFIG_SYS_MAXARGS, 1, do_part, "disk partition related commands", "part uuid <interface> <dev>:<part>\n" " - print partition UUID\n" @@ -106,6 +134,7 @@ U_BOOT_CMD( " - set environment variable to partition UUID\n" "part list <interface> <dev>\n" " - print a device's partition table\n" - "part list <interface> <dev> <varname>\n" - " - set environment variable to the list of partitions" + "part list <interface> <dev> [flags] <varname>\n" + " - set environment variable to the list of partitions\n" + " flags can be -bootable (list only bootable partitions)" ); diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 6c8570377e..cbc10c5494 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -114,7 +114,7 @@ static int ubi_check(char *name) return 0; } - return -EEXIST; + return 1; } diff --git a/common/env_sf.c b/common/env_sf.c index 5e3729c2c2..e928f5752c 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -188,15 +188,17 @@ void env_relocate_spec(void) tmp_env2->flags == ACTIVE_FLAG) { gd->env_valid = 2; } else if (tmp_env1->flags == tmp_env2->flags) { - gd->env_valid = 2; + gd->env_valid = 1; } else if (tmp_env1->flags == 0xFF) { + gd->env_valid = 1; + } else if (tmp_env2->flags == 0xFF) { gd->env_valid = 2; } else { /* * this differs from code in env_flash.c, but I think a sane * default path is desirable. */ - gd->env_valid = 2; + gd->env_valid = 1; } if (gd->env_valid == 1) diff --git a/common/image.c b/common/image.c index a911aa9b4d..162b68269d 100644 --- a/common/image.c +++ b/common/image.c @@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, { IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",}, { IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin", }, + { IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", }, { -1, "", "", }, }; diff --git a/common/spl/spl.c b/common/spl/spl.c index cd75bbc4ce..8e1fb40c47 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -101,10 +101,22 @@ void spl_parse_image_header(const struct image_header *header) (int)sizeof(spl_image.name), spl_image.name, spl_image.load_addr, spl_image.size); } else { +#ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE + /* + * CONFIG_SPL_PANIC_ON_RAW_IMAGE is defined when the + * code which loads images in SPL cannot guarantee that + * absolutely all read errors will be reported. + * An example is the LPC32XX MLC NAND driver, which + * will consider that a completely unreadable NAND block + * is bad, and thus should be skipped silently. + */ + panic("** no mkimage signature but raw image not supported"); +#else /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", header->ih_magic); spl_set_header_raw_uboot(); +#endif } } diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index c2e596be69..e580f2291a 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -10,7 +10,6 @@ #include <spl.h> #include <asm/u-boot.h> #include <mmc.h> -#include <version.h> #include <image.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index d9eb2d6687..2a5eb29857 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -15,7 +15,6 @@ #include <sata.h> #include <scsi.h> #include <fat.h> -#include <version.h> #include <image.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 48a0705558..3e19424f9c 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -7,3 +7,4 @@ CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=123 CONFIG_DRAM_EMR1=4 +CONFIG_SYS_CLK_FREQ=912000000 diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 5c23bc76cd..fa48331fc5 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -1,6 +1,7 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI" CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb" +CONFIG_GMAC_TX_DELAY=1 CONFIG_VIDEO_VGA=y CONFIG_ARM=y CONFIG_ARCH_SUNXI=y diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig index 1504664dba..7690d1e722 100644 --- a/configs/Linksprite_pcDuino3_fdt_defconfig +++ b/configs/Linksprite_pcDuino3_fdt_defconfig @@ -13,5 +13,3 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=122 CONFIG_DRAM_EMR1=4 -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index 28fadcd3b9..0c39f70203 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -1,3 +1,10 @@ +# The Orangepi is a development board using the Allwinner A20 SoC, with 1G +# RAM, microsd slot, HDMI, 1Gbit ethernet, USB wifi, Micro USB (otg), sata, +# 4 USB A ports, ir receiver and a headphones jack. +# +# Also see: +# http://linux-sunxi.org/Xunlong_Orange_Pi +# http://www.orangepi.org/ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" CONFIG_FDTFILE="sun7i-a20-orangepi.dtb" diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 330679be2d..733e07fa96 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -1,6 +1,14 @@ +# The Orangepi mini is a development board using the Allwinner A20 SoC, +# with 1G RAM, 2 microsd slots (use the top side one for booting), HDMI, +# 1Gbit ethernet, USB wifi, Micro USB (otg), sata, 2 USB A ports, +# ir receiver and a headphones jack. +# +# Also see: +# http://linux-sunxi.org/Xunlong_Orange_Pi_Mini +# http://www.orangepi.org/ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI" -CONFIG_FDTFILE="sun7i-a20-orangepi.dtb" +CONFIG_FDTFILE="sun7i-a20-orangepi-mini.dtb" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_MMC0_CD_PIN="PH10" CONFIG_MMC3_CD_PIN="PH11" diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig index 8d38e262da..7ff0a13c0b 100644 --- a/configs/am335x_igep0033_defconfig +++ b/configs/am335x_igep0033_defconfig @@ -3,5 +3,3 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_ARM=y CONFIG_TARGET_AM335X_IGEP0033=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/arcangel4-be_defconfig b/configs/arcangel4-be_defconfig index 979f26e6dc..36ea6be09a 100644 --- a/configs/arcangel4-be_defconfig +++ b/configs/arcangel4-be_defconfig @@ -1,5 +1,10 @@ CONFIG_ARC=y -CONFIG_TARGET_ARCANGEL4=y -CONFIG_SYS_CLK_FREQ=70000000 CONFIG_CPU_BIG_ENDIAN=y +CONFIG_TARGET_ARCANGEL4=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="arcangel4" CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_CLK_FREQ=70000000 +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig index 797595f2c3..75a91c850f 100644 --- a/configs/arcangel4_defconfig +++ b/configs/arcangel4_defconfig @@ -1,4 +1,9 @@ CONFIG_ARC=y CONFIG_TARGET_ARCANGEL4=y -CONFIG_SYS_CLK_FREQ=70000000 +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="arcangel4" CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_CLK_FREQ=70000000 +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 6949d3a007..f3e1ebec93 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 30967e39c4..5e0b16e775 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index f908246d3d..11b42d4a9d 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index d106b5a28e..5426bcd288 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index c2ebb00a97..6eea1af904 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 76f68a6039..7ef1534a6e 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -1,3 +1,4 @@ +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 34ed9633a1..e5e1d8769a 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,6 +1,6 @@ CONFIG_ARC=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_TARGET_AXS101=y +CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_SYS_CLK_FREQ=750000000 -CONFIG_ARC_CACHE_LINE_SHIFT=5 -CONFIG_SYS_DCACHE_OFF=y -CONFIG_SYS_TEXT_BASE=0x81000000
\ No newline at end of file diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index c63dd4ab2e..7d662add41 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -1,5 +1,5 @@ -CONFIG_SYS_TEXT_BASE=0x81000000 -CONFIG_SYS_CLK_FREQ=50000000 CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_TARGET_AXS101=y +CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_CLK_FREQ=50000000 diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index 60df411cbd..54ac4d1024 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -1,5 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_ARM=y CONFIG_TARGET_BAV335X=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_MALLOC_F=y CONFIG_BAV_VERSION=1 +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index ed3f6fa13c..9046553878 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -1,5 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_ARM=y CONFIG_TARGET_BAV335X=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_MALLOC_F=y CONFIG_BAV_VERSION=2 +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 2fd21cf6d7..f10a5c2c90 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -5,5 +5,3 @@ CONFIG_TARGET_CM_FX6=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 086e526871..d189799c4b 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -1,5 +1,3 @@ CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_CM_T335=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig new file mode 100644 index 0000000000..89875672b5 --- /dev/null +++ b/configs/colibri_t20_defconfig @@ -0,0 +1,5 @@ +CONFIG_ARM=y +CONFIG_TEGRA=y +CONFIG_TEGRA20=y +CONFIG_TARGET_COLIBRI_T20=y +CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri" diff --git a/configs/colibri_t20_iris_defconfig b/configs/colibri_t20_iris_defconfig deleted file mode 100644 index a14d55a08b..0000000000 --- a/configs/colibri_t20_iris_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_ARM=y -CONFIG_TEGRA=y -CONFIG_TEGRA20=y -CONFIG_TARGET_COLIBRI_T20_IRIS=y -CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri_t20_iris" diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 266a2ab498..0427e9ed60 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -1,5 +1,5 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH" CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_CORVUS=y diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index 6eab019c1e..d6bbdc1742 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -3,4 +3,3 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" CONFIG_ARM=y CONFIG_TARGET_GW_VENTANA=y CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index 47f3f871ec..8bc5e8be8b 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -1,7 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index ab72942ad5..ba9e512b4e 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -1,7 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 112918b1bb..1764b39207 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -1,7 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index cc823226c1..5c862cf11e 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -1,7 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX" CONFIG_ARM=y CONFIG_TARGET_MX6SXSABRESD=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_DM=y CONFIG_DM_THERMAL=y diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 1bb7664ed7..20a51e1d2f 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -4,5 +4,3 @@ CONFIG_TARGET_NOKIA_RX51=y CONFIG_DM=n CONFIG_DM_SERIAL=n CONFIG_DM_GPIO=n -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index f417aacb48..08075e7c15 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -2,5 +2,3 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="REV1" CONFIG_ARM=y CONFIG_TARGET_PCM051=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index cc6f3f5418..56deb48fb7 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -2,5 +2,3 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="REV3" CONFIG_ARM=y CONFIG_TARGET_PCM051=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 9c6ddf4ca2..6346b57809 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -1,5 +1,3 @@ CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_PENGWYN=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index e14b008818..3b042ec1bb 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -1,5 +1,3 @@ CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_PEPPER=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 292f2ca13e..aa1805b665 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_DM=y CONFIG_DM_SERIAL=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_MACH_PH1_LD4=y CONFIG_PFC_MICRO_SUPPORT_CARD=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 202186245e..194f7a5c58 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_DM=y CONFIG_DM_SERIAL=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_MACH_PH1_PRO4=y CONFIG_PFC_MICRO_SUPPORT_CARD=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index cf229aef25..e7e7ffff0b 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_DM=y CONFIG_DM_SERIAL=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_MACH_PH1_SLD8=y CONFIG_PFC_MICRO_SUPPORT_CARD=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index b539d4a689..965fcaeaa7 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -1,4 +1,3 @@ CONFIG_ARM=y +CONFIG_ARCH_BCM283X=y CONFIG_TARGET_RPI_2=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 98d3199ccd..8de1d9f74e 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -1,4 +1,3 @@ CONFIG_ARM=y +CONFIG_ARCH_BCM283X=y CONFIG_TARGET_RPI=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 33e6fb8848..618e590802 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -2,5 +2,3 @@ CONFIG_ARM=y CONFIG_ARCH_S5PC1XX=y CONFIG_TARGET_S5P_GONI=y CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 70f5b86b85..a216039ab2 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -5,8 +5,6 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_DM=y CONFIG_DEFAULT_DEVICE_TREE="sandbox" -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_CROS_EC=y CONFIG_DM_CROS_EC=y CONFIG_CROS_EC_SANDBOX=y diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index e933a329b6..041030f942 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -2,5 +2,3 @@ CONFIG_ARM=y CONFIG_TARGET_SMDKC100=y CONFIG_ARCH_S5PC1XX=y CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 3a475053ba..576d9c51aa 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -5,5 +5,3 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index 1f0244b251..07a26434dc 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -5,5 +5,3 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y -CONFIG_SYS_MALLOC_F=y -CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 1c9ba881a4..e8cf311eb5 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -1,7 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="stv0991" CONFIG_ARM=y CONFIG_TARGET_STV0991=y -CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DM=y CONFIG_DM_SERIAL=y diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index b0e8c9f602..59f09d9f64 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -1,5 +1,10 @@ CONFIG_ARC=y -CONFIG_TARGET_TB100=y -CONFIG_SYS_CLK_FREQ=500000000 CONFIG_ARC_CACHE_LINE_SHIFT=5 +CONFIG_TARGET_TB100=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100" CONFIG_SYS_TEXT_BASE=0x84000000 +CONFIG_SYS_CLK_FREQ=500000000 +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y diff --git a/configs/vexpress_aemv8a_defconfig b/configs/vexpress_aemv8a_defconfig deleted file mode 100644 index 9f4b876556..0000000000 --- a/configs/vexpress_aemv8a_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_VEXPRESS64_AEMV8A=y -CONFIG_DEFAULT_DEVICE_TREE="vexpress64" diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig new file mode 100644 index 0000000000..142a505fe4 --- /dev/null +++ b/configs/work_92105_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_WORK_92105=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="" diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 39a7f6b5fb..b6bca82db0 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -3,6 +3,7 @@ CONFIG_ARM=y CONFIG_ZYNQ=y CONFIG_TARGET_ZYNQ_MICROZED=y CONFIG_OF_CONTROL=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/zynq_zc70x_defconfig b/configs/zynq_zc70x_defconfig index a8ef97f173..44f3ae0ad1 100644 --- a/configs/zynq_zc70x_defconfig +++ b/configs/zynq_zc70x_defconfig @@ -4,6 +4,7 @@ CONFIG_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC70X=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702" +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index ecd245a549..d689857f17 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -5,6 +5,7 @@ CONFIG_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010" +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 341a4d83aa..9745d21703 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -5,6 +5,7 @@ CONFIG_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012" +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index ee08a9f7e0..924efb4262 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -5,6 +5,7 @@ CONFIG_ZYNQ=y CONFIG_TARGET_ZYNQ_ZC770=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013" +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 2500d84e9a..01fa7235f9 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -4,6 +4,7 @@ CONFIG_ZYNQ=y CONFIG_TARGET_ZYNQ_ZED=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zed" +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index c9d0121afb..f1001f1162 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -4,6 +4,7 @@ CONFIG_ZYNQ=y CONFIG_TARGET_ZYNQ_ZYBO=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo" +# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y diff --git a/doc/README.distro b/doc/README.distro index dd0f1c7b6a..0308a4c73a 100644 --- a/doc/README.distro +++ b/doc/README.distro @@ -1,6 +1,7 @@ /* * (C) Copyright 2014 Red Hat Inc. * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2015 K. Merker <merker@debian.org> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -339,3 +340,49 @@ scan_dev_for_scripts: If you want to disable boot.scr on all disks, set the value to something innocuous, e.g. setenv scan_dev_for_scripts true. + + +Interactively booting from a specific device at the u-boot prompt +================================================================= + +For interactively booting from a user-selected device at the u-boot command +prompt, the environment provides predefined bootcmd_<target> variables for +every target defined in boot_targets, which can be run be the user. + +If the target is a storage device, the format of the target is always +<device type><device number>, e.g. mmc0. Specifying the device number is +mandatory for storage devices, even if only support for a single instance +of the storage device is actually implemented. + +For network targets (dhcp, pxe), only the device type gets specified; +they do not have a device number. + +Examples: + + - run bootcmd_usb0 + boots from the first USB mass storage device + + - run bootcmd_mmc1 + boots from the second MMC device + + - run bootcmd_pxe + boots by tftp using a pxelinux.cfg + +The list of possible targets consists of: + +- network targets + * dhcp + * pxe + +- storage targets (to which a device number must be appended) + * mmc + * sata + * scsi + * ide + * usb + +Other *boot* variables than the ones defined above are only for internal use +of the boot environment and are not guaranteed to exist or work in the same +way in future u-boot versions. In particular the <device type>_boot +variables (e.g. mmc_boot, usb_boot) are a strictly internal implementation +detail and must not be used as a public interface. diff --git a/doc/README.drivers.eth b/doc/README.drivers.eth index eb83038b5d..42af442ea1 100644 --- a/doc/README.drivers.eth +++ b/doc/README.drivers.eth @@ -43,15 +43,16 @@ int ape_register(bd_t *bis, int iobase) { struct ape_priv *priv; struct eth_device *dev; + struct mii_dev *bus; priv = malloc(sizeof(*priv)); if (priv == NULL) - return 1; + return -ENOMEM; dev = malloc(sizeof(*dev)); if (dev == NULL) { free(priv); - return 1; + return -ENOMEM; } /* setup whatever private state you need */ @@ -59,7 +60,8 @@ int ape_register(bd_t *bis, int iobase) memset(dev, 0, sizeof(*dev)); sprintf(dev->name, "APE"); - /* if your device has dedicated hardware storage for the + /* + * if your device has dedicated hardware storage for the * MAC, read it and initialize dev->enetaddr with it */ ape_mac_read(dev->enetaddr); @@ -74,8 +76,17 @@ int ape_register(bd_t *bis, int iobase) eth_register(dev); -#ifdef CONFIG_CMD_MII) - miiphy_register(dev->name, ape_mii_read, ape_mii_write); +#ifdef CONFIG_PHYLIB + bus = mdio_alloc(); + if (!bus) { + free(priv); + free(dev); + return -ENOMEM; + } + + bus->read = ape_mii_read; + bus->write = ape_mii_write; + mdio_register(bus); #endif return 1; @@ -166,25 +177,33 @@ some net operation (ping / tftp / whatever...) eth_halt() dev->halt() ------------------------------ - CONFIG_MII / CONFIG_CMD_MII ------------------------------ +-------------------------------- + CONFIG_PHYLIB / CONFIG_CMD_MII +-------------------------------- If your device supports banging arbitrary values on the MII bus (pretty much every device does), you should add support for the mii command. Doing so is fairly trivial and makes debugging mii issues a lot easier at runtime. After you have called eth_register() in your driver's register function, add -a call to miiphy_register() like so: -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, mii_read, mii_write); -#endif +a call to mdio_alloc() and mdio_register() like so: + bus = mdio_alloc(); + if (!bus) { + free(priv); + free(dev); + return -ENOMEM; + } + + bus->read = ape_mii_read; + bus->write = ape_mii_write; + mdio_register(bus); And then define the mii_read and mii_write functions if you haven't already. Their syntax is straightforward: - int mii_read(char *devname, uchar addr, uchar reg, ushort *val); - int mii_write(char *devname, uchar addr, uchar reg, ushort val); + int mii_read(struct mii_dev *bus, int addr, int devad, int reg); + int mii_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val); The read function should read the register 'reg' from the phy at address 'addr' -and store the result in the pointer 'val'. The implementation for the write -function should logically follow. +and return the result to its caller. The implementation for the write function +should logically follow. diff --git a/doc/README.generic-board b/doc/README.generic-board index 37c1b03ced..bd8eae1992 100644 --- a/doc/README.generic-board +++ b/doc/README.generic-board @@ -44,16 +44,18 @@ The following architectures are supported now: arc arm + avr32 + blackfin + m68k + microblaze mips + nios2 powerpc sandbox x86 -If your architecture is not supported, you need to adjust your -arch/<arch>/config.mk file to include: - - __HAVE_ARCH_GENERIC_BOARD := y - +If your architecture is not supported, you need to select +HAVE_GENERIC_BOARD in arch/Kconfig and test it with a suitable board, as follows. diff --git a/doc/README.nand b/doc/README.nand index dee0e00a61..46d7edd179 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -99,12 +99,6 @@ Configuration Options: CONFIG_CMD_NAND_TORTURE Enables the torture command (see description of this command below). - CONFIG_MTD_NAND_ECC_JFFS2 - Define this if you want the Error Correction Code information in - the out-of-band data to be formatted to match the JFFS2 file system. - CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for - someone to implement. - CONFIG_SYS_MAX_NAND_DEVICE The maximum number of NAND devices you want to support. @@ -312,12 +306,6 @@ Platform specific options NOTE: ===== -The current NAND implementation is based on what is in recent -Linux kernels. The old legacy implementation has been removed. - -If you have board code which used CONFIG_NAND_LEGACY, you'll need -to convert to the current NAND interface for it to continue to work. - The Disk On Chip driver is currently broken and has been for some time. There is a driver in drivers/mtd/nand, taken from Linux, that works with the current NAND system but has not yet been adapted to the u-boot diff --git a/doc/README.semihosting b/doc/README.semihosting index 7248560780..c016a4f840 100644 --- a/doc/README.semihosting +++ b/doc/README.semihosting @@ -30,25 +30,10 @@ vexpress_aemv8a.h but differentiate the two models by the presence or absence of CONFIG_BASE_FVP. This change is tested and works on both the Foundation and Base fastmodel simulators. -The level of semihosting support is minimal, restricted to just what it -takes to load images to memory. If more semihosting functionality is -required, such as file seek, outputting strings, reading characters, etc, -then it can be easily added later. +The semihosting code adds a command: -We require that the board include file define these env variables: -- kernel_name e.g. "uImage" -- kernel_addr_r e.g. "0x80000000" -- initrd_name e.g. "ramdisk.img" -- initrd_addr_r e.g. "0x88000000" -- fdt_name e.g. "devtree.dtb" -- fdt_addr_r e.g. "0x83000000" + smhload <image> <address> [env var] -Optionally, "fdt_high" and "initrd_high" can be specified as per -their rules for allowing or preventing copying of these images. - -For the "fdt chosen" startup macro, this code will then define: -- initrd_end (based on retrieving initrd_addr_r plus actual initrd_size) - -We will then load the kernel, initrd, and fdt into the specified -locations in memory in a similar way that the ATF fastmodel code -uses semihosting calls to load other boot stages and u-boot itself. +That will load an image from the host filesystem into RAM at the specified +address and optionally store the load end address in the specified +environment variable. diff --git a/doc/README.x86 b/doc/README.x86 index fb87682e05..0355d1c9cb 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -105,6 +105,13 @@ in this FSP package too. Rename the first one to fsp.bin and second one to cmc.bin and put them in the board directory. +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + Now you can build U-Boot and obtain u-boot.rom $ make crownbay_defconfig diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index dc4e44fbc5..b022f6163f 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -61,6 +61,8 @@ Board(panel specific): disabled with compatible string "samsung,sysmmu-v3.3", with a "reg" property holding the register address of FIMD sysmmu. + samsung,pwm-out-gpio: PWM output GPIO. + samsung,bl-en-gpio: backlight enable GPIO. Example: SOC specific part: diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index c908fab450..88b90e0203 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -785,7 +785,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) /* Read/Write from ahci */ if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), - user_buffer, user_buffer_size, + user_buffer, transfer_size, is_write)) { debug("scsi_ahci: SCSI %s10 command failure.\n", is_write ? "WRITE" : "READ"); diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index f9ee18999a..a9754922e8 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -64,7 +64,7 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, return ret; /* then write */ ret = nand_write_skip_bad(nand, start, &count, &actual, - lim, buf, 0); + lim, buf, WITH_WR_VERIFY); } if (ret != 0) { diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index b609e73bba..7b5178a23a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -7,3 +7,10 @@ config DM_GPIO the GPIO uclass. Drivers provide methods to query the particular GPIOs that they provide. The uclass interface is defined in include/asm-generic/gpio.h. + +config LPC32XX_GPIO + bool "LPC32XX GPIO driver" + depends on DM + default n + help + Support for the LPC32XX GPIO driver. diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fe9a3b2396..85f71c5d4a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o oby-$(CONFIG_SX151X) += sx151x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o +obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c new file mode 100644 index 0000000000..96b312592b --- /dev/null +++ b/drivers/gpio/lpc32xx_gpio.c @@ -0,0 +1,293 @@ +/* + * LPC32xxGPIO driver + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch-lpc32xx/cpu.h> +#include <asm/arch-lpc32xx/gpio.h> +#include <asm-generic/gpio.h> +#include <dm.h> + +/** + * LPC32xx GPIOs work in banks but are non-homogeneous: + * - each bank holds a different number of GPIOs + * - some GPIOs are input/ouput, some input only, some output only; + * - some GPIOs have different meanings as an input and as an output; + * - some GPIOs are controlled on a given port and bit index, but + * read on another one. +* + * In order to keep this code simple, GPIOS are considered here as + * homogeneous and linear, from 0 to 127. + * + * ** WARNING #1 ** + * + * Client code is responsible for properly using valid GPIO numbers, + * including cases where a single physical GPIO has differing numbers + * for setting its direction, reading it and/or writing to it. + * + * ** WARNING #2 ** + * + * Please read NOTE in description of lpc32xx_gpio_get_function(). + */ + +#define LPC32XX_GPIOS 128 + +struct lpc32xx_gpio_platdata { + struct gpio_regs *regs; + /* GPIO FUNCTION: SEE WARNING #2 */ + signed char function[LPC32XX_GPIOS]; +}; + +/** + * We have 4 GPIO ports of 32 bits each + */ + +#define MAX_GPIO 128 + +#define GPIO_TO_PORT(gpio) ((gpio / 32) & 3) +#define GPIO_TO_RANK(gpio) (gpio % 32) +#define GPIO_TO_MASK(gpio) (1 << (gpio % 32)) + +/** + * Configure a GPIO number 'offset' as input + */ + +static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + int port, mask; + struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + struct gpio_regs *regs = gpio_platdata->regs; + + port = GPIO_TO_PORT(offset); + mask = GPIO_TO_MASK(offset); + + switch (port) { + case 0: + writel(mask, ®s->p0_dir_clr); + break; + case 1: + writel(mask, ®s->p1_dir_clr); + break; + case 2: + /* ports 2 and 3 share a common direction */ + case 3: + writel(mask, ®s->p2_p3_dir_clr); + break; + default: + return -1; + } + + /* GPIO FUNCTION: SEE WARNING #2 */ + gpio_platdata->function[offset] = GPIOF_INPUT; + + return 0; +} + +/** + * Get the value of a GPIO + */ + +static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset) +{ + int port, rank, mask, value; + struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + struct gpio_regs *regs = gpio_platdata->regs; + + port = GPIO_TO_PORT(offset); + + switch (port) { + case 0: + value = readl(®s->p0_inp_state); + break; + case 1: + value = readl(®s->p1_inp_state); + break; + case 2: + value = readl(®s->p2_inp_state); + break; + case 3: + value = readl(®s->p3_inp_state); + break; + default: + return -1; + } + + rank = GPIO_TO_RANK(offset); + mask = GPIO_TO_MASK(offset); + + return (value & mask) >> rank; +} + +/** + * Set a GPIO + */ + +static int gpio_set(struct udevice *dev, unsigned gpio) +{ + int port, mask; + struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + struct gpio_regs *regs = gpio_platdata->regs; + + port = GPIO_TO_PORT(gpio); + mask = GPIO_TO_MASK(gpio); + + switch (port) { + case 0: + writel(mask, ®s->p0_outp_set); + break; + case 1: + writel(mask, ®s->p1_outp_set); + break; + case 2: + writel(mask, ®s->p2_outp_set); + break; + case 3: + writel(mask, ®s->p3_outp_set); + break; + default: + return -1; + } + return 0; +} + +/** + * Clear a GPIO + */ + +static int gpio_clr(struct udevice *dev, unsigned gpio) +{ + int port, mask; + struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + struct gpio_regs *regs = gpio_platdata->regs; + + port = GPIO_TO_PORT(gpio); + mask = GPIO_TO_MASK(gpio); + + switch (port) { + case 0: + writel(mask, ®s->p0_outp_clr); + break; + case 1: + writel(mask, ®s->p1_outp_clr); + break; + case 2: + writel(mask, ®s->p2_outp_clr); + break; + case 3: + writel(mask, ®s->p3_outp_clr); + break; + default: + return -1; + } + return 0; +} + +/** + * Set the value of a GPIO + */ + +static int lpc32xx_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + if (value) + return gpio_set(dev, offset); + else + return gpio_clr(dev, offset); +} + +/** + * Configure a GPIO number 'offset' as output with given initial value. + */ + +static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) +{ + int port, mask; + struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + struct gpio_regs *regs = gpio_platdata->regs; + + port = GPIO_TO_PORT(offset); + mask = GPIO_TO_MASK(offset); + + switch (port) { + case 0: + writel(mask, ®s->p0_dir_set); + break; + case 1: + writel(mask, ®s->p1_dir_set); + break; + case 2: + /* ports 2 and 3 share a common direction */ + case 3: + writel(mask, ®s->p2_p3_dir_set); + break; + default: + return -1; + } + + /* GPIO FUNCTION: SEE WARNING #2 */ + gpio_platdata->function[offset] = GPIOF_OUTPUT; + + return lpc32xx_gpio_set_value(dev, offset, value); +} + +/** + * GPIO functions are supposed to be computed from their current + * configuration, but that's way too complicated in LPC32XX. A simpler + * approach is used, where the GPIO functions are cached in an array. + * When the GPIO is in use, its function is either "input" or "output" + * depending on its direction, otherwise its function is "unknown". + * + * ** NOTE ** + * + * THIS APPROACH WAS CHOSEN DU TO THE COMPLEX NATURE OF THE LPC32XX + * GPIOS; DO NOT TAKE THIS AS AN EXAMPLE FOR NEW CODE. + */ + +static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + return gpio_platdata->function[offset]; +} + +static const struct dm_gpio_ops gpio_lpc32xx_ops = { + .direction_input = lpc32xx_gpio_direction_input, + .direction_output = lpc32xx_gpio_direction_output, + .get_value = lpc32xx_gpio_get_value, + .set_value = lpc32xx_gpio_set_value, + .get_function = lpc32xx_gpio_get_function, +}; + +static int lpc32xx_gpio_probe(struct udevice *dev) +{ + struct lpc32xx_gpio_platdata *gpio_platdata = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + if (dev->of_offset == -1) { + /* Tell the uclass how many GPIOs we have */ + uc_priv->gpio_count = LPC32XX_GPIOS; + } + + /* set base address for GPIO registers */ + gpio_platdata->regs = (struct gpio_regs *)GPIO_BASE; + + /* all GPIO functions are unknown until requested */ + /* GPIO FUNCTION: SEE WARNING #2 */ + memset(gpio_platdata->function, GPIOF_UNKNOWN, + sizeof(gpio_platdata->function)); + + return 0; +} + +U_BOOT_DRIVER(gpio_lpc32xx) = { + .name = "gpio_lpc32xx", + .id = UCLASS_GPIO, + .ops = &gpio_lpc32xx_ops, + .probe = lpc32xx_gpio_probe, + .priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_platdata), +}; diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 25b8e8a2d7..b4fb057c16 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o obj-$(CONFIG_DTT_DS1621) += ds1621.o obj-$(CONFIG_DTT_DS1722) += ds1722.o obj-$(CONFIG_DTT_DS1775) += ds1775.o +obj-$(CONFIG_DTT_DS620) += ds620.o obj-$(CONFIG_DTT_LM63) += lm63.o obj-$(CONFIG_DTT_LM73) += lm73.o obj-$(CONFIG_DTT_LM75) += lm75.o diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c new file mode 100644 index 0000000000..1ecc3da799 --- /dev/null +++ b/drivers/hwmon/ds620.c @@ -0,0 +1,65 @@ +/* + * DS620 DTT support + * + * (C) Copyright 2014 3ADEV <http://www.3adev.com> + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat. + */ + +#include <common.h> +#include <i2c.h> +#include <dtt.h> + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x48 +#define DTT_START_CONVERT 0x51 +#define DTT_TEMP 0xAA +#define DTT_CONFIG 0xAC + +/* + * Config register MSB bits + */ +#define DTT_CONFIG_1SHOT 0x01 +#define DTT_CONFIG_AUTOC 0x02 +#define DTT_CONFIG_R0 0x04 /* always 1 */ +#define DTT_CONFIG_R1 0x08 /* always 1 */ +#define DTT_CONFIG_TLF 0x10 +#define DTT_CONFIG_THF 0x20 +#define DTT_CONFIG_NVB 0x40 +#define DTT_CONFIG_DONE 0x80 + +#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor & 0x07)) + +int dtt_init_one(int sensor) +{ + uint8_t config = DTT_CONFIG_1SHOT + | DTT_CONFIG_R0 + | DTT_CONFIG_R1; + return i2c_write(CHIP(sensor), DTT_CONFIG, 1, &config, 1); +} + +int dtt_get_temp(int sensor) +{ + uint8_t status; + uint8_t temp[2]; + + /* Start a conversion, may take up to 1 second. */ + i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0); + do { + if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, &status, 1)) + /* bail out if I2C error */ + status |= DTT_CONFIG_DONE; + } while (!(status & DTT_CONFIG_DONE)); + if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2)) + /* bail out if I2C error */ + return -274; /* below absolute zero == error */ + + return ((int16_t)(temp[1] | (temp[0] << 8))) >> 7; +} diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 774bc94a4a..26ea854ec8 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o +obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c new file mode 100644 index 0000000000..78d26e48c3 --- /dev/null +++ b/drivers/i2c/lpc32xx_i2c.c @@ -0,0 +1,249 @@ +/* + * LPC32xx I2C interface driver + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <i2c.h> +#include <asm/errno.h> +#include <asm/arch/clk.h> + +/* + * Provide default speed and slave if target did not + */ + +#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED) +#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000 +#endif + +#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE) +#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0 +#endif + +/* i2c register set */ +struct lpc32xx_i2c_registers { + union { + u32 rx; + u32 tx; + }; + u32 stat; + u32 ctrl; + u32 clk_hi; + u32 clk_lo; + u32 adr; + u32 rxfl; + u32 txfl; + u32 rxb; + u32 txb; + u32 stx; + u32 stxfl; +}; + +/* TX register fields */ +#define LPC32XX_I2C_TX_START 0x00000100 +#define LPC32XX_I2C_TX_STOP 0x00000200 + +/* Control register values */ +#define LPC32XX_I2C_SOFT_RESET 0x00000100 + +/* Status register values */ +#define LPC32XX_I2C_STAT_TFF 0x00000400 +#define LPC32XX_I2C_STAT_RFE 0x00000200 +#define LPC32XX_I2C_STAT_DRMI 0x00000008 +#define LPC32XX_I2C_STAT_NAI 0x00000004 +#define LPC32XX_I2C_STAT_TDI 0x00000001 + +static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = { + (struct lpc32xx_i2c_registers *)I2C1_BASE, + (struct lpc32xx_i2c_registers *)I2C2_BASE +}; + +/* Set I2C bus speed */ +static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + int half_period; + + if (speed == 0) + return -EINVAL; + + half_period = (105000000 / speed) / 2; + + if ((half_period > 255) || (half_period < 0)) + return -EINVAL; + + writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi); + writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo); + return 0; +} + +/* I2C init called by cmd_i2c when doing 'i2c reset'. */ +static void _i2c_init(struct i2c_adapter *adap, + int requested_speed, int slaveadd) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + + /* soft reset (auto-clears) */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + /* set HI and LO periods for about 350 kHz */ + lpc32xx_i2c_set_bus_speed(adap, requested_speed); +} + +/* I2C probe called by cmd_i2c when doing 'i2c probe'. */ +static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + int stat; + + /* Soft-reset the controller */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET) + ; + /* Addre slave for write with start before and stop after */ + writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP, + &i2c->tx); + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* was there no acknowledge? */ + return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0; +} + +/* + * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c + * Begin write, send address byte(s), begin read, receive data bytes, end. + */ +static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + int stat, wlen; + + /* Soft-reset the controller */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET) + ; + /* do we need to write an address at all? */ + if (alen) { + /* Address slave in write mode */ + writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx); + /* write address bytes */ + while (alen--) { + /* compute address byte + stop for the last one */ + int a = (addr >> (8 * alen)) & 0xff; + if (!alen) + a |= LPC32XX_I2C_TX_STOP; + /* Send address byte */ + writel(a, &i2c->tx); + } + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* clear end-of-transaction flag */ + writel(1, &i2c->stat); + } + /* do we have to read data at all? */ + if (length) { + /* Address slave in read mode */ + writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx); + wlen = length; + /* get data */ + while (length | wlen) { + /* read status for TFF and RFE */ + stat = readl(&i2c->stat); + /* must we, can we write a trigger byte? */ + if ((wlen > 0) + & (!(stat & LPC32XX_I2C_STAT_TFF))) { + wlen--; + /* write trigger byte + stop if last */ + writel(wlen ? 0 : + LPC32XX_I2C_TX_STOP, &i2c->tx); + } + /* must we, can we read a data byte? */ + if ((length > 0) + & (!(stat & LPC32XX_I2C_STAT_RFE))) { + length--; + /* read byte */ + *(data++) = readl(&i2c->rx); + } + } + } + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* clear end-of-transaction flag */ + writel(1, &i2c->stat); + /* success */ + return 0; +} + +/* + * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c + * Begin write, send address byte(s), send data bytes, end. + */ +static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + int stat; + + /* Soft-reset the controller */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET) + ; + /* do we need to write anything at all? */ + if (alen | length) + /* Address slave in write mode */ + writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx); + /* write address bytes */ + while (alen) { + /* wait for transmit fifo not full */ + stat = readl(&i2c->stat); + if (!(stat & LPC32XX_I2C_STAT_TFF)) { + alen--; + int a = (addr >> (8 * alen)) & 0xff; + if (!(alen | length)) + a |= LPC32XX_I2C_TX_STOP; + /* Send address byte */ + writel(a, &i2c->tx); + } + } + while (length) { + /* wait for transmit fifo not full */ + stat = readl(&i2c->stat); + if (!(stat & LPC32XX_I2C_STAT_TFF)) { + /* compute data byte, add stop if length==0 */ + length--; + int d = *(data++); + if (!length) + d |= LPC32XX_I2C_TX_STOP; + /* Send data byte */ + writel(d, &i2c->tx); + } + } + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* clear end-of-transaction flag */ + writel(1, &i2c->stat); + return 0; +} + +U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe, + lpc32xx_i2c_read, lpc32xx_i2c_write, + lpc32xx_i2c_set_bus_speed, + CONFIG_SYS_I2C_LPC32XX_SPEED, + CONFIG_SYS_I2C_LPC32XX_SLAVE, + 0) + +U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe, + lpc32xx_i2c_read, lpc32xx_i2c_write, + lpc32xx_i2c_set_bus_speed, + CONFIG_SYS_I2C_LPC32XX_SPEED, + CONFIG_SYS_I2C_LPC32XX_SLAVE, + 1) diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 92f7d8942f..4ec2968ece 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -39,8 +39,8 @@ #include <common.h> #include <malloc.h> #include <sdhci.h> -#include <asm/arch/timer.h> -#include <asm/arch-bcm2835/sdhci.h> +#include <mach/timer.h> +#include <mach/sdhci.h> /* 400KHz is max freq for card ID etc. Use that as min */ #define MIN_FREQ 400000 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 1f02bfc35f..347ea62e0b 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o +obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index b16e3aa157..a2016e7945 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1456,6 +1456,9 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = at91_nand_wait_ready; #endif nand->chip_delay = 20; +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + nand->bbt_options |= NAND_BBT_USE_FLASH; +#endif #ifdef CONFIG_ATMEL_NAND_HWECC #ifdef CONFIG_ATMEL_NAND_HW_PMECC @@ -1522,6 +1525,9 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) nand->dev_ready = at91_nand_ready; #endif nand->chip_delay = 75; +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + nand->bbt_options |= NAND_BBT_USE_FLASH; +#endif ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); if (ret) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 41689b5165..a3970745c9 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -405,18 +405,6 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, goto err; } -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - /* Send command to read back the data */ - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - - if (chip->verify_buf(mtd, buf, mtd->writesize)) { - ret = -EIO; - goto err; - } - - /* Make sure the next page prog is preceded by a status read */ - chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); -#endif err: /* restore ECC layout */ if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 3372b64212..e85832d319 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -561,41 +561,6 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) len, avail); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* - * Verify buffer against the FCM Controller Data Buffer - */ -static int fsl_elbc_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; - struct fsl_elbc_ctrl *ctrl = priv->ctrl; - int i; - - if (len < 0) { - printf("write_buf of %d bytes", len); - return -EINVAL; - } - - if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { - printf("verify_buf beyond end of buffer " - "(%d requested, %u available)\n", - len, ctrl->read_bytes - ctrl->index); - - ctrl->index = ctrl->read_bytes; - return -EINVAL; - } - - for (i = 0; i < len; i++) - if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) - break; - - ctrl->index += len; - return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; -} -#endif - /* This function is called after Program and Erase Operations to * check for success or failure. */ @@ -727,9 +692,6 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) nand->read_byte = fsl_elbc_read_byte; nand->write_buf = fsl_elbc_write_buf; nand->read_buf = fsl_elbc_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = fsl_elbc_verify_buf; -#endif nand->select_chip = fsl_elbc_select_chip; nand->cmdfunc = fsl_elbc_cmdfunc; nand->waitfunc = fsl_elbc_wait; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index b283eaea34..7903eebd53 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -683,41 +683,6 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) __func__, len, avail); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* - * Verify buffer against the IFC Controller Data Buffer - */ -static int fsl_ifc_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; - int i; - - if (len < 0) { - printf("%s of %d bytes", __func__, len); - return -EINVAL; - } - - if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { - printf("%s beyond end of buffer " - "(%d requested, %u available)\n", - __func__, len, ctrl->read_bytes - ctrl->index); - - ctrl->index = ctrl->read_bytes; - return -EINVAL; - } - - for (i = 0; i < len; i++) - if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) - break; - - ctrl->index += len; - return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO; -} -#endif - /* This function is called after Program and Erase Operations to * check for success or failure. */ @@ -940,9 +905,6 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->write_buf = fsl_ifc_write_buf; nand->read_buf = fsl_ifc_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = fsl_ifc_verify_buf; -#endif nand->select_chip = fsl_ifc_select_chip; nand->cmdfunc = fsl_ifc_cmdfunc; nand->waitfunc = fsl_ifc_wait; diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 65ce98ad5e..5426c32114 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -153,21 +153,6 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) buf[i] = in_8(chip->IO_ADDR_R); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int upm_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - - for (i = 0; i < len; i++) { - if (buf[i] != in_8(chip->IO_ADDR_R)) - return -EFAULT; - } - - return 0; -} -#endif - static int nand_dev_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -193,9 +178,6 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) chip->read_byte = upm_nand_read_byte; chip->read_buf = upm_nand_read_buf; chip->write_buf = upm_nand_write_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - chip->verify_buf = upm_nand_verify_buf; -#endif if (fun->dev_ready) chip->dev_ready = nand_dev_ready; diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c new file mode 100644 index 0000000000..8156fe9613 --- /dev/null +++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c @@ -0,0 +1,764 @@ +/* + * LPC32xx MLC NAND flash controller driver + * + * (C) Copyright 2014 3ADEV <http://3adev.com> + * Written by Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * NOTE: + * + * The MLC NAND flash controller provides hardware Reed-Solomon ECC + * covering in- and out-of-band data together. Therefore, in- and out- + * of-band data must be written together in order to have a valid ECC. + * + * Consequently, pages with meaningful in-band data are written with + * blank (all-ones) out-of-band data and a valid ECC, and any later + * out-of-band data write will void the ECC. + * + * Therefore, code which reads such late-written out-of-band data + * should not rely on the ECC validity. + */ + +#include <common.h> +#include <nand.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <nand.h> +#include <asm/arch/clk.h> +#include <asm/arch/sys_proto.h> + +/* + * MLC NAND controller registers. + */ +struct lpc32xx_nand_mlc_registers { + u8 buff[32768]; /* controller's serial data buffer */ + u8 data[32768]; /* NAND's raw data buffer */ + u32 cmd; + u32 addr; + u32 ecc_enc_reg; + u32 ecc_dec_reg; + u32 ecc_auto_enc_reg; + u32 ecc_auto_dec_reg; + u32 rpr; + u32 wpr; + u32 rubp; + u32 robp; + u32 sw_wp_add_low; + u32 sw_wp_add_hig; + u32 icr; + u32 time_reg; + u32 irq_mr; + u32 irq_sr; + u32 lock_pr; + u32 isr; + u32 ceh; +}; + +/* LOCK_PR register defines */ +#define LOCK_PR_UNLOCK_KEY 0x0000A25E /* Magic unlock value */ + +/* ICR defines */ +#define ICR_LARGE_BLOCKS 0x00000004 /* configure for 2KB blocks */ +#define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */ + +/* CEH defines */ +#define CEH_NORMAL_CE 0x00000001 /* do not force CE ON */ + +/* ISR register defines */ +#define ISR_NAND_READY 0x00000001 +#define ISR_CONTROLLER_READY 0x00000002 +#define ISR_ECC_READY 0x00000004 +#define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1) +#define ISR_DECODER_FAILURE 0x00000040 +#define ISR_DECODER_ERROR 0x00000008 + +/* time-out for NAND chip / controller loops, in us */ +#define LPC32X_NAND_TIMEOUT 5000 + +/* + * There is a single instance of the NAND MLC controller + */ + +static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers + = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE; + +#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o) + +/** + * OOB data in each small page are 6 'free' then 10 ECC bytes. + * To make things easier, when reading large pages, the four pages' + * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer, + * while the the four ECC bytes are groupe in its last 40 bytes. + * + * The struct below represents how free vs ecc oob bytes are stored + * in the buffer. + * + * Note: the OOB bytes contain the bad block marker at offsets 0 and 1. + */ + +struct lpc32xx_oob { + struct { + uint8_t free_oob_bytes[6]; + } free[4]; + struct { + uint8_t ecc_oob_bytes[10]; + } ecc[4]; +}; + +/* + * Initialize the controller + */ + +static void lpc32xx_nand_init(void) +{ + unsigned int clk; + + /* Configure controller for no software write protection, x8 bus + width, large block device, and 4 address words */ + + /* unlock controller registers with magic key */ + writel(LOCK_PR_UNLOCK_KEY, + &lpc32xx_nand_mlc_registers->lock_pr); + + /* enable large blocks and large NANDs */ + writel(ICR_LARGE_BLOCKS | ICR_ADDR4, + &lpc32xx_nand_mlc_registers->icr); + + /* Make sure MLC interrupts are disabled */ + writel(0, &lpc32xx_nand_mlc_registers->irq_mr); + + /* Normal chip enable operation */ + writel(CEH_NORMAL_CE, + &lpc32xx_nand_mlc_registers->ceh); + + /* Setup NAND timing */ + clk = get_hclk_clk_rate(); + + writel( + clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | + clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | + clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | + clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | + clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | + clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | + clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), + &lpc32xx_nand_mlc_registers->time_reg); +} + +#if !defined(CONFIG_SPL_BUILD) + +/** + * lpc32xx_cmd_ctrl - write command to either cmd or data register + */ + +static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd); + else if (ctrl & NAND_ALE) + writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr); +} + +/** + * lpc32xx_read_byte - read a byte from the NAND + * @mtd: MTD device structure + */ + +static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) +{ + return readb(&lpc32xx_nand_mlc_registers->data); +} + +/** + * lpc32xx_dev_ready - test if NAND device (actually controller) is ready + * @mtd: MTD device structure + * @mode: mode to set the ECC HW to. + */ + +static int lpc32xx_dev_ready(struct mtd_info *mtd) +{ + /* means *controller* ready for us */ + int status = readl(&lpc32xx_nand_mlc_registers->isr); + return status & ISR_CONTROLLER_READY; +} + +/** + * ECC layout -- this is needed whatever ECC mode we are using. + * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes. + * To make U-Boot's life easier, we pack 'useable' OOB at the + * front and R/S ECC at the back. + */ + +static struct nand_ecclayout lpc32xx_largepage_ecclayout = { + .eccbytes = 40, + .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 48, 50, 51, 52, 53, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + /* bytes 0 and 1 are used for the bad block marker */ + { + .offset = 2, + .length = 22 + }, + } +}; + +/** + * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: caller requires OOB data read to chip->oob_poi + * @page: page number to read + * + * Use large block Auto Decode Read Mode(1) as described in User Manual + * section 8.6.2.1. + * + * The initial Read Mode and Read Start commands are sent by the caller. + * + * ECC will be false if out-of-band data has been updated since in-band + * data was initially written. + */ + +static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int oob_required, + int page) +{ + unsigned int i, status, timeout, err, max_bitflips = 0; + struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; + + /* go through all four small pages */ + for (i = 0; i < 4; i++) { + /* start auto decode (reads 528 NAND bytes) */ + writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg); + /* wait for controller to return to ready state */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if (status & ISR_CONTROLLER_READY) + break; + udelay(1); + } + /* if decoder failed, return failure */ + if (status & ISR_DECODER_FAILURE) + return -1; + /* keep count of maximum bitflips performed */ + if (status & ISR_DECODER_ERROR) { + err = ISR_DECODER_ERRORS(status); + if (err > max_bitflips) + max_bitflips = err; + } + /* copy first 512 bytes into buffer */ + memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512); + /* copy next 6 bytes at front of OOB buffer */ + memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6); + /* copy last 10 bytes (R/S ECC) at back of OOB buffer */ + memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10); + } + return max_bitflips; +} + +/** + * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: caller requires OOB data read to chip->oob_poi + * @page: page number to read + * + * Read NAND directly; can read pages with invalid ECC. + */ + +static int lpc32xx_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, int oob_required, + int page) +{ + unsigned int i, status, timeout; + struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; + + /* when we get here we've already had the Read Mode(1) */ + + /* go through all four small pages */ + for (i = 0; i < 4; i++) { + /* wait for NAND to return to ready state */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if (status & ISR_NAND_READY) + break; + udelay(1); + } + /* if NAND stalled, return failure */ + if (!(status & ISR_NAND_READY)) + return -1; + /* copy first 512 bytes into buffer */ + memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512); + /* copy next 6 bytes at front of OOB buffer */ + memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6); + /* copy last 10 bytes (R/S ECC) at back of OOB buffer */ + memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10); + } + return 0; +} + +/** + * lpc32xx_read_oob - read out-of-band data + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to read + * + * Read out-of-band data. User Manual section 8.6.4 suggests using Read + * Mode(3) which the controller will turn into a Read Mode(1) internally + * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0) + * directly. + * + * ECC covers in- and out-of-band data and was written when out-of-band + * data was blank. Therefore, if the out-of-band being read here is not + * blank, then the ECC will be false and the read will return bitflips, + * even in case of ECC failure where we will return 5 bitflips. The + * caller should be prepared to handle this. + */ + +static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + unsigned int i, status, timeout, err, max_bitflips = 0; + struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; + + /* No command was sent before calling read_oob() so send one */ + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + /* go through all four small pages */ + for (i = 0; i < 4; i++) { + /* start auto decode (reads 528 NAND bytes) */ + writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg); + /* wait for controller to return to ready state */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if (status & ISR_CONTROLLER_READY) + break; + udelay(1); + } + /* if decoder failure, count 'one too many' bitflips */ + if (status & ISR_DECODER_FAILURE) + max_bitflips = 5; + /* keep count of maximum bitflips performed */ + if (status & ISR_DECODER_ERROR) { + err = ISR_DECODER_ERRORS(status); + if (err > max_bitflips) + max_bitflips = err; + } + /* set read pointer to OOB area */ + writel(0, &lpc32xx_nand_mlc_registers->robp); + /* copy next 6 bytes at front of OOB buffer */ + memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6); + /* copy next 10 bytes (R/S ECC) at back of OOB buffer */ + memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10); + } + return max_bitflips; +} + +/** + * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * @oob_required: must write chip->oob_poi to OOB + * + * Use large block Auto Encode as per User Manual section 8.6.4. + * + * The initial Write Serial Input and final Auto Program commands are + * sent by the caller. + */ + +static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, int oob_required) +{ + unsigned int i, status, timeout; + struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; + + /* when we get here we've already had the SEQIN */ + for (i = 0; i < 4; i++) { + /* start encode (expects 518 writes to buff) */ + writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg); + /* copy first 512 bytes from buffer */ + memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512); + /* copy next 6 bytes from OOB buffer -- excluding ECC */ + memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6); + /* wait for ECC to return to ready state */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if (status & ISR_ECC_READY) + break; + udelay(1); + } + /* if ECC stalled, return failure */ + if (!(status & ISR_ECC_READY)) + return -1; + /* Trigger auto encode (writes 528 bytes to NAND) */ + writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg); + /* wait for controller to return to ready state */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if (status & ISR_CONTROLLER_READY) + break; + udelay(1); + } + /* if controller stalled, return error */ + if (!(status & ISR_CONTROLLER_READY)) + return -1; + } + return 0; +} + +/** + * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: caller requires OOB data read to chip->oob_poi + * @page: page number to read + * + * Use large block write but without encode. + * + * The initial Write Serial Input and final Auto Program commands are + * sent by the caller. + * + * This function will write the full out-of-band data, including the + * ECC area. Therefore, it can write pages with valid *or* invalid ECC. + */ + +static int lpc32xx_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf, int oob_required) +{ + unsigned int i; + struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; + + /* when we get here we've already had the Read Mode(1) */ + for (i = 0; i < 4; i++) { + /* copy first 512 bytes from buffer */ + memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512); + /* copy next 6 bytes into OOB buffer -- excluding ECC */ + memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6); + /* copy next 10 bytes into OOB buffer -- that is 'ECC' */ + memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10); + } + return 0; +} + +/** + * lpc32xx_write_oob - write out-of-band data + * @mtd: mtd info structure + * @chip: nand chip info structure + * @page: page number to read + * + * Since ECC covers in- and out-of-band data, writing out-of-band data + * with ECC will render the page ECC wrong -- or, if the page was blank, + * then it will produce a good ECC but a later in-band data write will + * render it wrong. + * + * Therefore, do not compute or write any ECC, and always return success. + * + * This implies that we do four writes, since non-ECC out-of-band data + * are not contiguous in a large page. + */ + +static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + /* update oob on all 4 subpages in sequence */ + unsigned int i, status, timeout; + struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; + + for (i = 0; i < 4; i++) { + /* start data input */ + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page); + /* copy 6 non-ECC out-of-band bytes directly into NAND */ + memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6); + /* program page */ + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + /* wait for NAND to return to ready state */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if (status & ISR_NAND_READY) + break; + udelay(1); + } + /* if NAND stalled, return error */ + if (!(status & ISR_NAND_READY)) + return -1; + } + return 0; +} + +/** + * lpc32xx_waitfunc - wait until a command is done + * @mtd: MTD device structure + * @chip: NAND chip structure + * + * Wait for controller and FLASH to both be ready. + */ + +static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) +{ + int status; + unsigned int timeout; + /* wait until both controller and NAND are ready */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY)) + == (ISR_CONTROLLER_READY || ISR_NAND_READY)) + break; + udelay(1); + } + /* if controller or NAND stalled, return error */ + if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY)) + != (ISR_CONTROLLER_READY || ISR_NAND_READY)) + return -1; + /* write NAND status command */ + writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd); + /* read back status and return it */ + return readb(&lpc32xx_nand_mlc_registers->data); +} + +/* + * We are self-initializing, so we need our own chip struct + */ + +static struct nand_chip lpc32xx_chip; + +/* + * Initialize the controller + */ + +void board_nand_init(void) +{ + /* we have only one device anyway */ + struct mtd_info *mtd = &nand_info[0]; + /* chip is struct nand_chip, and is now provided by the driver. */ + mtd->priv = &lpc32xx_chip; + /* to store return status in case we need to print it */ + int ret; + + /* Set all BOARDSPECIFIC (actually core-specific) fields */ + + lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff; + lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff; + lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl; + /* do not set init_size: nand_base.c will read sizes from chip */ + lpc32xx_chip.dev_ready = lpc32xx_dev_ready; + /* do not set setup_read_retry: this is NAND-chip-specific */ + /* do not set chip_delay: we have dev_ready defined. */ + lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE; + + /* Set needed ECC fields */ + + lpc32xx_chip.ecc.mode = NAND_ECC_HW; + lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout; + lpc32xx_chip.ecc.size = 512; + lpc32xx_chip.ecc.bytes = 10; + lpc32xx_chip.ecc.strength = 4; + lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc; + lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw; + lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc; + lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw; + lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob; + lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob; + lpc32xx_chip.waitfunc = lpc32xx_waitfunc; + + lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */ + + /* BBT options: read from last two pages */ + lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK + | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE + | NAND_BBT_WRITE; + + /* Initialize NAND interface */ + lpc32xx_nand_init(); + + /* identify chip */ + ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL); + if (ret) { + error("nand_scan_ident returned %i", ret); + return; + } + + /* finish scanning the chip */ + ret = nand_scan_tail(mtd); + if (ret) { + error("nand_scan_tail returned %i", ret); + return; + } + + /* chip is good, register it */ + ret = nand_register(0); + if (ret) + error("nand_register returned %i", ret); +} + +#else /* defined(CONFIG_SPL_BUILD) */ + +void nand_init(void) +{ + /* enable NAND controller */ + lpc32xx_mlc_nand_init(); + /* initialize NAND controller */ + lpc32xx_nand_init(); +} + +void nand_deselect(void) +{ + /* nothing to do, but SPL requires this function */ +} + +static int read_single_page(uint8_t *dest, int page, + struct lpc32xx_oob *oob) +{ + int status, i, timeout, err, max_bitflips = 0; + + /* enter read mode */ + writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd); + /* send column (lsb then MSB) and page (lsb to MSB) */ + writel(0, &lpc32xx_nand_mlc_registers->addr); + writel(0, &lpc32xx_nand_mlc_registers->addr); + writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr); + writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr); + writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr); + /* start reading */ + writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd); + + /* large page auto decode read */ + for (i = 0; i < 4; i++) { + /* start auto decode (reads 528 NAND bytes) */ + writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg); + /* wait for controller to return to ready state */ + for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { + status = readl(&lpc32xx_nand_mlc_registers->isr); + if (status & ISR_CONTROLLER_READY) + break; + udelay(1); + } + /* if controller stalled, return error */ + if (!(status & ISR_CONTROLLER_READY)) + return -1; + /* if decoder failure, return error */ + if (status & ISR_DECODER_FAILURE) + return -1; + /* keep count of maximum bitflips performed */ + if (status & ISR_DECODER_ERROR) { + err = ISR_DECODER_ERRORS(status); + if (err > max_bitflips) + max_bitflips = err; + } + /* copy first 512 bytes into buffer */ + memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512); + /* copy next 6 bytes bytes into OOB buffer */ + memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6); + } + return max_bitflips; +} + +/* + * Load U-Boot signed image. + * This loads an image from NAND, skipping bad blocks. + * A block is declared bad if at least one of its readable pages has + * a bad block marker in its OOB at position 0. + * If all pages ion a block are unreadable, the block is considered + * bad (i.e., assumed not to be part of the image) and skipped. + * + * IMPORTANT NOTE: + * + * If the first block of the image is fully unreadable, it will be + * ignored and skipped as if it had been marked bad. If it was not + * actually marked bad at the time of writing the image, the resulting + * image loaded will lack a header and magic number. It could thus be + * considered as a raw, headerless, image and SPL might erroneously + * jump into it. + * + * In order to avoid this risk, LPC32XX-based boards which use this + * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE. + */ + +#define BYTES_PER_PAGE 2048 +#define PAGES_PER_BLOCK 64 +#define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK) +#define PAGES_PER_CHIP_MAX 524288 + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + int bytes_left = size; + int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE); + int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK); + int block = 0; + int page = offs / BYTES_PER_PAGE; + /* perform reads block by block */ + while (blocks_left) { + /* compute first page number to read */ + void *block_page_dst = dst; + /* read at most one block, possibly less */ + int block_bytes_left = bytes_left; + if (block_bytes_left > BYTES_PER_BLOCK) + block_bytes_left = BYTES_PER_BLOCK; + /* keep track of good, failed, and "bad" pages */ + int block_pages_good = 0; + int block_pages_bad = 0; + int block_pages_err = 0; + /* we shall read a full block of pages, maybe less */ + int block_pages_left = pages_left; + if (block_pages_left > PAGES_PER_BLOCK) + block_pages_left = PAGES_PER_BLOCK; + int block_pages = block_pages_left; + int block_page = page; + /* while pages are left and the block is not known as bad */ + while ((block_pages > 0) && (block_pages_bad == 0)) { + /* we will read OOB, too, for bad block markers */ + struct lpc32xx_oob oob; + /* read page */ + int res = read_single_page(block_page_dst, block_page, + &oob); + /* count readable pages */ + if (res >= 0) { + /* this page is good */ + block_pages_good++; + /* this page is bad */ + if ((oob.free[0].free_oob_bytes[0] != 0xff) + | (oob.free[0].free_oob_bytes[1] != 0xff)) + block_pages_bad++; + } else + /* count errors */ + block_pages_err++; + /* we're done with this page */ + block_page++; + block_page_dst += BYTES_PER_PAGE; + if (block_pages) + block_pages--; + } + /* a fully unreadable block is considered bad */ + if (block_pages_good == 0) + block_pages_bad = block_pages_err; + /* errors are fatal only in good blocks */ + if ((block_pages_err > 0) && (block_pages_bad == 0)) + return -1; + /* we keep reads only of good blocks */ + if (block_pages_bad == 0) { + dst += block_bytes_left; + bytes_left -= block_bytes_left; + pages_left -= block_pages_left; + blocks_left--; + } + /* good or bad, we're done with this block */ + block++; + page += PAGES_PER_BLOCK; + } + + /* report success */ + return 0; +} + +#endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index 7233bfc127..e621c3665e 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -459,29 +459,6 @@ static void mpc5121_nfc_write_buf(struct mtd_info *mtd, mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* Compare buffer with NAND flash */ -static int mpc5121_nfc_verify_buf(struct mtd_info *mtd, - const u_char * buf, int len) -{ - u_char tmp[256]; - uint bsize; - - while (len) { - bsize = min(len, 256); - mpc5121_nfc_read_buf(mtd, tmp, bsize); - - if (memcmp(buf, tmp, bsize)) - return 1; - - buf += bsize; - len -= bsize; - } - - return 0; -} -#endif - /* Read byte from NFC buffers */ static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd) { @@ -609,9 +586,6 @@ int board_nand_init(struct nand_chip *chip) chip->read_word = mpc5121_nfc_read_word; chip->read_buf = mpc5121_nfc_read_buf; chip->write_buf = mpc5121_nfc_write_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - chip->verify_buf = mpc5121_nfc_verify_buf; -#endif chip->select_chip = mpc5121_nfc_select_chip; chip->bbt_options = NAND_BBT_USE_FLASH; chip->ecc.mode = NAND_ECC_SOFT; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 2e5b5b9bf9..f12b07e7ad 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -949,34 +949,6 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) host->col_addr = col; } -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* - * Used by the upper layer to verify the data in NAND Flash - * with the data in the buf. - */ -static int mxc_nand_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - u_char tmp[256]; - uint bsize; - - while (len) { - bsize = min(len, 256); - mxc_nand_read_buf(mtd, tmp, bsize); - - if (memcmp(buf, tmp, bsize)) - return 1; - - buf += bsize; - len -= bsize; - } - - return 0; -} -#endif -#endif - /* * This function is used by upper layer for select and * deselect of the NAND chip @@ -1207,11 +1179,6 @@ int board_nand_init(struct nand_chip *this) this->read_word = mxc_nand_read_word; this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - this->verify_buf = mxc_nand_verify_buf; -#endif -#endif host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 7a064ab1bf..2d2b938633 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -453,7 +453,7 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) d->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM | - MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET); + MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); d->cmd.address = 0; @@ -510,7 +510,7 @@ static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, d->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | - (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | + (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | (length << MXS_DMA_DESC_BYTES_OFFSET); d->cmd.address = (dma_addr_t)nand_info->data_buf; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6db6566e73..c0e381ad2d 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -361,51 +361,6 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ioread8_rep(chip->IO_ADDR_R, buf, len); } -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/** - * nand_verify_buf - [DEFAULT] Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * Default verify function for 8bit buswidth. - */ -static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - - for (i = 0; i < len; i++) - if (buf[i] != readb(chip->IO_ADDR_R)) - return -EFAULT; - return 0; -} - -/** - * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * Default verify function for 16bit buswidth. - */ -static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - u16 *p = (u16 *) buf; - len >>= 1; - - for (i = 0; i < len; i++) - if (p[i] != readw(chip->IO_ADDR_R)) - return -EFAULT; - - return 0; -} -#endif -#endif - /** * nand_write_buf16 - [DEFAULT] write buffer to chip * @mtd: MTD device structure @@ -2435,20 +2390,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, status = chip->waitfunc(mtd, chip); } - -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - /* Send command to read back the data */ - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - - if (chip->verify_buf(mtd, buf, mtd->writesize)) - return -EIO; - - /* Make sure the next page prog is preceded by a status read */ - chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); -#endif -#endif - return 0; } @@ -3139,12 +3080,6 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - if (!chip->verify_buf) - chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; -#endif -#endif if (!chip->controller) { chip->controller = &chip->hwcontrol; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index afdd160d81..12dd26a33f 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -464,6 +464,87 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, #endif /** + * nand_verify_page_oob: + * + * Verify a page of NAND flash, including the OOB. + * Reads page of NAND and verifies the contents and OOB against the + * values in ops. + * + * @param nand NAND device + * @param ops MTD operations, including data to verify + * @param ofs offset in flash + * @return 0 in case of success + */ +int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs) +{ + int rval; + struct mtd_oob_ops vops; + size_t verlen = nand->writesize + nand->oobsize; + + memcpy(&vops, ops, sizeof(vops)); + + vops.datbuf = malloc(verlen); + + if (!vops.datbuf) + return -ENOMEM; + + vops.oobbuf = vops.datbuf + nand->writesize; + + rval = mtd_read_oob(nand, ofs, &vops); + if (!rval) + rval = memcmp(ops->datbuf, vops.datbuf, vops.len); + if (!rval) + rval = memcmp(ops->oobbuf, vops.oobbuf, vops.ooblen); + + free(vops.datbuf); + + return rval ? -EIO : 0; +} + +/** + * nand_verify: + * + * Verify a region of NAND flash. + * Reads NAND in page-sized chunks and verifies the contents against + * the contents of a buffer. The offset into the NAND must be + * page-aligned, and the function doesn't handle skipping bad blocks. + * + * @param nand NAND device + * @param ofs offset in flash + * @param len buffer length + * @param buf buffer to read from + * @return 0 in case of success + */ +int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf) +{ + int rval = 0; + size_t verofs; + size_t verlen = nand->writesize; + uint8_t *verbuf = malloc(verlen); + + if (!verbuf) + return -ENOMEM; + + /* Read the NAND back in page-size groups to limit malloc size */ + for (verofs = ofs; verofs < ofs + len; + verofs += verlen, buf += verlen) { + verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs)); + rval = nand_read(nand, verofs, &verlen, verbuf); + if (!rval || (rval == -EUCLEAN)) + rval = memcmp(buf, verbuf, verlen); + + if (rval) + break; + } + + free(verbuf); + + return rval ? -EIO : 0; +} + + + +/** * nand_write_skip_bad: * * Write image to NAND flash. @@ -499,24 +580,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, if (actual) *actual = 0; -#ifdef CONFIG_CMD_NAND_YAFFS - if (flags & WITH_YAFFS_OOB) { - if (flags & ~WITH_YAFFS_OOB) - return -EINVAL; - - int pages; - pages = nand->erasesize / nand->writesize; - blocksize = (pages * nand->oobsize) + nand->erasesize; - if (*length % (nand->writesize + nand->oobsize)) { - printf("Attempt to write incomplete page" - " in yaffs mode\n"); - return -EINVAL; - } - } else -#endif - { - blocksize = nand->erasesize; - } + blocksize = nand->erasesize; /* * nand_write() handles unaligned, partial page writes. @@ -554,6 +618,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, if (!need_skip && !(flags & WITH_DROP_FFS)) { rval = nand_write(nand, offset, length, buffer); + + if ((flags & WITH_WR_VERIFY) && !rval) + rval = nand_verify(nand, offset, *length, buffer); + if (rval == 0) return 0; @@ -581,48 +649,22 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, else write_size = blocksize - block_offset; -#ifdef CONFIG_CMD_NAND_YAFFS - if (flags & WITH_YAFFS_OOB) { - int page, pages; - size_t pagesize = nand->writesize; - size_t pagesize_oob = pagesize + nand->oobsize; - struct mtd_oob_ops ops; - - ops.len = pagesize; - ops.ooblen = nand->oobsize; - ops.mode = MTD_OPS_AUTO_OOB; - ops.ooboffs = 0; - - pages = write_size / pagesize_oob; - for (page = 0; page < pages; page++) { - WATCHDOG_RESET(); - - ops.datbuf = p_buffer; - ops.oobbuf = ops.datbuf + pagesize; - - rval = mtd_write_oob(nand, offset, &ops); - if (rval != 0) - break; - - offset += pagesize; - p_buffer += pagesize_oob; - } - } - else -#endif - { - truncated_write_size = write_size; + truncated_write_size = write_size; #ifdef CONFIG_CMD_NAND_TRIMFFS - if (flags & WITH_DROP_FFS) - truncated_write_size = drop_ffs(nand, p_buffer, - &write_size); + if (flags & WITH_DROP_FFS) + truncated_write_size = drop_ffs(nand, p_buffer, + &write_size); #endif - rval = nand_write(nand, offset, &truncated_write_size, - p_buffer); - offset += write_size; - p_buffer += write_size; - } + rval = nand_write(nand, offset, &truncated_write_size, + p_buffer); + + if ((flags & WITH_WR_VERIFY) && !rval) + rval = nand_verify(nand, offset, + truncated_write_size, p_buffer); + + offset += write_size; + p_buffer += write_size; if (rval != 0) { printf("NAND write to offset %llx failed %d\n", diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 265959502d..8a68cb0a67 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -118,21 +118,6 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len out_be32((u32 *)(base + NDFC_DATA), *p++); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - uint32_t *p = (uint32_t *) buf; - - for (; len > 0; len -= 4) - if (*p++ != in_be32((u32 *)(base + NDFC_DATA))) - return -1; - - return 0; -} -#endif - /* * Read a byte from the NDFC. */ @@ -207,9 +192,6 @@ int board_nand_init(struct nand_chip *nand) #endif nand->write_buf = ndfc_write_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = ndfc_verify_buf; -#endif nand->read_byte = ndfc_read_byte; chip++; diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 928d58b3a7..d98dd28800 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -146,6 +146,7 @@ struct vf610_nfc { void __iomem *regs; uint column; int spareonly; + int page_sz; int page; /* Status and ID are in alternate locations. */ int alt_buf; @@ -329,6 +330,11 @@ static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) ROW_ADDR_SHIFT, page); } +static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) +{ + __raw_writel(size, regbase + NFC_SECTOR_SIZE); +} + /* Send command to NAND chip */ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, int column, int page) @@ -342,12 +348,14 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, switch (command) { case NAND_CMD_PAGEPROG: nfc->page = -1; + vf610_nfc_transfer_size(nfc->regs, nfc->page_sz); vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, command, PROGRAM_PAGE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); break; case NAND_CMD_RESET: + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE); break; /* @@ -363,14 +371,15 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, if (nfc->page == page) return; nfc->page = page; + vf610_nfc_transfer_size(nfc->regs, nfc->page_sz); vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, NAND_CMD_READSTART, READ_PAGE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); break; case NAND_CMD_ERASE1: - if (nfc->page == page) - nfc->page = -1; + nfc->page = -1; + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_commands(nfc->regs, command, NAND_CMD_ERASE2, ERASE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); @@ -378,11 +387,13 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_READID: nfc->alt_buf = ALT_BUF_ID; + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE); break; case NAND_CMD_STATUS: nfc->alt_buf = ALT_BUF_STAT; + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE); break; @@ -580,7 +591,6 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) struct nand_chip *chip; struct vf610_nfc *nfc; int err = 0; - int page_sz; struct vf610_nfc_config cfg = { .hardware_ecc = 1, #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT @@ -634,9 +644,8 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) chip->bbt_td = &bbt_main_descr; chip->bbt_md = &bbt_mirror_descr; - page_sz = PAGE_2K + OOB_64; - page_sz += cfg.width == 16 ? 1 : 0; - vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + nfc->page_sz = PAGE_2K + OOB_64; + nfc->page_sz += cfg.width == 16 ? 1 : 0; /* Set configuration register. */ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); @@ -665,16 +674,15 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) chip->ecc.mode = NAND_ECC_SOFT; /* default */ - page_sz = mtd->writesize + mtd->oobsize; + nfc->page_sz = mtd->writesize + mtd->oobsize; /* Single buffer only, max 256 OOB minus ECC status */ - if (page_sz > PAGE_2K + 256 - 8) { + if (nfc->page_sz > PAGE_2K + 256 - 8) { dev_err(nfc->dev, "Unsupported flash size\n"); err = -ENXIO; goto error; } - page_sz += cfg.width == 16 ? 1 : 0; - vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + nfc->page_sz += cfg.width == 16 ? 1 : 0; if (cfg.hardware_ecc) { if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b8b08034eb..5a5269aa06 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_GRETH) += greth.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o +obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o @@ -46,6 +47,7 @@ obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o obj-$(CONFIG_NETCONSOLE) += netconsole.o obj-$(CONFIG_NS8382X) += ns8382x.o +obj-$(CONFIG_PCH_GBE) += pch_gbe.o obj-$(CONFIG_PCNET) += pcnet.o obj-$(CONFIG_RTL8139) += rtl8139.o obj-$(CONFIG_RTL8169) += rtl8169.o diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 6d110eb5d5..f3b77b1d97 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -430,12 +430,11 @@ struct e1000_phy_stats { #define ENET_HEADER_SIZE 14 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ -#define ETHERNET_FCS_SIZE 4 #define MAXIMUM_ETHERNET_PACKET_SIZE \ - (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) + (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) #define MINIMUM_ETHERNET_PACKET_SIZE \ - (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) -#define CRC_LENGTH ETHERNET_FCS_SIZE + (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) +#define CRC_LENGTH ETH_FCS_LEN #define MAX_JUMBO_FRAME_SIZE 0x3F00 /* 802.1q VLAN Packet Sizes */ diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c new file mode 100644 index 0000000000..fcadf0c77f --- /dev/null +++ b/drivers/net/lpc32xx_eth.c @@ -0,0 +1,637 @@ +/* + * LPC32xx Ethernet MAC interface driver + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/types.h> +#include <asm/system.h> +#include <asm/byteorder.h> +#include <asm/arch/cpu.h> +#include <asm/arch/config.h> + +/* + * Notes: + * + * 1. Unless specified otherwise, all references to tables or paragraphs + * are to UM10326, "LPC32x0 and LPC32x0/01 User manual". + * + * 2. Only bitfield masks/values which are actually used by the driver + * are defined. + */ + +/* a single RX descriptor. The controller has an array of these */ +struct lpc32xx_eth_rxdesc { + u32 packet; /* Receive packet pointer */ + u32 control; /* Descriptor command status */ +}; + +#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc)) + +/* RX control bitfields/masks (see Table 330) */ +#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF +#define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800 +#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000 + +/* a single RX status. The controller has an array of these */ +struct lpc32xx_eth_rxstat { + u32 statusinfo; /* Transmit Descriptor status */ + u32 statushashcrc; /* Transmit Descriptor CRCs */ +}; + +#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat)) + +/* RX statusinfo bitfields/masks (see Table 333) */ +#define RX_STAT_RXSIZE 0x000007FF +/* Helper: OR of all errors except RANGE */ +#define RX_STAT_ERRORS 0x1B800000 + +/* a single TX descriptor. The controller has an array of these */ +struct lpc32xx_eth_txdesc { + u32 packet; /* Transmit packet pointer */ + u32 control; /* Descriptor control */ +}; + +#define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc)) + +/* TX control bitfields/masks (see Table 335) */ +#define TX_CTRL_TXSIZE 0x000007FF +#define TX_CTRL_LAST 0x40000000 + +/* a single TX status. The controller has an array of these */ +struct lpc32xx_eth_txstat { + u32 statusinfo; /* Transmit Descriptor status */ +}; + +#define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat)) + +/* Ethernet MAC interface registers (see Table 283) */ +struct lpc32xx_eth_registers { + /* MAC registers - 0x3106_0000 to 0x3106_01FC */ + u32 mac1; /* MAC configuration register 1 */ + u32 mac2; /* MAC configuration register 2 */ + u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */ + u32 ipgr; /* Non-back-to-back IPG register */ + u32 clrt; /* Collision Window / Retry register */ + u32 maxf; /* Maximum Frame register */ + u32 supp; /* Phy Support register */ + u32 test; + u32 mcfg; /* MII management configuration reg. */ + u32 mcmd; /* MII management command register */ + u32 madr; /* MII management address register */ + u32 mwtd; /* MII management wite data register */ + u32 mrdd; /* MII management read data register */ + u32 mind; /* MII management indicators register */ + u32 reserved1[2]; + u32 sa0; /* Station address register 0 */ + u32 sa1; /* Station address register 1 */ + u32 sa2; /* Station address register 2 */ + u32 reserved2[45]; + /* Control registers */ + u32 command; + u32 status; + u32 rxdescriptor; + u32 rxstatus; + u32 rxdescriptornumber; /* actually, number MINUS ONE */ + u32 rxproduceindex; /* head of rx desc fifo */ + u32 rxconsumeindex; /* tail of rx desc fifo */ + u32 txdescriptor; + u32 txstatus; + u32 txdescriptornumber; /* actually, number MINUS ONE */ + u32 txproduceindex; /* head of rx desc fifo */ + u32 txconsumeindex; /* tail of rx desc fifo */ + u32 reserved3[10]; + u32 tsv0; /* Transmit status vector register 0 */ + u32 tsv1; /* Transmit status vector register 1 */ + u32 rsv; /* Receive status vector register */ + u32 reserved4[3]; + u32 flowcontrolcounter; + u32 flowcontrolstatus; + u32 reserved5[34]; + /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */ + u32 rxfilterctrl; + u32 rxfilterwolstatus; + u32 rxfilterwolclear; + u32 reserved6; + u32 hashfilterl; + u32 hashfilterh; + u32 reserved7[882]; + /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */ + u32 intstatus; /* Interrupt status register */ + u32 intenable; + u32 intclear; + u32 intset; + u32 reserved8; + u32 powerdown; + u32 reserved9; +}; + +/* MAC1 register bitfields/masks and offsets (see Table 283) */ +#define MAC1_RECV_ENABLE 0x00000001 +#define MAC1_PASS_ALL_RX_FRAMES 0x00000002 +#define MAC1_SOFT_RESET 0x00008000 +/* Helper: general reset */ +#define MAC1_RESETS 0x0000CF00 + +/* MAC2 register bitfields/masks and offsets (see Table 284) */ +#define MAC2_FULL_DUPLEX 0x00000001 +#define MAC2_CRC_ENABLE 0x00000010 +#define MAC2_PAD_CRC_ENABLE 0x00000020 + +/* SUPP register bitfields/masks and offsets (see Table 290) */ +#define SUPP_SPEED 0x00000100 + +/* MCFG register bitfields/masks and offsets (see Table 292) */ +#define MCFG_CLOCK_SELECT_MASK 0x0000001C +/* divide clock by 28 (see Table 293) */ +#define MCFG_CLOCK_SELECT_DIV28 0x0000001C + +/* MADR register bitfields/masks and offsets (see Table 295) */ +#define MADR_REG_MASK 0x0000001F +#define MADR_PHY_MASK 0x00001F00 +#define MADR_REG_OFFSET 0 +#define MADR_PHY_OFFSET 8 + +/* MIND register bitfields/masks (see Table 298) */ +#define MIND_BUSY 0x00000001 + +/* COMMAND register bitfields/masks and offsets (see Table 283) */ +#define COMMAND_RXENABLE 0x00000001 +#define COMMAND_TXENABLE 0x00000002 +#define COMMAND_PASSRUNTFRAME 0x00000040 +#define COMMAND_FULL_DUPLEX 0x00000400 +/* Helper: general reset */ +#define COMMAND_RESETS 0x0000001C + +/* STATUS register bitfields/masks and offsets (see Table 283) */ +#define STATUS_RXSTATUS 0x00000001 +#define STATUS_TXSTATUS 0x00000002 + +/* RXFILTERCTRL register bitfields/masks (see Table 319) */ +#define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002 +#define RXFILTERCTRL_ACCEPTPERFECT 0x00000020 + +/* Buffers and descriptors */ + +#define ATTRS(n) __aligned(n) + +#define TX_BUF_COUNT 4 +#define RX_BUF_COUNT 4 + +struct lpc32xx_eth_buffers { + ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT]; + ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT]; + ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN]; + ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT]; + ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT]; + ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN]; +}; + +/* port device data struct */ +struct lpc32xx_eth_device { + struct eth_device dev; + struct lpc32xx_eth_registers *regs; + struct lpc32xx_eth_buffers *bufs; +}; + +#define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device)) + +/* generic macros */ +#define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev) + +/* timeout for MII polling */ +#define MII_TIMEOUT 10000000 + +/* limits for PHY and register addresses */ +#define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET) + +#define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET) + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +/* + * mii_reg_read - miiphy_read callback function. + * + * Returns 16bit phy register value, or 0xffff on error + */ +static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); + struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; + u32 mind_reg; + u32 timeout; + + /* check parameters */ + if (phy_adr > MII_MAX_PHY) { + printf("%s:%u: Invalid PHY address %d\n", + __func__, __LINE__, phy_adr); + return -EFAULT; + } + if (reg_ofs > MII_MAX_REG) { + printf("%s:%u: Invalid register offset %d\n", + __func__, __LINE__, reg_ofs); + return -EFAULT; + } + + /* write the phy and reg addressse into the MII address reg */ + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), + ®s->madr); + + /* write 1 to the MII command register to cause a read */ + writel(1, ®s->mcmd); + + /* wait till the MII is not busy */ + timeout = MII_TIMEOUT; + do { + /* read MII indicators register */ + mind_reg = readl(®s->mind); + if (--timeout == 0) + break; + } while (mind_reg & MIND_BUSY); + + /* write 0 to the MII command register to finish the read */ + writel(0, ®s->mcmd); + + if (timeout == 0) { + printf("%s:%u: MII busy timeout\n", __func__, __LINE__); + return -EFAULT; + } + + *data = (u16) readl(®s->mrdd); + + debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, + reg_ofs, *data); + + return 0; +} + +/* + * mii_reg_write - imiiphy_write callback function. + * + * Returns 0 if write succeed, -EINVAL on bad parameters + * -ETIME on timeout + */ +static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); + struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; + u32 mind_reg; + u32 timeout; + + /* check parameters */ + if (phy_adr > MII_MAX_PHY) { + printf("%s:%u: Invalid PHY address %d\n", + __func__, __LINE__, phy_adr); + return -EFAULT; + } + if (reg_ofs > MII_MAX_REG) { + printf("%s:%u: Invalid register offset %d\n", + __func__, __LINE__, reg_ofs); + return -EFAULT; + } + + /* wait till the MII is not busy */ + timeout = MII_TIMEOUT; + do { + /* read MII indicators register */ + mind_reg = readl(®s->mind); + if (--timeout == 0) + break; + } while (mind_reg & MIND_BUSY); + + if (timeout == 0) { + printf("%s:%u: MII busy timeout\n", __func__, + __LINE__); + return -EFAULT; + } + + /* write the phy and reg addressse into the MII address reg */ + writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET), + ®s->madr); + + /* write data to the MII write register */ + writel(data, ®s->mwtd); + + /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr, + reg_ofs, data);*/ + + return 0; +} +#endif + +#if defined(CONFIG_PHYLIB) +int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr) +{ + u16 data; + int ret; + ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data); + if (ret) + return ret; + return data; +} + +int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, + int reg_addr, u16 data) +{ + return mii_reg_write(bus->name, phy_addr, reg_addr, data); +} +#endif + +/* + * Locate buffers in SRAM at 0x00001000 to avoid cache issues and + * maximize throughput. + */ + +#define LPC32XX_ETH_BUFS 0x00001000 + +static struct lpc32xx_eth_device lpc32xx_eth = { + .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE, + .bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS +}; + +#define TX_TIMEOUT 10000 + +static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; + int timeout, tx_index; + + /* time out if transmit descriptor array remains full too long */ + timeout = TX_TIMEOUT; + while ((readl(®s->status) & STATUS_TXSTATUS) && + (readl(®s->txconsumeindex) + == readl(®s->txproduceindex))) { + if (timeout-- == 0) + return -1; + } + + /* determine next transmit packet index to use */ + tx_index = readl(®s->txproduceindex); + + /* set up transmit packet */ + writel((u32)dataptr, &bufs->tx_desc[tx_index].packet); + writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), + &bufs->tx_desc[tx_index].control); + writel(0, &bufs->tx_stat[tx_index].statusinfo); + + /* pass transmit packet to DMA engine */ + tx_index = (tx_index + 1) % TX_BUF_COUNT; + writel(tx_index, ®s->txproduceindex); + + /* transmission succeeded */ + return 0; +} + +#define RX_TIMEOUT 1000000 + +static int lpc32xx_eth_recv(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; + int timeout, rx_index; + + /* time out if receive descriptor array remains empty too long */ + timeout = RX_TIMEOUT; + while (readl(®s->rxproduceindex) == readl(®s->rxconsumeindex)) { + if (timeout-- == 0) + return -1; + } + + /* determine next receive packet index to use */ + rx_index = readl(®s->rxconsumeindex); + + /* if data was valid, pass it on */ + if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) + NetReceive(&(bufs->rx_buf[rx_index*PKTSIZE_ALIGN]), + (bufs->rx_stat[rx_index].statusinfo + & RX_STAT_RXSIZE) + 1); + + /* pass receive slot back to DMA engine */ + rx_index = (rx_index + 1) % RX_BUF_COUNT; + writel(rx_index, ®s->rxconsumeindex); + + /* reception successful */ + return 0; +} + +static int lpc32xx_eth_write_hwaddr(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + + /* Save station address */ + writel((unsigned long) (dev->enetaddr[0] | + (dev->enetaddr[1] << 8)), ®s->sa2); + writel((unsigned long) (dev->enetaddr[2] | + (dev->enetaddr[3] << 8)), ®s->sa1); + writel((unsigned long) (dev->enetaddr[4] | + (dev->enetaddr[5] << 8)), ®s->sa0); + + return 0; +} + +static int lpc32xx_eth_init(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs; + int index; + + /* Release SOFT reset to let MII talk to PHY */ + clrbits_le32(®s->mac1, MAC1_SOFT_RESET); + + /* Configure Full/Half Duplex mode */ + if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) { + setbits_le32(®s->mac2, MAC2_FULL_DUPLEX); + setbits_le32(®s->command, COMMAND_FULL_DUPLEX); + writel(0x15, ®s->ipgt); + } else { + writel(0x12, ®s->ipgt); + } + + /* Configure 100MBit/10MBit mode */ + if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET) + writel(SUPP_SPEED, ®s->supp); + else + writel(0, ®s->supp); + + /* Initial MAC initialization */ + writel(MAC1_PASS_ALL_RX_FRAMES, ®s->mac1); + writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, ®s->mac2); + writel(PKTSIZE_ALIGN, ®s->maxf); + + /* Retries: 15 (0xF). Collision window: 57 (0x37). */ + writel(0x370F, ®s->clrt); + + /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */ + writel(0x0012, ®s->ipgr); + + /* pass runt (smaller than 64 bytes) frames */ + writel(COMMAND_PASSRUNTFRAME, ®s->command); + + /* Save station address */ + writel((unsigned long) (dev->enetaddr[0] | + (dev->enetaddr[1] << 8)), ®s->sa2); + writel((unsigned long) (dev->enetaddr[2] | + (dev->enetaddr[3] << 8)), ®s->sa1); + writel((unsigned long) (dev->enetaddr[4] | + (dev->enetaddr[5] << 8)), ®s->sa0); + + /* set up transmit buffers */ + for (index = 0; index < TX_BUF_COUNT; index++) { + bufs->tx_desc[index].control = 0; + bufs->tx_stat[index].statusinfo = 0; + } + writel((u32)(&bufs->tx_desc), (u32 *)®s->txdescriptor); + writel((u32)(&bufs->tx_stat), ®s->txstatus); + writel(TX_BUF_COUNT-1, ®s->txdescriptornumber); + + /* set up receive buffers */ + for (index = 0; index < RX_BUF_COUNT; index++) { + bufs->rx_desc[index].packet = + (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN); + bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1; + bufs->rx_stat[index].statusinfo = 0; + bufs->rx_stat[index].statushashcrc = 0; + } + writel((u32)(&bufs->rx_desc), ®s->rxdescriptor); + writel((u32)(&bufs->rx_stat), ®s->rxstatus); + writel(RX_BUF_COUNT-1, ®s->rxdescriptornumber); + + /* Enable broadcast and matching address packets */ + writel(RXFILTERCTRL_ACCEPTBROADCAST | + RXFILTERCTRL_ACCEPTPERFECT, ®s->rxfilterctrl); + + /* Clear and disable interrupts */ + writel(0xFFFF, ®s->intclear); + writel(0, ®s->intenable); + + /* Enable receive and transmit mode of MAC ethernet core */ + setbits_le32(®s->command, COMMAND_RXENABLE | COMMAND_TXENABLE); + setbits_le32(®s->mac1, MAC1_RECV_ENABLE); + + /* + * Perform a 'dummy' first send to work around Ethernet.1 + * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011). + * Use zeroed "index" variable as the dummy. + */ + + index = 0; + lpc32xx_eth_send(dev, &index, 4); + + return 0; +} + +static int lpc32xx_eth_halt(struct eth_device *dev) +{ + struct lpc32xx_eth_device *lpc32xx_eth_device = + container_of(dev, struct lpc32xx_eth_device, dev); + struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs; + + /* Reset all MAC logic */ + writel(MAC1_RESETS, ®s->mac1); + writel(COMMAND_RESETS, ®s->command); + /* Let reset condition settle */ + udelay(2000); + + return 0; +} + +#if defined(CONFIG_PHYLIB) +int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) +{ + struct mii_dev *bus; + struct phy_device *phydev; + int ret; + + bus = mdio_alloc(); + if (!bus) { + printf("mdio_alloc failed\n"); + return -ENOMEM; + } + bus->read = lpc32xx_eth_phy_read; + bus->write = lpc32xx_eth_phy_write; + sprintf(bus->name, dev->name); + + ret = mdio_register(bus); + if (ret) { + printf("mdio_register failed\n"); + free(bus); + return -ENOMEM; + } + + phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII); + if (!phydev) { + printf("phy_connect failed\n"); + return -ENODEV; + } + + phy_config(phydev); + phy_startup(phydev); + + return 0; +} +#endif + +int lpc32xx_eth_initialize(bd_t *bis) +{ + struct eth_device *dev = &lpc32xx_eth.dev; + struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs; + + /* + * Set RMII management clock rate. With HCLK at 104 MHz and + * a divider of 28, this will be 3.72 MHz. + */ + + writel(MCFG_CLOCK_SELECT_DIV28, ®s->mcfg); + + /* Reset all MAC logic */ + writel(MAC1_RESETS, ®s->mac1); + writel(COMMAND_RESETS, ®s->command); + + /* wait 10 ms for the whole I/F to reset */ + udelay(10000); + + /* must be less than sizeof(dev->name) */ + strcpy(dev->name, "eth0"); + + dev->init = (void *)lpc32xx_eth_init; + dev->halt = (void *)lpc32xx_eth_halt; + dev->send = (void *)lpc32xx_eth_send; + dev->recv = (void *)lpc32xx_eth_recv; + dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr; + + /* Release SOFT reset to let MII talk to PHY */ + clrbits_le32(®s->mac1, MAC1_SOFT_RESET); + + /* register driver before talking to phy */ + eth_register(dev); + +#if defined(CONFIG_PHYLIB) + lpc32xx_eth_phylib_init(dev, 0); +#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, mii_reg_read, mii_reg_write); +#endif + + return 0; +} diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c new file mode 100644 index 0000000000..976848df4d --- /dev/null +++ b/drivers/net/pch_gbe.c @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <pci.h> +#include <malloc.h> +#include <miiphy.h> +#include "pch_gbe.h" + +#if !defined(CONFIG_PHYLIB) +# error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE }, + { } +}; + +static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr) +{ + u32 macid_hi, macid_lo; + + macid_hi = readl(&mac_regs->mac_adr[0].high); + macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff; + debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo); + + addr[0] = (u8)(macid_hi & 0xff); + addr[1] = (u8)((macid_hi >> 8) & 0xff); + addr[2] = (u8)((macid_hi >> 16) & 0xff); + addr[3] = (u8)((macid_hi >> 24) & 0xff); + addr[4] = (u8)(macid_lo & 0xff); + addr[5] = (u8)((macid_lo >> 8) & 0xff); +} + +static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr) +{ + u32 macid_hi, macid_lo; + ulong start; + + macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24); + macid_lo = addr[4] + (addr[5] << 8); + + writel(macid_hi, &mac_regs->mac_adr[0].high); + writel(macid_lo, &mac_regs->mac_adr[0].low); + writel(0xfffe, &mac_regs->addr_mask); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY)) + return 0; + + udelay(10); + } + + return -ETIME; +} + +static int pch_gbe_reset(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + ulong start; + + priv->rx_idx = 0; + priv->tx_idx = 0; + + writel(PCH_GBE_ALL_RST, &mac_regs->reset); + + /* + * Configure the MAC to RGMII mode after reset + * + * For some unknown reason, we must do the configuration here right + * after resetting the whole MAC, otherwise the reset bit in the RESET + * register will never be cleared by the hardware. And there is another + * way of having the same magic, that is to configure the MODE register + * to have the MAC work in MII/GMII mode, which is how current Linux + * pch_gbe driver does. Since anyway we need program the MAC to RGMII + * mode in the driver, we just do it here. + * + * Note: this behavior is not documented in the hardware manual. + */ + writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL, + &mac_regs->rgmii_ctrl); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) { + /* + * Soft reset clears hardware MAC address registers, + * so we have to reload MAC address here in order to + * make linux pch_gbe driver happy. + */ + return pch_gbe_mac_write(mac_regs, dev->enetaddr); + } + + udelay(10); + } + + debug("pch_gbe: reset timeout\n"); + return -ETIME; +} + +static void pch_gbe_rx_descs_init(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0]; + int i; + + memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM); + for (i = 0; i < PCH_GBE_DESC_NUM; i++) + rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, + (u32)(priv->rx_buff[i])); + + writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc), + &mac_regs->rx_dsc_base); + writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), + &mac_regs->rx_dsc_size); + + writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)), + &mac_regs->rx_dsc_sw_p); +} + +static void pch_gbe_tx_descs_init(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0]; + + memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM); + + writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc), + &mac_regs->tx_dsc_base); + writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), + &mac_regs->tx_dsc_size); + writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)), + &mac_regs->tx_dsc_sw_p); +} + +static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs, + struct phy_device *phydev) +{ + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + clrbits_le32(&mac_regs->rgmii_ctrl, + PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL); + clrbits_le32(&mac_regs->mode, + PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX); + + switch (phydev->speed) { + case 1000: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER); + break; + case 100: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER); + break; + case 10: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER); + break; + } + + if (phydev->duplex) { + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX); + } + + printf("Speed: %d, %s duplex\n", phydev->speed, + (phydev->duplex) ? "full" : "half"); + + return; +} + +static int pch_gbe_init(struct eth_device *dev, bd_t *bis) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + + if (pch_gbe_reset(dev)) + return -1; + + pch_gbe_rx_descs_init(dev); + pch_gbe_tx_descs_init(dev); + + /* Enable frame bursting */ + writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode); + /* Disable TCP/IP accelerator */ + writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc); + /* Disable RX flow control */ + writel(0, &mac_regs->rx_fctrl); + /* Configure RX/TX mode */ + writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 | + PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode); + writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 | + PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD | + PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode); + + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; + } + + pch_gbe_adjust_link(mac_regs, priv->phydev); + + if (!priv->phydev->link) + return -1; + + /* Enable TX & RX */ + writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl); + writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en); + + return 0; +} + +static void pch_gbe_halt(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + + pch_gbe_reset(dev); + + phy_shutdown(priv->phydev); +} + +static int pch_gbe_send(struct eth_device *dev, void *packet, int length) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_tx_desc *tx_head, *tx_desc; + u16 frame_ctrl = 0; + u32 int_st; + ulong start; + + tx_head = &priv->tx_desc[0]; + tx_desc = &priv->tx_desc[priv->tx_idx]; + + if (length < 64) + frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; + + tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet); + tx_desc->length = length; + tx_desc->tx_words_eob = length + 3; + tx_desc->tx_frame_ctrl = frame_ctrl; + tx_desc->dma_status = 0; + tx_desc->gbec_status = 0; + + /* Test the wrap-around condition */ + if (++priv->tx_idx >= PCH_GBE_DESC_NUM) + priv->tx_idx = 0; + + writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)), + &mac_regs->tx_dsc_sw_p); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + int_st = readl(&mac_regs->int_st); + if (int_st & PCH_GBE_INT_TX_CMPLT) + return 0; + + udelay(10); + } + + debug("pch_gbe: sent failed\n"); + return -ETIME; +} + +static int pch_gbe_recv(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_rx_desc *rx_head, *rx_desc; + u32 hw_desc, buffer_addr, length; + int rx_swp; + + rx_head = &priv->rx_desc[0]; + rx_desc = &priv->rx_desc[priv->rx_idx]; + + readl(&mac_regs->int_st); + hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld); + + /* Just return if not receiving any packet */ + if ((u32)rx_desc == hw_desc) + return 0; + + buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr); + length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN; + NetReceive((uchar *)buffer_addr, length); + + /* Test the wrap-around condition */ + if (++priv->rx_idx >= PCH_GBE_DESC_NUM) + priv->rx_idx = 0; + rx_swp = priv->rx_idx; + if (++rx_swp >= PCH_GBE_DESC_NUM) + rx_swp = 0; + + writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)), + &mac_regs->rx_dsc_sw_p); + + return length; +} + +static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs) +{ + ulong start = get_timer(0); + + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY) + return 0; + + udelay(10); + } + + return -ETIME; +} + +static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct pch_gbe_regs *mac_regs = bus->priv; + u32 miim; + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | + (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | + PCH_GBE_MIIM_OPER_READ; + writel(miim, &mac_regs->miim); + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + return readl(&mac_regs->miim) & 0xffff; +} + +static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 val) +{ + struct pch_gbe_regs *mac_regs = bus->priv; + u32 miim; + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | + (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | + PCH_GBE_MIIM_OPER_WRITE | val; + writel(miim, &mac_regs->miim); + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + else + return 0; +} + +static int pch_gbe_mdio_init(char *name, struct pch_gbe_regs *mac_regs) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + debug("pch_gbe: failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = pch_gbe_mdio_read; + bus->write = pch_gbe_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs; + + return mdio_register(bus); +} + +static int pch_gbe_phy_init(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct phy_device *phydev; + int mask = 0xffffffff; + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) { + printf("pch_gbe: cannot find the phy\n"); + return -1; + } + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 1; +} + +int pch_gbe_register(bd_t *bis) +{ + struct eth_device *dev; + struct pch_gbe_priv *priv; + pci_dev_t devno; + u32 iobase; + + devno = pci_find_devices(supported, 0); + if (devno == -1) + return -ENODEV; + + dev = (struct eth_device *)malloc(sizeof(*dev)); + if (!dev) + return -ENOMEM; + memset(dev, 0, sizeof(*dev)); + + /* + * The priv structure contains the descriptors and frame buffers which + * need a strict buswidth alignment (64 bytes) + */ + priv = (struct pch_gbe_priv *)memalign(PCH_GBE_ALIGN_SIZE, + sizeof(*priv)); + if (!priv) { + free(dev); + return -ENOMEM; + } + memset(priv, 0, sizeof(*priv)); + + dev->priv = priv; + priv->dev = dev; + priv->bdf = devno; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = pci_mem_to_phys(devno, iobase); + + dev->iobase = iobase; + priv->mac_regs = (struct pch_gbe_regs *)iobase; + + sprintf(dev->name, "pch_gbe.%x", iobase); + + /* Read MAC address from SROM and initialize dev->enetaddr with it */ + pch_gbe_mac_read(priv->mac_regs, dev->enetaddr); + + dev->init = pch_gbe_init; + dev->halt = pch_gbe_halt; + dev->send = pch_gbe_send; + dev->recv = pch_gbe_recv; + + eth_register(dev); + + priv->interface = PHY_INTERFACE_MODE_RGMII; + pch_gbe_mdio_init(dev->name, priv->mac_regs); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return pch_gbe_phy_init(dev); +} diff --git a/drivers/net/pch_gbe.h b/drivers/net/pch_gbe.h new file mode 100644 index 0000000000..11329d4834 --- /dev/null +++ b/drivers/net/pch_gbe.h @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver + * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCH_GBE_H_ +#define _PCH_GBE_H_ + +#define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ) + +#define PCH_GBE_DESC_NUM 4 +#define PCH_GBE_ALIGN_SIZE 64 + +/* + * Topcliff GBE MAC supports receiving ethernet frames with normal frame size + * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a + * register bit to turn off receiving 'jumbo frame', so we have to allocate + * our own buffer to store the received frames instead of using U-Boot's own. + */ +#define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE) + +/* Interrupt Status */ +/* Interrupt Status Hold */ +/* Interrupt Enable */ +#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 +#define PCH_GBE_INT_RX_VALID 0x00000002 +#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 +#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 +#define PCH_GBE_INT_RX_DMA_ERR 0x00000010 +#define PCH_GBE_INT_RX_DSC_EMP 0x00000020 +#define PCH_GBE_INT_TX_CMPLT 0x00000100 +#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 +#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 +#define PCH_GBE_INT_TX_DMA_ERR 0x00000800 +#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 +#define PCH_GBE_INT_MIIM_CMPLT 0x00010000 +#define PCH_GBE_INT_PHY_INT 0x00100000 +#define PCH_GBE_INT_WOL_DET 0x01000000 +#define PCH_GBE_INT_TCPIP_ERR 0x10000000 + +/* Mode */ +#define PCH_GBE_MODE_MII_ETHER 0x00000000 +#define PCH_GBE_MODE_GMII_ETHER 0x80000000 +#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 +#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 +#define PCH_GBE_MODE_FR_BST 0x04000000 + +/* Reset */ +#define PCH_GBE_ALL_RST 0x80000000 +#define PCH_GBE_TX_RST 0x00008000 +#define PCH_GBE_RX_RST 0x00004000 + +/* TCP/IP Accelerator Control */ +#define PCH_GBE_EX_LIST_EN 0x00000008 +#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 +#define PCH_GBE_TX_TCPIPACC_EN 0x00000002 +#define PCH_GBE_RX_TCPIPACC_EN 0x00000001 + +/* MAC RX Enable */ +#define PCH_GBE_MRE_MAC_RX_EN 0x00000001 + +/* RX Flow Control */ +#define PCH_GBE_FL_CTRL_EN 0x80000000 + +/* RX Mode */ +#define PCH_GBE_ADD_FIL_EN 0x80000000 +#define PCH_GBE_MLT_FIL_EN 0x40000000 +#define PCH_GBE_RH_ALM_EMP_4 0x00000000 +#define PCH_GBE_RH_ALM_EMP_8 0x00004000 +#define PCH_GBE_RH_ALM_EMP_16 0x00008000 +#define PCH_GBE_RH_ALM_EMP_32 0x0000c000 +#define PCH_GBE_RH_ALM_FULL_4 0x00000000 +#define PCH_GBE_RH_ALM_FULL_8 0x00001000 +#define PCH_GBE_RH_ALM_FULL_16 0x00002000 +#define PCH_GBE_RH_ALM_FULL_32 0x00003000 +#define PCH_GBE_RH_RD_TRG_4 0x00000000 +#define PCH_GBE_RH_RD_TRG_8 0x00000200 +#define PCH_GBE_RH_RD_TRG_16 0x00000400 +#define PCH_GBE_RH_RD_TRG_32 0x00000600 +#define PCH_GBE_RH_RD_TRG_64 0x00000800 +#define PCH_GBE_RH_RD_TRG_128 0x00000a00 +#define PCH_GBE_RH_RD_TRG_256 0x00000c00 +#define PCH_GBE_RH_RD_TRG_512 0x00000e00 + +/* TX Mode */ +#define PCH_GBE_TM_NO_RTRY 0x80000000 +#define PCH_GBE_TM_LONG_PKT 0x40000000 +#define PCH_GBE_TM_ST_AND_FD 0x20000000 +#define PCH_GBE_TM_SHORT_PKT 0x10000000 +#define PCH_GBE_TM_LTCOL_RETX 0x08000000 +#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 +#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 +#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 +#define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000 +#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 +#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 +#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 +#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 +#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 +#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 +#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 +#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 +#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 +#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 +#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 +#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 + +/* MAC Address Mask */ +#define PCH_GBE_BUSY 0x80000000 + +/* MIIM */ +#define PCH_GBE_MIIM_OPER_WRITE 0x04000000 +#define PCH_GBE_MIIM_OPER_READ 0x00000000 +#define PCH_GBE_MIIM_OPER_READY 0x04000000 +#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21 +#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16 + +/* RGMII Control */ +#define PCH_GBE_CRS_SEL 0x00000010 +#define PCH_GBE_RGMII_RATE_125M 0x00000000 +#define PCH_GBE_RGMII_RATE_25M 0x00000008 +#define PCH_GBE_RGMII_RATE_2_5M 0x0000000c +#define PCH_GBE_RGMII_MODE_GMII 0x00000000 +#define PCH_GBE_RGMII_MODE_RGMII 0x00000002 +#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000 +#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001 + +/* DMA Control */ +#define PCH_GBE_RX_DMA_EN 0x00000002 +#define PCH_GBE_TX_DMA_EN 0x00000001 + +/* Receive Descriptor bit definitions */ +#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400 +#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200 +#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100 +#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0 +#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080 +#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040 +#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020 +#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010 +#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008 +#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004 +#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002 +#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001 +#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200 +#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100 +#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080 +#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040 +#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020 +#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010 +#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008 +#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004 +#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002 +#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001 + +/* Transmit Descriptor bit definitions */ +#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008 +#define PCH_GBE_TXD_CTRL_ITAG 0x0004 +#define PCH_GBE_TXD_CTRL_ICRC 0x0002 +#define PCH_GBE_TXD_CTRL_APAD 0x0001 +#define PCH_GBE_TXD_WORDS_SHIFT 2 +#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000 +#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000 +#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800 +#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400 +#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200 +#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100 +#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080 +#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040 +#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020 +#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010 + +/** + * struct pch_gbe_rx_desc - Receive Descriptor + * @buffer_addr: RX Frame Buffer Address + * @tcp_ip_status: TCP/IP Accelerator Status + * @rx_words_eob: RX word count and Byte position + * @gbec_status: GMAC Status + * @dma_status: DMA Status + * @reserved1: Reserved + * @reserved2: Reserved + */ +struct pch_gbe_rx_desc { + u32 buffer_addr; + u32 tcp_ip_status; + u16 rx_words_eob; + u16 gbec_status; + u8 dma_status; + u8 reserved1; + u16 reserved2; +}; + +/** + * struct pch_gbe_tx_desc - Transmit Descriptor + * @buffer_addr: TX Frame Buffer Address + * @length: Data buffer length + * @reserved1: Reserved + * @tx_words_eob: TX word count and Byte position + * @tx_frame_ctrl: TX Frame Control + * @dma_status: DMA Status + * @reserved2: Reserved + * @gbec_status: GMAC Status + */ +struct pch_gbe_tx_desc { + u32 buffer_addr; + u16 length; + u16 reserved1; + u16 tx_words_eob; + u16 tx_frame_ctrl; + u8 dma_status; + u8 reserved2; + u16 gbec_status; +}; + +/** + * pch_gbe_regs_mac_adr - structure holding values of mac address registers + * + * @high Denotes the 1st to 4th byte from the initial of MAC address + * @low Denotes the 5th to 6th byte from the initial of MAC address + */ +struct pch_gbe_regs_mac_adr { + u32 high; + u32 low; +}; + +/** + * pch_gbe_regs - structure holding values of MAC registers + */ +struct pch_gbe_regs { + u32 int_st; + u32 int_en; + u32 mode; + u32 reset; + u32 tcpip_acc; + u32 ex_list; + u32 int_st_hold; + u32 phy_int_ctrl; + u32 mac_rx_en; + u32 rx_fctrl; + u32 pause_req; + u32 rx_mode; + u32 tx_mode; + u32 rx_fifo_st; + u32 tx_fifo_st; + u32 tx_fid; + u32 tx_result; + u32 pause_pkt1; + u32 pause_pkt2; + u32 pause_pkt3; + u32 pause_pkt4; + u32 pause_pkt5; + u32 reserve[2]; + struct pch_gbe_regs_mac_adr mac_adr[16]; + u32 addr_mask; + u32 miim; + u32 mac_addr_load; + u32 rgmii_st; + u32 rgmii_ctrl; + u32 reserve3[3]; + u32 dma_ctrl; + u32 reserve4[3]; + u32 rx_dsc_base; + u32 rx_dsc_size; + u32 rx_dsc_hw_p; + u32 rx_dsc_hw_p_hld; + u32 rx_dsc_sw_p; + u32 reserve5[3]; + u32 tx_dsc_base; + u32 tx_dsc_size; + u32 tx_dsc_hw_p; + u32 tx_dsc_hw_p_hld; + u32 tx_dsc_sw_p; + u32 reserve6[3]; + u32 rx_dma_st; + u32 tx_dma_st; + u32 reserve7[2]; + u32 wol_st; + u32 wol_ctrl; + u32 wol_addr_mask; +}; + +struct pch_gbe_priv { + struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM]; + struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM]; + char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN]; + struct eth_device *dev; + struct phy_device *phydev; + struct mii_dev *bus; + struct pch_gbe_regs *mac_regs; + pci_dev_t bdf; + u32 interface; + int rx_idx; + int tx_idx; +}; + +#endif /* _PCH_GBE_H_ */ diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index 4565398b0b..f8c9b77be0 100644 --- a/drivers/power/axp209.c +++ b/drivers/power/axp209.c @@ -119,7 +119,7 @@ int axp209_set_ldo3(int mvolt) if (mvolt == -1) cfg = 0x80; /* determined by LDO3IN pin */ else - cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); + cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); return axp209_write(AXP209_LDO3_VOLTAGE, cfg); } diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index c9d318c0a7..44857a6e41 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -14,7 +14,6 @@ #include <common.h> #include <command.h> #include <rtc.h> -#include <version.h> #if defined(__I386__) || defined(CONFIG_MALTA) #include <asm/io.h> diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 3fc7104359..2de3737739 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -16,8 +16,6 @@ #include <dm/lists.h> #include <dm/device-internal.h> -#include <ns16550.h> - DECLARE_GLOBAL_DATA_PTR; /* diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index 2ddbf32a50..54e596c4ed 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <dm.h> #include <serial.h> DECLARE_GLOBAL_DATA_PTR; @@ -23,21 +24,23 @@ struct arc_serial_regs { unsigned int baudh; }; + +struct arc_serial_platdata { + struct arc_serial_regs *reg; + unsigned int uartclk; +}; + /* Bit definitions of STATUS register */ #define UART_RXEMPTY (1 << 5) #define UART_OVERFLOW_ERR (1 << 1) #define UART_TXEMPTY (1 << 7) -struct arc_serial_regs *regs; - -static void arc_serial_setbrg(void) +static int arc_serial_setbrg(struct udevice *dev, int baudrate) { - int arc_console_baud; + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1; - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - - arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; writeb(arc_console_baud & 0xff, ®s->baudl); #ifdef CONFIG_ARC @@ -56,34 +59,49 @@ static void arc_serial_setbrg(void) #else writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); #endif -} -static int arc_serial_init(void) -{ - regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE; - serial_setbrg(); return 0; } -static void arc_serial_putc(const char c) +static int arc_serial_putc(struct udevice *dev, const char c) { + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + if (c == '\n') - arc_serial_putc('\r'); + arc_serial_putc(dev, '\r'); while (!(readb(®s->status) & UART_TXEMPTY)) ; writeb(c, ®s->data); + + return 0; } -static int arc_serial_tstc(void) +static int arc_serial_tstc(struct arc_serial_regs *const regs) { return !(readb(®s->status) & UART_RXEMPTY); } -static int arc_serial_getc(void) +static int arc_serial_pending(struct udevice *dev, bool input) +{ + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + uint32_t status = readb(®s->status); + + if (input) + return status & UART_RXEMPTY ? 0 : 1; + else + return status & UART_TXEMPTY ? 0 : 1; +} + +static int arc_serial_getc(struct udevice *dev) { - while (!arc_serial_tstc()) + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + + while (!arc_serial_tstc(regs)) ; /* Check for overflow errors */ @@ -93,23 +111,42 @@ static int arc_serial_getc(void) return readb(®s->data) & 0xFF; } -static struct serial_device arc_serial_drv = { - .name = "arc_serial", - .start = arc_serial_init, - .stop = NULL, - .setbrg = arc_serial_setbrg, - .putc = arc_serial_putc, - .puts = default_serial_puts, - .getc = arc_serial_getc, - .tstc = arc_serial_tstc, -}; - -void arc_serial_initialize(void) +static int arc_serial_probe(struct udevice *dev) { - serial_register(&arc_serial_drv); + return 0; } -__weak struct serial_device *default_serial_console(void) +static const struct dm_serial_ops arc_serial_ops = { + .putc = arc_serial_putc, + .pending = arc_serial_pending, + .getc = arc_serial_getc, + .setbrg = arc_serial_setbrg, +}; + +static const struct udevice_id arc_serial_ids[] = { + { .compatible = "snps,arc-uart" }, + { } +}; + +static int arc_serial_ofdata_to_platdata(struct udevice *dev) { - return &arc_serial_drv; + struct arc_serial_platdata *plat = dev_get_platdata(dev); + DECLARE_GLOBAL_DATA_PTR; + + plat->reg = (struct arc_serial_regs *)fdtdec_get_addr(gd->fdt_blob, + dev->of_offset, "reg"); + plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; } + +U_BOOT_DRIVER(serial_arc) = { + .name = "serial_arc", + .id = UCLASS_SERIAL, + .of_match = arc_serial_ids, + .ofdata_to_platdata = arc_serial_ofdata_to_platdata, + .probe = arc_serial_probe, + .ops = &arc_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index edbd520141..ce6f1cc74e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o +obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c index 6b8563366b..834c5bd259 100644 --- a/drivers/spi/cf_qspi.c +++ b/drivers/spi/cf_qspi.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define clamp(x, low, high) (min(max(low, x), high)) -#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s) +#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave) struct cf_qspi_slave { struct spi_slave slave; /* Specific bus:cs ID for each device */ diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 879a809cba..6ce11012e8 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -20,13 +20,6 @@ struct cf_spi_slave { int charbit; }; -int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags); -struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode); -void cfspi_init(void); -void cfspi_tx(u32 ctrl, u16 data); -u16 cfspi_rx(void); - extern void cfspi_port_conf(void); extern int cfspi_claim_bus(uint bus, uint cs); extern void cfspi_release_bus(uint bus, uint cs); @@ -46,7 +39,12 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000 -void cfspi_init(void) +static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct cf_spi_slave, slave); +} + +static void cfspi_init(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -84,7 +82,7 @@ void cfspi_init(void) #endif } -void cfspi_tx(u32 ctrl, u16 data) +static void cfspi_tx(u32 ctrl, u16 data) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -93,7 +91,7 @@ void cfspi_tx(u32 ctrl, u16 data) dspi->tfr = (ctrl | data); } -u16 cfspi_rx(void) +static u16 cfspi_rx(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -102,10 +100,10 @@ u16 cfspi_rx(void) return (dspi->rfr & 0xFFFF); } -int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags) +static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, + void *din, ulong flags) { - struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave; + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; static u32 ctrl = 0; @@ -176,7 +174,8 @@ int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, return 0; } -struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) +static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, + uint mode) { /* * bit definition for mode: @@ -326,7 +325,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + + free(cfslave); } int spi_claim_bus(struct spi_slave *slave) diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0ec5b9d859..bf18362baa 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -32,9 +32,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!ds) return NULL; - ds->slave.bus = bus; - ds->slave.cs = cs; - switch (bus) { case SPI0_BUS: ds->regs = (struct davinci_spi_regs *)SPI0_BASE; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 2624844d52..8f5c0fc802 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv) if (!priv->fifo_len) { u32 fifo; - for (fifo = 2; fifo <= 256; fifo++) { + for (fifo = 1; fifo < 256; fifo++) { dw_writew(priv, DW_SPI_TXFLTR, fifo); if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) break; } - priv->fifo_len = (fifo == 2) ? 0 : fifo - 1; + priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_writew(priv, DW_SPI_TXFLTR, 0); } debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c index 267e4d83bd..c7d6480478 100644 --- a/drivers/spi/ftssp010_spi.c +++ b/drivers/spi/ftssp010_spi.c @@ -431,7 +431,9 @@ free_out: void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + + free(chip); } int spi_claim_bus(struct spi_slave *slave) diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c new file mode 100644 index 0000000000..c5b766c0dd --- /dev/null +++ b/drivers/spi/lpc32xx_ssp.c @@ -0,0 +1,144 @@ +/* + * LPC32xx SSP interface (SPI mode) + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> +#include <asm/arch/clk.h> + +/* SSP chip registers */ +struct ssp_regs { + u32 cr0; + u32 cr1; + u32 data; + u32 sr; + u32 cpsr; + u32 imsc; + u32 ris; + u32 mis; + u32 icr; + u32 dmacr; +}; + +/* CR1 register defines */ +#define SSP_CR1_SSP_ENABLE 0x0002 + +/* SR register defines */ +#define SSP_SR_TNF 0x0002 +/* SSP status RX FIFO not empty bit */ +#define SSP_SR_RNE 0x0004 + +/* lpc32xx spi slave */ +struct lpc32xx_spi_slave { + struct spi_slave slave; + struct ssp_regs *regs; +}; + +static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave( + struct spi_slave *slave) +{ + return container_of(slave, struct lpc32xx_spi_slave, slave); +} + +/* spi_init is called during boot when CONFIG_CMD_SPI is defined */ +void spi_init(void) +{ + /* + * nothing to do: clocking was enabled in lpc32xx_ssp_enable() + * and configuration will be done in spi_setup_slave() + */ +} + +/* the following is called in sequence by do_spi_xfer() */ + +struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{ + struct lpc32xx_spi_slave *lslave; + + /* we only set up SSP0 for now, so ignore bus */ + + if (mode & SPI_3WIRE) { + error("3-wire mode not supported"); + return NULL; + } + + if (mode & SPI_SLAVE) { + error("slave mode not supported\n"); + return NULL; + } + + if (mode & SPI_PREAMBLE) { + error("preamble byte skipping not supported\n"); + return NULL; + } + + lslave = spi_alloc_slave(struct lpc32xx_spi_slave, bus, cs); + if (!lslave) { + printf("SPI_error: Fail to allocate lpc32xx_spi_slave\n"); + return NULL; + } + + lslave->regs = (struct ssp_regs *)SSP0_BASE; + + /* + * 8 bit frame, SPI fmt, 500kbps -> clock divider is 26. + * Set SCR to 0 and CPSDVSR to 26. + */ + + writel(0x7, &lslave->regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */ + writel(26, &lslave->regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */ + writel(0, &lslave->regs->imsc); /* do not raise any interrupts */ + writel(0, &lslave->regs->icr); /* clear any pending interrupt */ + writel(0, &lslave->regs->dmacr); /* do not do DMAs */ + writel(SSP_CR1_SSP_ENABLE, &lslave->regs->cr1); /* enable SSP0 */ + return &lslave->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave); + + debug("(lpc32xx) spi_free_slave: 0x%08x\n", (u32)lslave); + free(lslave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + /* only one bus and slave so far, always available */ + return 0; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave); + int bytelen = bitlen >> 3; + int idx_out = 0; + int idx_in = 0; + int start_time; + + start_time = get_timer(0); + while ((idx_out < bytelen) || (idx_in < bytelen)) { + int status = readl(&lslave->regs->sr); + if ((idx_out < bytelen) && (status & SSP_SR_TNF)) + writel(((u8 *)dout)[idx_out++], &lslave->regs->data); + if ((idx_in < bytelen) && (status & status & SSP_SR_RNE)) + ((u8 *)din)[idx_in++] = readl(&lslave->regs->data); + if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT) + return -1; + } + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* do nothing */ +} diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 857b60455a..3356c0f072 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -109,10 +109,17 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave->op_mode_rx = 8; #endif +#ifdef CONFIG_QSPI_QUAD_SUPPORT + memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | + QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS); +#else memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; +#endif writel(memval, &qslave->base->setup0); } diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index ba442d5ed5..8f03a6bb9d 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -68,7 +68,6 @@ unsigned packet_received, packet_sent; #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ #define ETH_DATA_LEN 1500 /* Max. octets in payload */ #define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */ -#define ETH_FCS_LEN 4 /* Octets in the FCS */ #define DRIVER_DESC "Ethernet Gadget" /* Based on linux 2.6.27 version */ diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c index 404a7b96f8..62c9b2ead7 100644 --- a/drivers/usb/gadget/rndis.c +++ b/drivers/usb/gadget/rndis.c @@ -43,7 +43,6 @@ #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ #define ETH_DATA_LEN 1500 /* Max. octets in payload */ #define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */ -#define ETH_FCS_LEN 4 /* Octets in the FCS */ #define ENOTSUPP 524 /* Operation is not supported */ diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 6e58ddf02c..51fb3fd7e2 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -1,5 +1,8 @@ #include <common.h> #include <watchdog.h> +#ifdef CONFIG_ARCH_SUNXI +#include <asm/arch/usbc.h> +#endif #include <asm/errno.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> @@ -186,8 +189,19 @@ void usb_reset_root_port(void) power &= 0xf0; musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power); mdelay(50); +#ifdef CONFIG_ARCH_SUNXI + /* + * sunxi phy has a bug and it will wrongly detect high speed squelch + * when clearing reset on low-speed devices, temporary disable + * squelch detection to work around this. + */ + sunxi_usbc_enable_squelch_detect(0, 0); +#endif power = musb_readb(mbase, MUSB_POWER); musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power); +#ifdef CONFIG_ARCH_SUNXI + sunxi_usbc_enable_squelch_detect(0, 1); +#endif host->isr(0, host); host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ? USB_SPEED_HIGH : diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 4d8c15a5e0..90aaec60d5 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -261,7 +261,7 @@ static int sunxi_musb_init(struct musb *musb) } err = gpio_get_value(vbus_det); - if (err) { + if (err < 0) { gpio_free(vbus_det); return -EIO; } diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index c5d7330804..8f3b8263da 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -19,6 +19,7 @@ #include <asm/arch/mipi_dsim.h> #include <asm/arch/dp_info.h> #include <asm/arch/system.h> +#include <asm/gpio.h> #include <asm-generic/errno.h> #include "exynos_fb.h" @@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid) static void lcd_panel_on(vidinfo_t *vid) { + struct gpio_desc pwm_out_gpio; + struct gpio_desc bl_en_gpio; + unsigned int node; + udelay(vid->init_delay); exynos_backlight_reset(); @@ -121,6 +126,22 @@ static void lcd_panel_on(vidinfo_t *vid) exynos_backlight_on(1); +#ifdef CONFIG_OF_CONTROL + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_SAMSUNG_EXYNOS_FIMD); + if (node <= 0) { + debug("FIMD: Can't get device node for FIMD\n"); + return; + } + gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio", + 0, &pwm_out_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0, + &bl_en_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + +#endif exynos_cfg_ldo(); exynos_enable_ldo(1); diff --git a/drivers/video/mpc8xx_lcd.c b/drivers/video/mpc8xx_lcd.c index faa58c020b..b08576eab2 100644 --- a/drivers/video/mpc8xx_lcd.c +++ b/drivers/video/mpc8xx_lcd.c @@ -15,7 +15,6 @@ #include <common.h> #include <command.h> #include <watchdog.h> -#include <version.h> #include <stdarg.h> #include <lcdvideo.h> #include <linux/types.h> diff --git a/drivers/video/parade.c b/drivers/video/parade.c index 0f543f653c..ae5097160f 100644 --- a/drivers/video/parade.c +++ b/drivers/video/parade.c @@ -12,6 +12,7 @@ #include <common.h> #include <i2c.h> #include <fdtdec.h> +#include <asm/gpio.h> /* * Initialization of the chip is a process of writing certaing values into @@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct reg_data *table) int parade_init(const void *blob) { + struct gpio_desc rst_gpio; + struct gpio_desc slp_gpio; int bus, old_bus; int parent; int node; @@ -201,6 +204,14 @@ int parade_init(const void *blob) return -1; } + gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + mdelay(10); + + gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + bus = i2c_get_bus_num_fdt(parent); old_bus = i2c_get_bus_num(); diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c index 04105d4eaa..64cef37bc9 100644 --- a/drivers/video/pxa_lcd.c +++ b/drivers/video/pxa_lcd.c @@ -13,7 +13,6 @@ #include <config.h> #include <common.h> -#include <version.h> #include <stdarg.h> #include <linux/types.h> #include <stdio_dev.h> diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index 73c9544ea0..e79a13be8b 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -21,6 +21,7 @@ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_EDITENV /* editenv */ +#define CONFIG_CMD_ENV_EXISTS /* query whether env variables exists */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_IMI /* iminfo */ #define CONFIG_CMD_ITEST /* Integer (and string) test */ diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 73f093f9ea..d71e58dae1 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -213,7 +213,8 @@ "done\0" \ \ "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ + "part list ${devtype} ${devnum} -bootable devplist; " \ + "env exists devplist || setenv devplist 1; " \ "for bootpart in ${devplist}; do " \ "if fstype ${devtype} ${devnum}:${bootpart} " \ "bootfstype; then " \ diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h index 1ecc0bb0a9..8237239c00 100644 --- a/include/config_distro_defaults.h +++ b/include/config_distro_defaults.h @@ -20,10 +20,12 @@ #define CONFIG_BOOTP_PXE #define CONFIG_BOOTP_SUBNETMASK -#if defined(__arm__) +#if defined(__arm__) || defined(__aarch64__) #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) #define CONFIG_BOOTP_VCI_STRING "U-boot.armv7" +#elif defined(__aarch64__) +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8" #else #define CONFIG_BOOTP_VCI_STRING "U-boot.arm" #endif @@ -31,7 +33,11 @@ #define CONFIG_OF_LIBFDT +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI +#else #define CONFIG_CMD_BOOTZ +#endif #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_EXT2 diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 838a0b18c3..dca1ca5abd 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -391,7 +391,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 6aaaaa43f0..047ed8b1bb 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -198,7 +198,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 59a8d1b5d1..ceee0e4d49 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -320,7 +320,6 @@ combinations. this should be removed later /* NAND */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index e24b923368..7c45c3617a 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -234,7 +234,6 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 66303773c3..9390464b10 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -14,9 +14,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF520x /* define processor family */ -#define CONFIG_M5208 /* define processor type */ - #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index cde7305954..e9424b4a07 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF5227x /* define processor family */ -#define CONFIG_M52277 /* define processor type */ #define CONFIG_M52277EVB /* M52277EVB board */ #define CONFIG_MCFUART diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 0f6e2f72cf..883347b0fd 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF523x /* define processor family */ -#define CONFIG_M5235 /* define processor type */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index ae4fe45fce..60e5b45942 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -18,9 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5249 /* define processor type */ - #define CONFIG_MCFTMR #define CONFIG_MCFUART diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 3a1cbcae93..7421b57b0f 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -7,8 +7,6 @@ #ifndef _M5253DEMO_H #define _M5253DEMO_H -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5253 /* define processor type */ #define CONFIG_M5253DEMO /* define board type */ #define CONFIG_MCFTMR diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index fabfdb93db..8fd3907ad8 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -8,8 +8,6 @@ #ifndef _M5253EVBE_H #define _M5253EVBE_H -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5253 /* define processor type */ #define CONFIG_M5253EVBE /* define board type */ #define CONFIG_MCFTMR diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 4c84126559..2c056b114b 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -17,9 +17,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ - #define CONFIG_MCFTMR #define CONFIG_MCFUART diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 4dddab7c1d..7eb31722da 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -21,8 +21,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5275 /* define processor type */ #define CONFIG_M5275EVB /* define board type */ #define CONFIG_MCFTMR diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index fd970d0787..569ad4201e 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -17,9 +17,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5282 /* define processor type */ - #define CONFIG_MCFTMR #define CONFIG_MCFUART diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index a100d9f316..e3fa85655b 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF5301x /* define processor family */ -#define CONFIG_M53015 /* define processor type */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) @@ -202,7 +200,7 @@ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ -#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) #define CONFIG_ENV_SIZE 0x1000 #define CONFIG_ENV_SECT_SIZE 0x8000 #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 78ea384375..795f3592b6 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF532x /* define processor family */ -#define CONFIG_M5329 /* define processor type */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 849c26562a..d75b43cdd3 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF532x /* define processor family */ -#define CONFIG_M5373 /* define processor type */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 3d7dc1fb2d..3a6e9811d5 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF5441x /* define processor family */ -#define CONFIG_M54418 /* define processor type */ #define CONFIG_M54418TWR /* M54418TWR board */ #define CONFIG_MCFUART @@ -55,7 +53,6 @@ #define CONFIG_CMD_MISC #define CONFIG_CMD_MII #undef CONFIG_CMD_NAND -#undef CONFIG_CMD_NAND_YAFFS #define CONFIG_CMD_NET #define CONFIG_CMD_NFS #define CONFIG_CMD_PING diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 734a77fb4f..1b3598a092 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF5445x /* define processor family */ -#define CONFIG_M54451 /* define processor type */ #define CONFIG_M54451EVB /* M54451EVB board */ #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 2faf58156d..2288bff56d 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -18,8 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF5445x /* define processor family */ -#define CONFIG_M54455 /* define processor type */ #define CONFIG_M54455EVB /* M54455EVB board */ #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 2f4549f270..91d6a1ada9 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -18,9 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF547x_8x /* define processor family */ -#define CONFIG_M547x /* define processor type */ -#define CONFIG_M5475 /* define processor type */ #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 9aa02f7c6c..ce9f3b01b2 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -18,9 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF547x_8x /* define processor family */ -#define CONFIG_M548x /* define processor type */ -#define CONFIG_M5485 /* define processor type */ #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index d9a19c3694..9cea76ae9b 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -272,7 +272,6 @@ "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 1384f360bd..fbf38c88d9 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -245,7 +245,6 @@ "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 85f5c40ede..521904daad 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -283,7 +283,6 @@ * NAND Flash on the Local Bus */ #define CONFIG_CMD_NAND 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_NAND_FSL_ELBC 1 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 27221648e4..dc09b1f870 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -308,7 +308,6 @@ CONFIG_SYS_NAND_BASE + 0x80000, \ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 4da247c51a..e624c717ff 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -194,7 +194,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 0b07876e78..5e7bc49dcf 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -303,7 +303,6 @@ CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index cd6a39c657..ccf3ce3bac 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -444,7 +444,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #if defined(CONFIG_P1010RDB_PA) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 437111070d..795e3b5e18 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -290,7 +290,6 @@ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index a8b7817a8e..d65c461fda 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -136,7 +136,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index d8d30bb280..f99da6562a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -251,7 +251,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 3f02cede32..2927043df4 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -398,7 +398,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bd40d6ac93..84e8336a72 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -379,7 +379,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 92f5f56718..faf8c9dc7e 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -308,7 +308,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 52633181ad..6cc95ef2d1 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -341,7 +341,6 @@ #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index ff6d2c1d37..046aa48baa 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -357,7 +357,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index db6b42ea0f..faaf22c9bf 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -328,7 +328,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index dd7d52f293..cfe6557caa 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -281,7 +281,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b644a6ce8b..c1ad35a018 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -467,7 +467,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 94078f5481..6aee6db3f3 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -62,7 +62,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_NAND -#define CONFIG_CMD_NAND_YAFFS #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 73e1b0afa8..d5b6e37a38 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -10,6 +10,8 @@ #ifndef __AMCC_COMMON_H #define __AMCC_COMMON_H +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 2a785b3fc3..229fa5a6c2 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -12,11 +12,6 @@ #define CONFIG_AMCORE #define CONFIG_HOSTNAME AMCORE -#define CONFIG_SYS_GENERIC_BOARD - -#define CONFIG_MCF530x -#define CONFIG_M5307 - #define CONFIG_MCFTMR #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT 0 diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index fa64a688a4..de837cfe08 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -39,16 +39,6 @@ #error No card type defined! #endif -/* - * Define processor - * possible values for Urmel board: only Coldfire M5373 processor supported - * (please do not change) - */ - -/* it seems not clear yet which processor defines we should use */ -#define CONFIG_MCF537x /* define processor family */ -#define CONFIG_MCF532x /* define processor family */ -#define CONFIG_M5373 /* define processor type */ #define CONFIG_ASTRO5373L /* define board type */ /* Command line configuration */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h new file mode 100644 index 0000000000..dedb7857ad --- /dev/null +++ b/include/configs/at91-sama5_common.h @@ -0,0 +1,87 @@ +/* + * Common part of configuration settings for the AT91 SAMA5 board. + * + * Copyright (C) 2015 Atmel Corporation + * Josh Wu <josh.wu@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AT91_SAMA5_COMMON_H +#define __AT91_SAMA5_COMMON_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT /* Device Tree support */ + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mmcblk0p2 rw rootwait" +#else +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ + "256K(env),256k(evn_redundent),256k(spare)," \ + "512k(dtb),6M(kernel)ro,-(rootfs) " \ + "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +#endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index db5d5ea846..e4c49f4c14 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -203,4 +203,62 @@ */ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x010000 +#define CONFIG_SPL_STACK 0x310000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +#define CONFIG_SYS_MONITOR_LEN 0x80000 + +#ifdef CONFIG_SYS_USE_MMC + +#define CONFIG_SPL_BSS_START_ADDR 0x70000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 +#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 + +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE + +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, } +#endif + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0 #endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index f02fce95b3..c44da1c19e 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -201,11 +201,22 @@ #else /* CONFIG_SYS_USE_MMC */ /* bootstrap + u-boot + env + linux in mmc */ -#define CONFIG_ENV_IS_IN_MMC -/* For FAT system, most cases it should be in the reserved sector */ + +#ifdef CONFIG_ENV_IS_IN_MMC +/* Use raw reserved sectors to save environment */ #define CONFIG_ENV_OFFSET 0x2000 #define CONFIG_ENV_SIZE 0x1000 #define CONFIG_SYS_MMC_ENV_DEV 0 +#else +/* Use file in FAT file to save environment */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_FILE "uboot.env" +#define FAT_ENV_DEVICE_AND_PART "0" +#define CONFIG_ENV_SIZE 0x4000 +#endif + #define CONFIG_BOOTCOMMAND \ "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \ "fatload mmc 0:1 0x21000000 dtb;" \ @@ -228,6 +239,62 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20953f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#elif CONFIG_SYS_USE_SPIFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 + +#endif #endif diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 6d8b71dced..1a481b3fd1 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -243,4 +243,61 @@ */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x6000 +#define CONFIG_SPL_STACK 0x308000 + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER + +#elif CONFIG_SYS_USE_SPIFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 + +#endif + #endif diff --git a/include/configs/axs101.h b/include/configs/axs101.h index 5fb8aca4bc..8a7095c5b2 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -34,6 +34,12 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* + * This board might be of different versions so handle it + */ +#define CONFIG_BOARD_TYPES +#define CONFIG_BOARD_EARLY_INIT_F + +/* * NAND Flash configuration */ #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 7a1499d2e3..ed790ccaf3 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -13,8 +13,6 @@ #include <linux/kconfig.h> -#define CONFIG_SYS_GENERIC_BOARD - /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 464436930d..b9f0b0b123 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -25,16 +25,6 @@ #define _CONFIG_COBRA5272_H /* --- - * Define processor - * possible values for Sentec board: only Coldfire M5272 processor supported - * (please do not change) - * --- - */ - -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ - -/* --- * Defines processor clock - important for correct timings concerning serial * interface etc. * --- diff --git a/include/configs/colibri_t20_iris.h b/include/configs/colibri_t20.h index 4888c945fe..c17f245a17 100644 --- a/include/configs/colibri_t20_iris.h +++ b/include/configs/colibri_t20.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Lucas Stach + * Copyright (C) 2012 Lucas Stach * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,13 +10,16 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define V_PROMPT "Tegra20 (Colibri) # " -#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20 on Iris" +#define V_PROMPT "Colibri T20 # " +#define CONFIG_TEGRA_BOARD_STRING "Toradex Colibri T20" /* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T20 /* SD/MMC support */ #define CONFIG_MMC @@ -29,17 +32,17 @@ #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT -#define CONFIG_USB_STORAGE #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_USB_STORAGE #define CONFIG_CMD_USB /* USB networking support */ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX + +/* General networking support */ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING /* NAND support */ #define CONFIG_CMD_NAND @@ -56,6 +59,26 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_CACHE +/* Miscellaneous commands */ +#define CONFIG_CMD_SETEXPR +#define CONFIG_FAT_WRITE + +/* Increase console I/O buffer size */ +#undef CONFIG_SYS_CBSIZE +#define CONFIG_SYS_CBSIZE 1024 + +/* Increase arguments buffer size */ +#undef CONFIG_SYS_BARGSIZE +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Increase print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Increase maximum number of arguments */ +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 32 + +#include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 225ffdd0a5..8e27ae4b72 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -248,7 +248,6 @@ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index ace511f765..f5b8f9b442 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -16,9 +16,6 @@ #include <asm/hardware.h> -#define MACH_TYPE_CORVUS 2066 - -#define CONFIG_MACH_TYPE MACH_TYPE_CORVUS #define CONFIG_SYS_GENERIC_BOARD /* * Warning: changing CONFIG_SYS_TEXT_BASE requires diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index b927b1c9f5..df32f2ac52 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -52,8 +52,20 @@ #define CONFIG_MMC_SDMA #define CONFIG_CMD_MMC +/* Topcliff Gigabit Ethernet */ +#define CONFIG_PCH_GBE +#define CONFIG_PHYLIB + /* Video is not supported */ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE +/* Environment configuration */ +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0 + #endif /* __CONFIG_H */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 8a7447dcd3..56317ef5e7 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -15,7 +15,6 @@ #define CONFIG_DBAU1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_DBAU1000 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index dee2b11056..8fe0e6c16a 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -77,6 +77,7 @@ #define CONFIG_TI_SPI_MMAP #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +#define CONFIG_QSPI_QUAD_SUPPORT /* * Default to using SPI for environment, etc. diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index bdca705874..e2b93268b4 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -15,9 +15,6 @@ * High Level Configuration Options (easy to change) * *----------------------------------------------------------------------*/ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5282 /* define processor type */ - #define CONFIG_MISC_INIT_R #define CONFIG_MCFUART diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index ce61a1621c..b79000e706 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -153,7 +153,6 @@ /* JFFS2 */ #ifdef CONFIG_CMD_JFFS2 -#define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_NAND #endif diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 41631c72e9..577afe7e8f 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -66,4 +66,58 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE +/* Common environment variables */ +#define CONFIG_EXTRA_ENV_ITB \ + "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "${initrdname}\0" \ + "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "check_ramdisk=" \ + "if run loadinitrd; then " \ + "setenv initrd_addr ${initrdaddr};" \ + "else " \ + "setenv initrd_addr -;" \ + "fi;\0" \ + "check_dtb=" \ + "if run loaddtb; then " \ + "setenv fdt_addr ${fdtaddr};" \ + "else " \ + "setenv fdt_addr;" \ + "fi;\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart}" \ + " ${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};\0" \ + "boot_fit=" \ + "setenv kerneladdr 0x42000000;" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr}#${board_name}\0" \ + "boot_uimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname uImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "boot_zimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname zImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "autoboot=" \ + "if test -e mmc ${mmcdev}:${mmcbootpart} Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc ${mmcdev}:${mmcbootpart} zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc ${mmcdev}:${mmcbootpart} uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" + #endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 3ab8d559bf..2eddb07f0a 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -16,14 +16,14 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EXYNOS_SPL -/* Allow tracing to be enabled */ +#ifdef FTRACE #define CONFIG_TRACE #define CONFIG_CMD_TRACE #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) #define CONFIG_TRACE_EARLY_SIZE (8 << 20) #define CONFIG_TRACE_EARLY #define CONFIG_TRACE_EARLY_ADDR 0x50000000 - +#endif /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA diff --git a/include/configs/galileo.h b/include/configs/galileo.h index d745f4eb89..288acf30f1 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -57,4 +57,17 @@ #define CONFIG_MMC_SDMA #define CONFIG_CMD_MMC +/* 10/100M Ethernet support */ +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_PHYLIB + +/* Environment configuration */ +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0 + #endif /* __CONFIG_H */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 2384864eb0..c1ca56c692 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -214,7 +214,6 @@ #define CONFIG_SYS_NAND_BASE 0xE1000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_PAGE_SIZE (2048) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index eac517aeeb..4362925ae1 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -86,3 +86,25 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* + * FLASH and environment organization + * Top varies according to amount fitted + * Reserve top 4 blocks of flash + * - ARM Boot Monitor + * - Unused + * - SIB block + * - U-Boot environment + */ +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ARMFLASH +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Timeout values in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ +#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index edea769a92..e168c8c9ba 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -55,22 +55,12 @@ */ #define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +/* Flash settings */ +#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ #define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_ENV_IS_NOWHERE 1 #define CONFIG_ENV_SIZE 32768 - /*----------------------------------------------------------------------- * PCI definitions */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 608719a7ea..7c1ef2483e 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -55,28 +55,10 @@ */ #define CONFIG_SYS_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ -/* - * FLASH and environment organization - * Top varies according to amount fitted - * Reserve top 4 blocks of flash - * - ARM Boot Monitor - * - Unused - * - SIB block - * - U-Boot environment - * - * Base is always 0x24000000 - */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_MAX_FLASH_SECT 64 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_SYS_MONITOR_LEN 0x00100000 +#define CONFIG_SYS_MAX_FLASH_SECT 64 #define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* * Move up the U-Boot & monitor area if more flash is fitted. diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 949b3dadb3..b70b5b19f5 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -167,7 +167,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 3dc4da391b..5de416d117 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -251,7 +251,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index f80efedeb2..e0435cc0a7 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -191,7 +191,6 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/malta.h b/include/configs/malta.h index 354672ecf8..9445c9b1d7 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -14,7 +14,6 @@ * System configuration */ #define CONFIG_MALTA -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 3fd3184245..de7792a469 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -25,6 +25,8 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MCX #define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 11d7b86eb1..8d3531c828 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -10,22 +10,13 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define CONFIG_NAND -#define CONFIG_SDRC /* The chip has SDRC controller */ +/* override base for compatibility with MLO the device ships with */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> +#include <configs/ti_omap3_common.h> /* * Display CPU and Board information @@ -33,79 +24,42 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* * Hardware drivers */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define CONFIG_SYS_DEVICE_NULLDEV 1 +/* I2C Support */ +#define CONFIG_SYS_I2C_OMAP34XX -/* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 +/* TWL4030 LED */ +#define CONFIG_TWL4030_LED -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 +/* Initialize GPIOs by default */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ /* * NS16550 Configuration */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 +#undef CONFIG_OMAP_SERIAL #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SERIAL3 3 -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - /* commands to include */ #include <config_cmd_default.h> -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_CACHE /* Cache control */ - #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ @@ -113,53 +67,36 @@ #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 - /* * Board NAND Info. */ -#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand */ - /* at CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ - -#ifdef CONFIG_CMD_NAND -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_RBTREE -#define CONFIG_LZO - -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:512k(xloader),"\ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 + +#ifdef CONFIG_NAND +#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */ +#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ + +#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ +#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ + +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ + +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader),"\ "1920k(uboot),128k(uboot-env),"\ "10m(boot),-(rootfs)" #else #define MTDPARTS_DEFAULT #endif -/* Environment information */ -#define CONFIG_BOOTDELAY 1 - #define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ "usbtty=cdc_acm\0" \ - "loadaddr=0x82000000\0" \ "bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ @@ -172,60 +109,18 @@ "ubi part boot && ubifsmount ubi:boot && " \ "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" -#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#undef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "Pandora # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command */ - /* args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -#define CONFIG_SYS_TEXT_BASE 0x80008000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_CMD_NAND) +#if defined(CONFIG_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE #endif diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 7378acdb21..e97c5e30da 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -43,8 +43,13 @@ #define CONFIG_CMD_GPIO /* ENV related config options */ -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_CMD_SAVEENV +#define CONFIG_ENV_OVERWRITE #endif /* __CONFIG_PANDA_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 5f27c2a41a..a5f97176ce 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -494,7 +494,6 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #if defined(CONFIG_P1020RDB_PD) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 61e6af384d..a1926bb64d 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -15,7 +15,6 @@ #define CONFIG_PB1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_PB1000 diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index f04f0613aa..e3cb09e3d5 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -16,6 +16,14 @@ #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) #define CONFIG_SPI_BOOTING +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x22000000\0" \ + "fdt_addr_r=0x23000000\0" \ + "ramdisk_addr_r=0x23300000\0" \ + "scriptaddr=0x30000000\0" \ + "pxefile_addr_r=0x31000000\0" + #include <configs/exynos5420-common.h> #include <configs/exynos5-dt-common.h> diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index b5efbdcaa6..3ee42ef2c8 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -16,6 +16,14 @@ #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) #define CONFIG_SPI_BOOTING +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x22000000\0" \ + "fdt_addr_r=0x23000000\0" \ + "ramdisk_addr_r=0x23300000\0" \ + "scriptaddr=0x30000000\0" \ + "pxefile_addr_r=0x31000000\0" + #include <configs/exynos5420-common.h> #include <configs/exynos5-dt-common.h> diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 1548d3e682..75da8a1ebe 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -14,7 +14,6 @@ #define CONFIG_QEMU_MIPS -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 61cafadd7c..b07ca4e02a 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -14,7 +14,6 @@ #define CONFIG_QEMU_MIPS -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index e9ef7cc980..c33f1cb880 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) - /* Support File sytems */ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index c82728e999..bfd8aa7e6c 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -10,30 +10,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART @@ -51,29 +31,6 @@ */ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* No NOR flash */ -#define CONFIG_SYS_NO_FLASH - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -181,34 +138,6 @@ #define CONFIG_ENV_IS_NOWHERE #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x300000 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index a99b559da6..d933a9e7c6 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -13,30 +13,11 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD - -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +/* + * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH + * before the common header. + */ +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART @@ -69,40 +50,17 @@ /* board specific (not enough SRAM) */ #define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - /* NOR flash */ +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_CMD_FLASH - -#ifdef CONFIG_CMD_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_BASE 0x10000000 #define CONFIG_SYS_MAX_FLASH_SECT 131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#else -#define CONFIG_SYS_NO_FLASH #endif -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -228,34 +186,6 @@ #define CONFIG_ENV_IS_NOWHERE #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x300000 diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 4cb0761520..5fb621ec85 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -10,59 +10,16 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_USART3 #define CONFIG_USART_ID ATMEL_ID_USART3 -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* No NOR flash */ -#define CONFIG_SYS_NO_FLASH - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SETEXPR - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -199,33 +156,6 @@ "bootz 0x22000000 - 0x21000000" #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* SPL */ diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 897d4819f8..546d7a3a9f 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -10,59 +10,16 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/hardware.h> - -#define CONFIG_SYS_TEXT_BASE 0x26f00000 - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_ARCH_CPU_INIT - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - -#define CONFIG_CMD_BOOTZ -#define CONFIG_OF_LIBFDT /* Device Tree support */ - -#define CONFIG_SYS_GENERIC_BOARD +/* No NOR flash, this definition should put before common header */ +#define CONFIG_SYS_NO_FLASH -/* general purpose I/O */ -#define CONFIG_AT91_GPIO +#include "at91-sama5_common.h" /* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_USART3 #define CONFIG_USART_ID ATMEL_ID_USART3 -#define CONFIG_BOOTDELAY 3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* No NOR flash */ -#define CONFIG_SYS_NO_FLASH - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SETEXPR - /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS @@ -197,35 +154,6 @@ "bootz 0x22000000 - 0x21000000" #endif -#ifdef CONFIG_SYS_USE_MMC -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "root=/dev/mmcblk0p2 rw rootwait" -#else -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk " \ - "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(evn_redundent),256k(spare)," \ - "512k(dtb),6M(kernel)ro,-(rootfs) " \ - "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -#endif - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 4442064db9..78ff651d06 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -27,9 +27,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ -#define CONFIG_UART_DISABLE_GPIO GPIO_PI3 - #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD /* I2C */ diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 1537e536f9..7cd5c69d3a 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -11,7 +11,6 @@ /* * A10 specific configuration */ -#define CONFIG_CLK_FULL_SPEED 1008000000 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index e7555313db..e0470d4282 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -11,7 +11,6 @@ /* * High Level Configuration Options */ -#define CONFIG_CLK_FULL_SPEED 1008000000 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index f5e11ddb69..617c1cdfde 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -14,7 +14,6 @@ /* * A31 specific configuration */ -#define CONFIG_CLK_FULL_SPEED 1008000000 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index f817f73076..7fa7cec244 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -12,7 +12,6 @@ /* * A20 specific configuration */ -#define CONFIG_CLK_FULL_SPEED 912000000 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI @@ -21,8 +20,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE -#define CONFIG_SYS_CLK_FREQ 24000000 -#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_TIMER_CLK_FREQ 24000000 /* * Include common sunxi configuration where most the settings are diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 3bdedb390c..79796d75d3 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -12,7 +12,6 @@ /* * A23 specific configuration */ -#define CONFIG_CLK_FULL_SPEED 1008000000 #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 46df40661d..501449a581 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -35,14 +35,10 @@ /* * UART configuration */ -#define CONFIG_CONS_INDEX 1 +#define CONFIG_DW_SERIAL #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_CLK 166666666 -#define CONFIG_SYS_NS16550_COM1 0xFF100000 -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_BAUDRATE 115200 /* diff --git a/include/configs/trats.h b/include/configs/trats.h index b21ea2de5f..6808e789f3 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -51,8 +51,10 @@ #define MACH_TYPE_TRATS 3928 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE #define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_BOOTCOMMAND "run autoboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ @@ -106,7 +108,8 @@ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ - "params.bin raw 0x38 0x8\0" + "params.bin raw 0x38 0x8;" \ + "/Image.itb ext4 0 2\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ @@ -172,6 +175,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ + CONFIG_EXTRA_ENV_ITB \ "fdtaddr=40800000\0" \ /* Falcon mode definitions */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 42481ab6e1..94c31fbf2b 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -44,8 +44,10 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE #define CONFIG_BOOTARGS "Please use defined boot" -#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_BOOTCOMMAND "run autoboot" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ @@ -96,7 +98,8 @@ ""PARTS_ROOT" part 0 5;" \ ""PARTS_DATA" part 0 6;" \ ""PARTS_UMS" part 0 7;" \ - "params.bin raw 0x38 0x8\0" + "params.bin raw 0x38 0x8;" \ + "/Image.itb ext4 0 2\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ @@ -153,6 +156,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ + CONFIG_EXTRA_ENV_ITB \ "fdtaddr=40800000\0" \ /* GPT */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index df89d14cc3..d4688c54ba 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -1,6 +1,7 @@ /* * Copyright (C) 2012-2015 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -275,20 +276,13 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif +#define CONFIG_SPL_STACK (0x0ff08000) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) -#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000) -#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000) -#else -#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000) -#endif +#define CONFIG_PANIC_HANG #define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ @@ -298,4 +292,6 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 +#define CONFIG_SPL_MAX_FOOTPRINT 0x10000 + #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ diff --git a/include/configs/vct.h b/include/configs/vct.h index 83e4163e3f..88e58ec54b 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -25,7 +25,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index bce94b3fdc..107f01a07e 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -186,7 +186,6 @@ */ #define CONFIG_SYS_NAND_BASE 0x61000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 810eef12de..3fda20a8f6 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -8,6 +8,8 @@ #ifndef __VEXPRESS_AEMV8A_H #define __VEXPRESS_AEMV8A_H +#define CONFIG_DM + /* We use generic board for v8 Versatile Express */ #define CONFIG_SYS_GENERIC_BOARD @@ -15,20 +17,11 @@ #ifndef CONFIG_SEMIHOSTING #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING #endif -#define CONFIG_BOARD_LATE_INIT #define CONFIG_ARMV8_SWITCH_TO_EL1 #endif #define CONFIG_REMAKE_ELF -#if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \ - !defined(CONFIG_TARGET_VEXPRESS64_JUNO) -/* Base FVP and Juno not using GICv3 yet */ -#define CONFIG_GICV3 -#endif - -/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ - #define CONFIG_SUPPORT_RAW_INITRD /* Cache Definitions */ @@ -47,8 +40,7 @@ #define CONFIG_SYS_TEXT_BASE 0xe0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) #else -#define CONFIG_SYS_TEXT_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#error "Unknown board variant" #endif /* Flat Device Tree Definitions */ @@ -118,15 +110,15 @@ #define GICD_BASE (0x2C010000) #define GICC_BASE (0x2C02f000) #else -#define GICD_BASE (0x2C001000) -#define GICC_BASE (0x2C002000) -#endif +#error "Unknown board variant" #endif +#endif /* !CONFIG_GICV3 */ #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) /* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) /* Ethernet Configuration */ @@ -142,6 +134,14 @@ #endif /* PL011 Serial Configuration */ +#define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_DM +#define CONFIG_DM_SERIAL +#define CONFIG_PL01X_SERIAL +#else +#define CONFIG_SYS_SERIAL0 V2M_UART0 +#define CONFIG_SYS_SERIAL1 V2M_UART1 +#define CONFIG_CONS_INDEX 0 #define CONFIG_PL011_SERIAL #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define CONFIG_PL011_CLOCK 7273800 @@ -150,7 +150,7 @@ #endif #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1} -#define CONFIG_CONS_INDEX 0 +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_SERIAL0 V2M_UART0 @@ -198,14 +198,41 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Initial environment variables */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO +/* + * Defines where the kernel and FDT exist in NOR flash and where it will + * be copied into DRAM + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=Image\0" \ + "kernel_addr=0x80000000\0" \ + "fdt_name=juno\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Assume we boot with root on the first partition of a USB stick */ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \ + "root=/dev/sda1 rw " \ + "earlyprintk=pl011,0x7ff80000 debug user_debug=31 "\ + "loglevel=9" + +/* Copy the kernel and FDT to DRAM memory and boot */ +#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ + "afs load ${fdt_name} ${fdt_addr} ; " \ + "fdt addr ${fdt_addr}; fdt resize; " \ + "booti ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTDELAY 1 + +#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=uImage\0" \ - "kernel_addr_r=0x80000000\0" \ + "kernel_name=uImage\0" \ + "kernel_addr=0x80000000\0" \ "initrd_name=ramdisk.img\0" \ - "initrd_addr_r=0x88000000\0" \ - "fdt_name=devtree.dtb\0" \ - "fdt_addr_r=0x83000000\0" \ + "initrd_addr=0x88000000\0" \ + "fdt_name=devtree.dtb\0" \ + "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" @@ -213,24 +240,17 @@ "0x1c090000 debug user_debug=31 "\ "loglevel=9" -#define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \ - "fdt chosen $initrd_addr_r $initrd_end; " \ - "bootm $kernel_addr_r - $fdt_addr_r" +#define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ + "smhload ${fdt_name} $fdt_addr; " \ + "smhload ${initrd_name} $initrd_addr initrd_end; " \ + "fdt addr $fdt_addr; fdt resize; " \ + "fdt chosen $initrd_addr $initrd_end; " \ + "bootm $kernel_addr - $fdt_addr" #define CONFIG_BOOTDELAY 1 #else - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x80000000\0" \ - "initrd_addr_r=0x88000000\0" \ - "fdt_addr_r=0x83000000\0" \ - "fdt_high=0xa0000000\0" - -#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0" -#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \ - "$initrd_addr_r:$initrd_size $fdt_addr_r" -#define CONFIG_BOOTDELAY -1 +#error "Unknown board variant" #endif /* Do not preserve environment */ @@ -253,6 +273,7 @@ #define CONFIG_SYS_NO_FLASH #else #define CONFIG_CMD_FLASH +#define CONFIG_CMD_ARMFLASH #define CONFIG_SYS_FLASH_CFI 1 #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_FLASH_BASE 0x08000000 diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h new file mode 100644 index 0000000000..dc8e99fffd --- /dev/null +++ b/include/configs/work_92105.h @@ -0,0 +1,241 @@ +/* + * WORK Microwave work_92105 board configuration file + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_WORK_92105_H__ +#define __CONFIG_WORK_92105_H__ + +/* SoC and board defines */ +#include <linux/sizes.h> +#include <asm/arch/cpu.h> + +/* + * Define work_92105 machine type by hand -- done only for compatibility + * with original board code + */ +#define MACH_TYPE_WORK_92105 736 +#define CONFIG_MACH_TYPE MACH_TYPE_WORK_92105 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + +/* generate LPC32XX-specific SPL image */ +#define CONFIG_LPC32XX_SPL + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MALLOC_LEN SZ_1M +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ + - GENERATED_GBL_DATA_SIZE) + +/* + * Serial Driver + */ +#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ +#define CONFIG_BAUDRATE 115200 + +/* + * Ethernet Driver + */ + +#define CONFIG_PHY_SMSC +#define CONFIG_LPC32XX_ETH +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ + +/* + * I2C driver + */ + +#define CONFIG_SYS_I2C_LPC32XX +#define CONFIG_SYS_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SPEED 350000 + +/* + * I2C EEPROM + */ + +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* + * I2C RTC + */ + +#define CONFIG_CMD_DATE +#define CONFIG_RTC_DS1374 + +/* + * I2C Temperature Sensor (DTT) + */ + +#define CONFIG_CMD_DTT +#define CONFIG_DTT_SENSORS { 0, 1 } +#define CONFIG_DTT_DS620 + +/* + * U-Boot General Configurations + */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +/* + * No NOR + */ + +#define CONFIG_SYS_NO_FLASH + +/* + * NAND chip timings for FIXME: which one? + */ + +#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 +#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 +#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 +#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 +#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 +#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 +#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 + +/* + * NAND + */ + +/* driver configuration */ +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE +#define CONFIG_NAND_LPC32XX_MLC + +#define CONFIG_CMD_NAND + +/* + * GPIO + */ + +#define CONFIG_CMD_GPIO +#define CONFIG_LPC32XX_GPIO + +/* + * SSP/SPI/DISPLAY + */ + +#define CONFIG_CMD_SPI +#define CONFIG_LPC32XX_SSP +#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 +#define CONFIG_CMD_MAX6957 +#define CONFIG_CMD_HD44760 +/* + * Environment + */ + +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE 0x00020000 +#define CONFIG_ENV_OFFSET 0x00100000 +#define CONFIG_ENV_OFFSET_REDUND 0x00120000 +#define CONFIG_ENV_ADDR 0x80000100 + +/* + * Provide default ethernet address + * + * THIS IS NORMALLY NOT DONE. HERE WE KEEP WHAT WAS IN THE PORTED + * BOARD CONFIG IN CASE SOME PROVISIONING PROCESS OUT THERE EXPECTS + * THIS MAC ADDRESS WHEN THE DEVICE HAS STILL ITS DEFAULT CONFIG. + */ + +#define CONFIG_ETHADDR 00:12:B4:00:AF:FE +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* + * U-Boot Commands + */ +#include <config_cmd_default.h> + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyS2,115200n8" +#define CONFIG_LOADADDR 0x80008000 + +/* + * SPL + */ + +/* SPL will be executed at offset 0 */ +#define CONFIG_SPL_TEXT_BASE 0x00000000 +/* SPL will use SRAM as stack */ +#define CONFIG_SPL_STACK 0x0000FFF8 +#define CONFIG_SPL_BOARD_INIT +/* Use the framework and generic lib */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* SPL will use serial */ +#define CONFIG_SPL_SERIAL_SUPPORT +/* SPL will load U-Boot from NAND offset 0x40000 */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_BOOT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 +#define CONFIG_SPL_PAD_TO 0x20000 +/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE + +/* + * Include SoC specific configuration + */ +#include <asm/arch/config.h> + +#endif /* __CONFIG_WORK_92105_H__*/ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 994874ca60..b7dd63e060 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -243,7 +243,34 @@ #define CONFIG_CMD_USB -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_STD_DEVICES_SETTINGS +/* Default environment */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_HOSTNAME "x86" +#define CONFIG_BOOTFILE "bzImage" +#define CONFIG_LOADADDR 0x1000000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_STD_DEVICES_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "othbootargs=acpi=off\0" \ + "ramdiskaddr=0x2000000\0" \ + "ramdiskfile=initramfs.gz\0" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftpboot $loadaddr $bootfile;" \ + "tftpboot $ramdiskaddr $ramdiskfile;" \ + "zboot $loadaddr 0 $ramdiskaddr $filesize" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftpboot $loadaddr $bootfile;" \ + "zboot $loadaddr" #endif /* __CONFIG_H */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index d6b6143500..988a2e8bfe 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -131,7 +131,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ #define CONFIG_NAND_FSL_ELBC diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 4536b94e91..ac3f4f1c84 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -122,7 +122,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ #define CONFIG_NAND_FSL_ELBC diff --git a/include/dtt.h b/include/dtt.h index 058bca4d5d..173159dc62 100644 --- a/include/dtt.h +++ b/include/dtt.h @@ -12,13 +12,14 @@ #define _DTT_H_ #if defined(CONFIG_DTT_ADM1021) || \ - defined(CONFIG_DTT_ADT7460) || \ - defined(CONFIG_DTT_DS1621) || \ - defined(CONFIG_DTT_DS1775) || \ - defined(CONFIG_DTT_LM63) || \ - defined(CONFIG_DTT_LM73) || \ - defined(CONFIG_DTT_LM75) || \ - defined(CONFIG_DTT_LM81) + defined(CONFIG_DTT_ADT7460) || \ + defined(CONFIG_DTT_DS1621) || \ + defined(CONFIG_DTT_DS1775) || \ + defined(CONFIG_DTT_DS620) || \ + defined(CONFIG_DTT_LM63) || \ + defined(CONFIG_DTT_LM73) || \ + defined(CONFIG_DTT_LM75) || \ + defined(CONFIG_DTT_LM81) #define CONFIG_DTT /* We have a DTT */ diff --git a/include/fdtdec.h b/include/fdtdec.h index 5ac515d87d..11a7b86007 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -347,7 +347,10 @@ int fdtdec_get_pci_vendev(const void *blob, int node, /** * Look at the pci address of a device node that represents a PCI device - * and parse the bus, device and function number from it. + * and parse the bus, device and function number from it. For some cases + * like the bus number encoded in reg property is not correct after pci + * enumeration, this function looks through the node's compatible strings + * to get these numbers extracted instead. * * @param blob FDT blob * @param node node to examine diff --git a/include/image.h b/include/image.h index 0e6af00c16..3844be67d8 100644 --- a/include/image.h +++ b/include/image.h @@ -242,6 +242,7 @@ struct lmb; #define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ #define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ #define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */ +#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */ /* * Compression Types diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 8438490fe4..bc927ecc59 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -678,11 +678,6 @@ struct nand_chip { void (*write_byte)(struct mtd_info *mtd, uint8_t byte); void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); -#endif -#endif void (*select_chip)(struct mtd_info *mtd, int chip); int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); diff --git a/include/nand.h b/include/nand.h index 15e31ab538..d2a53ab856 100644 --- a/include/nand.h +++ b/include/nand.h @@ -82,34 +82,8 @@ static inline int nand_erase(nand_info_t *info, loff_t off, size_t size) * declarations from nand_util.c ****************************************************************************/ -struct nand_write_options { - u_char *buffer; /* memory block containing image to write */ - ulong length; /* number of bytes to write */ - ulong offset; /* start address in NAND */ - int quiet; /* don't display progress messages */ - int autoplace; /* if true use auto oob layout */ - int forcejffs2; /* force jffs2 oob layout */ - int forceyaffs; /* force yaffs oob layout */ - int noecc; /* write without ecc */ - int writeoob; /* image contains oob data */ - int pad; /* pad to page size */ - int blockalign; /* 1|2|4 set multiple of eraseblocks - * to align to */ -}; - -typedef struct nand_write_options nand_write_options_t; typedef struct mtd_oob_ops mtd_oob_ops_t; -struct nand_read_options { - u_char *buffer; /* memory block in which read image is written*/ - ulong length; /* number of bytes to read */ - ulong offset; /* start address in NAND */ - int quiet; /* don't display progress messages */ - int readoob; /* put oob data in image */ -}; - -typedef struct nand_read_options nand_read_options_t; - struct nand_erase_options { loff_t length; /* number of bytes to erase */ loff_t offset; /* first address in NAND to erase */ @@ -130,15 +104,16 @@ typedef struct nand_erase_options nand_erase_options_t; int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, size_t *actual, loff_t lim, u_char *buffer); -#define WITH_YAFFS_OOB (1 << 0) /* whether write with yaffs format. This flag - * is a 'mode' meaning it cannot be mixed with - * other flags */ -#define WITH_DROP_FFS (1 << 1) /* drop trailing all-0xff pages */ +#define WITH_DROP_FFS (1 << 0) /* drop trailing all-0xff pages */ +#define WITH_WR_VERIFY (1 << 1) /* verify data was written correctly */ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, size_t *actual, loff_t lim, u_char *buffer, int flags); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); int nand_torture(nand_info_t *nand, loff_t offset); +int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, + loff_t ofs); +int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf); #define NAND_LOCK_STATUS_TIGHT 0x01 #define NAND_LOCK_STATUS_UNLOCK 0x04 diff --git a/include/net.h b/include/net.h index 43e3d28729..237c932be3 100644 --- a/include/net.h +++ b/include/net.h @@ -191,6 +191,8 @@ struct ethernet_hdr { /* Ethernet header size */ #define ETHER_HDR_SIZE (sizeof(struct ethernet_hdr)) +#define ETH_FCS_LEN 4 /* Octets in the FCS */ + struct e802_hdr { uchar et_dest[6]; /* Destination node */ uchar et_src[6]; /* Source node */ diff --git a/include/netdev.h b/include/netdev.h index 90140bd9bb..d96e1dabf9 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -57,6 +57,7 @@ int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); int ks8851_mll_initialize(u8 dev_num, int base_addr); int lan91c96_initialize(u8 dev_num, int base_addr); +int lpc32xx_eth_initialize(bd_t *bis); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); int mcdmafec_initialize(bd_t *bis); int mcffec_initialize(bd_t *bis); @@ -69,6 +70,7 @@ int natsemi_initialize(bd_t *bis); int ne2k_register(void); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); +int pch_gbe_register(bd_t *bis); int pcnet_initialize(bd_t *bis); int ppc_4xx_eth_initialize (bd_t *bis); int rtl8139_initialize(bd_t *bis); @@ -123,6 +125,9 @@ static inline int pci_eth_init(bd_t *bis) #ifdef CONFIG_E1000 num += e1000_initialize(bis); #endif +#ifdef CONFIG_PCH_GBE + num += pch_gbe_register(bis); +#endif #ifdef CONFIG_PCNET num += pcnet_initialize(bis); #endif diff --git a/include/usb_ether.h b/include/usb_ether.h index b38d037fbe..23507e19e6 100644 --- a/include/usb_ether.h +++ b/include/usb_ether.h @@ -18,7 +18,6 @@ #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ #define ETH_DATA_LEN 1500 /* Max. octets in payload */ #define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */ -#define ETH_FCS_LEN 4 /* Octets in the FCS */ struct ueth_data { /* eth info */ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 13af604e5f..8731fc64b4 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -275,7 +275,7 @@ $(obj)/%.dtb.S: $(obj)/%.dtb quiet_cmd_dtc = DTC $@ # Modified for U-Boot cmd_dtc = $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ - dtc -O dtb -o $@ -b 0 \ + $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index 349f77038e..ff4ce6e92c 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -5,6 +5,12 @@ PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config \ localmodconfig localyesconfig +# Added for U-Boot +# Linux has defconfig files in arch/$(SRCARCH)/configs/, +# on the other hand, U-Boot does in configs/. +# Set SRCARCH to .. fake this Makefile. +SRCARCH := .. + ifdef KBUILD_KCONFIG Kconfig := $(KBUILD_KCONFIG) else @@ -104,6 +110,10 @@ endif %_defconfig: $(obj)/conf $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) +# Added for U-Boot (backward compatibility) +%_config: %_defconfig + @: + configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config) define mergeconfig diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh deleted file mode 100755 index cc8a787f88..0000000000 --- a/scripts/multiconfig.sh +++ /dev/null @@ -1,102 +0,0 @@ -#!/bin/sh -# -# A wrapper script to adjust Kconfig for U-Boot -# -# This file will be removed after cleaning up defconfig files -# -# Copyright (C) 2014, Masahiro Yamada <yamada.m@jp.panasonic.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -set -e - -# Make a configuration target -# Usage: -# run_make_config <target> <objdir> -# <target>: Make target such as "config", "menuconfig", "defconfig", etc. -run_make_config () { - # Linux expects defconfig files in arch/$(SRCARCH)/configs/ directory, - # but U-Boot has them in configs/ directory. - # Give SRCARCH=.. to fake scripts/kconfig/Makefile. - $MAKE -f $srctree/scripts/Makefile.build obj=scripts/kconfig SRCARCH=.. $1 -} - -do_silentoldconfig () { - run_make_config silentoldconfig - - # If the following part fails, include/config/auto.conf should be - # deleted so "make silentoldconfig" will be re-run on the next build. - $MAKE -f $srctree/scripts/Makefile.autoconf || { - rm -f include/config/auto.conf - exit 1 - } - - # include/config.h has been updated after "make silentoldconfig". - # We need to touch include/config/auto.conf so it gets newer - # than include/config.h. - # Otherwise, 'make silentoldconfig' would be invoked twice. - touch include/config/auto.conf -} - -cleanup_after_defconfig () { - rm -f configs/.tmp_defconfig - # ignore 'Directory not empty' error - # without using non-POSIX option '--ignore-fail-on-non-empty' - rmdir arch configs 2>/dev/null || true -} - -# Usage: -# do_board_defconfig <board>_defconfig -do_board_defconfig () { - defconfig_path=$srctree/configs/$1 - - if [ ! -r $defconfig_path ]; then - echo >&2 "***" - echo >&2 "*** Can't find default configuration \"configs/$1\"!" - echo >&2 "***" - exit 1 - fi - - mkdir -p arch configs - # prefix "*:" is deprecated. Drop it simply. - sed -e 's/^[+A-Z]*://' $defconfig_path > configs/.tmp_defconfig - - run_make_config .tmp_defconfig || { - cleanup_after_defconfig - exit 1 - } - - cleanup_after_defconfig -} - -do_board_felconfig () { - do_board_defconfig ${1%%_felconfig}_defconfig - if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then - echo "$progname: Cannot felconfig a non-sunxi or non-SPL platform" >&2 - exit 1 - fi - sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y\nCONFIG_UART0_PORT_F=n/g' \ - .config -} - -do_others () { - run_make_config $1 -} - -progname=$(basename $0) -target=$1 - -case $target in -*_defconfig) - do_board_defconfig $target;; -*_felconfig) - do_board_felconfig $target;; -*_config) - # backward compatibility - do_board_defconfig ${target%_config}_defconfig;; -silentoldconfig) - do_silentoldconfig;; -*) - do_others $target;; -esac diff --git a/tools/Makefile b/tools/Makefile index 88770b0611..4bbb15336e 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \ imximage.o \ kwbimage.o \ lib/md5.o \ + lpc32xximage.o \ mxsimage.o \ omapimage.o \ os_support.o \ diff --git a/tools/buildman/README b/tools/buildman/README index cf7bf5c17e..e870d54c1f 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -613,7 +613,7 @@ $ ./tools/buildman/buildman -b us-mem4 -sSdB run_list_real 1996 2000 +4 do_nandboot 760 756 -4 do_mem_crc 168 68 -100 - colibri_t20_iris: all -9 rodata -29 text +20 + colibri_t20 : all -9 rodata -29 text +20 u-boot: add: 1/0, grow: 2/-3 bytes: 140/-112 (28) function old new delta hash_command 80 160 +80 diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c new file mode 100644 index 0000000000..6b3865f642 --- /dev/null +++ b/tools/lpc32xximage.c @@ -0,0 +1,178 @@ +/* + * Image manipulator for LPC32XX SoCs + * + * (C) Copyright 2015 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Derived from omapimage.c: + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby <john.rigby@linaro.org> + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include <compiler.h> +#include <image.h> + +/* + * NAND page 0 boot header + */ + +struct nand_page_0_boot_header { + uint32_t data[129]; + uint32_t pad[383]; +}; + +/* + * Default ICC (interface configuration data [sic]) if none specified + * in board config + */ + +#ifndef LPC32XX_BOOT_ICR +#define LPC32XX_BOOT_ICR 0x00000096 +#endif + +/* + * Default boot NAND page size if none specified in board config + */ + +#ifndef LPC32XX_BOOT_NAND_PAGESIZE +#define LPC32XX_BOOT_NAND_PAGESIZE 2048 +#endif + +/* + * Default boot NAND pages per sector if none specified in board config + */ + +#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR +#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64 +#endif + +/* + * Maximum size for boot code is 56K unless defined in board config + */ + +#ifndef LPC32XX_BOOT_CODESIZE +#define LPC32XX_BOOT_CODESIZE (56*1024) +#endif + +/* signature byte for a readable block */ + +#define LPC32XX_BOOT_BLOCK_OK 0xaa + +static struct nand_page_0_boot_header lpc32xximage_header; + +static int lpc32xximage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_LPC32XXIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static int lpc32xximage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + + /* turn image size from bytes to NAND pages, page 0 included */ + int image_size_in_pages = ((image_size - 1) + / LPC32XX_BOOT_NAND_PAGESIZE); + + if (hdr->data[0] != (0xff & LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[1] != (0xff & ~LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[2] != (0xff & LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[3] != (0xff & ~LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[4] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[5] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[6] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[7] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[8] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[9] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[10] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[11] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[12] != LPC32XX_BOOT_BLOCK_OK) + return -1; + if (hdr->data[128] != LPC32XX_BOOT_BLOCK_OK) + return -1; + return 0; +} + +static void print_hdr_byte(struct nand_page_0_boot_header *hdr, int ofs) +{ + printf("header[%d] = %02x\n", ofs, hdr->data[ofs]); +} + +static void lpc32xximage_print_header(const void *ptr) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int ofs; + + for (ofs = 0; ofs <= 12; ofs++) + print_hdr_byte(hdr, ofs); + print_hdr_byte(hdr, 128); +} + +static void lpc32xximage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + + /* turn image size from bytes to NAND pages, page 0 included */ + int image_size_in_pages = ((sbuf->st_size + + LPC32XX_BOOT_NAND_PAGESIZE - 1) + / LPC32XX_BOOT_NAND_PAGESIZE); + + /* fill header -- default byte value is 0x00, not 0xFF */ + memset((void *)hdr, 0, sizeof(*hdr)); + hdr->data[0] = (hdr->data[2] = 0xff & LPC32XX_BOOT_ICR); + hdr->data[1] = (hdr->data[3] = 0xff & ~LPC32XX_BOOT_ICR); + hdr->data[4] = (hdr->data[6] = (hdr->data[8] + = (hdr->data[10] = 0xff & image_size_in_pages))); + hdr->data[5] = (hdr->data[7] = (hdr->data[9] + = (hdr->data[11] = 0xff & ~image_size_in_pages))); + hdr->data[12] = (hdr->data[128] = LPC32XX_BOOT_BLOCK_OK); +} + +/* + * lpc32xximage parameters + */ +U_BOOT_IMAGE_TYPE( + lpc32xximage, + "LPC32XX Boot Image", + sizeof(lpc32xximage_header), + (void *)&lpc32xximage_header, + NULL, + lpc32xximage_verify_header, + lpc32xximage_print_header, + lpc32xximage_set_header, + NULL, + lpc32xximage_check_image_types, + NULL, + NULL +); diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index 6971b91314..8eee72e257 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -214,14 +214,10 @@ int main(int argc, char **argv) } ret = close(txt_fd); } - /* The +1 is for the additionnal ending \0. See below. */ - if (filesize + 1 > envsize) { - fprintf(stderr, "The input file is larger than the environment partition size\n"); - return EXIT_FAILURE; - } - /* Replace newlines separating variables with \0 */ - for (fp = 0, ep = 0 ; fp < filesize ; fp++) { + /* Parse a byte at time until reaching the file OR until the environment fills + * up. Check ep against envsize - 1 to allow for extra trailing '\0'. */ + for (fp = 0, ep = 0 ; fp < filesize && ep < envsize - 1; fp++) { if (filebuf[fp] == '\n') { if (fp == 0 || filebuf[fp-1] == '\n') { /* @@ -249,6 +245,25 @@ int main(int argc, char **argv) envptr[ep++] = filebuf[fp]; } } + /* If there are more bytes in the file still, it means the env filled up + * before parsing the whole file. Eat comments & whitespace here to see if + * there was anything meaning full left in the file, and if so, throw a error + * and exit. */ + for( ; fp < filesize; fp++ ) + { + if (filebuf[fp] == '\n') { + if (fp == 0 || filebuf[fp-1] == '\n') { + /* Ignore blank lines */ + continue; + } + } else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') { + while (++fp < filesize && filebuf[fp] != '\n') + continue; + } else { + fprintf(stderr, "The environment file is too large for the target environment storage\n"); + return EXIT_FAILURE; + } + } /* * Make sure there is a final '\0' * And do it again on the next byte to mark the end of the environment. |