diff options
| -rw-r--r-- | board/Marvell/mvebu_armada-37xx/board.c | 47 | ||||
| -rw-r--r-- | board/solidrun/clearfog/clearfog.c | 3 | ||||
| -rw-r--r-- | configs/dns325_defconfig | 2 | ||||
| -rw-r--r-- | configs/mvebu_espressobin-88f3720_defconfig | 2 | ||||
| -rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 1 | ||||
| -rw-r--r-- | drivers/pci/pci-aardvark.c | 5 | ||||
| -rw-r--r-- | include/configs/mvebu_armada-37xx.h | 4 |
7 files changed, 63 insertions, 1 deletions
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 7b9c3223ed..eacee15cb3 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -5,6 +5,7 @@ #include <common.h> #include <dm.h> +#include <env.h> #include <i2c.h> #include <init.h> #include <phy.h> @@ -50,6 +51,22 @@ DECLARE_GLOBAL_DATA_PTR; #define MVEBU_G2_SMI_PHY_CMD_REG (24) #define MVEBU_G2_SMI_PHY_DATA_REG (25) +/* + * Memory Controller Registers + * + * Assembled based on public information: + * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336 + * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332 + * + * And checked against the written register values for the various topologies: + * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h + */ +#define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4) +#define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf +#define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4 +#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2 +#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3 + int board_early_init_f(void) { return 0; @@ -63,6 +80,36 @@ int board_init(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + bool ddr4, emmc; + + if (env_get("fdtfile")) + return 0; + + if (!of_machine_is_compatible("globalscale,espressobin")) + return 0; + + /* If the memory controller has been configured for DDR4, we're running on v7 */ + ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS) + & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4; + + emmc = of_machine_is_compatible("globalscale,espressobin-emmc"); + + if (ddr4 && emmc) + env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb"); + else if (ddr4) + env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb"); + else if (emmc) + env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb"); + else + env_set("fdtfile", "marvell/armada-3720-espressobin.dtb"); + + return 0; +} +#endif + /* Board specific AHCI / SATA enable code */ int board_ahci_enable(void) { diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index d5535ebebe..92443d5177 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -240,6 +240,9 @@ int board_eth_init(struct bd_info *bis) int board_late_init(void) { + if (env_get("fdtfile")) + return 0; + cf_read_tlv_data(); if (sr_product_is(&cf_tlv_data, "Clearfog Base")) diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 8a04e1492c..a5fe9cd331 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 -CONFIG_NR_DRAM_BANKS=2 +CONFIG_NR_DRAM_BANKS=1 CONFIG_TARGET_DNS325=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 7aabbba59f..559aeb076f 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -84,3 +84,5 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_SHA1=y CONFIG_SHA256=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_BOARD_LATE_INIT=y diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 114ebacde1..bc9d4f7e9f 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -151,6 +151,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, + { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index b2c417701f..babb84ca93 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -647,10 +647,15 @@ static int pcie_advk_probe(struct udevice *dev) static int pcie_advk_remove(struct udevice *dev) { struct pcie_advk *pcie = dev_get_priv(dev); + u32 reg; if (dm_gpio_is_valid(&pcie->reset_gpio)) dm_gpio_set_value(&pcie->reset_gpio, 1); + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg &= ~LINK_TRAINING_EN; + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + return 0; } diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 905ce09b7a..27428d5a0f 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -6,6 +6,8 @@ #ifndef _CONFIG_MVEBU_ARMADA_37XX_H #define _CONFIG_MVEBU_ARMADA_37XX_H +#include <linux/sizes.h> + /* * High Level Configuration Options (easy to change) */ @@ -13,6 +15,8 @@ /* additions for new ARM relocation support */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + /* auto boot */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |