diff options
58 files changed, 3397 insertions, 359 deletions
@@ -375,6 +375,10 @@ KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ KBUILD_CFLAGS += -fshort-wchar KBUILD_AFLAGS := -D__ASSEMBLY__ +# Don't generate position independent code +KBUILD_CFLAGS += $(call cc-option,-fno-PIE) +KBUILD_AFLAGS += $(call cc-option,-fno-PIE) + # Read UBOOTRELEASE from include/config/uboot.release (if it exists) UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) diff --git a/arch/arm/dts/axp81x.dtsi b/arch/arm/dts/axp81x.dtsi new file mode 100644 index 0000000000..043c717dce --- /dev/null +++ b/arch/arm/dts/axp81x.dtsi @@ -0,0 +1,169 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* AXP813/818 Integrated Power Management Chip */ + +&axp81x { + interrupt-controller; + #interrupt-cells = <1>; + + axp_adc: adc { + compatible = "x-powers,axp813-adc"; + #io-channel-cells = <1>; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp813-gpio"; + gpio-controller; + #gpio-cells = <2>; + + gpio0_ldo: gpio0-ldo { + pins = "GPIO0"; + function = "ldo"; + }; + + gpio1_ldo: gpio1-ldo { + pins = "GPIO1"; + function = "ldo"; + }; + }; + + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp813-battery-power-supply"; + status = "disabled"; + }; + + regulators { + /* Default work frequency for buck regulators */ + x-powers,dcdc-freq = <3000>; + + reg_dcdc1: dcdc1 { + }; + + reg_dcdc2: dcdc2 { + }; + + reg_dcdc3: dcdc3 { + }; + + reg_dcdc4: dcdc4 { + }; + + reg_dcdc5: dcdc5 { + }; + + reg_dcdc6: dcdc6 { + }; + + reg_dcdc7: dcdc7 { + }; + + reg_aldo1: aldo1 { + }; + + reg_aldo2: aldo2 { + }; + + reg_aldo3: aldo3 { + }; + + reg_dldo1: dldo1 { + }; + + reg_dldo2: dldo2 { + }; + + reg_dldo3: dldo3 { + }; + + reg_dldo4: dldo4 { + }; + + reg_eldo1: eldo1 { + }; + + reg_eldo2: eldo2 { + }; + + reg_eldo3: eldo3 { + }; + + reg_fldo1: fldo1 { + }; + + reg_fldo2: fldo2 { + }; + + reg_fldo3: fldo3 { + }; + + reg_ldo_io0: ldo-io0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_ldo>; + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_ldo_io1: ldo-io1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_ldo>; + /* Disable by default to avoid conflicts with GPIO */ + status = "disabled"; + }; + + reg_rtc_ldo: rtc-ldo { + /* RTC_LDO is a fixed, always-on regulator */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sw: sw { + }; + + reg_drivevbus: drivevbus { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts index c8495d7624..36ecebaff3 100644 --- a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts +++ b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts @@ -44,6 +44,8 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include <dt-bindings/gpio/gpio.h> + / { model = "Allwinner A83T H8Homlet Proto Dev Board v2.0"; compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t"; @@ -55,22 +57,213 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reg_usb0_vbus: reg-usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; }; &ehci0 { status = "okay"; }; +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + &ohci0 { status = "okay"; }; +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp818", "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ephy"; +}; + +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + regulator-name = "vcc-wifi"; +}; + &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; &usb_otg { + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts index dfc16a0272..eaff6fa401 100644 --- a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts @@ -1,6 +1,7 @@ /* - * Copyright 2015 Vishnu Patekar - * Vishnu Patekar <vishnupatekar0510@gmail.com> + * Copyright 2017 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -44,29 +45,316 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include <dt-bindings/gpio/gpio.h> + / { - model = "Allwinner A83T BananaPi M3 Board v1.2"; - compatible = "bananapi,m3v1.2", "allwinner,sun8i-a83t"; + model = "Banana Pi BPI-M3"; + compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "bananapi-m3:blue:usr"; + gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "bananapi-m3:green:usr"; + gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; +}; + +&de { + status = "okay"; }; &ehci0 { + /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ status = "okay"; + + /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_sw>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + allwinner,rx-delay-ps = <700>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + fldoin-supply = <®_dcdc5>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + /* schematics says 3.1V but FEX file says 3.3V */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + /* + * This powers both the WiFi/BT module's main power, I/O supply, + * and external pull-ups on all the data lines. It should be set + * to the same voltage as the I/O supply (DCDC1 in this case) to + * avoid any leakage or mismatch. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pd"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_fldo1 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-name = "vcc-ephy"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &usb_otg { status = "okay"; }; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts index 8437c8f59e..5dba4fc310 100644 --- a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts @@ -45,33 +45,353 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include <dt-bindings/gpio/gpio.h> + / { model = "Cubietech Cubietruck Plus"; compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "cubietruck-plus:blue:usr"; + gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ + }; + + orange { + label = "cubietruck-plus:orange:usr"; + gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */ + }; + + white { + label = "cubietruck-plus:white:usr"; + gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */ + }; + + green { + label = "cubietruck-plus:green:usr"; + gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ + }; + }; + + usb-hub { + /* I2C is not connected */ + compatible = "smsc,usb3503"; + initial-mode = <1>; /* initialize in HUB mode */ + disabled-ports = <1>; + intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */ + connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + refclk-frequency = <19200000>; + }; + + reg_usb1_vbus: reg-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */ + }; + + reg_usb2_vbus: reg-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + /* The WiFi low power clock must be 32768 Hz */ + assigned-clocks = <&ac100_rtc 1>; + assigned-clock-rates = <32768>; + /* enables internal regulator and de-asserts reset */ + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + }; }; &ehci0 { + /* GL830 USB-to-SATA bridge here */ status = "okay"; }; &ehci1 { + /* USB3503 HSIC USB 2.0 hub here */ + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_dldo4>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&mdio { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_sw>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp818", "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; +}; + +#include "axp81x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1v8"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dram-pll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + /* + * The schematics say this should be 3.3V, but the FEX file says + * it should be 3V. The latter makes sense, as the WiFi module's + * I/O is indirectly powered from DCDC1, through SW. It is rated + * at 2.98V maximum. + */ + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpua"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-sys"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "dp-pwr"; +}; + +®_dldo3 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "ephy-io"; +}; + +®_dldo4 { + /* + * The PHY requires 20ms after all voltages are applied until core + * logic is ready and 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ephy"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-1"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dp-bridge-2"; +}; + +®_fldo1 { + /* TODO should be handled by USB PHY */ + regulator-always-on; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd12-hsic"; +}; + +®_fldo2 { + /* + * Despite the embedded CPUs core not being used in any way, + * this must remain on or the system will hang. + */ + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpus"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +®_sw { + regulator-name = "vcc-wifi-io"; +}; + +&spdif { status = "okay"; }; &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; &usb_otg { status = "okay"; }; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/dts/sun8i-a83t-tbs-a711.dts index 80e8b1cc90..1537ce148c 100644 --- a/arch/arm/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/dts/sun8i-a83t-tbs-a711.dts @@ -1,6 +1,6 @@ /* - * Copyright 2017 OndÅ™ej Jirman - * OndÅ™ej Jirman <megous@megous.com> + * Copyright (C) 2017 Touchless Biometric Systems AG + * Tomas Novotny <tomas@novotny.cz> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -44,33 +44,380 @@ /dts-v1/; #include "sun8i-a83t.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pwm/pwm.h> + / { model = "TBS A711 Tablet"; compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t"; aliases { serial0 = &uart0; + serial1 = &uart1; }; chosen { stdout-path = "serial0:115200n8"; }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>; + + brightness-levels = <0 1 2 4 8 16 32 64 128 255>; + default-brightness-level = <9>; + }; + + panel { + compatible = "tbs,a711-panel", "panel-lvds"; + backlight = <&backlight>; + power-supply = <®_sw>; + + width-mm = <153>; + height-mm = <90>; + data-mapping = "vesa-24"; + + panel-timing { + /* 1024x600 @60Hz */ + clock-frequency = <52000000>; + hactive = <1024>; + vactive = <600>; + hsync-len = <20>; + hfront-porch = <180>; + hback-porch = <160>; + vfront-porch = <12>; + vback-porch = <23>; + vsync-len = <5>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; + + reg_vbat: reg-vbat { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + reg_vmain: reg-vmain { + compatible = "regulator-fixed"; + regulator-name = "vmain"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vbat>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ + + /* + * This is actually Bluetooth's clock, but we have to + * hook it up somewheere + */ + clocks = <&ac100_rtc 1>; + clock-names = "ext_clock"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&cpu100 { + cpu-supply = <®_dcdc3>; +}; + +&de { + status = "okay"; }; +/* + * An USB-2 hub is connected here, which also means we don't need to + * enable the OHCI controller. + */ &ehci0 { status = "okay"; }; -&ohci0 { +/* + * There's a modem connected here that needs to be initialised before + * being able to be enumerated. + */ +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + non-removable; + wakeup-source; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-0 = <&mmc2_8bit_emmc_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pin>; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp81x: pmic@3a3 { + compatible = "x-powers,axp813"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + swin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; + +}; + +#include "axp81x.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-1.8"; +}; + +®_aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-name = "vdd-drampll"; +}; + +®_aldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-name = "vcc-io"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-A"; +}; + +®_dcdc3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpu-B"; +}; + +®_dcdc4 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-name = "vcc-dram"; +}; + +®_dcdc6 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-name = "vdd-sys"; +}; + +®_dldo1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <4200000>; + regulator-name = "vcc-mipi"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; status = "okay"; }; +®_eldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-r"; +}; + +®_eldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dsi"; +}; + +®_eldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-csi-f"; +}; + +®_fldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-hsic"; +}; + +®_fldo2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-name = "vdd-cpus"; +}; + +®_ldo_io0 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-ctp"; + status = "okay"; +}; + +®_ldo_io1 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-vb"; + status = "okay"; +}; + +®_sw { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-name = "vcc-lcd"; +}; + +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_lvds_pins>; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + &uart0 { pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_b>; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +/* There's the BT part of the AP6210 connected to that UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; status = "okay"; }; &usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus_supply = <®_vmain>; + usb2_vbus_supply = <®_vmain>; status = "okay"; }; diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi index 2953e0fdac..2be23d6009 100644 --- a/arch/arm/dts/sun8i-a83t.dtsi +++ b/arch/arm/dts/sun8i-a83t.dtsi @@ -40,67 +40,99 @@ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "skeleton.dtsi" - #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/clock/sun8i-a83t-ccu.h> +#include <dt-bindings/clock/sun8i-de2.h> +#include <dt-bindings/clock/sun8i-r-ccu.h> +#include <dt-bindings/reset/sun8i-a83t-ccu.h> +#include <dt-bindings/reset/sun8i-de2.h> +#include <dt-bindings/reset/sun8i-r-ccu.h> / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { + clocks = <&ccu CLK_C0CPUX>; + clock-names = "cpu"; compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <1>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <3>; }; - cpu@100 { + cpu100: cpu@100 { + clocks = <&ccu CLK_C1CPUX>; + clock-names = "cpu"; compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x100>; }; cpu@101 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x101>; }; cpu@102 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x102>; }; cpu@103 { compatible = "arm,cortex-a7"; device_type = "cpu"; + operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; + enable-method = "allwinner,sun8i-a83t-smp"; reg = <0x103>; }; }; @@ -123,6 +155,7 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; @@ -148,48 +181,575 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-a83t-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + + memory { + reg = <0x40000000 0x80000000>; + device_type = "memory"; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1128000000 { + opp-hz = /bits/ 64 <1128000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + + cpu1_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1128000000 { + opp-hz = /bits/ 64 <1128000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <840000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - pio: pinctrl@01c20800 { + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-a83t-de2-clk"; + reg = <0x01000000 0x100000>; + clocks = <&ccu CLK_PLL_DE>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-0"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mixer0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@1200000 { + compatible = "allwinner,sun8i-a83t-de2-mixer-1"; + reg = <0x01200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_WB>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + + mixer1_out_tcon1: endpoint { + remote-endpoint = <&tcon1_in_mixer1>; + }; + }; + }; + }; + + cpucfg@1700000 { + compatible = "allwinner,sun8i-a83t-cpucfg"; + reg = <0x01700000 0x400>; + }; + + cci@1790000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01790000 0x10000>; + ranges = <0x0 0x01790000 0x10000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + syscon: syscon@1c00000 { + compatible = "allwinner,sun8i-a83t-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; + }; + + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-a83t-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c0d000 0x1000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON1>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + reg = <0>; + + tcon1_in_mixer1: endpoint { + remote-endpoint = <&mixer1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + }; + }; + }; + }; + + mmc0: mmc@1c0f000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-a83t-mmc", + "allwinner,sun7i-a20-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-a83t-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + sid: eeprom@1c14000 { + compatible = "allwinner,sun8i-a83t-sid"; + reg = <0x1c14000 0x400>; + }; + + usb_otg: usb@1c19000 { + compatible = "allwinner,sun8i-a83t-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@1c19400 { + compatible = "allwinner,sun8i-a83t-usb-phy"; + reg = <0x01c19400 0x10>, + <0x01c1a800 0x14>, + <0x01c1b800 0x14>; + reg-names = "phy_ctrl", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_HSIC>, + <&ccu CLK_USB_HSIC_12M>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb2_hsic_12M"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_HSIC>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@1c1a000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>; + resets = <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@1c1a400 { + compatible = "allwinner,sun8i-a83t-ohci", + "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@1c1b000 { + compatible = "allwinner,sun8i-a83t-ehci", + "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@1c20000 { + compatible = "allwinner,sun8i-a83t-ccu"; + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc16Md512>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@1c20800 { compatible = "allwinner,sun8i-a83t-pinctrl"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; reg = <0x01c20800 0x400>; - clocks = <&osc24M>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + emac_rgmii_pins: emac-rgmii-pins { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD11", "PD12", "PD13", "PD14", "PD18", + "PD19", "PD21", "PD22", "PD23"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + + hdmi_pins: hdmi-pins { + pins = "PH6", "PH7", "PH8"; + function = "hdmi"; + }; + + i2c0_pins: i2c0-pins { + pins = "PH0", "PH1"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH2", "PH3"; + function = "i2c1"; + }; + + i2c2_ph_pins: i2c2-ph-pins { + pins = "PH4", "PH5"; + function = "i2c2"; + }; + + i2s1_pins: i2s1-pins { + /* I2S1 does not have external MCLK pin */ + pins = "PG10", "PG11", "PG12", "PG13"; + function = "i2s1"; + }; + + lcd_lvds_pins: lcd-lvds-pins { + pins = "PD18", "PD19", "PD20", "PD21", "PD22", + "PD23", "PD24", "PD25", "PD26", "PD27"; + function = "lvds0"; + }; + + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { + pins = "PC5", "PC6", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", + "PC14", "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + pwm_pin: pwm-pin { + pins = "PD28"; + function = "pwm"; + }; + + spdif_tx_pin: spdif-tx-pin { + pins = "PE18"; + function = "spdif"; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB9", "PB10"; + function = "uart0"; + }; + + uart0_pf_pins: uart0-pf-pins { + pins = "PF2", "PF4"; + function = "uart0"; }; - uart0_pins_a: uart0@0 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart1_pins: uart1-pins { + pins = "PG6", "PG7"; + function = "uart1"; }; - uart0_pins_b: uart0@1 { - allwinner,pins = "PB9", "PB10"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + uart1_rts_cts_pins: uart1-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; }; }; - timer@01c20c00 { + timer@1c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -197,27 +757,166 @@ clocks = <&osc24M>; }; - watchdog@01c20ca0 { + watchdog@1c20ca0 { compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc24M>; }; - uart0: serial@01c28000 { + spdif: spdif@1c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-spdif", + "allwinner,sun8i-h3-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + resets = <&ccu RST_BUS_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "disabled"; + }; + + i2s0: i2s@1c22000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; + clock-names = "apb", "mod"; + dmas = <&dma 3>, <&dma 3>; + resets = <&ccu RST_BUS_I2S0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22400 0x400>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_pins>; + status = "disabled"; + }; + + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a83t-i2s"; + reg = <0x01c22800 0x400>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma 27>; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "tx"; + status = "disabled"; + }; + + pwm: pwm@1c21400 { + compatible = "allwinner,sun8i-a83t-pwm", + "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; - gic: interrupt-controller@01c81000 { + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + i2c0: i2c@1c2ac00 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun8i-a83t-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x104>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu 13>; + reset-names = "stmmaceth"; + clocks = <&ccu 27>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; @@ -225,59 +924,107 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; - usb_otg: usb@01c19000 { - compatible = "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x400>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon1: endpoint { + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; }; - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-a83t-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x14>, - <0x01c1b800 0x14>; - reg-names = "phy_ctrl", - "pmu1", - "pmu2"; - status = "disabled"; - #phy-cells = <1>; + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun8i-a83t-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; }; - ehci0: usb@01c1a000 { - compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; + r_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun8i-a83t-r-intc", + "allwinner,sun6i-a31-r-intc"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c00 0x400>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; - ohci0: usb@01c1a400 { - compatible = "allwinner,sun8i-a83t-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; + r_ccu: clock@1f01400 { + compatible = "allwinner,sun8i-a83t-r-ccu"; + reg = <0x01f01400 0x400>; + clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, + <&ccu 6>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; }; - ehci1: usb@01c1b000 { - compatible = "allwinner,sun8i-a83t-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; + r_cpucfg@1f01c00 { + compatible = "allwinner,sun8i-a83t-r-cpucfg"; + reg = <0x1f01c00 0x400>; }; - r_pio: pinctrl@01f02c00 { + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a83t-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_rsb_pins: r-rsb-pins { + pins = "PL0", "PL1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; + }; + }; + + r_rsb: rsb@1f03400 { + compatible = "allwinner,sun8i-a83t-rsb", + "allwinner,sun8i-a23-rsb"; + reg = <0x01f03400 0x400>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_APB0_RSB>; + clock-frequency = <3000000>; + resets = <&r_ccu RST_APB0_RSB>; + pinctrl-names = "default"; + pinctrl-0 = <&r_rsb_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index 28c9158302..25fb048c7d 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -1,5 +1,6 @@ /* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -43,6 +44,8 @@ /dts-v1/; #include "sun8i-r40.dtsi" +#include <dt-bindings/gpio/gpio.h> + / { model = "Banana Pi BPI-M2-Ultra"; compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; @@ -55,17 +58,47 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led-green { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + + user-led-blue { + label = "bananapi:blue:user"; + gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + }; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; +&ehci1 { status = "okay"; }; -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; +&ehci2 { status = "okay"; }; @@ -74,6 +107,7 @@ pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; phy-mode = "rgmii"; + phy-supply = <®_dc1sw>; status = "okay"; }; @@ -83,3 +117,123 @@ reg = <1>; }; }; + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-gmac-phy"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 2cdfb54282..bd97ca3dc2 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -1,7 +1,6 @@ /* - * Copyright 2016 Chen-Yu Tsai - * - * Chen-Yu Tsai <wens@csie.org> + * Copyright 2017 Chen-Yu Tsai <wens@csie.org> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -51,24 +50,19 @@ #size-cells = <1>; interrupt-parent = <&gic>; - aliases { - }; - - chosen { - }; - clocks { #address-cells = <1>; #size-cells = <1>; ranges; - osc24M: osc24M_clk { + osc24M: osc24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -80,7 +74,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { + cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; @@ -105,11 +99,6 @@ }; }; - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -140,6 +129,122 @@ #size-cells = <0>; }; + mmc1: mmc@1c10000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@1c11000 { + compatible = "allwinner,sun8i-r40-emmc", + "allwinner,sun50i-a64-emmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + pinctrl-0 = <&mmc2_pins>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc3: mmc@1c12000 { + compatible = "allwinner,sun8i-r40-mmc", + "allwinner,sun50i-a64-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC3>; + reset-names = "ahb"; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI1>; + resets = <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI2>; + resets = <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; @@ -153,8 +258,7 @@ compatible = "allwinner,sun8i-r40-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - /* apb should be replaced once CCU is implemented */ - clocks = <&osc24M>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -174,10 +278,9 @@ drive-strength = <40>; }; - i2c0_pins: i2c0_pins { + i2c0_pins: i2c0-pins { pins = "PB0", "PB1"; function = "i2c0"; - bias-pull-up; }; mmc0_pins: mmc0-pins { @@ -188,20 +291,119 @@ bias-pull-up; }; - uart0_pb_pins: uart0_pb_pins { + mmc1_pg_pins: mmc1-pg-pins { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC5", "PC6", "PC7", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC24"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; - bias-pull-up; }; }; + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@1c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@1c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@1c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@1c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@1c29400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29400 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + uart6: serial@1c29800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29800 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART6>; + resets = <&ccu RST_BUS_UART6>; + status = "disabled"; + }; + + uart7: serial@1c29c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29c00 0x400>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART7>; + resets = <&ccu RST_BUS_UART7>; status = "disabled"; }; @@ -209,7 +411,54 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@1c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@1c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@1c2b800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b800 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@1c2c000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2c000 0x400>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -237,7 +486,7 @@ }; gic: interrupt-controller@1c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x1000>, <0x01c84000 0x2000>, @@ -254,7 +503,5 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; }; }; diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts index 193d9b29ec..35859d8f32 100644 --- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts @@ -56,6 +56,40 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led { + label = "bananapi:green:user"; + gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ + }; +}; + +&ehci1 { + /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */ + status = "okay"; }; &i2c0 { @@ -125,8 +159,24 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo2>; + vqmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; status = "okay"; }; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index f568def8b4..41a9b0fc47 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -20,7 +20,7 @@ #define SUNXI_DMA_BASE 0x03002000 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ #define SUNXI_SIDC_BASE 0x03006000 -#define SNUXI_SID_BASE 0x03006200 +#define SUNXI_SID_BASE 0x03006200 #define SUNXI_TIMER_BASE 0x03009000 #define SUNXI_PIO_BASE 0x0300B000 #define SUNXI_PSI_BASE 0x0300C000 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 558363b52d..686f38fec4 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -417,7 +417,6 @@ config DRAM_ZQ config DRAM_ODT_EN bool "sunxi dram odt enable" - default n if !MACH_SUN8I_A23 default y if MACH_SUN8I_A23 default y if MACH_SUN8I_R40 default y if MACH_SUN50I diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 392c258945..93f61f2fa4 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -3,26 +3,26 @@ if TARGET_COREBOOT config SYS_COREBOOT bool default y + imply SYS_NS16550 + imply SCSI + imply SCSI_AHCI imply AHCI_PCI - imply E1000 - imply ICH_SPI imply MMC imply MMC_PCI imply MMC_SDHCI imply MMC_SDHCI_SDMA - imply SCSI - imply SCSI_AHCI - imply SPI_FLASH - imply SYS_NS16550 imply USB imply USB_EHCI_HCD imply USB_XHCI_HCD + imply USB_STORAGE + imply USB_KEYBOARD imply VIDEO_COREBOOT + imply E1000 + imply ETH_DESIGNWARE + imply PCH_GBE + imply RTL8169 imply CMD_CBFS imply FS_CBFS - -config CBMEM_CONSOLE - bool - default y + imply CBMEM_CONSOLE endif diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 69025c1537..a6fd3a849a 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -7,6 +7,7 @@ #include <common.h> #include <fdtdec.h> +#include <usb.h> #include <asm/io.h> #include <asm/msr.h> #include <asm/mtrr.h> @@ -75,12 +76,10 @@ int last_stage_init(void) if (gd->flags & GD_FLG_COLD_BOOT) timestamp_add_to_bootstage(); - board_final_cleanup(); + /* start usb so that usb keyboard can be used as input device */ + usb_init(); - return 0; -} + board_final_cleanup(); -int misc_init_r(void) -{ return 0; } diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 37e4fdc760..fa717bc096 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -6,6 +6,7 @@ dtb-y += bayleybay.dtb \ chromebox_panther.dtb \ chromebook_samus.dtb \ conga-qeval20-qa3-e3845.dtb \ + coreboot.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ @@ -17,7 +18,6 @@ dtb-y += bayleybay.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ theadorable-x86-dfi-bt700.dtb \ - broadwell_som-6896.dtb \ baytrail_som-db5800-som-6867.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 9683c525a7..291dc07ff6 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -15,7 +15,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Intel Bayley Bay"; diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts deleted file mode 100644 index ec691f136a..0000000000 --- a/arch/x86/dts/broadwell_som-6896.dts +++ /dev/null @@ -1,52 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" -/include/ "serial.dtsi" -/include/ "reset.dtsi" -/include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" - -/ { - model = "Advantech SOM-6896"; - compatible = "advantech,som-6896", "intel,broadwell"; - - aliases { - spi0 = &spi; - }; - - config { - silent_console = <0>; - }; - - chosen { - stdout-path = "/serial"; - }; - - pci { - compatible = "pci-x86"; - #address-cells = <3>; - #size-cells = <2>; - u-boot,dm-pre-reloc; - ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 - 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 - 0x01000000 0x0 0x2000 0x2000 0 0xe000>; - - pch@1f,0 { - reg = <0x0000f800 0 0 0 0>; - compatible = "intel,pch9"; - - spi: spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich9-spi"; - spi-flash@0 { - reg = <0>; - compatible = "winbond,w25q128", "spi-flash"; - memory-map = <0xff000000 0x01000000>; - }; - }; - }; - }; - -}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 115a088a7a..f9f0979730 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -8,7 +8,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Link"; diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 9c48c9a3fa..b58936b4ac 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -8,7 +8,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Samus"; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index a72a85ef9c..f56e482944 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -5,7 +5,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Google Panther"; diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts new file mode 100644 index 0000000000..e212f3dc7d --- /dev/null +++ b/arch/x86/dts/coreboot.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * + * Generic coreboot payload device tree for x86 targets + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "keyboard.dtsi" +/include/ "reset.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "coreboot x86 payload"; + compatible = "coreboot,x86-payload"; + + aliases { + serial0 = &serial; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + tsc-timer { + clock-frequency = <1000000000>; + }; + + pci { + compatible = "pci-x86"; + u-boot,dm-pre-reloc; + }; + + coreboot-fb { + compatible = "coreboot-fb"; + }; +}; diff --git a/arch/x86/dts/coreboot_fb.dtsi b/arch/x86/dts/coreboot_fb.dtsi deleted file mode 100644 index 7d72f18537..0000000000 --- a/arch/x86/dts/coreboot_fb.dtsi +++ /dev/null @@ -1,5 +0,0 @@ -/ { - coreboot-fb { - compatible = "coreboot-fb"; - }; -}; diff --git a/arch/x86/dts/efi-x86_payload.dts b/arch/x86/dts/efi-x86_payload.dts index 19f253064b..5ccb986774 100644 --- a/arch/x86/dts/efi-x86_payload.dts +++ b/arch/x86/dts/efi-x86_payload.dts @@ -30,6 +30,10 @@ stdout-path = "/serial"; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 02ab4c160a..6c65fb9611 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -14,7 +14,6 @@ /include/ "reset.dtsi" /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -/include/ "coreboot_fb.dtsi" / { model = "Intel Minnowboard Max"; diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index cfa1d50ee4..5bd6465d98 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -9,35 +9,15 @@ config SYS_VENDOR config SYS_SOC default "coreboot" +config SYS_CONFIG_NAME + default "coreboot" + config SYS_TEXT_BASE default 0x01110000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - imply SPI_FLASH_ATMEL - imply SPI_FLASH_EON - imply SPI_FLASH_GIGADEVICE - imply SPI_FLASH_MACRONIX - imply SPI_FLASH_SPANSION - imply SPI_FLASH_STMICRO - imply SPI_FLASH_SST - imply SPI_FLASH_WINBOND - -comment "coreboot-specific options" - -config SYS_CONFIG_NAME - string "Board configuration file" - default "qemu-x86" - help - This option selects the board configuration file in include/configs/ - directory to be used to build U-Boot for coreboot. - -config DEFAULT_DEVICE_TREE - string "Board Device Tree Source (dts) file" - default "qemu-x86_i440fx" - help - This option selects the board Device Tree Source (dts) file in - arch/x86/dts/ directory to be used to build U-Boot for coreboot. + select BOARD_EARLY_INIT_R config SYS_CAR_ADDR hex "Board specific Cache-As-RAM (CAR) address" diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index ea0f3ee1ae..8db7cc62f3 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -10,4 +10,4 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -obj-y += coreboot_start.o +obj-y += start.o coreboot.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c new file mode 100644 index 0000000000..ed5606d4a4 --- /dev/null +++ b/board/coreboot/coreboot/coreboot.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> + +int board_early_init_r(void) +{ + /* + * Make sure PCI bus is enumerated so that peripherals on the PCI bus + * can be discovered by their drivers + */ + pci_init(); + + return 0; +} diff --git a/board/coreboot/coreboot/coreboot_start.S b/board/coreboot/coreboot/start.S index aa702622d4..aa702622d4 100644 --- a/board/coreboot/coreboot/coreboot_start.S +++ b/board/coreboot/coreboot/start.S diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850 index 519267e2f0..f24e8b5342 100644 --- a/board/davinci/da8xxevm/README.da850 +++ b/board/davinci/da8xxevm/README.da850 @@ -112,6 +112,25 @@ uflash writes the AIS image at offset 117. For compatibility with uflash, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is set to take into account this offset, and the dd command is adjusted accordingly. +Flashing the images to NOR +========================== +NOR Flash is XIP (execute-in-place), so no AIS (or SPL) is needed. The +u-boot.bin is directy flashed, but CONFIT_DA850_LOWLEVEL must be set +to initialize hardware that's normally done by SPL. + +For this case, CONFIG_SYS_TEXT_BASE=0x60000000 which is the address to +which the bootloader jumps when powered on. + +Example: +For the da850evm, there is a defconfig setup to use the NOR flash on +the UI expander board called da850evm_direct_nor_defconfig. + +Flash to NOR directly using +sudo mono ./sfh_OMAP-L138.exe -p /dev/ttyUSB0 -flash_noubl + -flashType NOR u-boot.bin + +SW7:5 through SW7:7 should be switched on and all others off. + Recovery ======== diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 857d5ff010..d1d7f9f400 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -503,7 +503,6 @@ static void mmc_pinmux_setup(int sdc) int board_mmc_init(bd_t *bis) { __maybe_unused struct mmc *mmc0, *mmc1; - __maybe_unused char buf[512]; mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); @@ -759,7 +758,6 @@ static void setup_environment(const void *fdt) int misc_init_r(void) { - __maybe_unused int ret; uint boot; env_set("fel_booted", NULL); diff --git a/cmd/Kconfig b/cmd/Kconfig index d5abcfd42a..51db3da33d 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -254,6 +254,14 @@ config CMD_BOOTMENU help Add an ANSI terminal boot menu command. +config CMD_DTIMG + bool "dtimg" + help + Android DTB/DTBO image manipulation commands. Read dtb/dtbo files from + image into RAM, dump image structure information, etc. Those dtb/dtbo + files should be merged in one dtb further, which needs to be passed to + the kernel, as part of a boot process. + config CMD_ELF bool "bootelf, bootvx" default y diff --git a/cmd/Makefile b/cmd/Makefile index 12d2118f1d..b1206fca85 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -43,6 +43,7 @@ ifdef CONFIG_POST obj-$(CONFIG_CMD_DIAG) += diag.o endif obj-$(CONFIG_CMD_DISPLAY) += display.o +obj-$(CONFIG_CMD_DTIMG) += dtimg.o obj-$(CONFIG_CMD_ECHO) += echo.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o obj-$(CONFIG_CMD_EEPROM) += eeprom.o diff --git a/cmd/dtimg.c b/cmd/dtimg.c new file mode 100644 index 0000000000..65c8d101b9 --- /dev/null +++ b/cmd/dtimg.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#include <image-android-dt.h> +#include <common.h> + +enum cmd_dtimg_info { + CMD_DTIMG_START = 0, + CMD_DTIMG_SIZE, +}; + +static int do_dtimg_dump(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + char *endp; + ulong hdr_addr; + + if (argc != 2) + return CMD_RET_USAGE; + + hdr_addr = simple_strtoul(argv[1], &endp, 16); + if (*endp != '\0') { + printf("Error: Wrong image address\n"); + return CMD_RET_FAILURE; + } + + if (!android_dt_check_header(hdr_addr)) { + printf("Error: DT image header is incorrect\n"); + return CMD_RET_FAILURE; + } + + android_dt_print_contents(hdr_addr); + + return CMD_RET_SUCCESS; +} + +static int dtimg_get_fdt(int argc, char * const argv[], enum cmd_dtimg_info cmd) +{ + ulong hdr_addr; + u32 index; + char *endp; + ulong fdt_addr; + u32 fdt_size; + char buf[65]; + + if (argc != 4) + return CMD_RET_USAGE; + + hdr_addr = simple_strtoul(argv[1], &endp, 16); + if (*endp != '\0') { + printf("Error: Wrong image address\n"); + return CMD_RET_FAILURE; + } + + if (!android_dt_check_header(hdr_addr)) { + printf("Error: DT image header is incorrect\n"); + return CMD_RET_FAILURE; + } + + index = simple_strtoul(argv[2], &endp, 0); + if (*endp != '\0') { + printf("Error: Wrong index\n"); + return CMD_RET_FAILURE; + } + + if (!android_dt_get_fdt_by_index(hdr_addr, index, &fdt_addr, &fdt_size)) + return CMD_RET_FAILURE; + + switch (cmd) { + case CMD_DTIMG_START: + snprintf(buf, sizeof(buf), "%lx", fdt_addr); + break; + case CMD_DTIMG_SIZE: + snprintf(buf, sizeof(buf), "%x", fdt_size); + break; + default: + printf("Error: Unknown cmd_dtimg_info value: %d\n", cmd); + return CMD_RET_FAILURE; + } + + env_set(argv[3], buf); + + return CMD_RET_SUCCESS; +} + +static int do_dtimg_start(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return dtimg_get_fdt(argc, argv, CMD_DTIMG_START); +} + +static int do_dtimg_size(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + return dtimg_get_fdt(argc, argv, CMD_DTIMG_SIZE); +} + +static cmd_tbl_t cmd_dtimg_sub[] = { + U_BOOT_CMD_MKENT(dump, 2, 0, do_dtimg_dump, "", ""), + U_BOOT_CMD_MKENT(start, 4, 0, do_dtimg_start, "", ""), + U_BOOT_CMD_MKENT(size, 4, 0, do_dtimg_size, "", ""), +}; + +static int do_dtimg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *cp; + + cp = find_cmd_tbl(argv[1], cmd_dtimg_sub, ARRAY_SIZE(cmd_dtimg_sub)); + + /* Strip off leading 'dtimg' command argument */ + argc--; + argv++; + + if (!cp || argc > cp->maxargs) + return CMD_RET_USAGE; + if (flag == CMD_FLAG_REPEAT && !cp->repeatable) + return CMD_RET_SUCCESS; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + dtimg, CONFIG_SYS_MAXARGS, 0, do_dtimg, + "manipulate dtb/dtbo Android image", + "dump <addr>\n" + " - parse specified image and print its structure info\n" + " <addr>: image address in RAM, in hex\n" + "dtimg start <addr> <index> <varname>\n" + " - get address (hex) of FDT in the image, by index\n" + " <addr>: image address in RAM, in hex\n" + " <index>: index of desired FDT in the image\n" + " <varname>: name of variable where to store address of FDT\n" + "dtimg size <addr> <index> <varname>\n" + " - get size (hex, bytes) of FDT in the image, by index\n" + " <addr>: image address in RAM, in hex\n" + " <index>: index of desired FDT in the image\n" + " <varname>: name of variable where to store size of FDT" +); diff --git a/common/Makefile b/common/Makefile index 7100541ece..7473b85011 100644 --- a/common/Makefile +++ b/common/Makefile @@ -108,6 +108,8 @@ obj-$(CONFIG_IO_TRACE) += iotrace.o obj-y += memsize.o obj-y += stdio.o +obj-$(CONFIG_CMD_DTIMG) += image-android-dt.o + ifdef CONFIG_CMD_EEPROM_LAYOUT obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o endif diff --git a/common/image-android-dt.c b/common/image-android-dt.c new file mode 100644 index 0000000000..c0683ee70f --- /dev/null +++ b/common/image-android-dt.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#include <image-android-dt.h> +#include <dt_table.h> +#include <common.h> +#include <linux/libfdt.h> +#include <mapmem.h> + +/** + * Check if image header is correct. + * + * @param hdr_addr Start address of DT image + * @return true if header is correct or false if header is incorrect + */ +bool android_dt_check_header(ulong hdr_addr) +{ + const struct dt_table_header *hdr; + u32 magic; + + hdr = map_sysmem(hdr_addr, sizeof(*hdr)); + magic = fdt32_to_cpu(hdr->magic); + unmap_sysmem(hdr); + + return magic == DT_TABLE_MAGIC; +} + +/** + * Get the address of FDT (dtb or dtbo) in memory by its index in image. + * + * @param hdr_addr Start address of DT image + * @param index Index of desired FDT in image (starting from 0) + * @param[out] addr If not NULL, will contain address to specified FDT + * @param[out] size If not NULL, will contain size of specified FDT + * + * @return true on success or false on error + */ +bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr, + u32 *size) +{ + const struct dt_table_header *hdr; + const struct dt_table_entry *e; + u32 entry_count, entries_offset, entry_size; + ulong e_addr; + u32 dt_offset, dt_size; + + hdr = map_sysmem(hdr_addr, sizeof(*hdr)); + entry_count = fdt32_to_cpu(hdr->dt_entry_count); + entries_offset = fdt32_to_cpu(hdr->dt_entries_offset); + entry_size = fdt32_to_cpu(hdr->dt_entry_size); + unmap_sysmem(hdr); + + if (index > entry_count) { + printf("Error: index > dt_entry_count (%u > %u)\n", index, + entry_count); + return false; + } + + e_addr = hdr_addr + entries_offset + index * entry_size; + e = map_sysmem(e_addr, sizeof(*e)); + dt_offset = fdt32_to_cpu(e->dt_offset); + dt_size = fdt32_to_cpu(e->dt_size); + unmap_sysmem(e); + + if (addr) + *addr = hdr_addr + dt_offset; + if (size) + *size = dt_size; + + return true; +} + +#if !defined(CONFIG_SPL_BUILD) +static void android_dt_print_fdt_info(const struct fdt_header *fdt) +{ + u32 fdt_size; + int root_node_off; + const char *compatible = NULL; + + fdt_size = fdt_totalsize(fdt); + root_node_off = fdt_path_offset(fdt, "/"); + if (root_node_off < 0) { + printf("Error: Root node not found\n"); + } else { + compatible = fdt_getprop(fdt, root_node_off, "compatible", + NULL); + } + + printf(" (FDT)size = %d\n", fdt_size); + printf(" (FDT)compatible = %s\n", + compatible ? compatible : "(unknown)"); +} + +/** + * Print information about DT image structure. + * + * @param hdr_addr Start address of DT image + */ +void android_dt_print_contents(ulong hdr_addr) +{ + const struct dt_table_header *hdr; + u32 entry_count, entries_offset, entry_size; + u32 i; + + hdr = map_sysmem(hdr_addr, sizeof(*hdr)); + entry_count = fdt32_to_cpu(hdr->dt_entry_count); + entries_offset = fdt32_to_cpu(hdr->dt_entries_offset); + entry_size = fdt32_to_cpu(hdr->dt_entry_size); + + /* Print image header info */ + printf("dt_table_header:\n"); + printf(" magic = %08x\n", fdt32_to_cpu(hdr->magic)); + printf(" total_size = %d\n", fdt32_to_cpu(hdr->total_size)); + printf(" header_size = %d\n", fdt32_to_cpu(hdr->header_size)); + printf(" dt_entry_size = %d\n", entry_size); + printf(" dt_entry_count = %d\n", entry_count); + printf(" dt_entries_offset = %d\n", entries_offset); + printf(" page_size = %d\n", fdt32_to_cpu(hdr->page_size)); + printf(" version = %d\n", fdt32_to_cpu(hdr->version)); + + unmap_sysmem(hdr); + + /* Print image entries info */ + for (i = 0; i < entry_count; ++i) { + const ulong e_addr = hdr_addr + entries_offset + i * entry_size; + const struct dt_table_entry *e; + const struct fdt_header *fdt; + u32 dt_offset, dt_size; + u32 j; + + e = map_sysmem(e_addr, sizeof(*e)); + dt_offset = fdt32_to_cpu(e->dt_offset); + dt_size = fdt32_to_cpu(e->dt_size); + + printf("dt_table_entry[%d]:\n", i); + printf(" dt_size = %d\n", dt_size); + printf(" dt_offset = %d\n", dt_offset); + printf(" id = %08x\n", fdt32_to_cpu(e->id)); + printf(" rev = %08x\n", fdt32_to_cpu(e->rev)); + for (j = 0; j < 4; ++j) { + printf(" custom[%d] = %08x\n", j, + fdt32_to_cpu(e->custom[j])); + } + + unmap_sysmem(e); + + /* Print FDT info for this entry */ + fdt = map_sysmem(hdr_addr + dt_offset, sizeof(*fdt)); + android_dt_print_fdt_info(fdt); + unmap_sysmem(fdt); + } +} +#endif diff --git a/common/spl/spl.c b/common/spl/spl.c index eda84d0c74..19508c7168 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -317,8 +317,6 @@ static int spl_common_init(bool setup_malloc) { int ret; - debug("spl_early_init()\n"); - #if CONFIG_VAL(SYS_MALLOC_F_LEN) if (setup_malloc) { #ifdef CONFIG_MALLOC_F_ADDR @@ -366,6 +364,8 @@ int spl_early_init(void) { int ret; + debug("%s\n", __func__); + ret = spl_common_init(true); if (ret) return ret; @@ -380,6 +380,8 @@ int spl_init(void) bool setup_malloc = !(IS_ENABLED(CONFIG_SPL_STACK_R) && IS_ENABLED(CONFIG_SPL_SYS_MALLOC_SIMPLE)); + debug("%s\n", __func__); + if (!(gd->flags & GD_FLG_SPL_EARLY_INIT)) { ret = spl_common_init(setup_malloc); if (ret) diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index d4442c2a74..95ba3250a2 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -8,7 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_I2C1_ENABLE=y CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" -CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro" +CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro-emmc" CONFIG_AHCI=y CONFIG_NR_DRAM_BANKS=1 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 2771893e15..0123ccee12 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -4,7 +4,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 CONFIG_DRAM_ZQ=3881979 -CONFIG_DRAM_ODT_EN=y CONFIG_MACPWR="PA17" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index 8b17b7fed4..ba46d902a6 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y -CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic" diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index dc37a4d867..a6ba32462b 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -4,7 +4,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 CONFIG_DRAM_ZQ=3881979 -CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry" CONFIG_AHCI=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index 114ac6115e..ad0b35f204 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -4,28 +4,25 @@ CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y CONFIG_NR_DRAM_BANKS=8 CONFIG_FIT=y -CONFIG_BOOTSTAGE=y -CONFIG_BOOTSTAGE_REPORT=y +CONFIG_FIT_SIGNATURE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y +CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_BOOTSTAGE=y -CONFIG_CMD_TPM=y -CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -34,11 +31,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="coreboot" CONFIG_REGMAP=y CONFIG_SYSCON=y -CONFIG_SPI=y -CONFIG_TPM_TIS_LPC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_KEYBOARD=y +# CONFIG_PCI_PNP is not set CONFIG_CONSOLE_SCROLL_LINES=5 -CONFIG_TPM=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 026355ebe0..0b8bf2ad36 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -19,6 +19,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " @@ -41,7 +42,6 @@ CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MTD_DEVICE=y CONFIG_MTD_PARTITIONS=y @@ -58,3 +58,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y # CONFIG_FAT_WRITE is not set +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 5b9fd334d1..ea826aabad 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -6,7 +6,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 -CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y diff --git a/doc/README.x86 b/doc/README.x86 index 9162ea17d8..8cc46725f2 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -47,21 +47,6 @@ on other architectures, like below: $ make coreboot_defconfig $ make all -Note this default configuration will build a U-Boot payload for the QEMU board. -To build a coreboot payload against another board, you can change the build -configuration during the 'make menuconfig' process. - -x86 architecture ---> - ... - (qemu-x86) Board configuration file - (qemu-x86_i440fx) Board Device Tree Source (dts) file - (0x01920000) Board specific Cache-As-RAM (CAR) address - (0x4000) Board specific Cache-As-RAM (CAR) size - -Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' -to point to a new board. You can also change the Cache-As-RAM (CAR) related -settings here if the default values do not fit your new board. - Build Instructions for U-Boot as main bootloader ------------------------------------------------ @@ -427,17 +412,10 @@ To enable video you must enable these options in coreboot: - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5)) - Keep VESA framebuffer -And include coreboot_fb.dtsi in your board's device tree source file, like: - - /include/ "coreboot_fb.dtsi" - At present it seems that for Minnowboard Max, coreboot does not pass through the video information correctly (it always says the resolution is 0x0). This works correctly for link though. -Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown -at this point. Patches are welcome if you figure out anything wrong. - Test with QEMU for bare mode ---------------------------- QEMU is a fancy emulator that can enable us to test U-Boot without access to diff --git a/doc/device-tree-bindings/regulator/fixed.txt b/doc/device-tree-bindings/regulator/fixed.txt index 5fd9033fea..453d2bef44 100644 --- a/doc/device-tree-bindings/regulator/fixed.txt +++ b/doc/device-tree-bindings/regulator/fixed.txt @@ -11,6 +11,7 @@ Required properties: Optional properties: - gpio: GPIO to use for enable control - startup-delay-us: startup time in microseconds +- u-boot,off-on-delay-us: off delay time in microseconds - regulator constraints (binding info: regulator.txt) - enable-active-high: Polarity of GPIO is Active high. If this property is missing, the default assumed is Active low. diff --git a/doc/uImage.FIT/beaglebone_vboot.txt b/doc/uImage.FIT/beaglebone_vboot.txt index f1862c2753..685ec1f46d 100644 --- a/doc/uImage.FIT/beaglebone_vboot.txt +++ b/doc/uImage.FIT/beaglebone_vboot.txt @@ -462,7 +462,7 @@ you sign. cd $UBOOT make O=b/am335x_boneblack_vboot EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb -Here we are overrriding the normal device tree file with our one, which +Here we are overriding the normal device tree file with our one, which contains the public key. Now you have a special U-Boot image with the public key. It can verify can diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 18bf8a6d28..a99abed9e9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -83,13 +83,13 @@ config CLK_STM32MP1 Enable the STM32 clock (RCC) driver. Enable support for manipulating STM32MP1's on-SoC clocks. -source "drivers/clk/tegra/Kconfig" -source "drivers/clk/uniphier/Kconfig" -source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" -source "drivers/clk/renesas/Kconfig" +source "drivers/clk/exynos/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" +source "drivers/clk/renesas/Kconfig" +source "drivers/clk/tegra/Kconfig" +source "drivers/clk/uniphier/Kconfig" config ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver" diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 0be5b7bd51..a99aa78310 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -16,6 +16,7 @@ struct fixed_regulator_platdata { struct gpio_desc gpio; /* GPIO for regulator enable control */ unsigned int startup_delay_us; + unsigned int off_on_delay_us; }; static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) @@ -50,6 +51,8 @@ static int fixed_regulator_ofdata_to_platdata(struct udevice *dev) /* Get optional ramp up delay */ dev_pdata->startup_delay_us = dev_read_u32_default(dev, "startup-delay-us", 0); + dev_pdata->off_on_delay_us = + dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0); return 0; } @@ -123,6 +126,9 @@ static int fixed_regulator_set_enable(struct udevice *dev, bool enable) udelay(dev_pdata->startup_delay_us); debug("%s: done\n", __func__); + if (!enable && dev_pdata->off_on_delay_us) + udelay(dev_pdata->off_on_delay_us); + return 0; } diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index 747f190d38..6473de20f1 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -341,16 +341,12 @@ static int tsc_timer_get_count(struct udevice *dev, u64 *count) return 0; } -static void tsc_timer_ensure_setup(void) +static void tsc_timer_ensure_setup(bool stop) { if (gd->arch.tsc_base) return; gd->arch.tsc_base = rdtsc(); - /* - * If there is no clock frequency specified in the device tree, - * calibrate it by ourselves. - */ if (!gd->arch.clock_rate) { unsigned long fast_calibrate; @@ -366,7 +362,10 @@ static void tsc_timer_ensure_setup(void) if (fast_calibrate) goto done; - panic("TSC frequency is ZERO"); + if (stop) + panic("TSC frequency is ZERO"); + else + return; done: gd->arch.clock_rate = fast_calibrate * 1000000; @@ -377,11 +376,17 @@ static int tsc_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - if (!uc_priv->clock_rate) { - tsc_timer_ensure_setup(); - uc_priv->clock_rate = gd->arch.clock_rate; + /* Try hardware calibration first */ + tsc_timer_ensure_setup(false); + if (!gd->arch.clock_rate) { + /* + * Use the clock frequency specified in the + * device tree as last resort + */ + if (!uc_priv->clock_rate) + panic("TSC frequency is ZERO"); } else { - gd->arch.tsc_base = rdtsc(); + uc_priv->clock_rate = gd->arch.clock_rate; } return 0; @@ -394,7 +399,7 @@ unsigned long notrace timer_early_get_rate(void) * clock rate can only be calibrated via some hardware ways. Specifying * it in the device tree won't work for the early timer. */ - tsc_timer_ensure_setup(); + tsc_timer_ensure_setup(true); return gd->arch.clock_rate; } diff --git a/env/Kconfig b/env/Kconfig index be99efb937..f23be00a54 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -431,23 +431,35 @@ config ENV_EXT4_FILE It's a string of the EXT4 file name. This file use to store the environment (explicit path to the file) -if ARCH_SUNXI +if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP config ENV_OFFSET hex "Environment Offset" depends on !ENV_IS_IN_UBI depends on !ENV_IS_NOWHERE + default 0x3f8000 if ARCH_ROCKCHIP default 0x88000 if ARCH_SUNXI + default 0xE0000 if ARCH_ZYNQ + default 0x1E00000 if ARCH_ZYNQMP help Offset from the start of the device (or partition) config ENV_SIZE hex "Environment Size" - depends on !ENV_IS_NOWHERE - default 0x20000 if ARCH_SUNXI + default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP + default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ + default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP help Size of the environment storage area +config ENV_SECT_SIZE + hex "Environment Sector-Size" + depends on !ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP) + default 0x40000 if ARCH_ZYNQMP + default 0x20000 if ARCH_ZYNQ + help + Size of the sector containing the environment. + config ENV_UBI_PART string "UBI partition name" depends on ENV_IS_IN_UBI @@ -462,52 +474,6 @@ config ENV_UBI_VOLUME endif -if ARCH_ROCKCHIP - -config ENV_OFFSET - hex - depends on !ENV_IS_IN_UBI - depends on !ENV_IS_NOWHERE - default 0x3f8000 - help - Offset from the start of the device (or partition) - -config ENV_SIZE - hex - default 0x8000 - help - Size of the environment storage area - -endif - -if ARCH_ZYNQMP || ARCH_ZYNQ - -config ENV_OFFSET - hex "Environment Offset" - depends on !ENV_IS_NOWHERE - default 0x1E00000 if ARCH_ZYNQMP - default 0xE0000 if ARCH_ZYNQ - help - Offset from the start of the device (or partition) - -config ENV_SIZE - hex "Environment Size" - default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP - default 0x8000 if ARCH_ZYNQMP - default 0x20000 if ARCH_ZYNQ - help - Size of the environment storage area. - -config ENV_SECT_SIZE - hex "Environment Sector-Size" - depends on !ENV_IS_NOWHERE - default 0x40000 if ARCH_ZYNQMP - default 0x20000 if ARCH_ZYNQ - help - Size of the sector containing the environment. - -endif - config USE_DEFAULT_ENV_FILE bool "Create default environment from file" help diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 4efe8a3eda..4b722fc5ca 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -1095,7 +1095,7 @@ int file_fat_read_at(const char *filename, loff_t pos, void *buffer, if (ret) goto out_free_both; - debug("reading %s\n", filename); + debug("reading %s at pos %llu\n", filename, pos); ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread); out_free_both: diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h new file mode 100644 index 0000000000..1cf5c037e8 --- /dev/null +++ b/include/configs/coreboot.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +/* ATA/IDE support */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#endif /* __CONFIG_H */ diff --git a/include/configs/display5.h b/include/configs/display5.h index fc8261373a..514638f684 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -166,7 +166,7 @@ "rootwait rootfstype=ext4 rw; " \ "run set_kernel_part;" \ "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ - "mmc read ${loadaddr} ${lba_start} 0x2000; " \ + "mmc read ${loadaddr} ${lba_start} ${fitImg_fw_sz}; " \ "setenv fdt_conf imx6q-${board}-${display}.dtb; " /* All the numbers are in LBAs */ @@ -273,6 +273,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "kernel_file=fitImage\0" \ + "fitImg_fw_sz=0x2200\0" \ "up=run tftp_sf_SPL; run tftp_sf_uboot\0" \ "download_kernel=" \ "tftpboot ${loadaddr} ${kernel_file};\0" \ diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h deleted file mode 100644 index 031b82bfb9..0000000000 --- a/include/configs/som-6896.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the SOM-6896 - * - * Copyright (C) 2015 NovaTech LLC - * George McCollister <george.mccollister@gmail.com> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <configs/x86-common.h> - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x00ff0000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 2adf80464f..9819d9980c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -153,8 +153,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #endif #define CONFIG_SYS_MMC_MAX_DEVICE 4 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE (128 << 10) #endif #ifndef CONFIG_MACH_SUN8I_V3S diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h new file mode 100644 index 0000000000..78af5085f6 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-a83t-ccu.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ +#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ + +#define CLK_PLL_PERIPH 6 + +#define CLK_PLL_DE 9 + +#define CLK_C0CPUX 11 +#define CLK_C1CPUX 12 + +#define CLK_BUS_MIPI_DSI 19 +#define CLK_BUS_SS 20 +#define CLK_BUS_DMA 21 +#define CLK_BUS_MMC0 22 +#define CLK_BUS_MMC1 23 +#define CLK_BUS_MMC2 24 +#define CLK_BUS_NAND 25 +#define CLK_BUS_DRAM 26 +#define CLK_BUS_EMAC 27 +#define CLK_BUS_HSTIMER 28 +#define CLK_BUS_SPI0 29 +#define CLK_BUS_SPI1 30 +#define CLK_BUS_OTG 31 +#define CLK_BUS_EHCI0 32 +#define CLK_BUS_EHCI1 33 +#define CLK_BUS_OHCI0 34 + +#define CLK_BUS_VE 35 +#define CLK_BUS_TCON0 36 +#define CLK_BUS_TCON1 37 +#define CLK_BUS_CSI 38 +#define CLK_BUS_HDMI 39 +#define CLK_BUS_DE 40 +#define CLK_BUS_GPU 41 +#define CLK_BUS_MSGBOX 42 +#define CLK_BUS_SPINLOCK 43 + +#define CLK_BUS_SPDIF 44 +#define CLK_BUS_PIO 45 +#define CLK_BUS_I2S0 46 +#define CLK_BUS_I2S1 47 +#define CLK_BUS_I2S2 48 +#define CLK_BUS_TDM 49 + +#define CLK_BUS_I2C0 50 +#define CLK_BUS_I2C1 51 +#define CLK_BUS_I2C2 52 +#define CLK_BUS_UART0 53 +#define CLK_BUS_UART1 54 +#define CLK_BUS_UART2 55 +#define CLK_BUS_UART3 56 +#define CLK_BUS_UART4 57 + +#define CLK_NAND 59 +#define CLK_MMC0 60 +#define CLK_MMC0_SAMPLE 61 +#define CLK_MMC0_OUTPUT 62 +#define CLK_MMC1 63 +#define CLK_MMC1_SAMPLE 64 +#define CLK_MMC1_OUTPUT 65 +#define CLK_MMC2 66 +#define CLK_MMC2_SAMPLE 67 +#define CLK_MMC2_OUTPUT 68 +#define CLK_SS 69 +#define CLK_SPI0 70 +#define CLK_SPI1 71 +#define CLK_I2S0 72 +#define CLK_I2S1 73 +#define CLK_I2S2 74 +#define CLK_TDM 75 +#define CLK_SPDIF 76 +#define CLK_USB_PHY0 77 +#define CLK_USB_PHY1 78 +#define CLK_USB_HSIC 79 +#define CLK_USB_HSIC_12M 80 +#define CLK_USB_OHCI0 81 + +#define CLK_DRAM_VE 83 +#define CLK_DRAM_CSI 84 + +#define CLK_TCON0 85 +#define CLK_TCON1 86 +#define CLK_CSI_MISC 87 +#define CLK_MIPI_CSI 88 +#define CLK_CSI_MCLK 89 +#define CLK_CSI_SCLK 90 +#define CLK_VE 91 +#define CLK_AVS 92 +#define CLK_HDMI 93 +#define CLK_HDMI_SLOW 94 + +#define CLK_MIPI_DSI0 96 +#define CLK_MIPI_DSI1 97 +#define CLK_GPU_CORE 98 +#define CLK_GPU_MEMORY 99 +#define CLK_GPU_HYD 100 + +#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-a83t-ccu.h b/include/dt-bindings/reset/sun8i-a83t-ccu.h new file mode 100644 index 0000000000..784f6e1166 --- /dev/null +++ b/include/dt-bindings/reset/sun8i-a83t-ccu.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ +#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ + +#define RST_USB_PHY0 0 +#define RST_USB_PHY1 1 +#define RST_USB_HSIC 2 + +#define RST_DRAM 3 +#define RST_MBUS 4 + +#define RST_BUS_MIPI_DSI 5 +#define RST_BUS_SS 6 +#define RST_BUS_DMA 7 +#define RST_BUS_MMC0 8 +#define RST_BUS_MMC1 9 +#define RST_BUS_MMC2 10 +#define RST_BUS_NAND 11 +#define RST_BUS_DRAM 12 +#define RST_BUS_EMAC 13 +#define RST_BUS_HSTIMER 14 +#define RST_BUS_SPI0 15 +#define RST_BUS_SPI1 16 +#define RST_BUS_OTG 17 +#define RST_BUS_EHCI0 18 +#define RST_BUS_EHCI1 19 +#define RST_BUS_OHCI0 20 + +#define RST_BUS_VE 21 +#define RST_BUS_TCON0 22 +#define RST_BUS_TCON1 23 +#define RST_BUS_CSI 24 +#define RST_BUS_HDMI0 25 +#define RST_BUS_HDMI1 26 +#define RST_BUS_DE 27 +#define RST_BUS_GPU 28 +#define RST_BUS_MSGBOX 29 +#define RST_BUS_SPINLOCK 30 + +#define RST_BUS_LVDS 31 + +#define RST_BUS_SPDIF 32 +#define RST_BUS_I2S0 33 +#define RST_BUS_I2S1 34 +#define RST_BUS_I2S2 35 +#define RST_BUS_TDM 36 + +#define RST_BUS_I2C0 37 +#define RST_BUS_I2C1 38 +#define RST_BUS_I2C2 39 +#define RST_BUS_UART0 40 +#define RST_BUS_UART1 41 +#define RST_BUS_UART2 42 +#define RST_BUS_UART3 43 +#define RST_BUS_UART4 44 + +#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */ diff --git a/include/image-android-dt.h b/include/image-android-dt.h new file mode 100644 index 0000000000..9a3aa8fa30 --- /dev/null +++ b/include/image-android-dt.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#ifndef IMAGE_ANDROID_DT_H +#define IMAGE_ANDROID_DT_H + +#include <linux/types.h> + +bool android_dt_check_header(ulong hdr_addr); +bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr, + u32 *size); + +#if !defined(CONFIG_SPL_BUILD) +void android_dt_print_contents(ulong hdr_addr); +#endif + +#endif /* IMAGE_ANDROID_DT_H */ |