diff options
36 files changed, 3340 insertions, 27 deletions
@@ -2,6 +2,19 @@ Changes for U-Boot 1.0.2: ====================================================================== +* Patch by Thomas Elste, 10 Feb 2004: + Add support for NET+50 CPU and ModNET50 board + +* Patch by Sam Song, 10 Feb 2004: + Fix typos in cfi_flash.c + +* Patch by Leon Kukovec, 10 Feb 2004 + Fixed long dir entry slot id calculation in get_vfatname + +* Patch by Robin Gilks, 10 Feb 2004: + add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==, + !=, <>, <, >, <=, >=) + * Fix problem with side effects in macros in include/usb.h * Patch by David Benson, 13 Nov 2003: @@ -959,6 +959,9 @@ impa7_config : unconfig ep7312_config : unconfig @./mkconfig $(@:_config=) arm arm720t ep7312 +modnet50_config : unconfig + @./mkconfig $(@:_config=) arm arm720t modnet50 + ######################################################################### ## XScale Systems ######################################################################### @@ -644,6 +644,7 @@ The following options need to be configured: CFG_CMD_IMLS List all found images CFG_CMD_IMMAP * IMMR dump support CFG_CMD_IRQ * irqinfo + CFG_CMD_ITEST * Integer/string test of 2 values CFG_CMD_JFFS2 * JFFS2 Support CFG_CMD_KGDB * kgdb CFG_CMD_LOADB loadb diff --git a/board/modnet50/Makefile b/board/modnet50/Makefile new file mode 100644 index 0000000000..7dbcc1c937 --- /dev/null +++ b/board/modnet50/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := modnet50.o flash.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/modnet50/config.mk b/board/modnet50/config.mk new file mode 100644 index 0000000000..49d4836c0a --- /dev/null +++ b/board/modnet50/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH <www.elinos.com> +# Marius Groeger <mgroeger@sysgo.de> +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x00f00000 +#CROSS_COMPILE = arm-elf- diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c new file mode 100644 index 0000000000..fc04d9124e --- /dev/null +++ b/board/modnet50/flash.c @@ -0,0 +1,536 @@ +/* + * (C) Copyright 2002 + * MAZeT GmbH <www.mazet.de> + * Stephan Linz <linz@mazet.de>, <linz@li-pro.net> + * + * The most stuff comes from PPCBoot and Linux. + * + * IMMS gGmbH <www.imms.de> + * Thomas Elste <info@elste.org> + * + * Modifications for ModNET50 Board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/netarm_registers.h> + +#define SCR (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_SYSTEM_CONTROL)) + +#define ALIGN_ABORT_OFF SCR = SCR & ~NETARM_GEN_SYS_CFG_ALIGN_ABORT +#define ALIGN_ABORT_ON SCR = SCR | NETARM_GEN_SYS_CFG_ALIGN_ABORT + +#define PROG_ADDR (0x555*2) +#define SETUP_ADDR (0x555*2) +#define ID_ADDR (0x555*2) +#define UNLOCK_ADDR1 (0x555*2) +#define UNLOCK_ADDR2 (0x2AA*2) + +#define UNLOCK_CMD1 (0xAA) +#define UNLOCK_CMD2 (0x55) +#define ERASE_SUSPEND_CMD (0xB0) +#define ERASE_RESUME_CMD (0x30) +#define RESET_CMD (0xF0) +#define ID_CMD (0x90) +#define SECERASE_CMD (0x30) +#define CHIPERASE_CMD (0x10) +#define PROG_CMD (0xa0) +#define SETUP_CMD (0x80) + +#define DQ2 (0x04) +#define DQ3 (DQ2*2) +#define DQ5 (DQ3*4) +#define DQ6 (DQ5*2) + +#define WRITE_UNLOCK(addr) { \ + *(volatile __u16*)(addr + UNLOCK_ADDR1) = (__u16)UNLOCK_CMD1; \ + *(volatile __u16*)(addr + UNLOCK_ADDR2) = (__u16)UNLOCK_CMD2; \ +} + +#define CONFIG_AM29_RESERVED (0) +#define K (1024) +#define MB (4) + +#define CELL_SIZE (64*K) +#define DEVICE_SIZE (MB*K*K) +#define CELLS_PER_DEVICE (DEVICE_SIZE/CELL_SIZE) +#define RESERVED_CELLS (CONFIG_AM29_RESERVED*K)/CELL_SIZE +#define MAX_FLASH_DEVICES (1) +#define AVAIL_SIZE (DEVICE_SIZE*MAX_FLASH_DEVICES - RESERVED_CELLS*CELL_SIZE) + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +static __u16 toggling_bits; + + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (ulong baseaddr, flash_info_t * info) +{ + short i; + __u16 flashtest; + + /* Write auto select command sequence and test FLASH answer */ + WRITE_UNLOCK (baseaddr); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD; + flashtest /* manufacturer ID */ = *(volatile __u16 *) (baseaddr); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD; + + switch ((__u32) ((flashtest << 16) + flashtest)) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD & FLASH_VENDMASK; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ & FLASH_VENDMASK; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + /* Write auto select command sequence and test FLASH answer */ + WRITE_UNLOCK (baseaddr); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD; + flashtest /* device ID */ = *(volatile __u16 *) (baseaddr + 2); + *(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD; + + /* toggling_bits = (flashtest == TOSHIBA)?(DQ6):(DQ2|DQ6); */ + toggling_bits = (DQ2 | DQ6); + + switch ((__u32) ((flashtest << 16) + flashtest)) { + case AMD_ID_LV160B: + info->flash_id += + (FLASH_AM160LV | FLASH_AM160B) & FLASH_TYPEMASK; + info->sector_count = CFG_MAX_FLASH_SECT; + info->size = CFG_FLASH_SIZE; + /* 1*16K Boot Block + 2*8K Parameter Block + 1*32K Small Main Block */ + info->start[0] = baseaddr; + info->start[1] = baseaddr + 0x4000; + info->start[2] = baseaddr + 0x6000; + info->start[3] = baseaddr + 0x8000; + for (i = 1; i < info->sector_count; i++) + info->start[3 + i] = baseaddr + i * CFG_MAIN_SECT_SIZE; + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* no or unknown flash */ + } + + for (i = 0; i < info->sector_count; i++) { + /* Write auto select command sequence and test FLASH answer */ + WRITE_UNLOCK (info->start[i]); + *(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) ID_CMD; + flashtest /* protected verify */ = *(volatile __u16 *) (info->start[i] + 4); + *(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) RESET_CMD; + if (flashtest & 0x0001) { + info->protect[i] = 1; /* D0 = 1 if protected */ + } else { + info->protect[i] = 0; + } + } + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +ulong flash_init (void) +{ + ulong size = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + size = flash_get_size (CFG_FLASH_BASE, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN || size == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size, size >> 20); + } + + /* + * protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("Fujitsu "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMDL323B: + printf ("29DL323B (32 M, bottom sector)\n"); + break; + case (FLASH_AM160LV | FLASH_AM160B): + printf ("29LV160BE (1M x 16, bottom sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 4) == 0) + printf ("\n "); + printf (" S%02d @ 0x%08lX%s", i, + info->start[i], info->protect[i] ? " !" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ +int flash_check_protection (flash_info_t * info, int s_first, int s_last) +{ + int sect, prot = 0; + + for (sect = s_first; sect <= s_last; sect++) + if (info->protect[sect]) + prot++; + if (prot) + printf ("- can't erase %d protected sectors\n", prot); + return prot; +} + +/*----------------------------------------------------------------------- + */ +int flash_check_erase_amd (ulong start) +{ + __u16 v1, v2; + + v1 = *(volatile __u16 *) (start); + v2 = *(volatile __u16 *) (start); + + if (((v1 ^ v2) & toggling_bits) == toggling_bits) { + if (((v1 | v2) & DQ5) == DQ5) { + printf ("[DQ5] "); + /* OOPS: exceeded timing limits */ + + v1 = *(volatile __u16 *) (start); + v2 = *(volatile __u16 *) (start); + + if (((v1 ^ v2) & toggling_bits) == toggling_bits) { + + printf ("[%s] ", + ((toggling_bits & (DQ2 | DQ6)) == + (DQ2 | DQ6)) ? "DQ2,DQ6" : "DQ6"); + + /* OOPS: there is an erasure in progress, + * try to reset chip */ + *(volatile __u16 *) (start) = + (__u16) RESET_CMD; + + return 1; /* still busy */ + } + } + return 1; /* still busy */ + } + return 0; /* be free */ +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, sect, setup_offset = 0; + int rc = ERR_OK; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + return ERR_UNKNOWN_FLASH_TYPE; + } + + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return ERR_INVAL; + } + + if (flash_check_protection (info, s_first, s_last)) + return ERR_PROTECTED; + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_FUJ: + case FLASH_MAN_AMD: + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_AM160LV | FLASH_AM160B): + setup_offset = UNLOCK_ADDR1; /* just the adress for setup_cmd differs */ + case FLASH_AMDL323B: + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); + sect++) { + printf ("Erasing sector %2d ... ", sect); + + if (info->protect[sect] == 0) { + /* not protected */ + /* Write sector erase command sequence */ + WRITE_UNLOCK (info->start[0]); + *(volatile __u16 *) (info->start[0] + + setup_offset) = + (__u16) SETUP_CMD; + WRITE_UNLOCK (info->start[0]); + *(volatile __u16 *) (info-> + start[sect]) = + (__u16) SECERASE_CMD; + + /* wait some time */ + reset_timer_masked (); + while (get_timer_masked () < 1000) { + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + while (flash_check_erase_amd (info->start[sect])) { + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + printf ("timeout!\n"); + /* OOPS: reach timeout, + * try to reset chip + */ + *(volatile __u16 *) (info-> start[sect]) = (__u16) RESET_CMD; + rc = ERR_TIMOUT; + goto outahere_323B; + } + } + printf ("ok.\n"); + } else { + printf ("protected!\n"); + } + } + if (ctrlc ()) + printf ("User Interrupt!\n"); +outahere_323B: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) + enable_interrupts (); + return rc; + default: + printf ("- unknown chip type\n"); + return ERR_UNKNOWN_FLASH_TYPE; + } + break; + default: + printf ("- unknown vendor "); + return ERR_UNKNOWN_FLASH_VENDOR; + } +} + +/*----------------------------------------------------------------------- + */ +int flash_check_write_amd (ulong dest) +{ + __u16 v1, v2; + + v1 = *(volatile __u16 *) (dest); + v2 = *(volatile __u16 *) (dest); + + /* DQ6 toggles during write */ + if (((v1 ^ v2) & DQ6) == DQ6) { + if (((v1 | v2) & DQ5) == DQ5) { + printf ("[DQ5] @ %08lX\n", dest); + + /* OOPS: exceeded timing limits, + * try to reset chip */ + *(volatile __u16 *) (dest) = (__u16) RESET_CMD; + return 0; /* be free */ + } + return 1; /* still busy */ + } + + return 0; /* be free */ +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ +static int write_word (flash_info_t * info, ulong dest, ushort data) +{ + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*(__u16 *) (dest) & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + /* Write program command sequence */ + WRITE_UNLOCK (info->start[0]); + + /* Flash dependend program seqence */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_FUJ: + case FLASH_MAN_AMD: + switch (info->flash_id & FLASH_TYPEMASK) { + case (FLASH_AM160LV | FLASH_AM160B): + *(volatile __u16 *) (info->start[0] + UNLOCK_ADDR1) = + (__u16) PROG_CMD; + *(volatile __u16 *) (dest) = (__u16) data; + break; + case FLASH_AMDL323B: + *(volatile __u16 *) (dest) = (__u16) PROG_CMD; + *(volatile __u16 *) (dest) = (__u16) data; + break; + } + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + while (flash_check_write_amd (dest)) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + printf ("timeout! @ %08lX\n", dest); + /* OOPS: reach timeout, + * try to reset chip */ + *(volatile __u16 *) (dest) = (__u16) RESET_CMD; + + rc = ERR_TIMOUT; + goto outahere_323B; + } + } + + /* Check if Flash was (accurately) written */ + if (*(__u16 *) (dest) != data) + rc = ERR_PROG_ERROR; + +outahere_323B: + if (flag) + enable_interrupts (); + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + ushort data; + int l; + int i, rc; + + wp = (addr & ~1); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + for (; i < 2 && cnt > 0; ++i) { + data = (data >> 8) | (*src++ << 8); + --cnt; + ++cp; + } + for (; cnt == 0 && i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 2; + } + + /* + * handle word aligned part + */ + while (cnt >= 2) { + data = *((ushort *) src); + if ((rc = write_word (info, wp, data)) != 0) + return (rc); + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 0) + return ERR_OK; + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 8); + --cnt; + } + for (; i < 2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *) cp << 8); + } + + return write_word (info, wp, data); +} diff --git a/board/modnet50/memsetup.S b/board/modnet50/memsetup.S new file mode 100644 index 0000000000..674b1d2e05 --- /dev/null +++ b/board/modnet50/memsetup.S @@ -0,0 +1,204 @@ +/* + * Memory Setup stuff - taken from Linux + * + * Copyright (c) 2002 Stephan Linz <linz@mazet.de>, <linz@li-pro.net> + * (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> +#include <version.h> +#include <asm/arch/netarm_registers.h> + + +/* some parameters for the board */ +#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3) +#define FLASH_70ns_WAIT_STATES 4 + +#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1) +#if 1 +#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1)) +#else +#define NETARM_MMAP_CS0_MASK (~(1000000 - 1)) +#endif +#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1) +#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1)) +#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2) +#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1)) +#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE) +#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1) +#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1)) +#endif +#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1) +#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1)) + +/* setting up the memory */ +.globl memsetup +memsetup: + +#if defined(CONFIG_MODNET50) + ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE) + +_jump_to_high: + /* + * MEM Config Reg + * --------------------------------------------------- + */ + ldr r0, =NETARM_MEM_MODULE_BASE + ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \ + NETARM_MEM_CFG_REFRESH_EN | \ + NETARM_MEM_CFG_REFR_CYCLE_5CLKS ) + str r1, [r0, #+NETARM_MEM_MODULE_CONFIG] + + +memsetup_cs0: + /* + * Base Addr / Option Reg 0 (Flash) + * --------------------------------------------------- + */ + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \ + NETARM_MEM_BAR_DRAM_FP | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_BAL | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR] + + /* trust that the bus size for flash was strapped correctly */ + /* this saves the bus width in r2 and then ORs it back in */ + /* it's pretty safe assumption, otherwise it wouldn't boot */ + ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS] + and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK + +/* just a test: assume 32 bit flash mem */ +/* mov r2, #NETARM_MEM_OPT_32BIT */ + + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \ + NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \ + NETARM_MEM_OPT_BCYC_4 | \ + NETARM_MEM_OPT_BSIZE_16 | \ + NETARM_MEM_OPT_16BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + + orr r1, r1, r2 + str r1, [r0, #+NETARM_MEM_CS0_OPTIONS] + + +memsetup_cs1: + /* + * Base Addr / Option Reg 1 (DRAM #1) + * --------------------------------------------------- + */ +#ifdef CONFIG_NETARM_NET40_REV2 + /* we have to config SDRAM in burst mode */ + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \ + NETARM_MEM_OPT_BCYC_2 | \ + NETARM_MEM_OPT_BSIZE_16 | \ + NETARM_MEM_OPT_WAIT_STATES(0) | \ + NETARM_MEM_OPT_32BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + str r1, [r0, #+NETARM_MEM_CS1_OPTIONS] + + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \ + NETARM_MEM_BAR_DRAM_SYNC | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_UNBAL | \ + NETARM_MEM_BAR_DRAM_SEL | \ + NETARM_MEM_BAR_BURST_EN | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR] +#else + /* we have to config FPDRAM in burst mode with smaller burst access size */ + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \ + NETARM_MEM_OPT_BCYC_2 | \ + NETARM_MEM_OPT_BSIZE_16 | \ + NETARM_MEM_OPT_WAIT_STATES(0) | \ + NETARM_MEM_OPT_32BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + str r1, [r0, #+NETARM_MEM_CS1_OPTIONS] + + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \ + NETARM_MEM_BAR_DRAM_SYNC | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_UNBAL | \ + NETARM_MEM_BAR_DRAM_SEL | \ + NETARM_MEM_BAR_BURST_EN | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR] + +#endif /* CONFIG_NETARM_NET40_REV2 */ + + +memsetup_cs3: + /* + * Base Addr / Option Reg 3 (EEPROM, NVRAM) + * --------------------------------------------------- + */ +#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE) + ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \ + NETARM_MEM_OPT_BCYC_3 | \ + NETARM_MEM_OPT_BSIZE_2 | \ + NETARM_MEM_OPT_WAIT_STATES(10) | \ + NETARM_MEM_OPT_8BIT | \ + NETARM_MEM_OPT_READ_ASYNC | \ + NETARM_MEM_OPT_WRITE_ASYNC ) + str r1, [r0, #+NETARM_MEM_CS3_OPTIONS] + + ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \ + NETARM_MEM_BAR_DRAM_FP | \ + NETARM_MEM_BAR_DRAM_MUX_INT | \ + NETARM_MEM_BAR_DRAM_MUX_BAL | \ + NETARM_MEM_BAR_VALID ) + str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR] +#else + /* we don't need EEPROM --> no config */ + ldr r1, =( 0 ) + str r1, [r0, #+NETARM_MEM_CS3_OPTIONS] + + ldr r1, =( 0 ) + str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR] +#endif + + +#else +/* +#error "missing CONFIG_MODNET50 (see your config.h)" +*/ +#endif /* CONFIG_MODNET50 */ + + +memsetup_end: + /* + * manipulate address in lr and ip to match new + * address space + */ + ldr r3, =(NETARM_MMAP_CS0_BASE) + mov r0, lr + add r0, r3, r0 + mov lr, r0 + mov r0, ip + add r0, r3, r0 + mov ip, r0 + + /* everything is fine now */ + mov pc, lr diff --git a/board/modnet50/modnet50.c b/board/modnet50/modnet50.c new file mode 100644 index 0000000000..448c6233e9 --- /dev/null +++ b/board/modnet50/modnet50.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + /* address for the kernel command line */ + gd->bd->bi_boot_params = 0x800; + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + if (CONFIG_NR_DRAM_BANKS == 2) { + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + } + return (0); +} diff --git a/board/modnet50/u-boot.lds b/board/modnet50/u-boot.lds new file mode 100644 index 0000000000..ac09f5fb7c --- /dev/null +++ b/board/modnet50/u-boot.lds @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/common/Makefile b/common/Makefile index 66cb9ed883..eccb4e46f0 100644 --- a/common/Makefile +++ b/common/Makefile @@ -34,7 +34,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o \ cmd_date.o cmd_dcr.o cmd_diag.o cmd_doc.o cmd_dtt.o \ cmd_eeprom.o cmd_elf.o \ cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ - cmd_i2c.o cmd_ide.o cmd_immap.o cmd_jffs2.o \ + cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \ cmd_load.o cmd_log.o \ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ cmd_nand.o cmd_net.o cmd_nvedit.o \ @@ -44,10 +44,10 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o \ environment.o env_common.o \ env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \ flash.o fpga.o \ - hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \ + hush.o kgdb.o lists.o lynxkdi.o memsize.o miiphybb.o miiphyutil.o \ s_record.o soft_i2c.o soft_spi.o spartan2.o \ usb.o usb_kbd.o usb_storage.o \ - virtex2.o xilinx.o memsize.o + virtex2.o xilinx.o OBJS = $(AOBJS) $(COBJS) diff --git a/common/cmd_itest.c b/common/cmd_itest.c new file mode 100644 index 0000000000..9e920c9bdc --- /dev/null +++ b/common/cmd_itest.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2003 + * Tait Electronics Limited, Christchurch, New Zealand + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file provides a shell like 'test' function to return + * true/false from an integer or string compare of two memory + * locations or a location and a scalar/literal. + * A few parts were lifted from bash 'test' command + */ + +#include <common.h> +#include <config.h> +#include <command.h> + +#define EQ 0 +#define NE 1 +#define LT 2 +#define GT 3 +#define LE 4 +#define GE 5 + +struct op_tbl_s { + char *op; /* operator string */ + int opcode; /* internal representation of opcode */ +}; + +typedef struct op_tbl_s op_tbl_t; + +op_tbl_t op_table [] = { + { "-lt", LT }, + { "<" , LT }, + { "-gt", GT }, + { ">" , GT }, + { "-eq", EQ }, + { "==" , EQ }, + { "-ne", NE }, + { "!=" , NE }, + { "<>" , NE }, + { "-ge", GE }, + { ">=" , GE }, + { "-le", LE }, + { "<=" , LE }, +}; + +#define op_tbl_size (sizeof(op_table)/sizeof(op_table[0])) + +extern int cmd_get_data_size(char* arg, int default_size); + +static long evalexp(char *s, int w) +{ + long l, *p; + + /* if the parameter starts with a * then assume is a pointer to the value we want */ + if (s[0] == '*') { + p = (long *)simple_strtoul(&s[1], NULL, 16); + l = *p; + } else { + l = simple_strtoul(s, NULL, 16); + } + + return (l & ((1 << (w * 8)) - 1)); +} + +static char * evalstr(char *s) +{ + /* if the parameter starts with a * then assume a string pointer else its a literal */ + if (s[0] == '*') { + return (char *)simple_strtoul(&s[1], NULL, 16); + } else { + return s; + } +} + +static int stringcomp(char *s, char *t, int op) +{ + int n, p; + char *l, *r; + + l = evalstr(s); + r = evalstr(t); + + /* we'll do a compare based on the length of the shortest string */ + n = min(strlen(l), strlen(r)); + + p = strncmp(l, r, n); + switch (op) { + case EQ: return (p == 0); + case NE: return (p != 0); + case LT: return (p < 0); + case GT: return (p > 0); + case LE: return (p <= 0); + case GE: return (p >= 0); + } + return (0); +} + +static int arithcomp (char *s, char *t, int op, int w) +{ + long l, r; + + l = evalexp (s, w); + r = evalexp (t, w); + + switch (op) { + case EQ: return (l == r); + case NE: return (l != r); + case LT: return (l < r); + case GT: return (l > r); + case LE: return (l <= r); + case GE: return (l >= r); + } + return (0); +} + +int binary_test (char *op, char *arg1, char *arg2, int w) +{ + int len, i; + op_tbl_t *optp; + + len = strlen(op); + + for (optp = (op_tbl_t *)&op_table, i = 0; + i < op_tbl_size; + optp++, i++) { + + if ((strncmp (op, optp->op, len) == 0) && (len == strlen (optp->op))) { + if (w == 0) { + return (stringcomp(arg1, arg2, optp->opcode)); + } else { + return (arithcomp (arg1, arg2, optp->opcode, w)); + } + } + } + + printf("Unknown operator '%s'\n", op); + return 0; /* op code not found */ +} + +/* command line interface to the shell test */ +int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + int value, w; + + /* Validate arguments */ + if ((argc != 4)){ + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* Check for a data width specification. + * Defaults to long (4) if no specification. + * Uses -2 as 'width' for .s (string) so as not to upset existing code + */ + switch (w = cmd_get_data_size(argv[0], 4)) { + case 1: + case 2: + case 4: + value = binary_test (argv[2], argv[1], argv[3], w); + break; + case -2: + value = binary_test (argv[2], argv[1], argv[3], 0); + break; + case -1: + default: + puts("Invalid data width specifier\n"); + value = 0; + break; + } + + return !value; +} + +U_BOOT_CMD( + itest, 4, 0, do_itest, + "itest - return true/false on integer compare\n", + "[.b, .w, .l, .s] [*]value1 <op> [*]value2\n" +); diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 6ccad70fe1..0a5cca9a93 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -53,6 +53,8 @@ int cmd_get_data_size(char* arg, int default_size) return 2; case 'l': return 4; + case 's': + return -2; default: return -1; } diff --git a/common/hush.c b/common/hush.c index 7e8a80deb9..4712adcbfc 100644 --- a/common/hush.c +++ b/common/hush.c @@ -2173,7 +2173,7 @@ static int set_local_var(const char *s, int flg_export) #ifdef __U_BOOT__ if (getenv(name) != NULL) { printf ("ERROR: " - "There is a global environmet variable with the same name.\n"); + "There is a global environment variable with the same name.\n"); return -1; } #endif diff --git a/cpu/arm720t/Makefile b/cpu/arm720t/Makefile index 8c950daee8..f273d92997 100644 --- a/cpu/arm720t/Makefile +++ b/cpu/arm720t/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -OBJS = serial.o interrupts.o cpu.o +OBJS = serial.o serial_netarm.o interrupts.o cpu.o all: .depend $(START) $(LIB) diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 5637eb672f..0ad5481fd2 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -106,7 +106,9 @@ int cleanup_before_linux (void) unsigned long i; disable_interrupts (); - +#ifdef CONFIG_NETARM + return 0; +#endif /* turn off I-cache */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); i &= ~0x1000; diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index b1ee188ff1..0291193e83 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -30,14 +30,24 @@ #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#ifdef CONFIG_NETARM +#include <asm/arch/netarm_registers.h> +#endif extern void reset_cpu(ulong addr); +#ifndef CONFIG_NETARM /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff - /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff) +#else +#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) +#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) +#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS)) +#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK +#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) +#endif #ifdef CONFIG_USE_IRQ /* enable IRQ/FIQ interrupts */ @@ -177,6 +187,18 @@ static ulong lastdec; int interrupt_init (void) { +#ifdef CONFIG_NETARM + /* disable all interrupts */ + IRQEN = 0; + + /* operate timer 2 in non-prescale mode */ + TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) | + NETARM_GEN_TCTL_ENABLE | + NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); + + /* set timer 2 counter */ + lastdec = TIMER_LOAD_VAL; +#else /* disable all interrupts */ IO_INTMR1 = 0; @@ -188,6 +210,7 @@ int interrupt_init (void) /* set timer 1 counter */ lastdec = IO_TC1D = TIMER_LOAD_VAL; +#endif timestamp = 0; return (0); diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index d38ac39472..5c6a0cc555 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -31,6 +31,8 @@ #include <common.h> #include <clps7111.h> +#ifndef CONFIG_NETARM + void serial_setbrg (void) { DECLARE_GLOBAL_DATA_PTR; @@ -124,3 +126,5 @@ serial_puts (const char *s) serial_putc (*s++); } } + +#endif /* CONFIG_NETARM */ diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c new file mode 100644 index 0000000000..8cfe049b03 --- /dev/null +++ b/cpu/arm720t/serial_netarm.c @@ -0,0 +1,185 @@ +/* + * Serial Port stuff - taken from Linux + * + * (C) Copyright 2002 + * MAZeT GmbH <www.mazet.de> + * Stephan Linz <linz@mazet.de>, <linz@li-pro.net> + * + * (c) 2004 + * IMMS gGmbH <www.imms.de> + * Thomas Elste <info@elste.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/netarm_registers.h> + +#ifdef CONFIG_NETARM + +#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA)) +#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB)) + +/* wait until transmitter is ready for another character */ +#define TXWAITRDY(registers) \ +{ \ + ulong tmo = get_timer(0) + 1 * CFG_HZ; \ + while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ + if (get_timer(0) > tmo) \ + break; \ + } \ +} + + +volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); +volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); + +extern void _netarm_led_FAIL1(void); + +/* + * Setup both serial i/f with given baudrate + */ +void serial_setbrg (void) +{ + /* get the gd pointer */ + DECLARE_GLOBAL_DATA_PTR; + + /* set 0 ... make sure pins are configured for serial */ + PORTA = PORTB = + NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0); + + /* first turn em off */ + serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0; + + /* clear match register, we don't need it */ + serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0; + + /* setup bit rate generator and rx buffer gap timer (1 byte only) */ + if ((gd->baudrate >= MIN_BAUD_RATE) + && (gd->baudrate <= MAX_BAUD_RATE)) { + serial_reg_ch1->bitrate = serial_reg_ch2->bitrate = + NETARM_SER_BR_X16 (gd->baudrate); + serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer = + 0; + serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer = + NETARM_SER_RXGAP (gd->baudrate); + } else { + hang (); + } + + /* setup port mode */ + serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b = + ( NETARM_SER_CTLB_RCGT_EN | + NETARM_SER_CTLB_UART_MODE); + serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = + ( NETARM_SER_CTLA_ENABLE | + NETARM_SER_CTLA_P_NONE | + /* see errata */ + NETARM_SER_CTLA_2STOP | + NETARM_SER_CTLA_8BITS | + NETARM_SER_CTLA_DTR_EN | + NETARM_SER_CTLA_RTS_EN); +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +int serial_init (void) +{ + serial_setbrg (); + return 0; +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + volatile unsigned char *fifo; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); + + fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo); + TXWAITRDY (serial_reg_ch1); + *fifo = c; +} + +/* + * Test of a single byte from the serial port. Returns 1 on success, 0 + * otherwise. + */ +int serial_tstc(void) +{ + return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. + */ +int serial_getc (void) +{ + unsigned int ch_uint; + volatile unsigned int *fifo; + volatile unsigned char *fifo_char = NULL; + int buf_count = 0; + + while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY)) + /* NOP */ ; + + fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo); + fifo_char = (unsigned char *) &ch_uint; + ch_uint = *fifo; + + buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a); + switch (buf_count) { + case NETARM_SER_STATA_RXFDB_4BYTES: + buf_count = 4; + break; + case NETARM_SER_STATA_RXFDB_3BYTES: + buf_count = 3; + break; + case NETARM_SER_STATA_RXFDB_2BYTES: + buf_count = 2; + break; + case NETARM_SER_STATA_RXFDB_1BYTES: + buf_count = 1; + break; + default: + /* panic, be never here */ + } + + serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED; + + return ch_uint & 0xff; +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +#endif /* CONFIG_NETARM */ diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 7fe36c6ded..791049a2f5 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -26,7 +26,9 @@ #include <config.h> #include <version.h> - +#ifdef CONFIG_NETARM +#include <asm/arch/netarm_registers.h> +#endif /* ************************************************************************* @@ -195,6 +197,7 @@ SYSCON3: .word 0x80002200 #define CLKCTL_73 0x6 /* 73.728 MHz */ cpu_init_crit: +#ifndef CONFIG_NETARM /* * mask all IRQs by clearing all bits in the INTMRs */ @@ -221,6 +224,54 @@ cpu_init_crit: bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) orr r0, r0, #0x00000002 @ set bit 2 (A) Align mcr p15,0,r0,c1,c0 +#else /* CONFIG_NETARM */ + /* + * prior to software reset : need to set pin PORTC4 to be *HRESET + */ + ldr r0, =NETARM_GEN_MODULE_BASE + ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \ + NETARM_GEN_PORT_DIR(0x10)) + str r1, [r0, #+NETARM_GEN_PORTC] + /* + * software reset : see HW Ref. Guide 8.2.4 : Software Service register + * for an explanation of this process + */ + ldr r0, =NETARM_GEN_MODULE_BASE + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE] + /* + * setup PLL and System Config + */ + ldr r0, =NETARM_GEN_MODULE_BASE + + ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \ + NETARM_GEN_SYS_CFG_BUSFULL | \ + NETARM_GEN_SYS_CFG_USER_EN | \ + NETARM_GEN_SYS_CFG_ALIGN_ABORT | \ + NETARM_GEN_SYS_CFG_BUSARB_INT | \ + NETARM_GEN_SYS_CFG_BUSMON_EN ) + + str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL] + + ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \ + NETARM_GEN_PLL_CTL_POLTST_DEF | \ + NETARM_GEN_PLL_CTL_INDIV(1) | \ + NETARM_GEN_PLL_CTL_ICP_DEF | \ + NETARM_GEN_PLL_CTL_OUTDIV(2) ) + str r1, [r0, #+NETARM_GEN_PLL_CONTROL] + /* + * mask all IRQs by clearing all bits in the INTMRs + */ + mov r1, #0 + ldr r0, =NETARM_GEN_MODULE_BASE + str r1, [r0, #+NETARM_GEN_INTR_ENABLE] +#endif /* CONFIG_NETARM */ #ifdef CONFIG_ARM7_REVD /* set clock speed */ @@ -415,6 +466,7 @@ fiq: .align 5 .globl reset_cpu reset_cpu: +#ifndef CONFIG_NETARM mov ip, #0 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) @@ -423,3 +475,21 @@ reset_cpu: bic ip, ip, #0x2100 @ ..v....s........ mcr p15, 0, ip, c1, c0, 0 @ ctrl register mov pc, r0 +#else + ldr r1, =NETARM_MEM_MODULE_BASE + ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] + ldr r1, =0xFFFFF000 + and r0, r1, r0 + ldr r1, =(relocate-TEXT_BASE) + add r0, r1, r0 + ldr r4, =NETARM_GEN_MODULE_BASE + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETA + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + ldr r1, =NETARM_GEN_SW_SVC_RESETB + str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE] + mov pc, r0 +#endif diff --git a/doc/README.commands.itest b/doc/README.commands.itest new file mode 100644 index 0000000000..db54160e1f --- /dev/null +++ b/doc/README.commands.itest @@ -0,0 +1,16 @@ +A slow day today so here is a revised itest command with provisional +support for comparing strings as well :-)) + +Now table driven to allow the operators +-eq, -ne, -lt, -gt, -le, -ge, ==, !=, <>, <, >, <=, >= + +Uses the expected command modifier for integer compares of width 1, 2 or +4 bytes of .b, .w, .l and the new modifer of .s for a string compare. +String comparison is over the length of the shorter, this hopefully +avoids missing terminators when using an indirect pointer. + +eg. +if itest.l *40000 == 12345678 then; .... +if itest.w *40000 != 1234 then; .... +if itest.b *40000 >= 12 then; .... +if itest.s *40000 -eq hello then; .... diff --git a/doc/README.modnet50 b/doc/README.modnet50 new file mode 100644 index 0000000000..de7165c927 --- /dev/null +++ b/doc/README.modnet50 @@ -0,0 +1,62 @@ +U-BOOT Port for FSForth ModNET50 Board +-------------------------------------- + +author: Thomas Elste <info@elste.org> + IMMS gGmbH <www.imms.de> + +The port based upon an early (partial complete) +armboot-port from Stephan Linz for the ModNET50 Board. + + +Overview: + +- board with Netsilicon NET+50 ARM7TDMI CPU without MMU +- 16 MB SDRAM +- 2 MB Flash (MBL29LV160BE) +- 10/100 Ethernet PHY (LXT971A) + + +Current Configuration (include/configs/modnet50.h): + +Memory Map: 0x00000000 - 0x00FFFFFF 16M SDRAM + 0x10000000 - 0x101FFFFF 2M Flash + +The Flash uses a BB-Architectur with 35 sectors +(0:16K; 1,2:8K; 3:32K; 4-34:64K). U-Boot is located in +the first 5 sectors. + +The environment is located at the end of the 4th Flash +sector (0x1001C000-0x1001FFFF). + +Build: + +U-boot should be build by using the ELDK Toolchain (arm-linux-*). + + make modnet50_config + make + + +Status: + +Everything seems to work fine. Booting images was tested by +booting uCLinux (with and without a separate ramdisk image) from +flash. + + +Files: + +cpu/arm720t/serial_netarm.c .. serial I/O for the cpu + +board/modnet50/memsetup.S .. memory setup for ModNET50 +board/modnet50/flash.c .. flash routines +board/modnet50/modnet50.c .. some board init stuff + +drivers/netarm_eth.c .. ethernet driver for the NET+50 CPU +drivers/netarm_eth.h .. header for ethernet driver + +include/configs/modnet50.h .. configuration file for ModNET50 + +include/netarm_*.h .. register and macro definitions for + the NETARM CPU family + +doc/README.modnet50 .. this readme diff --git a/drivers/Makefile b/drivers/Makefile index 2999eb465a..b333aed678 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -32,24 +32,16 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ cs8900.o ct69000.o dataflash.o dc2114x.o \ e1000.o eepro100.o \ i8042.o i82365.o inca-ip_sw.o \ - lan91c96.o natsemi.o \ + lan91c96.o natsemi.o netarm_eth.o \ ns16550.o ns8382x.o ns87308.o \ pci.o pci_auto.o pci_indirect.o \ pcnet.o plb2800_eth.o \ ps2ser.o ps2mult.o pc_keyb.o keyboard.o \ rtl8019.o rtl8139.o \ - s3c24x0_i2c.o sed13806.o serial.o \ - serial_max3100.o \ - smc91111.o smiLynxEM.o sym53c8xx.o \ - status_led.o \ + s3c24x0_i2c.o sed13806.o serial.o serial_max3100.o \ + smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \ ti_pci1410a.o tigon3.o w83c553f.o -## Disabled for now: -## cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \ -## lan91c96.o mw_eeprom.o natsemi.o \ -## smc91111.o smiLynxEM.o spi_eeprom.o sym53c8xx.o \ -## - all: $(LIB) $(LIB): $(OBJS) diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index c6c2751d64..95179aeb65 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -36,13 +36,14 @@ * * Tested Architectures * Port Width Chip Width # of banks Flash Chip Board - * 32 16 1 23F128J3 seranoa/eagle - * 64 16 1 23F128J3 seranoa/falcon + * 32 16 1 28F128J3 seranoa/eagle + * 64 16 1 28F128J3 seranoa/falcon * */ /* The DEBUG define must be before common to enable debugging */ -#undef DEBUG +/* #define DEBUG */ + #include <common.h> #include <asm/processor.h> #ifdef CFG_FLASH_CFI_DRIVER diff --git a/drivers/netarm_eth.c b/drivers/netarm_eth.c new file mode 100644 index 0000000000..a15b653e73 --- /dev/null +++ b/drivers/netarm_eth.c @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2004 IMMS gGmbH <www.imms.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * author(s): Thomas Elste, <info@elste.org> + * (some parts derived from uCLinux Netarm Ethernet Driver) + */ + + +#include <common.h> +#include <command.h> +#include <net.h> +#include "netarm_eth.h" +#include <asm/arch/netarm_registers.h> + +#ifdef CONFIG_DRIVER_NETARMETH + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +static int na_mii_poll_busy (void); + +static void na_get_mac_addr (void) +{ + unsigned short p[3]; + char *m_addr; + char ethaddr[20]; + + m_addr = (char *) p; + + p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1); + p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2); + p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3); + + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + m_addr[0], m_addr[1], + m_addr[2], m_addr[3], m_addr[4], m_addr[5]); + + printf ("HW-MAC Address: %s\n", ethaddr); + + /* set env, todo: check if already an adress is set */ + setenv ("ethaddr", ethaddr); +} + + +static void na_mii_write (int reg, int value) +{ + int mii_addr; + + /* Select register */ + mii_addr = CFG_ETH_PHY_ADDR + reg; + SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); + /* Write value */ + SET_EADDR (NETARM_ETH_MII_WRITE, value); + na_mii_poll_busy (); +} + +static unsigned int na_mii_read (int reg) +{ + int mii_addr, val; + + /* Select register */ + mii_addr = CFG_ETH_PHY_ADDR + reg; + SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); + /* do one management cycle */ + SET_EADDR (NETARM_ETH_MII_CMD, + GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT); + na_mii_poll_busy (); + /* Return read value */ + val = GET_EADDR (NETARM_ETH_MII_READ); + return val; +} + +static int na_mii_poll_busy (void) +{ + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) { + if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { + return 1; + } + } + printf ("na_mii_busy timeout\n"); + return (0); +} + +static int na_mii_identify_phy (void) +{ + int id_reg_a = 0; + + /* get phy id register */ + id_reg_a = na_mii_read (MII_PHY_ID); + + if (id_reg_a == 0x0043) { + /* This must be an Enable or a Lucent LU3X31 PHY chip */ + return 1; + } else if (id_reg_a == 0x0013) { + /* it is an Intel LXT971A */ + return 1; + } + return (0); +} + +static int na_mii_negotiate (void) +{ + int i = 0; + + /* Enable auto-negotiation */ + na_mii_write (MII_PHY_AUTONEGADV, 0x01e1); + /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */ + /* Restart auto-negotiation */ + na_mii_write (MII_PHY_CONTROL, 0x1200); + + /* status register is 0xffff after setting the autoneg restart bit */ + while (na_mii_read (MII_PHY_STATUS) == 0xffff) { + i++; + } + + /* na_mii_read uses the timer already, so we can't use it again for + timeout checking. + Instead we just try some times. + */ + for (i = 0; i < 40000; i++) { + if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) { + return 0; + } + } + /* + printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS)); + */ + return (1); +} + +static unsigned int na_mii_check_speed (void) +{ + unsigned int status; + + /* Read Status register */ + status = na_mii_read (MII_PHY_STATUS); + /* Check link status. If 0, default to 100 Mbps. */ + if ((status & 0x0004) == 0) { + printf ("*Warning* no link detected, set default speed to 100Mbs\n"); + return 1; + } else { + if ((na_mii_read (17) & 0x4000) != 0) { + printf ("100Mbs link detected\n"); + return 1; + } else { + printf ("10Mbs link detected\n"); + return 0; + } + } + return 0; +} + +static int reset_eth (void) +{ + int pt; + + na_get_mac_addr (); + pt = na_mii_identify_phy (); + + /* reset the phy */ + na_mii_write (MII_PHY_CONTROL, 0x8000); + reset_timer_masked (); + while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) { + if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { + break; + } + } + if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY) + printf ("phy reset timeout\n"); + + /* set the PCS reg */ + SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M | + NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR); + + na_mii_negotiate (); + na_mii_check_speed (); + + /* Delay 10 millisecond. (Maybe this should be 1 second.) */ + udelay (10000); + + /* Turn receive on. + Enable statistics register autozero on read. + Do not insert MAC address on transmit. + Do not enable special test modes. */ + SET_EADDR (NETARM_ETH_STL_CFG, + (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN)); + + /* Set the inter-packet gap delay to 0.96us for MII. + The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG + Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG + Gap Timer Register should be set to 0x00000C12 for the MII PHY. */ + SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15); + SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12); + + /* Add CRC to end of packets. + Pad packets to minimum length of 64 bytes. + Allow unlimited length transmit packets. + Receive all broadcast packets. + NOTE: Multicast addressing is NOT enabled here currently. */ + SET_EADDR (NETARM_ETH_MAC_CFG, + (NETARM_ETH_MACC_CRCEN | + NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN)); + SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD); + + /* enable fifos */ + SET_EADDR (NETARM_ETH_GEN_CTRL, + (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX)); + + return (0); +} + + +extern int eth_init (bd_t * bd) +{ + reset_eth (); + return 0; +} + +extern void eth_halt (void) +{ + SET_EADDR (NETARM_ETH_GEN_CTRL, 0); +} + +/* Get a data block via Ethernet */ +extern int eth_rx (void) +{ + int i; + unsigned short rxlen; + unsigned int *addr; + unsigned int rxstatus, lastrxlen; + char *pa; + + /* RXBR is 1, data block was received */ + if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0) + return 0; + + /* get status register and the length of received block */ + rxstatus = GET_EADDR (NETARM_ETH_RX_STAT); + rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16; + + if (rxlen == 0) + return 0; + + /* clear RXBR to make fifo available */ + SET_EADDR (NETARM_ETH_GEN_STAT, + GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR); + + /* clear TXBC to make fifo available */ + /* According to NETARM50 data manual you just have to clear + RXBR but that has no effect. Only after clearing TXBC the + Fifo becomes readable. */ + SET_EADDR (NETARM_ETH_GEN_STAT, + GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC); + + addr = (unsigned int *) NetRxPackets[0]; + pa = (char *) NetRxPackets[0]; + + /* read the fifo */ + for (i = 0; i < rxlen / 4; i++) { + *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); + addr++; + } + + if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) { + /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ + lastrxlen = + (GET_EADDR (NETARM_ETH_GEN_STAT) & + NETARM_ETH_GST_RXFDB) >> 28; + *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); + switch (lastrxlen) { + case 1: + *addr &= 0xff000000; + break; + case 2: + *addr &= 0xffff0000; + break; + case 3: + *addr &= 0xffffff00; + break; + } + } + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + return rxlen; +} + +/* Send a data block via Ethernet. */ +extern int eth_send (volatile void *packet, int length) +{ + int i, length32; + char *pa; + unsigned int *pa32, lastp = 0, rest; + + pa = (char *) packet; + pa32 = (unsigned int *) packet; + length32 = length / 4; + rest = length % 4; + + /* make sure there's no garbage in the last word */ + switch (rest) { + case 0: + lastp = pa32[length32]; + length32--; + break; + case 1: + lastp = pa32[length32] & 0x000000ff; + break; + case 2: + lastp = pa32[length32] & 0x0000ffff; + break; + case 3: + lastp = pa32[length32] & 0x00ffffff; + break; + } + + /* write to the fifo */ + for (i = 0; i < length32; i++) + SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]); + + /* the last word is written to an extra register, this + starts the transmission */ + SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp); + + /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission + went fine. But we can't use the timer for a timeout loop because + of it is used already in upper layers. So we just try some times. */ + i = 0; + while (i < 50000) { + if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK) + == NETARM_ETH_TXSTAT_TXOK) + return 0; + i++; + } + + printf ("eth_send timeout\n"); + return 1; +} + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/netarm_eth.h b/drivers/netarm_eth.h new file mode 100644 index 0000000000..8edab82da3 --- /dev/null +++ b/drivers/netarm_eth.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2003 IMMS gGmbH <www.imms.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * author(s): Thomas Elste, <info@elste.org> + */ + +#include <asm/types.h> +#include <config.h> + +#ifdef CONFIG_DRIVER_NETARMETH + +#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val +#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE)) + +#define NA_MII_POLL_BUSY_DELAY 900 + +/* MII negotiation timeout value + 500 jiffies = 5 seconds */ +#define NA_MII_NEGOTIATE_DELAY 30 + +/* Registers in the physical layer chip */ +#define MII_PHY_CONTROL 0 +#define MII_PHY_STATUS 1 +#define MII_PHY_ID 2 +#define MII_PHY_AUTONEGADV 4 + +#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/fs/fat/fat.c b/fs/fat/fat.c index f02c404a8b..daa70349d2 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -432,12 +432,13 @@ get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, dir_entry *realdent; dir_slot *slotptr = (dir_slot*) retdent; __u8 *nextclust = cluster + mydata->clust_size * SECTOR_SIZE; - __u8 counter = slotptr->id & 0xf; + __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff; int idx = 0; while ((__u8*)slotptr < nextclust) { if (counter == 0) break; - if ((slotptr->id & 0x0f) != counter) return -1; + if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter) + return -1; slotptr++; counter--; } @@ -475,7 +476,7 @@ get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, do { slotptr--; if (slot2str(slotptr, l_name, &idx)) break; - } while (!(slotptr->id & 0x40)); + } while (!(slotptr->id & LAST_LONG_ENTRY_MASK)); l_name[idx] = '\0'; if (*l_name == DELETED_FLAG) *l_name = '\0'; @@ -536,7 +537,7 @@ static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, if ((dentptr->attr & ATTR_VOLUME)) { #ifdef CONFIG_SUPPORT_VFAT if ((dentptr->attr & ATTR_VFAT) && - (dentptr->name[0] & 0x40)) { + (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { prevcksum = ((dir_slot *) dentptr) ->alias_checksum; get_vfatname (mydata, curclust, get_dentfromdir_block, @@ -799,7 +800,7 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, if ((dentptr->attr & ATTR_VOLUME)) { #ifdef CONFIG_SUPPORT_VFAT if ((dentptr->attr & ATTR_VFAT) && - (dentptr->name[0] & 0x40)) { + (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { prevcksum = ((dir_slot *) dentptr)->alias_checksum; get_vfatname (mydata, 0, do_fat_read_block, dentptr, l_name); if (dols == LS_ROOT) { diff --git a/include/asm-arm/arch-arm720t/netarm_dma_module.h b/include/asm-arm/arch-arm720t/netarm_dma_module.h new file mode 100644 index 0000000000..c5170359a2 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_dma_module.h @@ -0,0 +1,184 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_dma_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * David Smith + */ + +#ifndef __NETARM_DMA_MODULE_REGISTERS_H +#define __NETARM_DMA_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_DMA_MODULE_BASE (0xFF900000) + +#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c))) + +#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00) +#define NETARM_DMA1A_CONTROL (0x10) +#define NETARM_DMA1A_STATUS (0x14) +#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20) +#define NETARM_DMA1B_CONTROL (0x30) +#define NETARM_DMA1B_STATUS (0x34) +#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40) +#define NETARM_DMA1C_CONTROL (0x50) +#define NETARM_DMA1C_STATUS (0x54) +#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60) +#define NETARM_DMA1D_CONTROL (0x70) +#define NETARM_DMA1D_STATUS (0x74) + +#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80) +#define NETARM_DMA2_CONTROL (0x90) +#define NETARM_DMA2_STATUS (0x94) + +#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0) +#define NETARM_DMA3_CONTROL (0xB0) +#define NETARM_DMA3_STATUS (0xB4) + +#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0) +#define NETARM_DMA4_CONTROL (0xD0) +#define NETARM_DMA4_STATUS (0xD4) + +#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0) +#define NETARM_DMA5_CONTROL (0xF0) +#define NETARM_DMA5_STATUS (0xF4) + +#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100) +#define NETARM_DMA6_CONTROL (0x110) +#define NETARM_DMA6_STATUS (0x114) + +#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120) +#define NETARM_DMA7_CONTROL (0x130) +#define NETARM_DMA7_STATUS (0x134) + +#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140) +#define NETARM_DMA8_CONTROL (0x150) +#define NETARM_DMA8_STATUS (0x154) + +#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160) +#define NETARM_DMA9_CONTROL (0x170) +#define NETARM_DMA9_STATUS (0x174) + +#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180) +#define NETARM_DMA10_CONTROL (0x190) +#define NETARM_DMA10_STATUS (0x194) + +/* select bitfield defintions */ + +/* DMA Control Register ( 0xFF90_0XX0 ) */ + +#define NETARM_DMA_CTL_ENABLE (0x80000000) + +#define NETARM_DMA_CTL_ABORT (0x40000000) + +#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000) +#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000) +#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000) +#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000) + +#define NETARM_DMA_CTL_BUS_MASK (0x30000000) + +#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000) +#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000) +#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000) + +#define NETARM_DMA_CTL_BURST_NONE (0x00000000) +#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000) +#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000) + +#define NETARM_DMA_CTL_BURST_MASK (0x03000000) + +#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000) + +#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000) + +/* these apply only to ext xfers on DMA 3 or 4 */ + +#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000) + +#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000) +#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000) +#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000) + +#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00) +#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF) + +/* DMA Status Register ( 0xFF90_0XX4 ) */ + +#define NETARM_DMA_STAT_NC_INTPEN (0x80000000) +#define NETARM_DMA_STAT_EC_INTPEN (0x40000000) +#define NETARM_DMA_STAT_NR_INTPEN (0x20000000) +#define NETARM_DMA_STAT_CA_INTPEN (0x10000000) +#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000) + +#define NETARM_DMA_STAT_NC_INT_EN (0x00800000) +#define NETARM_DMA_STAT_EC_INT_EN (0x00400000) +#define NETARM_DMA_STAT_NR_INT_EN (0x00200000) +#define NETARM_DMA_STAT_CA_INT_EN (0x00100000) +#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000) + +#define NETARM_DMA_STAT_WRAP (0x00080000) +#define NETARM_DMA_STAT_IDONE (0x00040000) +#define NETARM_DMA_STAT_LAST (0x00020000) +#define NETARM_DMA_STAT_FULL (0x00010000) + +#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF) + +/* DMA Buffer Descriptor Word 0 bitfields. */ + +#define NETARM_DMA_BD0_WRAP (0x80000000) +#define NETARM_DMA_BD0_IDONE (0x40000000) +#define NETARM_DMA_BD0_LAST (0x20000000) +#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF) + +/* DMA Buffer Descriptor Word 1 bitfields. */ + +#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000) +#define NETARM_DMA_BD1_FULL (0x00008000) +#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF) + +#ifndef __ASSEMBLER__ + +typedef struct __NETARM_DMA_Buff_Desc_FlyBy +{ + unsigned int word0; + unsigned int word1; +} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ; + +typedef struct __NETARM_DMA_Buff_Desc_M_to_M +{ + unsigned int word0; + unsigned int word1; + unsigned int word2; + unsigned int word3; +} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ; + +#endif + +#endif + diff --git a/include/asm-arm/arch-arm720t/netarm_eni_module.h b/include/asm-arm/arch-arm720t/netarm_eni_module.h new file mode 100644 index 0000000000..317b354513 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_eni_module.h @@ -0,0 +1,121 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_eni_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : David Smith + */ + +#ifndef __NETARM_ENI_MODULE_REGISTERS_H +#define __NETARM_ENI_MODULE_REGISTERS_H + +/* ENI unit register offsets */ + +/* #ifdef CONFIG_ARCH_NETARM */ +#define NETARM_ENI_MODULE_BASE (0xFFA00000) +/* #endif / * CONFIG_ARCH_NETARM */ + +#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c))) +#define get_eni_ctl_reg_addr(minor) \ + (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor)) + +#define NETARM_ENI_GENERAL_CONTROL (0x00) +#define NETARM_ENI_STATUS_CONTROL (0x04) +#define NETARM_ENI_FIFO_MODE_DATA (0x08) + +#define NETARM_ENI_1284_PORT1_CONTROL (0x10) +#define NETARM_ENI_1284_PORT2_CONTROL (0x14) +#define NETARM_ENI_1284_PORT3_CONTROL (0x18) +#define NETARM_ENI_1284_PORT4_CONTROL (0x1c) + +#define NETARM_ENI_1284_CHANNEL1_DATA (0x20) +#define NETARM_ENI_1284_CHANNEL2_DATA (0x24) +#define NETARM_ENI_1284_CHANNEL3_DATA (0x28) +#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c) + +#define NETARM_ENI_ENI_CONTROL (0x30) +#define NETARM_ENI_ENI_PULSED_INTR (0x34) +#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38) +#define NETARM_ENI_ENI_SHARED (0x3c) + +/* select bitfield defintions */ + +/* General Control Register (0xFFA0_0000) */ + +#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001) +#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004) +#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005) +#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006) +#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007) + +#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007) + +/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014, + 0xFFA0_0018, 0xFFA0_001c) */ + +#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000) +#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000) +#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000) +#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000) +#define NETARM_ENI_1284PC_ECP_MODE (0x08000000) +#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000) + +#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */ +#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */ +#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000) + +#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000) +#define NETARM_ENI_1284PC_FAST_MODE (0x00400000) +#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000) + +#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000) +#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000) +#define NETARM_ENI_1284PC_INIT (0x00020000) +#define NETARM_ENI_1284PC_HSELECT (0x00010000) +#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000) +#define NETARM_ENI_1284PC_EPP_MODE (0x00004000) +#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000) +#define NETARM_ENI_1284PC_IBR (0x00001000) + +#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400) +#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800) +#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00) +#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000) + +#define NETARM_ENI_1284PC_RBCC (0x00000200) +#define NETARM_ENI_1284PC_RBCT (0x00000100) +#define NETARM_ENI_1284PC_ACK (0x00000080) +#define NETARM_ENI_1284PC_FIFO_E (0x00000040) +#define NETARM_ENI_1284PC_OBE (0x00000020) +#define NETARM_ENI_1284PC_ACK_INT (0x00000010) +#define NETARM_ENI_1284PC_BUSY (0x00000008) +#define NETARM_ENI_1284PC_PE (0x00000004) +#define NETARM_ENI_1284PC_PSELECT (0x00000002) +#define NETARM_ENI_1284PC_FAULT (0x00000001) + +#endif /* __NETARM_ENI_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_eth_module.h b/include/asm-arm/arch-arm720t/netarm_eth_module.h new file mode 100644 index 0000000000..8f2f36981a --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_eth_module.h @@ -0,0 +1,160 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_eth_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Jackie Smith Cashion + * David Smith + */ + +#ifndef __NETARM_ETH_MODULE_REGISTERS_H +#define __NETARM_ETH_MODULE_REGISTERS_H + +/* ETH unit register offsets */ + +#define NETARM_ETH_MODULE_BASE (0xFF800000) + +#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) + +#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ +#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ +#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ +#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ +#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ +#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ + +#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ +#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ +#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ +#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG + Gap Timer Reg */ +#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back + IPG Gap Timer Reg */ +#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ +#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ +#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ +#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ +#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ +#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ +#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ +#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ +#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ +#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ +#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ +#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral + Counter */ +#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ +#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address + Filter Reg */ +#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address + Reg */ +#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) +#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) +#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ +#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) +#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) +#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) + +/* select bitfield defintions */ + +/* Ethernet General Control Register (0xFF80_0000) */ + +#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ +#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ +#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ +#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ +#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water + Mark. Start transmit + when FIFO is 50% + full. */ +#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer + Descriptor Format */ + +/* Ethernet General Status Register (0xFF80_0004) */ + +#define NETARM_ETH_GST_RXFDB (0x30000000) +#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register + Ready */ +#define NETARM_ETH_GST_RXFIFOH (0x04000000) +#define NETARM_ETH_GST_RXBR (0x02000000) +#define NETARM_ETH_GST_RXSKIP (0x01000000) + +#define NETARM_ETH_GST_TXBC (0x00020000) + + +/* Ethernet Transmit Status Register (0xFF80_0010) */ + +#define NETARM_ETH_TXSTAT_TXOK (0x00008000) + + +/* Ethernet Receive Status Register (0xFF80_0014) */ + +#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) +#define NETARM_ETH_RXSTAT_RXOK (0x00002000) + + +/* PCS Configuration Register (0xFF80_0408) */ + +#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ +#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ +#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ +#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ + +/* STL Configuration Register (0xFF80_0410) */ + +#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ +#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ + +/* MAC Configuration Register (0xFF80_0400) */ + +#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit + Frame Sizes */ +#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames + to 64 Bytes */ +#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit + Frames */ + +/* MII (PHY) Command Register (0xFF80_0540) */ + +#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ + +/* MII Indicators Register (0xFF80_0550) */ + +#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with + Read/Write */ + +/* SAL Station Address Filter Register (0xFF80_05C0) */ + +#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ +#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast + Packets */ +#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets + using Hash Table */ +#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast + Packets */ + + +#endif /* __NETARM_GEN_MODULE_REGISTERS_H */ diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h new file mode 100644 index 0000000000..6ab5cc10fa --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_gen_module.h @@ -0,0 +1,170 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_gen_module.h + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + */ + +#ifndef __NETARM_GEN_MODULE_REGISTERS_H +#define __NETARM_GEN_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_GEN_MODULE_BASE (0xFFB00000) + +#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) + +#define NETARM_GEN_SYSTEM_CONTROL (0x00) +#define NETARM_GEN_STATUS_CONTROL (0x04) +#define NETARM_GEN_PLL_CONTROL (0x08) +#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) + +#define NETARM_GEN_TIMER1_CONTROL (0x10) +#define NETARM_GEN_TIMER1_STATUS (0x14) +#define NETARM_GEN_TIMER2_CONTROL (0x18) +#define NETARM_GEN_TIMER2_STATUS (0x1c) + +#define NETARM_GEN_PORTA (0x20) +#define NETARM_GEN_PORTB (0x24) +#define NETARM_GEN_PORTC (0x28) + +#define NETARM_GEN_INTR_ENABLE (0x30) +#define NETARM_GEN_INTR_ENABLE_SET (0x34) +#define NETARM_GEN_INTR_ENABLE_CLR (0x38) +#define NETARM_GEN_INTR_STATUS_EN (0x34) +#define NETARM_GEN_INTR_STATUS_RAW (0x38) + +#define NETARM_GEN_CACHE_CONTROL1 (0x40) +#define NETARM_GEN_CACHE_CONTROL2 (0x44) + +/* select bitfield definitions */ + +/* System Control Register ( 0xFFB0_0000 ) */ + +#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) +#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) + +#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) +#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) +#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) + +#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) + +#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) +#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) +#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) +#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) +#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) +#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) +#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) +#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) + +#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) +#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) +#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) +#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) +#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) + +#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) +#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) + +#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) +#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) + +#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) + +#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) + +#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) + +#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) + +#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) + +#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) + +/* PLL Control Register ( 0xFFB0_0008 ) */ + +#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) + +#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ + NETARM_GEN_PLL_CTL_PLLCNT_MASK) + +/* Defaults for POLTST and ICP Fields in PLL CTL */ +#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) +#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) +#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) +#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) + + +/* Software Service Register ( 0xFFB0_000C ) */ + +#define NETARM_GEN_SW_SVC_RESETA (0x123) +#define NETARM_GEN_SW_SVC_RESETB (0x321) + +/* PORT C Register ( 0xFFB0_0028 ) */ + +#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) +#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) + +/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ + +#define NETARM_GEN_TCTL_ENABLE (0x80000000) +#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) + +#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) +#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) + +#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) +#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) + +#define NETARM_GEN_TSTAT_INTPEN (0x40000000) +#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) + +/* prescale to msecs conversion */ + +#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ + NETARM_GEN_TSTAT_CTC_MASK ) + \ + 1 ) ) / (NETARM_XTAL_FREQ/1000) ) + +#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ + NETARM_GEN_TSTAT_CTC_MASK ) | \ + NETARM_GEN_TCTL_USE_PRESCALE ) + +#if 0 +/* ifdef CONFIG_NETARM_PLL_BYPASS else */ +#error test +#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ + NETARM_GEN_TSTAT_CTC_MASK ) + \ + 1 ) ) / (NETARM_XTAL_FREQ/1000) ) + +#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ + NETARM_GEN_TSTAT_CTC_MASK ) | \ + NETARM_GEN_TCTL_USE_PRESCALE ) +#endif + +#endif diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h new file mode 100644 index 0000000000..02ca9fb571 --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -0,0 +1,158 @@ +/* + * include/asm-armnommu/arch-netarm/netarm_mem_module.h + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + */ + +#ifndef __NETARM_MEM_MODULE_REGISTERS_H +#define __NETARM_MEM_MODULE_REGISTERS_H + +/* GEN unit register offsets */ + +#define NETARM_MEM_MODULE_BASE (0xFFC00000) + +#define NETARM_MEM_MODULE_CONFIG (0x00) +#define NETARM_MEM_CS0_BASE_ADDR (0x10) +#define NETARM_MEM_CS0_OPTIONS (0x14) +#define NETARM_MEM_CS1_BASE_ADDR (0x20) +#define NETARM_MEM_CS1_OPTIONS (0x24) +#define NETARM_MEM_CS2_BASE_ADDR (0x30) +#define NETARM_MEM_CS2_OPTIONS (0x34) +#define NETARM_MEM_CS3_BASE_ADDR (0x40) +#define NETARM_MEM_CS3_OPTIONS (0x44) +#define NETARM_MEM_CS4_BASE_ADDR (0x50) +#define NETARM_MEM_CS4_OPTIONS (0x54) + +/* select bitfield defintions */ + +/* Module Configuration Register ( 0xFFC0_0000 ) */ + +#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000) +#define NETARM_MEM_CFG_REFRESH_EN (0x00800000) + +#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000) +#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000) +#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000) +#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000) + +#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000) + +#define NETARM_MEM_CFG_A27_ADDR (0x00080000) +#define NETARM_MEM_CFG_A27_CS0OE (0x00000000) + +#define NETARM_MEM_CFG_A26_ADDR (0x00040000) +#define NETARM_MEM_CFG_A26_CS0WE (0x00000000) + +#define NETARM_MEM_CFG_A25_ADDR (0x00020000) +#define NETARM_MEM_CFG_A25_BLAST (0x00000000) + +#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000) + + +/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ +/* the expression will round down, so make sure to reverse it to verify */ +/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */ +/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */ + +#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ + (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \ + ) - (1) ) << (24))) + +#if 0 +/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */ +/* the expression will round down, so make sure to reverse it toverify */ +/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */ + +#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \ + (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \ + ) - (1) ) << (24))) +#endif + +/* Base Address Registers (0xFFC0_00X0) */ + +#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000) + +/* macro to define base */ + +#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) + +#define NETARM_MEM_BAR_DRAM_FP (0x00000000) +#define NETARM_MEM_BAR_DRAM_EDO (0x00000100) +#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200) + +#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000) +#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080) + +#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000) +#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020) + +#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010) + +#define NETARM_MEM_BAR_DRAM_SEL (0x00000008) + +#define NETARM_MEM_BAR_BURST_EN (0x00000004) + +#define NETARM_MEM_BAR_WRT_PROT (0x00000002) + +#define NETARM_MEM_BAR_VALID (0x00000001) + +/* Option Registers (0xFFC0_00X4) */ + +/* macro to define which bits of the base are significant */ + +#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK) + +#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00) + +#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK ) + +#define NETARM_MEM_OPT_BCYC_1 (0x00000000) +#define NETARM_MEM_OPT_BCYC_2 (0x00000040) +#define NETARM_MEM_OPT_BCYC_3 (0x00000080) +#define NETARM_MEM_OPT_BCYC_4 (0x000000C0) + +#define NETARM_MEM_OPT_BSIZE_2 (0x00000000) +#define NETARM_MEM_OPT_BSIZE_4 (0x00000010) +#define NETARM_MEM_OPT_BSIZE_8 (0x00000020) +#define NETARM_MEM_OPT_BSIZE_16 (0x00000030) + +#define NETARM_MEM_OPT_32BIT (0x00000000) +#define NETARM_MEM_OPT_16BIT (0x00000004) +#define NETARM_MEM_OPT_8BIT (0x00000008) +#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C) + +#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C) + +#define NETARM_MEM_OPT_READ_ASYNC (0x00000000) +#define NETARM_MEM_OPT_READ_SYNC (0x00000002) + +#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000) +#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001) + +#endif + diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h new file mode 100644 index 0000000000..231a37843e --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_registers.h @@ -0,0 +1,80 @@ +/* + * linux/include/asm-arm/arch-netarm/netarm_registers.h + * + * Copyright (C) 2000, 2001 NETsilicon, Inc. + * Copyright (C) 2000, 2001 WireSpeed Communications Corporation + * + * This software is copyrighted by WireSpeed. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall WireSpeed + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + */ + +#ifndef __NET_ARM_REGISTERS_H +#define __NET_ARM_REGISTERS_H + +#include <config.h> + +/* fundamental constants : */ +/* the input crystal/clock frequency ( in Hz ) */ +#define NETARM_XTAL_FREQ_25MHz (18432000) +#define NETARM_XTAL_FREQ_33MHz (23698000) +#define NETARM_XTAL_FREQ_EMLIN1 (20000000) + +/* the frequency of SYS_CLK */ +#if defined(CONFIG_NETARM_EMLIN) + +/* EMLIN board: 33 MHz (exp.) */ +#define NETARM_PLL_COUNT_VAL 6 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#elif defined(CONFIG_NETARM_NET40_REV2) + +/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */ +#define NETARM_PLL_COUNT_VAL 6 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#elif defined(CONFIG_NETARM_NET40_REV4) + +/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with + NETARM_XTAL_FREQ_25MHz) 4 */ +#define NETARM_PLL_COUNT_VAL 4 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#else /* CONFIG_NETARM_NET50 */ + +/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */ +#define NETARM_PLL_COUNT_VAL 8 +#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz + +#endif + +/* #include "arm_registers.h" */ +#include <asm/arch/netarm_gen_module.h> +#include <asm/arch/netarm_mem_module.h> +#include <asm/arch/netarm_ser_module.h> +#include <asm/arch/netarm_eni_module.h> +#include <asm/arch/netarm_dma_module.h> +#include <asm/arch/netarm_eth_module.h> + +#endif + diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h new file mode 100644 index 0000000000..fceabd173e --- /dev/null +++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h @@ -0,0 +1,347 @@ +/* + * linux/include/asm-arm/arch-netarm/netarm_ser_module.h + * + * Copyright (C) 2000 NETsilicon, Inc. + * Copyright (C) 2000 Red Hat, Inc. + * + * This software is copyrighted by Red Hat. LICENSEE agrees that + * it will not delete this copyright notice, trademarks or protective + * notices from any copy made by LICENSEE. + * + * This software is provided "AS-IS" and any express or implied + * warranties or conditions, including but not limited to any + * implied warranties of merchantability and fitness for a particular + * purpose regarding this software. In no event shall Red Hat + * be liable for any indirect, consequential, or incidental damages, + * loss of profits or revenue, loss of use or data, or interruption + * of business, whether the alleged damages are labeled in contract, + * tort, or indemnity. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * author(s) : Joe deBlaquiere + * Clark Williams + */ + +#ifndef __NETARM_SER_MODULE_REGISTERS_H +#define __NETARM_SER_MODULE_REGISTERS_H + +#ifndef __ASSEMBLER__ + +/* (--sub)#include "types.h" */ + +/* serial channel control structure */ +typedef struct { + u32 ctrl_a; + u32 ctrl_b; + u32 status_a; + u32 bitrate; + u32 fifo; + u32 rx_buf_timer; + u32 rx_char_timer; + u32 rx_match; + u32 rx_match_mask; + u32 ctrl_c; + u32 status_b; + u32 status_c; + u32 fifo_last; + u32 unused[3]; +} netarm_serial_channel_t; + +#endif + +/* SER unit register offsets */ + +/* #ifdef CONFIG_ARCH_NETARM */ +#define NETARM_SER_MODULE_BASE (0xFFD00000) +/* #else */ +/* extern serial_channel_t netarm_dummy_registers[]; */ +/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */ +/* #ifndef NETARM_XTAL_FREQ */ +/* #define NETARM_XTAL_FREQ 18432000 */ +/* #endif */ +/* #endif */ + +/* calculate the sysclk value from the pll setting */ +#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \ + ( NETARM_PLL_COUNT_VAL + 3 )) + +#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c])) + +#define NETARM_SER_CH1_CTRL_A (0x00) +#define NETARM_SER_CH1_CTRL_B (0x04) +#define NETARM_SER_CH1_STATUS_A (0x08) +#define NETARM_SER_CH1_BITRATE (0x0C) +#define NETARM_SER_CH1_FIFO (0x10) +#define NETARM_SER_CH1_RX_BUF_TMR (0x14) +#define NETARM_SER_CH1_RX_CHAR_TMR (0x18) +#define NETARM_SER_CH1_RX_MATCH (0x1c) +#define NETARM_SER_CH1_RX_MATCH_MASK (0x20) +#define NETARM_SER_CH1_CTRL_C (0x24) +#define NETARM_SER_CH1_STATUS_B (0x28) +#define NETARM_SER_CH1_STATUS_C (0x2c) +#define NETARM_SER_CH1_FIFO_LAST (0x30) + +#define NETARM_SER_CH2_CTRL_A (0x40) +#define NETARM_SER_CH2_CTRL_B (0x44) +#define NETARM_SER_CH2_STATUS_A (0x48) +#define NETARM_SER_CH2_BITRATE (0x4C) +#define NETARM_SER_CH2_FIFO (0x50) +#define NETARM_SER_CH2_RX_BUF_TMR (0x54) +#define NETARM_SER_CH2_RX_CHAR_TMR (0x58) +#define NETARM_SER_CH2_RX_MATCH (0x5c) +#define NETARM_SER_CH2_RX_MATCH_MASK (0x60) +#define NETARM_SER_CH2_CTRL_C (0x64) +#define NETARM_SER_CH2_STATUS_B (0x68) +#define NETARM_SER_CH2_STATUS_C (0x6c) +#define NETARM_SER_CH2_FIFO_LAST (0x70) + +/* select bitfield defintions */ + +/* Control Register A */ + +#define NETARM_SER_CTLA_ENABLE (0x80000000) +#define NETARM_SER_CTLA_BRK (0x40000000) + +#define NETARM_SER_CTLA_STICKP (0x20000000) + +#define NETARM_SER_CTLA_P_EVEN (0x18000000) +#define NETARM_SER_CTLA_P_ODD (0x08000000) +#define NETARM_SER_CTLA_P_NONE (0x00000000) + +/* if you read the errata, you will find that the STOP bits don't work right */ +#define NETARM_SER_CTLA_2STOP (0x00000000) +#define NETARM_SER_CTLA_3STOP (0x04000000) + +#define NETARM_SER_CTLA_5BITS (0x00000000) +#define NETARM_SER_CTLA_6BITS (0x01000000) +#define NETARM_SER_CTLA_7BITS (0x02000000) +#define NETARM_SER_CTLA_8BITS (0x03000000) + +#define NETARM_SER_CTLA_CTSTX (0x00800000) +#define NETARM_SER_CTLA_RTSRX (0x00400000) + +#define NETARM_SER_CTLA_LOOP_REM (0x00200000) +#define NETARM_SER_CTLA_LOOP_LOC (0x00100000) + +#define NETARM_SER_CTLA_GPIO2 (0x00080000) +#define NETARM_SER_CTLA_GPIO1 (0x00040000) + +#define NETARM_SER_CTLA_DTR_EN (0x00020000) +#define NETARM_SER_CTLA_RTS_EN (0x00010000) + +#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000) +#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000) +#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000) +#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000) +#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800) +#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400) +#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200) +#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100) +#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080) +#define NETARM_SER_CTLA_IE_RX_RI (0x00000040) +#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020) + +#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \ + |NETARM_SER_CTLA_IE_RX_FRMERR \ + |NETARM_SER_CTLA_IE_RX_PARERR \ + |NETARM_SER_CTLA_IE_RX_OVERRUN \ + |NETARM_SER_CTLA_IE_RX_RDY \ + |NETARM_SER_CTLA_IE_RX_HALF \ + |NETARM_SER_CTLA_IE_RX_FULL \ + |NETARM_SER_CTLA_IE_RX_DMAEN \ + |NETARM_SER_CTLA_IE_RX_DCD \ + |NETARM_SER_CTLA_IE_RX_RI \ + |NETARM_SER_CTLA_IE_RX_DSR) + +#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010) +#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008) +#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004) +#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002) +#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001) + +#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \ + |NETARM_SER_CTLA_IE_TX_EMPTY \ + |NETARM_SER_CTLA_IE_TX_HALF \ + |NETARM_SER_CTLA_IE_TX_FULL \ + |NETARM_SER_CTLA_IE_TX_DMAEN) + +/* Control Register B */ + +#define NETARM_SER_CTLB_MATCH1_EN (0x80000000) +#define NETARM_SER_CTLB_MATCH2_EN (0x40000000) +#define NETARM_SER_CTLB_MATCH3_EN (0x20000000) +#define NETARM_SER_CTLB_MATCH4_EN (0x10000000) + +#define NETARM_SER_CTLB_RBGT_EN (0x08000000) +#define NETARM_SER_CTLB_RCGT_EN (0x04000000) + +#define NETARM_SER_CTLB_UART_MODE (0x00000000) +#define NETARM_SER_CTLB_HDLC_MODE (0x00100000) +#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000) +#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000) + +#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000) + +#define NETARM_SER_CTLB_MAM1 (0x00040000) +#define NETARM_SER_CTLB_MAM2 (0x00020000) + +/* Status Register A */ + +#define NETARM_SER_STATA_MATCH1 (0x80000000) +#define NETARM_SER_STATA_MATCH2 (0x40000000) +#define NETARM_SER_STATA_MATCH3 (0x20000000) +#define NETARM_SER_STATA_MATCH4 (0x10000000) + +#define NETARM_SER_STATA_BGAP (0x80000000) +#define NETARM_SER_STATA_CGAP (0x40000000) + +#define NETARM_SER_STATA_RX_1B (0x00100000) +#define NETARM_SER_STATA_RX_2B (0x00200000) +#define NETARM_SER_STATA_RX_3B (0x00300000) +#define NETARM_SER_STATA_RX_4B (0x00000000) + +/* downshifted values */ + +#define NETARM_SER_STATA_RXFDB_1BYTES (0x001) +#define NETARM_SER_STATA_RXFDB_2BYTES (0x002) +#define NETARM_SER_STATA_RXFDB_3BYTES (0x003) +#define NETARM_SER_STATA_RXFDB_4BYTES (0x000) + +#define NETARM_SER_STATA_RXFDB_MASK (0x00300000) +#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \ + >> 20) + +#define NETARM_SER_STATA_DCD (0x00080000) +#define NETARM_SER_STATA_RI (0x00040000) +#define NETARM_SER_STATA_DSR (0x00020000) +#define NETARM_SER_STATA_CTS (0x00010000) + +#define NETARM_SER_STATA_RX_BRK (0x00008000) +#define NETARM_SER_STATA_RX_FRMERR (0x00004000) +#define NETARM_SER_STATA_RX_PARERR (0x00002000) +#define NETARM_SER_STATA_RX_OVERRUN (0x00001000) +#define NETARM_SER_STATA_RX_RDY (0x00000800) +#define NETARM_SER_STATA_RX_HALF (0x00000400) +#define NETARM_SER_STATA_RX_CLOSED (0x00000200) +#define NETARM_SER_STATA_RX_FULL (0x00000100) +#define NETARM_SER_STATA_RX_DCD (0x00000080) +#define NETARM_SER_STATA_RX_RI (0x00000040) +#define NETARM_SER_STATA_RX_DSR (0x00000020) + +#define NETARM_SER_STATA_TX_CTS (0x00000010) +#define NETARM_SER_STATA_TX_RDY (0x00000008) +#define NETARM_SER_STATA_TX_HALF (0x00000004) +#define NETARM_SER_STATA_TX_FULL (0x00000002) +#define NETARM_SER_STATA_TX_DMAEN (0x00000001) + +/* you have to clear all receive signals to get the fifo to move forward */ +#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \ + NETARM_SER_STATA_RX_FRMERR | \ + NETARM_SER_STATA_RX_PARERR | \ + NETARM_SER_STATA_RX_OVERRUN | \ + NETARM_SER_STATA_RX_HALF | \ + NETARM_SER_STATA_RX_CLOSED | \ + NETARM_SER_STATA_RX_FULL | \ + NETARM_SER_STATA_RX_DCD | \ + NETARM_SER_STATA_RX_RI | \ + NETARM_SER_STATA_RX_DSR | \ + NETARM_SER_STATA_TX_CTS ) + +/* Bit Rate Registers */ + +#define NETARM_SER_BR_EN (0x80000000) +#define NETARM_SER_BR_TMODE (0x40000000) + +#define NETARM_SER_BR_RX_CLK_INT (0x00000000) +#define NETARM_SER_BR_RX_CLK_EXT (0x20000000) +#define NETARM_SER_BR_TX_CLK_INT (0x00000000) +#define NETARM_SER_BR_TX_CLK_EXT (0x10000000) + +#define NETARM_SER_BR_RX_CLK_DRV (0x08000000) +#define NETARM_SER_BR_TX_CLK_DRV (0x04000000) + +#define NETARM_SER_BR_CLK_EXT_5 (0x00000000) +#define NETARM_SER_BR_CLK_SYSTEM (0x01000000) +#define NETARM_SER_BR_CLK_OUT1A (0x02000000) +#define NETARM_SER_BR_CLK_OUT2A (0x03000000) + +#define NETARM_SER_BR_TX_CLK_INV (0x00800000) +#define NETARM_SER_BR_RX_CLK_INV (0x00400000) + +/* complete settings assuming system clock input is 18MHz */ + +#define NETARM_SER_BR_MASK (0x000007FF) + +/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */ +/* from section 7.5.4 of HW Ref Guide */ + +/* #ifdef CONFIG_NETARM_PLL_BYPASS */ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_EXT_5 | \ + ( ( ( ( NETARM_XTAL_FREQ / \ + ( x * 10 ) ) - 1 ) / 16 ) & \ + NETARM_SER_BR_MASK ) ) +/* +#else +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_SYSTEM | \ + ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ + ( x * 2 ) ) - 1 ) / 16 ) & \ + NETARM_SER_BR_MASK ) ) +#endif +*/ + +/* Receive Buffer Gap Timer */ + +#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000) +#define NETARM_SER_RX_GAP_MASK (0x00003FFF) + +/* rx gap is a function of bit rate x */ + +/* #ifdef CONFIG_NETARM_PLL_BYPASS */ +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ + ( x * 5 * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +/* +#else +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ + ( x * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#endif +*/ + +#if 0 +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ + ( x * 5 * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ + ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ + ( x * 512 ) ) - 1 ) & \ + NETARM_SER_RX_GAP_MASK ) ) +#endif + +#define MIN_BAUD_RATE 600 +#define MAX_BAUD_RATE 115200 + +/* the default BAUD rate for the BOOTLOADER, there is a separate */ +/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */ +#define DEFAULT_BAUD_RATE 9600 +#define NETARM_SER_FIFO_SIZE 32 +#define MIN_GAP 0 + +#endif diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index ebea56b844..af5654cd67 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -85,6 +85,7 @@ #define CFG_CMD_MMC 0x0008000000000000U /* MMC support */ #define CFG_CMD_FAT 0x0010000000000000U /* FAT support */ #define CFG_CMD_IMLS 0x0020000000000000U /* List all found images */ +#define CFG_CMD_ITEST 0x0040000000000000U /* Integer (and string) test */ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFU /* ALL commands */ diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h new file mode 100644 index 0000000000..fd1b47c4fc --- /dev/null +++ b/include/configs/modnet50.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2004 + * IMMS, gGmbH <www.imms.de> + * Thomas Elste <info@elste.org> + * + * Configuation settings for ModNET50 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start u-boot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#define CONFIG_NETARM /* it's a Netsiclicon NET+ARM */ +#undef CONFIG_NETARM_NET40_REV2 /* it's a Net+40 Rev. 2 */ +#undef CONFIG_NETARM_NET40_REV4 /* it's a Net+40 Rev. 4 */ +#define CONFIG_NETARM_NET50 /* it's a Net+50 */ + +#define CONFIG_MODNET50 1 /* on an ModNET50 Board */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_NETARMETH 1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.30.2 +#define CONFIG_SERVERIP 192.168.30.122 +#define CFG_ETH_PHY_ADDR 0x100 +#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */ + +/*#define CONFIG_BOOTDELAY 10*/ +/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */ +#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000" +#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "modnet50 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00500000 /* default load address */ + +#define CFG_HZ 900 /* decrementer freq: 2 kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +#define PHYS_SDRAM_2 0x01000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */ + +#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */ +#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip only, 16bit access) */ + +#define PHYS_FLASH_2 0x10200001 +#define PHYS_FLASH_2_SIZE 0x00200000 + +#define CONFIG_NETARM_EEPROM +/* #ifdef CONFIG_NETARM_EEPROM */ +#define PHYS_NVRAM_1 0x20000000 /* EEPROM Bank #1 */ +#define PHYS_NVRAM_SIZE 0x00002000 /* 8 KB */ +/* #endif */ + +#define PHYS_EXT_1 0x30000000 /* Extensions Bank #1 */ +#define PHYS_EXT_SIZE 0x01000000 /* 32 MB memory mapped I/O */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ +#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* environment settings */ +#define CFG_ENV_IS_IN_FLASH +#undef CFG_ENV_IS_NOWHERE + +#define CFG_ENV_ADDR 0x1001C000 /* environment start address */ +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* max size for environment */ + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 8 +#define CFG_JFFS2_NUM_BANKS 2 + +#endif /* __CONFIG_H */ diff --git a/include/fat.h b/include/fat.h index 8fffb420b6..13910f984a 100644 --- a/include/fat.h +++ b/include/fat.h @@ -67,6 +67,10 @@ #define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */ #define aRING 0x05 /* Used to represent 'å' in name[0] */ +/* Indicates that the entry is the last long entry in a set of long + * dir entries + */ +#define LAST_LONG_ENTRY_MASK 0x40 /* Flags telling whether we should read a file or list a directory */ #define LS_NO 0 |