diff options
1392 files changed, 24053 insertions, 12682 deletions
@@ -145,6 +145,7 @@ menu "Boot images" config FIT bool "Support Flattened Image Tree" select MD5 + select SHA1 help This option allows you to boot the new uImage structure, Flattened Image Tree. FIT is formally a FDT, which can include @@ -157,6 +158,20 @@ config FIT if FIT +config FIT_ENABLE_SHA256_SUPPORT + bool "Support SHA256 checksum of FIT image contents" + select SHA256 + default y + help + Enable this to support SHA256 checksum of FIT image contents. A + SHA256 checksum is a 256-bit (32-byte) hash value used to check that + the image contents have not been corrupted. SHA256 is recommended + for use in secure applications since (as at 2016) there is no known + feasible attack that could produce a 'collision' with differing + input data. Use this for the highest security. Note that only the + SHA256 variant is supported: SHA512 and others are not currently + supported in U-Boot. + config FIT_SIGNATURE bool "Enable signature verification of FIT uImages" depends on DM @@ -205,18 +220,22 @@ config FIT_IMAGE_POST_PROCESS injected into the FIT creation (i.e. the blobs would have been pre- processed before being added to the FIT image). +if SPL + config SPL_FIT bool "Support Flattened Image Tree within SPL" depends on SPL + select SPL_OF_LIBFDT config SPL_FIT_SIGNATURE bool "Enable signature verification of FIT firmware within SPL" - depends on SPL_FIT depends on SPL_DM + select SPL_FIT select SPL_RSA config SPL_LOAD_FIT bool "Enable SPL loading U-Boot as a FIT" + select SPL_FIT help Normally with the SPL framework a legacy image is generated as part of the build. This contains U-Boot along with information as to @@ -239,6 +258,26 @@ config SPL_FIT_IMAGE_POST_PROCESS injected into the FIT creation (i.e. the blobs would have been pre- processed before being added to the FIT image). +config SPL_FIT_SOURCE + string ".its source file for U-Boot FIT image" + depends on SPL_FIT + help + Specifies a (platform specific) FIT source file to generate the + U-Boot FIT image. This could specify further image to load and/or + execute. + +config SPL_FIT_GENERATOR + string ".its file generator script for U-Boot FIT image" + depends on SPL_FIT + default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI + help + Specifies a (platform specific) script file to generate the FIT + source file used to build the U-Boot FIT image file. This gets + passed a list of supported device tree file stub names to + include in the generated image. + +endif # SPL + endif # FIT config OF_BOARD_SETUP @@ -653,7 +653,6 @@ libs-y += drivers/ libs-y += drivers/dma/ libs-y += drivers/gpio/ libs-y += drivers/i2c/ -libs-y += drivers/mmc/ libs-y += drivers/mtd/ libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/ libs-y += drivers/mtd/onenand/ @@ -834,6 +833,10 @@ quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) +quiet_cmd_mkfitimage = MKIMAGE $@ +cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \ + $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + quiet_cmd_cat = CAT $@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@ @@ -953,6 +956,19 @@ quiet_cmd_cpp_cfg = CFG $@ cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ -DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $< +# Boards with more complex image requirments can provide an .its source file +# or a generator script +ifneq ($(CONFIG_SPL_FIT_SOURCE),"") +U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE)) +else +ifneq ($(CONFIG_SPL_FIT_GENERATOR),"") +U_BOOT_ITS := u-boot.its +$(U_BOOT_ITS): FORCE + $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \ + $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@ +endif +endif + ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ @@ -985,6 +1001,9 @@ u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE $(call if_changed,mkimage) +u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE + $(call if_changed,mkfitimage) + u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) @@ -292,7 +292,7 @@ board_init_r(): - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and CONFIG_SPL_STACK_R_ADDR points into SDRAM - preloader_console_init() can be called here - typically this is - done by defining CONFIG_SPL_BOARD_INIT and then supplying a + done by selecting CONFIG_SPL_BOARD_INIT and then supplying a spl_board_init() function containing this call - loads U-Boot or (in falcon mode) Linux @@ -830,18 +830,9 @@ The following options need to be configured: CONFIG_CMD_CRC32 * crc32 CONFIG_CMD_DHCP * DHCP support CONFIG_CMD_DIAG * Diagnostics - CONFIG_CMD_DS4510 * ds4510 I2C gpio commands - CONFIG_CMD_DS4510_INFO * ds4510 I2C info command - CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd - CONFIG_CMD_DS4510_RST * ds4510 I2C rst command - CONFIG_CMD_DTT * Digital Therm and Thermostat CONFIG_CMD_ECHO echo arguments CONFIG_CMD_EDITENV edit env variable - CONFIG_CMD_EEPROM * EEPROM read/write support - CONFIG_CMD_EEPROM_LAYOUT* EEPROM layout aware commands CONFIG_CMD_ELF * bootelf, bootvx - CONFIG_CMD_ENV_CALLBACK * display details about env callbacks - CONFIG_CMD_ENV_FLAGS * display details about env flags CONFIG_CMD_ENV_EXISTS * check existence of env variable CONFIG_CMD_EXPORTENV * export the environment CONFIG_CMD_EXT2 * ext2 command support @@ -850,28 +841,18 @@ The following options need to be configured: that work for multiple fs types CONFIG_CMD_FS_UUID * Look up a filesystem UUID CONFIG_CMD_SAVEENV saveenv - CONFIG_CMD_FDC * Floppy Disk Support CONFIG_CMD_FAT * FAT command support CONFIG_CMD_FLASH flinfo, erase, protect CONFIG_CMD_FPGA FPGA device initialization support - CONFIG_CMD_FUSE * Device fuse support - CONFIG_CMD_GETTIME * Get time since boot CONFIG_CMD_GO * the 'go' command (exec code) CONFIG_CMD_GREPENV * search environment - CONFIG_CMD_HASH * calculate hash / digest CONFIG_CMD_I2C * I2C serial bus support - CONFIG_CMD_IDE * IDE harddisk support CONFIG_CMD_IMI iminfo CONFIG_CMD_IMLS List all images found in NOR flash CONFIG_CMD_IMLS_NAND * List all images found in NAND flash - CONFIG_CMD_IMMAP * IMMR dump support - CONFIG_CMD_IOTRACE * I/O tracing for debugging CONFIG_CMD_IMPORTENV * import an environment CONFIG_CMD_INI * import data from an ini file into the env - CONFIG_CMD_IRQ * irqinfo CONFIG_CMD_ITEST Integer/string test of 2 values - CONFIG_CMD_JFFS2 * JFFS2 Support - CONFIG_CMD_KGDB * kgdb CONFIG_CMD_LDRINFO * ldrinfo (display Blackfin loader) CONFIG_CMD_LINK_LOCAL * link-local IP address auto-configuration (169.254.*.*) @@ -1095,7 +1076,7 @@ The following options need to be configured: disk/part_efi.c CONFIG_MTD_PARTITIONS Memory Technology Device partition table. - If IDE or SCSI support is enabled (CONFIG_CMD_IDE or + If IDE or SCSI support is enabled (CONFIG_IDE or CONFIG_SCSI) you must configure support for at least one non-MTD partition type as well. @@ -1742,29 +1723,6 @@ The following options need to be configured: the malloc area (as defined by CONFIG_SYS_MALLOC_LEN) should be at least 4MB. - CONFIG_LZMA - - If this option is set, support for lzma compressed - images is included. - - Note: The LZMA algorithm adds between 2 and 4KB of code and it - requires an amount of dynamic memory that is given by the - formula: - - (1846 + 768 << (lc + lp)) * sizeof(uint16) - - Where lc and lp stand for, respectively, Literal context bits - and Literal pos bits. - - This value is upper-bounded by 14MB in the worst case. Anyway, - for a ~4MB large kernel image, we have lc=3 and lp=0 for a - total amount of (1846 + 768 << (3 + 0)) * 2 = ~41KB... that is - a very small buffer. - - Use the lzmainfo tool to determinate the lc and lp values and - then calculate the amount of needed dynamic memory (ensuring - the appropriate CONFIG_SYS_MALLOC_LEN value). - CONFIG_LZO If this option is set, support for LZO compressed images @@ -2204,52 +2162,7 @@ The following options need to be configured: If you do not have i2c muxes on your board, omit this define. -- Legacy I2C Support: CONFIG_HARD_I2C - - NOTE: It is intended to move drivers to CONFIG_SYS_I2C which - provides the following compelling advantages: - - - more than one i2c adapter is usable - - approved multibus support - - better i2c mux support - - ** Please consider updating your I2C driver now. ** - - These enable legacy I2C serial bus commands. Defining - CONFIG_HARD_I2C will include the appropriate I2C driver - for the selected CPU. - - This will allow you to use i2c commands at the u-boot - command line (as long as you set CONFIG_CMD_I2C in - CONFIG_COMMANDS) and communicate with i2c based realtime - clock chips. See common/cmd_i2c.c for a description of the - command line interface. - - CONFIG_HARD_I2C selects a hardware I2C controller. - - There are several other quantities that must also be - defined when you define CONFIG_HARD_I2C. - - In both cases you will need to define CONFIG_SYS_I2C_SPEED - to be the frequency (in Hz) at which you wish your i2c bus - to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie - the CPU's i2c node address). - - Now, the u-boot i2c code for the mpc8xx - (arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node - and so its address should therefore be cleared to 0 (See, - eg, MPC823e User's Manual p.16-473). So, set - CONFIG_SYS_I2C_SLAVE to 0. - - CONFIG_SYS_I2C_INIT_MPC5XXX - - When a board is reset during an i2c bus transfer - chips might think that the current transfer is still - in progress. Reset the slave devices by sending start - commands until the slave device responds. - - That's all that's required for CONFIG_HARD_I2C. - +- Legacy I2C Support: If you use the software i2c interface (CONFIG_SYS_I2C_SOFT) then the following macros need to be defined (examples are from include/configs/lwmon.h): @@ -2338,23 +2251,6 @@ The following options need to be configured: custom i2c_init_board() routine in boards/xxx/board.c is run early in the boot sequence. - CONFIG_SYS_I2C_BOARD_LATE_INIT - - An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is - defined a custom i2c_board_late_init() routine in - boards/xxx/board.c is run AFTER the operations in i2c_init() - is completed. This callpoint can be used to unreset i2c bus - using CPU i2c controller register accesses for CPUs whose i2c - controller provide such a method. It is called at the end of - i2c_init() to allow i2c_init operations to setup the i2c bus - controller on the CPU (e.g. setting bus speed & slave address). - - CONFIG_I2CFAST (PPC405GP|PPC405EP only) - - This option enables configuration of bi_iic_fast[] flags - in u-boot bd_info structure based on u-boot environment - variable "i2cfast". (see also i2cfast) - CONFIG_I2C_MULTI_BUS This option allows the use of multiple I2C buses, each of which @@ -2390,17 +2286,6 @@ The following options need to be configured: If defined, then this indicates the I2C bus number for the RTC. If not defined, then U-Boot assumes that RTC is on I2C bus 0. - CONFIG_SYS_DTT_BUS_NUM - - If defined, then this indicates the I2C bus number for the DTT. - If not defined, then U-Boot assumes that DTT is on I2C bus 0. - - CONFIG_SYS_I2C_DTT_ADDR: - - If defined, specifies the I2C address of the DTT device. - If not defined, then U-Boot uses predefined value for - specified DTT device. - CONFIG_SOFT_I2C_READ_REPEATED_START defining this will force the i2c_read() function in @@ -2467,19 +2352,6 @@ The following options need to be configured: Specify the number of FPGA devices to support. - CONFIG_CMD_FPGA_LOADMK - - Enable support for fpga loadmk command - - CONFIG_CMD_FPGA_LOADP - - Enable support for fpga loadp command - load partial bitstream - - CONFIG_CMD_FPGA_LOADBP - - Enable support for fpga loadbp command - load partial bitstream - (Xilinx only) - CONFIG_SYS_FPGA_PROG_FEEDBACK Enable printing of hash marks during FPGA configuration. @@ -2808,37 +2680,14 @@ The following options need to be configured: but sometimes that is not allowed. - Hashing support: - CONFIG_CMD_HASH - - This enables a generic 'hash' command which can produce - hashes / digests from a few algorithms (e.g. SHA1, SHA256). - CONFIG_HASH_VERIFY Enable the hash verify command (hash -v). This adds to code size a little. - CONFIG_SHA1 - This option enables support of hashing using SHA1 - algorithm. The hash is calculated in software. - CONFIG_SHA256 - This option enables support of hashing using - SHA256 algorithm. The hash is calculated in software. - CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration - for SHA1/SHA256 hashing. - This affects the 'hash' command and also the - hash_lookup_algo() function. - CONFIG_SHA_PROG_HW_ACCEL - This option enables - hardware-acceleration for SHA1/SHA256 progressive hashing. - Data can be streamed in a block at a time and the hashing - is performed in hardware. - Note: There is also a sha1sum command, which should perhaps be deprecated in favour of 'hash sha1'. -- Freescale i.MX specific commands: - CONFIG_CMD_HDMIDETECT - This enables 'hdmidet' command which returns true if an - HDMI monitor is detected. This command is i.MX 6 specific. - - bootcount support: CONFIG_BOOTCOUNT_LIMIT @@ -3035,15 +2884,6 @@ FIT uImage format: This define is introduced, as the legacy image format is enabled per default for backward compatibility. -- FIT image support: - CONFIG_FIT_DISABLE_SHA256 - Supporting SHA256 hashes has quite an impact on binary size. - For constrained systems sha256 hash support can be disabled - with this option. - - TODO(sjg@chromium.org): Adjust this option to be positive, - and move it to Kconfig - - Standalone program support: CONFIG_STANDALONE_LOAD_ADDR @@ -3708,11 +3548,6 @@ Configuration Settings: If defined, don't allow the -f switch to env set override variable access flags. -- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only) - This is set by OMAP boards for the max time that reset should - be asserted. See doc/README.omap-reset-time for details on how - the value can be calculated on a given board. - - CONFIG_USE_STDINT If stdint.h is available with your toolchain you can define this option to enable it. You can provide option 'USE_STDINT=1' when diff --git a/api/api_storage.c b/api/api_storage.c index a5357bc9cf..f858f09f1a 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -46,7 +46,7 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, }; void dev_stor_init(void) { -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE; specs[ENUM_IDE].enum_started = 0; specs[ENUM_IDE].enum_ended = 0; diff --git a/arch/Kconfig b/arch/Kconfig index 160accdbcb..02e887ac86 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -34,6 +34,7 @@ config M68K config MICROBLAZE bool "MicroBlaze architecture" select SUPPORT_OF_CONTROL + imply CMD_IRQ config MIPS bool "MIPS architecture" @@ -43,6 +44,7 @@ config MIPS config NDS32 bool "NDS32 architecture" + select SUPPORT_OF_CONTROL config NIOS2 bool "Nios II architecture" @@ -68,6 +70,12 @@ config SANDBOX select DM_SPI select DM_GPIO select DM_MMC + imply CMD_GETTIME + imply CMD_HASH + imply CMD_IO + imply CMD_IOTRACE + imply LZMA + imply CMD_LZMADEC config SH bool "SuperH architecture" @@ -84,6 +92,12 @@ config X86 select DM_GPIO select DM_SPI select DM_SPI_FLASH + select USB_EHCI_HCD + select DM_MMC if MMC + imply CMD_FPGA_LOADMK + imply CMD_GETTIME + imply CMD_IO + imply CMD_IRQ config XTENSA bool "Xtensa architecture" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2db7e3cb3b..91f50b0637 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -281,6 +281,7 @@ choice config ARCH_AT91 bool "Atmel AT91" + select SPL_BOARD_INIT if SPL config TARGET_EDB93XX bool "Support edb93xx" @@ -502,6 +503,7 @@ config TARGET_BCM28155_AP config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7 + imply CMD_HASH config TARGET_BCMNSP bool "Support bcmnsp" @@ -553,6 +555,7 @@ config ARCH_KEYSTONE config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL imply FIT @@ -654,7 +657,7 @@ config ARCH_SUNXI imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT if GENERIC_MMC + imply SPL_MMC_SUPPORT if MMC imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT @@ -674,6 +677,7 @@ config ARCH_ZYNQ select CPU_V7 select SUPPORT_SPL select OF_CONTROL + select SPL_BOARD_INIT if SPL select SPL_OF_CONTROL if SPL select DM select DM_ETH @@ -701,6 +705,7 @@ config ARCH_ZYNQMP select DM_SERIAL select SUPPORT_SPL select CLK + select SPL_BOARD_INIT if SPL select SPL_CLK select DM_USB if USB @@ -957,6 +962,7 @@ config ARCH_UNIPHIER select OF_CONTROL select OF_LIBFDT select PINCTRL + select SPL_BOARD_INIT if SPL select SPL_DM if SPL select SPL_LIBCOMMON_SUPPORT if SPL select SPL_LIBGENERIC_SUPPORT if SPL diff --git a/arch/arm/cpu/arm926ejs/omap/Makefile b/arch/arm/cpu/arm926ejs/omap/Makefile deleted file mode 100644 index add923276c..0000000000 --- a/arch/arm/cpu/arm926ejs/omap/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = timer.o -obj-$(CONFIG_DISPLAY_CPUINFO) += cpuinfo.o -obj-y += reset.o diff --git a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c b/arch/arm/cpu/arm926ejs/omap/cpuinfo.c deleted file mode 100644 index 587d99a2bb..0000000000 --- a/arch/arm/cpu/arm926ejs/omap/cpuinfo.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * OMAP1 CPU identification code - * - * Copyright (C) 2004 Nokia Corporation - * Written by Tony Lindgren <tony@atomide.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <common.h> -#include <command.h> -#include <linux/compiler.h> - -#if defined(CONFIG_OMAP) - -#define omap_readw(x) *(volatile unsigned short *)(x) -#define omap_readl(x) *(volatile unsigned long *)(x) - -#define OMAP_DIE_ID_0 0xfffe1800 -#define OMAP_DIE_ID_1 0xfffe1804 -#define OMAP_PRODUCTION_ID_0 0xfffe2000 -#define OMAP_PRODUCTION_ID_1 0xfffe2004 -#define OMAP32_ID_0 0xfffed400 -#define OMAP32_ID_1 0xfffed404 - -struct omap_id { - u16 jtag_id; /* Used to determine OMAP type */ - u8 die_rev; /* Processor revision */ - u32 omap_id; /* OMAP revision */ - u32 type; /* Cpu id bits [31:08], cpu class bits [07:00] */ -}; - -/* Register values to detect the OMAP version */ -static struct omap_id omap_ids[] = { - { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, - { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, - { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, - { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, - { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, - { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, - { .jtag_id = 0xb576, .die_rev = 0x3, .omap_id = 0x03320100, .type = 0x16100c00}, - { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320200, .type = 0x16100d00}, - { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, - { .jtag_id = 0xb613, .die_rev = 0x0, .omap_id = 0x03320300, .type = 0x1610ef00}, - { .jtag_id = 0xb576, .die_rev = 0x1, .omap_id = 0x03320100, .type = 0x16110000}, - { .jtag_id = 0xb58c, .die_rev = 0x2, .omap_id = 0x03320200, .type = 0x16110b00}, - { .jtag_id = 0xb58c, .die_rev = 0x3, .omap_id = 0x03320200, .type = 0x16110c00}, - { .jtag_id = 0xb65f, .die_rev = 0x0, .omap_id = 0x03320400, .type = 0x16212300}, - { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320400, .type = 0x16212300}, - { .jtag_id = 0xb65f, .die_rev = 0x1, .omap_id = 0x03320500, .type = 0x16212300}, - { .jtag_id = 0xb5f7, .die_rev = 0x0, .omap_id = 0x03330000, .type = 0x17100000}, - { .jtag_id = 0xb5f7, .die_rev = 0x1, .omap_id = 0x03330100, .type = 0x17100000}, - { .jtag_id = 0xb5f7, .die_rev = 0x2, .omap_id = 0x03330100, .type = 0x17100000}, -}; - -/* - * Get OMAP type from PROD_ID. - * 1710 has the PROD_ID in bits 15:00, not in 16:01 as documented in TRM. - * 1510 PROD_ID is empty, and 1610 PROD_ID does not make sense. - * Undocumented register in TEST BLOCK is used as fallback; This seems to - * work on 1510, 1610 & 1710. The official way hopefully will work in future - * processors. - */ -static u16 omap_get_jtag_id(void) -{ - u32 prod_id, omap_id; - - prod_id = omap_readl(OMAP_PRODUCTION_ID_1); - omap_id = omap_readl(OMAP32_ID_1); - - /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */ - if (((prod_id >> 20) == 0) || (prod_id == omap_id)) - prod_id = 0; - else - prod_id &= 0xffff; - - if (prod_id) - return prod_id; - - /* Use OMAP32_ID_1 as fallback */ - prod_id = ((omap_id >> 12) & 0xffff); - - return prod_id; -} - -/* - * Get OMAP revision from DIE_REV. - * Early 1710 processors may have broken OMAP_DIE_ID, it contains PROD_ID. - * Undocumented register in the TEST BLOCK is used as fallback. - * REVISIT: This does not seem to work on 1510 - */ -static u8 omap_get_die_rev(void) -{ - u32 die_rev; - - die_rev = omap_readl(OMAP_DIE_ID_1); - - /* Check for broken OMAP_DIE_ID on early 1710 */ - if (((die_rev >> 12) & 0xffff) == omap_get_jtag_id()) - die_rev = 0; - - die_rev = (die_rev >> 17) & 0xf; - if (die_rev) - return die_rev; - - die_rev = (omap_readl(OMAP32_ID_1) >> 28) & 0xf; - - return die_rev; -} - -static unsigned long dpll1(void) -{ - unsigned short pll_ctl_val = omap_readw(DPLL_CTL_REG); - unsigned long rate; - - rate = CONFIG_SYS_CLK_FREQ; /* Base xtal rate */ - if (pll_ctl_val & 0x10) { - /* PLL enabled, apply multiplier and divisor */ - if (pll_ctl_val & 0xf80) - rate *= (pll_ctl_val & 0xf80) >> 7; - rate /= ((pll_ctl_val & 0x60) >> 5) + 1; - } else { - /* PLL disabled, apply bypass divisor */ - switch (pll_ctl_val & 0xc) { - case 0: - break; - case 0x4: - rate /= 2; - break; - default: - rate /= 4; - break; - } - } - - return rate; -} - -static unsigned long armcore(void) -{ - unsigned short arm_ckctl = omap_readw(ARM_CKCTL); - - return (dpll1() >> ((arm_ckctl & 0x0030) >> 4)); -} - -int print_cpuinfo (void) -{ - int i; - u16 jtag_id; - u8 die_rev; - u32 omap_id; - u8 cpu_type; - __maybe_unused u32 system_serial_high; - __maybe_unused u32 system_serial_low; - u32 system_rev = 0; - - jtag_id = omap_get_jtag_id(); - die_rev = omap_get_die_rev(); - omap_id = omap_readl(OMAP32_ID_0); - -#ifdef DEBUG - printf("OMAP_DIE_ID_0: 0x%08x\n", omap_readl(OMAP_DIE_ID_0)); - printf("OMAP_DIE_ID_1: 0x%08x DIE_REV: %i\n", - omap_readl(OMAP_DIE_ID_1), - (omap_readl(OMAP_DIE_ID_1) >> 17) & 0xf); - printf("OMAP_PRODUCTION_ID_0: 0x%08x\n", omap_readl(OMAP_PRODUCTION_ID_0)); - printf("OMAP_PRODUCTION_ID_1: 0x%08x JTAG_ID: 0x%04x\n", - omap_readl(OMAP_PRODUCTION_ID_1), - omap_readl(OMAP_PRODUCTION_ID_1) & 0xffff); - printf("OMAP32_ID_0: 0x%08x\n", omap_readl(OMAP32_ID_0)); - printf("OMAP32_ID_1: 0x%08x\n", omap_readl(OMAP32_ID_1)); - printf("JTAG_ID: 0x%04x DIE_REV: %i\n", jtag_id, die_rev); -#endif - - system_serial_high = omap_readl(OMAP_DIE_ID_0); - system_serial_low = omap_readl(OMAP_DIE_ID_1); - - /* First check only the major version in a safe way */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == (omap_ids[i].jtag_id)) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Check if we can find the die revision */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == omap_ids[i].jtag_id && die_rev == omap_ids[i].die_rev) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Finally check also the omap_id */ - for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { - if (jtag_id == omap_ids[i].jtag_id - && die_rev == omap_ids[i].die_rev - && omap_id == omap_ids[i].omap_id) { - system_rev = omap_ids[i].type; - break; - } - } - - /* Add the cpu class info (7xx, 15xx, 16xx, 24xx) */ - cpu_type = system_rev >> 24; - - switch (cpu_type) { - case 0x07: - system_rev |= 0x07; - break; - case 0x03: - case 0x15: - system_rev |= 0x15; - break; - case 0x16: - case 0x17: - system_rev |= 0x16; - break; - case 0x24: - system_rev |= 0x24; - break; - default: - printf("Unknown OMAP cpu type: 0x%02x\n", cpu_type); - } - - printf("CPU: OMAP%04x", system_rev >> 16); - if ((system_rev >> 8) & 0xff) - printf("%x", (system_rev >> 8) & 0xff); -#ifdef DEBUG - printf(" revision %i handled as %02xxx id: %08x%08x", - die_rev, system_rev & 0xff, system_serial_low, system_serial_high); -#endif - printf(" at %ld.%01ld MHz (DPLL1=%ld.%01ld MHz)\n", - armcore() / 1000000, (armcore() / 100000) % 10, - dpll1() / 1000000, (dpll1() / 100000) % 10); - - return 0; -} - -#endif /* #if defined(CONFIG_OMAP) */ diff --git a/arch/arm/cpu/arm926ejs/omap/reset.S b/arch/arm/cpu/arm926ejs/omap/reset.S deleted file mode 100644 index 1c557b0d91..0000000000 --- a/arch/arm/cpu/arm926ejs/omap/reset.S +++ /dev/null @@ -1,29 +0,0 @@ -/* - * armboot - Startup Code for ARM926EJS CPU-core - * - * Copyright (c) 2003 Texas Instruments - * - * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ - * - * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> - * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> - * Copyright (c) 2003 Kshitij <kshitij@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -_loop_forever: - b _loop_forever - -rstctl1: - .word 0xfffece10 diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c deleted file mode 100644 index b9715656c8..0000000000 --- a/arch/arm/cpu/arm926ejs/omap/timer.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> - -#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) -#define TIMER_LOAD_VAL 0xffffffff - -/* macro to read the 32 bit timer */ -#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+8) \ - / (TIMER_CLOCK / CONFIG_SYS_HZ) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -int timer_init (void) -{ - int32_t val; - - /* Start the decrementer ticking down from 0xffffffff */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT); - *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; - - /* init the timestamp and lastdec value */ - reset_timer_masked(); - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - }else{ /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ - else - tmo += tmp; /* else, set advancing stamp wake up time */ - - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (lastdec >= now) { /* normal mode (non roll) */ - /* normal mode */ - timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ - } else { /* we have overflow of the count down timer */ - /* nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and cause problems. - */ - timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK / - CONFIG_SYS_HZ)) - now; - } - lastdec = now; - - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index af6dad3aa9..4fd60d480e 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -7,6 +7,7 @@ config MX6 select ARM_ERRATA_751472 if !MX6UL select ARM_ERRATA_761320 if !MX6UL select ARM_ERRATA_794072 if !MX6UL + imply CMD_FUSE config MX6D bool @@ -173,8 +174,10 @@ config TARGET_MX6QARM2 config TARGET_MX6Q_ICORE bool "Support Engicam i.Core" + select BOARD_LATE_INIT select MX6QDL select OF_CONTROL + select SPL_OF_LIBFDT select DM select DM_ETH select DM_GPIO @@ -182,12 +185,14 @@ config TARGET_MX6Q_ICORE select DM_MMC select DM_THERMAL select SUPPORT_SPL + select SPL_LOAD_FIT config TARGET_MX6Q_ICORE_RQS bool "Support Engicam i.Core RQS" select BOARD_LATE_INIT select MX6QDL select OF_CONTROL + select SPL_OF_LIBFDT select DM select DM_ETH select DM_GPIO @@ -195,6 +200,7 @@ config TARGET_MX6Q_ICORE_RQS select DM_MMC select DM_THERMAL select SUPPORT_SPL + select SPL_LOAD_FIT config TARGET_MX6QSABREAUTO bool "mx6qsabreauto" @@ -256,6 +262,7 @@ config TARGET_MX6UL_14X14_EVK config TARGET_MX6UL_GEAM bool "Support Engicam GEAM6UL" + select BOARD_LATE_INIT select MX6UL select OF_CONTROL select DM diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index 8dfb4c9646..80c129019a 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -6,10 +6,12 @@ config MX7 select CPU_V7_HAS_VIRT select CPU_V7_HAS_NONSEC select ARCH_SUPPORT_PSCI + imply CMD_FUSE default y config MX7D select ROM_UNIFIED_SECTIONS + imply CMD_FUSE bool choice diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 62d97f7e88..354468b905 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -86,12 +86,12 @@ save_boot_params_ret: 0: /* - * Enalbe SMPEN bit for coherency. + * Enable SMPEN bit for coherency. * This register is not architectural but at the moment * this bit should be set for A53/A57/A72. */ #ifdef CONFIG_ARMV8_SET_SMPEN - mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ + mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */ orr x0, x0, #0x40 msr S3_1_c15_c2_1, x0 #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 55f4ae9c6d..2b1a4e926e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -149,6 +149,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_arria10_socdk_sdmmc.dtb \ socfpga_arria5_socdk.dtb \ socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_mcvevk.dtb \ @@ -347,7 +348,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb -dtb-$(CONFIG_MX7) += imx7-colibri.dtb +dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ + imx7d-sdb.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi new file mode 100644 index 0000000000..d7b296b5c6 --- /dev/null +++ b/arch/arm/dts/am335x-evm-u-boot.dtsi @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +&mmc3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts index cbef5d5c3b..f6c21052ae 100644 --- a/arch/arm/dts/imx7-colibri.dts +++ b/arch/arm/dts/imx7-colibri.dts @@ -6,7 +6,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> -#include "imx7.dtsi" +#include "imx7d.dtsi" / { model = "Toradex Colibri iMX7S/D"; @@ -83,15 +83,15 @@ &iomuxc_lpsr { pinctrl_i2c1: i2c1-grp { fsl,pins = < - MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f - MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f >; }; pinctrl_i2c1_gpio: i2c1-gpio-grp { fsl,pins = < - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f - MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f >; }; }; diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi deleted file mode 100644 index 755cc4627b..0000000000 --- a/arch/arm/dts/imx7.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright 2016 Toradex AG - * - * SPDX-License-Identifier: GPL-2.0+ or X11 - */ -#include "imx7d-pinfunc.h" -#include "skeleton.dtsi" - -/ { - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - aips1: aips-bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30000000 0x400000>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio6: gpio@30250000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30250000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio7: gpio@30260000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30260000 0x10000>; - gpio-controller; - #gpio-cells = <2>; - }; - - iomuxc_lpsr: iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - }; - - iomuxc: iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - }; - }; - - aips3: aips-bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x400000>; - ranges; - - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - status = "disabled"; - }; - - uart5: serial@30a70000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a70000 0x10000>; - status = "disabled"; - }; - - uart6: serial@30a80000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a80000 0x10000>; - status = "disabled"; - }; - - uart7: serial@30a90000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a90000 0x10000>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h index 32d2464b41..f6f7e78f88 100644 --- a/arch/arm/dts/imx7d-pinfunc.h +++ b/arch/arm/dts/imx7d-pinfunc.h @@ -1,7 +1,10 @@ /* * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * */ #ifndef __DTS_IMX7D_PINFUNC_H @@ -12,57 +15,61 @@ * <mux_reg conf_reg input_reg mux_mode input_val> */ -#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 -#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 -#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 -#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 -#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 -#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 -#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 -#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 -#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 -#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 -#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 -#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 -#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 -#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 -#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 -#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 -#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 -#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 -#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 -#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 -#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 -#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 -#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 -#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 -#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 -#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 -#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 +#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 +#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 +#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 +#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 #define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 #define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 #define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts new file mode 100644 index 0000000000..85b83c351f --- /dev/null +++ b/arch/arm/dts/imx7d-sdb.dts @@ -0,0 +1,309 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 SabreSD Board"; + compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + gpio-sck = <&gpio1 13 0>; + gpio-mosi = <&gpio1 9 0>; + cs-gpios = <&gpio1 12 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ + spi-max-frequency = <100000>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + enable-active-high; + }; + }; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_spi1: spi1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi new file mode 100644 index 0000000000..f6dee41a05 --- /dev/null +++ b/arch/arm/dts/imx7d.dtsi @@ -0,0 +1,140 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx7s.dtsi" + +/ { + cpus { + cpu0: cpu@0 { + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + clock-frequency = <996000000>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clock-frequency = <996000000>; + }; + }; + + soc { + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; + + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; +}; + +&aips3 { + usbotg2: usb@30b20000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b20000 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc2: usbmisc@30b20200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b20200 0x200>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + }; + + fec2: ethernet@30bf0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30bf0000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; +}; + +&ca_funnel_ports { + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; + }; + }; +}; diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi new file mode 100644 index 0000000000..a7d48e785d --- /dev/null +++ b/arch/arm/dts/imx7s.dtsi @@ -0,0 +1,999 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/imx7d-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx7d-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + * Also for U-Boot there must be a pre-existing /memory node. + */ + chosen {}; + memory { device_type = "memory"; reg = <0 0>; }; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <792000000>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_CLK_ARM>; + }; + }; + + ckil: clock-cki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + funnel@30041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ca_funnel_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* funnel output port */ + port@2 { + reg = <0>; + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + + funnel@30083000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + slave-mode; /* M4 input */ + }; + }; + + port@2 { + reg = <0>; + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + aips1: aips-bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 13 32>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 45 29>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 74 24>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 98 18>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 116 23>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 139 16>; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; + status = "disabled"; + }; + + wdog4: wdog@302b0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302b0000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc_lpsr: iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + }; + + gpt1: gpt@302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: gpt@302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: gpt@302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: gpt@30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x30300000 0x10000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "fsl,imx7d-ocotp", "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_OCOTP_CLK>; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x30360000 0x10000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + reg_1p0d: regulator-vdd1p0d { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + }; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clks: ccm@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: src@30390000 { + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + }; + + aips2: aips-bus@30400000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30400000 0x400000>; + ranges; + + adc1: adc@30610000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30610000 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + status = "disabled"; + }; + + adc2: adc@30620000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30620000 0x10000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + status = "disabled"; + }; + + ecspi4: ecspi@30630000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30630000 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, + <&clks IMX7D_ECSPI4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm1: pwm@30660000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM1_ROOT_CLK>, + <&clks IMX7D_PWM1_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM2_ROOT_CLK>, + <&clks IMX7D_PWM2_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM3_ROOT_CLK>, + <&clks IMX7D_PWM3_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM4_ROOT_CLK>, + <&clks IMX7D_PWM4_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + lcdif: lcdif@30730000 { + compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; + reg = <0x30730000 0x10000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, + <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; + clock-names = "pix", "axi"; + status = "disabled"; + }; + }; + + aips3: aips-bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; + + flexcan1: can@30a00000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a00000 0x10000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan2: can@30a10000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a10000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usbotg1: usb@30b10000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b10000 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbh: usb@30b30000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b30000 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop3>; + fsl,usbmisc = <&usbmisc3 0>; + phy_type = "hsic"; + dr_mode = "host"; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc1: usbmisc@30b10200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b10200 0x200>; + }; + + usbmisc3: usbmisc@30b30200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b30200 0x200>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + }; + + usbphynop3: usbphynop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + }; + + usdhc1: usdhc@30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc@30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + sdma: sdma@30bd0000 { + compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SDMA_CORE_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi new file mode 100644 index 0000000000..377700df11 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -0,0 +1,869 @@ +/* + * Copyright Altera Corporation (C) 2014-2017. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/altr,rst-mgr-a10.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + spi0 = &spi0; + spi1 = &spi1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@ffffd000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xffffd000 0x1000>, + <0xffffc100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffda1000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda1000 0x1000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, + <0 84 IRQ_TYPE_LEVEL_HIGH>, + <0 85 IRQ_TYPE_LEVEL_HIGH>, + <0 86 IRQ_TYPE_LEVEL_HIGH>, + <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>, + <0 89 IRQ_TYPE_LEVEL_HIGH>, + <0 90 IRQ_TYPE_LEVEL_HIGH>, + <0 91 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + reg-names = "soc_clock_manager_OCP_SLV"; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + cb_intosc_ls_clk: cb_intosc_ls_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_free_clk: f2s_free_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>; + reg = <0x40>; + + main_mpu_base_clk: main_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x140 0 11>; + }; + + main_noc_base_clk: main_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + div-reg = <0x144 0 11>; + }; + + main_emaca_clk: main_emaca_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x68>; + }; + + main_emacb_clk: main_emacb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x6C>; + }; + + main_emac_ptp_clk: main_emac_ptp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x70>; + }; + + main_gpio_db_clk: main_gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x74>; + }; + + main_sdmmc_clk: main_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x78>; + }; + + main_s2f_usr0_clk: main_s2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x7C>; + }; + + main_s2f_usr1_clk: main_s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x80>; + }; + + main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x84>; + }; + + main_periph_ref_clk: main_periph_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_pll>; + reg = <0x9C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-a10-pll-clock"; + clocks = <&osc1>, <&cb_intosc_ls_clk>, + <&f2s_free_clk>, <&main_periph_ref_clk>; + reg = <0xC0>; + + peri_mpu_base_clk: peri_mpu_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x140 16 11>; + }; + + peri_noc_base_clk: peri_noc_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + div-reg = <0x144 16 11>; + }; + + peri_emaca_clk: peri_emaca_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xE8>; + }; + + peri_emacb_clk: peri_emacb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xEC>; + }; + + peri_emac_ptp_clk: peri_emac_ptp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF0>; + }; + + peri_gpio_db_clk: peri_gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF4>; + }; + + peri_sdmmc_clk: peri_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xF8>; + }; + + peri_s2f_usr0_clk: peri_s2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0xFC>; + }; + + peri_s2f_usr1_clk: peri_s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x100>; + }; + + peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&periph_pll>; + reg = <0x104>; + }; + }; + + mpu_free_clk: mpu_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x60>; + }; + + noc_free_clk: noc_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x64>; + }; + + s2f_user1_free_clk: s2f_user1_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + reg = <0x104>; + }; + + sdmmc_free_clk: sdmmc_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, + <&osc1>, <&cb_intosc_hs_div2_clk>, + <&f2s_free_clk>; + fixed-divider = <4>; + reg = <0xF8>; + }; + + l4_sys_free_clk: l4_sys_free_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-perip-clk"; + clocks = <&noc_free_clk>; + fixed-divider = <4>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 0 2>; + clk-gate = <0x48 1>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 8 2>; + clk-gate = <0x48 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&noc_free_clk>; + div-reg = <0xA8 16 2>; + clk-gate = <0x48 3>; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&mpu_free_clk>; + fixed-divider = <4>; + clk-gate = <0x48 0>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&sdmmc_free_clk>; + clk-gate = <0xC8 5>; + clk-phase = <0 135>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 11>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 10>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_main_clk>; + clk-gate = <0xC8 9>; + }; + + usb_clk: usb_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&l4_mp_clk>; + clk-gate = <0xC8 8>; + }; + + s2f_usr1_clk: s2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-a10-gate-clk"; + clocks = <&peri_s2f_usr1_clk>; + clk-gate = <0xC8 6>; + }; + }; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + reg = <0xff800000 0x2000>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + reg = <0xff802000 0x2000>; + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x4C 0>; + reg = <0xff804000 0x2000>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <4096>; + rx-fifo-depth = <16384>; + clocks = <&l4_mp_clk>; + clock-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02900 0x100>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02a00 0x100>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio2: gpio@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02b00 0x100>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + fpga_mgr: fpga-mgr@ffd03000 { + compatible = "altr,socfpga-a10-fpga-mgr"; + reg = <0xffd03000 0x100 + 0xffcfe400 0x20>; + clocks = <&l4_mp_clk>; + resets = <&rst FPGAMGR_RESET>; + reset-names = "fpgamgr"; + }; + + i2c0: i2c@ffc02200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02200 0x100>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c1: i2c@ffc02300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02300 0x100>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c2: i2c@ffc02400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02400 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c3: i2c@ffc02500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02500 0x100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + i2c4: i2c@ffc02600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02600 0x100>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + sdr: sdr@0xffcfb100 { + compatible = "syscon"; + reg = <0xffcfb100 0x80>; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x100>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + num-chipselect = <4>; + bus-num = <0>; + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + num-chipselect = <4>; + bus-num = <0>; + tx-dma-channel = <&pdma 20>; + rx-dma-channel = <&pdma 21>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + + L2: l2-cache@fffff000 { + compatible = "arm,pl310-cache"; + reg = <0xfffff000 0x1000>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + }; + + mmc: dwmmc0@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + fifo-depth = <0x400>; + bus-width = <4>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x40000>; + }; + + eccmgr: eccmgr@ffd06000 { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-a10"; + altr,sdr-syscon = <&sdr>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <49 IRQ_TYPE_LEVEL_HIGH>; + }; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <32 IRQ_TYPE_LEVEL_HIGH>; + }; + + ocram-ecc@ff8c3000 { + compatible = "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8c3000 0x400>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-rx-ecc@ff8c0800 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0800 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, + <36 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@ff8c0c00 { + compatible = "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0c00 0x400>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, + <37 IRQ_TYPE_LEVEL_HIGH>; + }; + + dma-ecc@ff8c8000 { + compatible = "altr,socfpga-dma-ecc"; + reg = <0xff8c8000 0x400>; + altr,ecc-parent = <&pdma>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <42 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@ff8c8800 { + compatible = "altr,socfpga-usb-ecc"; + reg = <0xff8c8800 0x400>; + altr,ecc-parent = <&usb0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qspi: qspi@ff809000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cadence,qspi"; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_main_clk>; + ext-decoder = <0>; /* external decoder */ + num-chipselect = <4>; + fifo-depth = <128>; + sram-size = <512>; + bus-num = <2>; + status = "disabled"; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x100>; + altr,modrst-offset = <0x20>; + }; + + scu: snoop-control-unit@ffffc000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xffffc000 0x100>; + }; + + sysmgr: sysmgr@ffd06000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd06000 0x300>; + cpu1-start-addr = <0xffd06230>; + }; + + /* Local timer */ + timer@ffffc600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xffffc600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc02700 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02700 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc02800 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02800 0x100>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd00000 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd01000 0x100>; + clocks = <&l4_sys_free_clk>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + uart1: serial1@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>; + clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usb_clk>; + clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&l4_sys_free_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts new file mode 100644 index 0000000000..b573d0e658 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015-2017 Altera Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200"; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&mmc { + u-boot,dm-pre-reloc; + status = "okay"; + num-slots = <1>; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi new file mode 100644 index 0000000000..d10e089976 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi @@ -0,0 +1,481 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 X11 + * + *<auto-generated> + * This code was generated by a tool based on + * handoffs from both Qsys and Quartus. + * + * Changes to this file may be lost if + * the code is regenerated. + *</auto-generated> + */ + +#include "socfpga_arria10.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + chosen { + /* Bootloader setting: uboot.rbf_filename */ + cff-file = "ghrd_10as066n2.periph.rbf"; + early-release-fpga-config; + }; + + soc { + u-boot,dm-pre-reloc; + clkmgr@ffd04000 { + u-boot,dm-pre-reloc; + clocks { + u-boot,dm-pre-reloc; + osc1 { + u-boot,dm-pre-reloc; + clock-frequency = <25000000>; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + }; + + cb_intosc_ls_clk { + u-boot,dm-pre-reloc; + clock-frequency = <60000000>; + clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk"; + }; + + f2s_free_clk { + u-boot,dm-pre-reloc; + clock-frequency = <200000000>; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + }; + + main_pll { + u-boot,dm-pre-reloc; + /* + * Address Block: soc_clock_manager_OCP_SLV. + * i_clk_mgr_mainpllgrp + */ + altr,of_reg_value = < + 0 /* Field: vco0.psrc */ + 1 /* Field: vco1.denom */ + 191 /* Field: vco1.numer */ + 0 /* Field: mpuclk */ + 0 /* Field: mpuclk.cnt */ + 0 /* Field: mpuclk.src */ + 0 /* Field: nocclk */ + 0 /* Field: nocclk.cnt */ + 0 /* Field: nocclk.src */ + 900 /* Field: cntr2clk.cnt */ + 900 /* Field: cntr3clk.cnt */ + 900 /* Field: cntr4clk.cnt */ + 900 /* Field: cntr5clk.cnt */ + 900 /* Field: cntr6clk.cnt */ + 900 /* Field: cntr7clk.cnt */ + 0 /* Field: cntr7clk.src */ + 900 /* Field: cntr8clk.cnt */ + 900 /* Field: cntr9clk.cnt */ + 0 /* Field: cntr9clk.src */ + 900 /* Field: cntr15clk.cnt */ + 0 /* Field: nocdiv.l4mainclk */ + 0 /* Field: nocdiv.l4mpclk */ + 2 /* Field: nocdiv.l4spclk */ + 0 /* Field: nocdiv.csatclk */ + 1 /* Field: nocdiv.cstraceclk */ + 1 /* Field: nocdiv.cspdbgclk */ + >; + }; + + periph_pll { + u-boot,dm-pre-reloc; + /* + * Address Block: soc_clock_manager_OCP_SLV. + * i_clk_mgr_perpllgrp + */ + altr,of_reg_value = < + 0 /* Field: vco0.psrc */ + 1 /* Field: vco1.denom */ + 159 /* Field: vco1.numer */ + 7 /* Field: cntr2clk.cnt */ + 1 /* Field: cntr2clk.src */ + 900 /* Field: cntr3clk.cnt */ + 1 /* Field: cntr3clk.src */ + 19 /* Field: cntr4clk.cnt */ + 1 /* Field: cntr4clk.src */ + 499 /* Field: cntr5clk.cnt */ + 1 /* Field: cntr5clk.src */ + 9 /* Field: cntr6clk.cnt */ + 1 /* Field: cntr6clk.src */ + 900 /* Field: cntr7clk.cnt */ + 900 /* Field: cntr8clk.cnt */ + 0 /* Field: cntr8clk.src */ + 900 /* Field: cntr9clk.cnt */ + 0 /* Field: emacctl.emac0sel */ + 0 /* Field: emacctl.emac1sel */ + 0 /* Field: emacctl.emac2sel */ + 32000 /* Field: gpiodiv.gpiodbclk */ + >; + }; + + altera { + u-boot,dm-pre-reloc; + /* + * Address Block: soc_clock_manager_OCP_SLV. + * i_clk_mgr_alteragrp + */ + altr,of_reg_value = < + 0x0384000b /* Register: nocclk */ + 0x03840001 /* Register: mpuclk */ + >; + }; + }; + }; + + /* + * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver + * Binding: pinmux + */ + i_io48_pin_mux: pinmux@0xffd07000 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_shared_3v_io_grp + */ + shared { + u-boot,dm-pre-reloc; + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Reg: pinmux_shared_io_q1_1 */ + <0x00000000 0x00000008>, + /* Reg: pinmux_shared_io_q1_2 */ + <0x00000004 0x00000008>, + /* Reg: pinmux_shared_io_q1_3 */ + <0x00000008 0x00000008>, + /* Reg: pinmux_shared_io_q1_4 */ + <0x0000000c 0x00000008>, + /* Reg: pinmux_shared_io_q1_5 */ + <0x00000010 0x00000008>, + /* Reg: pinmux_shared_io_q1_6 */ + <0x00000014 0x00000008>, + /* Reg: pinmux_shared_io_q1_7 */ + <0x00000018 0x00000008>, + /* Reg: pinmux_shared_io_q1_8 */ + <0x0000001c 0x00000008>, + /* Reg: pinmux_shared_io_q1_9 */ + <0x00000020 0x00000008>, + /* Reg: pinmux_shared_io_q1_10 */ + <0x00000024 0x00000008>, + /* Reg: pinmux_shared_io_q1_11 */ + <0x00000028 0x00000008>, + /* Reg: pinmux_shared_io_q1_12 */ + <0x0000002c 0x00000008>, + /* Reg: pinmux_shared_io_q2_1 */ + <0x00000030 0x00000004>, + /* Reg: pinmux_shared_io_q2_2 */ + <0x00000034 0x00000004>, + /* Reg: pinmux_shared_io_q2_3 */ + <0x00000038 0x00000004>, + /* Reg: pinmux_shared_io_q2_4 */ + <0x0000003c 0x00000004>, + /* Reg: pinmux_shared_io_q2_5 */ + <0x00000040 0x00000004>, + /* Reg: pinmux_shared_io_q2_6 */ + <0x00000044 0x00000004>, + /* Reg: pinmux_shared_io_q2_7 */ + <0x00000048 0x00000004>, + /* Reg: pinmux_shared_io_q2_8 */ + <0x0000004c 0x00000004>, + /* Reg: pinmux_shared_io_q2_9 */ + <0x00000050 0x00000004>, + /* Reg: pinmux_shared_io_q2_10 */ + <0x00000054 0x00000004>, + /* Reg: pinmux_shared_io_q2_11 */ + <0x00000058 0x00000004>, + /* Reg: pinmux_shared_io_q2_12 */ + <0x0000005c 0x00000004>, + /* Reg: pinmux_shared_io_q3_1 */ + <0x00000060 0x00000003>, + /* Reg: pinmux_shared_io_q3_2 */ + <0x00000064 0x00000003>, + /* Reg: pinmux_shared_io_q3_3 */ + <0x00000068 0x00000003>, + /* Reg: pinmux_shared_io_q3_4 */ + <0x0000006c 0x00000003>, + /* Reg: pinmux_shared_io_q3_5 */ + <0x00000070 0x00000003>, + /* Reg: pinmux_shared_io_q3_6 */ + <0x00000074 0x0000000f>, + /* Reg: pinmux_shared_io_q3_7 */ + <0x00000078 0x0000000a>, + /* Reg: pinmux_shared_io_q3_8 */ + <0x0000007c 0x0000000a>, + /* Reg: pinmux_shared_io_q3_9 */ + <0x00000080 0x0000000a>, + /* Reg: pinmux_shared_io_q3_10 */ + <0x00000084 0x0000000a>, + /* Reg: pinmux_shared_io_q3_11 */ + <0x00000088 0x00000001>, + /* Reg: pinmux_shared_io_q3_12 */ + <0x0000008c 0x00000001>, + /* Reg: pinmux_shared_io_q4_1 */ + <0x00000090 0x00000000>, + /* Reg: pinmux_shared_io_q4_2 */ + <0x00000094 0x00000000>, + /* Reg: pinmux_shared_io_q4_3 */ + <0x00000098 0x0000000f>, + /* Reg: pinmux_shared_io_q4_4 */ + <0x0000009c 0x0000000c>, + /* Reg: pinmux_shared_io_q4_5 */ + <0x000000a0 0x0000000f>, + /* Reg: pinmux_shared_io_q4_6 */ + <0x000000a4 0x0000000f>, + /* Reg: pinmux_shared_io_q4_7 */ + <0x000000a8 0x0000000a>, + /* Reg: pinmux_shared_io_q4_8 */ + <0x000000ac 0x0000000a>, + /* Reg: pinmux_shared_io_q4_9 */ + <0x000000b0 0x0000000c>, + /* Reg: pinmux_shared_io_q4_10 */ + <0x000000b4 0x0000000c>, + /* Reg: pinmux_shared_io_q4_11 */ + <0x000000b8 0x0000000c>, + /* Reg: pinmux_shared_io_q4_12 */ + <0x000000bc 0x0000000c>; + }; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_dedicated_io_grp + */ + dedicated { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Reg: pinmux_dedicated_io_4 */ + <0x0000000c 0x00000008>, + /* Reg: pinmux_dedicated_io_5 */ + <0x00000010 0x00000008>, + /* Reg: pinmux_dedicated_io_6 */ + <0x00000014 0x00000008>, + /* Regi: pinmux_dedicated_io_7 */ + <0x00000018 0x00000008>, + /* Reg: pinmux_dedicated_io_8 */ + <0x0000001c 0x00000008>, + /* Reg: pinmux_dedicated_io_9 */ + <0x00000020 0x00000008>, + /* Reg: pinmux_dedicated_io_10 */ + <0x00000024 0x0000000a>, + /* Reg: pinmux_dedicated_io_11 */ + <0x00000028 0x0000000a>, + /* Reg: pinmux_dedicated_io_12 */ + <0x0000002c 0x00000008>, + /* Reg: pinmux_dedicated_io_13 */ + <0x00000030 0x00000008>, + /* Reg: pinmux_dedicated_io_14 */ + <0x00000034 0x00000008>, + /* Reg: pinmux_dedicated_io_15 */ + <0x00000038 0x00000008>, + /* Reg: pinmux_dedicated_io_16 */ + <0x0000003c 0x0000000d>, + /* Reg: pinmux_dedicated_io_17 */ + <0x00000040 0x0000000d>; + }; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_dedicated_io_grp + */ + dedicated_cfg { + u-boot,dm-pre-reloc; + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + /* Reg: cfg_dedicated_io_bank */ + <0x00000100 0x00000101>, + /* Reg: cfg_dedicated_io_1 */ + <0x00000104 0x000b080a>, + /* Reg: cfg_dedicated_io_2 */ + <0x00000108 0x000b080a>, + /* Reg: cfg_dedicated_io_3 */ + <0x0000010c 0x000b080a>, + /* Reg: cfg_dedicated_io_4 */ + <0x00000110 0x000a282a>, + /* Reg: cfg_dedicated_io_5 */ + <0x00000114 0x000a282a>, + /* Reg: cfg_dedicated_io_6 */ + <0x00000118 0x0008282a>, + /* Reg: cfg_dedicated_io_7 */ + <0x0000011c 0x000a282a>, + /* Reg: cfg_dedicated_io_8 */ + <0x00000120 0x000a282a>, + /* Reg: cfg_dedicated_io_9 */ + <0x00000124 0x000a282a>, + /* Reg: cfg_dedicated_io_10 */ + <0x00000128 0x00090000>, + /* Reg: cfg_dedicated_io_11 */ + <0x0000012c 0x00090000>, + /* Reg: cfg_dedicated_io_12 */ + <0x00000130 0x000b282a>, + /* Reg: cfg_dedicated_io_13 */ + <0x00000134 0x000b282a>, + /* Reg: cfg_dedicated_io_14 */ + <0x00000138 0x000b282a>, + /* Reg: cfg_dedicated_io_15 */ + <0x0000013c 0x000b282a>, + /* Reg: cfg_dedicated_io_16 */ + <0x00000140 0x0008282a>, + /* Reg: cfg_dedicated_io_17 */ + <0x00000144 0x000a282a>; + }; + + /* + * Address Block: soc_3v_io48_pin_mux_OCP_SLV. + * i_io48_pin_mux_fpga_interface_grp + */ + fpga { + u-boot,dm-pre-reloc; + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + /* Reg: pinmux_emac0_usefpga */ + <0x00000000 0x00000000>, + /* Reg: pinmux_emac1_usefpga */ + <0x00000004 0x00000000>, + /* Reg: pinmux_emac2_usefpga */ + <0x00000008 0x00000000>, + /* Reg: pinmux_i2c0_usefpga */ + <0x0000000c 0x00000000>, + /* Reg: pinmux_i2c1_usefpga */ + <0x00000010 0x00000000>, + /* Reg: pinmux_i2c_emac0_usefpga */ + <0x00000014 0x00000000>, + /* Reg: pinmux_i2c_emac1_usefpga */ + <0x00000018 0x00000000>, + /* Reg: pinmux_i2c_emac2_usefpga */ + <0x0000001c 0x00000000>, + /* Reg: pinmux_nand_usefpga */ + <0x00000020 0x00000000>, + /* Reg: pinmux_qspi_usefpga */ + <0x00000024 0x00000000>, + /* Reg: pinmux_sdmmc_usefpga */ + <0x00000028 0x00000000>, + /* Reg: pinmux_spim0_usefpga */ + <0x0000002c 0x00000000>, + /* Reg: pinmux_spim1_usefpga */ + <0x00000030 0x00000000>, + /* Reg: pinmux_spis0_usefpga */ + <0x00000034 0x00000000>, + /* Reg: pinmux_spis1_usefpga */ + <0x00000038 0x00000000>, + /* Reg: pinmux_uart0_usefpga */ + <0x0000003c 0x00000000>, + /* Reg: pinmux_uart1_usefpga */ + <0x00000040 0x00000000>; + }; + }; + + i_noc: noc@0xffd10000 { + u-boot,dm-pre-reloc; + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + + firewall { + u-boot,dm-pre-reloc; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * mpuregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * mpuregion0addr.limit + */ + altr,mpu0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. + * hpsregion0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr. + * hpsregion0addr.limit + */ + altr,l3-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.limit + */ + altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.limit + */ + altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.base + * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.limit + */ + altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>; + }; + }; + + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + altr,init-val = <1>; + }; + + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + altr,init-val = <0>; + }; + + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + altr,init-val = <1>; + }; + }; +}; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 5294a90ccf..af7a22f22c 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -273,7 +273,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 290647148d..dccb56938e 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -342,7 +342,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index 0d3d963ffb..0fd4cbf19d 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ / { @@ -282,7 +318,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; @@ -446,7 +482,7 @@ }; nand: nand@68000000 { - compatible = "socionext,denali-nand-v5a"; + compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 210ac27093..c21b159674 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ / { @@ -405,7 +441,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; @@ -609,7 +645,7 @@ }; nand: nand@68000000 { - compatible = "socionext,denali-nand-v5a"; + compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 2c8558cb4d..4180d8ec1f 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -528,7 +528,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 6cd3a93b58..fb9d26a5e6 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -505,7 +505,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index 76b656652c..cdf7f9005f 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2017 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /memreserve/ 0x80000000 0x00080000; @@ -207,7 +243,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi index 9e458d3fce..b54e7a9bae 100644 --- a/arch/arm/dts/uniphier-sld3.dtsi +++ b/arch/arm/dts/uniphier-sld3.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ / { @@ -304,7 +340,7 @@ #size-cells = <1>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; @@ -444,7 +480,7 @@ }; nand: nand@f8000000 { - compatible = "socionext,denali-nand-v5a"; + compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0xf8000000 0x20>, <0xf8100000 0x1000>; diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 4117132d01..b6934afbdb 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ / { @@ -282,7 +318,7 @@ pinctrl-0 = <&pinctrl_system_bus>; }; - smpctrl@59800000 { + smpctrl@59801000 { compatible = "socionext,uniphier-smpctrl"; reg = <0x59801000 0x400>; }; @@ -446,7 +482,7 @@ }; nand: nand@68000000 { - compatible = "socionext,denali-nand-v5a"; + compatible = "socionext,uniphier-denali-nand-v5a"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-support-card.dtsi b/arch/arm/dts/uniphier-support-card.dtsi index 924f2296e6..fdbf0f6e99 100644 --- a/arch/arm/dts/uniphier-support-card.dtsi +++ b/arch/arm/dts/uniphier-support-card.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2017 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ &system_bus { @@ -17,14 +53,14 @@ #size-cells = <1>; ranges = <0x00000000 1 0x01f00000 0x00100000>; - ethsc: ethernet@00000000 { + ethsc: ethernet@0 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <0x00000000 0x1000>; phy-mode = "mii"; reg-io-width = <4>; }; - serialsc: uart@000b0000 { + serialsc: uart@b0000 { compatible = "ns16550a"; reg = <0x000b0000 0x20>; clock-frequency = <12288000>; diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index 25cbd12c89..cd8b8d2882 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -55,3 +55,9 @@ config CMD_DEKBLOB Freescale secure boot mechanism. This command encapsulates and creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for more information. + +config CMD_HDMIDETECT + bool "Support the 'hdmidet' command" + help + This enables the 'hdmidet' command which detects if an HDMI monitor + is connected. diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c index 5df4e02b53..1d97ac8e7f 100644 --- a/arch/arm/imx-common/rdc-sema.c +++ b/arch/arm/imx-common/rdc-sema.c @@ -94,7 +94,7 @@ int imx_rdc_sema_unlock(int per_id) reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID) - return 1; /*Not the semaphore owner */ + return -EACCES; /*Not the semaphore owner */ writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index ee6eff2b28..9b011147d6 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -105,9 +105,6 @@ int timer_init(void) #endif __raw_writel(i, &cur_gpt->control); - gd->arch.tbl = __raw_readl(&cur_gpt->counter); - gd->arch.tbu = 0; - return 0; } diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index 6ebc759f4b..113e1c73f3 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -24,17 +24,5 @@ #define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE #define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register represents UART Unit Enable */ -/* - * I2C definition - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MV 1 -#define CONFIG_MV_I2C_NUM 2 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000} -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 0 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif #endif /* _ARMD1_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index 170a9b3a7c..6424fafe14 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -34,7 +34,7 @@ u32 imx_get_i2cclk(unsigned i2c_num); #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable); #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD void enable_usboh3_clk(unsigned char enable); #endif void init_clk_usdhc(u32 index); diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 7ea7199f2b..0c99bbdc93 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -370,13 +370,6 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -/* - * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. - * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles - * into microsec and passing the value. - */ -#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 - #if defined(CONFIG_DRA7XX) #define V_OSCK 20000000 /* Clock output from T2 */ #else diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index faa14791f9..d328df9597 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -84,7 +84,8 @@ struct sunxi_ccm_reg { u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ #endif - u32 reserved14[3]; + u32 tve_clk_cfg; /* 0x120 H3/H5 TVE module clock */ + u32 reserved14[2]; u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ @@ -307,6 +308,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_DE_BE0 12 #define AHB_GATE_OFFSET_DE 12 #define AHB_GATE_OFFSET_HDMI 11 +#define AHB_GATE_OFFSET_TVE 9 #ifndef CONFIG_SUNXI_DE2 #define AHB_GATE_OFFSET_LCD1 5 #define AHB_GATE_OFFSET_LCD0 4 @@ -415,6 +417,9 @@ struct sunxi_ccm_reg { #define CCM_HDMI_SLOW_CTRL_DDC_GATE (1 << 31) +#define CCM_TVE_CTRL_GATE (0x1 << 31) +#define CCM_TVE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) + #if defined(CONFIG_MACH_SUN50I) #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */ #elif defined(CONFIG_MACH_SUN8I) @@ -448,6 +453,7 @@ struct sunxi_ccm_reg { #define AHB_RESET_OFFSET_DE 12 #define AHB_RESET_OFFSET_HDMI 11 #define AHB_RESET_OFFSET_HDMI2 10 +#define AHB_RESET_OFFSET_TVE 9 #ifndef CONFIG_SUNXI_DE2 #define AHB_RESET_OFFSET_LCD1 5 #define AHB_RESET_OFFSET_LCD0 4 diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 93803addfb..e10197784e 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -225,52 +225,6 @@ struct sunxi_hdmi_reg { }; /* - * This is based on the A10s User Manual, and the A10s only supports - * composite video and not vga like the A10 / A20 does, still other - * than the removed vga out capability the tvencoder seems to be the same. - * "unknown#" registers are registers which are used in the A10 kernel code, - * but not documented in the A10s User Manual. - */ -struct sunxi_tve_reg { - u32 gctrl; /* 0x000 */ - u32 cfg0; /* 0x004 */ - u32 dac_cfg0; /* 0x008 */ - u32 filter; /* 0x00c */ - u32 chroma_freq; /* 0x010 */ - u32 porch_num; /* 0x014 */ - u32 unknown0; /* 0x018 */ - u32 line_num; /* 0x01c */ - u32 blank_black_level; /* 0x020 */ - u32 unknown1; /* 0x024, seems to be 1 byte per dac */ - u8 res0[0x08]; /* 0x028 */ - u32 auto_detect_en; /* 0x030 */ - u32 auto_detect_int_status; /* 0x034 */ - u32 auto_detect_status; /* 0x038 */ - u32 auto_detect_debounce; /* 0x03c */ - u32 csc_reg0; /* 0x040 */ - u32 csc_reg1; /* 0x044 */ - u32 csc_reg2; /* 0x048 */ - u32 csc_reg3; /* 0x04c */ - u8 res1[0xb0]; /* 0x050 */ - u32 color_burst; /* 0x100 */ - u32 vsync_num; /* 0x104 */ - u32 notch_freq; /* 0x108 */ - u32 cbr_level; /* 0x10c */ - u32 burst_phase; /* 0x110 */ - u32 burst_width; /* 0x114 */ - u32 unknown2; /* 0x118 */ - u32 sync_vbi_level; /* 0x11c */ - u32 white_level; /* 0x120 */ - u32 active_num; /* 0x124 */ - u32 chroma_bw_gain; /* 0x128 */ - u32 notch_width; /* 0x12c */ - u32 resync_num; /* 0x130 */ - u32 slave_para; /* 0x134 */ - u32 cfg1; /* 0x138 */ - u32 cfg2; /* 0x13c */ -}; - -/* * DE-FE register constants. */ #define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) @@ -394,67 +348,6 @@ struct sunxi_tve_reg { #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8) #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9) -/* - * TVE register constants. - */ -#define SUNXI_TVE_GCTRL_ENABLE (1 << 0) -/* - * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed - * dac from tve1. When using tve1 the mux value must be written to both tve0's - * and tve1's gctrl reg. - */ -#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4)) -#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) -#define SUNXI_TVE_CFG0_VGA 0x20000000 -#define SUNXI_TVE_CFG0_PAL 0x07030001 -#define SUNXI_TVE_CFG0_NTSC 0x07030000 -#define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 -#ifdef CONFIG_MACH_SUN5I -#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 -#else -#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 -#endif -#define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 -#define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 -#define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 -#define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018 -#define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020 -#define SUNXI_TVE_LINE_NUM_PAL 0x00160271 -#define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d -#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc -#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a -#define SUNXI_TVE_UNKNOWN1_VGA 0x00000000 -#define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818 -#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0)) -#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16)) -#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0)) -#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8) -#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8)) -#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0 -#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1 -#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 -#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) -#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) -#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) -#define SUNXI_TVE_CSC_REG0 0x08440832 -#define SUNXI_TVE_CSC_REG1 0x3b6dace1 -#define SUNXI_TVE_CSC_REG2 0x0e1d13dc -#define SUNXI_TVE_CSC_REG3 0x00108080 -#define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000 -#define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828 -#define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f -#define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000 -#define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e -#define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0 -#define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0 -#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0 -#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0 -#define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002 -#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101 -#define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c -#define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c -#define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000 - int sunxi_simplefb_setup(void *blob); #endif /* _SUNXI_DISPLAY_H */ diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index 831d0c0ff6..9358397da2 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -10,7 +10,7 @@ #define BOOT0_MAGIC "eGON.BT0" #define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ -#define SPL_HEADER_VERSION 1 +#define SPL_HEADER_VERSION 2 #ifdef CONFIG_SUNXI_HIGH_SRAM #define SPL_ADDR 0x10000 @@ -58,11 +58,24 @@ struct boot_file_head { * compatible format, ready to be imported via "env import -t". */ uint32_t fel_uEnv_length; - uint32_t reserved1[2]; + /* + * Offset of an ASCIIZ string (relative to the SPL header), which + * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE). + * This is optional and may be set to NULL. Is intended to be used + * by flash programming tools for providing nice informative messages + * to the users. + */ + uint32_t dt_name_offset; + uint32_t reserved1; uint32_t boot_media; /* written here by the boot ROM */ - uint32_t reserved2[5]; /* padding, align to 64 bytes */ + /* A padding area (may be used for storing text strings) */ + uint32_t string_pool[13]; + /* The header must be a multiple of 32 bytes (for VBAR alignment) */ }; +/* Compile time check to assure proper alignment of structure */ +typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)]; + #define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) #endif diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h new file mode 100644 index 0000000000..41a14a68e4 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/tve.h @@ -0,0 +1,131 @@ +/* + * Sunxi TV encoder register and constant defines + * + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TVE_H +#define _TVE_H + +enum tve_mode { + tve_mode_vga, + tve_mode_composite_pal, + tve_mode_composite_ntsc, + tve_mode_composite_pal_m, + tve_mode_composite_pal_nc, +}; + +/* + * This is based on the A10s User Manual, and the A10s only supports + * composite video and not vga like the A10 / A20 does, still other + * than the removed vga out capability the tvencoder seems to be the same. + * "unknown#" registers are registers which are used in the A10 kernel code, + * but not documented in the A10s User Manual. + */ +struct sunxi_tve_reg { + u32 gctrl; /* 0x000 */ + u32 cfg0; /* 0x004 */ + u32 dac_cfg0; /* 0x008 */ + u32 filter; /* 0x00c */ + u32 chroma_freq; /* 0x010 */ + u32 porch_num; /* 0x014 */ + u32 unknown0; /* 0x018 */ + u32 line_num; /* 0x01c */ + u32 blank_black_level; /* 0x020 */ + u32 unknown1; /* 0x024, seems to be 1 byte per dac */ + u8 res0[0x08]; /* 0x028 */ + u32 auto_detect_en; /* 0x030 */ + u32 auto_detect_int_status; /* 0x034 */ + u32 auto_detect_status; /* 0x038 */ + u32 auto_detect_debounce; /* 0x03c */ + u32 csc_reg0; /* 0x040 */ + u32 csc_reg1; /* 0x044 */ + u32 csc_reg2; /* 0x048 */ + u32 csc_reg3; /* 0x04c */ + u8 res1[0xb0]; /* 0x050 */ + u32 color_burst; /* 0x100 */ + u32 vsync_num; /* 0x104 */ + u32 notch_freq; /* 0x108 */ + u32 cbr_level; /* 0x10c */ + u32 burst_phase; /* 0x110 */ + u32 burst_width; /* 0x114 */ + u32 unknown2; /* 0x118 */ + u32 sync_vbi_level; /* 0x11c */ + u32 white_level; /* 0x120 */ + u32 active_num; /* 0x124 */ + u32 chroma_bw_gain; /* 0x128 */ + u32 notch_width; /* 0x12c */ + u32 resync_num; /* 0x130 */ + u32 slave_para; /* 0x134 */ + u32 cfg1; /* 0x138 */ + u32 cfg2; /* 0x13c */ +}; + +/* + * TVE register constants. + */ +#define SUNXI_TVE_GCTRL_ENABLE (1 << 0) +/* + * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed + * dac from tve1. When using tve1 the mux value must be written to both tve0's + * and tve1's gctrl reg. + */ +#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4)) +#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) +#define SUNXI_TVE_CFG0_VGA 0x20000000 +#define SUNXI_TVE_CFG0_PAL 0x07030001 +#define SUNXI_TVE_CFG0_NTSC 0x07030000 +#define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 +#ifdef CONFIG_MACH_SUN5I +#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 +#else +#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 +#endif +#define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 +#define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 +#define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 +#define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018 +#define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020 +#define SUNXI_TVE_LINE_NUM_PAL 0x00160271 +#define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d +#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc +#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a +#define SUNXI_TVE_UNKNOWN1_VGA 0x00000000 +#define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818 +#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0)) +#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16)) +#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0)) +#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8) +#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8)) +#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0 +#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1 +#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 +#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) +#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) +#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) +#define SUNXI_TVE_CSC_REG0 0x08440832 +#define SUNXI_TVE_CSC_REG1 0x3b6dace1 +#define SUNXI_TVE_CSC_REG2 0x0e1d13dc +#define SUNXI_TVE_CSC_REG3 0x00108080 +#define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000 +#define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828 +#define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f +#define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000 +#define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e +#define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0 +#define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0 +#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0 +#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0 +#define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002 +#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101 +#define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c +#define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c +#define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000 + +void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode); +void tvencoder_enable(struct sunxi_tve_reg * const tve); + +#endif /* _TVE_H */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b0ca4bcf04..b0b3b9377e 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,12 +8,8 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_CHAIN_OF_TRUST -#define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_HW_ACCEL -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_SPL_BOARD_INIT #ifdef CONFIG_SPL_BUILD /* * Define the key hash for U-Boot here if public/private key pair used to @@ -30,7 +26,6 @@ #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SPL_BUILD -#define CONFIG_CMD_HASH #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images * is picked up from an Extension Table which has diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index ba0ed43811..ad35e0109e 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -253,6 +253,12 @@ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { \ imx_iomux_v3_setup_pad(MX6Q_##def); #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#elif defined(CONFIG_MX6UL) +#define IOMUX_PADS(x) MX6_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) #else #define IOMUX_PADS(x) MX6DL_##x #define SETUP_IOMUX_PAD(def) \ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index a0bda28104..5d7f7e6ec5 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -7,7 +7,7 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ -#if defined(CONFIG_OMAP) \ +#if defined(CONFIG_ARCH_OMAP2PLUS) \ || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ || defined(CONFIG_EXYNOS4210) /* Platform-specific defines */ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 53d4ed2bc6..f162c1428c 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -44,8 +44,10 @@ obj-y += stack.o ifdef CONFIG_CPU_V7M obj-y += interrupts_m.o else ifdef CONFIG_ARM64 -obj-y += ccn504.o +obj-$(CONFIG_FSL_LAYERSCAPE) += ccn504.o +ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),) obj-y += gic_64.o +endif obj-y += interrupts_64.o else obj-y += interrupts.o diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index 8de086efd6..a939b1fb8d 100644 --- a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -161,7 +161,7 @@ void at91_spi1_hw_init(unsigned long cs_mask) } #endif -#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD) void at91_uhp_hw_init(void) { /* Enable VBus on UHP ports */ diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 46981a5933..5b6c5ea328 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -17,6 +17,8 @@ config ARCH_EXYNOS5 bool "Exynos5 SoC family" select CPU_V7 select BOARD_EARLY_INIT_F + select SHA_HW_ACCEL + imply CMD_HASH help Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 3ea8dc33ef..cababdba52 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -6,19 +6,23 @@ choice config TARGET_K2HK_EVM bool "TI Keystone 2 Kepler/Hawking EVM" + select SPL_BOARD_INIT if SPL imply DM_I2C config TARGET_K2E_EVM bool "TI Keystone 2 Edison EVM" + select SPL_BOARD_INIT if SPL imply DM_I2C config TARGET_K2L_EVM bool "TI Keystone 2 Lamar EVM" + select SPL_BOARD_INIT if SPL imply DM_I2C config TARGET_K2G_EVM bool "TI Keystone 2 Galileo EVM" select BOARD_LATE_INIT + select SPL_BOARD_INIT if SPL select TI_I2C_BOARD_DETECT imply DM_I2C diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index b786df0aaf..ba6007186e 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -89,14 +89,13 @@ * USB/EHCI */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MARVELL #define CONFIG_EHCI_IS_TDI #endif /* CONFIG_CMD_USB */ /* * IDE Support on SATA ports */ -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define __io #define CONFIG_MVSATA_IDE #define CONFIG_IDE_PREINIT @@ -111,12 +110,12 @@ #define CONFIG_SYS_ATA_STRIDE 4 /* Controller supports 48-bits LBA addressing */ #define CONFIG_LBA48 -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +/* CONFIG_IDE requires some #defines for ATA registers */ #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* ATA registers base is at SATA controller base */ #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ /* * I2C related stuff diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 933fcba37c..7b298d671d 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -1,5 +1,21 @@ if OMAP34XX +# We only enable the clocks for the GPIO banks that a given board requies. +config OMAP3_GPIO_2 + bool + +config OMAP3_GPIO_3 + bool + +config OMAP3_GPIO_4 + bool + +config OMAP3_GPIO_5 + bool + +config OMAP3_GPIO_6 + bool + choice prompt "OMAP3 board select" optional @@ -9,18 +25,28 @@ config TARGET_AM3517_EVM config TARGET_MT_VENTOUX bool "TeeJet Mt.Ventoux" + select OMAP3_GPIO_4 + select OMAP3_GPIO_5 if USB_EHCI_HCD config TARGET_OMAP3_BEAGLE bool "TI OMAP3 BeagleBoard" select DM select DM_SERIAL select DM_GPIO + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" + select OMAP3_GPIO_2 + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 if LED_STATUS config TARGET_CM_T3517 bool "CompuLab CM-T3517 boards" + select OMAP3_GPIO_2 + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 if LED_STATUS config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" @@ -36,12 +62,20 @@ config TARGET_OMAP3_IGEP00X0 select DM select DM_SERIAL select DM_GPIO + select OMAP3_GPIO_3 + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 config TARGET_OMAP3_OVERO bool "OMAP35xx Gumstix Overo" select DM select DM_SERIAL select DM_GPIO + select OMAP3_GPIO_2 + select OMAP3_GPIO_3 + select OMAP3_GPIO_4 + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 config TARGET_OMAP3_ZOOM1 bool "TI Zoom1" @@ -54,16 +88,22 @@ config TARGET_AM3517_CRANE config TARGET_OMAP3_PANDORA bool "OMAP3 Pandora" + select OMAP3_GPIO_4 + select OMAP3_GPIO_6 config TARGET_ECO5PK bool "ECO5PK" + select OMAP3_GPIO_5 if USB_EHCI_HCD config TARGET_TRICORDER bool "Tricorder" + select OMAP3_GPIO_2 config TARGET_MCX bool "MCX" select BOARD_LATE_INIT + select OMAP3_GPIO_2 if USB_EHCI_HCD + select OMAP3_GPIO_5 if USB_EHCI_HCD config TARGET_OMAP3_LOGIC bool "OMAP3 Logic" @@ -71,15 +111,24 @@ config TARGET_OMAP3_LOGIC select DM select DM_SERIAL select DM_GPIO + select OMAP3_GPIO_4 + select OMAP3_GPIO_6 config TARGET_NOKIA_RX51 bool "Nokia RX51" config TARGET_TAO3530 bool "TAO3530" + select OMAP3_GPIO_2 + select OMAP3_GPIO_3 + select OMAP3_GPIO_4 + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 config TARGET_TWISTER bool "Twister" + select OMAP3_GPIO_2 + select OMAP3_GPIO_5 if USB_EHCI_HCD config TARGET_OMAP3_CAIRO bool "QUIPOS CAIRO" @@ -92,6 +141,11 @@ config TARGET_SNIPER select DM select DM_SERIAL select DM_GPIO + select OMAP3_GPIO_2 + select OMAP3_GPIO_3 + select OMAP3_GPIO_4 + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 endchoice diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index c89c438305..1a66abdeb2 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -63,6 +63,23 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE using hardware memory firewalls. This value must be smaller than the TI_SECURE_EMIF_TOTAL_REGION_SIZE value. +config OMAP_PLATFORM_RESET_TIME_MAX_USEC + int "Something" + range 0 31219 + default 31219 + help + Most OMAPs' provide a way to specify the time for which the reset + should be held low while the voltages and Oscillator outputs + stabilize. + This time is mostly board and PMIC dependent. Hence the boards are + expected to specify a pre-computed time using the above option. + This value can be computed using a summation of the below 3 + parameters + 1: Time taken by the Osciallator to stop and restart + 2: PMIC OTP time + 3: Voltage ramp time, which can be derived using the PMIC slew rate + and value of voltage ramp needed. + if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM menu "Voltage Domain OPP selections" diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 839d79d102..afe59e0b58 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -414,12 +414,13 @@ void setup_warmreset_time(void) { u32 rst_time, rst_val; -#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC - rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC; -#else - rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC; -#endif - rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT; + /* + * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. + * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles + * into microsec and passing the value. + */ + rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC) + << RSTTIME1_SHIFT; if (rst_time > RSTTIME1_MASK) rst_time = RSTTIME1_MASK; diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index a68f1d145d..b7f79800de 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -19,14 +19,6 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -/* - * Define Master code if there are multiple masters on the I2C_SR bus. - * Normally not required - */ -#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE -#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0 -#endif - /* Register defines and masks for VC IP Block */ /* PRM_VC_CFG_I2C_MODE */ #define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6) @@ -84,8 +76,10 @@ static void omap_vc_init(u16 speed_khz) (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); writel(val, (*prcm)->prm_vc_cfg_i2c_clk); - val = CONFIG_OMAP_VC_I2C_HS_MCODE << - PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; + /* + * Master code if there are multiple masters on the I2C_SR bus. + */ + val = 0x0 << PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; /* No HS mode for now */ val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; writel(val, (*prcm)->prm_vc_cfg_i2c_mode); diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 2a7eeba828..5db93ac8d6 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -1,7 +1,15 @@ if RCAR_GEN3 +choice + prompt "Select Target SoC" + config R8A7795 - bool + bool "Renesas SoC R8A7795" + +config R8A7796 + bool "Renesas SoC R8A7796" + +endchoice choice prompt "Renesus ARM64 SoCs board select" @@ -9,20 +17,14 @@ choice config TARGET_SALVATOR_X bool "Salvator-X board" - select R8A7795 help - Support for Renesas R-Car Gen3 R8a7795 platform + Support for Renesas R-Car Gen3 platform endchoice config SYS_SOC default "rmobile" -config RCAR_GEN3_EXTRAM_BOOT - bool "Enable boot from RAM" - depends on TARGET_SALVATOR_X - default n - source "board/renesas/salvator-x/Kconfig" endif diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 3b56fcf96f..2aea527bae 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -17,5 +17,6 @@ obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o +obj-$(CONFIG_R8A7796) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7796.o memmap-r8a7796.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index 42ee30fbe7..c373eef73d 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -8,7 +8,10 @@ #include <common.h> #include <asm/io.h> -#define PRR 0xFF000044 +#define PRR 0xFF000044 +#define PRR_MASK 0x7fff +#define R8A7796_REV_1_0 0x5200 +#define R8A7796_REV_1_1 0x5210 u32 rmobile_get_cpu_type(void) { @@ -17,10 +20,20 @@ u32 rmobile_get_cpu_type(void) u32 rmobile_get_cpu_rev_integer(void) { - return ((readl(PRR) & 0x000000F0) >> 4) + 1; + const u32 prr = readl(PRR); + + if ((prr & PRR_MASK) == R8A7796_REV_1_1) + return 1; + else + return ((prr & 0x000000F0) >> 4) + 1; } u32 rmobile_get_cpu_rev_fraction(void) { - return readl(PRR) & 0x0000000F; + const u32 prr = readl(PRR); + + if ((prr & PRR_MASK) == R8A7796_REV_1_1) + return 1; + else + return prr & 0x0000000F; } diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 129ab0c0f7..faa53197d5 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -56,6 +56,8 @@ static const struct { { 0x4A, "R8A7792" }, { 0x4B, "R8A7793" }, { 0x4C, "R8A7794" }, + { 0x4F, "R8A7795" }, + { 0x52, "R8A7796" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h index 4861bfe066..02b29364c5 100644 --- a/arch/arm/mach-rmobile/include/mach/gpio.h +++ b/arch/arm/mach-rmobile/include/mach/gpio.h @@ -25,6 +25,9 @@ void r8a7794_pinmux_init(void); #elif defined(CONFIG_R8A7795) #include "r8a7795-gpio.h" void r8a7795_pinmux_init(void); +#elif defined(CONFIG_R8A7796) +#include "r8a7796-gpio.h" +void r8a7796_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h index 63e156da27..554063ab8f 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h @@ -2,7 +2,7 @@ * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h * This file defines pin function control of gpio. * - * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015-2016 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,6 +13,8 @@ * GPIO_FN_xx - GPIO used to select pin function * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU */ + +/* V2(ES2.0) */ enum { GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, @@ -26,6 +28,7 @@ enum { GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + GPIO_GP_1_28, GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, @@ -81,6 +84,7 @@ enum { GPIO_GFN_D0, /* GPSR1 */ + GPIO_GFN_CLKOUT, GPIO_GFN_EX_WAIT0_A, GPIO_GFN_WE1x, GPIO_GFN_WE0x, @@ -146,23 +150,23 @@ enum { GPIO_GFN_SD0_CLK, /* GPSR4 */ - GPIO_FN_SD3_DS, + GPIO_GFN_SD3_DS, GPIO_GFN_SD3_DAT7, GPIO_GFN_SD3_DAT6, GPIO_GFN_SD3_DAT5, GPIO_GFN_SD3_DAT4, - GPIO_FN_SD3_DAT3, - GPIO_FN_SD3_DAT2, - GPIO_FN_SD3_DAT1, - GPIO_FN_SD3_DAT0, - GPIO_FN_SD3_CMD, - GPIO_FN_SD3_CLK, + GPIO_GFN_SD3_DAT3, + GPIO_GFN_SD3_DAT2, + GPIO_GFN_SD3_DAT1, + GPIO_GFN_SD3_DAT0, + GPIO_GFN_SD3_CMD, + GPIO_GFN_SD3_CLK, GPIO_GFN_SD2_DS, GPIO_GFN_SD2_DAT3, GPIO_GFN_SD2_DAT2, GPIO_GFN_SD2_DAT1, GPIO_GFN_SD2_DAT0, - GPIO_FN_SD2_CMD, + GPIO_GFN_SD2_CMD, GPIO_GFN_SD2_CLK, /* GPSR5 */ @@ -194,8 +198,8 @@ enum { GPIO_GFN_SCK0, /* GPSR6 */ - GPIO_GFN_USB31_OVC, - GPIO_GFN_USB31_PWEN, + GPIO_GFN_USB3_OVC, + GPIO_GFN_USB3_PWEN, GPIO_GFN_USB30_OVC, GPIO_GFN_USB30_PWEN, GPIO_GFN_USB1_OVC, @@ -224,8 +228,8 @@ enum { GPIO_GFN_SSI_SDATA2_A, GPIO_GFN_SSI_SDATA1_A, GPIO_GFN_SSI_SDATA0, - GPIO_GFN_SSI_WS0129, - GPIO_GFN_SSI_SCK0129, + GPIO_GFN_SSI_WS01239, + GPIO_GFN_SSI_SCK01239, /* GPSR7 */ GPIO_FN_HDMI1_CEC, @@ -237,7 +241,7 @@ enum { GPIO_IFN_AVB_MDC, GPIO_FN_MSIOF2_SS2_C, GPIO_IFN_AVB_MAGIC, - GPIO_FN_MSIOF2_S1_C, + GPIO_FN_MSIOF2_SS1_C, GPIO_FN_SCK4_A, GPIO_IFN_AVB_PHY_INT, GPIO_FN_MSIOF2_SYNC_C, @@ -248,6 +252,7 @@ enum { GPIO_IFN_AVB_AVTP_MATCH_A, GPIO_FN_MSIOF2_RXD_C, GPIO_FN_CTS4x_A, + GPIO_FN_FSCLKST2x_A, GPIO_IFN_AVB_AVTP_CAPTURE_A, GPIO_FN_MSIOF2_TXD_C, GPIO_FN_RTS4x_TANS_A, @@ -257,50 +262,53 @@ enum { GPIO_FN_VI4_DATA0_B, GPIO_FN_CAN0_TX_B, GPIO_FN_CANFD0_TX_B, + GPIO_FN_MSIOF3_SS2_E, GPIO_IFN_IRQ1, GPIO_FN_QPOLA, GPIO_FN_DU_DISP, GPIO_FN_VI4_DATA1_B, GPIO_FN_CAN0_RX_B, GPIO_FN_CANFD0_RX_B, + GPIO_FN_MSIOF3_SS1_E, /* IPSR1 */ GPIO_IFN_IRQ2, GPIO_FN_QCPV_QDE, GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, GPIO_FN_VI4_DATA2_B, + GPIO_FN_MSIOF3_SYNC_E, GPIO_FN_PWM3_B, GPIO_IFN_IRQ3, GPIO_FN_QSTVB_QVE, GPIO_FN_A25, GPIO_FN_DU_DOTCLKOUT1, GPIO_FN_VI4_DATA3_B, + GPIO_FN_MSIOF3_SCK_E, GPIO_FN_PWM4_B, GPIO_IFN_IRQ4, GPIO_FN_QSTH_QHS, GPIO_FN_A24, GPIO_FN_DU_EXHSYNC_DU_HSYNC, GPIO_FN_VI4_DATA4_B, + GPIO_FN_MSIOF3_RXD_E, GPIO_FN_PWM5_B, GPIO_IFN_IRQ5, GPIO_FN_QSTB_QHE, GPIO_FN_A23, GPIO_FN_DU_EXVSYNC_DU_VSYNC, GPIO_FN_VI4_DATA5_B, + GPIO_FN_FSCLKST2x_B, + GPIO_FN_MSIOF3_TXD_E, GPIO_FN_PWM6_B, GPIO_IFN_PWM0, GPIO_FN_AVB_AVTP_PPS, - GPIO_FN_A22, GPIO_FN_VI4_DATA6_B, GPIO_FN_IECLK_B, GPIO_IFN_PWM1_A, - GPIO_FN_A21, GPIO_FN_HRX3_D, GPIO_FN_VI4_DATA7_B, GPIO_FN_IERX_B, GPIO_IFN_PWM2_A, - GPIO_FN_PWMFSW0, - GPIO_FN_A20, GPIO_FN_HTX3_D, GPIO_FN_IETX_B, GPIO_IFN_A0, @@ -382,7 +390,6 @@ enum { GPIO_FN_SCL6_A, GPIO_FN_AVB_AVTP_CAPTURE_B, GPIO_FN_PWM2_B, - GPIO_FN_SPV_EVEN, GPIO_IFN_A12, GPIO_FN_LCDOUT12, GPIO_FN_MSIOF3_SCK_C, @@ -588,67 +595,94 @@ enum { GPIO_IFN_SD1_CLK, GPIO_FN_MSIOF1_SCK_G, GPIO_FN_SIM0_CLK_A, - GPIO_IFN_SD1_CMD, GPIO_FN_MSIOF1_SYNC_G, + GPIO_FN_NFCEx_B, GPIO_FN_SIM0_D_A, GPIO_FN_STP_IVCXO27_1_B, - GPIO_IFN_SD1_DAT0, GPIO_FN_SD2_DAT4, GPIO_FN_MSIOF1_RXD_G, + GPIO_FN_NFWPx_B, GPIO_FN_TS_SCK1_B, GPIO_FN_STP_ISCLK_1_B, - GPIO_IFN_SD1_DAT1, GPIO_FN_SD2_DAT5, GPIO_FN_MSIOF1_TXD_G, + GPIO_FN_NFDATA14_B, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_STP_ISSYNC_1_B, - GPIO_IFN_SD1_DAT2, GPIO_FN_SD2_DAT6, GPIO_FN_MSIOF1_SS1_G, + GPIO_FN_NFDATA15_B, GPIO_FN_TS_SDAT1_B, GPIO_FN_STP_IOD_1_B, GPIO_IFN_SD1_DAT3, GPIO_FN_SD2_DAT7, GPIO_FN_MSIOF1_SS2_G, + GPIO_FN_NFRBx_B, GPIO_FN_TS_SDEN1_B, GPIO_FN_STP_ISEN_1_B, /* IPSR9 */ GPIO_IFN_SD2_CLK, - GPIO_FN_SCKZ_A, + GPIO_FN_NFDATA8, + GPIO_IFN_SD2_CMD, + GPIO_FN_NFDATA9, GPIO_IFN_SD2_DAT0, - GPIO_FN_MTSx_A, + GPIO_FN_NFDATA10, GPIO_IFN_SD2_DAT1, - GPIO_FN_STMx_A, + GPIO_FN_NFDATA11, GPIO_IFN_SD2_DAT2, - GPIO_FN_MDATA_A, + GPIO_FN_NFDATA12, GPIO_IFN_SD2_DAT3, - GPIO_FN_SDATA_A, + GPIO_FN_NFDATA13, GPIO_IFN_SD2_DS, + GPIO_FN_NFALE, GPIO_FN_SATA_DEVSLP_B, - GPIO_FN_VSP_A, + GPIO_IFN_SD3_CLK, + GPIO_FN_NFWEx, + + /* IPSR10 */ + GPIO_IFN_SD3_CMD, + GPIO_FN_NFREx, + GPIO_IFN_SD3_DAT0, + GPIO_FN_NFDATA0, + GPIO_IFN_SD3_DAT1, + GPIO_FN_NFDATA1, + GPIO_IFN_SD3_DAT2, + GPIO_FN_NFDATA2, + GPIO_IFN_SD3_DAT3, + GPIO_FN_NFDATA3, GPIO_IFN_SD3_DAT4, GPIO_FN_SD2_CD_A, + GPIO_FN_NFDATA4, GPIO_IFN_SD3_DAT5, GPIO_FN_SD2_WP_A, - - /* IPSR10 */ + GPIO_FN_NFDATA5, GPIO_IFN_SD3_DAT6, GPIO_FN_SD3_CD, + GPIO_FN_NFDATA6, + + /* IPSR11 */ GPIO_IFN_SD3_DAT7, GPIO_FN_SD3_WP, + GPIO_FN_NFDATA7, + GPIO_IFN_SD3_DS, + GPIO_FN_NFCLE, GPIO_IFN_SD0_CD, + GPIO_FN_NFDATA14_A, GPIO_FN_SCL2_B, GPIO_FN_SIM0_RST_A, GPIO_IFN_SD0_WP, + GPIO_FN_NFDATA15_A, GPIO_FN_SDA2_B, GPIO_IFN_SD1_CD, + GPIO_FN_NFRBx_A, GPIO_FN_SIM0_CLK_B, GPIO_IFN_SD1_WP, + GPIO_FN_NFCEx_A, GPIO_FN_SIM0_D_B, GPIO_IFN_SCK0, GPIO_FN_HSCK1_B, @@ -656,16 +690,17 @@ enum { GPIO_FN_AUDIO_CLKC_B, GPIO_FN_SDA2_A, GPIO_FN_SIM0_RST_B, - GPIO_FN_STP_OPWM__C, + GPIO_FN_STP_OPWM_0_C, GPIO_FN_RIF0_CLK_B, GPIO_FN_ADICHS2, + GPIO_FN_SCK5_B, GPIO_IFN_RX0, GPIO_FN_HRX1_B, GPIO_FN_TS_SCK0_C, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_RIF0_D0_B, - /* IPSR11 */ + /* IPSR12 */ GPIO_IFN_TX0, GPIO_FN_HTX1_B, GPIO_FN_TS_SPSYNC0_C, @@ -690,7 +725,7 @@ enum { GPIO_IFN_RX1_A, GPIO_FN_HRX1_A, GPIO_FN_TS_SDAT0_C, - GPIO_FN_STP_IDS_0_C, + GPIO_FN_STP_ISD_0_C, GPIO_FN_RIF1_CLK_C, GPIO_IFN_TX1_A, GPIO_FN_HTX1_A, @@ -719,21 +754,19 @@ enum { GPIO_FN_RIF1_CLK_B, GPIO_FN_ADICLK, - /* IPSR12 */ + /* IPSR13 */ GPIO_IFN_TX2_A, GPIO_FN_SD2_CD_B, GPIO_FN_SCL1_A, - GPIO_FN_RSD_CLK_B, GPIO_FN_FMCLK_A, GPIO_FN_RIF1_D1_C, - GPIO_FN_FSO_CFE_0_B, + GPIO_FN_FSO_CFE_0x, GPIO_IFN_RX2_A, GPIO_FN_SD2_WP_B, GPIO_FN_SDA1_A, - GPIO_FN_RDS_DATA_B, - GPIO_FN_RMIN_A, + GPIO_FN_FMIN_A, GPIO_FN_RIF1_SYNC_C, - GPIO_FN_FSO_CEF_1_B, + GPIO_FN_FSO_CFE_1x, GPIO_IFN_HSCK0, GPIO_FN_MSIOF1_SCK_D, GPIO_FN_AUDIO_CLKB_A, @@ -741,21 +774,19 @@ enum { GPIO_FN_TS_SCK0_D, GPIO_FN_STP_ISCLK_0_D, GPIO_FN_RIF0_CLK_C, - GPIO_FN_AD_CLK, + GPIO_FN_RX5_B, GPIO_IFN_HRX0, GPIO_FN_MSIOF1_RXD_D, - GPIO_FN_SS1_SDATA2_B, + GPIO_FN_SSI_SDATA2_B, GPIO_FN_TS_SDEN0_D, GPIO_FN_STP_ISEN_0_D, GPIO_FN_RIF0_D0_C, - GPIO_FN_AD_DI, GPIO_IFN_HTX0, GPIO_FN_MSIOF1_TXD_D, GPIO_FN_SSI_SDATA9_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_STP_ISD_0_D, GPIO_FN_RIF0_D1_C, - GPIO_FN_AD_DO, GPIO_IFN_HCTS0x, GPIO_FN_RX2_B, GPIO_FN_MSIOF1_SYNC_D, @@ -764,7 +795,6 @@ enum { GPIO_FN_STP_ISSYNC_0_D, GPIO_FN_RIF0_SYNC_C, GPIO_FN_AUDIO_CLKOUT1_A, - GPIO_FN_AD_NSCx, GPIO_IFN_HRTS0x, GPIO_FN_TX2_B, GPIO_FN_MSIOF1_SS1_D, @@ -774,22 +804,23 @@ enum { GPIO_FN_AUDIO_CLKOUT2_A, GPIO_IFN_MSIOF0_SYNC, GPIO_FN_AUDIO_CLKOUT_A, + GPIO_FN_TX5_B, + GPIO_FN_BPFCLK_D, - /* IPSR13 */ + /* IPSR14 */ GPIO_IFN_MSIOF0_SS1, - GPIO_FN_RX5, + GPIO_FN_RX5_A, + GPIO_FN_NFWPx_A, GPIO_FN_AUDIO_CLKA_C, GPIO_FN_SSI_SCK2_A, - GPIO_FN_RDS_CLK_A, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_AUDIO_CLKOUT3_A, GPIO_FN_TCLK1_B, GPIO_IFN_MSIOF0_SS2, - GPIO_FN_TX5, + GPIO_FN_TX5_A, GPIO_FN_MSIOF1_SS2_D, GPIO_FN_AUDIO_CLKC_A, GPIO_FN_SSI_WS2_A, - GPIO_FN_RDS_DATA_A, GPIO_FN_STP_OPWM_0_D, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_SPEEDIN_B, @@ -803,17 +834,17 @@ enum { GPIO_IFN_MLB_DAT, GPIO_FN_TX1_B, GPIO_FN_MSIOF1_RXD_F, - GPIO_IFN_SSI_SCK0129, + GPIO_IFN_SSI_SCK01239, GPIO_FN_MSIOF1_TXD_F, GPIO_FN_MOUT0, - GPIO_IFN_SSI_WS0129, + GPIO_IFN_SSI_WS01239, GPIO_FN_MSIOF1_SS1_F, GPIO_FN_MOUT1, GPIO_IFN_SSI_SDATA0, GPIO_FN_MSIOF1_SS2_F, GPIO_FN_MOUT2, - /* IPSR14 */ + /* IPSR15 */ GPIO_IFN_SSI_SDATA1_A, GPIO_FN_MOUT5, GPIO_IFN_SSI_SDATA2_A, @@ -855,17 +886,13 @@ enum { GPIO_FN_RIF0_D0_A, GPIO_FN_RIF2_D1_A, - /* IPSR15 */ + /* IPSR16 */ GPIO_IFN_SSI_SCK6, - GPIO_FN_USB2_PWEN, GPIO_FN_SIM0_RST_D, - GPIO_FN_RDS_CLK_C, GPIO_IFN_SSI_WS6, - GPIO_FN_USB2_OVC, GPIO_FN_SIM0_D_D, GPIO_IFN_SSI_SDATA6, GPIO_FN_SIM0_CLK_D, - GPIO_FN_RSD_DATA_C, GPIO_FN_SATA_DEVSLP_A, GPIO_IFN_SSI_SCK78, GPIO_FN_HRX2_B, @@ -877,7 +904,7 @@ enum { GPIO_IFN_SSI_WS78, GPIO_FN_HTX2_B, GPIO_FN_MSIOF1_SYNC_C, - GPIO_FN_TS_SDT1_A, + GPIO_FN_TS_SDAT1_A, GPIO_FN_STP_ISD_1_A, GPIO_FN_RIF1_SYNC_A, GPIO_FN_RIF3_SYNC_A, @@ -885,7 +912,7 @@ enum { GPIO_FN_HCTS2x_B, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SDEN1_A, - GPIO_FN_STP_IEN_1_A, + GPIO_FN_STP_ISEN_1_A, GPIO_FN_RIF1_D0_A, GPIO_FN_RIF3_D0_A, GPIO_FN_TCLK2_A, @@ -895,7 +922,7 @@ enum { GPIO_FN_TS_SPSYNC1_A, GPIO_FN_STP_ISSYNC_1_A, GPIO_FN_RIF1_D1_A, - GPIO_FN_EIF3_D1_A, + GPIO_FN_RIF3_D1_A, GPIO_IFN_SSI_SDATA9_A, GPIO_FN_HSCK2_B, GPIO_FN_MSIOF1_SS1_C, @@ -903,31 +930,29 @@ enum { GPIO_FN_SSI_WS1_B, GPIO_FN_SCK1, GPIO_FN_STP_IVCXO27_1_A, - GPIO_FN_SCK5, + GPIO_FN_SCK5_A, - /* IPSR16 */ + /* IPSR17 */ GPIO_IFN_AUDIO_CLKA_A, GPIO_FN_CC5_OSCOUT, GPIO_IFN_AUDIO_CLKB_B, GPIO_FN_SCIF_CLK_A, - GPIO_FN_DVC_MUTE, GPIO_FN_STP_IVCXO27_1_D, GPIO_FN_REMOCON_A, GPIO_FN_TCLK1_A, - GPIO_FN_VSP_B, GPIO_IFN_USB0_PWEN, GPIO_FN_SIM0_RST_C, GPIO_FN_TS_SCK1_D, GPIO_FN_STP_ISCLK_1_D, GPIO_FN_BPFCLK_B, GPIO_FN_RIF3_CLK_B, - GPIO_FN_SCKZ_B, + GPIO_FN_HSCK2_C, GPIO_IFN_USB0_OVC, GPIO_FN_SIM0_D_C, GPIO_FN_TS_SDAT1_D, GPIO_FN_STP_ISD_1_D, GPIO_FN_RIF3_SYNC_B, - GPIO_FN_VSP_C, + GPIO_FN_HRX2_C, GPIO_IFN_USB1_PWEN, GPIO_FN_SIM0_CLK_C, GPIO_FN_SSI_SCK1_A, @@ -935,9 +960,8 @@ enum { GPIO_FN_STP_ISCLK_0_E, GPIO_FN_FMCLK_B, GPIO_FN_RIF2_CLK_B, - GPIO_FN_MTSx_B, GPIO_FN_SPEEDIN_A, - GPIO_FN_VSP_D, + GPIO_FN_HTX2_C, GPIO_IFN_USB1_OVC, GPIO_FN_MSIOF1_SS2_C, GPIO_FN_SSI_WS1_A, @@ -945,8 +969,8 @@ enum { GPIO_FN_STP_ISD_0_E, GPIO_FN_FMIN_B, GPIO_FN_RIF2_SYNC_B, - GPIO_FN_STMx_B, GPIO_FN_REMOCON_B, + GPIO_FN_HCTS2x_C, GPIO_IFN_USB30_PWEN, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_SSI_SCK2_B, @@ -954,9 +978,10 @@ enum { GPIO_FN_STP_ISEN_1_D, GPIO_FN_STP_OPWM_0_E, GPIO_FN_RIF3_D0_B, - GPIO_FN_MDATA_B, GPIO_FN_TCLK2_B, GPIO_FN_TPU0TO0, + GPIO_FN_BPFCLK_C, + GPIO_FN_HRTS2x_C, GPIO_IFN_USB30_OVC, GPIO_FN_AUDIO_CLKOUT1_B, GPIO_FN_SSI_WS2_B, @@ -964,25 +989,28 @@ enum { GPIO_FN_STP_ISSYNC_1_D, GPIO_FN_STP_IVCXO27_0_E, GPIO_FN_RIF3_D1_B, - GPIO_FN_SDATA_B, - GPIO_FN_RSO_TOE_B, + GPIO_FN_FSO_TOEx, GPIO_FN_TPU0TO1, - /* IPSR17 */ - GPIO_IFN_USB31_PWEN, + /* IPSR18 */ + GPIO_IFN_USB3_PWEN, GPIO_FN_AUDIO_CLKOUT2_B, - GPIO_FN_SI_SCK9_B, + GPIO_FN_SSI_SCK9_B, GPIO_FN_TS_SDEN0_E, GPIO_FN_STP_ISEN_0_E, GPIO_FN_RIF2_D0_B, GPIO_FN_TPU0TO2, - GPIO_IFN_USB31_OVC, + GPIO_FN_FMCLK_C, + GPIO_FN_FMCLK_D, + GPIO_IFN_USB3_OVC, GPIO_FN_AUDIO_CLKOUT3_B, GPIO_FN_SSI_WS9_B, GPIO_FN_TS_SPSYNC0_E, GPIO_FN_STP_ISSYNC_0_E, GPIO_FN_RIF2_D1_B, GPIO_FN_TPU0TO3, + GPIO_FN_FMIN_C, + GPIO_FN_FMIN_D, }; #endif /* __ASM_R8A7795_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h new file mode 100644 index 0000000000..2359e36a14 --- /dev/null +++ b/arch/arm/mach-rmobile/include/mach/r8a7796-gpio.h @@ -0,0 +1,1084 @@ +/* + * arch/arm/include/asm/arch-rcar_gen3/r8a7796-gpio.h + * This file defines pin function control of gpio. + * + * Copyright (C) 2016 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_R8A7796_GPIO_H__ +#define __ASM_R8A7796_GPIO_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + GPIO_GP_1_28, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27, + GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31, + + GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3, + + /* GPSR0 */ + GPIO_GFN_D15, + GPIO_GFN_D14, + GPIO_GFN_D13, + GPIO_GFN_D12, + GPIO_GFN_D11, + GPIO_GFN_D10, + GPIO_GFN_D9, + GPIO_GFN_D8, + GPIO_GFN_D7, + GPIO_GFN_D6, + GPIO_GFN_D5, + GPIO_GFN_D4, + GPIO_GFN_D3, + GPIO_GFN_D2, + GPIO_GFN_D1, + GPIO_GFN_D0, + + /* GPSR1 */ + GPIO_GFN_CLKOUT, + GPIO_GFN_EX_WAIT0_A, + GPIO_GFN_WE1x, + GPIO_GFN_WE0x, + GPIO_GFN_RD_WRx, + GPIO_GFN_RDx, + GPIO_GFN_BSx, + GPIO_GFN_CS1x_A26, + GPIO_GFN_CS0x, + GPIO_GFN_A19, + GPIO_GFN_A18, + GPIO_GFN_A17, + GPIO_GFN_A16, + GPIO_GFN_A15, + GPIO_GFN_A14, + GPIO_GFN_A13, + GPIO_GFN_A12, + GPIO_GFN_A11, + GPIO_GFN_A10, + GPIO_GFN_A9, + GPIO_GFN_A8, + GPIO_GFN_A7, + GPIO_GFN_A6, + GPIO_GFN_A5, + GPIO_GFN_A4, + GPIO_GFN_A3, + GPIO_GFN_A2, + GPIO_GFN_A1, + GPIO_GFN_A0, + + /* GPSR2 */ + GPIO_GFN_AVB_AVTP_CAPTURE_A, + GPIO_GFN_AVB_AVTP_MATCH_A, + GPIO_GFN_AVB_LINK, + GPIO_GFN_AVB_PHY_INT, + GPIO_GFN_AVB_MAGIC, + GPIO_GFN_AVB_MDC, + GPIO_GFN_PWM2_A, + GPIO_GFN_PWM1_A, + GPIO_GFN_PWM0, + GPIO_GFN_IRQ5, + GPIO_GFN_IRQ4, + GPIO_GFN_IRQ3, + GPIO_GFN_IRQ2, + GPIO_GFN_IRQ1, + GPIO_GFN_IRQ0, + + /* GPSR3 */ + GPIO_GFN_SD1_WP, + GPIO_GFN_SD1_CD, + GPIO_GFN_SD0_WP, + GPIO_GFN_SD0_CD, + GPIO_GFN_SD1_DAT3, + GPIO_GFN_SD1_DAT2, + GPIO_GFN_SD1_DAT1, + GPIO_GFN_SD1_DAT0, + GPIO_GFN_SD1_CMD, + GPIO_GFN_SD1_CLK, + GPIO_GFN_SD0_DAT3, + GPIO_GFN_SD0_DAT2, + GPIO_GFN_SD0_DAT1, + GPIO_GFN_SD0_DAT0, + GPIO_GFN_SD0_CMD, + GPIO_GFN_SD0_CLK, + + /* GPSR4 */ + GPIO_GFN_SD3_DS, + GPIO_GFN_SD3_DAT7, + GPIO_GFN_SD3_DAT6, + GPIO_GFN_SD3_DAT5, + GPIO_GFN_SD3_DAT4, + GPIO_FN_SD3_DAT3, + GPIO_FN_SD3_DAT2, + GPIO_FN_SD3_DAT1, + GPIO_FN_SD3_DAT0, + GPIO_FN_SD3_CMD, + GPIO_FN_SD3_CLK, + GPIO_GFN_SD2_DS, + GPIO_GFN_SD2_DAT3, + GPIO_GFN_SD2_DAT2, + GPIO_GFN_SD2_DAT1, + GPIO_GFN_SD2_DAT0, + GPIO_FN_SD2_CMD, + GPIO_GFN_SD2_CLK, + + /* GPSR5 */ + GPIO_GFN_MLB_DAT, + GPIO_GFN_MLB_SIG, + GPIO_GFN_MLB_CLK, + GPIO_FN_MSIOF0_RXD, + GPIO_GFN_MSIOF0_SS2, + GPIO_FN_MSIOF0_TXD, + GPIO_GFN_MSIOF0_SS1, + GPIO_GFN_MSIOF0_SYNC, + GPIO_FN_MSIOF0_SCK, + GPIO_GFN_HRTS0x, + GPIO_GFN_HCTS0x, + GPIO_GFN_HTX0, + GPIO_GFN_HRX0, + GPIO_GFN_HSCK0, + GPIO_GFN_RX2_A, + GPIO_GFN_TX2_A, + GPIO_GFN_SCK2, + GPIO_GFN_RTS1x_TANS, + GPIO_GFN_CTS1x, + GPIO_GFN_TX1_A, + GPIO_GFN_RX1_A, + GPIO_GFN_RTS0x_TANS, + GPIO_GFN_CTS0x, + GPIO_GFN_TX0, + GPIO_GFN_RX0, + GPIO_GFN_SCK0, + + /* GPSR6 */ + GPIO_GFN_GP6_31, + GPIO_GFN_GP6_30, + GPIO_GFN_USB30_OVC, + GPIO_GFN_USB30_PWEN, + GPIO_GFN_USB1_OVC, + GPIO_GFN_USB1_PWEN, + GPIO_GFN_USB0_OVC, + GPIO_GFN_USB0_PWEN, + GPIO_GFN_AUDIO_CLKB_B, + GPIO_GFN_AUDIO_CLKA_A, + GPIO_GFN_SSI_SDATA9_A, + GPIO_GFN_SSI_SDATA8, + GPIO_GFN_SSI_SDATA7, + GPIO_GFN_SSI_WS78, + GPIO_GFN_SSI_SCK78, + GPIO_GFN_SSI_SDATA6, + GPIO_GFN_SSI_WS6, + GPIO_GFN_SSI_SCK6, + GPIO_FN_SSI_SDATA5, + GPIO_FN_SSI_WS5, + GPIO_FN_SSI_SCK5, + GPIO_GFN_SSI_SDATA4, + GPIO_GFN_SSI_WS4, + GPIO_GFN_SSI_SCK4, + GPIO_GFN_SSI_SDATA3, + GPIO_GFN_SSI_WS34, + GPIO_GFN_SSI_SCK34, + GPIO_GFN_SSI_SDATA2_A, + GPIO_GFN_SSI_SDATA1_A, + GPIO_GFN_SSI_SDATA0, + GPIO_GFN_SSI_WS01239, + GPIO_GFN_SSI_SCK01239, + + /* GPSR7 */ + GPIO_FN_HDMI1_CEC, + GPIO_FN_HDMI0_CEC, + GPIO_FN_AVS2, + GPIO_FN_AVS1, + + /* IPSR0 */ + GPIO_IFN_AVB_MDC, + GPIO_FN_MSIOF2_SS2_C, + GPIO_IFN_AVB_MAGIC, + GPIO_FN_MSIOF2_SS1_C, + GPIO_FN_SCK4_A, + GPIO_IFN_AVB_PHY_INT, + GPIO_FN_MSIOF2_SYNC_C, + GPIO_FN_RX4_A, + GPIO_IFN_AVB_LINK, + GPIO_FN_MSIOF2_SCK_C, + GPIO_FN_TX4_A, + GPIO_IFN_AVB_AVTP_MATCH_A, + GPIO_FN_MSIOF2_RXD_C, + GPIO_FN_CTS4x_A, + GPIO_IFN_AVB_AVTP_CAPTURE_A, + GPIO_FN_MSIOF2_TXD_C, + GPIO_FN_RTS4x_TANS_A, + GPIO_IFN_IRQ0, + GPIO_FN_QPOLB, + GPIO_FN_DU_CDE, + GPIO_FN_VI4_DATA0_B, + GPIO_FN_CAN0_TX_B, + GPIO_FN_CANFD0_TX_B, + GPIO_FN_MSIOF3_SS2_E, + GPIO_IFN_IRQ1, + GPIO_FN_QPOLA, + GPIO_FN_DU_DISP, + GPIO_FN_VI4_DATA1_B, + GPIO_FN_CAN0_RX_B, + GPIO_FN_CANFD0_RX_B, + GPIO_FN_MSIOF3_SS1_E, + + /* IPSR1 */ + GPIO_IFN_IRQ2, + GPIO_FN_QCPV_QDE, + GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE, + GPIO_FN_VI4_DATA2_B, + GPIO_FN_MSIOF3_SYNC_E, + GPIO_FN_PWM3_B, + GPIO_IFN_IRQ3, + GPIO_FN_QSTVB_QVE, + GPIO_FN_DU_DOTCLKOUT1, + GPIO_FN_VI4_DATA3_B, + GPIO_FN_MSIOF3_SCK_E, + GPIO_FN_PWM4_B, + GPIO_IFN_IRQ4, + GPIO_FN_QSTH_QHS, + GPIO_FN_DU_EXHSYNC_DU_HSYNC, + GPIO_FN_VI4_DATA4_B, + GPIO_FN_MSIOF3_RXD_E, + GPIO_FN_PWM5_B, + GPIO_IFN_IRQ5, + GPIO_FN_QSTB_QHE, + GPIO_FN_DU_EXVSYNC_DU_VSYNC, + GPIO_FN_VI4_DATA5_B, + GPIO_FN_MSIOF3_TXD_E, + GPIO_FN_PWM6_B, + GPIO_IFN_PWM0, + GPIO_FN_AVB_AVTP_PPS, + GPIO_FN_VI4_DATA6_B, + GPIO_FN_IECLK_B, + GPIO_IFN_PWM1_A, + GPIO_FN_HRX3_D, + GPIO_FN_VI4_DATA7_B, + GPIO_FN_IERX_B, + GPIO_IFN_PWM2_A, + GPIO_FN_PWMFSW0, + GPIO_FN_HTX3_D, + GPIO_FN_IETX_B, + GPIO_IFN_A0, + GPIO_FN_LCDOUT16, + GPIO_FN_MSIOF3_SYNC_B, + GPIO_FN_VI4_DATA8, + GPIO_FN_DU_DB0, + GPIO_FN_PWM3_A, + + /* IPSR2 */ + GPIO_IFN_A1, + GPIO_FN_LCDOUT17, + GPIO_FN_MSIOF3_TXD_B, + GPIO_FN_VI4_DATA9, + GPIO_FN_DU_DB1, + GPIO_FN_PWM4_A, + GPIO_IFN_A2, + GPIO_FN_LCDOUT18, + GPIO_FN_MSIOF3_SCK_B, + GPIO_FN_VI4_DATA10, + GPIO_FN_DU_DB2, + GPIO_FN_PWM5_A, + GPIO_IFN_A3, + GPIO_FN_LCDOUT19, + GPIO_FN_MSIOF3_RXD_B, + GPIO_FN_VI4_DATA11, + GPIO_FN_DU_DB3, + GPIO_FN_PWM6_A, + GPIO_IFN_A4, + GPIO_FN_LCDOUT20, + GPIO_FN_MSIOF3_SS1_B, + GPIO_FN_VI4_DATA12, + GPIO_FN_VI5_DATA12, + GPIO_FN_DU_DB4, + GPIO_IFN_A5, + GPIO_FN_LCDOUT21, + GPIO_FN_MSIOF3_SS2_B, + GPIO_FN_SCK4_B, + GPIO_FN_VI4_DATA13, + GPIO_FN_VI5_DATA13, + GPIO_FN_DU_DB5, + GPIO_IFN_A6, + GPIO_FN_LCDOUT22, + GPIO_FN_MSIOF2_SS1_A, + GPIO_FN_RX4_B, + GPIO_FN_VI4_DATA14, + GPIO_FN_VI5_DATA14, + GPIO_FN_DU_DB6, + GPIO_IFN_A7, + GPIO_FN_LCDOUT23, + GPIO_FN_MSIOF2_SS2_A, + GPIO_FN_TX4_B, + GPIO_FN_VI4_DATA15, + GPIO_FN_V15_DATA15, + GPIO_FN_DU_DB7, + GPIO_IFN_A8, + GPIO_FN_RX3_B, + GPIO_FN_MSIOF2_SYNC_A, + GPIO_FN_HRX4_B, + GPIO_FN_SDA6_A, + GPIO_FN_AVB_AVTP_MATCH_B, + GPIO_FN_PWM1_B, + + /* IPSR3 */ + GPIO_IFN_A9, + GPIO_FN_MSIOF2_SCK_A, + GPIO_FN_CTS4x_B, + GPIO_FN_VI5_VSYNCx, + GPIO_IFN_A10, + GPIO_FN_MSIOF2_RXD_A, + GPIO_FN_RTS4n_TANS_B, + GPIO_FN_VI5_HSYNCx, + GPIO_IFN_A11, + GPIO_FN_TX3_B, + GPIO_FN_MSIOF2_TXD_A, + GPIO_FN_HTX4_B, + GPIO_FN_HSCK4, + GPIO_FN_VI5_FIELD, + GPIO_FN_SCL6_A, + GPIO_FN_AVB_AVTP_CAPTURE_B, + GPIO_FN_PWM2_B, + GPIO_FN_SPV_EVEN, + GPIO_IFN_A12, + GPIO_FN_LCDOUT12, + GPIO_FN_MSIOF3_SCK_C, + GPIO_FN_HRX4_A, + GPIO_FN_VI5_DATA8, + GPIO_FN_DU_DG4, + GPIO_IFN_A13, + GPIO_FN_LCDOUT13, + GPIO_FN_MSIOF3_SYNC_C, + GPIO_FN_HTX4_A, + GPIO_FN_VI5_DATA9, + GPIO_FN_DU_DG5, + GPIO_IFN_A14, + GPIO_FN_LCDOUT14, + GPIO_FN_MSIOF3_RXD_C, + GPIO_FN_HCTS4x, + GPIO_FN_VI5_DATA10, + GPIO_FN_DU_DG6, + GPIO_IFN_A15, + GPIO_FN_LCDOUT15, + GPIO_FN_MSIOF3_TXD_C, + GPIO_FN_HRTS4x, + GPIO_FN_VI5_DATA11, + GPIO_FN_DU_DG7, + GPIO_IFN_A16, + GPIO_FN_LCDOUT8, + GPIO_FN_VI4_FIELD, + GPIO_FN_DU_DG0, + + /* IPSR4 */ + GPIO_IFN_A17, + GPIO_FN_LCDOUT9, + GPIO_FN_VI4_VSYNCx, + GPIO_FN_DU_DG1, + GPIO_IFN_A18, + GPIO_FN_LCDOUT10, + GPIO_FN_VI4_HSYNCx, + GPIO_FN_DU_DG2, + GPIO_IFN_A19, + GPIO_FN_LCDOUT11, + GPIO_FN_VI4_CLKENB, + GPIO_FN_DU_DG3, + GPIO_IFN_CS0x, + GPIO_FN_VI5_CLKENB, + GPIO_IFN_CS1x_A26, + GPIO_FN_VI5_CLK, + GPIO_FN_EX_WAIT0_B, + GPIO_IFN_BSx, + GPIO_FN_QSTVA_QVS, + GPIO_FN_MSIOF3_SCK_D, + GPIO_FN_SCK3, + GPIO_FN_HSCK3, + GPIO_FN_CAN1_TX, + GPIO_FN_CANFD1_TX, + GPIO_FN_IETX_A, + GPIO_IFN_RDx, + GPIO_FN_MSIOF3_SYNC_D, + GPIO_FN_RX3_A, + GPIO_FN_HRX3_A, + GPIO_FN_CAN0_TX_A, + GPIO_FN_CANFD0_TX_A, + GPIO_IFN_RD_WRx, + GPIO_FN_MSIOF3_RXD_D, + GPIO_FN_TX3_A, + GPIO_FN_HTX3_A, + GPIO_FN_CAN0_RX_A, + GPIO_FN_CANFD0_RX_A, + + /* IPSR5 */ + GPIO_IFN_WE0x, + GPIO_FN_MSIIOF3_TXD_D, + GPIO_FN_CTS3x, + GPIO_FN_HCTS3x, + GPIO_FN_SCL6_B, + GPIO_FN_CAN_CLK, + GPIO_FN_IECLK_A, + GPIO_IFN_WE1x, + GPIO_FN_MSIOF3_SS1_D, + GPIO_FN_RTS3x_TANS, + GPIO_FN_HRTS3x, + GPIO_FN_SDA6_B, + GPIO_FN_CAN1_RX, + GPIO_FN_CANFD1_RX, + GPIO_FN_IERX_A, + GPIO_IFN_EX_WAIT0_A, + GPIO_FN_QCLK, + GPIO_FN_VI4_CLK, + GPIO_FN_DU_DOTCLKOUT0, + GPIO_IFN_D0, + GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_MSIOF3_SCK_A, + GPIO_FN_VI4_DATA16, + GPIO_FN_VI5_DATA0, + GPIO_IFN_D1, + GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_MSIOF3_SYNC_A, + GPIO_FN_VI4_DATA17, + GPIO_FN_VI5_DATA1, + GPIO_IFN_D2, + GPIO_FN_MSIOF3_RXD_A, + GPIO_FN_VI4_DATA18, + GPIO_FN_VI5_DATA2, + GPIO_IFN_D3, + GPIO_FN_MSIOF3_TXD_A, + GPIO_FN_VI4_DATA19, + GPIO_FN_VI5_DATA3, + GPIO_IFN_D4, + GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_VI4_DATA20, + GPIO_FN_VI5_DATA4, + + /* IPSR6 */ + GPIO_IFN_D5, + GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_VI4_DATA21, + GPIO_FN_VI5_DATA5, + GPIO_IFN_D6, + GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_VI4_DATA22, + GPIO_FN_VI5_DATA6, + GPIO_IFN_D7, + GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_VI4_DATA23, + GPIO_FN_VI5_DATA7, + GPIO_IFN_D8, + GPIO_FN_LCDOUT0, + GPIO_FN_MSIOF2_SCK_D, + GPIO_FN_SCK4_C, + GPIO_FN_VI4_DATA0_A, + GPIO_FN_DU_DR0, + GPIO_IFN_D9, + GPIO_FN_LCDOUT1, + GPIO_FN_MSIOF2_SYNC_D, + GPIO_FN_VI4_DATA1_A, + GPIO_FN_DU_DR1, + GPIO_IFN_D10, + GPIO_FN_LCDOUT2, + GPIO_FN_MSIOF2_RXD_D, + GPIO_FN_HRX3_B, + GPIO_FN_VI4_DATA2_A, + GPIO_FN_CTS4x_C, + GPIO_FN_DU_DR2, + GPIO_IFN_D11, + GPIO_FN_LCDOUT3, + GPIO_FN_MSIOF2_TXD_D, + GPIO_FN_HTX3_B, + GPIO_FN_VI4_DATA3_A, + GPIO_FN_RTS4x_TANS_C, + GPIO_FN_DU_DR3, + GPIO_IFN_D12, + GPIO_FN_LCDOUT4, + GPIO_FN_MSIOF2_SS1_D, + GPIO_FN_RX4_C, + GPIO_FN_VI4_DATA4_A, + GPIO_FN_DU_DR4, + + /* IPSR7 */ + GPIO_IFN_D13, + GPIO_FN_LCDOUT5, + GPIO_FN_MSIOF2_SS2_D, + GPIO_FN_TX4_C, + GPIO_FN_VI4_DATA5_A, + GPIO_FN_DU_DR5, + GPIO_IFN_D14, + GPIO_FN_LCDOUT6, + GPIO_FN_MSIOF3_SS1_A, + GPIO_FN_HRX3_C, + GPIO_FN_VI4_DATA6_A, + GPIO_FN_DU_DR6, + GPIO_FN_SCL6_C, + GPIO_IFN_D15, + GPIO_FN_LCDOUT7, + GPIO_FN_MSIOF3_SS2_A, + GPIO_FN_HTX3_C, + GPIO_FN_VI4_DATA7_A, + GPIO_FN_DU_DR7, + GPIO_FN_SDA6_C, + GPIO_FN_FSCLKST, + GPIO_IFN_SD0_CLK, + GPIO_FN_MSIOF1_SCK_E, + GPIO_FN_STP_OPWM_0_B, + GPIO_IFN_SD0_CMD, + GPIO_FN_MSIOF1_SYNC_E, + GPIO_FN_STP_IVCXO27_0_B, + GPIO_IFN_SD0_DAT0, + GPIO_FN_MSIOF1_RXD_E, + GPIO_FN_TS_SCK0_B, + GPIO_FN_STP_ISCLK_0_B, + GPIO_IFN_SD0_DAT1, + GPIO_FN_MSIOF1_TXD_E, + GPIO_FN_TS_SPSYNC0_B, + GPIO_FN_STP_ISSYNC_0_B, + + /* IPSR8 */ + GPIO_IFN_SD0_DAT2, + GPIO_FN_MSIOF1_SS1_E, + GPIO_FN_TS_SDAT0_B, + GPIO_FN_STP_ISD_0_B, + + GPIO_IFN_SD0_DAT3, + GPIO_FN_MSIOF1_SS2_E, + GPIO_FN_TS_SDEN0_B, + GPIO_FN_STP_ISEN_0_B, + + GPIO_IFN_SD1_CLK, + GPIO_FN_MSIOF1_SCK_G, + GPIO_FN_SIM0_CLK_A, + + GPIO_IFN_SD1_CMD, + GPIO_FN_MSIOF1_SYNC_G, + GPIO_FN_NFCEx_B, + GPIO_FN_SIM0_D_A, + GPIO_FN_STP_IVCXO27_1_B, + + GPIO_IFN_SD1_DAT0, + GPIO_FN_SD2_DAT4, + GPIO_FN_MSIOF1_RXD_G, + GPIO_FN_NFWPx_B, + GPIO_FN_TS_SCK1_B, + GPIO_FN_STP_ISCLK_1_B, + + GPIO_IFN_SD1_DAT1, + GPIO_FN_SD2_DAT5, + GPIO_FN_MSIOF1_TXD_G, + GPIO_FN_NFDATA14_B, + GPIO_FN_TS_SPSYNC1_B, + GPIO_FN_STP_ISSYNC_1_B, + + GPIO_IFN_SD1_DAT2, + GPIO_FN_SD2_DAT6, + GPIO_FN_MSIOF1_SS1_G, + GPIO_FN_NFDATA15_B, + GPIO_FN_TS_SDAT1_B, + GPIO_FN_STP_IOD_1_B, + + GPIO_IFN_SD1_DAT3, + GPIO_FN_SD2_DAT7, + GPIO_FN_MSIOF1_SS2_G, + GPIO_FN_NFRBx_B, + GPIO_FN_TS_SDEN1_B, + GPIO_FN_STP_ISEN_1_B, + + /* IPSR9 */ + GPIO_IFN_SD2_CLK, + GPIO_FN_NFDATA8, + + GPIO_IFN_SD2_CMD, + GPIO_FN_NFDATA9, + + GPIO_IFN_SD2_DAT0, + GPIO_FN_NFDATA10, + + GPIO_IFN_SD2_DAT1, + GPIO_FN_NFDATA11, + + GPIO_IFN_SD2_DAT2, + GPIO_FN_NFDATA12, + + GPIO_IFN_SD2_DAT3, + GPIO_FN_NFDATA13, + + GPIO_IFN_SD2_DS, + GPIO_FN_NFALE, + + GPIO_IFN_SD3_CLK, + GPIO_FN_NFWEx, + + /* IPSR10 */ + GPIO_IFN_SD3_CMD, + GPIO_FN_NFREx, + + GPIO_IFN_SD3_DAT0, + GPIO_FN_NFDATA0, + + GPIO_IFN_SD3_DAT1, + GPIO_FN_NFDATA1, + + GPIO_IFN_SD3_DAT2, + GPIO_FN_NFDATA2, + + GPIO_IFN_SD3_DAT3, + GPIO_FN_NFDATA3, + + GPIO_IFN_SD3_DAT4, + GPIO_FN_SD2_CD_A, + GPIO_FN_NFDATA4, + + GPIO_IFN_SD3_DAT5, + GPIO_FN_SD2_WP_A, + GPIO_FN_NFDATA5, + + GPIO_IFN_SD3_DAT6, + GPIO_FN_SD3_CD, + GPIO_FN_NFDATA6, + + /* IPSR11 */ + GPIO_IFN_SD3_DAT7, + GPIO_FN_SD3_WP, + GPIO_FN_NFDATA7, + + GPIO_IFN_SD3_DS, + GPIO_FN_NFCLE, + + GPIO_IFN_SD0_CD, + GPIO_FN_NFDATA14_A, + GPIO_FN_SCL2_B, + GPIO_FN_SIM0_RST_A, + + GPIO_IFN_SD0_WP, + GPIO_FN_NFDATA15_A, + GPIO_FN_SDA2_B, + + GPIO_IFN_SD1_CD, + GPIO_FN_NFRBx_A, + GPIO_FN_SIM0_CLK_B, + + GPIO_IFN_SD1_WP, + GPIO_FN_NFCEx_A, + GPIO_FN_SIM0_D_B, + + GPIO_IFN_SCK0, + GPIO_FN_HSCK1_B, + GPIO_FN_MSIOF1_SS2_B, + GPIO_FN_AUDIO_CLKC_B, + GPIO_FN_SDA2_A, + GPIO_FN_SIM0_RST_B, + GPIO_FN_STP_OPWM_0_C, + GPIO_FN_RIF0_CLK_B, + GPIO_FN_ADICHS2, + GPIO_FN_SCK5_B, + + GPIO_IFN_RX0, + GPIO_FN_HRX1_B, + GPIO_FN_TS_SCK0_C, + GPIO_FN_STP_ISCLK_0_C, + GPIO_FN_RIF0_D0_B, + + /* IPSR12 */ + GPIO_IFN_TX0, + GPIO_FN_HTX1_B, + GPIO_FN_TS_SPSYNC0_C, + GPIO_FN_STP_ISSYNC_0_C, + GPIO_FN_RIF0_D1_B, + + GPIO_IFN_CTS0x, + GPIO_FN_HCTS1x_B, + GPIO_FN_MSIOF1_SYNC_B, + GPIO_FN_TS_SPSYNC1_C, + GPIO_FN_STP_ISSYNC_1_C, + GPIO_FN_RIF1_SYNC_B, + GPIO_FN_AUDIO_CLKOUT_C, + GPIO_FN_ADICS_SAMP, + + GPIO_IFN_RTS0x_TANS, + GPIO_FN_HRTS1x_B, + GPIO_FN_MSIOF1_SS1_B, + GPIO_FN_AUDIO_CLKA_B, + GPIO_FN_SCL2_A, + GPIO_FN_STP_IVCXO27_1_C, + GPIO_FN_RIF0_SYNC_B, + GPIO_FN_ADICHS1, + + GPIO_IFN_RX1_A, + GPIO_FN_HRX1_A, + GPIO_FN_TS_SDAT0_C, + GPIO_FN_STP_ISD_0_C, + GPIO_FN_RIF1_CLK_C, + + GPIO_IFN_TX1_A, + GPIO_FN_HTX1_A, + GPIO_FN_TS_SDEN0_C, + GPIO_FN_STP_ISEN_0_C, + GPIO_FN_RIF1_D0_C, + + GPIO_IFN_CTS1x, + GPIO_FN_HCTS1x_A, + GPIO_FN_MSIOF1_RXD_B, + GPIO_FN_TS_SDEN1_C, + GPIO_FN_STP_ISEN_1_C, + GPIO_FN_RIF1_D0_B, + GPIO_FN_ADIDATA, + + GPIO_IFN_RTS1x_TANS, + GPIO_FN_HRTS1x_A, + GPIO_FN_MSIOF1_TXD_B, + GPIO_FN_TS_SDAT1_C, + GPIO_FN_STP_ISD_1_C, + GPIO_FN_RIF1_D1_B, + GPIO_FN_ADICHS0, + + GPIO_IFN_SCK2, + GPIO_FN_SCIF_CLK_B, + GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_TS_SCK1_C, + GPIO_FN_STP_ISCLK_1_C, + GPIO_FN_RIF1_CLK_B, + GPIO_FN_ADICLK, + + /* IPSR13 */ + GPIO_IFN_TX2_A, + GPIO_FN_SD2_CD_B, + GPIO_FN_SCL1_A, + GPIO_FN_FMCLK_A, + GPIO_FN_RIF1_D1_C, + GPIO_FN_FSO_CFE_0_B, + + GPIO_IFN_RX2_A, + GPIO_FN_SD2_WP_B, + GPIO_FN_SDA1_A, + GPIO_FN_FMIN_A, + GPIO_FN_RIF1_SYNC_C, + GPIO_FN_FSO_CEF_1_B, + + GPIO_IFN_HSCK0, + GPIO_FN_MSIOF1_SCK_D, + GPIO_FN_AUDIO_CLKB_A, + GPIO_FN_SSI_SDATA1_B, + GPIO_FN_TS_SCK0_D, + GPIO_FN_STP_ISCLK_0_D, + GPIO_FN_RIF0_CLK_C, + GPIO_FN_RX5_B, + + GPIO_IFN_HRX0, + GPIO_FN_MSIOF1_RXD_D, + GPIO_FN_SS1_SDATA2_B, + GPIO_FN_TS_SDEN0_D, + GPIO_FN_STP_ISEN_0_D, + GPIO_FN_RIF0_D0_C, + + GPIO_IFN_HTX0, + GPIO_FN_MSIOF1_TXD_D, + GPIO_FN_SSI_SDATA9_B, + GPIO_FN_TS_SDAT0_D, + GPIO_FN_STP_ISD_0_D, + GPIO_FN_RIF0_D1_C, + + GPIO_IFN_HCTS0x, + GPIO_FN_RX2_B, + GPIO_FN_MSIOF1_SYNC_D, + GPIO_FN_SSI_SCK9_A, + GPIO_FN_TS_SPSYNC0_D, + GPIO_FN_STP_ISSYNC_0_D, + GPIO_FN_RIF0_SYNC_C, + GPIO_FN_AUDIO_CLKOUT1_A, + + GPIO_IFN_HRTS0x, + GPIO_FN_TX2_B, + GPIO_FN_MSIOF1_SS1_D, + GPIO_FN_SSI_WS9_A, + GPIO_FN_STP_IVCXO27_0_D, + GPIO_FN_BPFCLK_A, + GPIO_FN_AUDIO_CLKOUT2_A, + + GPIO_IFN_MSIOF0_SYNC, + GPIO_FN_AUDIO_CLKOUT_A, + GPIO_FN_TX5_B, + GPIO_FN_BPFCLK_D, + + /* IPSR14 */ + GPIO_IFN_MSIOF0_SS1, + GPIO_FN_RX5_A, + GPIO_FN_NFWPx_A, + GPIO_FN_AUDIO_CLKA_C, + GPIO_FN_SSI_SCK2_A, + GPIO_FN_STP_IVCXO27_0_C, + GPIO_FN_AUDIO_CLKOUT3_A, + GPIO_FN_TCLK1_B, + + GPIO_IFN_MSIOF0_SS2, + GPIO_FN_TX5_A, + GPIO_FN_MSIOF1_SS2_D, + GPIO_FN_AUDIO_CLKC_A, + GPIO_FN_SSI_WS2_A, + GPIO_FN_STP_OPWM_0_D, + GPIO_FN_AUDIO_CLKOUT_D, + GPIO_FN_SPEEDIN_B, + + GPIO_IFN_MLB_CLK, + GPIO_FN_MSIOF1_SCK_F, + GPIO_FN_SCL1_B, + + GPIO_IFN_MLB_SIG, + GPIO_FN_RX1_B, + GPIO_FN_MSIOF1_SYNC_F, + GPIO_FN_SDA1_B, + + GPIO_IFN_MLB_DAT, + GPIO_FN_TX1_B, + GPIO_FN_MSIOF1_RXD_F, + + GPIO_IFN_SSI_SCK0129, + GPIO_FN_MSIOF1_TXD_F, + GPIO_FN_MOUT0, + + GPIO_IFN_SSI_WS0129, + GPIO_FN_MSIOF1_SS1_F, + GPIO_FN_MOUT1, + + GPIO_IFN_SSI_SDATA0, + GPIO_FN_MSIOF1_SS2_F, + GPIO_FN_MOUT2, + + /* IPSR15 */ + GPIO_IFN_SSI_SDATA1_A, + GPIO_FN_MOUT5, + + GPIO_IFN_SSI_SDATA2_A, + GPIO_FN_SSI_SCK1_B, + GPIO_FN_MOUT6, + + GPIO_IFN_SSI_SCK34, + GPIO_FN_MSIOF1_SS1_A, + GPIO_FN_STP_OPWM_0_A, + + GPIO_IFN_SSI_WS34, + GPIO_FN_HCTS2x_A, + GPIO_FN_MSIOF1_SS2_A, + GPIO_FN_STP_IVCXO27_0_A, + + GPIO_IFN_SSI_SDATA3, + GPIO_FN_HRTS2x_A, + GPIO_FN_MSIOF1_TXD_A, + GPIO_FN_TS_SCK0_A, + GPIO_FN_STP_ISCLK_0_A, + GPIO_FN_RIF0_D1_A, + GPIO_FN_RIF2_D0_A, + + GPIO_IFN_SSI_SCK4, + GPIO_FN_HRX2_A, + GPIO_FN_MSIOF1_SCK_A, + GPIO_FN_TS_SDAT0_A, + GPIO_FN_STP_ISD_0_A, + GPIO_FN_RIF0_CLK_A, + GPIO_FN_RIF2_CLK_A, + + GPIO_IFN_SSI_WS4, + GPIO_FN_HTX2_A, + GPIO_FN_MSIOF1_SYNC_A, + GPIO_FN_TS_SDEN0_A, + GPIO_FN_STP_ISEN_0_A, + GPIO_FN_RIF0_SYNC_A, + GPIO_FN_RIF2_SYNC_A, + + GPIO_IFN_SSI_SDATA4, + GPIO_FN_HSCK2_A, + GPIO_FN_MSIOF1_RXD_A, + GPIO_FN_TS_SPSYNC0_A, + GPIO_FN_STP_ISSYNC_0_A, + GPIO_FN_RIF0_D0_A, + GPIO_FN_RIF2_D1_A, + + /* IPSR16 */ + GPIO_IFN_SSI_SCK6, + GPIO_FN_SIM0_RST_D, + GPIO_FN_FSO_TOE_A, + + GPIO_IFN_SSI_WS6, + GPIO_FN_SIM0_D_D, + + GPIO_IFN_SSI_SDATA6, + GPIO_FN_SIM0_CLK_D, + + GPIO_IFN_SSI_SCK78, + GPIO_FN_HRX2_B, + GPIO_FN_MSIOF1_SCK_C, + GPIO_FN_TS_SCK1_A, + GPIO_FN_STP_ISCLK_1_A, + GPIO_FN_RIF1_CLK_A, + GPIO_FN_RIF3_CLK_A, + + GPIO_IFN_SSI_WS78, + GPIO_FN_HTX2_B, + GPIO_FN_MSIOF1_SYNC_C, + GPIO_FN_TS_SDAT1_A, + GPIO_FN_STP_ISD_1_A, + GPIO_FN_RIF1_SYNC_A, + GPIO_FN_RIF3_SYNC_A, + + GPIO_IFN_SSI_SDATA7, + GPIO_FN_HCTS2x_B, + GPIO_FN_MSIOF1_RXD_C, + GPIO_FN_TS_SDEN1_A, + GPIO_FN_STP_IEN_1_A, + GPIO_FN_RIF1_D0_A, + GPIO_FN_RIF3_D0_A, + GPIO_FN_TCLK2_A, + + GPIO_IFN_SSI_SDATA8, + GPIO_FN_HRTS2x_B, + GPIO_FN_MSIOF1_TXD_C, + GPIO_FN_TS_SPSYNC1_A, + GPIO_FN_STP_ISSYNC_1_A, + GPIO_FN_RIF1_D1_A, + GPIO_FN_EIF3_D1_A, + + GPIO_IFN_SSI_SDATA9_A, + GPIO_FN_HSCK2_B, + GPIO_FN_MSIOF1_SS1_C, + GPIO_FN_HSCK1_A, + GPIO_FN_SSI_WS1_B, + GPIO_FN_SCK1, + GPIO_FN_STP_IVCXO27_1_A, + GPIO_FN_SCK5, + + /* IPSR17 */ + GPIO_IFN_AUDIO_CLKA_A, + GPIO_FN_CC5_OSCOUT, + + GPIO_IFN_AUDIO_CLKB_B, + GPIO_FN_SCIF_CLK_A, + GPIO_FN_STP_IVCXO27_1_D, + GPIO_FN_REMOCON_A, + GPIO_FN_TCLK1_A, + + GPIO_IFN_USB0_PWEN, + GPIO_FN_SIM0_RST_C, + GPIO_FN_TS_SCK1_D, + GPIO_FN_STP_ISCLK_1_D, + GPIO_FN_BPFCLK_B, + GPIO_FN_RIF3_CLK_B, + GPIO_FN_FSO_CFE_1_A, + GPIO_FN_HSCK2_C, + + GPIO_IFN_USB0_OVC, + GPIO_FN_SIM0_D_C, + GPIO_FN_TS_SDAT1_D, + GPIO_FN_STP_ISD_1_D, + GPIO_FN_RIF3_SYNC_B, + GPIO_FN_HRX2_C, + + GPIO_IFN_USB1_PWEN, + GPIO_FN_SIM0_CLK_C, + GPIO_FN_SSI_SCK1_A, + GPIO_FN_TS_SCK0_E, + GPIO_FN_STP_ISCLK_0_E, + GPIO_FN_FMCLK_B, + GPIO_FN_RIF2_CLK_B, + GPIO_FN_SPEEDIN_A, + GPIO_FN_HTX2_C, + + GPIO_IFN_USB1_OVC, + GPIO_FN_MSIOF1_SS2_C, + GPIO_FN_SSI_WS1_A, + GPIO_FN_TS_SDAT0_E, + GPIO_FN_STP_ISD_0_E, + GPIO_FN_FMIN_B, + GPIO_FN_RIF2_SYNC_B, + GPIO_FN_REMOCON_B, + GPIO_FN_HCTS2x_C, + + GPIO_IFN_USB30_PWEN, + GPIO_FN_AUDIO_CLKOUT_B, + GPIO_FN_SSI_SCK2_B, + GPIO_FN_TS_SDEN1_D, + GPIO_FN_STP_ISEN_1_D, + GPIO_FN_STP_OPWM_0_E, + GPIO_FN_RIF3_D0_B, + GPIO_FN_TCLK2_B, + GPIO_FN_TPU0TO0, + GPIO_FN_BPFCLK_C, + GPIO_FN_HRTS2x_C, + + GPIO_IFN_USB30_OVC, + GPIO_FN_AUDIO_CLKOUT1_B, + GPIO_FN_SSI_WS2_B, + GPIO_FN_TS_SPSYNC1_D, + GPIO_FN_STP_ISSYNC_1_D, + GPIO_FN_STP_IVCXO27_0_E, + GPIO_FN_RIF3_D1_B, + GPIO_FN_FSO_TOE_B, + GPIO_FN_TPU0TO1, + + /* IPSR18 */ + GPIO_IFN_GP6_30, + GPIO_FN_AUDIO_CLKOUT2_B, + GPIO_FN_SSI_SCK9_B, + GPIO_FN_TS_SDEN0_E, + GPIO_FN_STP_ISEN_0_E, + GPIO_FN_RIF2_D0_B, + GPIO_FN_FSO_CFE_0_A, + GPIO_FN_TPU0TO2, + GPIO_FN_FMCLK_C, + GPIO_FN_FMCLK_D, + + GPIO_IFN_GP6_31, + GPIO_FN_AUDIO_CLKOUT3_B, + GPIO_FN_SSI_WS9_B, + GPIO_FN_TS_SPSYNC0_E, + GPIO_FN_STP_ISSYNC_0_E, + GPIO_FN_RIF2_D1_B, + GPIO_FN_TPU0TO3, + GPIO_FN_FMIN_C, + GPIO_FN_FMIN_D, + +}; + +#endif /* __ASM_R8A7796_GPIO_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7796.h b/arch/arm/mach-rmobile/include/mach/r8a7796.h new file mode 100644 index 0000000000..dab6082012 --- /dev/null +++ b/arch/arm/mach-rmobile/include/mach/r8a7796.h @@ -0,0 +1,36 @@ +/* + * arch/arm/include/asm/arch-rcar_gen3/r8a7796.h + * This file defines registers and value for r8a7796. + * + * Copyright (C) 2016 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_R8A7796_H +#define __ASM_ARCH_R8A7796_H + +#include "rcar-gen3-base.h" + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00200000 +#define MSTP1_BITS 0xFFFFFFFF +#define MSTP2_BITS 0x340E2FDC +#define MSTP3_BITS 0xFFFFFFDF +#define MSTP4_BITS 0x80000184 +#define MSTP5_BITS 0xC3FFFFFF +#define MSTP6_BITS 0xFFFFFFFF +#define MSTP7_BITS 0xFFFFFFFF +#define MSTP8_BITS 0x01F1FFF7 +#define MSTP9_BITS 0xFFFFFFFE +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000000B7 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ +#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* either MMC1 */ +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 + +#endif /* __ASM_ARCH_R8A7796_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h index fbd87c4a01..c197642fe4 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -79,6 +79,9 @@ #define PUEN_USB1_OVC (1 << 2) #define PUEN_USB1_PWEN (1 << 1) +/* IICDVFS (I2C) */ +#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 + #ifndef __ASSEMBLY__ #include <asm/types.h> diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index 22d97b19ab..654349b0b3 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -18,6 +18,8 @@ #include <asm/arch/r8a7794.h> #elif defined(CONFIG_R8A7795) #include <asm/arch/r8a7795.h> +#elif defined(CONFIG_R8A7796) +#include <asm/arch/r8a7796.h> #else #error "SOC Name not defined" #endif diff --git a/arch/arm/mach-rmobile/memmap-r8a7796.c b/arch/arm/mach-rmobile/memmap-r8a7796.c new file mode 100644 index 0000000000..648743d51e --- /dev/null +++ b/arch/arm/mach-rmobile/memmap-r8a7796.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region r8a7796_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe0000000UL, + .phys = 0xe0000000UL, + .size = 0xe0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = r8a7796_mem_map; diff --git a/arch/arm/mach-rmobile/pfc-r8a7795.c b/arch/arm/mach-rmobile/pfc-r8a7795.c index 65d66a08e2..4446093973 100644 --- a/arch/arm/mach-rmobile/pfc-r8a7795.c +++ b/arch/arm/mach-rmobile/pfc-r8a7795.c @@ -2,7 +2,7 @@ * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c * This file is r8a7795 processor support - PFC hardware block. * - * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015-2016 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -24,6 +24,19 @@ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ PORT_10(fn, pfx##2, sfx) +#define CPU_32_PORT_29(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), \ + PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), \ + PORT_1(fn, pfx##25, sfx), \ + PORT_1(fn, pfx##26, sfx), \ + PORT_1(fn, pfx##27, sfx), \ + PORT_1(fn, pfx##28, sfx) + #define CPU_32_PORT_28(fn, pfx, sfx) \ PORT_10(fn, pfx, sfx), \ PORT_10(fn, pfx##1, sfx), \ @@ -91,7 +104,7 @@ GP5[26] - [31], GP7[4] - [31] */ -#define CPU_ALL_PORT(fn, pfx, sfx) \ +#define ES_CPU_ALL_PORT(fn, pfx, sfx) \ CPU_32_PORT_16(fn, pfx##_0_, sfx), \ CPU_32_PORT_28(fn, pfx##_1_, sfx), \ CPU_32_PORT_15(fn, pfx##_2_, sfx), \ @@ -101,6 +114,16 @@ CPU_32_PORT(fn, pfx##_6_, sfx), \ CPU_32_PORT_4(fn, pfx##_7_, sfx) +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT_16(fn, pfx##_0_, sfx), \ + CPU_32_PORT_29(fn, pfx##_1_, sfx), \ + CPU_32_PORT_15(fn, pfx##_2_, sfx), \ + CPU_32_PORT_16(fn, pfx##_3_, sfx), \ + CPU_32_PORT_18(fn, pfx##_4_, sfx), \ + CPU_32_PORT_26(fn, pfx##_5_, sfx), \ + CPU_32_PORT(fn, pfx##_6_, sfx), \ + CPU_32_PORT_4(fn, pfx##_7_, sfx) + #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ GP##pfx##_IN, GP##pfx##_OUT) @@ -169,6 +192,7 @@ enum { GFN_D0, /* GPSR1 */ + GFN_CLKOUT, GFN_EX_WAIT0_A, GFN_WE1x, GFN_WE0x, @@ -234,23 +258,23 @@ enum { GFN_SD0_CLK, /* GPSR4 */ - FN_SD3_DS, + GFN_SD3_DS, GFN_SD3_DAT7, GFN_SD3_DAT6, GFN_SD3_DAT5, GFN_SD3_DAT4, - FN_SD3_DAT3, - FN_SD3_DAT2, - FN_SD3_DAT1, - FN_SD3_DAT0, - FN_SD3_CMD, - FN_SD3_CLK, + GFN_SD3_DAT3, + GFN_SD3_DAT2, + GFN_SD3_DAT1, + GFN_SD3_DAT0, + GFN_SD3_CMD, + GFN_SD3_CLK, GFN_SD2_DS, GFN_SD2_DAT3, GFN_SD2_DAT2, GFN_SD2_DAT1, GFN_SD2_DAT0, - FN_SD2_CMD, + GFN_SD2_CMD, GFN_SD2_CLK, /* GPSR5 */ @@ -282,8 +306,8 @@ enum { GFN_SCK0, /* GPSR6 */ - GFN_USB31_OVC, - GFN_USB31_PWEN, + GFN_USB3_OVC, + GFN_USB3_PWEN, GFN_USB30_OVC, GFN_USB30_PWEN, GFN_USB1_OVC, @@ -312,8 +336,8 @@ enum { GFN_SSI_SDATA2_A, GFN_SSI_SDATA1_A, GFN_SSI_SDATA0, - GFN_SSI_WS0129, - GFN_SSI_SCK0129, + GFN_SSI_WS01239, + GFN_SSI_SCK01239, /* GPSR7 */ FN_HDMI1_CEC, @@ -325,7 +349,7 @@ enum { IFN_AVB_MDC, FN_MSIOF2_SS2_C, IFN_AVB_MAGIC, - FN_MSIOF2_S1_C, + FN_MSIOF2_SS1_C, FN_SCK4_A, IFN_AVB_PHY_INT, FN_MSIOF2_SYNC_C, @@ -336,6 +360,7 @@ enum { IFN_AVB_AVTP_MATCH_A, FN_MSIOF2_RXD_C, FN_CTS4x_A, + FN_FSCLKST2x_A, IFN_AVB_AVTP_CAPTURE_A, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, @@ -345,50 +370,50 @@ enum { FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, + FN_MSIOF3_SS2_E, IFN_IRQ1, FN_QPOLA, FN_DU_DISP, FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, + FN_MSIOF3_SS1_E, /* IPSR1 */ IFN_IRQ2, FN_QCPV_QDE, FN_DU_EXODDF_DU_ODDF_DISP_CDE, FN_VI4_DATA2_B, + FN_MSIOF3_SYNC_E, FN_PWM3_B, IFN_IRQ3, FN_QSTVB_QVE, - FN_A25, FN_DU_DOTCLKOUT1, FN_VI4_DATA3_B, + FN_MSIOF3_SCK_E, FN_PWM4_B, IFN_IRQ4, FN_QSTH_QHS, - FN_A24, FN_DU_EXHSYNC_DU_HSYNC, FN_VI4_DATA4_B, + FN_MSIOF3_RXD_E, FN_PWM5_B, IFN_IRQ5, FN_QSTB_QHE, - FN_A23, FN_DU_EXVSYNC_DU_VSYNC, FN_VI4_DATA5_B, + FN_FSCLKST2x_B, + FN_MSIOF3_TXD_E, FN_PWM6_B, IFN_PWM0, FN_AVB_AVTP_PPS, - FN_A22, FN_VI4_DATA6_B, FN_IECLK_B, IFN_PWM1_A, - FN_A21, FN_HRX3_D, FN_VI4_DATA7_B, FN_IERX_B, IFN_PWM2_A, - FN_PWMFSW0, - FN_A20, FN_HTX3_D, FN_IETX_B, IFN_A0, @@ -470,7 +495,6 @@ enum { FN_SCL6_A, FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, - FN_SPV_EVEN, IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, @@ -676,67 +700,94 @@ enum { IFN_SD1_CLK, FN_MSIOF1_SCK_G, FN_SIM0_CLK_A, - IFN_SD1_CMD, FN_MSIOF1_SYNC_G, + FN_NFCEx_B, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, + FN_NFWPx_B, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, + FN_NFDATA14_B, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, + FN_NFDATA15_B, FN_TS_SDAT1_B, FN_STP_IOD_1_B, IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, + FN_NFRBx_B, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, /* IPSR9 */ IFN_SD2_CLK, - FN_SCKZ_A, + FN_NFDATA8, + IFN_SD2_CMD, + FN_NFDATA9, IFN_SD2_DAT0, - FN_MTSx_A, + FN_NFDATA10, IFN_SD2_DAT1, - FN_STMx_A, + FN_NFDATA11, IFN_SD2_DAT2, - FN_MDATA_A, + FN_NFDATA12, IFN_SD2_DAT3, - FN_SDATA_A, + FN_NFDATA13, IFN_SD2_DS, + FN_NFALE, FN_SATA_DEVSLP_B, - FN_VSP_A, + IFN_SD3_CLK, + FN_NFWEx, + + /* IPSR10 */ + IFN_SD3_CMD, + FN_NFREx, + IFN_SD3_DAT0, + FN_NFDATA0, + IFN_SD3_DAT1, + FN_NFDATA1, + IFN_SD3_DAT2, + FN_NFDATA2, + IFN_SD3_DAT3, + FN_NFDATA3, IFN_SD3_DAT4, FN_SD2_CD_A, + FN_NFDATA4, IFN_SD3_DAT5, FN_SD2_WP_A, - - /* IPSR10 */ + FN_NFDATA5, IFN_SD3_DAT6, FN_SD3_CD, + FN_NFDATA6, + + /* IPSR11 */ IFN_SD3_DAT7, FN_SD3_WP, + FN_NFDATA7, + IFN_SD3_DS, + FN_NFCLE, IFN_SD0_CD, + FN_NFDATA14_A, FN_SCL2_B, FN_SIM0_RST_A, IFN_SD0_WP, + FN_NFDATA15_A, FN_SDA2_B, IFN_SD1_CD, + FN_NFRBx_A, FN_SIM0_CLK_B, IFN_SD1_WP, + FN_NFCEx_A, FN_SIM0_D_B, IFN_SCK0, FN_HSCK1_B, @@ -744,16 +795,17 @@ enum { FN_AUDIO_CLKC_B, FN_SDA2_A, FN_SIM0_RST_B, - FN_STP_OPWM__C, + FN_STP_OPWM_0_C, FN_RIF0_CLK_B, FN_ADICHS2, + FN_SCK5_B, IFN_RX0, FN_HRX1_B, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, - /* IPSR11 */ + /* IPSR12 */ IFN_TX0, FN_HTX1_B, FN_TS_SPSYNC0_C, @@ -778,7 +830,7 @@ enum { IFN_RX1_A, FN_HRX1_A, FN_TS_SDAT0_C, - FN_STP_IDS_0_C, + FN_STP_ISD_0_C, FN_RIF1_CLK_C, IFN_TX1_A, FN_HTX1_A, @@ -807,21 +859,19 @@ enum { FN_RIF1_CLK_B, FN_ADICLK, - /* IPSR12 */ + /* IPSR13 */ IFN_TX2_A, FN_SD2_CD_B, FN_SCL1_A, - FN_RSD_CLK_B, FN_FMCLK_A, FN_RIF1_D1_C, - FN_FSO_CFE_0_B, + FN_FSO_CFE_0x, IFN_RX2_A, FN_SD2_WP_B, FN_SDA1_A, - FN_RDS_DATA_B, - FN_RMIN_A, + FN_FMIN_A, FN_RIF1_SYNC_C, - FN_FSO_CEF_1_B, + FN_FSO_CFE_1x, IFN_HSCK0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, @@ -829,21 +879,19 @@ enum { FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - FN_AD_CLK, + FN_RX5_B, IFN_HRX0, FN_MSIOF1_RXD_D, - FN_SS1_SDATA2_B, + FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - FN_AD_DI, IFN_HTX0, FN_MSIOF1_TXD_D, FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - FN_AD_DO, IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, @@ -852,7 +900,6 @@ enum { FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C, FN_AUDIO_CLKOUT1_A, - FN_AD_NSCx, IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, @@ -862,22 +909,23 @@ enum { FN_AUDIO_CLKOUT2_A, IFN_MSIOF0_SYNC, FN_AUDIO_CLKOUT_A, + FN_TX5_B, + FN_BPFCLK_D, - /* IPSR13 */ + /* IPSR14 */ IFN_MSIOF0_SS1, - FN_RX5, + FN_RX5_A, + FN_NFWPx_A, FN_AUDIO_CLKA_C, FN_SSI_SCK2_A, - FN_RDS_CLK_A, FN_STP_IVCXO27_0_C, FN_AUDIO_CLKOUT3_A, FN_TCLK1_B, IFN_MSIOF0_SS2, - FN_TX5, + FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, FN_SSI_WS2_A, - FN_RDS_DATA_A, FN_STP_OPWM_0_D, FN_AUDIO_CLKOUT_D, FN_SPEEDIN_B, @@ -891,17 +939,17 @@ enum { IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, - IFN_SSI_SCK0129, + IFN_SSI_SCK01239, FN_MSIOF1_TXD_F, FN_MOUT0, - IFN_SSI_WS0129, + IFN_SSI_WS01239, FN_MSIOF1_SS1_F, FN_MOUT1, IFN_SSI_SDATA0, FN_MSIOF1_SS2_F, FN_MOUT2, - /* IPSR14 */ + /* IPSR15 */ IFN_SSI_SDATA1_A, FN_MOUT5, IFN_SSI_SDATA2_A, @@ -943,16 +991,13 @@ enum { FN_RIF0_D0_A, FN_RIF2_D1_A, + /* IPSR16 */ IFN_SSI_SCK6, - FN_USB2_PWEN, FN_SIM0_RST_D, - FN_RDS_CLK_C, IFN_SSI_WS6, - FN_USB2_OVC, FN_SIM0_D_D, IFN_SSI_SDATA6, FN_SIM0_CLK_D, - FN_RSD_DATA_C, FN_SATA_DEVSLP_A, IFN_SSI_SCK78, FN_HRX2_B, @@ -964,7 +1009,7 @@ enum { IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, - FN_TS_SDT1_A, + FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, FN_RIF3_SYNC_A, @@ -972,7 +1017,7 @@ enum { FN_HCTS2x_B, FN_MSIOF1_RXD_C, FN_TS_SDEN1_A, - FN_STP_IEN_1_A, + FN_STP_ISEN_1_A, FN_RIF1_D0_A, FN_RIF3_D0_A, FN_TCLK2_A, @@ -982,7 +1027,7 @@ enum { FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_EIF3_D1_A, + FN_RIF3_D1_A, IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, @@ -990,31 +1035,29 @@ enum { FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, - FN_SCK5, + FN_SCK5_A, - /* IPSR16 */ + /* IPSR17 */ IFN_AUDIO_CLKA_A, FN_CC5_OSCOUT, IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, - FN_DVC_MUTE, FN_STP_IVCXO27_1_D, FN_REMOCON_A, FN_TCLK1_A, - FN_VSP_B, IFN_USB0_PWEN, FN_SIM0_RST_C, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, FN_RIF3_CLK_B, - FN_SCKZ_B, + FN_HSCK2_C, IFN_USB0_OVC, FN_SIM0_D_C, FN_TS_SDAT1_D, FN_STP_ISD_1_D, FN_RIF3_SYNC_B, - FN_VSP_C, + FN_HRX2_C, IFN_USB1_PWEN, FN_SIM0_CLK_C, FN_SSI_SCK1_A, @@ -1022,9 +1065,8 @@ enum { FN_STP_ISCLK_0_E, FN_FMCLK_B, FN_RIF2_CLK_B, - FN_MTSx_B, FN_SPEEDIN_A, - FN_VSP_D, + FN_HTX2_C, IFN_USB1_OVC, FN_MSIOF1_SS2_C, FN_SSI_WS1_A, @@ -1032,8 +1074,8 @@ enum { FN_STP_ISD_0_E, FN_FMIN_B, FN_RIF2_SYNC_B, - FN_STMx_B, FN_REMOCON_B, + FN_HCTS2x_C, IFN_USB30_PWEN, FN_AUDIO_CLKOUT_B, FN_SSI_SCK2_B, @@ -1041,9 +1083,10 @@ enum { FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, FN_RIF3_D0_B, - FN_MDATA_B, FN_TCLK2_B, FN_TPU0TO0, + FN_BPFCLK_C, + FN_HRTS2x_C, IFN_USB30_OVC, FN_AUDIO_CLKOUT1_B, FN_SSI_WS2_B, @@ -1051,135 +1094,167 @@ enum { FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E, FN_RIF3_D1_B, - FN_SDATA_B, - FN_RSO_TOE_B, + FN_FSO_TOEx, FN_TPU0TO1, - /* IPSR17 */ - IFN_USB31_PWEN, + /* IPSR18 */ + IFN_USB3_PWEN, FN_AUDIO_CLKOUT2_B, - FN_SI_SCK9_B, + FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, FN_RIF2_D0_B, FN_TPU0TO2, - IFN_USB31_OVC, + FN_FMCLK_C, + FN_FMCLK_D, + IFN_USB3_OVC, FN_AUDIO_CLKOUT3_B, FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, FN_RIF2_D1_B, FN_TPU0TO3, + FN_FMIN_C, + FN_FMIN_D, /* MOD_SEL0 */ + /* sel_msiof3[3](0,1,2,3,4) */ FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, + FN_SEL_MSIOF3_4, + /* sel_msiof2[2](0,1,2,3) */ FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, + /* sel_msiof1[3](0,1,2,3,4,5,6) */ FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, FN_SEL_MSIOF1_6, + /* sel_lbsc[1](0,1) */ FN_SEL_LBSC_0, FN_SEL_LBSC_1, + /* sel_iebus[1](0,1) */ FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, + /* sel_i2c2[1](0,1) */ FN_SEL_I2C2_0, FN_SEL_I2C2_1, + /* sel_i2c1[1](0,1) */ FN_SEL_I2C1_0, FN_SEL_I2C1_1, + /* sel_hscif4[1](0,1) */ FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, + /* sel_hscif3[2](0,1,2,3) */ FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + /* sel_hscif1[1](0,1) */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - FN_SEL_FSO_1, - FN_SEL_FM_0, FN_SEL_FM_1, + /* reserved[1] */ + /* sel_hscif2[2](0,1,2) */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, + /* sel_etheravb[1](0,1) */ FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, + /* sel_drif3[1](0,1) */ FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, + /* sel_drif2[1](0,1) */ FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, + /* sel_drif1[2](0,1,2) */ FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, FN_SEL_DRIF1_2, + /* sel_drif0[2](0,1,2) */ FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, FN_SEL_DRIF0_2, + /* sel_canfd0[1](0,1) */ FN_SEL_CANFD_0, FN_SEL_CANFD_1, - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - FN_SEL_5LINE_0, FN_SEL_5LINE_1, + /* sel_adg_a[2](0,1,2) */ + FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, + FN_SEL_ADG_A_2, + /* reserved[3]*/ /* MOD_SEL1 */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, + /* sel_tsif1[2](0,1,2,3) */ + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, + FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, + /* sel_tsif0[3](0,1,2,3,4) */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_TSIF0_4, - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, + /* sel_timer_tmu1[1](0,1) */ + FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, + /* sel_ssp1_1[2](0,1,2,3) */ + FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, + FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, + /* sel_ssp1_0[3](0,1,2,3,4) */ + FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, + FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, FN_SEL_SSP1_0_4, - FN_SEL_SSI_0, - FN_SEL_SSI_1, - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, + /* sel_ssi1[1](0,1) */ + FN_SEL_SSI_0, FN_SEL_SSI_1, + /* sel_speed_pulse_if[1](0,1) */ + FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, + /* sel_simcard[2](0,1,2,3) */ + FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, + FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, + /* sel_sdhi2[1](0,1) */ + FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, + /* sel_scif4[2](0,1,2) */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - FN_SEL_RDS_0, - FN_SEL_RDS_1, - FN_SEL_RDS_2, - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, + /* sel_scif3[1](0,1) */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + /* sel_scif2[1](0,1) */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + /* sel_scif1[1](0,1) */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, + /* sel_scif[1](0,1) */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* sel_remocon[1](0,1) */ + FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, + /* reserved[8..7] */ + /* sel_rcan0[1](0,1) */ + FN_SEL_RCAN_0, FN_SEL_RCAN_1, + /* sel_pwm6[1](0,1) */ + FN_SEL_PWM6_0, FN_SEL_PWM6_1, + /* sel_pwm5[1](0,1) */ + FN_SEL_PWM5_0, FN_SEL_PWM5_1, + /* sel_pwm4[1](0,1) */ + FN_SEL_PWM4_0, FN_SEL_PWM4_1, + /* sel_pwm3[1](0,1) */ + FN_SEL_PWM3_0, FN_SEL_PWM3_1, + /* sel_pwm2[1](0,1) */ + FN_SEL_PWM2_0, FN_SEL_PWM2_1, + /* sel_pwm1[1](0,1) */ + FN_SEL_PWM1_0, FN_SEL_PWM1_1, /* MOD_SEL2 */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - FN_SEL_VSP_0, - FN_SEL_VSP_1, - FN_SEL_VSP_2, - FN_SEL_VSP_3, - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, + /* i2c_sel_5[1](0,1) */ + FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, + /* i2c_sel_3[1](0,1) */ + FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, + /* i2c_sel_0[1](0,1) */ + FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, + /* sel_fm[2](0,1,2,3) */ + FN_SEL_FM_0, FN_SEL_FM_1, + FN_SEL_FM_2, FN_SEL_FM_3, + /* sel_scif5[1](0,1) */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* sel_i2c6[3](0,1,2) */ + FN_SEL_I2C6_0, FN_SEL_I2C6_1, + FN_SEL_I2C6_2, + /* sel_ndfc[1](0,1) */ + FN_SEL_NDFC_0, FN_SEL_NDFC_1, + /* sel_ssi2[1](0,1) */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + /* sel_ssi9[1](0,1) */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* sel_timer_tmu2[1](0,1) */ + FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, + /* sel_adg_b[1](0,1) */ + FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, + /* sel_adg_c[1](0,1) */ + FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, + /* reserved[16..16] */ + /* reserved[15..8] */ + /* reserved[7..1] */ + /* sel_vin4[1](0,1) */ + FN_SEL_VIN4_0, FN_SEL_VIN4_1, PINMUX_FUNCTION_END, @@ -1204,6 +1279,7 @@ enum { D0_GMARK, /* GPSR1 */ + CLKOUT_GMARK, EX_WAIT0_A_GMARK, WE1x_GMARK, WE0x_GMARK, @@ -1269,23 +1345,23 @@ enum { SD0_CLK_GMARK, /* GPSR4 */ - SD3_DS_MARK, + SD3_DS_GMARK, SD3_DAT7_GMARK, SD3_DAT6_GMARK, SD3_DAT5_GMARK, SD3_DAT4_GMARK, - SD3_DAT3_MARK, - SD3_DAT2_MARK, - SD3_DAT1_MARK, - SD3_DAT0_MARK, - SD3_CMD_MARK, - SD3_CLK_MARK, + SD3_DAT3_GMARK, + SD3_DAT2_GMARK, + SD3_DAT1_GMARK, + SD3_DAT0_GMARK, + SD3_CMD_GMARK, + SD3_CLK_GMARK, SD2_DS_GMARK, SD2_DAT3_GMARK, SD2_DAT2_GMARK, SD2_DAT1_GMARK, SD2_DAT0_GMARK, - SD2_CMD_MARK, + SD2_CMD_GMARK, SD2_CLK_GMARK, /* GPSR5 */ @@ -1317,8 +1393,8 @@ enum { SCK0_GMARK, /* GPSR6 */ - USB31_OVC_GMARK, - USB31_PWEN_GMARK, + USB3_OVC_GMARK, + USB3_PWEN_GMARK, USB30_OVC_GMARK, USB30_PWEN_GMARK, USB1_OVC_GMARK, @@ -1347,8 +1423,8 @@ enum { SSI_SDATA2_A_GMARK, SSI_SDATA1_A_GMARK, SSI_SDATA0_GMARK, - SSI_WS0129_GMARK, - SSI_SCK0129_GMARK, + SSI_WS01239_GMARK, + SSI_SCK01239_GMARK, /* GPSR7 */ HDMI1_CEC_MARK, @@ -1360,7 +1436,7 @@ enum { AVB_MDC_IMARK, MSIOF2_SS2_C_MARK, AVB_MAGIC_IMARK, - MSIOF2_S1_C_MARK, + MSIOF2_SS1_C_MARK, SCK4_A_MARK, AVB_PHY_INT_IMARK, MSIOF2_SYNC_C_MARK, @@ -1371,6 +1447,7 @@ enum { AVB_AVTP_MATCH_A_IMARK, MSIOF2_RXD_C_MARK, CTS4x_A_MARK, + FSCLKST2x_A_MARK, AVB_AVTP_CAPTURE_A_IMARK, MSIOF2_TXD_C_MARK, RTS4x_TANS_A_MARK, @@ -1380,50 +1457,51 @@ enum { VI4_DATA0_B_MARK, CAN0_TX_B_MARK, CANFD0_TX_B_MARK, + MSIOF3_SS2_E_MARK, IRQ1_IMARK, QPOLA_MARK, DU_DISP_MARK, VI4_DATA1_B_MARK, CAN0_RX_B_MARK, CANFD0_RX_B_MARK, + MSIOF3_SS1_E_MARK, /* IPSR1 */ IRQ2_IMARK, QCPV_QDE_MARK, DU_EXODDF_DU_ODDF_DISP_CDE_MARK, VI4_DATA2_B_MARK, + MSIOF3_SYNC_E_MARK, PWM3_B_MARK, IRQ3_IMARK, QSTVB_QVE_MARK, - A25_MARK, DU_DOTCLKOUT1_MARK, VI4_DATA3_B_MARK, + MSIOF3_SCK_E_MARK, PWM4_B_MARK, IRQ4_IMARK, QSTH_QHS_MARK, - A24_MARK, DU_EXHSYNC_DU_HSYNC_MARK, VI4_DATA4_B_MARK, + MSIOF3_RXD_E_MARK, PWM5_B_MARK, IRQ5_IMARK, QSTB_QHE_MARK, - A23_MARK, DU_EXVSYNC_DU_VSYNC_MARK, VI4_DATA5_B_MARK, + FSCLKST2x_B_MARK, + MSIOF3_TXD_E_MARK, PWM6_B_MARK, PWM0_IMARK, AVB_AVTP_PPS_MARK, - A22_MARK, VI4_DATA6_B_MARK, IECLK_B_MARK, PWM1_A_IMARK, - A21_MARK, HRX3_D_MARK, VI4_DATA7_B_MARK, IERX_B_MARK, PWM2_A_IMARK, PWMFSW0_MARK, - A20_MARK, HTX3_D_MARK, IETX_B_MARK, A0_IMARK, @@ -1505,7 +1583,6 @@ enum { SCL6_A_MARK, AVB_AVTP_CAPTURE_B_MARK, PWM2_B_MARK, - SPV_EVEN_MARK, A12_IMARK, LCDOUT12_MARK, MSIOF3_SCK_C_MARK, @@ -1711,67 +1788,94 @@ enum { SD1_CLK_IMARK, MSIOF1_SCK_G_MARK, SIM0_CLK_A_MARK, - SD1_CMD_IMARK, MSIOF1_SYNC_G_MARK, + NFCEx_B_MARK, SIM0_D_A_MARK, STP_IVCXO27_1_B_MARK, - SD1_DAT0_IMARK, SD2_DAT4_MARK, MSIOF1_RXD_G_MARK, + NFWPx_B_MARK, TS_SCK1_B_MARK, STP_ISCLK_1_B_MARK, - SD1_DAT1_IMARK, SD2_DAT5_MARK, MSIOF1_TXD_G_MARK, + NFDATA14_B_MARK, TS_SPSYNC1_B_MARK, STP_ISSYNC_1_B_MARK, - SD1_DAT2_IMARK, SD2_DAT6_MARK, MSIOF1_SS1_G_MARK, + NFDATA15_B_MARK, TS_SDAT1_B_MARK, STP_IOD_1_B_MARK, SD1_DAT3_IMARK, SD2_DAT7_MARK, MSIOF1_SS2_G_MARK, + NFRBx_B_MARK, TS_SDEN1_B_MARK, STP_ISEN_1_B_MARK, /* IPSR9 */ SD2_CLK_IMARK, - SCKZ_A_MARK, + NFDATA8_MARK, + SD2_CMD_IMARK, + NFDATA9_MARK, SD2_DAT0_IMARK, - MTSx_A_MARK, + NFDATA10_MARK, SD2_DAT1_IMARK, - STMx_A_MARK, + NFDATA11_MARK, SD2_DAT2_IMARK, - MDATA_A_MARK, + NFDATA12_MARK, SD2_DAT3_IMARK, - SDATA_A_MARK, + NFDATA13_MARK, SD2_DS_IMARK, + NFALE_MARK, SATA_DEVSLP_B_MARK, - VSP_A_MARK, + SD3_CLK_IMARK, + NFWEx_MARK, + + /* IPSR10 */ + SD3_CMD_IMARK, + NFREx_MARK, + SD3_DAT0_IMARK, + NFDATA0_MARK, + SD3_DAT1_IMARK, + NFDATA1_MARK, + SD3_DAT2_IMARK, + NFDATA2_MARK, + SD3_DAT3_IMARK, + NFDATA3_MARK, SD3_DAT4_IMARK, SD2_CD_A_MARK, + NFDATA4_MARK, SD3_DAT5_IMARK, SD2_WP_A_MARK, - - /* IPSR10 */ + NFDATA5_MARK, SD3_DAT6_IMARK, SD3_CD_MARK, + NFDATA6_MARK, + + /* IPSR11 */ SD3_DAT7_IMARK, SD3_WP_MARK, + NFDATA7_MARK, + SD3_DS_IMARK, + NFCLE_MARK, SD0_CD_IMARK, + NFDATA14_A_MARK, SCL2_B_MARK, SIM0_RST_A_MARK, SD0_WP_IMARK, + NFDATA15_A_MARK, SDA2_B_MARK, SD1_CD_IMARK, + NFRBx_A_MARK, SIM0_CLK_B_MARK, SD1_WP_IMARK, + NFCEx_A_MARK, SIM0_D_B_MARK, SCK0_IMARK, HSCK1_B_MARK, @@ -1779,16 +1883,17 @@ enum { AUDIO_CLKC_B_MARK, SDA2_A_MARK, SIM0_RST_B_MARK, - STP_OPWM__C_MARK, + STP_OPWM_0_C_MARK, RIF0_CLK_B_MARK, ADICHS2_MARK, + SCK5_B_MARK, RX0_IMARK, HRX1_B_MARK, TS_SCK0_C_MARK, STP_ISCLK_0_C_MARK, RIF0_D0_B_MARK, - /* IPSR11 */ + /* IPSR12 */ TX0_IMARK, HTX1_B_MARK, TS_SPSYNC0_C_MARK, @@ -1813,7 +1918,7 @@ enum { RX1_A_IMARK, HRX1_A_MARK, TS_SDAT0_C_MARK, - STP_IDS_0_C_MARK, + STP_ISD_0_C_MARK, RIF1_CLK_C_MARK, TX1_A_IMARK, HTX1_A_MARK, @@ -1842,21 +1947,19 @@ enum { RIF1_CLK_B_MARK, ADICLK_MARK, - /* IPSR12 */ + /* IPSR13 */ TX2_A_IMARK, SD2_CD_B_MARK, SCL1_A_MARK, - RSD_CLK_B_MARK, FMCLK_A_MARK, RIF1_D1_C_MARK, - FSO_CFE_0_B_MARK, + FSO_CFE_0x_MARK, RX2_A_IMARK, SD2_WP_B_MARK, SDA1_A_MARK, - RDS_DATA_B_MARK, - RMIN_A_MARK, + FMIN_A_MARK, RIF1_SYNC_C_MARK, - FSO_CEF_1_B_MARK, + FSO_CFE_1x_MARK, HSCK0_IMARK, MSIOF1_SCK_D_MARK, AUDIO_CLKB_A_MARK, @@ -1864,21 +1967,19 @@ enum { TS_SCK0_D_MARK, STP_ISCLK_0_D_MARK, RIF0_CLK_C_MARK, - AD_CLK_MARK, + RX5_B_MARK, HRX0_IMARK, MSIOF1_RXD_D_MARK, - SS1_SDATA2_B_MARK, + SSI_SDATA2_B_MARK, TS_SDEN0_D_MARK, STP_ISEN_0_D_MARK, RIF0_D0_C_MARK, - AD_DI_MARK, HTX0_IMARK, MSIOF1_TXD_D_MARK, SSI_SDATA9_B_MARK, TS_SDAT0_D_MARK, STP_ISD_0_D_MARK, RIF0_D1_C_MARK, - AD_DO_MARK, HCTS0x_IMARK, RX2_B_MARK, MSIOF1_SYNC_D_MARK, @@ -1887,7 +1988,6 @@ enum { STP_ISSYNC_0_D_MARK, RIF0_SYNC_C_MARK, AUDIO_CLKOUT1_A_MARK, - AD_NSCx_MARK, HRTS0x_IMARK, TX2_B_MARK, MSIOF1_SS1_D_MARK, @@ -1897,22 +1997,23 @@ enum { AUDIO_CLKOUT2_A_MARK, MSIOF0_SYNC_IMARK, AUDIO_CLKOUT_A_MARK, + TX5_B_MARK, + BPFCLK_D_MARK, - /* IPSR13 */ + /* IPSR14 */ MSIOF0_SS1_IMARK, - RX5_MARK, + RX5_A_MARK, + NFWPx_A_MARK, AUDIO_CLKA_C_MARK, SSI_SCK2_A_MARK, - RDS_CLK_A_MARK, STP_IVCXO27_0_C_MARK, AUDIO_CLKOUT3_A_MARK, TCLK1_B_MARK, MSIOF0_SS2_IMARK, - TX5_MARK, + TX5_A_MARK, MSIOF1_SS2_D_MARK, AUDIO_CLKC_A_MARK, SSI_WS2_A_MARK, - RDS_DATA_A_MARK, STP_OPWM_0_D_MARK, AUDIO_CLKOUT_D_MARK, SPEEDIN_B_MARK, @@ -1926,17 +2027,17 @@ enum { MLB_DAT_IMARK, TX1_B_MARK, MSIOF1_RXD_F_MARK, - SSI_SCK0129_IMARK, + SSI_SCK01239_IMARK, MSIOF1_TXD_F_MARK, MOUT0_MARK, - SSI_WS0129_IMARK, + SSI_WS01239_IMARK, MSIOF1_SS1_F_MARK, MOUT1_MARK, SSI_SDATA0_IMARK, MSIOF1_SS2_F_MARK, MOUT2_MARK, - /* IPSR14 */ + /* IPSR15 */ SSI_SDATA1_A_IMARK, MOUT5_MARK, SSI_SDATA2_A_IMARK, @@ -1978,16 +2079,13 @@ enum { RIF0_D0_A_MARK, RIF2_D1_A_MARK, + /* IPSR16 */ SSI_SCK6_IMARK, - USB2_PWEN_MARK, SIM0_RST_D_MARK, - RDS_CLK_C_MARK, SSI_WS6_IMARK, - USB2_OVC_MARK, SIM0_D_D_MARK, SSI_SDATA6_IMARK, SIM0_CLK_D_MARK, - RSD_DATA_C_MARK, SATA_DEVSLP_A_MARK, SSI_SCK78_IMARK, HRX2_B_MARK, @@ -1999,7 +2097,7 @@ enum { SSI_WS78_IMARK, HTX2_B_MARK, MSIOF1_SYNC_C_MARK, - TS_SDT1_A_MARK, + TS_SDAT1_A_MARK, STP_ISD_1_A_MARK, RIF1_SYNC_A_MARK, RIF3_SYNC_A_MARK, @@ -2007,7 +2105,7 @@ enum { HCTS2x_B_MARK, MSIOF1_RXD_C_MARK, TS_SDEN1_A_MARK, - STP_IEN_1_A_MARK, + STP_ISEN_1_A_MARK, RIF1_D0_A_MARK, RIF3_D0_A_MARK, TCLK2_A_MARK, @@ -2017,7 +2115,7 @@ enum { TS_SPSYNC1_A_MARK, STP_ISSYNC_1_A_MARK, RIF1_D1_A_MARK, - EIF3_D1_A_MARK, + RIF3_D1_A_MARK, SSI_SDATA9_A_IMARK, HSCK2_B_MARK, MSIOF1_SS1_C_MARK, @@ -2025,31 +2123,29 @@ enum { SSI_WS1_B_MARK, SCK1_MARK, STP_IVCXO27_1_A_MARK, - SCK5_MARK, + SCK5_A_MARK, - /* IPSR16 */ + /* IPSR17 */ AUDIO_CLKA_A_IMARK, CC5_OSCOUT_MARK, AUDIO_CLKB_B_IMARK, SCIF_CLK_A_MARK, - DVC_MUTE_MARK, STP_IVCXO27_1_D_MARK, REMOCON_A_MARK, TCLK1_A_MARK, - VSP_B_MARK, USB0_PWEN_IMARK, SIM0_RST_C_MARK, TS_SCK1_D_MARK, STP_ISCLK_1_D_MARK, BPFCLK_B_MARK, RIF3_CLK_B_MARK, - SCKZ_B_MARK, + HSCK2_C_MARK, USB0_OVC_IMARK, SIM0_D_C_MARK, TS_SDAT1_D_MARK, STP_ISD_1_D_MARK, RIF3_SYNC_B_MARK, - VSP_C_MARK, + HRX2_C_MARK, USB1_PWEN_IMARK, SIM0_CLK_C_MARK, SSI_SCK1_A_MARK, @@ -2057,9 +2153,8 @@ enum { STP_ISCLK_0_E_MARK, FMCLK_B_MARK, RIF2_CLK_B_MARK, - MTSx_B_MARK, SPEEDIN_A_MARK, - VSP_D_MARK, + HTX2_C_MARK, USB1_OVC_IMARK, MSIOF1_SS2_C_MARK, SSI_WS1_A_MARK, @@ -2067,8 +2162,8 @@ enum { STP_ISD_0_E_MARK, FMIN_B_MARK, RIF2_SYNC_B_MARK, - STMx_B_MARK, REMOCON_B_MARK, + HCTS2x_C_MARK, USB30_PWEN_IMARK, AUDIO_CLKOUT_B_MARK, SSI_SCK2_B_MARK, @@ -2076,9 +2171,10 @@ enum { STP_ISEN_1_D_MARK, STP_OPWM_0_E_MARK, RIF3_D0_B_MARK, - MDATA_B_MARK, TCLK2_B_MARK, TPU0TO0_MARK, + BPFCLK_C_MARK, + HRTS2x_C_MARK, USB30_OVC_IMARK, AUDIO_CLKOUT1_B_MARK, SSI_WS2_B_MARK, @@ -2086,26 +2182,9 @@ enum { STP_ISSYNC_1_D_MARK, STP_IVCXO27_0_E_MARK, RIF3_D1_B_MARK, - SDATA_B_MARK, - RSO_TOE_B_MARK, + FSO_TOEx_MARK, TPU0TO1_MARK, - /* IPSR17 */ - USB31_PWEN_IMARK, - AUDIO_CLKOUT2_B_MARK, - SI_SCK9_B_MARK, - TS_SDEN0_E_MARK, - STP_ISEN_0_E_MARK, - RIF2_D0_B_MARK, - TPU0TO2_MARK, - USB31_OVC_IMARK, - AUDIO_CLKOUT3_B_MARK, - SSI_WS9_B_MARK, - TS_SPSYNC0_E_MARK, - STP_ISSYNC_0_E_MARK, - RIF2_D1_B_MARK, - TPU0TO3_MARK, - PINMUX_MARK_END, }; @@ -2131,6 +2210,7 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(D0_GMARK, GFN_D0), /* GPSR1 */ + PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), PINMUX_DATA(WE1x_GMARK, GFN_WE1x), PINMUX_DATA(WE0x_GMARK, GFN_WE0x), @@ -2196,23 +2276,23 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), /* GPSR4 */ - PINMUX_DATA(SD3_DS_MARK, FN_SD3_DS), + PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), - PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3), - PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2), - PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1), - PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0), - PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD), - PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK), + PINMUX_DATA(SD3_DAT3_GMARK, GFN_SD3_DAT3), + PINMUX_DATA(SD3_DAT2_GMARK, GFN_SD3_DAT2), + PINMUX_DATA(SD3_DAT1_GMARK, GFN_SD3_DAT1), + PINMUX_DATA(SD3_DAT0_GMARK, GFN_SD3_DAT0), + PINMUX_DATA(SD3_CMD_GMARK, GFN_SD3_CMD), + PINMUX_DATA(SD3_CLK_GMARK, GFN_SD3_CLK), PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), - PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD), + PINMUX_DATA(SD2_CMD_GMARK, GFN_SD2_CMD), PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), /* GPSR5 */ @@ -2244,8 +2324,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SCK0_GMARK, GFN_SCK0), /* GPSR6 */ - PINMUX_DATA(USB31_OVC_GMARK, GFN_USB31_OVC), - PINMUX_DATA(USB31_PWEN_GMARK, GFN_USB31_PWEN), + PINMUX_DATA(USB3_OVC_GMARK, GFN_USB3_OVC), + PINMUX_DATA(USB3_PWEN_GMARK, GFN_USB3_PWEN), PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), @@ -2274,16 +2354,14 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), - PINMUX_DATA(SSI_WS0129_GMARK, GFN_SSI_WS0129), - PINMUX_DATA(SSI_SCK0129_GMARK, GFN_SSI_SCK0129), + PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), + PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), /* GPSR7 */ PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), PINMUX_DATA(AVS2_MARK, FN_AVS2), PINMUX_DATA(AVS1_MARK, FN_AVS1), - - /* ipsr setting .. underconstruction */ }; static struct pinmux_gpio pinmux_gpios[] = { @@ -2306,6 +2384,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_GFN(D1), GPIO_GFN(D0), /* GPSR1 */ + GPIO_GFN(CLKOUT), GPIO_GFN(EX_WAIT0_A), GPIO_GFN(WE1x), GPIO_GFN(WE0x), @@ -2371,23 +2450,23 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_GFN(SD0_CLK), /* GPSR4 */ - GPIO_FN(SD3_DS), + GPIO_GFN(SD3_DS), GPIO_GFN(SD3_DAT7), GPIO_GFN(SD3_DAT6), GPIO_GFN(SD3_DAT5), GPIO_GFN(SD3_DAT4), - GPIO_FN(SD3_DAT3), - GPIO_FN(SD3_DAT2), - GPIO_FN(SD3_DAT1), - GPIO_FN(SD3_DAT0), - GPIO_FN(SD3_CMD), - GPIO_FN(SD3_CLK), + GPIO_GFN(SD3_DAT3), + GPIO_GFN(SD3_DAT2), + GPIO_GFN(SD3_DAT1), + GPIO_GFN(SD3_DAT0), + GPIO_GFN(SD3_CMD), + GPIO_GFN(SD3_CLK), GPIO_GFN(SD2_DS), GPIO_GFN(SD2_DAT3), GPIO_GFN(SD2_DAT2), GPIO_GFN(SD2_DAT1), GPIO_GFN(SD2_DAT0), - GPIO_FN(SD2_CMD), + GPIO_GFN(SD2_CMD), GPIO_GFN(SD2_CLK), /* GPSR5 */ @@ -2419,8 +2498,8 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_GFN(SCK0), /* GPSR6 */ - GPIO_GFN(USB31_OVC), - GPIO_GFN(USB31_PWEN), + GPIO_GFN(USB3_OVC), + GPIO_GFN(USB3_PWEN), GPIO_GFN(USB30_OVC), GPIO_GFN(USB30_PWEN), GPIO_GFN(USB1_OVC), @@ -2449,8 +2528,8 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_GFN(SSI_SDATA2_A), GPIO_GFN(SSI_SDATA1_A), GPIO_GFN(SSI_SDATA0), - GPIO_GFN(SSI_WS0129), - GPIO_GFN(SSI_SCK0129), + GPIO_GFN(SSI_WS01239), + GPIO_GFN(SSI_SCK01239), /* GPSR7 */ GPIO_FN(HDMI1_CEC), @@ -2462,7 +2541,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_IFN(AVB_MDC), GPIO_FN(MSIOF2_SS2_C), GPIO_IFN(AVB_MAGIC), - GPIO_FN(MSIOF2_S1_C), + GPIO_FN(MSIOF2_SS1_C), GPIO_FN(SCK4_A), GPIO_IFN(AVB_PHY_INT), GPIO_FN(MSIOF2_SYNC_C), @@ -2473,6 +2552,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_IFN(AVB_AVTP_MATCH_A), GPIO_FN(MSIOF2_RXD_C), GPIO_FN(CTS4x_A), + GPIO_FN(FSCLKST2x_A), GPIO_IFN(AVB_AVTP_CAPTURE_A), GPIO_FN(MSIOF2_TXD_C), GPIO_FN(RTS4x_TANS_A), @@ -2482,50 +2562,50 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(VI4_DATA0_B), GPIO_FN(CAN0_TX_B), GPIO_FN(CANFD0_TX_B), + GPIO_FN(MSIOF3_SS2_E), GPIO_IFN(IRQ1), GPIO_FN(QPOLA), GPIO_FN(DU_DISP), GPIO_FN(VI4_DATA1_B), GPIO_FN(CAN0_RX_B), GPIO_FN(CANFD0_RX_B), + GPIO_FN(MSIOF3_SS1_E), /* IPSR1 */ GPIO_IFN(IRQ2), GPIO_FN(QCPV_QDE), GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), GPIO_FN(VI4_DATA2_B), + GPIO_FN(MSIOF3_SYNC_E), GPIO_FN(PWM3_B), GPIO_IFN(IRQ3), GPIO_FN(QSTVB_QVE), - GPIO_FN(A25), GPIO_FN(DU_DOTCLKOUT1), GPIO_FN(VI4_DATA3_B), + GPIO_FN(MSIOF3_SCK_E), GPIO_FN(PWM4_B), GPIO_IFN(IRQ4), GPIO_FN(QSTH_QHS), - GPIO_FN(A24), GPIO_FN(DU_EXHSYNC_DU_HSYNC), GPIO_FN(VI4_DATA4_B), + GPIO_FN(MSIOF3_RXD_E), GPIO_FN(PWM5_B), GPIO_IFN(IRQ5), GPIO_FN(QSTB_QHE), - GPIO_FN(A23), GPIO_FN(DU_EXVSYNC_DU_VSYNC), GPIO_FN(VI4_DATA5_B), + GPIO_FN(FSCLKST2x_B), + GPIO_FN(MSIOF3_TXD_E), GPIO_FN(PWM6_B), GPIO_IFN(PWM0), GPIO_FN(AVB_AVTP_PPS), - GPIO_FN(A22), GPIO_FN(VI4_DATA6_B), GPIO_FN(IECLK_B), GPIO_IFN(PWM1_A), - GPIO_FN(A21), GPIO_FN(HRX3_D), GPIO_FN(VI4_DATA7_B), GPIO_FN(IERX_B), GPIO_IFN(PWM2_A), - GPIO_FN(PWMFSW0), - GPIO_FN(A20), GPIO_FN(HTX3_D), GPIO_FN(IETX_B), GPIO_IFN(A0), @@ -2607,7 +2687,6 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(SCL6_A), GPIO_FN(AVB_AVTP_CAPTURE_B), GPIO_FN(PWM2_B), - GPIO_FN(SPV_EVEN), GPIO_IFN(A12), GPIO_FN(LCDOUT12), GPIO_FN(MSIOF3_SCK_C), @@ -2813,67 +2892,94 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_IFN(SD1_CLK), GPIO_FN(MSIOF1_SCK_G), GPIO_FN(SIM0_CLK_A), - GPIO_IFN(SD1_CMD), GPIO_FN(MSIOF1_SYNC_G), + GPIO_FN(NFCEx_B), GPIO_FN(SIM0_D_A), GPIO_FN(STP_IVCXO27_1_B), - GPIO_IFN(SD1_DAT0), GPIO_FN(SD2_DAT4), GPIO_FN(MSIOF1_RXD_G), + GPIO_FN(NFWPx_B), GPIO_FN(TS_SCK1_B), GPIO_FN(STP_ISCLK_1_B), - GPIO_IFN(SD1_DAT1), GPIO_FN(SD2_DAT5), GPIO_FN(MSIOF1_TXD_G), + GPIO_FN(NFDATA14_B), GPIO_FN(TS_SPSYNC1_B), GPIO_FN(STP_ISSYNC_1_B), - GPIO_IFN(SD1_DAT2), GPIO_FN(SD2_DAT6), GPIO_FN(MSIOF1_SS1_G), + GPIO_FN(NFDATA15_B), GPIO_FN(TS_SDAT1_B), GPIO_FN(STP_IOD_1_B), GPIO_IFN(SD1_DAT3), GPIO_FN(SD2_DAT7), GPIO_FN(MSIOF1_SS2_G), + GPIO_FN(NFRBx_B), GPIO_FN(TS_SDEN1_B), GPIO_FN(STP_ISEN_1_B), /* IPSR9 */ GPIO_IFN(SD2_CLK), - GPIO_FN(SCKZ_A), + GPIO_FN(NFDATA8), + GPIO_IFN(SD2_CMD), + GPIO_FN(NFDATA9), GPIO_IFN(SD2_DAT0), - GPIO_FN(MTSx_A), + GPIO_FN(NFDATA10), GPIO_IFN(SD2_DAT1), - GPIO_FN(STMx_A), + GPIO_FN(NFDATA11), GPIO_IFN(SD2_DAT2), - GPIO_FN(MDATA_A), + GPIO_FN(NFDATA12), GPIO_IFN(SD2_DAT3), - GPIO_FN(SDATA_A), + GPIO_FN(NFDATA13), GPIO_IFN(SD2_DS), + GPIO_FN(NFALE), GPIO_FN(SATA_DEVSLP_B), - GPIO_FN(VSP_A), + GPIO_IFN(SD3_CLK), + GPIO_FN(NFWEx), + + /* IPSR10 */ + GPIO_IFN(SD3_CMD), + GPIO_FN(NFREx), + GPIO_IFN(SD3_DAT0), + GPIO_FN(NFDATA0), + GPIO_IFN(SD3_DAT1), + GPIO_FN(NFDATA1), + GPIO_IFN(SD3_DAT2), + GPIO_FN(NFDATA2), + GPIO_IFN(SD3_DAT3), + GPIO_FN(NFDATA3), GPIO_IFN(SD3_DAT4), GPIO_FN(SD2_CD_A), + GPIO_FN(NFDATA4), GPIO_IFN(SD3_DAT5), GPIO_FN(SD2_WP_A), - - /* IPSR10 */ + GPIO_FN(NFDATA5), GPIO_IFN(SD3_DAT6), GPIO_FN(SD3_CD), + GPIO_FN(NFDATA6), + + /* IPSR11 */ GPIO_IFN(SD3_DAT7), GPIO_FN(SD3_WP), + GPIO_FN(NFDATA7), + GPIO_IFN(SD3_DS), + GPIO_FN(NFCLE), GPIO_IFN(SD0_CD), + GPIO_FN(NFDATA14_A), GPIO_FN(SCL2_B), GPIO_FN(SIM0_RST_A), GPIO_IFN(SD0_WP), + GPIO_FN(NFDATA15_A), GPIO_FN(SDA2_B), GPIO_IFN(SD1_CD), + GPIO_FN(NFRBx_A), GPIO_FN(SIM0_CLK_B), GPIO_IFN(SD1_WP), + GPIO_FN(NFCEx_A), GPIO_FN(SIM0_D_B), GPIO_IFN(SCK0), GPIO_FN(HSCK1_B), @@ -2881,16 +2987,17 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(AUDIO_CLKC_B), GPIO_FN(SDA2_A), GPIO_FN(SIM0_RST_B), - GPIO_FN(STP_OPWM__C), + GPIO_FN(STP_OPWM_0_C), GPIO_FN(RIF0_CLK_B), GPIO_FN(ADICHS2), + GPIO_FN(SCK5_B), GPIO_IFN(RX0), GPIO_FN(HRX1_B), GPIO_FN(TS_SCK0_C), GPIO_FN(STP_ISCLK_0_C), GPIO_FN(RIF0_D0_B), - /* IPSR11 */ + /* IPSR12 */ GPIO_IFN(TX0), GPIO_FN(HTX1_B), GPIO_FN(TS_SPSYNC0_C), @@ -2915,7 +3022,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_IFN(RX1_A), GPIO_FN(HRX1_A), GPIO_FN(TS_SDAT0_C), - GPIO_FN(STP_IDS_0_C), + GPIO_FN(STP_ISD_0_C), GPIO_FN(RIF1_CLK_C), GPIO_IFN(TX1_A), GPIO_FN(HTX1_A), @@ -2944,21 +3051,19 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(RIF1_CLK_B), GPIO_FN(ADICLK), - /* IPSR12 */ + /* IPSR13 */ GPIO_IFN(TX2_A), GPIO_FN(SD2_CD_B), GPIO_FN(SCL1_A), - GPIO_FN(RSD_CLK_B), GPIO_FN(FMCLK_A), GPIO_FN(RIF1_D1_C), - GPIO_FN(FSO_CFE_0_B), + GPIO_FN(FSO_CFE_0x), GPIO_IFN(RX2_A), GPIO_FN(SD2_WP_B), GPIO_FN(SDA1_A), - GPIO_FN(RDS_DATA_B), - GPIO_FN(RMIN_A), + GPIO_FN(FMIN_A), GPIO_FN(RIF1_SYNC_C), - GPIO_FN(FSO_CEF_1_B), + GPIO_FN(FSO_CFE_1x), GPIO_IFN(HSCK0), GPIO_FN(MSIOF1_SCK_D), GPIO_FN(AUDIO_CLKB_A), @@ -2966,21 +3071,19 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(TS_SCK0_D), GPIO_FN(STP_ISCLK_0_D), GPIO_FN(RIF0_CLK_C), - GPIO_FN(AD_CLK), + GPIO_FN(RX5_B), GPIO_IFN(HRX0), GPIO_FN(MSIOF1_RXD_D), - GPIO_FN(SS1_SDATA2_B), + GPIO_FN(SSI_SDATA2_B), GPIO_FN(TS_SDEN0_D), GPIO_FN(STP_ISEN_0_D), GPIO_FN(RIF0_D0_C), - GPIO_FN(AD_DI), GPIO_IFN(HTX0), GPIO_FN(MSIOF1_TXD_D), GPIO_FN(SSI_SDATA9_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(STP_ISD_0_D), GPIO_FN(RIF0_D1_C), - GPIO_FN(AD_DO), GPIO_IFN(HCTS0x), GPIO_FN(RX2_B), GPIO_FN(MSIOF1_SYNC_D), @@ -2989,7 +3092,6 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(STP_ISSYNC_0_D), GPIO_FN(RIF0_SYNC_C), GPIO_FN(AUDIO_CLKOUT1_A), - GPIO_FN(AD_NSCx), GPIO_IFN(HRTS0x), GPIO_FN(TX2_B), GPIO_FN(MSIOF1_SS1_D), @@ -2999,22 +3101,23 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(AUDIO_CLKOUT2_A), GPIO_IFN(MSIOF0_SYNC), GPIO_FN(AUDIO_CLKOUT_A), + GPIO_FN(TX5_B), + GPIO_FN(BPFCLK_D), - /* IPSR13 */ + /* IPSR14 */ GPIO_IFN(MSIOF0_SS1), - GPIO_FN(RX5), + GPIO_FN(RX5_A), + GPIO_FN(NFWPx_A), GPIO_FN(AUDIO_CLKA_C), GPIO_FN(SSI_SCK2_A), - GPIO_FN(RDS_CLK_A), GPIO_FN(STP_IVCXO27_0_C), GPIO_FN(AUDIO_CLKOUT3_A), GPIO_FN(TCLK1_B), GPIO_IFN(MSIOF0_SS2), - GPIO_FN(TX5), + GPIO_FN(TX5_A), GPIO_FN(MSIOF1_SS2_D), GPIO_FN(AUDIO_CLKC_A), GPIO_FN(SSI_WS2_A), - GPIO_FN(RDS_DATA_A), GPIO_FN(STP_OPWM_0_D), GPIO_FN(AUDIO_CLKOUT_D), GPIO_FN(SPEEDIN_B), @@ -3028,17 +3131,17 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_IFN(MLB_DAT), GPIO_FN(TX1_B), GPIO_FN(MSIOF1_RXD_F), - GPIO_IFN(SSI_SCK0129), + GPIO_IFN(SSI_SCK01239), GPIO_FN(MSIOF1_TXD_F), GPIO_FN(MOUT0), - GPIO_IFN(SSI_WS0129), + GPIO_IFN(SSI_WS01239), GPIO_FN(MSIOF1_SS1_F), GPIO_FN(MOUT1), GPIO_IFN(SSI_SDATA0), GPIO_FN(MSIOF1_SS2_F), GPIO_FN(MOUT2), - /* IPSR14 */ + /* IPSR15 */ GPIO_IFN(SSI_SDATA1_A), GPIO_FN(MOUT5), GPIO_IFN(SSI_SDATA2_A), @@ -3080,16 +3183,13 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(RIF0_D0_A), GPIO_FN(RIF2_D1_A), + /* IPSR16 */ GPIO_IFN(SSI_SCK6), - GPIO_FN(USB2_PWEN), GPIO_FN(SIM0_RST_D), - GPIO_FN(RDS_CLK_C), GPIO_IFN(SSI_WS6), - GPIO_FN(USB2_OVC), GPIO_FN(SIM0_D_D), GPIO_IFN(SSI_SDATA6), GPIO_FN(SIM0_CLK_D), - GPIO_FN(RSD_DATA_C), GPIO_FN(SATA_DEVSLP_A), GPIO_IFN(SSI_SCK78), GPIO_FN(HRX2_B), @@ -3101,7 +3201,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_IFN(SSI_WS78), GPIO_FN(HTX2_B), GPIO_FN(MSIOF1_SYNC_C), - GPIO_FN(TS_SDT1_A), + GPIO_FN(TS_SDAT1_A), GPIO_FN(STP_ISD_1_A), GPIO_FN(RIF1_SYNC_A), GPIO_FN(RIF3_SYNC_A), @@ -3109,7 +3209,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(HCTS2x_B), GPIO_FN(MSIOF1_RXD_C), GPIO_FN(TS_SDEN1_A), - GPIO_FN(STP_IEN_1_A), + GPIO_FN(STP_ISEN_1_A), GPIO_FN(RIF1_D0_A), GPIO_FN(RIF3_D0_A), GPIO_FN(TCLK2_A), @@ -3119,7 +3219,7 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(TS_SPSYNC1_A), GPIO_FN(STP_ISSYNC_1_A), GPIO_FN(RIF1_D1_A), - GPIO_FN(EIF3_D1_A), + GPIO_FN(RIF3_D1_A), GPIO_IFN(SSI_SDATA9_A), GPIO_FN(HSCK2_B), GPIO_FN(MSIOF1_SS1_C), @@ -3127,31 +3227,29 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(SSI_WS1_B), GPIO_FN(SCK1), GPIO_FN(STP_IVCXO27_1_A), - GPIO_FN(SCK5), + GPIO_FN(SCK5_A), - /* IPSR16 */ + /* IPSR17 */ GPIO_IFN(AUDIO_CLKA_A), GPIO_FN(CC5_OSCOUT), GPIO_IFN(AUDIO_CLKB_B), GPIO_FN(SCIF_CLK_A), - GPIO_FN(DVC_MUTE), GPIO_FN(STP_IVCXO27_1_D), GPIO_FN(REMOCON_A), GPIO_FN(TCLK1_A), - GPIO_FN(VSP_B), GPIO_IFN(USB0_PWEN), GPIO_FN(SIM0_RST_C), GPIO_FN(TS_SCK1_D), GPIO_FN(STP_ISCLK_1_D), GPIO_FN(BPFCLK_B), GPIO_FN(RIF3_CLK_B), - GPIO_FN(SCKZ_B), + GPIO_FN(HSCK2_C), GPIO_IFN(USB0_OVC), GPIO_FN(SIM0_D_C), GPIO_FN(TS_SDAT1_D), GPIO_FN(STP_ISD_1_D), GPIO_FN(RIF3_SYNC_B), - GPIO_FN(VSP_C), + GPIO_FN(HRX2_C), GPIO_IFN(USB1_PWEN), GPIO_FN(SIM0_CLK_C), GPIO_FN(SSI_SCK1_A), @@ -3159,9 +3257,8 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(STP_ISCLK_0_E), GPIO_FN(FMCLK_B), GPIO_FN(RIF2_CLK_B), - GPIO_FN(MTSx_B), GPIO_FN(SPEEDIN_A), - GPIO_FN(VSP_D), + GPIO_FN(HTX2_C), GPIO_IFN(USB1_OVC), GPIO_FN(MSIOF1_SS2_C), GPIO_FN(SSI_WS1_A), @@ -3169,8 +3266,8 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(STP_ISD_0_E), GPIO_FN(FMIN_B), GPIO_FN(RIF2_SYNC_B), - GPIO_FN(STMx_B), GPIO_FN(REMOCON_B), + GPIO_FN(HCTS2x_C), GPIO_IFN(USB30_PWEN), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(SSI_SCK2_B), @@ -3178,9 +3275,10 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(STP_ISEN_1_D), GPIO_FN(STP_OPWM_0_E), GPIO_FN(RIF3_D0_B), - GPIO_FN(MDATA_B), GPIO_FN(TCLK2_B), GPIO_FN(TPU0TO0), + GPIO_FN(BPFCLK_C), + GPIO_FN(HRTS2x_C), GPIO_IFN(USB30_OVC), GPIO_FN(AUDIO_CLKOUT1_B), GPIO_FN(SSI_WS2_B), @@ -3188,25 +3286,8 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(STP_ISSYNC_1_D), GPIO_FN(STP_IVCXO27_0_E), GPIO_FN(RIF3_D1_B), - GPIO_FN(SDATA_B), - GPIO_FN(RSO_TOE_B), + GPIO_FN(FSO_TOEx), GPIO_FN(TPU0TO1), - - /* IPSR17 */ - GPIO_IFN(USB31_PWEN), - GPIO_FN(AUDIO_CLKOUT2_B), - GPIO_FN(SI_SCK9_B), - GPIO_FN(TS_SDEN0_E), - GPIO_FN(STP_ISEN_0_E), - GPIO_FN(RIF2_D0_B), - GPIO_FN(TPU0TO2), - GPIO_IFN(USB31_OVC), - GPIO_FN(AUDIO_CLKOUT3_B), - GPIO_FN(SSI_WS9_B), - GPIO_FN(TS_SPSYNC0_E), - GPIO_FN(STP_ISSYNC_0_E), - GPIO_FN(RIF2_D1_B), - GPIO_FN(TPU0TO3), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -3256,7 +3337,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - 0, 0, + GP_1_28_FN, GFN_CLKOUT, GP_1_27_FN, GFN_EX_WAIT0_A, GP_1_26_FN, GFN_WE1x, GP_1_25_FN, GFN_WE0x, @@ -3380,24 +3461,24 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - GP_4_17_FN, GPIO_FN_SD3_DS, + GP_4_17_FN, GFN_SD3_DS, GP_4_16_FN, GFN_SD3_DAT7, GP_4_15_FN, GFN_SD3_DAT6, GP_4_14_FN, GFN_SD3_DAT5, GP_4_13_FN, GFN_SD3_DAT4, - GP_4_12_FN, FN_SD3_DAT3, - GP_4_11_FN, FN_SD3_DAT2, - GP_4_10_FN, FN_SD3_DAT1, - GP_4_9_FN, FN_SD3_DAT0, - GP_4_8_FN, FN_SD3_CMD, - GP_4_7_FN, FN_SD3_CLK, + GP_4_12_FN, GFN_SD3_DAT3, + GP_4_11_FN, GFN_SD3_DAT2, + GP_4_10_FN, GFN_SD3_DAT1, + GP_4_9_FN, GFN_SD3_DAT0, + GP_4_8_FN, GFN_SD3_CMD, + GP_4_7_FN, GFN_SD3_CLK, GP_4_6_FN, GFN_SD2_DS, GP_4_5_FN, GFN_SD2_DAT3, GP_4_4_FN, GFN_SD2_DAT2, GP_4_3_FN, GFN_SD2_DAT1, GP_4_2_FN, GFN_SD2_DAT0, - GP_4_1_FN, FN_SD2_CMD, + GP_4_1_FN, GFN_SD2_CMD, GP_4_0_FN, GFN_SD2_CLK } }, /* GPSR5 */ @@ -3410,7 +3491,6 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, GP_5_25_FN, GFN_MLB_DAT, GP_5_24_FN, GFN_MLB_SIG, - GP_5_23_FN, GFN_MLB_CLK, GP_5_22_FN, FN_MSIOF0_RXD, GP_5_21_FN, GFN_MSIOF0_SS2, @@ -3438,8 +3518,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { }, /* GPSR6 */ { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { - GP_6_31_FN, GFN_USB31_OVC, - GP_6_30_FN, GFN_USB31_PWEN, + GP_6_31_FN, GFN_USB3_OVC, + GP_6_30_FN, GFN_USB3_PWEN, GP_6_29_FN, GFN_USB30_OVC, GP_6_28_FN, GFN_USB30_PWEN, GP_6_27_FN, GFN_USB1_OVC, @@ -3468,8 +3548,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_4_FN, GFN_SSI_SDATA2_A, GP_6_3_FN, GFN_SSI_SDATA1_A, GP_6_2_FN, GFN_SSI_SDATA0, - GP_6_1_FN, GFN_SSI_WS0129, - GP_6_0_FN, GFN_SSI_SCK0129 } + GP_6_1_FN, GFN_SSI_WS01239, + GP_6_0_FN, GFN_SSI_SCK01239 } }, /* GPSR7 */ { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { @@ -3513,12 +3593,12 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 4, 4, 4, 4, 4, 4, 4, 4) { /* IPSR0_31_28 [4] */ IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, - FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, 0, + FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, FN_MSIOF3_SS1_E, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR0_27_24 [4] */ IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, - FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, 0, + FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, FN_MSIOF3_SS2_E, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR0_23_20 [4] */ @@ -3528,7 +3608,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IPSR0_19_16 [4] */ IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, - 0, 0, 0, 0, + 0, FN_FSCLKST2x_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR0_15_12 [4] */ @@ -3542,7 +3622,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR0_7_4 [4] */ - IFN_AVB_MAGIC, 0, FN_MSIOF2_S1_C, FN_SCK4_A, + IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3561,38 +3641,38 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, FN_PWM3_A, 0, 0, 0, 0, 0, 0, /* IPSR1_27_24 [4] */ - IFN_PWM2_A, FN_PWMFSW0, FN_A20, FN_HTX3_D, + IFN_PWM2_A, 0, 0, FN_HTX3_D, 0, 0, 0, 0, 0, FN_IETX_B, 0, 0, 0, 0, 0, 0, /* IPSR1_23_20 [4] */ - IFN_PWM1_A, 0, FN_A21, FN_HRX3_D, + IFN_PWM1_A, 0, 0, FN_HRX3_D, FN_VI4_DATA7_B, 0, 0, 0, 0, FN_IERX_B, 0, 0, 0, 0, 0, 0, /* IPSR1_19_16 [4] */ - IFN_PWM0, FN_AVB_AVTP_PPS, FN_A22, 0, + IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, FN_VI4_DATA6_B, 0, 0, 0, 0, FN_IECLK_B, 0, 0, 0, 0, 0, 0, /* IPSR1_15_12 [4] */ - IFN_IRQ5, FN_QSTB_QHE, FN_A23, FN_DU_EXVSYNC_DU_VSYNC, - FN_VI4_DATA5_B, 0, 0, 0, + IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, + FN_VI4_DATA5_B, FN_FSCLKST2x_B, 0, FN_MSIOF3_TXD_E, 0, FN_PWM6_B, 0, 0, 0, 0, 0, 0, /* IPSR1_11_8 [4] */ - IFN_IRQ4, FN_QSTH_QHS, FN_A24, FN_DU_EXHSYNC_DU_HSYNC, - FN_VI4_DATA4_B, 0, 0, 0, + IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, + FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, 0, FN_PWM5_B, 0, 0, 0, 0, 0, 0, /* IPSR1_7_4 [4] */ - IFN_IRQ3, FN_QSTVB_QVE, FN_A25, FN_DU_DOTCLKOUT1, - FN_VI4_DATA3_B, 0, 0, + IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, + FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, 0, FN_PWM4_B, 0, 0, 0, 0, 0, 0, /* IPSR1_3_0 [4] */ IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, - FN_VI4_DATA2_B, 0, 0, 0, + FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, 0, FN_PWM3_B, 0, 0, 0, 0, 0, 0 } @@ -3671,7 +3751,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { /* IPSR3_11_8 [4] */ IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, - FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0, + FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, 0, 0, 0, 0, 0, 0, /* IPSR3_7_4 [4] */ IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, @@ -3864,27 +3944,27 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, 4, 4, 4, 4, 4, 4, 4, 4) { /* IPSR8_31_28 [4] */ - IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, 0, + IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, FN_NFRBx_B, 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR8_27_24 [4] */ - IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, 0, + IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, FN_NFDATA15_B, 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR8_23_20 [4] */ - IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, 0, + IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, FN_NFDATA14_B, 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR8_19_16 [4] */ - IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, 0, + IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, FN_NFWPx_B, 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR8_15_12 [4] */ - IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, 0, + IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, FN_NFCEx_B, 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3908,86 +3988,86 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, 4, 4, 4, 4, 4, 4, 4, 4) { /* IPSR9_31_28 [4] */ - IFN_SD3_DAT5, FN_SD2_WP_A, 0, 0, + IFN_SD3_CLK, 0, FN_NFWEx, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR9_27_24 [4] */ - IFN_SD3_DAT4, FN_SD2_CD_A, 0, 0, - 0, 0, 0, 0, + IFN_SD2_DS, 0, FN_NFALE, 0, 0, 0, 0, 0, + FN_SATA_DEVSLP_B, 0, 0, 0, 0, 0, 0, 0, /* IPSR9_23_20 [4] */ - IFN_SD2_DS, 0, 0, 0, + IFN_SD2_DAT3, 0, FN_NFDATA13, 0, + 0, 0, 0, 0, 0, 0, 0, 0, - FN_SATA_DEVSLP_B, 0, 0, FN_VSP_A, 0, 0, 0, 0, /* IPSR9_19_16 [4] */ - IFN_SD2_DAT3, 0, 0, 0, + IFN_SD2_DAT2, 0, FN_NFDATA12, 0, + 0, 0, 0, 0, 0, 0, 0, 0, - 0, FN_SDATA_A, 0, 0, 0, 0, 0, 0, /* IPSR9_15_12 [4] */ - IFN_SD2_DAT2, 0, 0, 0, + IFN_SD2_DAT1, 0, FN_NFDATA11, 0, + 0, 0, 0, 0, 0, 0, 0, 0, - 0, FN_MDATA_A, 0, 0, 0, 0, 0, 0, /* IPSR9_11_8 [4] */ - IFN_SD2_DAT1, 0, 0, 0, + IFN_SD2_DAT0, 0, FN_NFDATA10, 0, + 0, 0, 0, 0, 0, 0, 0, 0, - 0, FN_STMx_A, 0, 0, 0, 0, 0, 0, /* IPSR9_7_4 [4] */ - IFN_SD2_DAT0, 0, 0, 0, + IFN_SD2_CMD, 0, FN_NFDATA9, 0, + 0, 0, 0, 0, 0, 0, 0, 0, - 0, FN_MTSx_A, 0, 0, 0, 0, 0, 0, /* IPSR9_3_0 [4] */ - IFN_SD2_CLK, 0, 0, 0, + IFN_SD2_CLK, 0, FN_NFDATA8, 0, + 0, 0, 0, 0, 0, 0, 0, 0, - 0, FN_SCKZ_A, 0, 0, 0, 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, 4, 4, 4, 4, 4, 4, 4, 4) { /* IPSR10_31_28 [4] */ - IFN_RX0, FN_HRX1_B, 0, 0, - 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, + IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR10_27_24 [4] */ - IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, - FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM__C, FN_RIF0_CLK_B, - 0, FN_ADICHS2, 0, 0, + IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR10_23_20 [4] */ - IFN_SD1_WP, 0, 0, 0, - 0, FN_SIM0_D_B, 0, 0, + IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR10_19_16 [4] */ - IFN_SD1_CD, 0, 0, 0, - 0, FN_SIM0_CLK_B, 0, 0, + IFN_SD3_DAT3, 0, FN_NFDATA3, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR10_15_12 [4] */ - IFN_SD0_WP, 0, 0, 0, - FN_SDA2_B, 0, 0, 0, + IFN_SD3_DAT2, 0, FN_NFDATA2, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR10_11_8 [4] */ - IFN_SD0_CD, 0, 0, 0, - FN_SCL2_B, FN_SIM0_RST_A, 0, 0, + IFN_SD3_DAT1, 0, FN_NFDATA1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR10_7_4 [4] */ - IFN_SD3_DAT7, FN_SD3_WP, 0, 0, + IFN_SD3_DAT0, 0, FN_NFDATA0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IPSR10_3_0 [4] */ - IFN_SD3_DAT6, FN_SD3_CD, 0, 0, + IFN_SD3_CMD, 0, FN_NFREx, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3996,268 +4076,311 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, 4, 4, 4, 4, 4, 4, 4, 4) { /* IPSR11_31_28 [4] */ + IFN_RX0, FN_HRX1_B, 0, 0, + 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_27_24 [4] */ + IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, + FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, FN_RIF0_CLK_B, + FN_ADICHS2, FN_SCK5_B, 0, 0, + 0, 0, 0, 0, + /* IPSR11_23_20 [4] */ + IFN_SD1_WP, 0, FN_NFCEx_A, 0, + 0, FN_SIM0_D_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_19_16 [4] */ + IFN_SD1_CD, 0, FN_NFRBx_A, 0, + 0, FN_SIM0_CLK_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_15_12 [4] */ + IFN_SD0_WP, 0, FN_NFDATA15_A, 0, + FN_SDA2_B, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_11_8 [4] */ + IFN_SD0_CD, 0, FN_NFDATA14_A, 0, + FN_SCL2_B, FN_SIM0_RST_A, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_7_4 [4] */ + IFN_SD3_DS, 0, FN_NFCLE, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_3_0 [4] */ + IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR12_31_28 [4] */ IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, 0, FN_ADICLK, 0, 0, 0, 0, 0, 0, - /* IPSR11_27_24 [4] */ + /* IPSR12_27_24 [4] */ IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, 0, FN_ADICHS0, 0, 0, 0, 0, 0, 0, - /* IPSR11_23_20 [4] */ + /* IPSR12_23_20 [4] */ IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, 0, FN_ADIDATA, 0, 0, - /* IPSR11_19_16 [4] */ + 0, 0, 0, 0, + /* IPSR12_19_16 [4] */ IFN_TX1_A, FN_HTX1_A, 0, 0, 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR11_15_12 [4] */ + /* IPSR12_15_12 [4] */ IFN_RX1_A, FN_HRX1_A, 0, 0, - 0, FN_TS_SDAT0_C, FN_STP_IDS_0_C, FN_RIF1_CLK_C, + 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR11_11_8 [4] */ + /* IPSR12_11_8 [4] */ IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, 0, FN_ADICHS1, 0, 0, 0, 0, 0, 0, - /* IPSR11_7_4 [4] */ + /* IPSR12_7_4 [4] */ IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, 0, 0, 0, 0, - /* IPSR11_3_0 [4] */ + /* IPSR12_3_0 [4] */ IFN_TX0, FN_HTX1_B, 0, 0, 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, 0, 0, 0, 0, - 0, 0, 0, 0, } }, - { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR12_31_28 [4] */ + /* IPSR13_31_28 [4] */ IFN_MSIOF0_SYNC, 0, 0, 0, 0, 0, 0, 0, - FN_AUDIO_CLKOUT_A, 0, 0, 0, - 0, 0, 0, 0, - /* IPSR12_27_24 [4] */ + FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, + 0, FN_BPFCLK_D, 0, 0, + /* IPSR13_27_24 [4] */ IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, FN_AUDIO_CLKOUT2_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR12_23_20 [4] */ + /* IPSR13_23_20 [4] */ IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, - FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D, - FN_RIF0_SYNC_C, - FN_AUDIO_CLKOUT1_A, FN_AD_NSCx, 0, 0, + FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, + FN_STP_ISSYNC_0_D, FN_RIF0_SYNC_C, + FN_AUDIO_CLKOUT1_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR12_19_16 [4] */ + /* IPSR13_19_16 [4] */ IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, - 0, FN_AD_DO, 0, 0, 0, 0, 0, 0, - /* IPSR12_15_12 [4] */ + 0, 0, 0, 0, + /* IPSR13_15_12 [4] */ IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, - FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, - 0, FN_AD_DI, 0, 0, + FN_SSI_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, 0, 0, 0, 0, - /* IPSR12_11_8 [4] */ + 0, 0, 0, 0, + /* IPSR13_11_8 [4] */ IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, - 0, FN_AD_CLK, 0, 0, + 0, 0, FN_RX5_B, 0, 0, 0, 0, 0, - /* IPSR12_7_4 [4] */ + /* IPSR13_7_4 [4] */ IFN_RX2_A, 0, 0, FN_SD2_WP_B, - FN_SDA1_A, FN_RDS_DATA_B, FN_RMIN_A, FN_RIF1_SYNC_C, - 0, FN_FSO_CEF_1_B, 0, 0, + FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, + 0, FN_FSO_CFE_1x, 0, 0, 0, 0, 0, 0, - /* IPSR12_3_0 [4] */ + /* IPSR13_3_0 [4] */ IFN_TX2_A, 0, 0, FN_SD2_CD_B, - FN_SCL1_A, FN_RSD_CLK_B, FN_FMCLK_A, FN_RIF1_D1_C, - 0, FN_FSO_CFE_0_B, 0, 0, - 0, 0, 0, 0, + FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, + 0, FN_FSO_CFE_0x, 0, 0, } }, - { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR13_31_28 [4] */ + /* IPSR14_31_28 [4] */ IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, 0, 0, 0, FN_MOUT2, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR13_27_24 [4] */ - IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0, - 0, 0, 0, FN_MOUT1, + /* IPSR14_27_24 [4] */ + IFN_SSI_WS01239, 0, FN_MSIOF1_SS1_F, 0, + 0, 0, 0, 0, FN_MOUT1, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR13_23_20 [4] */ - IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0, + /* IPSR14_23_20 [4] */ + IFN_SSI_SCK01239, 0, FN_MSIOF1_TXD_F, 0, 0, 0, 0, FN_MOUT0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR13_19_16 [4] */ + /* IPSR14_19_16 [4] */ IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR13_15_12 [4] */ + /* IPSR14_15_12 [4] */ IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, FN_SDA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR13_11_8 [4] */ + /* IPSR14_11_8 [4] */ IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, FN_SCL1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR13_7_4 [4] */ - IFN_MSIOF0_SS2, FN_TX5, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, - FN_SSI_WS2_A, FN_RDS_DATA_A, FN_STP_OPWM_0_D, 0, + /* IPSR14_7_4 [4] */ + IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, + FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, - /* IPSR13_3_0 [4] */ - IFN_MSIOF0_SS1, FN_RX5, 0, FN_AUDIO_CLKA_C, - FN_SSI_SCK2_A, FN_RDS_CLK_A, FN_STP_IVCXO27_0_C, 0, + 0, 0, 0, 0, + /* IPSR14_3_0 [4] */ + IFN_MSIOF0_SS1, FN_RX5_A, FN_NFWPx_A, FN_AUDIO_CLKA_C, + FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, 0, 0, 0, 0, } }, - { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR14_31_28 [4] */ + /* IPSR15_31_28 [4] */ IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, FN_RIF2_D1_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR14_27_24 [4] */ + /* IPSR15_27_24 [4] */ IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, FN_RIF2_SYNC_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR14_23_20 [4] */ + /* IPSR15_23_20 [4] */ IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, FN_RIF2_CLK_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR14_19_16 [4] */ + /* IPSR15_19_16 [4] */ IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, FN_RIF2_D0_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR14_15_12 [4] */ + /* IPSR15_15_12 [4] */ IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, 0, 0, FN_STP_IVCXO27_0_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR14_11_8 [4] */ + /* IPSR15_11_8 [4] */ IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, 0, 0, FN_STP_OPWM_0_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR14_7_4 [4] */ + /* IPSR15_7_4 [4] */ IFN_SSI_SDATA2_A, 0, 0, 0, FN_SSI_SCK1_B, 0, 0, FN_MOUT6, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR14_3_0 [4] */ + /* IPSR15_3_0 [4] */ IFN_SSI_SDATA1_A, 0, 0, 0, 0, 0, 0, FN_MOUT5, 0, 0, 0, 0, 0, 0, 0, 0, } }, - { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR15_31_28 [4] */ + /* IPSR16_31_28 [4] */ IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, - FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5, + FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5_A, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR15_27_24 [4] */ + /* IPSR16_27_24 [4] */ IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, - FN_EIF3_D1_A, 0, 0, 0, + FN_RIF3_D1_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR15_23_20 [4] */ + /* IPSR16_23_20 [4] */ IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, - 0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A, + 0, FN_TS_SDEN1_A, FN_STP_ISEN_1_A, FN_RIF1_D0_A, FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, - /* IPSR15_19_16 [4] */ + 0, 0, 0, 0, + /* IPSR16_19_16 [4] */ IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, - 0, FN_TS_SDT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, + 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, FN_RIF3_SYNC_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR15_15_12 [4] */ + /* IPSR16_15_12 [4] */ IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, FN_RIF3_CLK_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR15_11_8 [4] */ + /* IPSR16_11_8 [4] */ IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, - 0, 0, FN_RSD_DATA_C, 0, + 0, 0, 0, 0, FN_SATA_DEVSLP_A, 0, 0, 0, 0, 0, 0, 0, - /* IPSR15_7_4 [4] */ - IFN_SSI_WS6, FN_USB2_OVC, 0, FN_SIM0_D_D, + /* IPSR16_7_4 [4] */ + IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IPSR15_3_0 [4] */ - IFN_SSI_SCK6, FN_USB2_PWEN, 0, FN_SIM0_RST_D, - 0, 0, FN_RDS_CLK_C, 0, + /* IPSR16_3_0 [4] */ + IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, } - }, - { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, + { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, 4, 4, 4, 4, 4, 4, 4, 4) { - /* IPSR16_31_28 [4] */ - IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0, - FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, - FN_STP_IVCXO27_0_E, - FN_RIF3_D1_B, FN_SDATA_B, FN_RSO_TOE_B, FN_TPU0TO1, + /* IPSR17_31_28 [4] */ + IFN_USB30_OVC, 0, 0, FN_AUDIO_CLKOUT1_B, + FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, FN_STP_IVCXO27_0_E, + FN_RIF3_D1_B, 0, FN_FSO_TOEx, FN_TPU0TO1, 0, 0, 0, 0, - /* IPSR16_27_24 [4] */ + /* IPSR17_27_24 [4] */ IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, - FN_RIF3_D0_B, FN_MDATA_B, FN_TCLK2_B, FN_TPU0TO0, - 0, 0, 0, 0, - /* IPSR16_23_20 [4] */ + FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, + FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, + /* IPSR17_23_20 [4] */ IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, - FN_RIF2_SYNC_B, FN_STMx_B, FN_REMOCON_B, 0, - 0, 0, 0, 0, - /* IPSR16_19_16 [4] */ + FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, + 0, FN_HCTS2x_C, 0, 0, + /* IPSR17_19_16 [4] */ IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, - FN_RIF2_CLK_B, FN_MTSx_B, FN_SPEEDIN_A, FN_VSP_D, - 0, 0, 0, 0, - /* IPSR16_15_12 [4] */ + FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, + 0, FN_HTX2_C, 0, 0, + /* IPSR17_15_12 [4] */ IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, - FN_RIF3_SYNC_B, 0, 0, FN_VSP_C, - 0, 0, 0, 0, - /* IPSR16_11_8 [4] */ + FN_RIF3_SYNC_B, 0, 0, 0, + 0, FN_HRX2_C, 0, 0, + /* IPSR17_11_8 [4] */ IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, - FN_RIF3_CLK_B, FN_SCKZ_B, 0, 0, - 0, 0, 0, 0, - /* IPSR16_7_4 [4] */ + FN_RIF3_CLK_B, 0, 0, 0, + 0, FN_HSCK2_C, 0, 0, + /* IPSR17_7_4 [4] */ IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, - FN_DVC_MUTE, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, - 0, 0, FN_TCLK1_A, FN_VSP_B, + 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, + 0, 0, FN_TCLK1_A, 0, 0, 0, 0, 0, - /* IPSR16_3_0 [4] */ + /* IPSR17_3_0 [4] */ IFN_AUDIO_CLKA_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FN_CC5_OSCOUT, 0, 0, 0, 0, } }, - { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, + { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -4289,201 +4412,195 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - /* IPSR17_7_4 [4] */ - IFN_USB31_OVC, 0, 0, FN_AUDIO_CLKOUT3_B, + /* IPSR18_7_4 [4] */ + IFN_USB3_OVC, 0, 0, FN_AUDIO_CLKOUT3_B, FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, - 0, 0, 0, 0, - /* IPSR17_3_0 [4] */ - IFN_USB31_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B, - FN_SI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, + FN_FMIN_C, FN_FMIN_D, 0, 0, + /* IPSR18_3_0 [4] */ + IFN_USB3_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B, + FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, FN_RIF2_D0_B, 0, 0, FN_TPU0TO2, - 0, 0, 0, 0, + FN_FMCLK_C, FN_FMCLK_D, 0, 0, } }, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, - 1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, - 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) { - /* RESERVED [1] */ - 0, 0, - /* SEL_MSIOF3 [2] */ + 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, + 1, 2, 1, 1, 1, 2, 2, 1, 2, 1, 1, 1) { + /* MOD_SEL0 */ + /* sel_msiof3[3](0,1,2,3,4) */ FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, - /* SEL_MSIOF2 [2] */ + FN_SEL_MSIOF3_4, 0, + 0, 0, + /* sel_msiof2[2](0,1,2,3) */ FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, - /* SEL_MSIOF1 [3] */ + /* sel_msiof1[3](0,1,2,3,4,5,6) */ FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, FN_SEL_MSIOF1_6, 0, - /* SEL_LBSC [1] */ + /* sel_lbsc[1](0,1) */ FN_SEL_LBSC_0, FN_SEL_LBSC_1, - /* SEL_IEBUS [1] */ + /* sel_iebus[1](0,1) */ FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, - /* SEL_I2C6 [2] */ - FN_SEL_I2C6_0, FN_SEL_I2C6_1, - FN_SEL_I2C6_2, 0, - /* SEL_I2C2 [1] */ + /* sel_i2c2[1](0,1) */ FN_SEL_I2C2_0, FN_SEL_I2C2_1, - /* SEL_I2C1 [1] */ + /* sel_i2c1[1](0,1) */ FN_SEL_I2C1_0, FN_SEL_I2C1_1, - /* SEL_HSCIF4 [1] */ + /* sel_hscif4[1](0,1) */ FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, - /* SEL_HSCIF3 [2] */ + /* sel_hscif3[2](0,1,2,3) */ FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, - /* SEL_HSCIF2 [1] */ - FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, - /* SEL_HSCIF1 [1] */ + /* sel_hscif1[1](0,1) */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* SEL_FSO [1] */ - 0, FN_SEL_FSO_1, - /* SEL_FM [1] */ - FN_SEL_FM_0, FN_SEL_FM_1, - /* SEL_ETHERAVB [1] */ + /* reserved[1] */ + 0, 0, + /* sel_hscif2[2](0,1,2) */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, 0, + /* sel_etheravb[1](0,1) */ FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, - /* SEL_DRIF3 [1] */ + /* sel_drif3[1](0,1) */ FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, - /* SEL_DRIF2 [1] */ + /* sel_drif2[1](0,1) */ FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, - /* SEL_DRIF1 [2] */ + /* sel_drif1[2](0,1,2) */ FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, FN_SEL_DRIF1_2, 0, - /* SEL_DRIF0 [2] */ + /* sel_drif0[2](0,1,2) */ FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, FN_SEL_DRIF0_2, 0, - /* SEL_CANFD0 [1] */ + /* sel_canfd0[1](0,1) */ FN_SEL_CANFD_0, FN_SEL_CANFD_1, - /* SEL_ADG [2] */ - FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_ADG_2, FN_SEL_ADG_3, - /* SEL_5LINE [1] */ - FN_SEL_5LINE_0, FN_SEL_5LINE_1, + /* sel_adg_a[2](0,1,2) */ + FN_SEL_ADG_A_0, FN_SEL_ADG_A_1, + FN_SEL_ADG_A_2, 0, + /* reserved[3]*/ + 0, 0, + 0, 0, + 0, 0, } }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, - 1, 1, 1, 1, 1, 1, 1) { - /* SEL_TSIF1 [2] */ - FN_SEL_TSIF1_0, - FN_SEL_TSIF1_1, - FN_SEL_TSIF1_2, - FN_SEL_TSIF1_3, - /* SEL_TSIF0 [3] */ - FN_SEL_TSIF0_0, - FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, - FN_SEL_TSIF0_3, - FN_SEL_TSIF0_4, - 0, - 0, - 0, - /* SEL_TIMER_TMU [1] */ - FN_SEL_TIMER_TMU_0, - FN_SEL_TIMER_TMU_1, - /* SEL_SSP1_1 [2] */ - FN_SEL_SSP1_1_0, - FN_SEL_SSP1_1_1, - FN_SEL_SSP1_1_2, - FN_SEL_SSP1_1_3, - /* SEL_SSP1_0 [3] */ - FN_SEL_SSP1_0_0, - FN_SEL_SSP1_0_1, - FN_SEL_SSP1_0_2, - FN_SEL_SSP1_0_3, - FN_SEL_SSP1_0_4, - 0, - 0, - 0, - /* SEL_SSI [1] */ - FN_SEL_SSI_0, - FN_SEL_SSI_1, - /* SEL_SPEED_PULSE_IF [1] */ - FN_SEL_SPEED_PULSE_IF_0, - FN_SEL_SPEED_PULSE_IF_1, - /* SEL_SIMCARD [2] */ - FN_SEL_SIMCARD_0, - FN_SEL_SIMCARD_1, - FN_SEL_SIMCARD_2, - FN_SEL_SIMCARD_3, - /* SEL_SDHI2 [1] */ - FN_SEL_SDHI2_0, - FN_SEL_SDHI2_1, - /* SEL_SCIF4 [2] */ - FN_SEL_SCIF4_0, - FN_SEL_SCIF4_1, - FN_SEL_SCIF4_2, - 0, - /* SEL_SCIF3 [1] */ - FN_SEL_SCIF3_0, - FN_SEL_SCIF3_1, - /* SEL_SCIF2 [1] */ - FN_SEL_SCIF2_0, - FN_SEL_SCIF2_1, - /* SEL_SCIF1 [1] */ - FN_SEL_SCIF1_0, - FN_SEL_SCIF1_1, - /* SEL_SCIF [1] */ - FN_SEL_SCIF_0, - FN_SEL_SCIF_1, - /* SEL_REMOCON [1] */ - FN_SEL_REMOCON_0, - FN_SEL_REMOCON_1, - /* SEL_RDS [2] */ - FN_SEL_RDS_0, - FN_SEL_RDS_1, - FN_SEL_RDS_2, - 0, - /* SEL_RCAN [1] */ - FN_SEL_RCAN_0, - FN_SEL_RCAN_1, - /* SEL_PWM6 [1] */ - FN_SEL_PWM6_0, - FN_SEL_PWM6_1, - /* SEL_PWM5 [1] */ - FN_SEL_PWM5_0, - FN_SEL_PWM5_1, - /* SEL_PWM4 [1] */ - FN_SEL_PWM4_0, - FN_SEL_PWM4_1, - /* SEL_PWM3 [1] */ - FN_SEL_PWM3_0, - FN_SEL_PWM3_1, - /* SEL_PWM2 [1] */ - FN_SEL_PWM2_0, - FN_SEL_PWM2_1, - /* SEL_PWM1 [1] */ - FN_SEL_PWM1_0, - FN_SEL_PWM1_1, + 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* sel_tsif1[2](0,1,2,3) */ + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, + FN_SEL_TSIF1_2, FN_SEL_TSIF1_3, + /* sel_tsif0[3](0,1,2,3,4) */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_TSIF0_4, 0, + 0, 0, + /* sel_timer_tmu1[1](0,1) */ + FN_SEL_TIMER_TMU1_0, FN_SEL_TIMER_TMU1_1, + /* sel_ssp1_1[2](0,1,2,3) */ + FN_SEL_SSP1_1_0, FN_SEL_SSP1_1_1, + FN_SEL_SSP1_1_2, FN_SEL_SSP1_1_3, + /* sel_ssp1_0[3](0,1,2,3,4) */ + FN_SEL_SSP1_0_0, FN_SEL_SSP1_0_1, + FN_SEL_SSP1_0_2, FN_SEL_SSP1_0_3, + FN_SEL_SSP1_0_4, 0, + 0, 0, + /* sel_ssi1[1](0,1) */ + FN_SEL_SSI_0, FN_SEL_SSI_1, + /* sel_speed_pulse_if[1](0,1) */ + FN_SEL_SPEED_PULSE_IF_0, FN_SEL_SPEED_PULSE_IF_1, + /* sel_simcard[2](0,1,2,3) */ + FN_SEL_SIMCARD_0, FN_SEL_SIMCARD_1, + FN_SEL_SIMCARD_2, FN_SEL_SIMCARD_3, + /* sel_sdhi2[1](0,1) */ + FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, + /* sel_scif4[2](0,1,2) */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, + FN_SEL_SCIF4_2, 0, + /* sel_scif3[1](0,1) */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + /* sel_scif2[1](0,1) */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, + /* sel_scif1[1](0,1) */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, + /* sel_scif[1](0,1) */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* sel_remocon[1](0,1) */ + FN_SEL_REMOCON_0, FN_SEL_REMOCON_1, + /* reserved[8..7] */ + 0, 0, + 0, 0, + /* sel_rcan0[1](0,1) */ + FN_SEL_RCAN_0, FN_SEL_RCAN_1, + /* sel_pwm6[1](0,1) */ + FN_SEL_PWM6_0, FN_SEL_PWM6_1, + /* sel_pwm5[1](0,1) */ + FN_SEL_PWM5_0, FN_SEL_PWM5_1, + /* sel_pwm4[1](0,1) */ + FN_SEL_PWM4_0, FN_SEL_PWM4_1, + /* sel_pwm3[1](0,1) */ + FN_SEL_PWM3_0, FN_SEL_PWM3_1, + /* sel_pwm2[1](0,1) */ + FN_SEL_PWM2_0, FN_SEL_PWM2_1, + /* sel_pwm1[1](0,1) */ + FN_SEL_PWM1_0, FN_SEL_PWM1_1, } }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, - 1, 1, 1, 26, 2, 1) { - /* I2C_SEL_5 [1] */ - FN_I2C_SEL_5_0, - FN_I2C_SEL_5_1, - /* I2C_SEL_3 [1] */ - FN_I2C_SEL_3_0, - FN_I2C_SEL_3_1, - /* I2C_SEL_0 [1] */ - FN_I2C_SEL_0_0, - FN_I2C_SEL_0_1, - /* reserved [26] */ - /* SEL_VSP [2] */ - FN_SEL_VSP_0, - FN_SEL_VSP_1, - FN_SEL_VSP_2, - FN_SEL_VSP_3, - /* SEL_VIN4 [1] */ - FN_SEL_VIN4_0, - FN_SEL_VIN4_1, + 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* i2c_sel_5[1](0,1) */ + FN_I2C_SEL_5_0, FN_I2C_SEL_5_1, + /* i2c_sel_3[1](0,1) */ + FN_I2C_SEL_3_0, FN_I2C_SEL_3_1, + /* i2c_sel_0[1](0,1) */ + FN_I2C_SEL_0_0, FN_I2C_SEL_0_1, + /* sel_fm[2](0,1,2,3) */ + FN_SEL_FM_0, FN_SEL_FM_1, + FN_SEL_FM_2, FN_SEL_FM_3, + /* sel_scif5[1](0,1) */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* sel_i2c6[3](0,1,2) */ + FN_SEL_I2C6_0, FN_SEL_I2C6_1, + FN_SEL_I2C6_2, 0, + /* sel_ndfc[1](0,1) */ + FN_SEL_NDFC_0, FN_SEL_NDFC_1, + /* sel_ssi2[1](0,1) */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + /* sel_ssi9[1](0,1) */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* sel_timer_tmu2[1](0,1) */ + FN_SEL_TIMER_TMU2_0, FN_SEL_TIMER_TMU2_1, + /* sel_adg_b[1](0,1) */ + FN_SEL_ADG_B_0, FN_SEL_ADG_B_1, + /* sel_adg_c[1](0,1) */ + FN_SEL_ADG_C_0, FN_SEL_ADG_C_1, + /* reserved[16..16] */ + 0, 0, + /* reserved[15..8] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* reserved[7..1] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* sel_vin4[1](0,1) */ + FN_SEL_VIN4_0, FN_SEL_VIN4_1, } }, - - /* under construction */ { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { 0, 0, 0, 0, @@ -4525,7 +4642,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - 0, 0, + GP_1_28_IN, GP_1_28_OUT, GP_1_27_IN, GP_1_27_OUT, GP_1_26_IN, GP_1_26_OUT, GP_1_25_IN, GP_1_25_OUT, @@ -4760,7 +4877,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } }, { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { - 0, 0, 0, 0, + 0, 0, 0, GP_1_28_DATA, GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, @@ -4813,8 +4930,10 @@ static struct pinmux_data_reg pinmux_data_regs[] = { 0, 0, 0, 0, GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } }, + { }, }; + static struct pinmux_info r8a7795_pinmux_info = { .name = "r8a7795_pfc", @@ -4828,7 +4947,7 @@ static struct pinmux_info r8a7795_pinmux_info = { .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, .first_gpio = GPIO_GP_0_0, - .last_gpio = GPIO_FN_TPU0TO3, + .last_gpio = GPIO_FN_FMIN_D, .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, diff --git a/arch/arm/mach-rmobile/pfc-r8a7796.c b/arch/arm/mach-rmobile/pfc-r8a7796.c new file mode 100644 index 0000000000..f734f96dd0 --- /dev/null +++ b/arch/arm/mach-rmobile/pfc-r8a7796.c @@ -0,0 +1,5253 @@ +/* + * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7796.c + * This file is r8a7796 processor support - PFC hardware block. + * + * Copyright (C) 2016 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#define CPU_32_PORT2(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#define CPU_32_PORT_29(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), \ + PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), \ + PORT_1(fn, pfx##25, sfx), \ + PORT_1(fn, pfx##26, sfx), \ + PORT_1(fn, pfx##27, sfx), \ + PORT_1(fn, pfx##28, sfx) + +#define CPU_32_PORT_26(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), \ + PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), \ + PORT_1(fn, pfx##25, sfx) + +#define CPU_32_PORT_18(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_1(fn, pfx##10, sfx), \ + PORT_1(fn, pfx##11, sfx), \ + PORT_1(fn, pfx##12, sfx), \ + PORT_1(fn, pfx##13, sfx), \ + PORT_1(fn, pfx##14, sfx), \ + PORT_1(fn, pfx##15, sfx), \ + PORT_1(fn, pfx##16, sfx), \ + PORT_1(fn, pfx##17, sfx) + +#define CPU_32_PORT_16(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_1(fn, pfx##10, sfx), \ + PORT_1(fn, pfx##11, sfx), \ + PORT_1(fn, pfx##12, sfx), \ + PORT_1(fn, pfx##13, sfx), \ + PORT_1(fn, pfx##14, sfx), \ + PORT_1(fn, pfx##15, sfx) + +#define CPU_32_PORT_15(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_1(fn, pfx##10, sfx), \ + PORT_1(fn, pfx##11, sfx), \ + PORT_1(fn, pfx##12, sfx), \ + PORT_1(fn, pfx##13, sfx), \ + PORT_1(fn, pfx##14, sfx) + +#define CPU_32_PORT_4(fn, pfx, sfx) \ + PORT_1(fn, pfx##0, sfx), \ + PORT_1(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##3, sfx) + + +/* --gen3-- */ +/* GP_0_0_DATA -> GP_7_4_DATA */ +/* except for GP0[16] - [31], + GP1[28] - [31], + GP2[15] - [31], + GP3[16] - [31], + GP4[18] - [31], + GP5[26] - [31], + GP7[4] - [31] */ + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT_16(fn, pfx##_0_, sfx), \ + CPU_32_PORT_29(fn, pfx##_1_, sfx), \ + CPU_32_PORT_15(fn, pfx##_2_, sfx), \ + CPU_32_PORT_16(fn, pfx##_3_, sfx), \ + CPU_32_PORT_18(fn, pfx##_4_, sfx), \ + CPU_32_PORT_26(fn, pfx##_5_, sfx), \ + CPU_32_PORT(fn, pfx##_6_, sfx), \ + CPU_32_PORT_4(fn, pfx##_7_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + GFN_D15, + GFN_D14, + GFN_D13, + GFN_D12, + GFN_D11, + GFN_D10, + GFN_D9, + GFN_D8, + GFN_D7, + GFN_D6, + GFN_D5, + GFN_D4, + GFN_D3, + GFN_D2, + GFN_D1, + GFN_D0, + + /* GPSR1 */ + GFN_CLKOUT, + GFN_EX_WAIT0_A, + GFN_WE1x, + GFN_WE0x, + GFN_RD_WRx, + GFN_RDx, + GFN_BSx, + GFN_CS1x_A26, + GFN_CS0x, + GFN_A19, + GFN_A18, + GFN_A17, + GFN_A16, + GFN_A15, + GFN_A14, + GFN_A13, + GFN_A12, + GFN_A11, + GFN_A10, + GFN_A9, + GFN_A8, + GFN_A7, + GFN_A6, + GFN_A5, + GFN_A4, + GFN_A3, + GFN_A2, + GFN_A1, + GFN_A0, + + /* GPSR2 */ + GFN_AVB_AVTP_CAPTURE_A, + GFN_AVB_AVTP_MATCH_A, + GFN_AVB_LINK, + GFN_AVB_PHY_INT, + GFN_AVB_MAGIC, + GFN_AVB_MDC, + GFN_PWM2_A, + GFN_PWM1_A, + GFN_PWM0, + GFN_IRQ5, + GFN_IRQ4, + GFN_IRQ3, + GFN_IRQ2, + GFN_IRQ1, + GFN_IRQ0, + + /* GPSR3 */ + GFN_SD1_WP, + GFN_SD1_CD, + GFN_SD0_WP, + GFN_SD0_CD, + GFN_SD1_DAT3, + GFN_SD1_DAT2, + GFN_SD1_DAT1, + GFN_SD1_DAT0, + GFN_SD1_CMD, + GFN_SD1_CLK, + GFN_SD0_DAT3, + GFN_SD0_DAT2, + GFN_SD0_DAT1, + GFN_SD0_DAT0, + GFN_SD0_CMD, + GFN_SD0_CLK, + + /* GPSR4 */ + GFN_SD3_DS, + GFN_SD3_DAT7, + GFN_SD3_DAT6, + GFN_SD3_DAT5, + GFN_SD3_DAT4, + FN_SD3_DAT3, + FN_SD3_DAT2, + FN_SD3_DAT1, + FN_SD3_DAT0, + FN_SD3_CMD, + FN_SD3_CLK, + GFN_SD2_DS, + GFN_SD2_DAT3, + GFN_SD2_DAT2, + GFN_SD2_DAT1, + GFN_SD2_DAT0, + FN_SD2_CMD, + GFN_SD2_CLK, + + /* GPSR5 */ + GFN_MLB_DAT, + GFN_MLB_SIG, + GFN_MLB_CLK, + FN_MSIOF0_RXD, + GFN_MSIOF0_SS2, + FN_MSIOF0_TXD, + GFN_MSIOF0_SS1, + GFN_MSIOF0_SYNC, + FN_MSIOF0_SCK, + GFN_HRTS0x, + GFN_HCTS0x, + GFN_HTX0, + GFN_HRX0, + GFN_HSCK0, + GFN_RX2_A, + GFN_TX2_A, + GFN_SCK2, + GFN_RTS1x_TANS, + GFN_CTS1x, + GFN_TX1_A, + GFN_RX1_A, + GFN_RTS0x_TANS, + GFN_CTS0x, + GFN_TX0, + GFN_RX0, + GFN_SCK0, + + /* GPSR6 */ + GFN_GP6_30, + GFN_GP6_31, + GFN_USB30_OVC, + GFN_USB30_PWEN, + GFN_USB1_OVC, + GFN_USB1_PWEN, + GFN_USB0_OVC, + GFN_USB0_PWEN, + GFN_AUDIO_CLKB_B, + GFN_AUDIO_CLKA_A, + GFN_SSI_SDATA9_A, + GFN_SSI_SDATA8, + GFN_SSI_SDATA7, + GFN_SSI_WS78, + GFN_SSI_SCK78, + GFN_SSI_SDATA6, + GFN_SSI_WS6, + GFN_SSI_SCK6, + FN_SSI_SDATA5, + FN_SSI_WS5, + FN_SSI_SCK5, + GFN_SSI_SDATA4, + GFN_SSI_WS4, + GFN_SSI_SCK4, + GFN_SSI_SDATA3, + GFN_SSI_WS34, + GFN_SSI_SCK34, + GFN_SSI_SDATA2_A, + GFN_SSI_SDATA1_A, + GFN_SSI_SDATA0, + GFN_SSI_WS01239, + GFN_SSI_SCK01239, + + /* GPSR7 */ + FN_HDMI1_CEC, + FN_HDMI0_CEC, + FN_AVS2, + FN_AVS1, + + /* IPSR0 */ + IFN_AVB_MDC, + FN_MSIOF2_SS2_C, + IFN_AVB_MAGIC, + FN_MSIOF2_SS1_C, + FN_SCK4_A, + IFN_AVB_PHY_INT, + FN_MSIOF2_SYNC_C, + FN_RX4_A, + IFN_AVB_LINK, + FN_MSIOF2_SCK_C, + FN_TX4_A, + IFN_AVB_AVTP_MATCH_A, + FN_MSIOF2_RXD_C, + FN_CTS4x_A, + IFN_AVB_AVTP_CAPTURE_A, + FN_MSIOF2_TXD_C, + FN_RTS4x_TANS_A, + IFN_IRQ0, + FN_QPOLB, + FN_DU_CDE, + FN_VI4_DATA0_B, + FN_CAN0_TX_B, + FN_CANFD0_TX_B, + FN_MSIOF3_SS2_E, + IFN_IRQ1, + FN_QPOLA, + FN_DU_DISP, + FN_VI4_DATA1_B, + FN_CAN0_RX_B, + FN_CANFD0_RX_B, + FN_MSIOF3_SS1_E, + + /* IPSR1 */ + IFN_IRQ2, + FN_QCPV_QDE, + FN_DU_EXODDF_DU_ODDF_DISP_CDE, + FN_VI4_DATA2_B, + FN_MSIOF3_SYNC_E, + FN_PWM3_B, + IFN_IRQ3, + FN_QSTVB_QVE, + FN_DU_DOTCLKOUT1, + FN_VI4_DATA3_B, + FN_MSIOF3_SCK_E, + FN_PWM4_B, + IFN_IRQ4, + FN_QSTH_QHS, + FN_DU_EXHSYNC_DU_HSYNC, + FN_VI4_DATA4_B, + FN_MSIOF3_RXD_E, + FN_PWM5_B, + IFN_IRQ5, + FN_QSTB_QHE, + FN_DU_EXVSYNC_DU_VSYNC, + FN_VI4_DATA5_B, + FN_MSIOF3_TXD_E, + FN_PWM6_B, + IFN_PWM0, + FN_AVB_AVTP_PPS, + FN_VI4_DATA6_B, + FN_IECLK_B, + IFN_PWM1_A, + FN_HRX3_D, + FN_VI4_DATA7_B, + FN_IERX_B, + IFN_PWM2_A, + FN_PWMFSW0, + FN_HTX3_D, + FN_IETX_B, + IFN_A0, + FN_LCDOUT16, + FN_MSIOF3_SYNC_B, + FN_VI4_DATA8, + FN_DU_DB0, + FN_PWM3_A, + + /* IPSR2 */ + IFN_A1, + FN_LCDOUT17, + FN_MSIOF3_TXD_B, + FN_VI4_DATA9, + FN_DU_DB1, + FN_PWM4_A, + IFN_A2, + FN_LCDOUT18, + FN_MSIOF3_SCK_B, + FN_VI4_DATA10, + FN_DU_DB2, + FN_PWM5_A, + IFN_A3, + FN_LCDOUT19, + FN_MSIOF3_RXD_B, + FN_VI4_DATA11, + FN_DU_DB3, + FN_PWM6_A, + IFN_A4, + FN_LCDOUT20, + FN_MSIOF3_SS1_B, + FN_VI4_DATA12, + FN_VI5_DATA12, + FN_DU_DB4, + IFN_A5, + FN_LCDOUT21, + FN_MSIOF3_SS2_B, + FN_SCK4_B, + FN_VI4_DATA13, + FN_VI5_DATA13, + FN_DU_DB5, + IFN_A6, + FN_LCDOUT22, + FN_MSIOF2_SS1_A, + FN_RX4_B, + FN_VI4_DATA14, + FN_VI5_DATA14, + FN_DU_DB6, + IFN_A7, + FN_LCDOUT23, + FN_MSIOF2_SS2_A, + FN_TX4_B, + FN_VI4_DATA15, + FN_V15_DATA15, + FN_DU_DB7, + IFN_A8, + FN_RX3_B, + FN_MSIOF2_SYNC_A, + FN_HRX4_B, + FN_SDA6_A, + FN_AVB_AVTP_MATCH_B, + FN_PWM1_B, + + /* IPSR3 */ + IFN_A9, + FN_MSIOF2_SCK_A, + FN_CTS4x_B, + FN_VI5_VSYNCx, + IFN_A10, + FN_MSIOF2_RXD_A, + FN_RTS4n_TANS_B, + FN_VI5_HSYNCx, + IFN_A11, + FN_TX3_B, + FN_MSIOF2_TXD_A, + FN_HTX4_B, + FN_HSCK4, + FN_VI5_FIELD, + FN_SCL6_A, + FN_AVB_AVTP_CAPTURE_B, + FN_PWM2_B, + FN_SPV_EVEN, + IFN_A12, + FN_LCDOUT12, + FN_MSIOF3_SCK_C, + FN_HRX4_A, + FN_VI5_DATA8, + FN_DU_DG4, + IFN_A13, + FN_LCDOUT13, + FN_MSIOF3_SYNC_C, + FN_HTX4_A, + FN_VI5_DATA9, + FN_DU_DG5, + IFN_A14, + FN_LCDOUT14, + FN_MSIOF3_RXD_C, + FN_HCTS4x, + FN_VI5_DATA10, + FN_DU_DG6, + IFN_A15, + FN_LCDOUT15, + FN_MSIOF3_TXD_C, + FN_HRTS4x, + FN_VI5_DATA11, + FN_DU_DG7, + IFN_A16, + FN_LCDOUT8, + FN_VI4_FIELD, + FN_DU_DG0, + + /* IPSR4 */ + IFN_A17, + FN_LCDOUT9, + FN_VI4_VSYNCx, + FN_DU_DG1, + IFN_A18, + FN_LCDOUT10, + FN_VI4_HSYNCx, + FN_DU_DG2, + IFN_A19, + FN_LCDOUT11, + FN_VI4_CLKENB, + FN_DU_DG3, + IFN_CS0x, + FN_VI5_CLKENB, + IFN_CS1x_A26, + FN_VI5_CLK, + FN_EX_WAIT0_B, + IFN_BSx, + FN_QSTVA_QVS, + FN_MSIOF3_SCK_D, + FN_SCK3, + FN_HSCK3, + FN_CAN1_TX, + FN_CANFD1_TX, + FN_IETX_A, + IFN_RDx, + FN_MSIOF3_SYNC_D, + FN_RX3_A, + FN_HRX3_A, + FN_CAN0_TX_A, + FN_CANFD0_TX_A, + IFN_RD_WRx, + FN_MSIOF3_RXD_D, + FN_TX3_A, + FN_HTX3_A, + FN_CAN0_RX_A, + FN_CANFD0_RX_A, + + /* IPSR5 */ + IFN_WE0x, + FN_MSIIOF3_TXD_D, + FN_CTS3x, + FN_HCTS3x, + FN_SCL6_B, + FN_CAN_CLK, + FN_IECLK_A, + IFN_WE1x, + FN_MSIOF3_SS1_D, + FN_RTS3x_TANS, + FN_HRTS3x, + FN_SDA6_B, + FN_CAN1_RX, + FN_CANFD1_RX, + FN_IERX_A, + IFN_EX_WAIT0_A, + FN_QCLK, + FN_VI4_CLK, + FN_DU_DOTCLKOUT0, + IFN_D0, + FN_MSIOF2_SS1_B, + FN_MSIOF3_SCK_A, + FN_VI4_DATA16, + FN_VI5_DATA0, + IFN_D1, + FN_MSIOF2_SS2_B, + FN_MSIOF3_SYNC_A, + FN_VI4_DATA17, + FN_VI5_DATA1, + IFN_D2, + FN_MSIOF3_RXD_A, + FN_VI4_DATA18, + FN_VI5_DATA2, + IFN_D3, + FN_MSIOF3_TXD_A, + FN_VI4_DATA19, + FN_VI5_DATA3, + IFN_D4, + FN_MSIOF2_SCK_B, + FN_VI4_DATA20, + FN_VI5_DATA4, + + /* IPSR6 */ + IFN_D5, + FN_MSIOF2_SYNC_B, + FN_VI4_DATA21, + FN_VI5_DATA5, + IFN_D6, + FN_MSIOF2_RXD_B, + FN_VI4_DATA22, + FN_VI5_DATA6, + IFN_D7, + FN_MSIOF2_TXD_B, + FN_VI4_DATA23, + FN_VI5_DATA7, + IFN_D8, + FN_LCDOUT0, + FN_MSIOF2_SCK_D, + FN_SCK4_C, + FN_VI4_DATA0_A, + FN_DU_DR0, + IFN_D9, + FN_LCDOUT1, + FN_MSIOF2_SYNC_D, + FN_VI4_DATA1_A, + FN_DU_DR1, + IFN_D10, + FN_LCDOUT2, + FN_MSIOF2_RXD_D, + FN_HRX3_B, + FN_VI4_DATA2_A, + FN_CTS4x_C, + FN_DU_DR2, + IFN_D11, + FN_LCDOUT3, + FN_MSIOF2_TXD_D, + FN_HTX3_B, + FN_VI4_DATA3_A, + FN_RTS4x_TANS_C, + FN_DU_DR3, + IFN_D12, + FN_LCDOUT4, + FN_MSIOF2_SS1_D, + FN_RX4_C, + FN_VI4_DATA4_A, + FN_DU_DR4, + + /* IPSR7 */ + IFN_D13, + FN_LCDOUT5, + FN_MSIOF2_SS2_D, + FN_TX4_C, + FN_VI4_DATA5_A, + FN_DU_DR5, + IFN_D14, + FN_LCDOUT6, + FN_MSIOF3_SS1_A, + FN_HRX3_C, + FN_VI4_DATA6_A, + FN_DU_DR6, + FN_SCL6_C, + IFN_D15, + FN_LCDOUT7, + FN_MSIOF3_SS2_A, + FN_HTX3_C, + FN_VI4_DATA7_A, + FN_DU_DR7, + FN_SDA6_C, + FN_FSCLKST, + IFN_SD0_CLK, + FN_MSIOF1_SCK_E, + FN_STP_OPWM_0_B, + IFN_SD0_CMD, + FN_MSIOF1_SYNC_E, + FN_STP_IVCXO27_0_B, + IFN_SD0_DAT0, + FN_MSIOF1_RXD_E, + FN_TS_SCK0_B, + FN_STP_ISCLK_0_B, + IFN_SD0_DAT1, + FN_MSIOF1_TXD_E, + FN_TS_SPSYNC0_B, + FN_STP_ISSYNC_0_B, + + /* IPSR8 */ + IFN_SD0_DAT2, + FN_MSIOF1_SS1_E, + FN_TS_SDAT0_B, + FN_STP_ISD_0_B, + + IFN_SD0_DAT3, + FN_MSIOF1_SS2_E, + FN_TS_SDEN0_B, + FN_STP_ISEN_0_B, + + IFN_SD1_CLK, + FN_MSIOF1_SCK_G, + FN_SIM0_CLK_A, + + IFN_SD1_CMD, + FN_MSIOF1_SYNC_G, + FN_NFCEx_B, + FN_SIM0_D_A, + FN_STP_IVCXO27_1_B, + + IFN_SD1_DAT0, + FN_SD2_DAT4, + FN_MSIOF1_RXD_G, + FN_NFWPx_B, + FN_TS_SCK1_B, + FN_STP_ISCLK_1_B, + + IFN_SD1_DAT1, + FN_SD2_DAT5, + FN_MSIOF1_TXD_G, + FN_NFDATA14_B, + FN_TS_SPSYNC1_B, + FN_STP_ISSYNC_1_B, + + IFN_SD1_DAT2, + FN_SD2_DAT6, + FN_MSIOF1_SS1_G, + FN_NFDATA15_B, + FN_TS_SDAT1_B, + FN_STP_IOD_1_B, + + IFN_SD1_DAT3, + FN_SD2_DAT7, + FN_MSIOF1_SS2_G, + FN_NFRBx_B, + FN_TS_SDEN1_B, + FN_STP_ISEN_1_B, + + /* IPSR9 */ + IFN_SD2_CLK, + FN_NFDATA8, + + IFN_SD2_CMD, + FN_NFDATA9, + + IFN_SD2_DAT0, + FN_NFDATA10, + + IFN_SD2_DAT1, + FN_NFDATA11, + + IFN_SD2_DAT2, + FN_NFDATA12, + + IFN_SD2_DAT3, + FN_NFDATA13, + + IFN_SD2_DS, + FN_NFALE, + + IFN_SD3_CLK, + FN_NFWEx, + + /* IPSR10 */ + IFN_SD3_CMD, + FN_NFREx, + + IFN_SD3_DAT0, + FN_NFDATA0, + + IFN_SD3_DAT1, + FN_NFDATA1, + + IFN_SD3_DAT2, + FN_NFDATA2, + + IFN_SD3_DAT3, + FN_NFDATA3, + + IFN_SD3_DAT4, + FN_SD2_CD_A, + FN_NFDATA4, + + IFN_SD3_DAT5, + FN_SD2_WP_A, + FN_NFDATA5, + + IFN_SD3_DAT6, + FN_SD3_CD, + FN_NFDATA6, + + /* IPSR11 */ + IFN_SD3_DAT7, + FN_SD3_WP, + FN_NFDATA7, + + IFN_SD3_DS, + FN_NFCLE, + + IFN_SD0_CD, + FN_NFDATA14_A, + FN_SCL2_B, + FN_SIM0_RST_A, + + IFN_SD0_WP, + FN_NFDATA15_A, + FN_SDA2_B, + + IFN_SD1_CD, + FN_NFRBx_A, + FN_SIM0_CLK_B, + + IFN_SD1_WP, + FN_NFCEx_A, + FN_SIM0_D_B, + + IFN_SCK0, + FN_HSCK1_B, + FN_MSIOF1_SS2_B, + FN_AUDIO_CLKC_B, + FN_SDA2_A, + FN_SIM0_RST_B, + FN_STP_OPWM_0_C, + FN_RIF0_CLK_B, + FN_ADICHS2, + FN_SCK5_B, + + IFN_RX0, + FN_HRX1_B, + FN_TS_SCK0_C, + FN_STP_ISCLK_0_C, + FN_RIF0_D0_B, + + /* IPSR12 */ + IFN_TX0, + FN_HTX1_B, + FN_TS_SPSYNC0_C, + FN_STP_ISSYNC_0_C, + FN_RIF0_D1_B, + + IFN_CTS0x, + FN_HCTS1x_B, + FN_MSIOF1_SYNC_B, + FN_TS_SPSYNC1_C, + FN_STP_ISSYNC_1_C, + FN_RIF1_SYNC_B, + FN_AUDIO_CLKOUT_C, + FN_ADICS_SAMP, + + IFN_RTS0x_TANS, + FN_HRTS1x_B, + FN_MSIOF1_SS1_B, + FN_AUDIO_CLKA_B, + FN_SCL2_A, + FN_STP_IVCXO27_1_C, + FN_RIF0_SYNC_B, + FN_ADICHS1, + + IFN_RX1_A, + FN_HRX1_A, + FN_TS_SDAT0_C, + FN_STP_ISD_0_C, + FN_RIF1_CLK_C, + + IFN_TX1_A, + FN_HTX1_A, + FN_TS_SDEN0_C, + FN_STP_ISEN_0_C, + FN_RIF1_D0_C, + + IFN_CTS1x, + FN_HCTS1x_A, + FN_MSIOF1_RXD_B, + FN_TS_SDEN1_C, + FN_STP_ISEN_1_C, + FN_RIF1_D0_B, + FN_ADIDATA, + + IFN_RTS1x_TANS, + FN_HRTS1x_A, + FN_MSIOF1_TXD_B, + FN_TS_SDAT1_C, + FN_STP_ISD_1_C, + FN_RIF1_D1_B, + FN_ADICHS0, + + IFN_SCK2, + FN_SCIF_CLK_B, + FN_MSIOF1_SCK_B, + FN_TS_SCK1_C, + FN_STP_ISCLK_1_C, + FN_RIF1_CLK_B, + FN_ADICLK, + + /* IPSR13 */ + IFN_TX2_A, + FN_SD2_CD_B, + FN_SCL1_A, + FN_FMCLK_A, + FN_RIF1_D1_C, + FN_FSO_CFE_0_B, + + IFN_RX2_A, + FN_SD2_WP_B, + FN_SDA1_A, + FN_FMIN_A, + FN_RIF1_SYNC_C, + FN_FSO_CEF_1_B, + + IFN_HSCK0, + FN_MSIOF1_SCK_D, + FN_AUDIO_CLKB_A, + FN_SSI_SDATA1_B, + FN_TS_SCK0_D, + FN_STP_ISCLK_0_D, + FN_RIF0_CLK_C, + FN_RX5_B, + + IFN_HRX0, + FN_MSIOF1_RXD_D, + FN_SS1_SDATA2_B, + FN_TS_SDEN0_D, + FN_STP_ISEN_0_D, + FN_RIF0_D0_C, + + IFN_HTX0, + FN_MSIOF1_TXD_D, + FN_SSI_SDATA9_B, + FN_TS_SDAT0_D, + FN_STP_ISD_0_D, + FN_RIF0_D1_C, + + IFN_HCTS0x, + FN_RX2_B, + FN_MSIOF1_SYNC_D, + FN_SSI_SCK9_A, + FN_TS_SPSYNC0_D, + FN_STP_ISSYNC_0_D, + FN_RIF0_SYNC_C, + FN_AUDIO_CLKOUT1_A, + + IFN_HRTS0x, + FN_TX2_B, + FN_MSIOF1_SS1_D, + FN_SSI_WS9_A, + FN_STP_IVCXO27_0_D, + FN_BPFCLK_A, + FN_AUDIO_CLKOUT2_A, + + IFN_MSIOF0_SYNC, + FN_AUDIO_CLKOUT_A, + FN_TX5_B, + FN_BPFCLK_D, + + /* IPSR14 */ + IFN_MSIOF0_SS1, + FN_RX5_A, + FN_NFWPx_A, + FN_AUDIO_CLKA_C, + FN_SSI_SCK2_A, + FN_STP_IVCXO27_0_C, + FN_AUDIO_CLKOUT3_A, + FN_TCLK1_B, + + IFN_MSIOF0_SS2, + FN_TX5_A, + FN_MSIOF1_SS2_D, + FN_AUDIO_CLKC_A, + FN_SSI_WS2_A, + FN_STP_OPWM_0_D, + FN_AUDIO_CLKOUT_D, + FN_SPEEDIN_B, + + IFN_MLB_CLK, + FN_MSIOF1_SCK_F, + FN_SCL1_B, + + IFN_MLB_SIG, + FN_RX1_B, + FN_MSIOF1_SYNC_F, + FN_SDA1_B, + + IFN_MLB_DAT, + FN_TX1_B, + FN_MSIOF1_RXD_F, + + IFN_SSI_SCK0129, + FN_MSIOF1_TXD_F, + FN_MOUT0, + + IFN_SSI_WS0129, + FN_MSIOF1_SS1_F, + FN_MOUT1, + + IFN_SSI_SDATA0, + FN_MSIOF1_SS2_F, + FN_MOUT2, + + /* IPSR15 */ + IFN_SSI_SDATA1_A, + FN_MOUT5, + + IFN_SSI_SDATA2_A, + FN_SSI_SCK1_B, + FN_MOUT6, + + IFN_SSI_SCK34, + FN_MSIOF1_SS1_A, + FN_STP_OPWM_0_A, + + IFN_SSI_WS34, + FN_HCTS2x_A, + FN_MSIOF1_SS2_A, + FN_STP_IVCXO27_0_A, + + IFN_SSI_SDATA3, + FN_HRTS2x_A, + FN_MSIOF1_TXD_A, + FN_TS_SCK0_A, + FN_STP_ISCLK_0_A, + FN_RIF0_D1_A, + FN_RIF2_D0_A, + + IFN_SSI_SCK4, + FN_HRX2_A, + FN_MSIOF1_SCK_A, + FN_TS_SDAT0_A, + FN_STP_ISD_0_A, + FN_RIF0_CLK_A, + FN_RIF2_CLK_A, + + IFN_SSI_WS4, + FN_HTX2_A, + FN_MSIOF1_SYNC_A, + FN_TS_SDEN0_A, + FN_STP_ISEN_0_A, + FN_RIF0_SYNC_A, + FN_RIF2_SYNC_A, + + IFN_SSI_SDATA4, + FN_HSCK2_A, + FN_MSIOF1_RXD_A, + FN_TS_SPSYNC0_A, + FN_STP_ISSYNC_0_A, + FN_RIF0_D0_A, + FN_RIF2_D1_A, + + /* IPSR16 */ + IFN_SSI_SCK6, + FN_SIM0_RST_D, + FN_FSO_TOE_A, + + IFN_SSI_WS6, + FN_SIM0_D_D, + + IFN_SSI_SDATA6, + FN_SIM0_CLK_D, + + IFN_SSI_SCK78, + FN_HRX2_B, + FN_MSIOF1_SCK_C, + FN_TS_SCK1_A, + FN_STP_ISCLK_1_A, + FN_RIF1_CLK_A, + FN_RIF3_CLK_A, + + IFN_SSI_WS78, + FN_HTX2_B, + FN_MSIOF1_SYNC_C, + FN_TS_SDAT1_A, + FN_STP_ISD_1_A, + FN_RIF1_SYNC_A, + FN_RIF3_SYNC_A, + + IFN_SSI_SDATA7, + FN_HCTS2x_B, + FN_MSIOF1_RXD_C, + FN_TS_SDEN1_A, + FN_STP_IEN_1_A, + FN_RIF1_D0_A, + FN_RIF3_D0_A, + FN_TCLK2_A, + + IFN_SSI_SDATA8, + FN_HRTS2x_B, + FN_MSIOF1_TXD_C, + FN_TS_SPSYNC1_A, + FN_STP_ISSYNC_1_A, + FN_RIF1_D1_A, + FN_EIF3_D1_A, + + IFN_SSI_SDATA9_A, + FN_HSCK2_B, + FN_MSIOF1_SS1_C, + FN_HSCK1_A, + FN_SSI_WS1_B, + FN_SCK1, + FN_STP_IVCXO27_1_A, + FN_SCK5, + + /* IPSR17 */ + IFN_AUDIO_CLKA_A, + FN_CC5_OSCOUT, + + IFN_AUDIO_CLKB_B, + FN_SCIF_CLK_A, + FN_STP_IVCXO27_1_D, + FN_REMOCON_A, + FN_TCLK1_A, + + IFN_USB0_PWEN, + FN_SIM0_RST_C, + FN_TS_SCK1_D, + FN_STP_ISCLK_1_D, + FN_BPFCLK_B, + FN_RIF3_CLK_B, + FN_FSO_CFE_1_A, + FN_HSCK2_C, + + IFN_USB0_OVC, + FN_SIM0_D_C, + FN_TS_SDAT1_D, + FN_STP_ISD_1_D, + FN_RIF3_SYNC_B, + FN_HRX2_C, + + IFN_USB1_PWEN, + FN_SIM0_CLK_C, + FN_SSI_SCK1_A, + FN_TS_SCK0_E, + FN_STP_ISCLK_0_E, + FN_FMCLK_B, + FN_RIF2_CLK_B, + FN_SPEEDIN_A, + FN_HTX2_C, + + IFN_USB1_OVC, + FN_MSIOF1_SS2_C, + FN_SSI_WS1_A, + FN_TS_SDAT0_E, + FN_STP_ISD_0_E, + FN_FMIN_B, + FN_RIF2_SYNC_B, + FN_REMOCON_B, + FN_HCTS2x_C, + + IFN_USB30_PWEN, + FN_AUDIO_CLKOUT_B, + FN_SSI_SCK2_B, + FN_TS_SDEN1_D, + FN_STP_ISEN_1_D, + FN_STP_OPWM_0_E, + FN_RIF3_D0_B, + FN_TCLK2_B, + FN_TPU0TO0, + FN_BPFCLK_C, + FN_HRTS2x_C, + + IFN_USB30_OVC, + FN_AUDIO_CLKOUT1_B, + FN_SSI_WS2_B, + FN_TS_SPSYNC1_D, + FN_STP_ISSYNC_1_D, + FN_STP_IVCXO27_0_E, + FN_RIF3_D1_B, + FN_FSO_TOE_B, + FN_TPU0TO1, + + /* IPSR18 */ + IFN_GP6_30, + FN_AUDIO_CLKOUT2_B, + FN_SSI_SCK9_B, + FN_TS_SDEN0_E, + FN_STP_ISEN_0_E, + FN_RIF2_D0_B, + FN_FSO_CFE_0_A, + FN_TPU0TO2, + FN_FMCLK_C, + FN_FMCLK_D, + + IFN_GP6_31, + FN_AUDIO_CLKOUT3_B, + FN_SSI_WS9_B, + FN_TS_SPSYNC0_E, + FN_STP_ISSYNC_0_E, + FN_RIF2_D1_B, + FN_TPU0TO3, + FN_FMIN_C, + FN_FMIN_D, + + /* MOD_SEL0 */ + FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, + FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, + FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, + FN_SEL_MSIOF3_6, + FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, + FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, + FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, + FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, + FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, + FN_SEL_MSIOF1_6, + FN_SEL_LBSC_0, FN_SEL_LBSC_1, + FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, + FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, + FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, + FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, + FN_SEL_FSO_0, FN_SEL_FSO_1, + FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, + FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, + FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, + FN_SEL_DRIF1_2, + FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, + FN_SEL_DRIF0_2, + FN_SEL_CANFD_0, FN_SEL_CANFD_1, + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_ADG_2, FN_SEL_ADG_3, + + /* MOD_SEL1 */ + FN_SEL_TSIF1_0, + FN_SEL_TSIF1_1, + FN_SEL_TSIF1_2, + FN_SEL_TSIF1_3, + FN_SEL_TSIF0_0, + FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, + FN_SEL_TSIF0_3, + FN_SEL_TSIF0_4, + FN_SEL_TIMER_TMU_0, + FN_SEL_TIMER_TMU_1, + FN_SEL_SSP1_1_0, + FN_SEL_SSP1_1_1, + FN_SEL_SSP1_1_2, + FN_SEL_SSP1_1_3, + FN_SEL_SSP1_0_0, + FN_SEL_SSP1_0_1, + FN_SEL_SSP1_0_2, + FN_SEL_SSP1_0_3, + FN_SEL_SSP1_0_4, + FN_SEL_SSI_0, + FN_SEL_SSI_1, + FN_SEL_SPEED_PULSE_IF_0, + FN_SEL_SPEED_PULSE_IF_1, + FN_SEL_SIMCARD_0, + FN_SEL_SIMCARD_1, + FN_SEL_SIMCARD_2, + FN_SEL_SIMCARD_3, + FN_SEL_SDHI2_0, + FN_SEL_SDHI2_1, + FN_SEL_SCIF4_0, + FN_SEL_SCIF4_1, + FN_SEL_SCIF4_2, + FN_SEL_SCIF3_0, + FN_SEL_SCIF3_1, + FN_SEL_SCIF2_0, + FN_SEL_SCIF2_1, + FN_SEL_SCIF1_0, + FN_SEL_SCIF1_1, + FN_SEL_SCIF_0, + FN_SEL_SCIF_1, + FN_SEL_REMOCON_0, + FN_SEL_REMOCON_1, + FN_SEL_RCAN_0, + FN_SEL_RCAN_1, + FN_SEL_PWM6_0, + FN_SEL_PWM6_1, + FN_SEL_PWM5_0, + FN_SEL_PWM5_1, + FN_SEL_PWM4_0, + FN_SEL_PWM4_1, + FN_SEL_PWM3_0, + FN_SEL_PWM3_1, + FN_SEL_PWM2_0, + FN_SEL_PWM2_1, + FN_SEL_PWM1_0, + FN_SEL_PWM1_1, + + /* MOD_SEL2 */ + FN_I2C_SEL_5_0, + FN_I2C_SEL_5_1, + FN_I2C_SEL_3_0, + FN_I2C_SEL_3_1, + FN_I2C_SEL_0_0, + FN_I2C_SEL_0_1, + FN_SEL_FM_0, + FN_SEL_FM_1, + FN_SEL_FM_2, + FN_SEL_FM_3, + FN_SEL_SCIF5_0, + FN_SEL_SCIF5_1, + FN_SEL_I2C6_0, + FN_SEL_I2C6_1, + FN_SEL_I2C6_2, + FN_SEL_NDF_0, + FN_SEL_NDF_1, + FN_SEL_SSI2_0, + FN_SEL_SSI2_1, + FN_SEL_SSI9_0, + FN_SEL_SSI9_1, + FN_SEL_TIMER_TMU2_0, + FN_SEL_TIMER_TMU2_1, + FN_SEL_ADG_B_0, + FN_SEL_ADG_B_1, + FN_SEL_ADG_C_0, + FN_SEL_ADG_C_1, + FN_SEL_VIN4_0, + FN_SEL_VIN4_1, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* GPSR0 */ + D15_GMARK, + D14_GMARK, + D13_GMARK, + D12_GMARK, + D11_GMARK, + D10_GMARK, + D9_GMARK, + D8_GMARK, + D7_GMARK, + D6_GMARK, + D5_GMARK, + D4_GMARK, + D3_GMARK, + D2_GMARK, + D1_GMARK, + D0_GMARK, + + /* GPSR1 */ + CLKOUT_GMARK, + EX_WAIT0_A_GMARK, + WE1x_GMARK, + WE0x_GMARK, + RD_WRx_GMARK, + RDx_GMARK, + BSx_GMARK, + CS1x_A26_GMARK, + CS0x_GMARK, + A19_GMARK, + A18_GMARK, + A17_GMARK, + A16_GMARK, + A15_GMARK, + A14_GMARK, + A13_GMARK, + A12_GMARK, + A11_GMARK, + A10_GMARK, + A9_GMARK, + A8_GMARK, + A7_GMARK, + A6_GMARK, + A5_GMARK, + A4_GMARK, + A3_GMARK, + A2_GMARK, + A1_GMARK, + A0_GMARK, + + /* GPSR2 */ + AVB_AVTP_CAPTURE_A_GMARK, + AVB_AVTP_MATCH_A_GMARK, + AVB_LINK_GMARK, + AVB_PHY_INT_GMARK, + AVB_MAGIC_GMARK, + AVB_MDC_GMARK, + PWM2_A_GMARK, + PWM1_A_GMARK, + PWM0_GMARK, + IRQ5_GMARK, + IRQ4_GMARK, + IRQ3_GMARK, + IRQ2_GMARK, + IRQ1_GMARK, + IRQ0_GMARK, + + /* GPSR3 */ + SD1_WP_GMARK, + SD1_CD_GMARK, + SD0_WP_GMARK, + SD0_CD_GMARK, + SD1_DAT3_GMARK, + SD1_DAT2_GMARK, + SD1_DAT1_GMARK, + SD1_DAT0_GMARK, + SD1_CMD_GMARK, + SD1_CLK_GMARK, + SD0_DAT3_GMARK, + SD0_DAT2_GMARK, + SD0_DAT1_GMARK, + SD0_DAT0_GMARK, + SD0_CMD_GMARK, + SD0_CLK_GMARK, + + /* GPSR4 */ + SD3_DS_GMARK, + SD3_DAT7_GMARK, + SD3_DAT6_GMARK, + SD3_DAT5_GMARK, + SD3_DAT4_GMARK, + SD3_DAT3_MARK, + SD3_DAT2_MARK, + SD3_DAT1_MARK, + SD3_DAT0_MARK, + SD3_CMD_MARK, + SD3_CLK_MARK, + SD2_DS_GMARK, + SD2_DAT3_GMARK, + SD2_DAT2_GMARK, + SD2_DAT1_GMARK, + SD2_DAT0_GMARK, + SD2_CMD_MARK, + SD2_CLK_GMARK, + + /* GPSR5 */ + MLB_DAT_GMARK, + MLB_SIG_GMARK, + MLB_CLK_GMARK, + MSIOF0_RXD_MARK, + MSIOF0_SS2_GMARK, + MSIOF0_TXD_MARK, + MSIOF0_SS1_GMARK, + MSIOF0_SYNC_GMARK, + MSIOF0_SCK_MARK, + HRTS0x_GMARK, + HCTS0x_GMARK, + HTX0_GMARK, + HRX0_GMARK, + HSCK0_GMARK, + RX2_A_GMARK, + TX2_A_GMARK, + SCK2_GMARK, + RTS1x_TANS_GMARK, + CTS1x_GMARK, + TX1_A_GMARK, + RX1_A_GMARK, + RTS0x_TANS_GMARK, + CTS0x_GMARK, + TX0_GMARK, + RX0_GMARK, + SCK0_GMARK, + + /* GPSR6 */ + GP6_30_GMARK, + GP6_31_GMARK, + USB30_OVC_GMARK, + USB30_PWEN_GMARK, + USB1_OVC_GMARK, + USB1_PWEN_GMARK, + USB0_OVC_GMARK, + USB0_PWEN_GMARK, + AUDIO_CLKB_B_GMARK, + AUDIO_CLKA_A_GMARK, + SSI_SDATA9_A_GMARK, + SSI_SDATA8_GMARK, + SSI_SDATA7_GMARK, + SSI_WS78_GMARK, + SSI_SCK78_GMARK, + SSI_SDATA6_GMARK, + SSI_WS6_GMARK, + SSI_SCK6_GMARK, + SSI_SDATA5_MARK, + SSI_WS5_MARK, + SSI_SCK5_MARK, + SSI_SDATA4_GMARK, + SSI_WS4_GMARK, + SSI_SCK4_GMARK, + SSI_SDATA3_GMARK, + SSI_WS34_GMARK, + SSI_SCK34_GMARK, + SSI_SDATA2_A_GMARK, + SSI_SDATA1_A_GMARK, + SSI_SDATA0_GMARK, + SSI_WS01239_GMARK, + SSI_SCK01239_GMARK, + + /* GPSR7 */ + HDMI1_CEC_MARK, + HDMI0_CEC_MARK, + AVS2_MARK, + AVS1_MARK, + + /* IPSR0 */ + AVB_MDC_IMARK, + MSIOF2_SS2_C_MARK, + AVB_MAGIC_IMARK, + MSIOF2_SS1_C_MARK, + SCK4_A_MARK, + AVB_PHY_INT_IMARK, + MSIOF2_SYNC_C_MARK, + RX4_A_MARK, + AVB_LINK_IMARK, + MSIOF2_SCK_C_MARK, + TX4_A_MARK, + AVB_AVTP_MATCH_A_IMARK, + MSIOF2_RXD_C_MARK, + CTS4x_A_MARK, + AVB_AVTP_CAPTURE_A_IMARK, + MSIOF2_TXD_C_MARK, + RTS4x_TANS_A_MARK, + IRQ0_IMARK, + QPOLB_MARK, + DU_CDE_MARK, + VI4_DATA0_B_MARK, + CAN0_TX_B_MARK, + CANFD0_TX_B_MARK, + MSIOF3_SS2_E_MARK, + IRQ1_IMARK, + QPOLA_MARK, + DU_DISP_MARK, + VI4_DATA1_B_MARK, + CAN0_RX_B_MARK, + CANFD0_RX_B_MARK, + MSIOF3_SS1_E_MARK, + + /* IPSR1 */ + IRQ2_IMARK, + QCPV_QDE_MARK, + DU_EXODDF_DU_ODDF_DISP_CDE_MARK, + VI4_DATA2_B_MARK, + MSIOF3_SYNC_E_MARK, + PWM3_B_MARK, + IRQ3_IMARK, + QSTVB_QVE_MARK, + DU_DOTCLKOUT1_MARK, + VI4_DATA3_B_MARK, + MSIOF3_SCK_E_MARK, + PWM4_B_MARK, + IRQ4_IMARK, + QSTH_QHS_MARK, + DU_EXHSYNC_DU_HSYNC_MARK, + VI4_DATA4_B_MARK, + MSIOF3_RXD_E_MARK, + PWM5_B_MARK, + IRQ5_IMARK, + QSTB_QHE_MARK, + DU_EXVSYNC_DU_VSYNC_MARK, + VI4_DATA5_B_MARK, + MSIOF3_TXD_E_MARK, + PWM6_B_MARK, + PWM0_IMARK, + AVB_AVTP_PPS_MARK, + VI4_DATA6_B_MARK, + IECLK_B_MARK, + PWM1_A_IMARK, + HRX3_D_MARK, + VI4_DATA7_B_MARK, + IERX_B_MARK, + PWM2_A_IMARK, + PWMFSW0_MARK, + HTX3_D_MARK, + IETX_B_MARK, + A0_IMARK, + LCDOUT16_MARK, + MSIOF3_SYNC_B_MARK, + VI4_DATA8_MARK, + DU_DB0_MARK, + PWM3_A_MARK, + + /* IPSR2 */ + A1_IMARK, + LCDOUT17_MARK, + MSIOF3_TXD_B_MARK, + VI4_DATA9_MARK, + DU_DB1_MARK, + PWM4_A_MARK, + A2_IMARK, + LCDOUT18_MARK, + MSIOF3_SCK_B_MARK, + VI4_DATA10_MARK, + DU_DB2_MARK, + PWM5_A_MARK, + A3_IMARK, + LCDOUT19_MARK, + MSIOF3_RXD_B_MARK, + VI4_DATA11_MARK, + DU_DB3_MARK, + PWM6_A_MARK, + A4_IMARK, + LCDOUT20_MARK, + MSIOF3_SS1_B_MARK, + VI4_DATA12_MARK, + VI5_DATA12_MARK, + DU_DB4_MARK, + A5_IMARK, + LCDOUT21_MARK, + MSIOF3_SS2_B_MARK, + SCK4_B_MARK, + VI4_DATA13_MARK, + VI5_DATA13_MARK, + DU_DB5_MARK, + A6_IMARK, + LCDOUT22_MARK, + MSIOF2_SS1_A_MARK, + RX4_B_MARK, + VI4_DATA14_MARK, + VI5_DATA14_MARK, + DU_DB6_MARK, + A7_IMARK, + LCDOUT23_MARK, + MSIOF2_SS2_A_MARK, + TX4_B_MARK, + VI4_DATA15_MARK, + V15_DATA15_MARK, + DU_DB7_MARK, + A8_IMARK, + RX3_B_MARK, + MSIOF2_SYNC_A_MARK, + HRX4_B_MARK, + SDA6_A_MARK, + AVB_AVTP_MATCH_B_MARK, + PWM1_B_MARK, + + /* IPSR3 */ + A9_IMARK, + MSIOF2_SCK_A_MARK, + CTS4x_B_MARK, + VI5_VSYNCx_MARK, + A10_IMARK, + MSIOF2_RXD_A_MARK, + RTS4n_TANS_B_MARK, + VI5_HSYNCx_MARK, + A11_IMARK, + TX3_B_MARK, + MSIOF2_TXD_A_MARK, + HTX4_B_MARK, + HSCK4_MARK, + VI5_FIELD_MARK, + SCL6_A_MARK, + AVB_AVTP_CAPTURE_B_MARK, + PWM2_B_MARK, + SPV_EVEN_MARK, + A12_IMARK, + LCDOUT12_MARK, + MSIOF3_SCK_C_MARK, + HRX4_A_MARK, + VI5_DATA8_MARK, + DU_DG4_MARK, + A13_IMARK, + LCDOUT13_MARK, + MSIOF3_SYNC_C_MARK, + HTX4_A_MARK, + VI5_DATA9_MARK, + DU_DG5_MARK, + A14_IMARK, + LCDOUT14_MARK, + MSIOF3_RXD_C_MARK, + HCTS4x_MARK, + VI5_DATA10_MARK, + DU_DG6_MARK, + A15_IMARK, + LCDOUT15_MARK, + MSIOF3_TXD_C_MARK, + HRTS4x_MARK, + VI5_DATA11_MARK, + DU_DG7_MARK, + A16_IMARK, + LCDOUT8_MARK, + VI4_FIELD_MARK, + DU_DG0_MARK, + + /* IPSR4 */ + A17_IMARK, + LCDOUT9_MARK, + VI4_VSYNCx_MARK, + DU_DG1_MARK, + A18_IMARK, + LCDOUT10_MARK, + VI4_HSYNCx_MARK, + DU_DG2_MARK, + A19_IMARK, + LCDOUT11_MARK, + VI4_CLKENB_MARK, + DU_DG3_MARK, + CS0x_IMARK, + VI5_CLKENB_MARK, + CS1x_A26_IMARK, + VI5_CLK_MARK, + EX_WAIT0_B_MARK, + BSx_IMARK, + QSTVA_QVS_MARK, + MSIOF3_SCK_D_MARK, + SCK3_MARK, + HSCK3_MARK, + CAN1_TX_MARK, + CANFD1_TX_MARK, + IETX_A_MARK, + RDx_IMARK, + MSIOF3_SYNC_D_MARK, + RX3_A_MARK, + HRX3_A_MARK, + CAN0_TX_A_MARK, + CANFD0_TX_A_MARK, + RD_WRx_IMARK, + MSIOF3_RXD_D_MARK, + TX3_A_MARK, + HTX3_A_MARK, + CAN0_RX_A_MARK, + CANFD0_RX_A_MARK, + + /* IPSR5 */ + WE0x_IMARK, + MSIIOF3_TXD_D_MARK, + CTS3x_MARK, + HCTS3x_MARK, + SCL6_B_MARK, + CAN_CLK_MARK, + IECLK_A_MARK, + WE1x_IMARK, + MSIOF3_SS1_D_MARK, + RTS3x_TANS_MARK, + HRTS3x_MARK, + SDA6_B_MARK, + CAN1_RX_MARK, + CANFD1_RX_MARK, + IERX_A_MARK, + EX_WAIT0_A_IMARK, + QCLK_MARK, + VI4_CLK_MARK, + DU_DOTCLKOUT0_MARK, + D0_IMARK, + MSIOF2_SS1_B_MARK, + MSIOF3_SCK_A_MARK, + VI4_DATA16_MARK, + VI5_DATA0_MARK, + D1_IMARK, + MSIOF2_SS2_B_MARK, + MSIOF3_SYNC_A_MARK, + VI4_DATA17_MARK, + VI5_DATA1_MARK, + D2_IMARK, + MSIOF3_RXD_A_MARK, + VI4_DATA18_MARK, + VI5_DATA2_MARK, + D3_IMARK, + MSIOF3_TXD_A_MARK, + VI4_DATA19_MARK, + VI5_DATA3_MARK, + D4_IMARK, + MSIOF2_SCK_B_MARK, + VI4_DATA20_MARK, + VI5_DATA4_MARK, + + /* IPSR6 */ + D5_IMARK, + MSIOF2_SYNC_B_MARK, + VI4_DATA21_MARK, + VI5_DATA5_MARK, + D6_IMARK, + MSIOF2_RXD_B_MARK, + VI4_DATA22_MARK, + VI5_DATA6_MARK, + D7_IMARK, + MSIOF2_TXD_B_MARK, + VI4_DATA23_MARK, + VI5_DATA7_MARK, + D8_IMARK, + LCDOUT0_MARK, + MSIOF2_SCK_D_MARK, + SCK4_C_MARK, + VI4_DATA0_A_MARK, + DU_DR0_MARK, + D9_IMARK, + LCDOUT1_MARK, + MSIOF2_SYNC_D_MARK, + VI4_DATA1_A_MARK, + DU_DR1_MARK, + D10_IMARK, + LCDOUT2_MARK, + MSIOF2_RXD_D_MARK, + HRX3_B_MARK, + VI4_DATA2_A_MARK, + CTS4x_C_MARK, + DU_DR2_MARK, + D11_IMARK, + LCDOUT3_MARK, + MSIOF2_TXD_D_MARK, + HTX3_B_MARK, + VI4_DATA3_A_MARK, + RTS4x_TANS_C_MARK, + DU_DR3_MARK, + D12_IMARK, + LCDOUT4_MARK, + MSIOF2_SS1_D_MARK, + RX4_C_MARK, + VI4_DATA4_A_MARK, + DU_DR4_MARK, + + /* IPSR7 */ + D13_IMARK, + LCDOUT5_MARK, + MSIOF2_SS2_D_MARK, + TX4_C_MARK, + VI4_DATA5_A_MARK, + DU_DR5_MARK, + D14_IMARK, + LCDOUT6_MARK, + MSIOF3_SS1_A_MARK, + HRX3_C_MARK, + VI4_DATA6_A_MARK, + DU_DR6_MARK, + SCL6_C_MARK, + D15_IMARK, + LCDOUT7_MARK, + MSIOF3_SS2_A_MARK, + HTX3_C_MARK, + VI4_DATA7_A_MARK, + DU_DR7_MARK, + SDA6_C_MARK, + FSCLKST_MARK, + SD0_CLK_IMARK, + MSIOF1_SCK_E_MARK, + STP_OPWM_0_B_MARK, + SD0_CMD_IMARK, + MSIOF1_SYNC_E_MARK, + STP_IVCXO27_0_B_MARK, + SD0_DAT0_IMARK, + MSIOF1_RXD_E_MARK, + TS_SCK0_B_MARK, + STP_ISCLK_0_B_MARK, + SD0_DAT1_IMARK, + MSIOF1_TXD_E_MARK, + TS_SPSYNC0_B_MARK, + STP_ISSYNC_0_B_MARK, + + /* IPSR8 */ + SD0_DAT2_IMARK, + MSIOF1_SS1_E_MARK, + TS_SDAT0_B_MARK, + STP_ISD_0_B_MARK, + + SD0_DAT3_IMARK, + MSIOF1_SS2_E_MARK, + TS_SDEN0_B_MARK, + STP_ISEN_0_B_MARK, + + SD1_CLK_IMARK, + MSIOF1_SCK_G_MARK, + SIM0_CLK_A_MARK, + + SD1_CMD_IMARK, + MSIOF1_SYNC_G_MARK, + NFCEx_B_MARK, + SIM0_D_A_MARK, + STP_IVCXO27_1_B_MARK, + + SD1_DAT0_IMARK, + SD2_DAT4_MARK, + MSIOF1_RXD_G_MARK, + NFWPx_B_MARK, + TS_SCK1_B_MARK, + STP_ISCLK_1_B_MARK, + + SD1_DAT1_IMARK, + SD2_DAT5_MARK, + MSIOF1_TXD_G_MARK, + NFDATA14_B_MARK, + TS_SPSYNC1_B_MARK, + STP_ISSYNC_1_B_MARK, + + SD1_DAT2_IMARK, + SD2_DAT6_MARK, + MSIOF1_SS1_G_MARK, + NFDATA15_B_MARK, + TS_SDAT1_B_MARK, + STP_IOD_1_B_MARK, + + SD1_DAT3_IMARK, + SD2_DAT7_MARK, + MSIOF1_SS2_G_MARK, + NFRBx_B_MARK, + TS_SDEN1_B_MARK, + STP_ISEN_1_B_MARK, + + /* IPSR9 */ + SD2_CLK_IMARK, + NFDATA8_MARK, + + SD2_CMD_IMARK, + NFDATA9_MARK, + + SD2_DAT0_IMARK, + NFDATA10_MARK, + + SD2_DAT1_IMARK, + NFDATA11_MARK, + + SD2_DAT2_IMARK, + NFDATA12_MARK, + + SD2_DAT3_IMARK, + NFDATA13_MARK, + + SD2_DS_IMARK, + NFALE_MARK, + + SD3_CLK_IMARK, + NFWEx_MARK, + + /* IPSR10 */ + SD3_CMD_IMARK, + NFREx_MARK, + + SD3_DAT0_IMARK, + NFDATA0_MARK, + + SD3_DAT1_IMARK, + NFDATA1_MARK, + + SD3_DAT2_IMARK, + NFDATA2_MARK, + + SD3_DAT3_IMARK, + NFDATA3_MARK, + + SD3_DAT4_IMARK, + SD2_CD_A_MARK, + NFDATA4_MARK, + + SD3_DAT5_IMARK, + SD2_WP_A_MARK, + NFDATA5_MARK, + + SD3_DAT6_IMARK, + SD3_CD_MARK, + NFDATA6_MARK, + + /* IPSR11 */ + SD3_DAT7_IMARK, + SD3_WP_MARK, + NFDATA7_MARK, + + SD3_DS_IMARK, + NFCLE_MARK, + + SD0_CD_IMARK, + NFDATA14_A_MARK, + SCL2_B_MARK, + SIM0_RST_A_MARK, + + SD0_WP_IMARK, + NFDATA15_A_MARK, + SDA2_B_MARK, + + SD1_CD_IMARK, + NFRBx_A_MARK, + SIM0_CLK_B_MARK, + + SD1_WP_IMARK, + NFCEx_A_MARK, + SIM0_D_B_MARK, + + SCK0_IMARK, + HSCK1_B_MARK, + MSIOF1_SS2_B_MARK, + AUDIO_CLKC_B_MARK, + SDA2_A_MARK, + SIM0_RST_B_MARK, + STP_OPWM_0_C_MARK, + RIF0_CLK_B_MARK, + ADICHS2_MARK, + SCK5_B_MARK, + + RX0_IMARK, + HRX1_B_MARK, + TS_SCK0_C_MARK, + STP_ISCLK_0_C_MARK, + RIF0_D0_B_MARK, + + /* IPSR12 */ + TX0_IMARK, + HTX1_B_MARK, + TS_SPSYNC0_C_MARK, + STP_ISSYNC_0_C_MARK, + RIF0_D1_B_MARK, + + CTS0x_IMARK, + HCTS1x_B_MARK, + MSIOF1_SYNC_B_MARK, + TS_SPSYNC1_C_MARK, + STP_ISSYNC_1_C_MARK, + RIF1_SYNC_B_MARK, + AUDIO_CLKOUT_C_MARK, + ADICS_SAMP_MARK, + + RTS0x_TANS_IMARK, + HRTS1x_B_MARK, + MSIOF1_SS1_B_MARK, + AUDIO_CLKA_B_MARK, + SCL2_A_MARK, + STP_IVCXO27_1_C_MARK, + RIF0_SYNC_B_MARK, + ADICHS1_MARK, + + RX1_A_IMARK, + HRX1_A_MARK, + TS_SDAT0_C_MARK, + STP_ISD_0_C_MARK, + RIF1_CLK_C_MARK, + + TX1_A_IMARK, + HTX1_A_MARK, + TS_SDEN0_C_MARK, + STP_ISEN_0_C_MARK, + RIF1_D0_C_MARK, + + CTS1x_IMARK, + HCTS1x_A_MARK, + MSIOF1_RXD_B_MARK, + TS_SDEN1_C_MARK, + STP_ISEN_1_C_MARK, + RIF1_D0_B_MARK, + ADIDATA_MARK, + + RTS1x_TANS_IMARK, + HRTS1x_A_MARK, + MSIOF1_TXD_B_MARK, + TS_SDAT1_C_MARK, + STP_ISD_1_C_MARK, + RIF1_D1_B_MARK, + ADICHS0_MARK, + + SCK2_IMARK, + SCIF_CLK_B_MARK, + MSIOF1_SCK_B_MARK, + TS_SCK1_C_MARK, + STP_ISCLK_1_C_MARK, + RIF1_CLK_B_MARK, + ADICLK_MARK, + + /* IPSR13 */ + TX2_A_IMARK, + SD2_CD_B_MARK, + SCL1_A_MARK, + FMCLK_A_MARK, + RIF1_D1_C_MARK, + FSO_CFE_0_B_MARK, + + RX2_A_IMARK, + SD2_WP_B_MARK, + SDA1_A_MARK, + FMIN_A_MARK, + RIF1_SYNC_C_MARK, + FSO_CEF_1_B_MARK, + + HSCK0_IMARK, + MSIOF1_SCK_D_MARK, + AUDIO_CLKB_A_MARK, + SSI_SDATA1_B_MARK, + TS_SCK0_D_MARK, + STP_ISCLK_0_D_MARK, + RIF0_CLK_C_MARK, + RX5_B_MARK, + + HRX0_IMARK, + MSIOF1_RXD_D_MARK, + SS1_SDATA2_B_MARK, + TS_SDEN0_D_MARK, + STP_ISEN_0_D_MARK, + RIF0_D0_C_MARK, + + HTX0_IMARK, + MSIOF1_TXD_D_MARK, + SSI_SDATA9_B_MARK, + TS_SDAT0_D_MARK, + STP_ISD_0_D_MARK, + RIF0_D1_C_MARK, + + HCTS0x_IMARK, + RX2_B_MARK, + MSIOF1_SYNC_D_MARK, + SSI_SCK9_A_MARK, + TS_SPSYNC0_D_MARK, + STP_ISSYNC_0_D_MARK, + RIF0_SYNC_C_MARK, + AUDIO_CLKOUT1_A_MARK, + + HRTS0x_IMARK, + TX2_B_MARK, + MSIOF1_SS1_D_MARK, + SSI_WS9_A_MARK, + STP_IVCXO27_0_D_MARK, + BPFCLK_A_MARK, + AUDIO_CLKOUT2_A_MARK, + + MSIOF0_SYNC_IMARK, + AUDIO_CLKOUT_A_MARK, + TX5_B_MARK, + BPFCLK_D_MARK, + + /* IPSR14 */ + MSIOF0_SS1_IMARK, + RX5_A_MARK, + NFWPx_A_MARK, + AUDIO_CLKA_C_MARK, + SSI_SCK2_A_MARK, + STP_IVCXO27_0_C_MARK, + AUDIO_CLKOUT3_A_MARK, + TCLK1_B_MARK, + + MSIOF0_SS2_IMARK, + TX5_A_MARK, + MSIOF1_SS2_D_MARK, + AUDIO_CLKC_A_MARK, + SSI_WS2_A_MARK, + STP_OPWM_0_D_MARK, + AUDIO_CLKOUT_D_MARK, + SPEEDIN_B_MARK, + + MLB_CLK_IMARK, + MSIOF1_SCK_F_MARK, + SCL1_B_MARK, + + MLB_SIG_IMARK, + RX1_B_MARK, + MSIOF1_SYNC_F_MARK, + SDA1_B_MARK, + + MLB_DAT_IMARK, + TX1_B_MARK, + MSIOF1_RXD_F_MARK, + + SSI_SCK0129_IMARK, + MSIOF1_TXD_F_MARK, + MOUT0_MARK, + + SSI_WS0129_IMARK, + MSIOF1_SS1_F_MARK, + MOUT1_MARK, + + SSI_SDATA0_IMARK, + MSIOF1_SS2_F_MARK, + MOUT2_MARK, + + /* IPSR15 */ + SSI_SDATA1_A_IMARK, + MOUT5_MARK, + + SSI_SDATA2_A_IMARK, + SSI_SCK1_B_MARK, + MOUT6_MARK, + + SSI_SCK34_IMARK, + MSIOF1_SS1_A_MARK, + STP_OPWM_0_A_MARK, + + SSI_WS34_IMARK, + HCTS2x_A_MARK, + MSIOF1_SS2_A_MARK, + STP_IVCXO27_0_A_MARK, + + SSI_SDATA3_IMARK, + HRTS2x_A_MARK, + MSIOF1_TXD_A_MARK, + TS_SCK0_A_MARK, + STP_ISCLK_0_A_MARK, + RIF0_D1_A_MARK, + RIF2_D0_A_MARK, + + SSI_SCK4_IMARK, + HRX2_A_MARK, + MSIOF1_SCK_A_MARK, + TS_SDAT0_A_MARK, + STP_ISD_0_A_MARK, + RIF0_CLK_A_MARK, + RIF2_CLK_A_MARK, + + SSI_WS4_IMARK, + HTX2_A_MARK, + MSIOF1_SYNC_A_MARK, + TS_SDEN0_A_MARK, + STP_ISEN_0_A_MARK, + RIF0_SYNC_A_MARK, + RIF2_SYNC_A_MARK, + + SSI_SDATA4_IMARK, + HSCK2_A_MARK, + MSIOF1_RXD_A_MARK, + TS_SPSYNC0_A_MARK, + STP_ISSYNC_0_A_MARK, + RIF0_D0_A_MARK, + RIF2_D1_A_MARK, + + /* IPSR16 */ + SSI_SCK6_IMARK, + SIM0_RST_D_MARK, + FSO_TOE_A_MARK, + + SSI_WS6_IMARK, + SIM0_D_D_MARK, + + SSI_SDATA6_IMARK, + SIM0_CLK_D_MARK, + + SSI_SCK78_IMARK, + HRX2_B_MARK, + MSIOF1_SCK_C_MARK, + TS_SCK1_A_MARK, + STP_ISCLK_1_A_MARK, + RIF1_CLK_A_MARK, + RIF3_CLK_A_MARK, + + SSI_WS78_IMARK, + HTX2_B_MARK, + MSIOF1_SYNC_C_MARK, + TS_SDAT1_A_MARK, + STP_ISD_1_A_MARK, + RIF1_SYNC_A_MARK, + RIF3_SYNC_A_MARK, + + SSI_SDATA7_IMARK, + HCTS2x_B_MARK, + MSIOF1_RXD_C_MARK, + TS_SDEN1_A_MARK, + STP_IEN_1_A_MARK, + RIF1_D0_A_MARK, + RIF3_D0_A_MARK, + TCLK2_A_MARK, + + SSI_SDATA8_IMARK, + HRTS2x_B_MARK, + MSIOF1_TXD_C_MARK, + TS_SPSYNC1_A_MARK, + STP_ISSYNC_1_A_MARK, + RIF1_D1_A_MARK, + EIF3_D1_A_MARK, + + SSI_SDATA9_A_IMARK, + HSCK2_B_MARK, + MSIOF1_SS1_C_MARK, + HSCK1_A_MARK, + SSI_WS1_B_MARK, + SCK1_MARK, + STP_IVCXO27_1_A_MARK, + SCK5_MARK, + + /* IPSR17 */ + AUDIO_CLKA_A_IMARK, + CC5_OSCOUT_MARK, + + AUDIO_CLKB_B_IMARK, + SCIF_CLK_A_MARK, + STP_IVCXO27_1_D_MARK, + REMOCON_A_MARK, + TCLK1_A_MARK, + + USB0_PWEN_IMARK, + SIM0_RST_C_MARK, + TS_SCK1_D_MARK, + STP_ISCLK_1_D_MARK, + BPFCLK_B_MARK, + RIF3_CLK_B_MARK, + FSO_CFE_1_A_MARK, + HSCK2_C_MARK, + + USB0_OVC_IMARK, + SIM0_D_C_MARK, + TS_SDAT1_D_MARK, + STP_ISD_1_D_MARK, + RIF3_SYNC_B_MARK, + HRX2_C_MARK, + + USB1_PWEN_IMARK, + SIM0_CLK_C_MARK, + SSI_SCK1_A_MARK, + TS_SCK0_E_MARK, + STP_ISCLK_0_E_MARK, + FMCLK_B_MARK, + RIF2_CLK_B_MARK, + SPEEDIN_A_MARK, + HTX2_C_MARK, + + USB1_OVC_IMARK, + MSIOF1_SS2_C_MARK, + SSI_WS1_A_MARK, + TS_SDAT0_E_MARK, + STP_ISD_0_E_MARK, + FMIN_B_MARK, + RIF2_SYNC_B_MARK, + REMOCON_B_MARK, + HCTS2x_C_MARK, + + USB30_PWEN_IMARK, + AUDIO_CLKOUT_B_MARK, + SSI_SCK2_B_MARK, + TS_SDEN1_D_MARK, + STP_ISEN_1_D_MARK, + STP_OPWM_0_E_MARK, + RIF3_D0_B_MARK, + TCLK2_B_MARK, + TPU0TO0_MARK, + BPFCLK_C_MARK, + HRTS2x_C_MARK, + + USB30_OVC_IMARK, + AUDIO_CLKOUT1_B_MARK, + SSI_WS2_B_MARK, + TS_SPSYNC1_D_MARK, + STP_ISSYNC_1_D_MARK, + STP_IVCXO27_0_E_MARK, + RIF3_D1_B_MARK, + FSO_TOE_B_MARK, + TPU0TO1_MARK, + + /* IPSR18 */ + GP6_30_IMARK, + AUDIO_CLKOUT2_B_MARK, + SSI_SCK9_B_MARK, + TS_SDEN0_E_MARK, + STP_ISEN_0_E_MARK, + RIF2_D0_B_MARK, + FSO_CFE_0_A_MARK, + TPU0TO2_MARK, + FMCLK_C_MARK, + FMCLK_D_MARK, + + GP6_31_IMARK, + AUDIO_CLKOUT3_B_MARK, + SSI_WS9_B_MARK, + TS_SPSYNC0_E_MARK, + STP_ISSYNC_0_E_MARK, + RIF2_D1_B_MARK, + TPU0TO3_MARK, + FMIN_C_MARK, + FMIN_D_MARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + /* GPSR0 */ + PINMUX_DATA(D15_GMARK, GFN_D15), + PINMUX_DATA(D14_GMARK, GFN_D14), + PINMUX_DATA(D13_GMARK, GFN_D13), + PINMUX_DATA(D12_GMARK, GFN_D12), + PINMUX_DATA(D11_GMARK, GFN_D11), + PINMUX_DATA(D10_GMARK, GFN_D10), + PINMUX_DATA(D9_GMARK, GFN_D9), + PINMUX_DATA(D8_GMARK, GFN_D8), + PINMUX_DATA(D7_GMARK, GFN_D7), + PINMUX_DATA(D6_GMARK, GFN_D6), + PINMUX_DATA(D5_GMARK, GFN_D5), + PINMUX_DATA(D4_GMARK, GFN_D4), + PINMUX_DATA(D3_GMARK, GFN_D3), + PINMUX_DATA(D2_GMARK, GFN_D2), + PINMUX_DATA(D1_GMARK, GFN_D1), + PINMUX_DATA(D0_GMARK, GFN_D0), + + /* GPSR1 */ + PINMUX_DATA(CLKOUT_GMARK, GFN_CLKOUT), + PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A), + PINMUX_DATA(WE1x_GMARK, GFN_WE1x), + PINMUX_DATA(WE0x_GMARK, GFN_WE0x), + PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx), + PINMUX_DATA(RDx_GMARK, GFN_RDx), + PINMUX_DATA(BSx_GMARK, GFN_BSx), + PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26), + PINMUX_DATA(CS0x_GMARK, GFN_CS0x), + PINMUX_DATA(A19_GMARK, GFN_A19), + PINMUX_DATA(A18_GMARK, GFN_A18), + PINMUX_DATA(A17_GMARK, GFN_A17), + PINMUX_DATA(A16_GMARK, GFN_A16), + PINMUX_DATA(A15_GMARK, GFN_A15), + PINMUX_DATA(A14_GMARK, GFN_A14), + PINMUX_DATA(A13_GMARK, GFN_A13), + PINMUX_DATA(A12_GMARK, GFN_A12), + PINMUX_DATA(A11_GMARK, GFN_A11), + PINMUX_DATA(A10_GMARK, GFN_A10), + PINMUX_DATA(A9_GMARK, GFN_A9), + PINMUX_DATA(A8_GMARK, GFN_A8), + PINMUX_DATA(A7_GMARK, GFN_A7), + PINMUX_DATA(A6_GMARK, GFN_A6), + PINMUX_DATA(A5_GMARK, GFN_A5), + PINMUX_DATA(A4_GMARK, GFN_A4), + PINMUX_DATA(A3_GMARK, GFN_A3), + PINMUX_DATA(A2_GMARK, GFN_A2), + PINMUX_DATA(A1_GMARK, GFN_A1), + PINMUX_DATA(A0_GMARK, GFN_A0), + + /* GPSR2 */ + PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A), + PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A), + PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK), + PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT), + PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC), + PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC), + PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A), + PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A), + PINMUX_DATA(PWM0_GMARK, GFN_PWM0), + PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), + PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), + PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3), + PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2), + PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1), + PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), + + /* GPSR3 */ + PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP), + PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD), + PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP), + PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD), + PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3), + PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2), + PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1), + PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0), + PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD), + PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK), + PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3), + PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2), + PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1), + PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0), + PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD), + PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK), + + /* GPSR4 */ + PINMUX_DATA(SD3_DS_GMARK, GFN_SD3_DS), + PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7), + PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6), + PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5), + PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4), + PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3), + PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2), + PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1), + PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0), + PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD), + PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK), + PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS), + PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3), + PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2), + PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1), + PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0), + PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD), + PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK), + + /* GPSR5 */ + PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT), + PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG), + PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK), + PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD), + PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), + PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD), + PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), + PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), + PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK), + PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x), + PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x), + PINMUX_DATA(HTX0_GMARK, GFN_HTX0), + PINMUX_DATA(HRX0_GMARK, GFN_HRX0), + PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0), + PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A), + PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A), + PINMUX_DATA(SCK2_GMARK, GFN_SCK2), + PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS), + PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x), + PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A), + PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A), + PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS), + PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x), + PINMUX_DATA(TX0_GMARK, GFN_TX0), + PINMUX_DATA(RX0_GMARK, GFN_RX0), + PINMUX_DATA(SCK0_GMARK, GFN_SCK0), + + /* GPSR6 */ + PINMUX_DATA(GP6_30_GMARK, GFN_GP6_30), + PINMUX_DATA(GP6_31_GMARK, GFN_GP6_31), + PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC), + PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN), + PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC), + PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN), + PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC), + PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN), + PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B), + PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A), + PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A), + PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8), + PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7), + PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78), + PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78), + PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6), + PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6), + PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6), + PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5), + PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5), + PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5), + PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4), + PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4), + PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4), + PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3), + PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34), + PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34), + PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A), + PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A), + PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0), + PINMUX_DATA(SSI_WS01239_GMARK, GFN_SSI_WS01239), + PINMUX_DATA(SSI_SCK01239_GMARK, GFN_SSI_SCK01239), + + /* GPSR7 */ + PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC), + PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC), + PINMUX_DATA(AVS2_MARK, FN_AVS2), + PINMUX_DATA(AVS1_MARK, FN_AVS1), + + /* ipsr setting .. underconstruction */ +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + /* GPSR0 */ + GPIO_GFN(D15), + GPIO_GFN(D14), + GPIO_GFN(D13), + GPIO_GFN(D12), + GPIO_GFN(D11), + GPIO_GFN(D10), + GPIO_GFN(D9), + GPIO_GFN(D8), + GPIO_GFN(D7), + GPIO_GFN(D6), + GPIO_GFN(D5), + GPIO_GFN(D4), + GPIO_GFN(D3), + GPIO_GFN(D2), + GPIO_GFN(D1), + GPIO_GFN(D0), + /* GPSR1 */ + GPIO_GFN(CLKOUT), + GPIO_GFN(EX_WAIT0_A), + GPIO_GFN(WE1x), + GPIO_GFN(WE0x), + GPIO_GFN(RD_WRx), + GPIO_GFN(RDx), + GPIO_GFN(BSx), + GPIO_GFN(CS1x_A26), + GPIO_GFN(CS0x), + GPIO_GFN(A19), + GPIO_GFN(A18), + GPIO_GFN(A17), + GPIO_GFN(A16), + GPIO_GFN(A15), + GPIO_GFN(A14), + GPIO_GFN(A13), + GPIO_GFN(A12), + GPIO_GFN(A11), + GPIO_GFN(A10), + GPIO_GFN(A9), + GPIO_GFN(A8), + GPIO_GFN(A7), + GPIO_GFN(A6), + GPIO_GFN(A5), + GPIO_GFN(A4), + GPIO_GFN(A3), + GPIO_GFN(A2), + GPIO_GFN(A1), + GPIO_GFN(A0), + + /* GPSR2 */ + GPIO_GFN(AVB_AVTP_CAPTURE_A), + GPIO_GFN(AVB_AVTP_MATCH_A), + GPIO_GFN(AVB_LINK), + GPIO_GFN(AVB_PHY_INT), + GPIO_GFN(AVB_MAGIC), + GPIO_GFN(AVB_MDC), + GPIO_GFN(PWM2_A), + GPIO_GFN(PWM1_A), + GPIO_GFN(PWM0), + GPIO_GFN(IRQ5), + GPIO_GFN(IRQ4), + GPIO_GFN(IRQ3), + GPIO_GFN(IRQ2), + GPIO_GFN(IRQ1), + GPIO_GFN(IRQ0), + + /* GPSR3 */ + GPIO_GFN(SD1_WP), + GPIO_GFN(SD1_CD), + GPIO_GFN(SD0_WP), + GPIO_GFN(SD0_CD), + GPIO_GFN(SD1_DAT3), + GPIO_GFN(SD1_DAT2), + GPIO_GFN(SD1_DAT1), + GPIO_GFN(SD1_DAT0), + GPIO_GFN(SD1_CMD), + GPIO_GFN(SD1_CLK), + GPIO_GFN(SD0_DAT3), + GPIO_GFN(SD0_DAT2), + GPIO_GFN(SD0_DAT1), + GPIO_GFN(SD0_DAT0), + GPIO_GFN(SD0_CMD), + GPIO_GFN(SD0_CLK), + + /* GPSR4 */ + GPIO_GFN(SD3_DS), + GPIO_GFN(SD3_DAT7), + GPIO_GFN(SD3_DAT6), + GPIO_GFN(SD3_DAT5), + GPIO_GFN(SD3_DAT4), + GPIO_FN(SD3_DAT3), + GPIO_FN(SD3_DAT2), + GPIO_FN(SD3_DAT1), + GPIO_FN(SD3_DAT0), + GPIO_FN(SD3_CMD), + GPIO_FN(SD3_CLK), + GPIO_GFN(SD2_DS), + GPIO_GFN(SD2_DAT3), + GPIO_GFN(SD2_DAT2), + GPIO_GFN(SD2_DAT1), + GPIO_GFN(SD2_DAT0), + GPIO_FN(SD2_CMD), + GPIO_GFN(SD2_CLK), + + /* GPSR5 */ + GPIO_GFN(MLB_DAT), + GPIO_GFN(MLB_SIG), + GPIO_GFN(MLB_CLK), + GPIO_FN(MSIOF0_RXD), + GPIO_GFN(MSIOF0_SS2), + GPIO_FN(MSIOF0_TXD), + GPIO_GFN(MSIOF0_SS1), + GPIO_GFN(MSIOF0_SYNC), + GPIO_FN(MSIOF0_SCK), + GPIO_GFN(HRTS0x), + GPIO_GFN(HCTS0x), + GPIO_GFN(HTX0), + GPIO_GFN(HRX0), + GPIO_GFN(HSCK0), + GPIO_GFN(RX2_A), + GPIO_GFN(TX2_A), + GPIO_GFN(SCK2), + GPIO_GFN(RTS1x_TANS), + GPIO_GFN(CTS1x), + GPIO_GFN(TX1_A), + GPIO_GFN(RX1_A), + GPIO_GFN(RTS0x_TANS), + GPIO_GFN(CTS0x), + GPIO_GFN(TX0), + GPIO_GFN(RX0), + GPIO_GFN(SCK0), + + /* GPSR6 */ + GPIO_GFN(GP6_30), + GPIO_GFN(GP6_31), + GPIO_GFN(USB30_OVC), + GPIO_GFN(USB30_PWEN), + GPIO_GFN(USB1_OVC), + GPIO_GFN(USB1_PWEN), + GPIO_GFN(USB0_OVC), + GPIO_GFN(USB0_PWEN), + GPIO_GFN(AUDIO_CLKB_B), + GPIO_GFN(AUDIO_CLKA_A), + GPIO_GFN(SSI_SDATA9_A), + GPIO_GFN(SSI_SDATA8), + GPIO_GFN(SSI_SDATA7), + GPIO_GFN(SSI_WS78), + GPIO_GFN(SSI_SCK78), + GPIO_GFN(SSI_SDATA6), + GPIO_GFN(SSI_WS6), + GPIO_GFN(SSI_SCK6), + GPIO_FN(SSI_SDATA5), + GPIO_FN(SSI_WS5), + GPIO_FN(SSI_SCK5), + GPIO_GFN(SSI_SDATA4), + GPIO_GFN(SSI_WS4), + GPIO_GFN(SSI_SCK4), + GPIO_GFN(SSI_SDATA3), + GPIO_GFN(SSI_WS34), + GPIO_GFN(SSI_SCK34), + GPIO_GFN(SSI_SDATA2_A), + GPIO_GFN(SSI_SDATA1_A), + GPIO_GFN(SSI_SDATA0), + GPIO_GFN(SSI_WS01239), + GPIO_GFN(SSI_SCK01239), + + /* GPSR7 */ + GPIO_FN(HDMI1_CEC), + GPIO_FN(HDMI0_CEC), + GPIO_FN(AVS2), + GPIO_FN(AVS1), + + /* IPSR0 */ + GPIO_IFN(AVB_MDC), + GPIO_FN(MSIOF2_SS2_C), + GPIO_IFN(AVB_MAGIC), + GPIO_FN(MSIOF2_SS1_C), + GPIO_FN(SCK4_A), + GPIO_IFN(AVB_PHY_INT), + GPIO_FN(MSIOF2_SYNC_C), + GPIO_FN(RX4_A), + GPIO_IFN(AVB_LINK), + GPIO_FN(MSIOF2_SCK_C), + GPIO_FN(TX4_A), + GPIO_IFN(AVB_AVTP_MATCH_A), + GPIO_FN(MSIOF2_RXD_C), + GPIO_FN(CTS4x_A), + GPIO_IFN(AVB_AVTP_CAPTURE_A), + GPIO_FN(MSIOF2_TXD_C), + GPIO_FN(RTS4x_TANS_A), + GPIO_IFN(IRQ0), + GPIO_FN(QPOLB), + GPIO_FN(DU_CDE), + GPIO_FN(VI4_DATA0_B), + GPIO_FN(CAN0_TX_B), + GPIO_FN(CANFD0_TX_B), + GPIO_FN(MSIOF3_SS2_E), + GPIO_IFN(IRQ1), + GPIO_FN(QPOLA), + GPIO_FN(DU_DISP), + GPIO_FN(VI4_DATA1_B), + GPIO_FN(CAN0_RX_B), + GPIO_FN(CANFD0_RX_B), + GPIO_FN(MSIOF3_SS1_E), + + /* IPSR1 */ + GPIO_IFN(IRQ2), + GPIO_FN(QCPV_QDE), + GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE), + GPIO_FN(VI4_DATA2_B), + GPIO_FN(MSIOF3_SYNC_E), + GPIO_FN(PWM3_B), + GPIO_IFN(IRQ3), + GPIO_FN(QSTVB_QVE), + GPIO_FN(DU_DOTCLKOUT1), + GPIO_FN(VI4_DATA3_B), + GPIO_FN(MSIOF3_SCK_E), + GPIO_FN(PWM4_B), + GPIO_IFN(IRQ4), + GPIO_FN(QSTH_QHS), + GPIO_FN(DU_EXHSYNC_DU_HSYNC), + GPIO_FN(VI4_DATA4_B), + GPIO_FN(MSIOF3_RXD_E), + GPIO_FN(PWM5_B), + GPIO_IFN(IRQ5), + GPIO_FN(QSTB_QHE), + GPIO_FN(DU_EXVSYNC_DU_VSYNC), + GPIO_FN(VI4_DATA5_B), + GPIO_FN(MSIOF3_TXD_E), + GPIO_FN(PWM6_B), + GPIO_IFN(PWM0), + GPIO_FN(AVB_AVTP_PPS), + GPIO_FN(VI4_DATA6_B), + GPIO_FN(IECLK_B), + GPIO_IFN(PWM1_A), + GPIO_FN(HRX3_D), + GPIO_FN(VI4_DATA7_B), + GPIO_FN(IERX_B), + GPIO_IFN(PWM2_A), + GPIO_FN(PWMFSW0), + GPIO_FN(HTX3_D), + GPIO_FN(IETX_B), + GPIO_IFN(A0), + GPIO_FN(LCDOUT16), + GPIO_FN(MSIOF3_SYNC_B), + GPIO_FN(VI4_DATA8), + GPIO_FN(DU_DB0), + GPIO_FN(PWM3_A), + + /* IPSR2 */ + GPIO_IFN(A1), + GPIO_FN(LCDOUT17), + GPIO_FN(MSIOF3_TXD_B), + GPIO_FN(VI4_DATA9), + GPIO_FN(DU_DB1), + GPIO_FN(PWM4_A), + GPIO_IFN(A2), + GPIO_FN(LCDOUT18), + GPIO_FN(MSIOF3_SCK_B), + GPIO_FN(VI4_DATA10), + GPIO_FN(DU_DB2), + GPIO_FN(PWM5_A), + GPIO_IFN(A3), + GPIO_FN(LCDOUT19), + GPIO_FN(MSIOF3_RXD_B), + GPIO_FN(VI4_DATA11), + GPIO_FN(DU_DB3), + GPIO_FN(PWM6_A), + GPIO_IFN(A4), + GPIO_FN(LCDOUT20), + GPIO_FN(MSIOF3_SS1_B), + GPIO_FN(VI4_DATA12), + GPIO_FN(VI5_DATA12), + GPIO_FN(DU_DB4), + GPIO_IFN(A5), + GPIO_FN(LCDOUT21), + GPIO_FN(MSIOF3_SS2_B), + GPIO_FN(SCK4_B), + GPIO_FN(VI4_DATA13), + GPIO_FN(VI5_DATA13), + GPIO_FN(DU_DB5), + GPIO_IFN(A6), + GPIO_FN(LCDOUT22), + GPIO_FN(MSIOF2_SS1_A), + GPIO_FN(RX4_B), + GPIO_FN(VI4_DATA14), + GPIO_FN(VI5_DATA14), + GPIO_FN(DU_DB6), + GPIO_IFN(A7), + GPIO_FN(LCDOUT23), + GPIO_FN(MSIOF2_SS2_A), + GPIO_FN(TX4_B), + GPIO_FN(VI4_DATA15), + GPIO_FN(V15_DATA15), + GPIO_FN(DU_DB7), + GPIO_IFN(A8), + GPIO_FN(RX3_B), + GPIO_FN(MSIOF2_SYNC_A), + GPIO_FN(HRX4_B), + GPIO_FN(SDA6_A), + GPIO_FN(AVB_AVTP_MATCH_B), + GPIO_FN(PWM1_B), + + /* IPSR3 */ + GPIO_IFN(A9), + GPIO_FN(MSIOF2_SCK_A), + GPIO_FN(CTS4x_B), + GPIO_FN(VI5_VSYNCx), + GPIO_IFN(A10), + GPIO_FN(MSIOF2_RXD_A), + GPIO_FN(RTS4n_TANS_B), + GPIO_FN(VI5_HSYNCx), + GPIO_IFN(A11), + GPIO_FN(TX3_B), + GPIO_FN(MSIOF2_TXD_A), + GPIO_FN(HTX4_B), + GPIO_FN(HSCK4), + GPIO_FN(VI5_FIELD), + GPIO_FN(SCL6_A), + GPIO_FN(AVB_AVTP_CAPTURE_B), + GPIO_FN(PWM2_B), + GPIO_FN(SPV_EVEN), + GPIO_IFN(A12), + GPIO_FN(LCDOUT12), + GPIO_FN(MSIOF3_SCK_C), + GPIO_FN(HRX4_A), + GPIO_FN(VI5_DATA8), + GPIO_FN(DU_DG4), + GPIO_IFN(A13), + GPIO_FN(LCDOUT13), + GPIO_FN(MSIOF3_SYNC_C), + GPIO_FN(HTX4_A), + GPIO_FN(VI5_DATA9), + GPIO_FN(DU_DG5), + GPIO_IFN(A14), + GPIO_FN(LCDOUT14), + GPIO_FN(MSIOF3_RXD_C), + GPIO_FN(HCTS4x), + GPIO_FN(VI5_DATA10), + GPIO_FN(DU_DG6), + GPIO_IFN(A15), + GPIO_FN(LCDOUT15), + GPIO_FN(MSIOF3_TXD_C), + GPIO_FN(HRTS4x), + GPIO_FN(VI5_DATA11), + GPIO_FN(DU_DG7), + GPIO_IFN(A16), + GPIO_FN(LCDOUT8), + GPIO_FN(VI4_FIELD), + GPIO_FN(DU_DG0), + + /* IPSR4 */ + GPIO_IFN(A17), + GPIO_FN(LCDOUT9), + GPIO_FN(VI4_VSYNCx), + GPIO_FN(DU_DG1), + GPIO_IFN(A18), + GPIO_FN(LCDOUT10), + GPIO_FN(VI4_HSYNCx), + GPIO_FN(DU_DG2), + GPIO_IFN(A19), + GPIO_FN(LCDOUT11), + GPIO_FN(VI4_CLKENB), + GPIO_FN(DU_DG3), + GPIO_IFN(CS0x), + GPIO_FN(VI5_CLKENB), + GPIO_IFN(CS1x_A26), + GPIO_FN(VI5_CLK), + GPIO_FN(EX_WAIT0_B), + GPIO_IFN(BSx), + GPIO_FN(QSTVA_QVS), + GPIO_FN(MSIOF3_SCK_D), + GPIO_FN(SCK3), + GPIO_FN(HSCK3), + GPIO_FN(CAN1_TX), + GPIO_FN(CANFD1_TX), + GPIO_FN(IETX_A), + GPIO_IFN(RDx), + GPIO_FN(MSIOF3_SYNC_D), + GPIO_FN(RX3_A), + GPIO_FN(HRX3_A), + GPIO_FN(CAN0_TX_A), + GPIO_FN(CANFD0_TX_A), + GPIO_IFN(RD_WRx), + GPIO_FN(MSIOF3_RXD_D), + GPIO_FN(TX3_A), + GPIO_FN(HTX3_A), + GPIO_FN(CAN0_RX_A), + GPIO_FN(CANFD0_RX_A), + + /* IPSR5 */ + GPIO_IFN(WE0x), + GPIO_FN(MSIIOF3_TXD_D), + GPIO_FN(CTS3x), + GPIO_FN(HCTS3x), + GPIO_FN(SCL6_B), + GPIO_FN(CAN_CLK), + GPIO_FN(IECLK_A), + GPIO_IFN(WE1x), + GPIO_FN(MSIOF3_SS1_D), + GPIO_FN(RTS3x_TANS), + GPIO_FN(HRTS3x), + GPIO_FN(SDA6_B), + GPIO_FN(CAN1_RX), + GPIO_FN(CANFD1_RX), + GPIO_FN(IERX_A), + GPIO_IFN(EX_WAIT0_A), + GPIO_FN(QCLK), + GPIO_FN(VI4_CLK), + GPIO_FN(DU_DOTCLKOUT0), + GPIO_IFN(D0), + GPIO_FN(MSIOF2_SS1_B), + GPIO_FN(MSIOF3_SCK_A), + GPIO_FN(VI4_DATA16), + GPIO_FN(VI5_DATA0), + GPIO_IFN(D1), + GPIO_FN(MSIOF2_SS2_B), + GPIO_FN(MSIOF3_SYNC_A), + GPIO_FN(VI4_DATA17), + GPIO_FN(VI5_DATA1), + GPIO_IFN(D2), + GPIO_FN(MSIOF3_RXD_A), + GPIO_FN(VI4_DATA18), + GPIO_FN(VI5_DATA2), + GPIO_IFN(D3), + GPIO_FN(MSIOF3_TXD_A), + GPIO_FN(VI4_DATA19), + GPIO_FN(VI5_DATA3), + GPIO_IFN(D4), + GPIO_FN(MSIOF2_SCK_B), + GPIO_FN(VI4_DATA20), + GPIO_FN(VI5_DATA4), + + /* IPSR6 */ + GPIO_IFN(D5), + GPIO_FN(MSIOF2_SYNC_B), + GPIO_FN(VI4_DATA21), + GPIO_FN(VI5_DATA5), + GPIO_IFN(D6), + GPIO_FN(MSIOF2_RXD_B), + GPIO_FN(VI4_DATA22), + GPIO_FN(VI5_DATA6), + GPIO_IFN(D7), + GPIO_FN(MSIOF2_TXD_B), + GPIO_FN(VI4_DATA23), + GPIO_FN(VI5_DATA7), + GPIO_IFN(D8), + GPIO_FN(LCDOUT0), + GPIO_FN(MSIOF2_SCK_D), + GPIO_FN(SCK4_C), + GPIO_FN(VI4_DATA0_A), + GPIO_FN(DU_DR0), + GPIO_IFN(D9), + GPIO_FN(LCDOUT1), + GPIO_FN(MSIOF2_SYNC_D), + GPIO_FN(VI4_DATA1_A), + GPIO_FN(DU_DR1), + GPIO_IFN(D10), + GPIO_FN(LCDOUT2), + GPIO_FN(MSIOF2_RXD_D), + GPIO_FN(HRX3_B), + GPIO_FN(VI4_DATA2_A), + GPIO_FN(CTS4x_C), + GPIO_FN(DU_DR2), + GPIO_IFN(D11), + GPIO_FN(LCDOUT3), + GPIO_FN(MSIOF2_TXD_D), + GPIO_FN(HTX3_B), + GPIO_FN(VI4_DATA3_A), + GPIO_FN(RTS4x_TANS_C), + GPIO_FN(DU_DR3), + GPIO_IFN(D12), + GPIO_FN(LCDOUT4), + GPIO_FN(MSIOF2_SS1_D), + GPIO_FN(RX4_C), + GPIO_FN(VI4_DATA4_A), + GPIO_FN(DU_DR4), + + /* IPSR7 */ + GPIO_IFN(D13), + GPIO_FN(LCDOUT5), + GPIO_FN(MSIOF2_SS2_D), + GPIO_FN(TX4_C), + GPIO_FN(VI4_DATA5_A), + GPIO_FN(DU_DR5), + GPIO_IFN(D14), + GPIO_FN(LCDOUT6), + GPIO_FN(MSIOF3_SS1_A), + GPIO_FN(HRX3_C), + GPIO_FN(VI4_DATA6_A), + GPIO_FN(DU_DR6), + GPIO_FN(SCL6_C), + GPIO_IFN(D15), + GPIO_FN(LCDOUT7), + GPIO_FN(MSIOF3_SS2_A), + GPIO_FN(HTX3_C), + GPIO_FN(VI4_DATA7_A), + GPIO_FN(DU_DR7), + GPIO_FN(SDA6_C), + GPIO_FN(FSCLKST), + GPIO_IFN(SD0_CLK), + GPIO_FN(MSIOF1_SCK_E), + GPIO_FN(STP_OPWM_0_B), + GPIO_IFN(SD0_CMD), + GPIO_FN(MSIOF1_SYNC_E), + GPIO_FN(STP_IVCXO27_0_B), + GPIO_IFN(SD0_DAT0), + GPIO_FN(MSIOF1_RXD_E), + GPIO_FN(TS_SCK0_B), + GPIO_FN(STP_ISCLK_0_B), + GPIO_IFN(SD0_DAT1), + GPIO_FN(MSIOF1_TXD_E), + GPIO_FN(TS_SPSYNC0_B), + GPIO_FN(STP_ISSYNC_0_B), + + /* IPSR8 */ + GPIO_IFN(SD0_DAT2), + GPIO_FN(MSIOF1_SS1_E), + GPIO_FN(TS_SDAT0_B), + GPIO_FN(STP_ISD_0_B), + + GPIO_IFN(SD0_DAT3), + GPIO_FN(MSIOF1_SS2_E), + GPIO_FN(TS_SDEN0_B), + GPIO_FN(STP_ISEN_0_B), + + GPIO_IFN(SD1_CLK), + GPIO_FN(MSIOF1_SCK_G), + GPIO_FN(SIM0_CLK_A), + + GPIO_IFN(SD1_CMD), + GPIO_FN(MSIOF1_SYNC_G), + GPIO_FN(NFCEx_B), + GPIO_FN(SIM0_D_A), + GPIO_FN(STP_IVCXO27_1_B), + + GPIO_IFN(SD1_DAT0), + GPIO_FN(SD2_DAT4), + GPIO_FN(MSIOF1_RXD_G), + GPIO_FN(NFWPx_B), + GPIO_FN(TS_SCK1_B), + GPIO_FN(STP_ISCLK_1_B), + + GPIO_IFN(SD1_DAT1), + GPIO_FN(SD2_DAT5), + GPIO_FN(MSIOF1_TXD_G), + GPIO_FN(NFDATA14_B), + GPIO_FN(TS_SPSYNC1_B), + GPIO_FN(STP_ISSYNC_1_B), + + GPIO_IFN(SD1_DAT2), + GPIO_FN(SD2_DAT6), + GPIO_FN(MSIOF1_SS1_G), + GPIO_FN(NFDATA15_B), + GPIO_FN(TS_SDAT1_B), + GPIO_FN(STP_IOD_1_B), + + GPIO_IFN(SD1_DAT3), + GPIO_FN(SD2_DAT7), + GPIO_FN(MSIOF1_SS2_G), + GPIO_FN(NFRBx_B), + GPIO_FN(TS_SDEN1_B), + GPIO_FN(STP_ISEN_1_B), + + /* IPSR9 */ + GPIO_IFN(SD2_CLK), + GPIO_FN(NFDATA8), + + GPIO_IFN(SD2_CMD), + GPIO_FN(NFDATA9), + + GPIO_IFN(SD2_DAT0), + GPIO_FN(NFDATA10), + + GPIO_IFN(SD2_DAT1), + GPIO_FN(NFDATA11), + + GPIO_IFN(SD2_DAT2), + GPIO_FN(NFDATA12), + + GPIO_IFN(SD2_DAT3), + GPIO_FN(NFDATA13), + + GPIO_IFN(SD2_DS), + GPIO_FN(NFALE), + + GPIO_IFN(SD3_CLK), + GPIO_FN(NFWEx), + + /* IPSR10 */ + GPIO_IFN(SD3_CMD), + GPIO_FN(NFREx), + + GPIO_IFN(SD3_DAT0), + GPIO_FN(NFDATA0), + + GPIO_IFN(SD3_DAT1), + GPIO_FN(NFDATA1), + + GPIO_IFN(SD3_DAT2), + GPIO_FN(NFDATA2), + + GPIO_IFN(SD3_DAT3), + GPIO_FN(NFDATA3), + + GPIO_IFN(SD3_DAT4), + GPIO_FN(SD2_CD_A), + GPIO_FN(NFDATA4), + + GPIO_IFN(SD3_DAT5), + GPIO_FN(SD2_WP_A), + GPIO_FN(NFDATA5), + + GPIO_IFN(SD3_DAT6), + GPIO_FN(SD3_CD), + GPIO_FN(NFDATA6), + + /* IPSR11 */ + GPIO_IFN(SD3_DAT7), + GPIO_FN(SD3_WP), + GPIO_FN(NFDATA7), + + GPIO_IFN(SD3_DS), + GPIO_FN(NFCLE), + + GPIO_IFN(SD0_CD), + GPIO_FN(NFDATA14_A), + GPIO_FN(SCL2_B), + GPIO_FN(SIM0_RST_A), + + GPIO_IFN(SD0_WP), + GPIO_FN(NFDATA15_A), + GPIO_FN(SDA2_B), + + GPIO_IFN(SD1_CD), + GPIO_FN(NFRBx_A), + GPIO_FN(SIM0_CLK_B), + + GPIO_IFN(SD1_WP), + GPIO_FN(NFCEx_A), + GPIO_FN(SIM0_D_B), + + GPIO_IFN(SCK0), + GPIO_FN(HSCK1_B), + GPIO_FN(MSIOF1_SS2_B), + GPIO_FN(AUDIO_CLKC_B), + GPIO_FN(SDA2_A), + GPIO_FN(SIM0_RST_B), + GPIO_FN(STP_OPWM_0_C), + GPIO_FN(RIF0_CLK_B), + GPIO_FN(ADICHS2), + GPIO_FN(SCK5_B), + + GPIO_IFN(RX0), + GPIO_FN(HRX1_B), + GPIO_FN(TS_SCK0_C), + GPIO_FN(STP_ISCLK_0_C), + GPIO_FN(RIF0_D0_B), + + /* IPSR12 */ + GPIO_IFN(TX0), + GPIO_FN(HTX1_B), + GPIO_FN(TS_SPSYNC0_C), + GPIO_FN(STP_ISSYNC_0_C), + GPIO_FN(RIF0_D1_B), + + GPIO_IFN(CTS0x), + GPIO_FN(HCTS1x_B), + GPIO_FN(MSIOF1_SYNC_B), + GPIO_FN(TS_SPSYNC1_C), + GPIO_FN(STP_ISSYNC_1_C), + GPIO_FN(RIF1_SYNC_B), + GPIO_FN(AUDIO_CLKOUT_C), + GPIO_FN(ADICS_SAMP), + + GPIO_IFN(RTS0x_TANS), + GPIO_FN(HRTS1x_B), + GPIO_FN(MSIOF1_SS1_B), + GPIO_FN(AUDIO_CLKA_B), + GPIO_FN(SCL2_A), + GPIO_FN(STP_IVCXO27_1_C), + GPIO_FN(RIF0_SYNC_B), + GPIO_FN(ADICHS1), + + GPIO_IFN(RX1_A), + GPIO_FN(HRX1_A), + GPIO_FN(TS_SDAT0_C), + GPIO_FN(STP_ISD_0_C), + GPIO_FN(RIF1_CLK_C), + + GPIO_IFN(TX1_A), + GPIO_FN(HTX1_A), + GPIO_FN(TS_SDEN0_C), + GPIO_FN(STP_ISEN_0_C), + GPIO_FN(RIF1_D0_C), + + GPIO_IFN(CTS1x), + GPIO_FN(HCTS1x_A), + GPIO_FN(MSIOF1_RXD_B), + GPIO_FN(TS_SDEN1_C), + GPIO_FN(STP_ISEN_1_C), + GPIO_FN(RIF1_D0_B), + GPIO_FN(ADIDATA), + + GPIO_IFN(RTS1x_TANS), + GPIO_FN(HRTS1x_A), + GPIO_FN(MSIOF1_TXD_B), + GPIO_FN(TS_SDAT1_C), + GPIO_FN(STP_ISD_1_C), + GPIO_FN(RIF1_D1_B), + GPIO_FN(ADICHS0), + + GPIO_IFN(SCK2), + GPIO_FN(SCIF_CLK_B), + GPIO_FN(MSIOF1_SCK_B), + GPIO_FN(TS_SCK1_C), + GPIO_FN(STP_ISCLK_1_C), + GPIO_FN(RIF1_CLK_B), + GPIO_FN(ADICLK), + + /* IPSR13 */ + GPIO_IFN(TX2_A), + GPIO_FN(SD2_CD_B), + GPIO_FN(SCL1_A), + GPIO_FN(FMCLK_A), + GPIO_FN(RIF1_D1_C), + GPIO_FN(FSO_CFE_0_B), + + GPIO_IFN(RX2_A), + GPIO_FN(SD2_WP_B), + GPIO_FN(SDA1_A), + GPIO_FN(FMIN_A), + GPIO_FN(RIF1_SYNC_C), + GPIO_FN(FSO_CEF_1_B), + + GPIO_IFN(HSCK0), + GPIO_FN(MSIOF1_SCK_D), + GPIO_FN(AUDIO_CLKB_A), + GPIO_FN(SSI_SDATA1_B), + GPIO_FN(TS_SCK0_D), + GPIO_FN(STP_ISCLK_0_D), + GPIO_FN(RIF0_CLK_C), + GPIO_FN(RX5_B), + + GPIO_IFN(HRX0), + GPIO_FN(MSIOF1_RXD_D), + GPIO_FN(SS1_SDATA2_B), + GPIO_FN(TS_SDEN0_D), + GPIO_FN(STP_ISEN_0_D), + GPIO_FN(RIF0_D0_C), + + GPIO_IFN(HTX0), + GPIO_FN(MSIOF1_TXD_D), + GPIO_FN(SSI_SDATA9_B), + GPIO_FN(TS_SDAT0_D), + GPIO_FN(STP_ISD_0_D), + GPIO_FN(RIF0_D1_C), + + GPIO_IFN(HCTS0x), + GPIO_FN(RX2_B), + GPIO_FN(MSIOF1_SYNC_D), + GPIO_FN(SSI_SCK9_A), + GPIO_FN(TS_SPSYNC0_D), + GPIO_FN(STP_ISSYNC_0_D), + GPIO_FN(RIF0_SYNC_C), + GPIO_FN(AUDIO_CLKOUT1_A), + + GPIO_IFN(HRTS0x), + GPIO_FN(TX2_B), + GPIO_FN(MSIOF1_SS1_D), + GPIO_FN(SSI_WS9_A), + GPIO_FN(STP_IVCXO27_0_D), + GPIO_FN(BPFCLK_A), + GPIO_FN(AUDIO_CLKOUT2_A), + + GPIO_IFN(MSIOF0_SYNC), + GPIO_FN(AUDIO_CLKOUT_A), + GPIO_FN(TX5_B), + GPIO_FN(BPFCLK_D), + + /* IPSR14 */ + GPIO_IFN(MSIOF0_SS1), + GPIO_FN(RX5_A), + GPIO_FN(NFWPx_A), + GPIO_FN(AUDIO_CLKA_C), + GPIO_FN(SSI_SCK2_A), + GPIO_FN(STP_IVCXO27_0_C), + GPIO_FN(AUDIO_CLKOUT3_A), + GPIO_FN(TCLK1_B), + + GPIO_IFN(MSIOF0_SS2), + GPIO_FN(TX5_A), + GPIO_FN(MSIOF1_SS2_D), + GPIO_FN(AUDIO_CLKC_A), + GPIO_FN(SSI_WS2_A), + GPIO_FN(STP_OPWM_0_D), + GPIO_FN(AUDIO_CLKOUT_D), + GPIO_FN(SPEEDIN_B), + + GPIO_IFN(MLB_CLK), + GPIO_FN(MSIOF1_SCK_F), + GPIO_FN(SCL1_B), + + GPIO_IFN(MLB_SIG), + GPIO_FN(RX1_B), + GPIO_FN(MSIOF1_SYNC_F), + GPIO_FN(SDA1_B), + + GPIO_IFN(MLB_DAT), + GPIO_FN(TX1_B), + GPIO_FN(MSIOF1_RXD_F), + + GPIO_IFN(SSI_SCK0129), + GPIO_FN(MSIOF1_TXD_F), + GPIO_FN(MOUT0), + + GPIO_IFN(SSI_WS0129), + GPIO_FN(MSIOF1_SS1_F), + GPIO_FN(MOUT1), + + GPIO_IFN(SSI_SDATA0), + GPIO_FN(MSIOF1_SS2_F), + GPIO_FN(MOUT2), + + /* IPSR15 */ + GPIO_IFN(SSI_SDATA1_A), + GPIO_FN(MOUT5), + + GPIO_IFN(SSI_SDATA2_A), + GPIO_FN(SSI_SCK1_B), + GPIO_FN(MOUT6), + + GPIO_IFN(SSI_SCK34), + GPIO_FN(MSIOF1_SS1_A), + GPIO_FN(STP_OPWM_0_A), + + GPIO_IFN(SSI_WS34), + GPIO_FN(HCTS2x_A), + GPIO_FN(MSIOF1_SS2_A), + GPIO_FN(STP_IVCXO27_0_A), + + GPIO_IFN(SSI_SDATA3), + GPIO_FN(HRTS2x_A), + GPIO_FN(MSIOF1_TXD_A), + GPIO_FN(TS_SCK0_A), + GPIO_FN(STP_ISCLK_0_A), + GPIO_FN(RIF0_D1_A), + GPIO_FN(RIF2_D0_A), + + GPIO_IFN(SSI_SCK4), + GPIO_FN(HRX2_A), + GPIO_FN(MSIOF1_SCK_A), + GPIO_FN(TS_SDAT0_A), + GPIO_FN(STP_ISD_0_A), + GPIO_FN(RIF0_CLK_A), + GPIO_FN(RIF2_CLK_A), + + GPIO_IFN(SSI_WS4), + GPIO_FN(HTX2_A), + GPIO_FN(MSIOF1_SYNC_A), + GPIO_FN(TS_SDEN0_A), + GPIO_FN(STP_ISEN_0_A), + GPIO_FN(RIF0_SYNC_A), + GPIO_FN(RIF2_SYNC_A), + + GPIO_IFN(SSI_SDATA4), + GPIO_FN(HSCK2_A), + GPIO_FN(MSIOF1_RXD_A), + GPIO_FN(TS_SPSYNC0_A), + GPIO_FN(STP_ISSYNC_0_A), + GPIO_FN(RIF0_D0_A), + GPIO_FN(RIF2_D1_A), + + /* IPSR16 */ + GPIO_IFN(SSI_SCK6), + GPIO_FN(SIM0_RST_D), + GPIO_FN(FSO_TOE_A), + + GPIO_IFN(SSI_WS6), + GPIO_FN(SIM0_D_D), + + GPIO_IFN(SSI_SDATA6), + GPIO_FN(SIM0_CLK_D), + + GPIO_IFN(SSI_SCK78), + GPIO_FN(HRX2_B), + GPIO_FN(MSIOF1_SCK_C), + GPIO_FN(TS_SCK1_A), + GPIO_FN(STP_ISCLK_1_A), + GPIO_FN(RIF1_CLK_A), + GPIO_FN(RIF3_CLK_A), + + GPIO_IFN(SSI_WS78), + GPIO_FN(HTX2_B), + GPIO_FN(MSIOF1_SYNC_C), + GPIO_FN(TS_SDAT1_A), + GPIO_FN(STP_ISD_1_A), + GPIO_FN(RIF1_SYNC_A), + GPIO_FN(RIF3_SYNC_A), + + GPIO_IFN(SSI_SDATA7), + GPIO_FN(HCTS2x_B), + GPIO_FN(MSIOF1_RXD_C), + GPIO_FN(TS_SDEN1_A), + GPIO_FN(STP_IEN_1_A), + GPIO_FN(RIF1_D0_A), + GPIO_FN(RIF3_D0_A), + GPIO_FN(TCLK2_A), + + GPIO_IFN(SSI_SDATA8), + GPIO_FN(HRTS2x_B), + GPIO_FN(MSIOF1_TXD_C), + GPIO_FN(TS_SPSYNC1_A), + GPIO_FN(STP_ISSYNC_1_A), + GPIO_FN(RIF1_D1_A), + GPIO_FN(EIF3_D1_A), + + GPIO_IFN(SSI_SDATA9_A), + GPIO_FN(HSCK2_B), + GPIO_FN(MSIOF1_SS1_C), + GPIO_FN(HSCK1_A), + GPIO_FN(SSI_WS1_B), + GPIO_FN(SCK1), + GPIO_FN(STP_IVCXO27_1_A), + GPIO_FN(SCK5), + + /* IPSR17 */ + GPIO_IFN(AUDIO_CLKA_A), + GPIO_FN(CC5_OSCOUT), + + GPIO_IFN(AUDIO_CLKB_B), + GPIO_FN(SCIF_CLK_A), + GPIO_FN(STP_IVCXO27_1_D), + GPIO_FN(REMOCON_A), + GPIO_FN(TCLK1_A), + + GPIO_IFN(USB0_PWEN), + GPIO_FN(SIM0_RST_C), + GPIO_FN(TS_SCK1_D), + GPIO_FN(STP_ISCLK_1_D), + GPIO_FN(BPFCLK_B), + GPIO_FN(RIF3_CLK_B), + GPIO_FN(FSO_CFE_1_A), + GPIO_FN(HSCK2_C), + + GPIO_IFN(USB0_OVC), + GPIO_FN(SIM0_D_C), + GPIO_FN(TS_SDAT1_D), + GPIO_FN(STP_ISD_1_D), + GPIO_FN(RIF3_SYNC_B), + GPIO_FN(HRX2_C), + + GPIO_IFN(USB1_PWEN), + GPIO_FN(SIM0_CLK_C), + GPIO_FN(SSI_SCK1_A), + GPIO_FN(TS_SCK0_E), + GPIO_FN(STP_ISCLK_0_E), + GPIO_FN(FMCLK_B), + GPIO_FN(RIF2_CLK_B), + GPIO_FN(SPEEDIN_A), + GPIO_FN(HTX2_C), + + GPIO_IFN(USB1_OVC), + GPIO_FN(MSIOF1_SS2_C), + GPIO_FN(SSI_WS1_A), + GPIO_FN(TS_SDAT0_E), + GPIO_FN(STP_ISD_0_E), + GPIO_FN(FMIN_B), + GPIO_FN(RIF2_SYNC_B), + GPIO_FN(REMOCON_B), + GPIO_FN(HCTS2x_C), + + GPIO_IFN(USB30_PWEN), + GPIO_FN(AUDIO_CLKOUT_B), + GPIO_FN(SSI_SCK2_B), + GPIO_FN(TS_SDEN1_D), + GPIO_FN(STP_ISEN_1_D), + GPIO_FN(STP_OPWM_0_E), + GPIO_FN(RIF3_D0_B), + GPIO_FN(TCLK2_B), + GPIO_FN(TPU0TO0), + GPIO_FN(BPFCLK_C), + GPIO_FN(HRTS2x_C), + + GPIO_IFN(USB30_OVC), + GPIO_FN(AUDIO_CLKOUT1_B), + GPIO_FN(SSI_WS2_B), + GPIO_FN(TS_SPSYNC1_D), + GPIO_FN(STP_ISSYNC_1_D), + GPIO_FN(STP_IVCXO27_0_E), + GPIO_FN(RIF3_D1_B), + GPIO_FN(FSO_TOE_B), + GPIO_FN(TPU0TO1), + + /* IPSR18 */ + GPIO_IFN(GP6_30), + GPIO_FN(AUDIO_CLKOUT2_B), + GPIO_FN(SSI_SCK9_B), + GPIO_FN(TS_SDEN0_E), + GPIO_FN(STP_ISEN_0_E), + GPIO_FN(RIF2_D0_B), + GPIO_FN(FSO_CFE_0_A), + GPIO_FN(TPU0TO2), + GPIO_FN(FMCLK_C), + GPIO_FN(FMCLK_D), + + GPIO_IFN(GP6_31), + GPIO_FN(AUDIO_CLKOUT3_B), + GPIO_FN(SSI_WS9_B), + GPIO_FN(TS_SPSYNC0_E), + GPIO_FN(STP_ISSYNC_0_E), + GPIO_FN(RIF2_D1_B), + GPIO_FN(TPU0TO3), + GPIO_FN(FMIN_C), + GPIO_FN(FMIN_D), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* GPSR0(0xE6060100) md[3:1] controls initial value */ + /* md[3:1] .. 0 : 0x0000FFFF */ + /* .. other : 0x00000000 */ + { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + GP_0_15_FN, GFN_D15, + GP_0_14_FN, GFN_D14, + GP_0_13_FN, GFN_D13, + GP_0_12_FN, GFN_D12, + GP_0_11_FN, GFN_D11, + GP_0_10_FN, GFN_D10, + GP_0_9_FN, GFN_D9, + GP_0_8_FN, GFN_D8, + GP_0_7_FN, GFN_D7, + GP_0_6_FN, GFN_D6, + GP_0_5_FN, GFN_D5, + GP_0_4_FN, GFN_D4, + GP_0_3_FN, GFN_D3, + GP_0_2_FN, GFN_D2, + GP_0_1_FN, GFN_D1, + GP_0_0_FN, GFN_D0 } + }, + /* GPSR1(0xE6060104) is md[3:1] controls initial value */ + /* md[3:1] .. 0 : 0x0EFFFFFF */ + /* .. other : 0x00000000 */ + { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + GP_1_28_FN, GFN_CLKOUT, + GP_1_27_FN, GFN_EX_WAIT0_A, + GP_1_26_FN, GFN_WE1x, + GP_1_25_FN, GFN_WE0x, + GP_1_24_FN, GFN_RD_WRx, + GP_1_23_FN, GFN_RDx, + GP_1_22_FN, GFN_BSx, + GP_1_21_FN, GFN_CS1x_A26, + GP_1_20_FN, GFN_CS0x, + GP_1_19_FN, GFN_A19, + GP_1_18_FN, GFN_A18, + GP_1_17_FN, GFN_A17, + GP_1_16_FN, GFN_A16, + GP_1_15_FN, GFN_A15, + GP_1_14_FN, GFN_A14, + GP_1_13_FN, GFN_A13, + GP_1_12_FN, GFN_A12, + GP_1_11_FN, GFN_A11, + GP_1_10_FN, GFN_A10, + GP_1_9_FN, GFN_A9, + GP_1_8_FN, GFN_A8, + GP_1_7_FN, GFN_A7, + GP_1_6_FN, GFN_A6, + GP_1_5_FN, GFN_A5, + GP_1_4_FN, GFN_A4, + GP_1_3_FN, GFN_A3, + GP_1_2_FN, GFN_A2, + GP_1_1_FN, GFN_A1, + GP_1_0_FN, GFN_A0 } + }, + /* GPSR2(0xE6060108) is md[3:1] controls */ + /* md[3:1] .. 0 : 0x000003C0 */ + /* .. other : 0x00000200 */ + { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A, + GP_2_13_FN, GFN_AVB_AVTP_MATCH_A, + GP_2_12_FN, GFN_AVB_LINK, + GP_2_11_FN, GFN_AVB_PHY_INT, + GP_2_10_FN, GFN_AVB_MAGIC, + GP_2_9_FN, GFN_AVB_MDC, + GP_2_8_FN, GFN_PWM2_A, + GP_2_7_FN, GFN_PWM1_A, + GP_2_6_FN, GFN_PWM0, + GP_2_5_FN, GFN_IRQ5, + GP_2_4_FN, GFN_IRQ4, + GP_2_3_FN, GFN_IRQ3, + GP_2_2_FN, GFN_IRQ2, + GP_2_1_FN, GFN_IRQ1, + GP_2_0_FN, GFN_IRQ0 } + }, + + /* GPSR3 */ + { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + GP_3_15_FN, GFN_SD1_WP, + GP_3_14_FN, GFN_SD1_CD, + GP_3_13_FN, GFN_SD0_WP, + GP_3_12_FN, GFN_SD0_CD, + GP_3_11_FN, GFN_SD1_DAT3, + GP_3_10_FN, GFN_SD1_DAT2, + GP_3_9_FN, GFN_SD1_DAT1, + GP_3_8_FN, GFN_SD1_DAT0, + GP_3_7_FN, GFN_SD1_CMD, + GP_3_6_FN, GFN_SD1_CLK, + GP_3_5_FN, GFN_SD0_DAT3, + GP_3_4_FN, GFN_SD0_DAT2, + GP_3_3_FN, GFN_SD0_DAT1, + GP_3_2_FN, GFN_SD0_DAT0, + GP_3_1_FN, GFN_SD0_CMD, + GP_3_0_FN, GFN_SD0_CLK } + }, + /* GPSR4 */ + { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_17_FN, GFN_SD3_DS, + GP_4_16_FN, GFN_SD3_DAT7, + + GP_4_15_FN, GFN_SD3_DAT6, + GP_4_14_FN, GFN_SD3_DAT5, + GP_4_13_FN, GFN_SD3_DAT4, + GP_4_12_FN, FN_SD3_DAT3, + GP_4_11_FN, FN_SD3_DAT2, + GP_4_10_FN, FN_SD3_DAT1, + GP_4_9_FN, FN_SD3_DAT0, + GP_4_8_FN, FN_SD3_CMD, + GP_4_7_FN, FN_SD3_CLK, + GP_4_6_FN, GFN_SD2_DS, + GP_4_5_FN, GFN_SD2_DAT3, + GP_4_4_FN, GFN_SD2_DAT2, + GP_4_3_FN, GFN_SD2_DAT1, + GP_4_2_FN, GFN_SD2_DAT0, + GP_4_1_FN, FN_SD2_CMD, + GP_4_0_FN, GFN_SD2_CLK } + }, + /* GPSR5 */ + { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_25_FN, GFN_MLB_DAT, + GP_5_24_FN, GFN_MLB_SIG, + + GP_5_23_FN, GFN_MLB_CLK, + GP_5_22_FN, FN_MSIOF0_RXD, + GP_5_21_FN, GFN_MSIOF0_SS2, + GP_5_20_FN, FN_MSIOF0_TXD, + GP_5_19_FN, GFN_MSIOF0_SS1, + GP_5_18_FN, GFN_MSIOF0_SYNC, + GP_5_17_FN, FN_MSIOF0_SCK, + GP_5_16_FN, GFN_HRTS0x, + GP_5_15_FN, GFN_HCTS0x, + GP_5_14_FN, GFN_HTX0, + GP_5_13_FN, GFN_HRX0, + GP_5_12_FN, GFN_HSCK0, + GP_5_11_FN, GFN_RX2_A, + GP_5_10_FN, GFN_TX2_A, + GP_5_9_FN, GFN_SCK2, + GP_5_8_FN, GFN_RTS1x_TANS, + GP_5_7_FN, GFN_CTS1x, + GP_5_6_FN, GFN_TX1_A, + GP_5_5_FN, GFN_RX1_A, + GP_5_4_FN, GFN_RTS0x_TANS, + GP_5_3_FN, GFN_CTS0x, + GP_5_2_FN, GFN_TX0, + GP_5_1_FN, GFN_RX0, + GP_5_0_FN, GFN_SCK0 } + }, + /* GPSR6 */ + { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) { + GP_6_31_FN, GFN_GP6_31, + GP_6_30_FN, GFN_GP6_30, + GP_6_29_FN, GFN_USB30_OVC, + GP_6_28_FN, GFN_USB30_PWEN, + GP_6_27_FN, GFN_USB1_OVC, + GP_6_26_FN, GFN_USB1_PWEN, + GP_6_25_FN, GFN_USB0_OVC, + GP_6_24_FN, GFN_USB0_PWEN, + GP_6_23_FN, GFN_AUDIO_CLKB_B, + GP_6_22_FN, GFN_AUDIO_CLKA_A, + GP_6_21_FN, GFN_SSI_SDATA9_A, + GP_6_20_FN, GFN_SSI_SDATA8, + GP_6_19_FN, GFN_SSI_SDATA7, + GP_6_18_FN, GFN_SSI_WS78, + GP_6_17_FN, GFN_SSI_SCK78, + GP_6_16_FN, GFN_SSI_SDATA6, + GP_6_15_FN, GFN_SSI_WS6, + GP_6_14_FN, GFN_SSI_SCK6, + GP_6_13_FN, FN_SSI_SDATA5, + GP_6_12_FN, FN_SSI_WS5, + GP_6_11_FN, FN_SSI_SCK5, + GP_6_10_FN, GFN_SSI_SDATA4, + GP_6_9_FN, GFN_SSI_WS4, + GP_6_8_FN, GFN_SSI_SCK4, + GP_6_7_FN, GFN_SSI_SDATA3, + GP_6_6_FN, GFN_SSI_WS34, + GP_6_5_FN, GFN_SSI_SCK34, + GP_6_4_FN, GFN_SSI_SDATA2_A, + GP_6_3_FN, GFN_SSI_SDATA1_A, + GP_6_2_FN, GFN_SSI_SDATA0, + GP_6_1_FN, GFN_SSI_WS01239, + GP_6_0_FN, GFN_SSI_SCK01239 } + }, + /* GPSR7 */ + { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_3_FN, FN_HDMI1_CEC, + GP_7_2_FN, FN_HDMI0_CEC, + GP_7_1_FN, FN_AVS2, + GP_7_0_FN, FN_AVS1 } + }, + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR0_31_28 [4] */ + IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP, + FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, + FN_MSIOF3_SS1_E, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_27_24 [4] */ + IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE, + FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, + FN_MSIOF3_SS2_E, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_23_20 [4] */ + IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_19_16 [4] */ + IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_15_12 [4] */ + IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_11_8 [4] */ + IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_7_4 [4] */ + IFN_AVB_MAGIC, 0, FN_MSIOF2_SS1_C, FN_SCK4_A, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_3_0 [4] */ + IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR1_31_28 [4] */ + IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0, + FN_VI4_DATA8, 0, FN_DU_DB0, 0, + 0, FN_PWM3_A, 0, 0, + 0, 0, 0, 0, + /* IPSR1_27_24 [4] */ + IFN_PWM2_A, FN_PWMFSW0, 0, FN_HTX3_D, + 0, 0, 0, 0, + 0, FN_IETX_B, 0, 0, + 0, 0, 0, 0, + /* IPSR1_23_20 [4] */ + IFN_PWM1_A, 0, 0, FN_HRX3_D, + FN_VI4_DATA7_B, 0, 0, 0, + 0, FN_IERX_B, 0, 0, + 0, 0, 0, 0, + /* IPSR1_19_16 [4] */ + IFN_PWM0, FN_AVB_AVTP_PPS, 0, 0, + FN_VI4_DATA6_B, 0, 0, 0, + 0, FN_IECLK_B, 0, 0, + 0, 0, 0, 0, + /* IPSR1_15_12 [4] */ + IFN_IRQ5, FN_QSTB_QHE, 0, FN_DU_EXVSYNC_DU_VSYNC, + FN_VI4_DATA5_B, 0, 0, FN_MSIOF3_TXD_E, + 0, FN_PWM6_B, 0, 0, + 0, 0, 0, 0, + /* IPSR1_11_8 [4] */ + IFN_IRQ4, FN_QSTH_QHS, 0, FN_DU_EXHSYNC_DU_HSYNC, + FN_VI4_DATA4_B, 0, 0, FN_MSIOF3_RXD_E, + 0, FN_PWM5_B, 0, 0, + 0, 0, 0, 0, + /* IPSR1_7_4 [4] */ + IFN_IRQ3, FN_QSTVB_QVE, 0, FN_DU_DOTCLKOUT1, + FN_VI4_DATA3_B, 0, 0, FN_MSIOF3_SCK_E, + 0, FN_PWM4_B, 0, 0, + 0, 0, 0, 0, + /* IPSR1_3_0 [4] */ + IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE, + FN_VI4_DATA2_B, 0, 0, FN_MSIOF3_SYNC_E, + 0, FN_PWM3_B, 0, 0, + 0, 0, 0, 0 + } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR2_31_28 [4] */ + IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B, + 0, 0, 0, FN_SDA6_A, + FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0, + 0, 0, 0, 0, + /* IPSR2_27_24 [4] */ + IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B, + FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_23_20 [4] */ + IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B, + FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_19_16 [4] */ + IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B, + FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_15_12 [4] */ + IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0, + FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_11_8 [4] */ + IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0, + FN_VI4_DATA11, 0, FN_DU_DB3, 0, + 0, FN_PWM6_A, 0, 0, + 0, 0, 0, 0, + /* IPSR2_7_4 [4] */ + IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0, + FN_VI4_DATA10, 0, FN_DU_DB2, 0, + 0, FN_PWM5_A, 0, 0, + 0, 0, 0, 0, + /* IPSR2_3_0 [4] */ + IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0, + FN_VI4_DATA9, 0, FN_DU_DB1, 0, + 0, FN_PWM4_A, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR3_31_28 [4] */ + IFN_A16, FN_LCDOUT8, 0, 0, + FN_VI4_FIELD, 0, FN_DU_DG0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_27_24 [4] */ + IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0, + FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_23_20 [4] */ + IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0, + FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_19_16 [4] */ + IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0, + FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_15_12 [4] */ + IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0, + FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_11_8 [4] */ + IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B, + FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A, + FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0, + 0, 0, 0, 0, + /* IPSR3_7_4 [4] */ + IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B, + 0, FN_VI5_HSYNCx, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_3_0 [4] */ + IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B, + 0, FN_VI5_VSYNCx, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR4_31_28 [4] */ + IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A, + FN_HTX3_A, 0, 0, 0, + FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0, + 0, 0, 0, 0, + /* IPSR4_27_24 [4] */ + IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A, + FN_HRX3_A, 0, 0, 0, + FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0, + 0, 0, 0, 0, + /* IPSR4_23_20 [4] */ + IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3, + FN_HSCK3, 0, 0, 0, + FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0, + 0, 0, 0, 0, + /* IPSR4_19_16 [4] */ + IFN_CS1x_A26, 0, 0, 0, + 0, FN_VI5_CLK, 0, FN_EX_WAIT0_B, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_15_12 [4] */ + IFN_CS0x, 0, 0, 0, + 0, FN_VI5_CLKENB, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_11_8 [4] */ + IFN_A19, FN_LCDOUT11, 0, 0, + FN_VI4_CLKENB, 0, FN_DU_DG3, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_7_4 [4] */ + IFN_A18, FN_LCDOUT10, 0, 0, + FN_VI4_HSYNCx, 0, FN_DU_DG2, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_3_0 [4] */ + IFN_A17, FN_LCDOUT9, 0, 0, + FN_VI4_VSYNCx, 0, FN_DU_DG1, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR5_31_28 [4] */ + IFN_D4, FN_MSIOF2_SCK_B, 0, 0, + FN_VI4_DATA20, FN_VI5_DATA4, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_27_24 [4] */ + IFN_D3, 0, FN_MSIOF3_TXD_A, 0, + FN_VI4_DATA19, FN_VI5_DATA3, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_23_20 [4] */ + IFN_D2, 0, FN_MSIOF3_RXD_A, 0, + FN_VI4_DATA18, FN_VI5_DATA2, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_19_16 [4] */ + IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0, + FN_VI4_DATA17, FN_VI5_DATA1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_15_12 [4] */ + IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0, + FN_VI4_DATA16, FN_VI5_DATA0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_11_8 [4] */ + IFN_EX_WAIT0_A, FN_QCLK, 0, 0, + FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_7_4 [4] */ + IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS, + FN_HRTS3x, 0, 0, FN_SDA6_B, + FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0, + 0, 0, 0, 0, + /* IPSR5_3_0 [4] */ + IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x, + FN_HCTS3x, 0, 0, FN_SCL6_B, + FN_CAN_CLK, 0, FN_IECLK_A, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR6_31_28 [4] */ + IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C, + FN_VI4_DATA4_A, 0, FN_DU_DR4, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_27_24 [4] */ + IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B, + FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_23_20 [4] */ + IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B, + FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_19_16 [4] */ + IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0, + FN_VI4_DATA1_A, 0, FN_DU_DR1, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_15_12 [4] */ + IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C, + FN_VI4_DATA0_A, 0, FN_DU_DR0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_11_8 [4] */ + IFN_D7, FN_MSIOF2_TXD_B, 0, 0, + FN_VI4_DATA23, FN_VI5_DATA7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_7_4 [4] */ + IFN_D6, FN_MSIOF2_RXD_B, 0, 0, + FN_VI4_DATA22, FN_VI5_DATA6, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_3_0 [4] */ + IFN_D5, FN_MSIOF2_SYNC_B, 0, 0, + FN_VI4_DATA21, FN_VI5_DATA5, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR7_31_28 [4] */ + IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0, + 0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_27_24 [4] */ + IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0, + 0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_23_20 [4] */ + IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0, + 0, 0, FN_STP_IVCXO27_0_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_19_16 [4] */ + IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0, + 0, 0, FN_STP_OPWM_0_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_15_12 [4] */ + FN_FSCLKST, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_11_8 [4] */ + IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C, + FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_7_4 [4] */ + IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C, + FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_3_0 [4] */ + IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C, + FN_VI4_DATA5_A, 0, FN_DU_DR5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR8_31_28 [4] */ + IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, + FN_NFRBx_B, + 0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_27_24 [4] */ + IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, + FN_NFDATA15_B, + 0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_23_20 [4] */ + IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, + FN_NFDATA14_B, + 0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_19_16 [4] */ + IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, + FN_NFWPx_B, + 0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_15_12 [4] */ + IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, + FN_NFCEx_B, + 0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_11_8 [4] */ + IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0, + 0, FN_SIM0_CLK_A, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_7_4 [4] */ + IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0, + 0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_3_0 [4] */ + IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0, + 0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR9_31_28 [4] */ + IFN_SD3_CLK, 0, FN_NFWEx, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_27_24 [4] */ + IFN_SD2_DS, 0, FN_NFALE, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_23_20 [4] */ + IFN_SD2_DAT3, 0, FN_NFDATA13, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_19_16 [4] */ + IFN_SD2_DAT2, 0, FN_NFDATA12, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_15_12 [4] */ + IFN_SD2_DAT1, 0, FN_NFDATA11, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_11_8 [4] */ + IFN_SD2_DAT0, 0, FN_NFDATA10, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_7_4 [4] */ + IFN_SD2_CMD, 0, FN_NFDATA9, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_3_0 [4] */ + IFN_SD3_CLK, 0, FN_NFDATA8, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR10_31_28 [4] */ + IFN_SD3_DAT6, FN_SD3_CD, FN_NFDATA6, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_27_24 [4] */ + IFN_SD3_DAT5, FN_SD2_WP_A, FN_NFDATA5, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_23_20 [4] */ + IFN_SD3_DAT4, FN_SD2_CD_A, FN_NFDATA4, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_19_16 [4] */ + IFN_SD3_DAT3, 0, FN_NFDATA3, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_15_12 [4] */ + IFN_SD3_DAT2, 0, FN_NFDATA2, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_11_8 [4] */ + IFN_SD3_DAT1, 0, FN_NFDATA1, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_7_4 [4] */ + IFN_SD3_DAT0, 0, FN_NFDATA0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_3_0 [4] */ + IFN_SD3_CMD, 0, FN_NFREx, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR11_31_28 [4] */ + IFN_RX0, FN_HRX1_B, 0, 0, + 0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_27_24 [4] */ + IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B, + FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM_0_C, + FN_RIF0_CLK_B, + 0, FN_ADICHS2, 0, FN_RIF0_CLK_B, + 0, 0, 0, 0, + /* IPSR11_23_20 [4] */ + IFN_SD1_WP, 0, FN_NFCEx_A, 0, + 0, FN_SIM0_D_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_19_16 [4] */ + IFN_SD1_CD, 0, FN_NFRBx_A, 0, + 0, FN_SIM0_CLK_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_15_12 [4] */ + IFN_SD0_WP, 0, FN_NFDATA15_A, 0, + FN_SDA2_B, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_11_8 [4] */ + IFN_SD0_CD, 0, FN_NFDATA14_A, 0, + FN_SCL2_B, FN_SIM0_RST_A, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_7_4 [4] */ + IFN_SD3_DS, 0, FN_NFCLE, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR11_3_0 [4] */ + IFN_SD3_DAT7, FN_SD3_WP, FN_NFDATA7, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR12_31_28 [4] */ + IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0, + 0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B, + 0, FN_ADICLK, 0, 0, + 0, 0, 0, 0, + /* IPSR12_27_24 [4] */ + IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0, + 0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B, + 0, FN_ADICHS0, 0, 0, + 0, 0, 0, 0, + /* IPSR12_23_20 [4] */ + IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0, + 0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B, + 0, FN_ADIDATA, 0, 0, + /* IPSR12_19_16 [4] */ + IFN_TX1_A, FN_HTX1_A, 0, 0, + 0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR12_15_12 [4] */ + IFN_RX1_A, FN_HRX1_A, 0, 0, + 0, FN_TS_SDAT0_C, FN_STP_ISD_0_C, FN_RIF1_CLK_C, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR12_11_8 [4] */ + IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B, + FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B, + 0, FN_ADICHS1, 0, 0, + 0, 0, 0, 0, + /* IPSR12_7_4 [4] */ + IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0, + 0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B, + FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0, + 0, 0, 0, 0, + /* IPSR12_3_0 [4] */ + IFN_TX0, FN_HTX1_B, 0, 0, + 0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR13_31_28 [4] */ + IFN_MSIOF0_SYNC, 0, 0, 0, + 0, 0, 0, 0, + FN_AUDIO_CLKOUT_A, 0, FN_TX5_B, 0, + 0, FN_BPFCLK_D, 0, 0, + /* IPSR13_27_24 [4] */ + IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0, + FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A, + FN_AUDIO_CLKOUT2_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR13_23_20 [4] */ + IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0, + FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D, + FN_RIF0_SYNC_C, + FN_AUDIO_CLKOUT1_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR13_19_16 [4] */ + IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0, + FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR13_15_12 [4] */ + IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0, + FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR13_11_8 [4] */ + IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A, + FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C, + 0, 0, FN_RX5_B, 0, + 0, 0, 0, 0, + /* IPSR13_7_4 [4] */ + IFN_RX2_A, 0, 0, FN_SD2_WP_B, + FN_SDA1_A, 0, FN_FMIN_A, FN_RIF1_SYNC_C, + 0, FN_FSO_CEF_1_B, 0, 0, + 0, 0, 0, 0, + /* IPSR13_3_0 [4] */ + IFN_TX2_A, 0, 0, FN_SD2_CD_B, + FN_SCL1_A, 0, FN_FMCLK_A, FN_RIF1_D1_C, + 0, FN_FSO_CFE_0_B, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR14_31_28 [4] */ + IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0, + 0, 0, 0, FN_MOUT2, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR14_27_24 [4] */ + IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0, + 0, 0, 0, FN_MOUT1, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR14_23_20 [4] */ + IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0, + 0, 0, 0, FN_MOUT0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR14_19_16 [4] */ + IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR14_15_12 [4] */ + IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0, + FN_SDA1_B, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR14_11_8 [4] */ + IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0, + FN_SCL1_B, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR14_7_4 [4] */ + IFN_MSIOF0_SS2, FN_TX5_A, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A, + FN_SSI_WS2_A, 0, FN_STP_OPWM_0_D, 0, + FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0, + /* IPSR14_3_0 [4] */ + IFN_MSIOF0_SS1, FN_RX5_A, 0, FN_AUDIO_CLKA_C, + FN_SSI_SCK2_A, 0, FN_STP_IVCXO27_0_C, 0, + FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR15_31_28 [4] */ + IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0, + 0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A, + FN_RIF2_D1_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR15_27_24 [4] */ + IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0, + 0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A, + FN_RIF2_SYNC_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR15_23_20 [4] */ + IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0, + 0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A, + FN_RIF2_CLK_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR15_19_16 [4] */ + IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0, + 0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A, + FN_RIF2_D0_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR15_15_12 [4] */ + IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0, + 0, 0, FN_STP_IVCXO27_0_A, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR15_11_8 [4] */ + IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0, + 0, 0, FN_STP_OPWM_0_A, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR15_7_4 [4] */ + IFN_SSI_SDATA2_A, 0, 0, 0, + FN_SSI_SCK1_B, 0, 0, FN_MOUT6, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR15_3_0 [4] */ + IFN_SSI_SDATA1_A, 0, 0, 0, + 0, 0, 0, FN_MOUT5, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR16_31_28 [4] */ + IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A, + FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR16_27_24 [4] */ + IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0, + 0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A, + FN_EIF3_D1_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR16_23_20 [4] */ + IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0, + 0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A, + FN_RIF3_D0_A, 0, FN_TCLK2_A, 0, + /* IPSR16_19_16 [4] */ + IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0, + 0, FN_TS_SDAT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A, + FN_RIF3_SYNC_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR16_15_12 [4] */ + IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0, + 0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A, + FN_RIF3_CLK_A, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR16_11_8 [4] */ + IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR16_7_4 [4] */ + IFN_SSI_WS6, 0, 0, FN_SIM0_D_D, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR16_3_0 [4] */ + IFN_SSI_SCK6, 0, 0, FN_SIM0_RST_D, + 0, 0, 0, 0, + 0, 0, FN_FSO_TOE_A, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR17_31_28 [4] */ + IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0, + FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D, + FN_STP_IVCXO27_0_E, + FN_RIF3_D1_B, 0, FN_FSO_TOE_B, FN_TPU0TO1, + 0, 0, 0, 0, + /* IPSR17_27_24 [4] */ + IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B, + FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E, + FN_RIF3_D0_B, 0, FN_TCLK2_B, FN_TPU0TO0, + FN_BPFCLK_C, FN_HRTS2x_C, 0, 0, + /* IPSR17_23_20 [4] */ + IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0, + FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B, + FN_RIF2_SYNC_B, 0, FN_REMOCON_B, 0, + 0, FN_HCTS2x_C, 0, 0, + /* IPSR17_19_16 [4] */ + IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C, + FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B, + FN_RIF2_CLK_B, 0, FN_SPEEDIN_A, 0, + 0, FN_HTX2_C, 0, 0, + /* IPSR17_15_12 [4] */ + IFN_USB0_OVC, 0, 0, FN_SIM0_D_C, + 0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0, + FN_RIF3_SYNC_B, 0, 0, 0, + 0, FN_HRX2_C, 0, 0, + /* IPSR17_11_8 [4] */ + IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C, + 0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B, + FN_RIF3_CLK_B, 0, FN_FSO_CFE_1_A, 0, + 0, FN_HSCK2_C, 0, 0, + /* IPSR17_7_4 [4] */ + IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0, + 0, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A, + 0, 0, FN_TCLK1_A, 0, + 0, 0, 0, 0, + /* IPSR17_3_0 [4] */ + IFN_AUDIO_CLKA_A, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, FN_CC5_OSCOUT, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 4, 4) { + /* reserved [31..24] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* reserved [23..16] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* reserved [15..8] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* IPSR18_7_4 [4] */ + IFN_GP6_31, 0, 0, FN_AUDIO_CLKOUT3_B, + FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0, + FN_RIF2_D1_B, 0, 0, FN_TPU0TO3, + FN_FMIN_C, FN_FMIN_D, 0, 0, + /* IPSR18_3_0 [4] */ + IFN_GP6_30, 0, 0, FN_AUDIO_CLKOUT2_B, + FN_SSI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0, + FN_RIF2_D0_B, 0, FN_FSO_CFE_0_A, FN_TPU0TO2, + FN_FMCLK_C, FN_FMCLK_D, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32, + 3, 2, 3, + 1, 1, 1, 1, 1, 2, 1, + 1, 2, 1, 1, 1, 2, + 2, 1, 2, 1, 1, 1) { + /* SEL_MSIOF3 [3] */ + FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1, + FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3, + FN_SEL_MSIOF3_4, FN_SEL_MSIOF3_5, + FN_SEL_MSIOF3_6, 0, + /* SEL_MSIOF2 [2] */ + FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, + FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3, + /* SEL_MSIOF1 [3] */ + FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, + FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3, + FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5, + FN_SEL_MSIOF1_6, 0, + + /* SEL_LBSC [1] */ + FN_SEL_LBSC_0, FN_SEL_LBSC_1, + /* SEL_IEBUS [1] */ + FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, + /* SEL_I2C2 [1] */ + FN_SEL_I2C2_0, FN_SEL_I2C2_1, + /* SEL_I2C1 [1] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, + /* SEL_HSCIF4 [1] */ + FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1, + /* SEL_HSCIF3 [2] */ + FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1, + FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3, + /* SEL_HSCIF1 [1] */ + FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, + + /* SEL_FSO [1] */ + FN_SEL_FSO_0, FN_SEL_FSO_1, + /* SEL_HSCIF2 [2] */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, 0, + /* SEL_ETHERAVB [1] */ + FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1, + /* SEL_DRIF3 [1] */ + FN_SEL_DRIF3_0, FN_SEL_DRIF3_1, + /* SEL_DRIF2 [1] */ + FN_SEL_DRIF2_0, FN_SEL_DRIF2_1, + /* SEL_DRIF1 [2] */ + FN_SEL_DRIF1_0, FN_SEL_DRIF1_1, + FN_SEL_DRIF1_2, 0, + + /* SEL_DRIF0 [2] */ + FN_SEL_DRIF0_0, FN_SEL_DRIF0_1, + FN_SEL_DRIF0_2, 0, + /* SEL_CANFD0 [1] */ + FN_SEL_CANFD_0, FN_SEL_CANFD_1, + /* SEL_ADG [2] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_ADG_2, FN_SEL_ADG_3, + /* reserved [3] */ + 0, 0, + 0, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32, + 2, 3, 1, 2, + 3, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1) { + /* SEL_TSIF1 [2] */ + FN_SEL_TSIF1_0, + FN_SEL_TSIF1_1, + FN_SEL_TSIF1_2, + FN_SEL_TSIF1_3, + /* SEL_TSIF0 [3] */ + FN_SEL_TSIF0_0, + FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, + FN_SEL_TSIF0_3, + FN_SEL_TSIF0_4, + 0, + 0, + 0, + /* SEL_TIMER_TMU [1] */ + FN_SEL_TIMER_TMU_0, + FN_SEL_TIMER_TMU_1, + /* SEL_SSP1_1 [2] */ + FN_SEL_SSP1_1_0, + FN_SEL_SSP1_1_1, + FN_SEL_SSP1_1_2, + FN_SEL_SSP1_1_3, + + /* SEL_SSP1_0 [3] */ + FN_SEL_SSP1_0_0, + FN_SEL_SSP1_0_1, + FN_SEL_SSP1_0_2, + FN_SEL_SSP1_0_3, + FN_SEL_SSP1_0_4, + 0, + 0, + 0, + /* SEL_SSI [1] */ + FN_SEL_SSI_0, + FN_SEL_SSI_1, + /* SEL_SPEED_PULSE_IF [1] */ + FN_SEL_SPEED_PULSE_IF_0, + FN_SEL_SPEED_PULSE_IF_1, + /* SEL_SIMCARD [2] */ + FN_SEL_SIMCARD_0, + FN_SEL_SIMCARD_1, + FN_SEL_SIMCARD_2, + FN_SEL_SIMCARD_3, + /* SEL_SDHI2 [1] */ + FN_SEL_SDHI2_0, + FN_SEL_SDHI2_1, + + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, + FN_SEL_SCIF4_1, + FN_SEL_SCIF4_2, + 0, + /* SEL_SCIF3 [1] */ + FN_SEL_SCIF3_0, + FN_SEL_SCIF3_1, + /* SEL_SCIF2 [1] */ + FN_SEL_SCIF2_0, + FN_SEL_SCIF2_1, + /* SEL_SCIF1 [1] */ + FN_SEL_SCIF1_0, + FN_SEL_SCIF1_1, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, + FN_SEL_SCIF_1, + /* SEL_REMOCON [1] */ + FN_SEL_REMOCON_0, + FN_SEL_REMOCON_1, + /* reserved [2] */ + 0, 0, + + 0, 0, + /* SEL_RCAN [1] */ + FN_SEL_RCAN_0, + FN_SEL_RCAN_1, + /* SEL_PWM6 [1] */ + FN_SEL_PWM6_0, + FN_SEL_PWM6_1, + /* SEL_PWM5 [1] */ + FN_SEL_PWM5_0, + FN_SEL_PWM5_1, + /* SEL_PWM4 [1] */ + FN_SEL_PWM4_0, + FN_SEL_PWM4_1, + /* SEL_PWM3 [1] */ + FN_SEL_PWM3_0, + FN_SEL_PWM3_1, + /* SEL_PWM2 [1] */ + FN_SEL_PWM2_0, + FN_SEL_PWM2_1, + /* SEL_PWM1 [1] */ + FN_SEL_PWM1_0, + FN_SEL_PWM1_1, + } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32, + 1, 1, 1, 2, 1, + 3, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1) { + /* I2C_SEL_5 [1] */ + FN_I2C_SEL_5_0, + FN_I2C_SEL_5_1, + /* I2C_SEL_3 [1] */ + FN_I2C_SEL_3_0, + FN_I2C_SEL_3_1, + /* I2C_SEL_0 [1] */ + FN_I2C_SEL_0_0, + FN_I2C_SEL_0_1, + /* SEL_FM [2] */ + FN_SEL_FM_0, + FN_SEL_FM_1, + FN_SEL_FM_2, + FN_SEL_FM_3, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, + FN_SEL_SCIF5_1, + + /* SEL_I2C6 [3] */ + FN_SEL_I2C6_0, + FN_SEL_I2C6_1, + FN_SEL_I2C6_2, + 0, + 0, + 0, + 0, + 0, + /* SEL_NDF [1] */ + FN_SEL_NDF_0, + FN_SEL_NDF_1, + /* SEL_SSI2 [1] */ + FN_SEL_SSI2_0, + FN_SEL_SSI2_1, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, + FN_SEL_SSI9_1, + /* SEL_TIMER_TME2 [1] */ + FN_SEL_TIMER_TMU2_0, + FN_SEL_TIMER_TMU2_1, + /* SEL_ADG_B [1] */ + FN_SEL_ADG_B_0, + FN_SEL_ADG_B_1, + + /* SEL_ADG_C [1] */ + FN_SEL_ADG_C_0, + FN_SEL_ADG_C_1, + /* reserved [16] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + /* SEL_VIN4 [1] */ + FN_SEL_VIN4_0, + FN_SEL_VIN4_1, + } + }, + + /* under construction */ + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + GP_0_15_IN, GP_0_15_OUT, + GP_0_14_IN, GP_0_14_OUT, + GP_0_13_IN, GP_0_13_OUT, + GP_0_12_IN, GP_0_12_OUT, + GP_0_11_IN, GP_0_11_OUT, + GP_0_10_IN, GP_0_10_OUT, + GP_0_9_IN, GP_0_9_OUT, + GP_0_8_IN, GP_0_8_OUT, + GP_0_7_IN, GP_0_7_OUT, + GP_0_6_IN, GP_0_6_OUT, + GP_0_5_IN, GP_0_5_OUT, + GP_0_4_IN, GP_0_4_OUT, + GP_0_3_IN, GP_0_3_OUT, + GP_0_2_IN, GP_0_2_OUT, + GP_0_1_IN, GP_0_1_OUT, + GP_0_0_IN, GP_0_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + GP_1_28_IN, GP_1_28_OUT, + GP_1_27_IN, GP_1_27_OUT, + GP_1_26_IN, GP_1_26_OUT, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + GP_2_14_IN, GP_2_14_OUT, + GP_2_13_IN, GP_2_13_OUT, + GP_2_12_IN, GP_2_12_OUT, + GP_2_11_IN, GP_2_11_OUT, + GP_2_10_IN, GP_2_10_OUT, + GP_2_9_IN, GP_2_9_OUT, + GP_2_8_IN, GP_2_8_OUT, + GP_2_7_IN, GP_2_7_OUT, + GP_2_6_IN, GP_2_6_OUT, + GP_2_5_IN, GP_2_5_OUT, + GP_2_4_IN, GP_2_4_OUT, + GP_2_3_IN, GP_2_3_OUT, + GP_2_2_IN, GP_2_2_OUT, + GP_2_1_IN, GP_2_1_OUT, + GP_2_0_IN, GP_2_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + GP_3_15_IN, GP_3_15_OUT, + GP_3_14_IN, GP_3_14_OUT, + GP_3_13_IN, GP_3_13_OUT, + GP_3_12_IN, GP_3_12_OUT, + GP_3_11_IN, GP_3_11_OUT, + GP_3_10_IN, GP_3_10_OUT, + GP_3_9_IN, GP_3_9_OUT, + GP_3_8_IN, GP_3_8_OUT, + GP_3_7_IN, GP_3_7_OUT, + GP_3_6_IN, GP_3_6_OUT, + GP_3_5_IN, GP_3_5_OUT, + GP_3_4_IN, GP_3_4_OUT, + GP_3_3_IN, GP_3_3_OUT, + GP_3_2_IN, GP_3_2_OUT, + GP_3_1_IN, GP_3_1_OUT, + GP_3_0_IN, GP_3_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_17_IN, GP_4_17_OUT, + GP_4_16_IN, GP_4_16_OUT, + + GP_4_15_IN, GP_4_15_OUT, + GP_4_14_IN, GP_4_14_OUT, + GP_4_13_IN, GP_4_13_OUT, + GP_4_12_IN, GP_4_12_OUT, + GP_4_11_IN, GP_4_11_OUT, + GP_4_10_IN, GP_4_10_OUT, + GP_4_9_IN, GP_4_9_OUT, + GP_4_8_IN, GP_4_8_OUT, + GP_4_7_IN, GP_4_7_OUT, + GP_4_6_IN, GP_4_6_OUT, + GP_4_5_IN, GP_4_5_OUT, + GP_4_4_IN, GP_4_4_OUT, + GP_4_3_IN, GP_4_3_OUT, + GP_4_2_IN, GP_4_2_OUT, + GP_4_1_IN, GP_4_1_OUT, + GP_4_0_IN, GP_4_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_25_IN, GP_5_25_OUT, + GP_5_24_IN, GP_5_24_OUT, + + GP_5_23_IN, GP_5_23_OUT, + GP_5_22_IN, GP_5_22_OUT, + GP_5_21_IN, GP_5_21_OUT, + GP_5_20_IN, GP_5_20_OUT, + GP_5_19_IN, GP_5_19_OUT, + GP_5_18_IN, GP_5_18_OUT, + GP_5_17_IN, GP_5_17_OUT, + GP_5_16_IN, GP_5_16_OUT, + + GP_5_15_IN, GP_5_15_OUT, + GP_5_14_IN, GP_5_14_OUT, + GP_5_13_IN, GP_5_13_OUT, + GP_5_12_IN, GP_5_12_OUT, + GP_5_11_IN, GP_5_11_OUT, + GP_5_10_IN, GP_5_10_OUT, + GP_5_9_IN, GP_5_9_OUT, + GP_5_8_IN, GP_5_8_OUT, + GP_5_7_IN, GP_5_7_OUT, + GP_5_6_IN, GP_5_6_OUT, + GP_5_5_IN, GP_5_5_OUT, + GP_5_4_IN, GP_5_4_OUT, + GP_5_3_IN, GP_5_3_OUT, + GP_5_2_IN, GP_5_2_OUT, + GP_5_1_IN, GP_5_1_OUT, + GP_5_0_IN, GP_5_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { + GP_INOUTSEL(6) + } + }, + { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_3_IN, GP_6_3_OUT, + GP_6_2_IN, GP_6_2_OUT, + GP_6_1_IN, GP_6_1_OUT, + GP_6_0_IN, GP_6_0_OUT, + } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + /* use OUTDT registers? */ + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, + GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, + GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, + GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } + }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, GP_1_28_DATA, + GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, + GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, + GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, + GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } + }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, + GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, + GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, + GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } + }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA, + GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, + GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, + GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, + GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } + }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { + 0, 0, 0, 0, + 0, 0, GP_5_25_DATA, GP_5_24_DATA, + GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, + GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, + GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, + GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, + GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, + GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } + }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { + GP_INDT(6) } + }, + { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7796_pinmux_info = { + .name = "r8a7796_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_FMIN_D, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7796_pinmux_init(void) +{ + register_pinmux(&r8a7796_pinmux_info); +} diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 740dbdf70e..6be2ab5025 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -14,6 +14,7 @@ config ROCKCHIP_RK3036 config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SUPPORT_TPL select SPL @@ -30,6 +31,7 @@ config ROCKCHIP_RK3188 config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL help diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f6e5773272..45e5379d56 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -37,6 +37,10 @@ config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 +config TARGET_SOCFPGA_ARRIA10 + bool + select SPL_BOARD_INIT if SPL + config TARGET_SOCFPGA_CYCLONE5 bool select TARGET_SOCFPGA_GEN5 @@ -49,6 +53,10 @@ choice prompt "Altera SOCFPGA board select" optional +config TARGET_SOCFPGA_ARRIA10_SOCDK + bool "Altera SOCFPGA SoCDK (Arria 10)" + select TARGET_SOCFPGA_ARRIA10 + config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" select TARGET_SOCFPGA_ARRIA5 @@ -98,6 +106,7 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC @@ -111,6 +120,7 @@ config SYS_BOARD config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES @@ -125,6 +135,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47947..41b779c5ca 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -2,21 +2,48 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# Copyright (C) 2012 Altera Corporation <www.altera.com> +# Copyright (C) 2012-2017 Altera Corporation <www.altera.com> # # SPDX-License-Identifier: GPL-2.0+ # -obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ - fpga_manager.o board.o +obj-y += board.o +obj-y += clock_manager.o +obj-y += fpga_manager.o +obj-y += misc.o +obj-y += reset_manager.o +obj-y += timer.o -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o +ifdef CONFIG_TARGET_SOCFPGA_GEN5 +obj-y += clock_manager_gen5.o +obj-y += misc_gen5.o +obj-y += reset_manager_gen5.o +obj-y += scan_manager.o +obj-y += system_manager_gen5.o +obj-y += wrap_pll_config.o +endif +ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +obj-y += clock_manager_arria10.o +obj-y += misc_arria10.o +obj-y += pinmux_arria10.o +obj-y += reset_manager_arria10.o +endif + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +ifdef CONFIG_TARGET_SOCFPGA_GEN5 +obj-y += freeze_controller.o +obj-y += wrap_iocsr_config.o +obj-y += wrap_pinmux_config.o +obj-y += wrap_sdram_config.o +endif +endif + +ifdef CONFIG_TARGET_SOCFPGA_GEN5 # QTS-generated config file wrappers -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ - wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR) +endif diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 29e18f8996..cb6ae03696 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -1,10 +1,11 @@ /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <wait_bit.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> @@ -13,12 +14,17 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; -static void cm_wait_for_lock(uint32_t mask) +void cm_wait_for_lock(u32 mask) { - register uint32_t inter_val; - uint32_t retry = 0; + u32 inter_val; + u32 retry = 0; do { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + inter_val = readl(&clock_manager_base->stat) & mask; +#endif + /* Wait for stable lock */ if (inter_val == mask) retry++; else @@ -29,510 +35,10 @@ static void cm_wait_for_lock(uint32_t mask) } /* function to poll in the fsm busy bit */ -static void cm_wait_for_fsm(void) +int cm_wait_for_fsm(void) { - while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) - ; -} - -/* - * function to write the bypass register which requires a poll of the - * busy bit - */ -static void cm_write_bypass(uint32_t val) -{ - writel(val, &clock_manager_base->bypass); - cm_wait_for_fsm(); -} - -/* function to write the ctrl register which requires a poll of the busy bit */ -static void cm_write_ctrl(uint32_t val) -{ - writel(val, &clock_manager_base->ctrl); - cm_wait_for_fsm(); -} - -/* function to write a clock register that has phase information */ -static void cm_write_with_phase(uint32_t value, - uint32_t reg_address, uint32_t mask) -{ - /* poll until phase is zero */ - while (readl(reg_address) & mask) - ; - - writel(value, reg_address); - - while (readl(reg_address) & mask) - ; -} - -/* - * Setup clocks while making no assumptions about previous state of the clocks. - * - * Start by being paranoid and gate all sw managed clocks - * Put all plls in bypass - * Put all plls VCO registers back to reset value (bandgap power down). - * Put peripheral and main pll src to reset value to avoid glitch. - * Delay 5 us. - * Deassert bandgap power down and set numerator and denominator - * Start 7 us timer. - * set internal dividers - * Wait for 7 us timer. - * Enable plls - * Set external dividers while plls are locking - * Wait for pll lock - * Assert/deassert outreset all. - * Take all pll's out of bypass - * Clear safe mode - * set source main and peripheral clocks - * Ungate clocks - */ - -void cm_basic_init(const struct cm_config * const cfg) -{ - unsigned long end; - - /* Start by being paranoid and gate all sw managed clocks */ - - /* - * We need to disable nandclk - * and then do another apb access before disabling - * gatting off the rest of the periperal clocks. - */ - writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & - readl(&clock_manager_base->per_pll.en), - &clock_manager_base->per_pll.en); - - /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ - writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | - CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | - CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | - CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, - &clock_manager_base->main_pll.en); - - writel(0, &clock_manager_base->sdr_pll.en); - - /* now we can gate off the rest of the peripheral clocks */ - writel(0, &clock_manager_base->per_pll.en); - - /* Put all plls in bypass */ - cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | - CLKMGR_BYPASS_MAINPLL); - - /* Put all plls VCO registers back to reset value. */ - writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & - ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->main_pll.vco); - writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & - ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->per_pll.vco); - writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & - ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, - &clock_manager_base->sdr_pll.vco); - - /* - * The clocks to the flash devices and the L4_MAIN clocks can - * glitch when coming out of safe mode if their source values - * are different from their reset value. So the trick it to - * put them back to their reset state, and change input - * after exiting safe mode but before ungating the clocks. - */ - writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, - &clock_manager_base->per_pll.src); - writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, - &clock_manager_base->main_pll.l4src); - - /* read back for the required 5 us delay. */ - readl(&clock_manager_base->main_pll.vco); - readl(&clock_manager_base->per_pll.vco); - readl(&clock_manager_base->sdr_pll.vco); - - - /* - * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN - * with numerator and denominator. - */ - writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); - writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); - writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); - - /* - * Time starts here. Must wait 7 us from - * BGPWRDN_SET(0) to VCO_ENABLE_SET(1). - */ - end = timer_get_us() + 7; - - /* main mpu */ - writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); - - /* altera group mpuclk */ - writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); - - /* main main clock */ - writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); - - /* main for dbg */ - writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); - - /* main for cfgs2fuser0clk */ - writel(cfg->cfg2fuser0clk, - &clock_manager_base->main_pll.cfgs2fuser0clk); - - /* Peri emac0 50 MHz default to RMII */ - writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); - - /* Peri emac1 50 MHz default to RMII */ - writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); - - /* Peri QSPI */ - writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); - - writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); - - /* Peri pernandsdmmcclk */ - writel(cfg->mainnandsdmmcclk, - &clock_manager_base->main_pll.mainnandsdmmcclk); - - writel(cfg->pernandsdmmcclk, - &clock_manager_base->per_pll.pernandsdmmcclk); - - /* Peri perbaseclk */ - writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); - - /* Peri s2fuser1clk */ - writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); - - /* 7 us must have elapsed before we can enable the VCO */ - while (timer_get_us() < end) - ; - - /* Enable vco */ - /* main pll vco */ - writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->main_pll.vco); - - /* periferal pll */ - writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->per_pll.vco); - - /* sdram pll vco */ - writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->sdr_pll.vco); - - /* L3 MP and L3 SP */ - writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); - - writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); - - writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); - - /* L4 MP, L4 SP, can0, and can1 */ - writel(cfg->perdiv, &clock_manager_base->per_pll.div); - - writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); - -#define LOCKED_MASK \ - (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ - CLKMGR_INTER_PERPLLLOCKED_MASK | \ - CLKMGR_INTER_MAINPLLLOCKED_MASK) - - cm_wait_for_lock(LOCKED_MASK); - - /* write the sdram clock counters before toggling outreset all */ - writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddrdqsclk); - - writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddr2xdqsclk); - - writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, - &clock_manager_base->sdr_pll.ddrdqclk); - - writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, - &clock_manager_base->sdr_pll.s2fuser2clk); - - /* - * after locking, but before taking out of bypass - * assert/deassert outresetall - */ - uint32_t mainvco = readl(&clock_manager_base->main_pll.vco); - - /* assert main outresetall */ - writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll.vco); - - uint32_t periphvco = readl(&clock_manager_base->per_pll.vco); - - /* assert pheriph outresetall */ - writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll.vco); - - /* assert sdram outresetall */ - writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, - &clock_manager_base->sdr_pll.vco); - - /* deassert main outresetall */ - writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->main_pll.vco); - - /* deassert pheriph outresetall */ - writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, - &clock_manager_base->per_pll.vco); - - /* deassert sdram outresetall */ - writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, - &clock_manager_base->sdr_pll.vco); - - /* - * now that we've toggled outreset all, all the clocks - * are aligned nicely; so we can change any phase. - */ - cm_write_with_phase(cfg->ddrdqsclk, - (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk, - CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); - - /* SDRAM DDR2XDQSCLK */ - cm_write_with_phase(cfg->ddr2xdqsclk, - (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk, - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); - - cm_write_with_phase(cfg->ddrdqclk, - (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk, - CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); - - cm_write_with_phase(cfg->s2fuser2clk, - (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk, - CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); - - /* Take all three PLLs out of bypass when safe mode is cleared. */ - cm_write_bypass(0); - - /* clear safe mode */ - cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); - - /* - * now that safe mode is clear with clocks gated - * it safe to change the source mux for the flashes the the L4_MAIN - */ - writel(cfg->persrc, &clock_manager_base->per_pll.src); - writel(cfg->l4src, &clock_manager_base->main_pll.l4src); - - /* Now ungate non-hw-managed clocks */ - writel(~0, &clock_manager_base->main_pll.en); - writel(~0, &clock_manager_base->per_pll.en); - writel(~0, &clock_manager_base->sdr_pll.en); - - /* Clear the loss of lock bits (write 1 to clear) */ - writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | - CLKMGR_INTER_MAINPLLLOST_MASK, - &clock_manager_base->inter); -} - -static unsigned int cm_get_main_vco_clk_hz(void) -{ - uint32_t reg, clock; - - /* get the main VCO clock */ - reg = readl(&clock_manager_base->main_pll.vco); - clock = cm_get_osc_clk_hz(1); - clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> - CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; - clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> - CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; - - return clock; -} - -static unsigned int cm_get_per_vco_clk_hz(void) -{ - uint32_t reg, clock = 0; - - /* identify PER PLL clock source */ - reg = readl(&clock_manager_base->per_pll.vco); - reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> - CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = cm_get_osc_clk_hz(1); - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = cm_get_osc_clk_hz(2); - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = cm_get_f2s_per_ref_clk_hz(); - - /* get the PER VCO clock */ - reg = readl(&clock_manager_base->per_pll.vco); - clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> - CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; - clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> - CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; - - return clock; -} - -unsigned long cm_get_mpu_clk_hz(void) -{ - uint32_t reg, clock; - - clock = cm_get_main_vco_clk_hz(); - - /* get the MPU clock */ - reg = readl(&clock_manager_base->altera.mpuclk); - clock /= (reg + 1); - reg = readl(&clock_manager_base->main_pll.mpuclk); - clock /= (reg + 1); - return clock; -} - -unsigned long cm_get_sdram_clk_hz(void) -{ - uint32_t reg, clock = 0; - - /* identify SDRAM PLL clock source */ - reg = readl(&clock_manager_base->sdr_pll.vco); - reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> - CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; - if (reg == CLKMGR_VCO_SSRC_EOSC1) - clock = cm_get_osc_clk_hz(1); - else if (reg == CLKMGR_VCO_SSRC_EOSC2) - clock = cm_get_osc_clk_hz(2); - else if (reg == CLKMGR_VCO_SSRC_F2S) - clock = cm_get_f2s_sdr_ref_clk_hz(); - - /* get the SDRAM VCO clock */ - reg = readl(&clock_manager_base->sdr_pll.vco); - clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> - CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; - clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> - CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; - - /* get the SDRAM (DDR_DQS) clock */ - reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); - reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> - CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; - clock /= (reg + 1); - - return clock; -} - -unsigned int cm_get_l4_sp_clk_hz(void) -{ - uint32_t reg, clock = 0; - - /* identify the source of L4 SP clock */ - reg = readl(&clock_manager_base->main_pll.l4src); - reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> - CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; - - if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { - clock = cm_get_main_vco_clk_hz(); - - /* get the clock prior L4 SP divider (main clk) */ - reg = readl(&clock_manager_base->altera.mainclk); - clock /= (reg + 1); - reg = readl(&clock_manager_base->main_pll.mainclk); - clock /= (reg + 1); - } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { - clock = cm_get_per_vco_clk_hz(); - - /* get the clock prior L4 SP divider (periph_base_clk) */ - reg = readl(&clock_manager_base->per_pll.perbaseclk); - clock /= (reg + 1); - } - - /* get the L4 SP clock which supplied to UART */ - reg = readl(&clock_manager_base->main_pll.maindiv); - reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> - CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; - clock = clock / (1 << reg); - - return clock; -} - -unsigned int cm_get_mmc_controller_clk_hz(void) -{ - uint32_t reg, clock = 0; - - /* identify the source of MMC clock */ - reg = readl(&clock_manager_base->per_pll.src); - reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> - CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; - - if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { - clock = cm_get_f2s_per_ref_clk_hz(); - } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { - clock = cm_get_main_vco_clk_hz(); - - /* get the SDMMC clock */ - reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); - clock /= (reg + 1); - } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { - clock = cm_get_per_vco_clk_hz(); - - /* get the SDMMC clock */ - reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); - clock /= (reg + 1); - } - - /* further divide by 4 as we have fixed divider at wrapper */ - clock /= 4; - return clock; -} - -unsigned int cm_get_qspi_controller_clk_hz(void) -{ - uint32_t reg, clock = 0; - - /* identify the source of QSPI clock */ - reg = readl(&clock_manager_base->per_pll.src); - reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> - CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; - - if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { - clock = cm_get_f2s_per_ref_clk_hz(); - } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { - clock = cm_get_main_vco_clk_hz(); - - /* get the qspi clock */ - reg = readl(&clock_manager_base->main_pll.mainqspiclk); - clock /= (reg + 1); - } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { - clock = cm_get_per_vco_clk_hz(); - - /* get the qspi clock */ - reg = readl(&clock_manager_base->per_pll.perqspiclk); - clock /= (reg + 1); - } - - return clock; -} - -unsigned int cm_get_spi_controller_clk_hz(void) -{ - uint32_t reg, clock = 0; - - clock = cm_get_per_vco_clk_hz(); - - /* get the clock prior L4 SP divider (periph_base_clk) */ - reg = readl(&clock_manager_base->per_pll.perbaseclk); - clock /= (reg + 1); - - return clock; -} - -static void cm_print_clock_quick_summary(void) -{ - printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); - printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000); - printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000); - printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000); - printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000); - printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000); - printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); - printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); - printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); - printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); + return wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat, + CLKMGR_STAT_BUSY, false, 20000, false); } int set_cpu_clk_info(void) @@ -543,7 +49,12 @@ int set_cpu_clk_info(void) gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; + +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + gd->bd->bi_ddr_freq = 0; +#endif return 0; } diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c new file mode 100644 index 0000000000..482b8543f4 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -0,0 +1,1096 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static u32 eosc1_hz; +static u32 cb_intosc_hz; +static u32 f2s_free_hz; +static u32 cm_l4_main_clk_hz; +static u32 cm_l4_sp_clk_hz; +static u32 cm_l4_mp_clk_hz; +static u32 cm_l4_sys_free_clk_hz; + +struct mainpll_cfg { + u32 vco0_psrc; + u32 vco1_denom; + u32 vco1_numer; + u32 mpuclk; + u32 mpuclk_cnt; + u32 mpuclk_src; + u32 nocclk; + u32 nocclk_cnt; + u32 nocclk_src; + u32 cntr2clk_cnt; + u32 cntr3clk_cnt; + u32 cntr4clk_cnt; + u32 cntr5clk_cnt; + u32 cntr6clk_cnt; + u32 cntr7clk_cnt; + u32 cntr7clk_src; + u32 cntr8clk_cnt; + u32 cntr9clk_cnt; + u32 cntr9clk_src; + u32 cntr15clk_cnt; + u32 nocdiv_l4mainclk; + u32 nocdiv_l4mpclk; + u32 nocdiv_l4spclk; + u32 nocdiv_csatclk; + u32 nocdiv_cstraceclk; + u32 nocdiv_cspdbclk; +}; + +struct perpll_cfg { + u32 vco0_psrc; + u32 vco1_denom; + u32 vco1_numer; + u32 cntr2clk_cnt; + u32 cntr2clk_src; + u32 cntr3clk_cnt; + u32 cntr3clk_src; + u32 cntr4clk_cnt; + u32 cntr4clk_src; + u32 cntr5clk_cnt; + u32 cntr5clk_src; + u32 cntr6clk_cnt; + u32 cntr6clk_src; + u32 cntr7clk_cnt; + u32 cntr8clk_cnt; + u32 cntr8clk_src; + u32 cntr9clk_cnt; + u32 emacctl_emac0sel; + u32 emacctl_emac1sel; + u32 emacctl_emac2sel; + u32 gpiodiv_gpiodbclk; +}; + +struct alteragrp_cfg { + u32 nocclk; + u32 mpuclk; +}; + +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; + +static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg) +{ + if (fdtdec_get_int_array(blob, node, "altr,of_reg_value", + (u32 *)cfg, cfg_len)) { + /* could not find required property */ + return -EINVAL; + } + + return 0; +} + +static int of_get_input_clks(const void *blob, int node, u32 *val) +{ + *val = fdtdec_get_uint(blob, node, "clock-frequency", 0); + if (!*val) + return -EINVAL; + + return 0; +} + +static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + struct alteragrp_cfg *altrgrp_cfg) +{ + int node, child, len; + const char *node_name; + + node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK); + if (node < 0) + return -EINVAL; + + child = fdt_first_subnode(blob, node); + if (child < 0) + return -EINVAL; + + child = fdt_first_subnode(blob, child); + if (child < 0) + return -EINVAL; + + node_name = fdt_get_name(blob, child, &len); + + while (node_name) { + if (!strcmp(node_name, "osc1")) { + if (of_get_input_clks(blob, child, &eosc1_hz)) + return -EINVAL; + } else if (!strcmp(node_name, "cb_intosc_ls_clk")) { + if (of_get_input_clks(blob, child, &cb_intosc_hz)) + return -EINVAL; + } else if (!strcmp(node_name, "f2s_free_clk")) { + if (of_get_input_clks(blob, child, &f2s_free_hz)) + return -EINVAL; + } else if (!strcmp(node_name, "main_pll")) { + if (of_to_struct(blob, child, + sizeof(*main_cfg)/sizeof(u32), + main_cfg)) + return -EINVAL; + } else if (!strcmp(node_name, "periph_pll")) { + if (of_to_struct(blob, child, + sizeof(*per_cfg)/sizeof(u32), + per_cfg)) + return -EINVAL; + } else if (!strcmp(node_name, "altera")) { + if (of_to_struct(blob, child, + sizeof(*altrgrp_cfg)/sizeof(u32), + altrgrp_cfg)) + return -EINVAL; + + main_cfg->mpuclk = altrgrp_cfg->mpuclk; + main_cfg->nocclk = altrgrp_cfg->nocclk; + } + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, &len); + } + + return 0; +} + +/* calculate the intended main VCO frequency based on handoff */ +static unsigned int cm_calc_handoff_main_vco_clk_hz + (struct mainpll_cfg *main_cfg) +{ + unsigned int clk_hz; + + /* Check main VCO clock source: eosc, intosc or f2s? */ + switch (main_cfg->vco0_psrc) { + case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + /* calculate the VCO frequency */ + clk_hz /= 1 + main_cfg->vco1_denom; + clk_hz *= 1 + main_cfg->vco1_numer; + + return clk_hz; +} + +/* calculate the intended periph VCO frequency based on handoff */ +static unsigned int cm_calc_handoff_periph_vco_clk_hz( + struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) +{ + unsigned int clk_hz; + + /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ + switch (per_cfg->vco0_psrc) { + case CLKMGR_PERPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= main_cfg->cntr15clk_cnt; + break; + default: + return 0; + } + + /* calculate the VCO frequency */ + clk_hz /= 1 + per_cfg->vco1_denom; + clk_hz *= 1 + per_cfg->vco1_numer; + + return clk_hz; +} + +/* calculate the intended MPU clock frequency based on handoff */ +static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg) +{ + unsigned int clk_hz; + + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (main_cfg->mpuclk_src) { + case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + + 1; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: + clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); + clk_hz /= ((main_cfg->mpuclk >> + CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + clk_hz /= main_cfg->mpuclk_cnt + 1; + return clk_hz; +} + +/* calculate the intended NOC clock frequency based on handoff */ +static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg) +{ + unsigned int clk_hz; + + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (main_cfg->nocclk_src) { + case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + + 1; + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: + clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); + clk_hz /= ((main_cfg->nocclk >> + CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1; + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + + clk_hz /= main_cfg->nocclk_cnt + 1; + return clk_hz; +} + +/* return 1 if PLL ramp is required */ +static int cm_is_pll_ramp_required(int main0periph1, + struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg) +{ + /* Check for main PLL */ + if (main0periph1 == 0) { + /* + * PLL ramp is not required if both MPU clock and NOC clock are + * not sourced from main PLL + */ + if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && + main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) + return 0; + + /* + * PLL ramp is required if MPU clock is sourced from main PLL + * and MPU clock is over 900MHz (as advised by HW team) + */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && + (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) + return 1; + + /* + * PLL ramp is required if NOC clock is sourced from main PLL + * and NOC clock is over 300MHz (as advised by HW team) + */ + if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && + (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) + return 2; + + } else if (main0periph1 == 1) { + /* + * PLL ramp is not required if both MPU clock and NOC clock are + * not sourced from periph PLL + */ + if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && + main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) + return 0; + + /* + * PLL ramp is required if MPU clock are source from periph PLL + * and MPU clock is over 900MHz (as advised by HW team) + */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && + (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) + return 1; + + /* + * PLL ramp is required if NOC clock are source from periph PLL + * and NOC clock is over 300MHz (as advised by HW team) + */ + if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && + (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > + CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) + return 2; + } + + return 0; +} + +static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + u32 safe_hz, u32 clk_hz) +{ + u32 cnt; + u32 clk; + u32 shift; + u32 mask; + u32 denom; + + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { + cnt = main_cfg->mpuclk_cnt; + clk = main_cfg->mpuclk; + shift = 0; + mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; + denom = main_cfg->vco1_denom; + } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { + cnt = main_cfg->nocclk_cnt; + clk = main_cfg->nocclk; + shift = 0; + mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; + denom = main_cfg->vco1_denom; + } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { + cnt = main_cfg->mpuclk_cnt; + clk = main_cfg->mpuclk; + shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB; + mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; + denom = per_cfg->vco1_denom; + } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { + cnt = main_cfg->nocclk_cnt; + clk = main_cfg->nocclk; + shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB; + mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; + denom = per_cfg->vco1_denom; + } else { + return 0; + } + + return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) * + (1 + denom) - 1; +} + +/* + * Calculate the new PLL numerator which is based on existing DTS hand off and + * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the + * numerator while maintaining denominator as denominator will influence the + * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final + * value for numerator is minus with 1 to cater our register value + * representation. + */ +static unsigned int cm_calc_safe_pll_numer(int main0periph1, + struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + unsigned int safe_hz) +{ + unsigned int clk_hz = 0; + + /* Check for main PLL */ + if (main0periph1 == 0) { + /* Check main VCO clock source: eosc, intosc or f2s? */ + switch (main_cfg->vco0_psrc) { + case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + default: + return 0; + } + } else if (main0periph1 == 1) { + /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ + switch (per_cfg->vco0_psrc) { + case CLKMGR_PERPLL_VCO0_PSRC_EOSC: + clk_hz = eosc1_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_F2S: + clk_hz = f2s_free_hz; + break; + case CLKMGR_PERPLL_VCO0_PSRC_MAIN: + clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); + clk_hz /= main_cfg->cntr15clk_cnt; + break; + default: + return 0; + } + } else { + return 0; + } + + return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz); +} + +/* ramping the main PLL to final value */ +static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + unsigned int pll_ramp_main_hz) +{ + unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; + + /* find out the increment value */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { + clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); + } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { + clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); + } + + /* execute the ramping here */ + for (clk_hz = pll_ramp_main_hz + clk_incr_hz; + clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { + writel((main_cfg->vco1_denom << + CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), + &clock_manager_base->main_pll.vco1); + mdelay(1); + cm_wait_for_lock(LOCKED_MASK); + } + writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1); + mdelay(1); + cm_wait_for_lock(LOCKED_MASK); +} + +/* ramping the periph PLL to final value */ +static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, + struct perpll_cfg *per_cfg, + unsigned int pll_ramp_periph_hz) +{ + unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; + + /* find out the increment value */ + if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { + clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); + } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { + clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; + clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); + } + /* execute the ramping here */ + for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; + clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz), + &clock_manager_base->per_pll.vco1); + mdelay(1); + cm_wait_for_lock(LOCKED_MASK); + } + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1); + mdelay(1); + cm_wait_for_lock(LOCKED_MASK); +} + +/* + * Setup clocks while making no assumptions of the + * previous state of the clocks. + * + * Start by being paranoid and gate all sw managed clocks + * + * Put all plls in bypass + * + * Put all plls VCO registers back to reset value (bgpwr dwn). + * + * Put peripheral and main pll src to reset value to avoid glitch. + * + * Delay 5 us. + * + * Deassert bg pwr dn and set numerator and denominator + * + * Start 7 us timer. + * + * set internal dividers + * + * Wait for 7 us timer. + * + * Enable plls + * + * Set external dividers while plls are locking + * + * Wait for pll lock + * + * Assert/deassert outreset all. + * + * Take all pll's out of bypass + * + * Clear safe mode + * + * set source main and peripheral clocks + * + * Ungate clocks + */ + +static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) +{ + unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, + ramp_required; + + /* gate off all mainpll clock excpet HW managed clock */ + writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | + CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, + &clock_manager_base->main_pll.enr); + + /* now we can gate off the rest of the peripheral clocks */ + writel(0, &clock_manager_base->per_pll.en); + + /* Put all plls in external bypass */ + writel(CLKMGR_MAINPLL_BYPASS_RESET, + &clock_manager_base->main_pll.bypasss); + writel(CLKMGR_PERPLL_BYPASS_RESET, + &clock_manager_base->per_pll.bypasss); + + /* + * Put all plls VCO registers back to reset value. + * Some code might have messed with them. At same time set the + * desired clock source + */ + writel(CLKMGR_MAINPLL_VCO0_RESET | + CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | + (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), + &clock_manager_base->main_pll.vco0); + + writel(CLKMGR_PERPLL_VCO0_RESET | + CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | + (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), + &clock_manager_base->per_pll.vco0); + + writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1); + writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1); + + /* clear the interrupt register status register */ + writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, + &clock_manager_base->intr); + + /* Program VCO Numerator and Denominator for main PLL */ + ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); + if (ramp_required) { + /* set main PLL to safe starting threshold frequency */ + if (ramp_required == 1) + pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; + else if (ramp_required == 2) + pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; + + writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(0, main_cfg, per_cfg, + pll_ramp_main_hz), + &clock_manager_base->main_pll.vco1); + } else + writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | + main_cfg->vco1_numer, + &clock_manager_base->main_pll.vco1); + + /* Program VCO Numerator and Denominator for periph PLL */ + ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); + if (ramp_required) { + /* set periph PLL to safe starting threshold frequency */ + if (ramp_required == 1) + pll_ramp_periph_hz = + CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; + else if (ramp_required == 2) + pll_ramp_periph_hz = + CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; + + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + cm_calc_safe_pll_numer(1, main_cfg, per_cfg, + pll_ramp_periph_hz), + &clock_manager_base->per_pll.vco1); + } else + writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | + per_cfg->vco1_numer, + &clock_manager_base->per_pll.vco1); + + /* Wait for at least 5 us */ + udelay(5); + + /* Now deassert BGPWRDN and PWRDN */ + clrbits_le32(&clock_manager_base->main_pll.vco0, + CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | + CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); + clrbits_le32(&clock_manager_base->per_pll.vco0, + CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | + CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); + + /* Wait for at least 7 us */ + udelay(7); + + /* enable the VCO and disable the external regulator to PLL */ + writel((readl(&clock_manager_base->main_pll.vco0) & + ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | + CLKMGR_MAINPLL_VCO0_EN_SET_MSK, + &clock_manager_base->main_pll.vco0); + writel((readl(&clock_manager_base->per_pll.vco0) & + ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | + CLKMGR_PERPLL_VCO0_EN_SET_MSK, + &clock_manager_base->per_pll.vco0); + + /* setup all the main PLL counter and clock source */ + writel(main_cfg->nocclk, + SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET); + writel(main_cfg->mpuclk, + SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET); + + /* main_emaca_clk divider */ + writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk); + /* main_emacb_clk divider */ + writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk); + /* main_emac_ptp_clk divider */ + writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk); + /* main_gpio_db_clk divider */ + writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk); + /* main_sdmmc_clk divider */ + writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk); + /* main_s2f_user0_clk divider */ + writel(main_cfg->cntr7clk_cnt | + (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), + &clock_manager_base->main_pll.cntr7clk); + /* main_s2f_user1_clk divider */ + writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk); + /* main_hmc_pll_clk divider */ + writel(main_cfg->cntr9clk_cnt | + (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), + &clock_manager_base->main_pll.cntr9clk); + /* main_periph_ref_clk divider */ + writel(main_cfg->cntr15clk_cnt, + &clock_manager_base->main_pll.cntr15clk); + + /* setup all the peripheral PLL counter and clock source */ + /* peri_emaca_clk divider */ + writel(per_cfg->cntr2clk_cnt | + (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr2clk); + /* peri_emacb_clk divider */ + writel(per_cfg->cntr3clk_cnt | + (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr3clk); + /* peri_emac_ptp_clk divider */ + writel(per_cfg->cntr4clk_cnt | + (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr4clk); + /* peri_gpio_db_clk divider */ + writel(per_cfg->cntr5clk_cnt | + (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr5clk); + /* peri_sdmmc_clk divider */ + writel(per_cfg->cntr6clk_cnt | + (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr6clk); + /* peri_s2f_user0_clk divider */ + writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk); + /* peri_s2f_user1_clk divider */ + writel(per_cfg->cntr8clk_cnt | + (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), + &clock_manager_base->per_pll.cntr8clk); + /* peri_hmc_pll_clk divider */ + writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk); + + /* setup all the external PLL counter */ + /* mpu wrapper / external divider */ + writel(main_cfg->mpuclk_cnt | + (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), + &clock_manager_base->main_pll.mpuclk); + /* NOC wrapper / external divider */ + writel(main_cfg->nocclk_cnt | + (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), + &clock_manager_base->main_pll.nocclk); + /* NOC subclock divider such as l4 */ + writel(main_cfg->nocdiv_l4mainclk | + (main_cfg->nocdiv_l4mpclk << + CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | + (main_cfg->nocdiv_l4spclk << + CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | + (main_cfg->nocdiv_csatclk << + CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | + (main_cfg->nocdiv_cstraceclk << + CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | + (main_cfg->nocdiv_cspdbclk << + CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), + &clock_manager_base->main_pll.nocdiv); + /* gpio_db external divider */ + writel(per_cfg->gpiodiv_gpiodbclk, + &clock_manager_base->per_pll.gpiodiv); + + /* setup the EMAC clock mux select */ + writel((per_cfg->emacctl_emac0sel << + CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | + (per_cfg->emacctl_emac1sel << + CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | + (per_cfg->emacctl_emac2sel << + CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), + &clock_manager_base->per_pll.emacctl); + + /* at this stage, check for PLL lock status */ + cm_wait_for_lock(LOCKED_MASK); + + /* + * after locking, but before taking out of bypass, + * assert/deassert outresetall + */ + /* assert mainpll outresetall */ + setbits_le32(&clock_manager_base->main_pll.vco0, + CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); + /* assert perpll outresetall */ + setbits_le32(&clock_manager_base->per_pll.vco0, + CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); + /* de-assert mainpll outresetall */ + clrbits_le32(&clock_manager_base->main_pll.vco0, + CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); + /* de-assert perpll outresetall */ + clrbits_le32(&clock_manager_base->per_pll.vco0, + CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); + + /* Take all PLLs out of bypass when boot mode is cleared. */ + /* release mainpll from bypass */ + writel(CLKMGR_MAINPLL_BYPASS_RESET, + &clock_manager_base->main_pll.bypassr); + /* wait till Clock Manager is not busy */ + cm_wait_for_fsm(); + + /* release perpll from bypass */ + writel(CLKMGR_PERPLL_BYPASS_RESET, + &clock_manager_base->per_pll.bypassr); + /* wait till Clock Manager is not busy */ + cm_wait_for_fsm(); + + /* clear boot mode */ + clrbits_le32(&clock_manager_base->ctrl, + CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); + /* wait till Clock Manager is not busy */ + cm_wait_for_fsm(); + + /* At here, we need to ramp to final value if needed */ + if (pll_ramp_main_hz != 0) + cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); + if (pll_ramp_periph_hz != 0) + cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); + + /* Now ungate non-hw-managed clocks */ + writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | + CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, + &clock_manager_base->main_pll.ens); + writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens); + + /* Clear the loss lock and slip bits as they might set during + clock reconfiguration */ + writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | + CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, + &clock_manager_base->intr); + + return 0; +} + +void cm_use_intosc(void) +{ + setbits_le32(&clock_manager_base->ctrl, + CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); +} + +unsigned int cm_get_noc_clk_hz(void) +{ + unsigned int clk_src, divisor, nocclk, src_hz; + + nocclk = readl(&clock_manager_base->main_pll.nocclk); + clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) & + CLKMGR_MAINPLL_NOCCLK_SRC_MSK; + + divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK); + + if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) { + src_hz = cm_get_main_vco_clk_hz(); + src_hz /= 1 + + (readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) & + CLKMGR_MAINPLL_NOCCLK_CNT_MSK); + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) { + src_hz = cm_get_per_vco_clk_hz(); + src_hz /= 1 + + ((readl(SOCFPGA_CLKMGR_ADDRESS + + CLKMGR_MAINPLL_NOC_CLK_OFFSET) >> + CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_NOCCLK_CNT_MSK); + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) { + src_hz = eosc1_hz; + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) { + src_hz = cb_intosc_hz; + } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) { + src_hz = f2s_free_hz; + } else { + src_hz = 0; + } + + return src_hz / divisor; +} + +unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift) +{ + unsigned int divisor2 = 1 << + ((readl(&clock_manager_base->main_pll.nocdiv) >> + nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK); + + return cm_get_noc_clk_hz() / divisor2; +} + +int cm_basic_init(const void *blob) +{ + struct mainpll_cfg main_cfg; + struct perpll_cfg per_cfg; + struct alteragrp_cfg altrgrp_cfg; + int rval; + + /* initialize to zero for use case of optional node */ + memset(&main_cfg, 0, sizeof(main_cfg)); + memset(&per_cfg, 0, sizeof(per_cfg)); + memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg)); + + rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg); + if (rval) + return rval; + + rval = cm_full_cfg(&main_cfg, &per_cfg); + + cm_l4_main_clk_hz = + cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); + + cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); + + cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz(); + + cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4; + + return rval; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + u32 reg, clk_hz; + u32 clk_src, mainmpuclk_reg; + + mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk); + + clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) & + CLKMGR_MAINPLL_MPUCLK_SRC_MSK; + + reg = readl(&clock_manager_base->altera.mpuclk); + /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ + switch (clk_src) { + case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: + clk_hz = cm_get_main_vco_clk_hz(); + clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: + clk_hz = cm_get_per_vco_clk_hz(); + clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & + CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1); + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: + clk_hz = eosc1_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + default: + printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src); + return 0; + } + + clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; + + return clk_hz; +} + +unsigned int cm_get_per_vco_clk_hz(void) +{ + u32 src_hz = 0; + u32 clk_src = 0; + u32 numer = 0; + u32 denom = 0; + u32 vco = 0; + + clk_src = readl(&clock_manager_base->per_pll.vco0); + + clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) & + CLKMGR_PERPLL_VCO0_PSRC_MSK; + + if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) { + src_hz = eosc1_hz; + } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) { + src_hz = cb_intosc_hz; + } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) { + src_hz = f2s_free_hz; + } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) { + src_hz = cm_get_main_vco_clk_hz(); + src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) & + CLKMGR_MAINPLL_CNTRCLK_MSK) + 1; + } else { + printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src); + return 0; + } + + vco = readl(&clock_manager_base->per_pll.vco1); + + numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK; + + denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & + CLKMGR_PERPLL_VCO1_DENOM_MSK; + + vco = src_hz; + vco /= 1 + denom; + vco *= 1 + numer; + + return vco; +} + +unsigned int cm_get_main_vco_clk_hz(void) +{ + u32 src_hz, numer, denom, vco; + + u32 clk_src = readl(&clock_manager_base->main_pll.vco0); + + clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) & + CLKMGR_MAINPLL_VCO0_PSRC_MSK; + + if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) { + src_hz = eosc1_hz; + } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) { + src_hz = cb_intosc_hz; + } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) { + src_hz = f2s_free_hz; + } else { + printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src); + return 0; + } + + vco = readl(&clock_manager_base->main_pll.vco1); + + numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK; + + denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) & + CLKMGR_MAINPLL_VCO1_DENOM_MSK; + + vco = src_hz; + vco /= 1 + denom; + vco *= 1 + numer; + + return vco; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB); +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + u32 clk_hz = 0; + u32 clk_input = 0; + + clk_input = readl(&clock_manager_base->per_pll.cntr6clk); + clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) & + CLKMGR_PERPLLGRP_SRC_MSK; + + switch (clk_input) { + case CLKMGR_PERPLLGRP_SRC_MAIN: + clk_hz = cm_get_main_vco_clk_hz(); + clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) & + CLKMGR_MAINPLL_CNTRCLK_MSK); + break; + + case CLKMGR_PERPLLGRP_SRC_PERI: + clk_hz = cm_get_per_vco_clk_hz(); + clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) & + CLKMGR_PERPLL_CNTRCLK_MSK); + break; + + case CLKMGR_PERPLLGRP_SRC_OSC1: + clk_hz = eosc1_hz; + break; + + case CLKMGR_PERPLLGRP_SRC_INTOSC: + clk_hz = cb_intosc_hz; + break; + + case CLKMGR_PERPLLGRP_SRC_FPGA: + clk_hz = f2s_free_hz; + break; + } + + return clk_hz / 4; +} + +unsigned int cm_get_spi_controller_clk_hz(void) +{ + return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB); +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); + printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); + printf("EOSC1 %8d kHz\n", eosc1_hz / 1000); + printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000); + printf("f2s_free %8d kHz\n", f2s_free_hz / 1000); + printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz() / 1000); + printf("NOC %8d kHz\n", cm_get_noc_clk_hz() / 1000); + printf("L4 Main %8d kHz\n", + cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000); + printf("L4 MP %8d kHz\n", + cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000); + printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); + printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000); +} diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c new file mode 100644 index 0000000000..31fd51097a --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -0,0 +1,524 @@ +/* + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> +#include <wait_bit.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_clock_manager *clock_manager_base = + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void cm_write_bypass(u32 val) +{ + writel(val, &clock_manager_base->bypass); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void cm_write_ctrl(u32 val) +{ + writel(val, &clock_manager_base->ctrl); + cm_wait_for_fsm(); +} + +/* function to write a clock register that has phase information */ +static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask) +{ + int ret; + + /* poll until phase is zero */ + ret = wait_for_bit(__func__, (const u32 *)reg_address, mask, + false, 20000, false); + if (ret) + return ret; + + writel(value, reg_address); + + return wait_for_bit(__func__, (const u32 *)reg_address, mask, + false, 20000, false); +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + * + * Start by being paranoid and gate all sw managed clocks + * Put all plls in bypass + * Put all plls VCO registers back to reset value (bandgap power down). + * Put peripheral and main pll src to reset value to avoid glitch. + * Delay 5 us. + * Deassert bandgap power down and set numerator and denominator + * Start 7 us timer. + * set internal dividers + * Wait for 7 us timer. + * Enable plls + * Set external dividers while plls are locking + * Wait for pll lock + * Assert/deassert outreset all. + * Take all pll's out of bypass + * Clear safe mode + * set source main and peripheral clocks + * Ungate clocks + */ + +int cm_basic_init(const struct cm_config * const cfg) +{ + unsigned long end; + int ret; + + /* Start by being paranoid and gate all sw managed clocks */ + + /* + * We need to disable nandclk + * and then do another apb access before disabling + * gatting off the rest of the periperal clocks. + */ + writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & + readl(&clock_manager_base->per_pll.en), + &clock_manager_base->per_pll.en); + + /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ + writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | + CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | + CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | + CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, + &clock_manager_base->main_pll.en); + + writel(0, &clock_manager_base->sdr_pll.en); + + /* now we can gate off the rest of the peripheral clocks */ + writel(0, &clock_manager_base->per_pll.en); + + /* Put all plls in bypass */ + cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | + CLKMGR_BYPASS_MAINPLL); + + /* Put all plls VCO registers back to reset value. */ + writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->main_pll.vco); + writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->per_pll.vco); + writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & + ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, + &clock_manager_base->sdr_pll.vco); + + /* + * The clocks to the flash devices and the L4_MAIN clocks can + * glitch when coming out of safe mode if their source values + * are different from their reset value. So the trick it to + * put them back to their reset state, and change input + * after exiting safe mode but before ungating the clocks. + */ + writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, + &clock_manager_base->per_pll.src); + writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, + &clock_manager_base->main_pll.l4src); + + /* read back for the required 5 us delay. */ + readl(&clock_manager_base->main_pll.vco); + readl(&clock_manager_base->per_pll.vco); + readl(&clock_manager_base->sdr_pll.vco); + + + /* + * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN + * with numerator and denominator. + */ + writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); + writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); + writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); + + /* + * Time starts here. Must wait 7 us from + * BGPWRDN_SET(0) to VCO_ENABLE_SET(1). + */ + end = timer_get_us() + 7; + + /* main mpu */ + writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); + + /* altera group mpuclk */ + writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); + + /* main main clock */ + writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); + + /* main for dbg */ + writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); + + /* main for cfgs2fuser0clk */ + writel(cfg->cfg2fuser0clk, + &clock_manager_base->main_pll.cfgs2fuser0clk); + + /* Peri emac0 50 MHz default to RMII */ + writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); + + /* Peri emac1 50 MHz default to RMII */ + writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); + + /* Peri QSPI */ + writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); + + writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); + + /* Peri pernandsdmmcclk */ + writel(cfg->mainnandsdmmcclk, + &clock_manager_base->main_pll.mainnandsdmmcclk); + + writel(cfg->pernandsdmmcclk, + &clock_manager_base->per_pll.pernandsdmmcclk); + + /* Peri perbaseclk */ + writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); + + /* Peri s2fuser1clk */ + writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); + + /* 7 us must have elapsed before we can enable the VCO */ + while (timer_get_us() < end) + ; + + /* Enable vco */ + /* main pll vco */ + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->main_pll.vco); + + /* periferal pll */ + writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->per_pll.vco); + + /* sdram pll vco */ + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); + + /* L3 MP and L3 SP */ + writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); + + writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); + + writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); + + /* L4 MP, L4 SP, can0, and can1 */ + writel(cfg->perdiv, &clock_manager_base->per_pll.div); + + writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); + + cm_wait_for_lock(LOCKED_MASK); + + /* write the sdram clock counters before toggling outreset all */ + writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll.ddrdqsclk); + + writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, + &clock_manager_base->sdr_pll.ddr2xdqsclk); + + writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, + &clock_manager_base->sdr_pll.ddrdqclk); + + writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, + &clock_manager_base->sdr_pll.s2fuser2clk); + + /* + * after locking, but before taking out of bypass + * assert/deassert outresetall + */ + u32 mainvco = readl(&clock_manager_base->main_pll.vco); + + /* assert main outresetall */ + writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll.vco); + + u32 periphvco = readl(&clock_manager_base->per_pll.vco); + + /* assert pheriph outresetall */ + writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll.vco); + + /* assert sdram outresetall */ + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, + &clock_manager_base->sdr_pll.vco); + + /* deassert main outresetall */ + writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->main_pll.vco); + + /* deassert pheriph outresetall */ + writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, + &clock_manager_base->per_pll.vco); + + /* deassert sdram outresetall */ + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, + &clock_manager_base->sdr_pll.vco); + + /* + * now that we've toggled outreset all, all the clocks + * are aligned nicely; so we can change any phase. + */ + ret = cm_write_with_phase(cfg->ddrdqsclk, + (u32)&clock_manager_base->sdr_pll.ddrdqsclk, + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); + if (ret) + return ret; + + /* SDRAM DDR2XDQSCLK */ + ret = cm_write_with_phase(cfg->ddr2xdqsclk, + (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk, + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); + if (ret) + return ret; + + ret = cm_write_with_phase(cfg->ddrdqclk, + (u32)&clock_manager_base->sdr_pll.ddrdqclk, + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); + if (ret) + return ret; + + ret = cm_write_with_phase(cfg->s2fuser2clk, + (u32)&clock_manager_base->sdr_pll.s2fuser2clk, + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); + if (ret) + return ret; + + /* Take all three PLLs out of bypass when safe mode is cleared. */ + cm_write_bypass(0); + + /* clear safe mode */ + cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); + + /* + * now that safe mode is clear with clocks gated + * it safe to change the source mux for the flashes the the L4_MAIN + */ + writel(cfg->persrc, &clock_manager_base->per_pll.src); + writel(cfg->l4src, &clock_manager_base->main_pll.l4src); + + /* Now ungate non-hw-managed clocks */ + writel(~0, &clock_manager_base->main_pll.en); + writel(~0, &clock_manager_base->per_pll.en); + writel(~0, &clock_manager_base->sdr_pll.en); + + /* Clear the loss of lock bits (write 1 to clear) */ + writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK, + &clock_manager_base->inter); + + return 0; +} + +static unsigned int cm_get_main_vco_clk_hz(void) +{ + u32 reg, clock; + + /* get the main VCO clock */ + reg = readl(&clock_manager_base->main_pll.vco); + clock = cm_get_osc_clk_hz(1); + clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; + + return clock; +} + +static unsigned int cm_get_per_vco_clk_hz(void) +{ + u32 reg, clock = 0; + + /* identify PER PLL clock source */ + reg = readl(&clock_manager_base->per_pll.vco); + reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = cm_get_osc_clk_hz(1); + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = cm_get_osc_clk_hz(2); + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = cm_get_f2s_per_ref_clk_hz(); + + /* get the PER VCO clock */ + reg = readl(&clock_manager_base->per_pll.vco); + clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; + + return clock; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + u32 reg, clock; + + clock = cm_get_main_vco_clk_hz(); + + /* get the MPU clock */ + reg = readl(&clock_manager_base->altera.mpuclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mpuclk); + clock /= (reg + 1); + return clock; +} + +unsigned long cm_get_sdram_clk_hz(void) +{ + u32 reg, clock = 0; + + /* identify SDRAM PLL clock source */ + reg = readl(&clock_manager_base->sdr_pll.vco); + reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; + if (reg == CLKMGR_VCO_SSRC_EOSC1) + clock = cm_get_osc_clk_hz(1); + else if (reg == CLKMGR_VCO_SSRC_EOSC2) + clock = cm_get_osc_clk_hz(2); + else if (reg == CLKMGR_VCO_SSRC_F2S) + clock = cm_get_f2s_sdr_ref_clk_hz(); + + /* get the SDRAM VCO clock */ + reg = readl(&clock_manager_base->sdr_pll.vco); + clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; + clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; + + /* get the SDRAM (DDR_DQS) clock */ + reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); + reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; + clock /= (reg + 1); + + return clock; +} + +unsigned int cm_get_l4_sp_clk_hz(void) +{ + u32 reg, clock = 0; + + /* identify the source of L4 SP clock */ + reg = readl(&clock_manager_base->main_pll.l4src); + reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; + + if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { + clock = cm_get_main_vco_clk_hz(); + + /* get the clock prior L4 SP divider (main clk) */ + reg = readl(&clock_manager_base->altera.mainclk); + clock /= (reg + 1); + reg = readl(&clock_manager_base->main_pll.mainclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + } + + /* get the L4 SP clock which supplied to UART */ + reg = readl(&clock_manager_base->main_pll.maindiv); + reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; + clock = clock / (1 << reg); + + return clock; +} + +unsigned int cm_get_mmc_controller_clk_hz(void) +{ + u32 reg, clock = 0; + + /* identify the source of MMC clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; + + if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { + clock = cm_get_f2s_per_ref_clk_hz(); + } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { + clock = cm_get_main_vco_clk_hz(); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { + clock = cm_get_per_vco_clk_hz(); + + /* get the SDMMC clock */ + reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); + clock /= (reg + 1); + } + + /* further divide by 4 as we have fixed divider at wrapper */ + clock /= 4; + return clock; +} + +unsigned int cm_get_qspi_controller_clk_hz(void) +{ + u32 reg, clock = 0; + + /* identify the source of QSPI clock */ + reg = readl(&clock_manager_base->per_pll.src); + reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; + + if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { + clock = cm_get_f2s_per_ref_clk_hz(); + } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { + clock = cm_get_main_vco_clk_hz(); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->main_pll.mainqspiclk); + clock /= (reg + 1); + } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { + clock = cm_get_per_vco_clk_hz(); + + /* get the qspi clock */ + reg = readl(&clock_manager_base->per_pll.perqspiclk); + clock /= (reg + 1); + } + + return clock; +} + +unsigned int cm_get_spi_controller_clk_hz(void) +{ + u32 reg, clock = 0; + + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + + return clock; +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); + printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000); + printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000); + printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000); + printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000); + printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000); + printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); + printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); + printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); +} diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index a7056d4da7..7818aa5c2d 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Altera Corporation <www.altera.com> + * Copyright (C) 2014-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -29,17 +29,23 @@ #define SOCFPGA_MPUL2_ADDRESS 0xfffff000 #define SOCFPGA_I2C0_ADDRESS 0xffc02200 #define SOCFPGA_I2C1_ADDRESS 0xffc02300 +#define SOCFPGA_I2C2_ADDRESS 0xffc02400 +#define SOCFPGA_I2C3_ADDRESS 0xffc02500 +#define SOCFPGA_I2C4_ADDRESS 0xffc02600 #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SDR_ADDRESS 0xffcfb000 +#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000 #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS 0xffd13400 +#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 803c926220..4c6b1f832b 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -1,317 +1,22 @@ /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _CLOCK_MANAGER_H_ -#define _CLOCK_MANAGER_H_ +#ifndef _CLOCK_MANAGER_H_ +#define _CLOCK_MANAGER_H_ #ifndef __ASSEMBLER__ -/* Clock speed accessors */ -unsigned long cm_get_mpu_clk_hz(void); -unsigned long cm_get_sdram_clk_hz(void); -unsigned int cm_get_l4_sp_clk_hz(void); -unsigned int cm_get_mmc_controller_clk_hz(void); -unsigned int cm_get_qspi_controller_clk_hz(void); -unsigned int cm_get_spi_controller_clk_hz(void); -const unsigned int cm_get_osc_clk_hz(const int osc); -const unsigned int cm_get_f2s_per_ref_clk_hz(void); -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); - -/* Clock configuration accessors */ -const struct cm_config * const cm_get_default_config(void); +void cm_wait_for_lock(u32 mask); +int cm_wait_for_fsm(void); +void cm_print_clock_quick_summary(void); #endif -struct cm_config { - /* main group */ - uint32_t main_vco_base; - uint32_t mpuclk; - uint32_t mainclk; - uint32_t dbgatclk; - uint32_t mainqspiclk; - uint32_t mainnandsdmmcclk; - uint32_t cfg2fuser0clk; - uint32_t maindiv; - uint32_t dbgdiv; - uint32_t tracediv; - uint32_t l4src; - - /* peripheral group */ - uint32_t peri_vco_base; - uint32_t emac0clk; - uint32_t emac1clk; - uint32_t perqspiclk; - uint32_t pernandsdmmcclk; - uint32_t perbaseclk; - uint32_t s2fuser1clk; - uint32_t perdiv; - uint32_t gpiodiv; - uint32_t persrc; - - /* sdram pll group */ - uint32_t sdram_vco_base; - uint32_t ddrdqsclk; - uint32_t ddr2xdqsclk; - uint32_t ddrdqclk; - uint32_t s2fuser2clk; - - /* altera group */ - uint32_t altera_grp_mpuclk; -}; - -void cm_basic_init(const struct cm_config * const cfg); - -struct socfpga_clock_manager_main_pll { - u32 vco; - u32 misc; - u32 mpuclk; - u32 mainclk; - u32 dbgatclk; - u32 mainqspiclk; - u32 mainnandsdmmcclk; - u32 cfgs2fuser0clk; - u32 en; - u32 maindiv; - u32 dbgdiv; - u32 tracediv; - u32 l4src; - u32 stat; - u32 _pad_0x38_0x40[2]; -}; - -struct socfpga_clock_manager_per_pll { - u32 vco; - u32 misc; - u32 emac0clk; - u32 emac1clk; - u32 perqspiclk; - u32 pernandsdmmcclk; - u32 perbaseclk; - u32 s2fuser1clk; - u32 en; - u32 div; - u32 gpiodiv; - u32 src; - u32 stat; - u32 _pad_0x34_0x40[3]; -}; - -struct socfpga_clock_manager_sdr_pll { - u32 vco; - u32 ctrl; - u32 ddrdqsclk; - u32 ddr2xdqsclk; - u32 ddrdqclk; - u32 s2fuser2clk; - u32 en; - u32 stat; -}; - -struct socfpga_clock_manager_altera { - u32 mpuclk; - u32 mainclk; -}; - -struct socfpga_clock_manager { - u32 ctrl; - u32 bypass; - u32 inter; - u32 intren; - u32 dbctrl; - u32 stat; - u32 _pad_0x18_0x3f[10]; - struct socfpga_clock_manager_main_pll main_pll; - struct socfpga_clock_manager_per_pll per_pll; - struct socfpga_clock_manager_sdr_pll sdr_pll; - struct socfpga_clock_manager_altera altera; - u32 _pad_0xe8_0x200[70]; -}; - -#define CLKMGR_CTRL_SAFEMODE (1 << 0) -#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 - -#define CLKMGR_BYPASS_PERPLLSRC (1 << 4) -#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 -#define CLKMGR_BYPASS_PERPLL (1 << 3) -#define CLKMGR_BYPASS_PERPLL_OFFSET 3 -#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) -#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 -#define CLKMGR_BYPASS_SDRPLL (1 << 1) -#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 -#define CLKMGR_BYPASS_MAINPLL (1 << 0) -#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 - -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 -#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 -#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 - -#define CLKMGR_STAT_BUSY (1 << 0) - -/* Main PLL */ -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 -#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 -#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 -#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) -#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 -#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 -#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d - -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 -#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 - -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 - -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c - -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 - -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 -#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 - -/* Per PLL */ -#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 -#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 -#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 -#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 -#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 -#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 - -#define CLKMGR_VCO_SSRC_EOSC1 0x0 -#define CLKMGR_VCO_SSRC_EOSC2 0x1 -#define CLKMGR_VCO_SSRC_F2S 0x2 - -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 -#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 - -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 -#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 -#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 - -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff - -#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 -#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c -#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 -#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 -#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 -#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 -#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 -#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 -#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 -#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 -#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 -#define CLKMGR_QSPI_CLK_SRC_PER 0x2 - -/* SDR PLL */ -#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 -#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 -#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 -#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 -#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 - -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 - -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 - -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 - -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/clock_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/clock_manager_arria10.h> +#endif #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h new file mode 100644 index 0000000000..1b55bb8ecf --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef CLOCK_MANAGER_ARRIA10 +#define CLOCK_MANAGER_ARRIA10 + +#ifndef __ASSEMBLER__ + +struct socfpga_clock_manager_main_pll { + u32 vco0; + u32 vco1; + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 mpuclk; + u32 nocclk; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 pad_0x48_0x5b[5]; + u32 cntr15clk; + u32 outrst; + u32 outrststat; + u32 nocdiv; + u32 pad_0x6c_0x80[5]; +}; + +struct socfpga_clock_manager_per_pll { + u32 vco0; + u32 vco1; + u32 en; + u32 ens; + u32 enr; + u32 bypass; + u32 bypasss; + u32 bypassr; + u32 pad_0x20_0x27[2]; + u32 cntr2clk; + u32 cntr3clk; + u32 cntr4clk; + u32 cntr5clk; + u32 cntr6clk; + u32 cntr7clk; + u32 cntr8clk; + u32 cntr9clk; + u32 pad_0x48_0x5f[6]; + u32 outrst; + u32 outrststat; + u32 emacctl; + u32 gpiodiv; + u32 pad_0x70_0x80[4]; +}; + +struct socfpga_clock_manager_altera { + u32 mpuclk; + u32 nocclk; + u32 mainmisc0; + u32 mainmisc1; + u32 perimisc0; + u32 perimisc1; +}; + +struct socfpga_clock_manager { + /* clkmgr */ + u32 ctrl; + u32 intr; + u32 intrs; + u32 intrr; + u32 intren; + u32 intrens; + u32 intrenr; + u32 stat; + u32 testioctrl; + u32 _pad_0x24_0x40[7]; + /* mainpllgrp */ + struct socfpga_clock_manager_main_pll main_pll; + /* perpllgrp */ + struct socfpga_clock_manager_per_pll per_pll; + struct socfpga_clock_manager_altera altera; +}; + +void cm_use_intosc(void); +unsigned int cm_get_noc_clk_hz(void); +unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift); +int cm_basic_init(const void *blob); + +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_main_vco_clk_hz(void); +unsigned int cm_get_per_vco_clk_hz(void); +unsigned long cm_get_mpu_clk_hz(void); + +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); + +#endif /* __ASSEMBLER__ */ + +#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140 +#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144 +#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \ + CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK) + +/* value */ +#define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f +#define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff +#define CLKMGR_MAINPLL_VCO0_RESET 0x00010053 +#define CLKMGR_MAINPLL_VCO1_RESET 0x00010001 +#define CLKMGR_PERPLL_VCO0_RESET 0x00010053 +#define CLKMGR_PERPLL_VCO1_RESET 0x00010001 +#define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0 +#define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1 +#define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2 +#define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0 +#define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1 +#define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2 +#define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3 + +/* mask */ +#define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6) +#define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7) +#define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8) +#define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9) +#define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17) +#define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0) +#define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1) +#define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2) +#define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3) +#define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4) +#define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0) +#define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1) +#define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2) +#define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3) +#define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4) +#define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0) +#define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1) +#define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2) +#define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3) +#define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8) +#define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9) +#define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10) +#define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11) +#define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0) +#define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300 +#define CLKMGR_PERPLL_EN_RESET 0x00000f7f +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003 +#define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff +#define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f +#define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff +#define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003 +#define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff +#define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f +#define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff +#define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007 +#define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff +#define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0 +#define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1 +#define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2 +#define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3 +#define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4 +#define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003 +#define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff +#define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007 +#define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0 +#define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1 +#define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2 +#define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3 +#define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4 + +#define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007 +#define CLKMGR_PERPLLGRP_SRC_MAIN 0 +#define CLKMGR_PERPLLGRP_SRC_PERI 1 +#define CLKMGR_PERPLLGRP_SRC_OSC1 2 +#define CLKMGR_PERPLLGRP_SRC_INTOSC 3 +#define CLKMGR_PERPLLGRP_SRC_FPGA 4 + +/* bit shifting macro */ +#define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8 +#define CLKMGR_PERPLL_VCO0_PSRC_LSB 8 +#define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16 +#define CLKMGR_PERPLL_VCO1_DENOM_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0 +#define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8 +#define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16 +#define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24 +#define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26 +#define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28 +#define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26 +#define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27 +#define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28 + +/* PLL ramping work around */ +#define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000 +#define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000 +#define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000 +#define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000 + +#define CLKMGR_STAT_BUSY BIT(0) + +#endif /* CLOCK_MANAGER_ARRIA10 */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h new file mode 100644 index 0000000000..9227dfb09a --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_MANAGER_GEN5_H_ +#define _CLOCK_MANAGER_GEN5_H_ + +#ifndef __ASSEMBLER__ + +struct cm_config { + /* main group */ + u32 main_vco_base; + u32 mpuclk; + u32 mainclk; + u32 dbgatclk; + u32 mainqspiclk; + u32 mainnandsdmmcclk; + u32 cfg2fuser0clk; + u32 maindiv; + u32 dbgdiv; + u32 tracediv; + u32 l4src; + + /* peripheral group */ + u32 peri_vco_base; + u32 emac0clk; + u32 emac1clk; + u32 perqspiclk; + u32 pernandsdmmcclk; + u32 perbaseclk; + u32 s2fuser1clk; + u32 perdiv; + u32 gpiodiv; + u32 persrc; + + /* sdram pll group */ + u32 sdram_vco_base; + u32 ddrdqsclk; + u32 ddr2xdqsclk; + u32 ddrdqclk; + u32 s2fuser2clk; + + /* altera group */ + u32 altera_grp_mpuclk; +}; + +struct socfpga_clock_manager_main_pll { + u32 vco; + u32 misc; + u32 mpuclk; + u32 mainclk; + u32 dbgatclk; + u32 mainqspiclk; + u32 mainnandsdmmcclk; + u32 cfgs2fuser0clk; + u32 en; + u32 maindiv; + u32 dbgdiv; + u32 tracediv; + u32 l4src; + u32 stat; + u32 _pad_0x38_0x40[2]; +}; + +struct socfpga_clock_manager_per_pll { + u32 vco; + u32 misc; + u32 emac0clk; + u32 emac1clk; + u32 perqspiclk; + u32 pernandsdmmcclk; + u32 perbaseclk; + u32 s2fuser1clk; + u32 en; + u32 div; + u32 gpiodiv; + u32 src; + u32 stat; + u32 _pad_0x34_0x40[3]; +}; + +struct socfpga_clock_manager_sdr_pll { + u32 vco; + u32 ctrl; + u32 ddrdqsclk; + u32 ddr2xdqsclk; + u32 ddrdqclk; + u32 s2fuser2clk; + u32 en; + u32 stat; +}; + +struct socfpga_clock_manager_altera { + u32 mpuclk; + u32 mainclk; +}; + +struct socfpga_clock_manager { + u32 ctrl; + u32 bypass; + u32 inter; + u32 intren; + u32 dbctrl; + u32 stat; + u32 _pad_0x18_0x3f[10]; + struct socfpga_clock_manager_main_pll main_pll; + struct socfpga_clock_manager_per_pll per_pll; + struct socfpga_clock_manager_sdr_pll sdr_pll; + struct socfpga_clock_manager_altera altera; + u32 _pad_0xe8_0x200[70]; +}; + +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +const unsigned int cm_get_osc_clk_hz(const int osc); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); + +/* Clock configuration accessors */ +int cm_basic_init(const struct cm_config * const cfg); +const struct cm_config * const cm_get_default_config(void); +#endif /* __ASSEMBLER__ */ + +#define LOCKED_MASK \ + (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ + CLKMGR_INTER_PERPLLLOCKED_MASK | \ + CLKMGR_INTER_MAINPLLLOCKED_MASK) + +#define CLKMGR_CTRL_SAFEMODE BIT(0) +#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 + +#define CLKMGR_BYPASS_PERPLLSRC BIT(4) +#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 +#define CLKMGR_BYPASS_PERPLL BIT(3) +#define CLKMGR_BYPASS_PERPLL_OFFSET 3 +#define CLKMGR_BYPASS_SDRPLLSRC BIT(2) +#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 +#define CLKMGR_BYPASS_SDRPLL BIT(1) +#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 +#define CLKMGR_BYPASS_MAINPLL BIT(0) +#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 + +#define CLKMGR_INTER_MAINPLLLOST_MASK BIT(3) +#define CLKMGR_INTER_PERPLLLOST_MASK BIT(4) +#define CLKMGR_INTER_SDRPLLLOST_MASK BIT(5) +#define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(6) +#define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(7) +#define CLKMGR_INTER_SDRPLLLOCKED_MASK BIT(8) + +#define CLKMGR_STAT_BUSY BIT(0) + +/* Main PLL */ +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_MAINPLLGRP_VCO_EN BIT(1) +#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK BIT(4) +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK BIT(5) +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK BIT(6) +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK BIT(7) +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(9) + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 + +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 + +/* Per PLL */ +#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_VCO_SSRC_EOSC1 0x0 +#define CLKMGR_VCO_SSRC_EOSC2 0x1 +#define CLKMGR_VCO_SSRC_F2S 0x2 + +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 + +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 + +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff + +#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 +#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c +#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 +#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2 + +/* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK BIT(31) +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 + +#endif /* _CLOCK_MANAGER_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h new file mode 100644 index 0000000000..0b65783b05 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MISC_H_ +#define _MISC_H_ + +void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode); + +struct bsel { + const char *mode; + const char *name; +}; + +extern struct bsel bsel_str[]; + +#ifdef CONFIG_FPGA +void socfpga_fpga_add(void); +#else +static inline void socfpga_fpga_add(void) {} +#endif + +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +unsigned int dedicated_uart_com_port(const void *blob); +unsigned int shared_uart_com_port(const void *blob); +unsigned int uart_com_port(const void *blob); +#endif + +#endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h b/arch/arm/mach-socfpga/include/mach/pinmux.h new file mode 100644 index 0000000000..563a3db110 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/pinmux.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _PINMUX_H_ +#define _PINMUX_H_ + +#define PINMUX_UART 0xD + +#ifndef __ASSEMBLY__ +int config_dedicated_pins(const void *blob); +int config_pins(const void *blob, const char *pin_grp); +#endif + +#endif /* _PINMUX_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f291c..65917454f8 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -1,34 +1,17 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _RESET_MANAGER_H_ -#define _RESET_MANAGER_H_ +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ void reset_cpu(ulong addr); -void reset_deassert_peripherals_handoff(void); - -void socfpga_bridges_reset(int enable); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); -struct socfpga_reset_manager { - u32 status; - u32 ctrl; - u32 counts; - u32 padding1; - u32 mpu_mod_reset; - u32 per_mod_reset; - u32 per2_mod_reset; - u32 brg_mod_reset; - u32 misc_mod_reset; - u32 padding2[12]; - u32 tstscratch; -}; - #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 #else @@ -55,28 +38,13 @@ struct socfpga_reset_manager { #define RSTMGR_BANK(_reset) \ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) -/* - * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: - * 0 ... mpumodrst - * 1 ... permodrst - * 2 ... per2modrst - * 3 ... brgmodrst - * 4 ... miscmodrst - */ -#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) -#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) -#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) -#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) -#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) -#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) -#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) -#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) -#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) -#define RSTMGR_DMA RSTMGR_DEFINE(1, 28) -#define RSTMGR_SDR RSTMGR_DEFINE(1, 29) - /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/reset_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/reset_manager_arria10.h> +#endif + #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h new file mode 100644 index 0000000000..7922db815c --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _RESET_MANAGER_ARRIA10_H_ +#define _RESET_MANAGER_ARRIA10_H_ + +#include <dt-bindings/reset/altr,rst-mgr-a10.h> + +void socfpga_watchdog_disable(void); +void socfpga_reset_deassert_noc_ddr_scheduler(void); +int socfpga_is_wdt_in_reset(void); +void socfpga_emac_manage_reset(ulong emacbase, u32 state); +int socfpga_reset_deassert_bridges_handoff(void); +void socfpga_reset_assert_fpga_connected_peripherals(void); +void socfpga_reset_deassert_osc1wd0(void); +void socfpga_reset_uart(int assert); +int socfpga_bridges_reset(int enable); + +struct socfpga_reset_manager { + u32 stat; + u32 ramstat; + u32 miscstat; + u32 ctrl; + u32 hdsken; + u32 hdskreq; + u32 hdskack; + u32 counts; + u32 mpumodrst; + u32 per0modrst; + u32 per1modrst; + u32 brgmodrst; + u32 sysmodrst; + u32 coldmodrst; + u32 nrstmodrst; + u32 dbgmodrst; + u32 mpuwarmmask; + u32 per0warmmask; + u32 per1warmmask; + u32 brgwarmmask; + u32 syswarmmask; + u32 nrstwarmmask; + u32 l3warmmask; + u32 tststa; + u32 tstscratch; + u32 hdsktimeout; + u32 hmcintr; + u32 hmcintren; + u32 hmcintrens; + u32 hmcintrenr; + u32 hmcgpout; + u32 hmcgpin; +}; + +/* + * SocFPGA Arria10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + * 4 ... sysmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 5) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) +#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2) +#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3) +#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) +#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6) + +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1) +#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0) +#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1) +#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2) +#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3) +#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4) +#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5) +#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6) +#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7) +#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8) +#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9) +#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10) +#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11) +#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12) +#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13) +#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14) +#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15) +#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16) +#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17) +#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18) +#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19) +#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20) +#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21) +#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22) +#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24) +#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25) +#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26) +#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27) +#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28) +#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29) +#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30) +#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31) + +#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0) +#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1) +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2) +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3) +#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4) +#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5) +#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8) +#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9) +#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10) +#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11) +#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12) +#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16) +#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17) +#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24) +#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25) +#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26) + +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0) +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1) +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2) +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3) +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4) +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5) +#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6) + +#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0) +#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1) +#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2) +#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3) + +#endif /* _RESET_MANAGER_ARRIA10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h new file mode 100644 index 0000000000..6d9cffea7b --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RESET_MANAGER_GEN5_H_ +#define _RESET_MANAGER_GEN5_H_ + +#include <dt-bindings/reset/altr,rst-mgr.h> + +void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_reset(int enable); + +struct socfpga_reset_manager { + u32 status; + u32 ctrl; + u32 counts; + u32 padding1; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; + u32 misc_mod_reset; + u32 padding2[12]; + u32 tstscratch; +}; + +/* + * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... permodrst + * 2 ... per2modrst + * 3 ... brgmodrst + * 4 ... miscmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_NAND RSTMGR_DEFINE(1, 4) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8) +#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 28) +#define RSTMGR_SDR RSTMGR_DEFINE(1, 29) + +#endif /* _RESET_MANAGER_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h new file mode 100644 index 0000000000..1d7b7c119a --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2015-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SOCFPGA_SDRAM_ARRIA10_H_ +#define _SOCFPGA_SDRAM_ARRIA10_H_ + +#ifndef __ASSEMBLY__ + +struct socfpga_ecc_hmc { + u32 ip_rev_id; + u32 _pad_0x4_0x7; + u32 ddrioctrl; + u32 ddrcalstat; + u32 mpr_0beat1; + u32 mpr_1beat1; + u32 mpr_2beat1; + u32 mpr_3beat1; + u32 mpr_4beat1; + u32 mpr_5beat1; + u32 mpr_6beat1; + u32 mpr_7beat1; + u32 mpr_8beat1; + u32 mpr_0beat2; + u32 mpr_1beat2; + u32 mpr_2beat2; + u32 mpr_3beat2; + u32 mpr_4beat2; + u32 mpr_5beat2; + u32 mpr_6beat2; + u32 mpr_7beat2; + u32 mpr_8beat2; + u32 _pad_0x58_0x5f[2]; + u32 auto_precharge; + u32 _pad_0x64_0xff[39]; + u32 eccctrl; + u32 eccctrl2; + u32 _pad_0x108_0x10f[2]; + u32 errinten; + u32 errintens; + u32 errintenr; + u32 intmode; + u32 intstat; + u32 diaginttest; + u32 modstat; + u32 derraddra; + u32 serraddra; + u32 _pad_0x134_0x137; + u32 autowb_corraddr; + u32 serrcntreg; + u32 autowb_drop_cntreg; + u32 _pad_0x144_0x147; + u32 ecc_reg2wreccdatabus; + u32 ecc_rdeccdata2regbus; + u32 ecc_reg2rdeccdatabus; + u32 _pad_0x154_0x15f[3]; + u32 ecc_diagon; + u32 ecc_decstat; + u32 _pad_0x168_0x16f[2]; + u32 ecc_errgenaddr_0; + u32 ecc_errgenaddr_1; + u32 ecc_errgenaddr_2; + u32 ecc_errgenaddr_3; +}; + +struct socfpga_noc_ddr_scheduler { + u32 ddr_t_main_scheduler_id_coreid; + u32 ddr_t_main_scheduler_id_revisionid; + u32 ddr_t_main_scheduler_ddrconf; + u32 ddr_t_main_scheduler_ddrtiming; + u32 ddr_t_main_scheduler_ddrmode; + u32 ddr_t_main_scheduler_readlatency; + u32 _pad_0x20_0x34[8]; + u32 ddr_t_main_scheduler_activate; + u32 ddr_t_main_scheduler_devtodev; +}; + +/* + * OCRAM firewall + */ +struct socfpga_noc_fw_ocram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 region0; + u32 region1; + u32 region2; + u32 region3; + u32 region4; + u32 region5; +}; + +/* for master such as MPU and FPGA */ +struct socfpga_noc_fw_ddr_mpu_fpga2sdram { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 _pad_0xc_0xf; + u32 mpuregion0addr; + u32 mpuregion1addr; + u32 mpuregion2addr; + u32 mpuregion3addr; + u32 fpga2sdram0region0addr; + u32 fpga2sdram0region1addr; + u32 fpga2sdram0region2addr; + u32 fpga2sdram0region3addr; + u32 fpga2sdram1region0addr; + u32 fpga2sdram1region1addr; + u32 fpga2sdram1region2addr; + u32 fpga2sdram1region3addr; + u32 fpga2sdram2region0addr; + u32 fpga2sdram2region1addr; + u32 fpga2sdram2region2addr; + u32 fpga2sdram2region3addr; +}; + +/* for L3 master */ +struct socfpga_noc_fw_ddr_l3 { + u32 enable; + u32 enable_set; + u32 enable_clear; + u32 hpsregion0addr; + u32 hpsregion1addr; + u32 hpsregion2addr; + u32 hpsregion3addr; + u32 hpsregion4addr; + u32 hpsregion5addr; + u32 hpsregion6addr; + u32 hpsregion7addr; +}; + +struct socfpga_io48_mmr { + u32 dbgcfg0; + u32 dbgcfg1; + u32 dbgcfg2; + u32 dbgcfg3; + u32 dbgcfg4; + u32 dbgcfg5; + u32 dbgcfg6; + u32 reserve0; + u32 reserve1; + u32 reserve2; + u32 ctrlcfg0; + u32 ctrlcfg1; + u32 ctrlcfg2; + u32 ctrlcfg3; + u32 ctrlcfg4; + u32 ctrlcfg5; + u32 ctrlcfg6; + u32 ctrlcfg7; + u32 ctrlcfg8; + u32 ctrlcfg9; + u32 dramtiming0; + u32 dramodt0; + u32 dramodt1; + u32 sbcfg0; + u32 sbcfg1; + u32 sbcfg2; + u32 sbcfg3; + u32 sbcfg4; + u32 sbcfg5; + u32 sbcfg6; + u32 sbcfg7; + u32 caltiming0; + u32 caltiming1; + u32 caltiming2; + u32 caltiming3; + u32 caltiming4; + u32 caltiming5; + u32 caltiming6; + u32 caltiming7; + u32 caltiming8; + u32 caltiming9; + u32 caltiming10; + u32 dramaddrw; + u32 sideband0; + u32 sideband1; + u32 sideband2; + u32 sideband3; + u32 sideband4; + u32 sideband5; + u32 sideband6; + u32 sideband7; + u32 sideband8; + u32 sideband9; + u32 sideband10; + u32 sideband11; + u32 sideband12; + u32 sideband13; + u32 sideband14; + u32 sideband15; + u32 dramsts; + u32 dbgdone; + u32 dbgsignals; + u32 dbgreset; + u32 dbgmatch; + u32 counter0mask; + u32 counter1mask; + u32 counter0match; + u32 counter1match; + u32 niosreserve0; + u32 niosreserve1; + u32 niosreserve2; +}; +#endif /*__ASSEMBLY__*/ + +#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000 +#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT 24 +#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000 +#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT 19 +#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000 +#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT 14 +#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00 +#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT 9 +#define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180 +#define IO48_MMR_CTRLCFG0_AC_POS_SHIFT 7 +#define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070 +#define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT 4 +#define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F +#define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0 + +#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM BIT(30) +#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM BIT(29) +#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM BIT(28) +#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM BIT(27) +#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM BIT(26) +#define IO48_MMR_CTRLCFG1_DQSTRK_EN BIT(25) +#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000 +#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT 19 +#define IO48_MMR_CTRLCFG1_REORDER_READ BIT(18) +#define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA BIT(17) +#define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA BIT(16) +#define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA BIT(15) +#define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA BIT(14) +#define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA BIT(13) +#define IO48_MMR_CTRLCFG1_REORDER_DATA BIT(12) +#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC BIT(11) +#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC BIT(10) +#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC BIT(9) +#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC BIT(8) +#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC BIT(7) +#define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060 +#define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT 5 +#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK 0x0000001F +#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT 0 + +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK 0x3F000000 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT 24 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK 0x00FC0000 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT 18 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK 0x0003F000 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT 12 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK 0x00000FC0 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT 6 +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK 0x0000003F +#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT 0 + +#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK 0x3F000000 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT 24 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK 0x00FC0000 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT 18 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK 0x0003F000 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT 12 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK 0x00000FC0 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT 6 +#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK 0x0000003F +#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT 0 + +#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK 0x3F000000 +#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT 24 +#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK 0x00FC0000 +#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT 18 +#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK 0x0003F000 +#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT 12 +#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK 0x00000FC0 +#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT 6 +#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK 0x0000003F +#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT 0 + +#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK 0x3F000000 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT 24 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK 0x00FC0000 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT 18 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK 0x0003F000 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT 12 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK 0x00000FC0 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT 6 +#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK 0x0000003F +#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT 0 + +#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK 0xFC000000 +#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT 26 +#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK 0x03FC0000 +#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT 18 +#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK 0x0003F000 +#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT 12 +#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK 0x00000FC0 +#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT 6 +#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK 0x0000003F +#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT 0 + +#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK 0x000000FF +#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT 0 + +#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK 0x00070000 +#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT 16 +#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK 0x0000C000 +#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT 14 +#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK 0x00003C00 +#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT 10 +#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK 0x000003E0 +#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT 5 +#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK 0x0000001F +#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT 0 + +#define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK 0x00000003 + +#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK BIT(0) +#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK BIT(1) +#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK BIT(0) +#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK BIT(1) +#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK BIT(16) +#define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) +#define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK BIT(8) +#define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK BIT(0) +#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK BIT(8) +#define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK BIT(0) + +#define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE 8 + +#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0 +#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6 +#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12 +#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18 +#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21 +#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26 +#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31 + +#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0 +#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1 + +#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0 +#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4 +#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10 + +#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0 +#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2 +#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4 + +#define ALT_NOC_FW_DDR_END_ADDR_LSB 16 +#define ALT_NOC_FW_DDR_ADDR_MASK 0xFFFF +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK BIT(0) +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK BIT(1) +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK BIT(2) +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK BIT(3) +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK BIT(4) +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK BIT(5) +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK BIT(6) +#define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK BIT(7) +#define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK BIT(0) +#define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK BIT(1) +#define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK BIT(2) +#define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK BIT(3) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK BIT(4) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK BIT(5) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK BIT(6) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK BIT(7) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK BIT(8) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK BIT(9) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK BIT(10) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK BIT(11) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK BIT(12) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK BIT(13) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK BIT(14) +#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK BIT(15) + +#define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK 0x0000003F +#endif /* _SOCFPGA_SDRAM_ARRIA10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index c45edea32d..e6d4280c5b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -1,139 +1,24 @@ /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SYSTEM_MANAGER_H_ -#define _SYSTEM_MANAGER_H_ +#ifndef _SYSTEM_MANAGER_H_ +#define _SYSTEM_MANAGER_H_ -#ifndef __ASSEMBLY__ - -void sysmgr_pinmux_init(void); -void sysmgr_config_warmrstcfgio(int enable); - -void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); -#endif - -struct socfpga_system_manager { - /* System Manager Module */ - u32 siliconid1; /* 0x00 */ - u32 siliconid2; - u32 _pad_0x8_0xf[2]; - u32 wddbg; /* 0x10 */ - u32 bootinfo; - u32 hpsinfo; - u32 parityinj; - /* FPGA Interface Group */ - u32 fpgaintfgrp_gbl; /* 0x20 */ - u32 fpgaintfgrp_indiv; - u32 fpgaintfgrp_module; - u32 _pad_0x2c_0x2f; - /* Scan Manager Group */ - u32 scanmgrgrp_ctrl; /* 0x30 */ - u32 _pad_0x34_0x3f[3]; - /* Freeze Control Group */ - u32 frzctrl_vioctrl; /* 0x40 */ - u32 _pad_0x44_0x4f[3]; - u32 frzctrl_hioctrl; /* 0x50 */ - u32 frzctrl_src; - u32 frzctrl_hwctrl; - u32 _pad_0x5c_0x5f; - /* EMAC Group */ - u32 emacgrp_ctrl; /* 0x60 */ - u32 emacgrp_l3master; - u32 _pad_0x68_0x6f[2]; - /* DMA Controller Group */ - u32 dmagrp_ctrl; /* 0x70 */ - u32 dmagrp_persecurity; - u32 _pad_0x78_0x7f[2]; - /* Preloader (initial software) Group */ - u32 iswgrp_handoff[8]; /* 0x80 */ - u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ - /* Boot ROM Code Register Group */ - u32 romcodegrp_ctrl; /* 0xc0 */ - u32 romcodegrp_cpu1startaddr; - u32 romcodegrp_initswstate; - u32 romcodegrp_initswlastld; - u32 romcodegrp_bootromswstate; /* 0xd0 */ - u32 __pad_0xd4_0xdf[3]; - /* Warm Boot from On-Chip RAM Group */ - u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ - u32 romcodegrp_warmramgrp_datastart; - u32 romcodegrp_warmramgrp_length; - u32 romcodegrp_warmramgrp_execution; - u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ - u32 __pad_0xf4_0xff[3]; - /* Boot ROM Hardware Register Group */ - u32 romhwgrp_ctrl; /* 0x100 */ - u32 _pad_0x104_0x107; - /* SDMMC Controller Group */ - u32 sdmmcgrp_ctrl; - u32 sdmmcgrp_l3master; - /* NAND Flash Controller Register Group */ - u32 nandgrp_bootstrap; /* 0x110 */ - u32 nandgrp_l3master; - /* USB Controller Group */ - u32 usbgrp_l3master; - u32 _pad_0x11c_0x13f[9]; - /* ECC Management Register Group */ - u32 eccgrp_l2; /* 0x140 */ - u32 eccgrp_ocram; - u32 eccgrp_usb0; - u32 eccgrp_usb1; - u32 eccgrp_emac0; /* 0x150 */ - u32 eccgrp_emac1; - u32 eccgrp_dma; - u32 eccgrp_can0; - u32 eccgrp_can1; /* 0x160 */ - u32 eccgrp_nand; - u32 eccgrp_qspi; - u32 eccgrp_sdmmc; - u32 _pad_0x170_0x3ff[164]; - /* Pin Mux Control Group */ - u32 emacio[20]; /* 0x400 */ - u32 flashio[12]; /* 0x450 */ - u32 generalio[28]; /* 0x480 */ - u32 _pad_0x4f0_0x4ff[4]; - u32 mixed1io[22]; /* 0x500 */ - u32 mixed2io[8]; /* 0x558 */ - u32 gplinmux[23]; /* 0x578 */ - u32 gplmux[71]; /* 0x5d4 */ - u32 nandusefpga; /* 0x6f0 */ - u32 _pad_0x6f4; - u32 rgmii1usefpga; /* 0x6f8 */ - u32 _pad_0x6fc_0x700[2]; - u32 i2c0usefpga; /* 0x704 */ - u32 sdmmcusefpga; /* 0x708 */ - u32 _pad_0x70c_0x710[2]; - u32 rgmii0usefpga; /* 0x714 */ - u32 _pad_0x718_0x720[3]; - u32 i2c3usefpga; /* 0x724 */ - u32 i2c2usefpga; /* 0x728 */ - u32 i2c1usefpga; /* 0x72c */ - u32 spim1usefpga; /* 0x730 */ - u32 _pad_0x734; - u32 spim0usefpga; /* 0x738 */ -}; - -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) -#define SYSMGR_ECC_OCRAM_EN (1 << 0) -#define SYSMGR_ECC_OCRAM_SERR (1 << 3) -#define SYSMGR_ECC_OCRAM_DERR (1 << 4) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define SYSMGR_ECC_OCRAM_EN BIT(0) +#define SYSMGR_ECC_OCRAM_SERR BIT(3) +#define SYSMGR_ECC_OCRAM_DERR BIT(4) #define SYSMGR_FPGAINTF_USEFPGA 0x1 -#define SYSMGR_FPGAINTF_SPIM0 (1 << 0) -#define SYSMGR_FPGAINTF_SPIM1 (1 << 1) -#define SYSMGR_FPGAINTF_EMAC0 (1 << 2) -#define SYSMGR_FPGAINTF_EMAC1 (1 << 3) -#define SYSMGR_FPGAINTF_NAND (1 << 4) -#define SYSMGR_FPGAINTF_SDMMC (1 << 5) - -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 -#else -#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 -#endif +#define SYSMGR_FPGAINTF_SPIM0 BIT(0) +#define SYSMGR_FPGAINTF_SPIM1 BIT(1) +#define SYSMGR_FPGAINTF_EMAC0 BIT(2) +#define SYSMGR_FPGAINTF_EMAC1 BIT(3) +#define SYSMGR_FPGAINTF_NAND BIT(4) +#define SYSMGR_FPGAINTF_SDMMC BIT(5) #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 @@ -146,4 +31,63 @@ struct socfpga_system_manager { #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 +/* For dedicated IO configuration */ +/* Voltage select enums */ +#define VOLTAGE_SEL_3V 0x0 +#define VOLTAGE_SEL_1P8V 0x1 +#define VOLTAGE_SEL_2P5V 0x2 + +/* Input buffer enable */ +#define INPUT_BUF_DISABLE 0 +#define INPUT_BUF_1P8V 1 +#define INPUT_BUF_2P5V3V 2 + +/* Weak pull up enable */ +#define WK_PU_DISABLE 0 +#define WK_PU_ENABLE 1 + +/* Pull up slew rate control */ +#define PU_SLW_RT_SLOW 0 +#define PU_SLW_RT_FAST 1 +#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW + +/* Pull down slew rate control */ +#define PD_SLW_RT_SLOW 0 +#define PD_SLW_RT_FAST 1 +#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW + +/* Drive strength control */ +#define PU_DRV_STRG_DEFAULT 0x10 +#define PD_DRV_STRG_DEFAULT 0x10 + +/* bit position */ +#define PD_DRV_STRG_LSB 0 +#define PD_SLW_RT_LSB 5 +#define PU_DRV_STRG_LSB 8 +#define PU_SLW_RT_LSB 13 +#define WK_PU_LSB 16 +#define INPUT_BUF_LSB 17 +#define BIAS_TRIM_LSB 19 +#define VOLTAGE_SEL_LSB 0 + +#define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0) +#define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4) +#define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8) +#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16) +#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20) +#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24) +#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0) + +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1) +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1) + +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/system_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/system_manager_arria10.h> +#endif + +#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \ + (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7) + #endif /* _SYSTEM_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h new file mode 100644 index 0000000000..f235abab0b --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SYSTEM_MANAGER_ARRIA10_H_ +#define _SYSTEM_MANAGER_ARRIA10_H_ + +struct socfpga_system_manager { + u32 siliconid1; + u32 siliconid2; + u32 wddbg; + u32 bootinfo; + u32 mpu_ctrl_l2_ecc; + u32 _pad_0x14_0x1f[3]; + u32 dma; + u32 dma_periph; + u32 sdmmcgrp_ctrl; + u32 sdmmc_l3master; + u32 nand_bootstrap; + u32 nand_l3master; + u32 usb0_l3master; + u32 usb1_l3master; + u32 emac_global; + u32 emac[3]; + u32 _pad_0x50_0x5f[4]; + u32 fpgaintf_en_global; + u32 fpgaintf_en_0; + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; + u32 _pad_0x74_0x7f[3]; + u32 noc_addr_remap_value; + u32 noc_addr_remap_set; + u32 noc_addr_remap_clear; + u32 _pad_0x8c_0x8f; + u32 ecc_intmask_value; + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; + u32 mpu_status_l2_ecc; + u32 mpu_clear_l2_ecc; + u32 mpu_status_l1_parity; + u32 mpu_clear_l1_parity; + u32 mpu_set_l1_parity; + u32 _pad_0xb8_0xbf[2]; + u32 noc_timeout; + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 _pad_0xdc_0xff[9]; + u32 tsmc_tsel_0; + u32 tsmc_tsel_1; + u32 tsmc_tsel_2; + u32 tsmc_tsel_3; + u32 _pad_0x110_0x200[60]; + u32 romhw_ctrl; + u32 romcode_ctrl; + u32 romcode_cpu1startaddr; + u32 romcode_initswstate; + u32 romcode_initswlastld; + u32 _pad_0x214_0x217; + u32 warmram_enable; + u32 warmram_datastart; + u32 warmram_length; + u32 warmram_execution; + u32 warmram_crc; + u32 _pad_0x22c_0x22f; + u32 isw_handoff[8]; + u32 romcode_bootromswstate[8]; +}; + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 12 + +#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h new file mode 100644 index 0000000000..285c1a29ad --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYSTEM_MANAGER_GEN5_H_ +#define _SYSTEM_MANAGER_GEN5_H_ + +#ifndef __ASSEMBLY__ + +void sysmgr_pinmux_init(void); +void sysmgr_config_warmrstcfgio(int enable); + +void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); + +struct socfpga_system_manager { + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ + u32 siliconid2; + u32 _pad_0x8_0xf[2]; + u32 wddbg; /* 0x10 */ + u32 bootinfo; + u32 hpsinfo; + u32 parityinj; + /* FPGA Interface Group */ + u32 fpgaintfgrp_gbl; /* 0x20 */ + u32 fpgaintfgrp_indiv; + u32 fpgaintfgrp_module; + u32 _pad_0x2c_0x2f; + /* Scan Manager Group */ + u32 scanmgrgrp_ctrl; /* 0x30 */ + u32 _pad_0x34_0x3f[3]; + /* Freeze Control Group */ + u32 frzctrl_vioctrl; /* 0x40 */ + u32 _pad_0x44_0x4f[3]; + u32 frzctrl_hioctrl; /* 0x50 */ + u32 frzctrl_src; + u32 frzctrl_hwctrl; + u32 _pad_0x5c_0x5f; + /* EMAC Group */ + u32 emacgrp_ctrl; /* 0x60 */ + u32 emacgrp_l3master; + u32 _pad_0x68_0x6f[2]; + /* DMA Controller Group */ + u32 dmagrp_ctrl; /* 0x70 */ + u32 dmagrp_persecurity; + u32 _pad_0x78_0x7f[2]; + /* Preloader (initial software) Group */ + u32 iswgrp_handoff[8]; /* 0x80 */ + u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ + /* Boot ROM Code Register Group */ + u32 romcodegrp_ctrl; /* 0xc0 */ + u32 romcodegrp_cpu1startaddr; + u32 romcodegrp_initswstate; + u32 romcodegrp_initswlastld; + u32 romcodegrp_bootromswstate; /* 0xd0 */ + u32 __pad_0xd4_0xdf[3]; + /* Warm Boot from On-Chip RAM Group */ + u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ + u32 romcodegrp_warmramgrp_datastart; + u32 romcodegrp_warmramgrp_length; + u32 romcodegrp_warmramgrp_execution; + u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ + u32 __pad_0xf4_0xff[3]; + /* Boot ROM Hardware Register Group */ + u32 romhwgrp_ctrl; /* 0x100 */ + u32 _pad_0x104_0x107; + /* SDMMC Controller Group */ + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x110 */ + u32 nandgrp_l3master; + /* USB Controller Group */ + u32 usbgrp_l3master; + u32 _pad_0x11c_0x13f[9]; + /* ECC Management Register Group */ + u32 eccgrp_l2; /* 0x140 */ + u32 eccgrp_ocram; + u32 eccgrp_usb0; + u32 eccgrp_usb1; + u32 eccgrp_emac0; /* 0x150 */ + u32 eccgrp_emac1; + u32 eccgrp_dma; + u32 eccgrp_can0; + u32 eccgrp_can1; /* 0x160 */ + u32 eccgrp_nand; + u32 eccgrp_qspi; + u32 eccgrp_sdmmc; + u32 _pad_0x170_0x3ff[164]; + /* Pin Mux Control Group */ + u32 emacio[20]; /* 0x400 */ + u32 flashio[12]; /* 0x450 */ + u32 generalio[28]; /* 0x480 */ + u32 _pad_0x4f0_0x4ff[4]; + u32 mixed1io[22]; /* 0x500 */ + u32 mixed2io[8]; /* 0x558 */ + u32 gplinmux[23]; /* 0x578 */ + u32 gplmux[71]; /* 0x5d4 */ + u32 nandusefpga; /* 0x6f0 */ + u32 _pad_0x6f4; + u32 rgmii1usefpga; /* 0x6f8 */ + u32 _pad_0x6fc_0x700[2]; + u32 i2c0usefpga; /* 0x704 */ + u32 sdmmcusefpga; /* 0x708 */ + u32 _pad_0x70c_0x710[2]; + u32 rgmii0usefpga; /* 0x714 */ + u32 _pad_0x718_0x720[3]; + u32 i2c3usefpga; /* 0x724 */ + u32 i2c2usefpga; /* 0x728 */ + u32 i2c1usefpga; /* 0x72c */ + u32 spim1usefpga; /* 0x730 */ + u32 _pad_0x734; + u32 spim0usefpga; /* 0x738 */ +}; +#endif + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3 +#define SYSMGR_BOOTINFO_BSEL_SHIFT 0 + +#endif /* _SYSTEM_MANAGER_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dd6b53b24d..00eff90275 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,6 +13,7 @@ #include <miiphy.h> #include <netdev.h> #include <watchdog.h> +#include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/scan_manager.h> #include <asm/arch/system_manager.h> @@ -20,20 +21,21 @@ #include <asm/arch/scu.h> #include <asm/pl310.h> -#include <dt-bindings/reset/altr,rst-mgr.h> - DECLARE_GLOBAL_DATA_PTR; -static struct pl310_regs *const pl310 = +static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; -static struct socfpga_reset_manager *reset_manager_base = - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; -static struct nic301_registers *nic301_regs = - (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct scu_registers *scu_regs = - (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; + +struct bsel bsel_str[] = { + { "rsvd", "Reserved", }, + { "fpga", "FPGA (HPS2FPGA Bridge)", }, + { "nand", "NAND Flash (1.8V)", }, + { "nand", "NAND Flash (3.0V)", }, + { "sd", "SD/MMC External Transceiver (1.8V)", }, + { "sd", "SD/MMC Internal Transceiver (3.0V)", }, + { "qspi", "QSPI Flash (1.8V)", }, + { "qspi", "QSPI Flash (3.0V)", }, +}; int dram_init(void) { @@ -72,207 +74,6 @@ void v7_outer_cache_disable(void) clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } -/* - * DesignWare Ethernet initialization - */ -#ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned int of_reset_id, - const u32 phymode) -{ - u32 physhift, reset; - - if (of_reset_id == EMAC0_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; - reset = SOCFPGA_RESET(EMAC0); - } else if (of_reset_id == EMAC1_RESET) { - physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; - reset = SOCFPGA_RESET(EMAC1); - } else { - printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); - return; - } - - /* Clearing emac0 PHY interface select to 0 */ - clrbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); - - /* configure to PHY interface select choosed */ - setbits_le32(&sysmgr_regs->emacgrp_ctrl, - phymode << physhift); - - /* Release the EMAC controller from reset */ - socfpga_per_reset(reset, 0); -} - -static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) -{ - if (!phymode) - return -EINVAL; - - if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; - return 0; - } - - if (!strcmp(phymode, "rgmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; - return 0; - } - - if (!strcmp(phymode, "rmii")) { - *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; - return 0; - } - - return -EINVAL; -} - -static int socfpga_eth_reset(void) -{ - const void *fdt = gd->fdt_blob; - struct fdtdec_phandle_args args; - const char *phy_mode; - u32 phy_modereg; - int nodes[2]; /* Max. two GMACs */ - int ret, count; - int i, node; - - /* Put both GMACs into RESET state. */ - socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); - socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); - - count = fdtdec_find_aliases_for_id(fdt, "ethernet", - COMPAT_ALTERA_SOCFPGA_DWMAC, - nodes, ARRAY_SIZE(nodes)); - for (i = 0; i < count; i++) { - node = nodes[i]; - if (node <= 0) - continue; - - ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", - "#reset-cells", 1, 0, - &args); - if (ret || (args.args_count != 1)) { - debug("GMAC%i: Failed to parse DT 'resets'!\n", i); - continue; - } - - phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); - ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); - if (ret) { - debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); - continue; - } - - dwmac_deassert_reset(args.args[0], phy_modereg); - } - - return 0; -} -#else -static int socfpga_eth_reset(void) -{ - return 0; -}; -#endif - -struct { - const char *mode; - const char *name; -} bsel_str[] = { - { "rsvd", "Reserved", }, - { "fpga", "FPGA (HPS2FPGA Bridge)", }, - { "nand", "NAND Flash (1.8V)", }, - { "nand", "NAND Flash (3.0V)", }, - { "sd", "SD/MMC External Transceiver (1.8V)", }, - { "sd", "SD/MMC Internal Transceiver (3.0V)", }, - { "qspi", "QSPI Flash (1.8V)", }, - { "qspi", "QSPI Flash (3.0V)", }, -}; - -static const struct { - const u16 pn; - const char *name; - const char *var; -} const socfpga_fpga_model[] = { - /* Cyclone V E */ - { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, - { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, - { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, - { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, - { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, - /* Cyclone V GX/GT */ - { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, - { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, - { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, - { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, - { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, - /* Cyclone V SE/SX/ST */ - { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, - { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, - { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, - { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, - /* Arria V */ - { 0x2d03, "Arria V, D5", "av_d5" }, -}; - -static int socfpga_fpga_id(const bool print_id) -{ - const u32 altera_mi = 0x6e; - const u32 id = scan_mgr_get_fpga_id(); - - const u32 lsb = id & 0x00000001; - const u32 mi = (id >> 1) & 0x000007ff; - const u32 pn = (id >> 12) & 0x0000ffff; - const u32 version = (id >> 28) & 0x0000000f; - int i; - - if ((mi != altera_mi) || (lsb != 1)) { - printf("FPGA: Not Altera chip ID\n"); - return -EINVAL; - } - - for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) - if (pn == socfpga_fpga_model[i].pn) - break; - - if (i == ARRAY_SIZE(socfpga_fpga_model)) { - printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); - return -EINVAL; - } - - if (print_id) - printf("FPGA: Altera %s, version 0x%01x\n", - socfpga_fpga_model[i].name, version); - return i; -} - -/* - * Print CPU information - */ -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; - puts("CPU: Altera SoCFPGA Platform\n"); - socfpga_fpga_id(1); - printf("BOOT: %s\n", bsel_str[bsel].name); - return 0; -} -#endif - -#ifdef CONFIG_ARCH_MISC_INIT -int arch_misc_init(void) -{ - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; - const int fpga_id = socfpga_fpga_id(0); - setenv("bootmode", bsel_str[bsel].mode); - if (fpga_id >= 0) - setenv("fpgatype", socfpga_fpga_model[fpga_id].var); - return socfpga_eth_reset(); -} -#endif - #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) @@ -303,15 +104,13 @@ static Altera_desc altera_fpga[] = { }; /* add device descriptor to FPGA device table */ -static void socfpga_fpga_add(void) +void socfpga_fpga_add(void) { int i; fpga_init(); for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) fpga_add(fpga_altera, &altera_fpga[i]); } -#else -static inline void socfpga_fpga_add(void) {} #endif int arch_cpu_init(void) @@ -337,135 +136,3 @@ int arch_cpu_init(void) return 0; } - -/* - * Convert all NIC-301 AMBA slaves from secure to non-secure - */ -static void socfpga_nic301_slave_ns(void) -{ - writel(0x1, &nic301_regs->lwhps2fpgaregs); - writel(0x1, &nic301_regs->hps2fpgaregs); - writel(0x1, &nic301_regs->acp); - writel(0x1, &nic301_regs->rom); - writel(0x1, &nic301_regs->ocram); - writel(0x1, &nic301_regs->sdrdata); -} - -static uint32_t iswgrp_handoff[8]; - -int arch_early_init_r(void) -{ - int i; - - /* - * Write magic value into magic register to unlock support for - * issuing warm reset. The ancient kernel code expects this - * value to be written into the register by the bootloader, so - * to support that old code, we write it here instead of in the - * reset_cpu() function just before resetting the CPU. - */ - writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); - - for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ - iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); - - socfpga_bridges_reset(1); - socfpga_nic301_slave_ns(); - - /* - * Private components security: - * U-Boot : configure private timer, global timer and cpu component - * access as non secure for kernel stage (as required by Linux) - */ - setbits_le32(&scu_regs->sacr, 0xfff); - - /* Configure the L2 controller to make SDRAM start at 0 */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET - writel(0x2, &nic301_regs->remap); -#else - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ - writel(0x1, &pl310->pl310_addr_filter_start); -#endif - - /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); - -#ifdef CONFIG_DESIGNWARE_SPI - /* Get Designware SPI controller out of reset */ - socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); - socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); -#endif - -#ifdef CONFIG_NAND_DENALI - socfpga_per_reset(SOCFPGA_RESET(NAND), 0); -#endif - - return 0; -} - -static void socfpga_sdram_apply_static_cfg(void) -{ - const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c; - const uint32_t applymask = 0x8; - uint32_t val = readl(staticcfg) | applymask; - - /* - * SDRAM staticcfg register specific: - * When applying the register setting, the CPU must not access - * SDRAM. Luckily for us, we can abuse i-cache here to help us - * circumvent the SDRAM access issue. The idea is to make sure - * that the code is in one full i-cache line by branching past - * it and back. Once it is in the i-cache, we execute the core - * of the code and apply the register settings. - * - * The code below uses 7 instructions, while the Cortex-A9 has - * 32-byte cachelines, thus the limit is 8 instructions total. - */ - asm volatile( - ".align 5 \n" - " b 2f \n" - "1: str %0, [%1] \n" - " dsb \n" - " isb \n" - " b 3f \n" - "2: b 1b \n" - "3: nop \n" - : : "r"(val), "r"(staticcfg) : "memory", "cc"); -} - -int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 2) - return CMD_RET_USAGE; - - argv++; - - switch (*argv[0]) { - case 'e': /* Enable */ - writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); - socfpga_sdram_apply_static_cfg(); - writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080); - writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); - writel(iswgrp_handoff[1], &nic301_regs->remap); - break; - case 'd': /* Disable */ - writel(0, &sysmgr_regs->fpgaintfgrp_module); - writel(0, SOCFPGA_SDR_ADDRESS + 0x5080); - socfpga_sdram_apply_static_cfg(); - writel(0, &reset_manager_base->brg_mod_reset); - writel(1, &nic301_regs->remap); - break; - default: - return CMD_RET_USAGE; - } - - return 0; -} - -U_BOOT_CMD( - bridge, 2, 1, do_bridge, - "SoCFPGA HPS FPGA bridge control", - "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "" -); diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c new file mode 100644 index 0000000000..9d751f6b2f --- /dev/null +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <altera.h> +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <miiphy.h> +#include <netdev.h> +#include <ns16550.h> +#include <watchdog.h> +#include <asm/arch/misc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/sdram_arria10.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/nic301.h> +#include <asm/io.h> +#include <asm/pl310.h> + +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08 +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58 +#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78 +#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98 + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SPL_BUILD) +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = + (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; +#endif + +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + u32 reset; + + if (of_reset_id == EMAC0_RESET) { + reset = SOCFPGA_RESET(EMAC0); + } else if (of_reset_id == EMAC1_RESET) { + reset = SOCFPGA_RESET(EMAC1); + } else if (of_reset_id == EMAC2_RESET) { + reset = SOCFPGA_RESET(EMAC2); + } else { + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + return; + } + + clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + phymode); + + /* Release the EMAC controller from reset */ + socfpga_per_reset(reset, 0); +} +#endif + +#if defined(CONFIG_SPL_BUILD) +/* ++ * This function initializes security policies to be consistent across ++ * all logic units in the Arria 10. ++ * ++ * The idea is to set all security policies to be normal, nonsecure ++ * for all units. ++ */ +static void initialize_security_policies(void) +{ + /* Put OCRAM in non-secure */ + writel(0x003f0000, &noc_fw_ocram_base->region0); + writel(0x1, &noc_fw_ocram_base->enable); +} + +int arch_early_init_r(void) +{ + initialize_security_policies(); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, &pl310->pl310_addr_filter_start); + + /* assert reset to all except L4WD0 and L4TIMER0 */ + socfpga_per_reset_all(); + + /* configuring the clock based on handoff */ + /* TODO: Add call to cm_basic_init() */ + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + return 0; +} +#else +int arch_early_init_r(void) +{ + return 0; +} +#endif + +/* + * This function looking the 1st encounter UART peripheral, + * and then return its offset of the dedicated/shared IO pin + * mux. offset value (zero and above). + */ +static int find_peripheral_uart(const void *blob, + int child, const char *node_name) +{ + int len; + fdt_addr_t base_addr = 0; + fdt_size_t size; + const u32 *cell; + u32 value, offset = 0; + + base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); + if (base_addr != FDT_ADDR_T_NONE) { + cell = fdt_getprop(blob, child, "pinctrl-single,pins", + &len); + if (cell != NULL) { + for (; len > 0; len -= (2 * sizeof(u32))) { + offset = fdt32_to_cpu(*cell++); + value = fdt32_to_cpu(*cell++); + /* Found UART peripheral. */ + if (value == PINMUX_UART) + return offset; + } + } + } + return -EINVAL; +} + +/* + * This function looks up the 1st encounter UART peripheral, + * and then return its offset of the dedicated/shared IO pin + * mux. UART peripheral is found if the offset is not in negative + * value. + */ +static int is_peripheral_uart_true(const void *blob, + int node, const char *child_name) +{ + int child, len; + const char *node_name; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return -EINVAL; + + node_name = fdt_get_name(blob, child, &len); + + while (node_name) { + if (!strcmp(child_name, node_name)) + return find_peripheral_uart(blob, child, node_name); + + child = fdt_next_subnode(blob, child); + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, &len); + } + + return -1; +} + +/* + * This function looking the 1st encounter UART dedicated IO peripheral, + * and then return based address of the 1st encounter UART dedicated + * IO peripheral. + */ +unsigned int dedicated_uart_com_port(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + if (node < 0) + return 0; + + if (is_peripheral_uart_true(blob, node, "dedicated") >= 0) + return SOCFPGA_UART1_ADDRESS; + + return 0; +} + +/* + * This function looking the 1st encounter UART shared IO peripheral, and then + * return based address of the 1st encounter UART shared IO peripheral. + */ +unsigned int shared_uart_com_port(const void *blob) +{ + int node, ret; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + if (node < 0) + return 0; + + ret = is_peripheral_uart_true(blob, node, "shared"); + + if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 || + ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 || + ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3) + return SOCFPGA_UART0_ADDRESS; + else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 || + ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 || + ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3) + return SOCFPGA_UART1_ADDRESS; + + return 0; +} + +/* + * This function looking the 1st encounter UART peripheral, and then return + * base address of the 1st encounter UART peripheral. + */ +unsigned int uart_com_port(const void *blob) +{ + unsigned int ret; + + ret = dedicated_uart_com_port(blob); + + if (ret) + return ret; + + return shared_uart_com_port(blob); +} + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + const u32 bsel = + SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); + + puts("CPU: Altera SoCFPGA Arria 10\n"); + + printf("BOOT: %s\n", bsel_str[bsel].name); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c new file mode 100644 index 0000000000..49b26b3570 --- /dev/null +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <altera.h> +#include <miiphy.h> +#include <netdev.h> +#include <watchdog.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/scan_manager.h> +#include <asm/arch/sdram.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/nic301.h> +#include <asm/arch/scu.h> +#include <asm/pl310.h> + +#include <dt-bindings/reset/altr,rst-mgr.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +static struct socfpga_reset_manager *reset_manager_base = + (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS; +static struct nic301_registers *nic301_regs = + (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; +static struct scu_registers *scu_regs = + (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; +static struct socfpga_sdr_ctrl *sdr_ctrl = + (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; + +/* + * DesignWare Ethernet initialization + */ +#ifdef CONFIG_ETH_DESIGNWARE +void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) +{ + u32 physhift, reset; + + if (of_reset_id == EMAC0_RESET) { + physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; + reset = SOCFPGA_RESET(EMAC0); + } else if (of_reset_id == EMAC1_RESET) { + physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; + reset = SOCFPGA_RESET(EMAC1); + } else { + printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); + return; + } + + /* configure to PHY interface select choosed */ + clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, + phymode << physhift); + + /* Release the EMAC controller from reset */ + socfpga_per_reset(reset, 0); +} + +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + +static int socfpga_eth_reset(void) +{ + const void *fdt = gd->fdt_blob; + struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; + int nodes[2]; /* Max. two GMACs */ + int ret, count; + int i, node; + + /* Put both GMACs into RESET state. */ + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1); + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1); + + count = fdtdec_find_aliases_for_id(fdt, "ethernet", + COMPAT_ALTERA_SOCFPGA_DWMAC, + nodes, ARRAY_SIZE(nodes)); + for (i = 0; i < count; i++) { + node = nodes[i]; + if (node <= 0) + continue; + + ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", + "#reset-cells", 1, 0, + &args); + if (ret || (args.args_count != 1)) { + debug("GMAC%i: Failed to parse DT 'resets'!\n", i); + continue; + } + + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); + } + + return 0; +} +#else +static int socfpga_eth_reset(void) +{ + return 0; +}; +#endif + +static const struct { + const u16 pn; + const char *name; + const char *var; +} const socfpga_fpga_model[] = { + /* Cyclone V E */ + { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, + { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, + { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" }, + { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" }, + { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" }, + /* Cyclone V GX/GT */ + { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" }, + { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" }, + { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" }, + { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" }, + { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" }, + /* Cyclone V SE/SX/ST */ + { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" }, + { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" }, + { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" }, + { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, + /* Arria V */ + { 0x2d03, "Arria V, D5", "av_d5" }, +}; + +static int socfpga_fpga_id(const bool print_id) +{ + const u32 altera_mi = 0x6e; + const u32 id = scan_mgr_get_fpga_id(); + + const u32 lsb = id & 0x00000001; + const u32 mi = (id >> 1) & 0x000007ff; + const u32 pn = (id >> 12) & 0x0000ffff; + const u32 version = (id >> 28) & 0x0000000f; + int i; + + if ((mi != altera_mi) || (lsb != 1)) { + printf("FPGA: Not Altera chip ID\n"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++) + if (pn == socfpga_fpga_model[i].pn) + break; + + if (i == ARRAY_SIZE(socfpga_fpga_model)) { + printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id); + return -EINVAL; + } + + if (print_id) + printf("FPGA: Altera %s, version 0x%01x\n", + socfpga_fpga_model[i].name, version); + return i; +} + +/* + * Print CPU information + */ +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + const u32 bsel = + SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); + + puts("CPU: Altera SoCFPGA Platform\n"); + socfpga_fpga_id(1); + + printf("BOOT: %s\n", bsel_str[bsel].name); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; + const int fpga_id = socfpga_fpga_id(0); + setenv("bootmode", bsel_str[bsel].mode); + if (fpga_id >= 0) + setenv("fpgatype", socfpga_fpga_model[fpga_id].var); + return socfpga_eth_reset(); +} +#endif + +/* + * Convert all NIC-301 AMBA slaves from secure to non-secure + */ +static void socfpga_nic301_slave_ns(void) +{ + writel(0x1, &nic301_regs->lwhps2fpgaregs); + writel(0x1, &nic301_regs->hps2fpgaregs); + writel(0x1, &nic301_regs->acp); + writel(0x1, &nic301_regs->rom); + writel(0x1, &nic301_regs->ocram); + writel(0x1, &nic301_regs->sdrdata); +} + +static u32 iswgrp_handoff[8]; + +int arch_early_init_r(void) +{ + int i; + + /* + * Write magic value into magic register to unlock support for + * issuing warm reset. The ancient kernel code expects this + * value to be written into the register by the bootloader, so + * to support that old code, we write it here instead of in the + * reset_cpu() function just before resetting the CPU. + */ + writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); + + for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ + iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); + + socfpga_bridges_reset(1); + + socfpga_nic301_slave_ns(); + + /* + * Private components security: + * U-Boot : configure private timer, global timer and cpu component + * access as non secure for kernel stage (as required by Linux) + */ + setbits_le32(&scu_regs->sacr, 0xfff); + + /* Configure the L2 controller to make SDRAM start at 0 */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET + writel(0x2, &nic301_regs->remap); +#else + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + writel(0x1, &pl310->pl310_addr_filter_start); +#endif + + /* Add device descriptor to FPGA device table */ + socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0); + socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0); +#endif + +#ifdef CONFIG_NAND_DENALI + socfpga_per_reset(SOCFPGA_RESET(NAND), 0); +#endif + + return 0; +} + +static void socfpga_sdram_apply_static_cfg(void) +{ + const u32 applymask = 0x8; + u32 val = readl(&sdr_ctrl->static_cfg) | applymask; + + /* + * SDRAM staticcfg register specific: + * When applying the register setting, the CPU must not access + * SDRAM. Luckily for us, we can abuse i-cache here to help us + * circumvent the SDRAM access issue. The idea is to make sure + * that the code is in one full i-cache line by branching past + * it and back. Once it is in the i-cache, we execute the core + * of the code and apply the register settings. + * + * The code below uses 7 instructions, while the Cortex-A9 has + * 32-byte cachelines, thus the limit is 8 instructions total. + */ + asm volatile( + ".align 5 \n" + " b 2f \n" + "1: str %0, [%1] \n" + " dsb \n" + " isb \n" + " b 3f \n" + "2: b 1b \n" + "3: nop \n" + : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); +} + +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + + argv++; + + switch (*argv[0]) { + case 'e': /* Enable */ + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); + socfpga_sdram_apply_static_cfg(); + writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); + writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); + writel(iswgrp_handoff[1], &nic301_regs->remap); + break; + case 'd': /* Disable */ + writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, &sdr_ctrl->fpgaport_rst); + socfpga_sdram_apply_static_cfg(); + writel(0, &reset_manager_base->brg_mod_reset); + writel(1, &nic301_regs->remap); + break; + default: + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + bridge, 2, 1, do_bridge, + "SoCFPGA HPS FPGA bridge control", + "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "" +); diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c b/arch/arm/mach-socfpga/pinmux_arria10.c new file mode 100644 index 0000000000..69d6a928a0 --- /dev/null +++ b/arch/arm/mach-socfpga/pinmux_arria10.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/arch/pinmux.h> +#include <asm/io.h> +#include <common.h> +#include <fdtdec.h> + +static int do_pinctr_pin(const void *blob, int child, const char *node_name) +{ + int len; + fdt_addr_t base_addr; + fdt_size_t size; + const u32 *cell; + u32 offset, value; + + base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); + if (base_addr != FDT_ADDR_T_NONE) { + cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len); + if (!cell || len <= 0) + return -EFAULT; + + debug("%p %d\n", cell, len); + for (; len > 0; len -= (2 * sizeof(u32))) { + offset = fdt32_to_cpu(*cell++); + value = fdt32_to_cpu(*cell++); + debug("<0x%x 0x%x>\n", offset, value); + writel(value, base_addr + offset); + } + return 0; + } + return -EFAULT; +} + +static int do_pinctrl_pins(const void *blob, int node, const char *child_name) +{ + int child, len; + const char *node_name; + + child = fdt_first_subnode(blob, node); + + if (child < 0) + return -EINVAL; + + node_name = fdt_get_name(blob, child, &len); + + while (node_name) { + if (!strcmp(child_name, node_name)) + return do_pinctr_pin(blob, child, node_name); + + child = fdt_next_subnode(blob, child); + + if (child < 0) + break; + + node_name = fdt_get_name(blob, child, &len); + } + + return -EFAULT; +} + +int config_dedicated_pins(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + if (node < 0) + return -EINVAL; + + if (do_pinctrl_pins(blob, node, "dedicated_cfg")) + return -EFAULT; + + if (do_pinctrl_pins(blob, node, "dedicated")) + return -EFAULT; + + return 0; +} + +int config_pins(const void *blob, const char *pin_grp) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE); + if (node < 0) + return -EINVAL; + + if (do_pinctrl_pins(blob, node, pin_grp)) + return -EFAULT; + + return 0; +} diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2f22..29438ed533 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -7,53 +7,12 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/fpga_manager.h> #include <asm/arch/reset_manager.h> -#include <asm/arch/system_manager.h> DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; - -/* Assert or de-assert SoCFPGA reset manager reset. */ -void socfpga_per_reset(u32 reset, int set) -{ - const void *reg; - - if (RSTMGR_BANK(reset) == 0) - reg = &reset_manager_base->mpu_mod_reset; - else if (RSTMGR_BANK(reset) == 1) - reg = &reset_manager_base->per_mod_reset; - else if (RSTMGR_BANK(reset) == 2) - reg = &reset_manager_base->per2_mod_reset; - else if (RSTMGR_BANK(reset) == 3) - reg = &reset_manager_base->brg_mod_reset; - else if (RSTMGR_BANK(reset) == 4) - reg = &reset_manager_base->misc_mod_reset; - else /* Invalid reset register, do nothing */ - return; - - if (set) - setbits_le32(reg, 1 << RSTMGR_RESET(reset)); - else - clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); -} - -/* - * Assert reset on every peripheral but L4WD0. - * Watchdog must be kept intact to prevent glitches - * and/or hangs. - */ -void socfpga_per_reset_all(void) -{ - const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); - - writel(~l4wd0, &reset_manager_base->per_mod_reset); - writel(0xffffffff, &reset_manager_base->per2_mod_reset); -} /* * Write the reset manager register to cause reset @@ -61,8 +20,8 @@ void socfpga_per_reset_all(void) void reset_cpu(ulong addr) { /* request a warm reset */ - writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), - &reset_manager_base->ctrl); + writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, + &reset_manager_base->ctrl); /* * infinite loop here as watchdog will trigger and reset * the processor @@ -70,51 +29,3 @@ void reset_cpu(ulong addr) while (1) ; } - -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -void socfpga_bridges_reset(int enable) -{ - /* For SoCFPGA-VT, this is NOP. */ -} -#else - -#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 -#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 -#define L3REGS_REMAP_OCRAM_MASK 0x01 - -void socfpga_bridges_reset(int enable) -{ - const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | - L3REGS_REMAP_HPS2FPGA_MASK | - L3REGS_REMAP_OCRAM_MASK; - - if (enable) { - /* brdmodrst */ - writel(0xffffffff, &reset_manager_base->brg_mod_reset); - } else { - writel(0, &sysmgr_regs->iswgrp_handoff[0]); - writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); - - /* Check signal from FPGA. */ - if (!fpgamgr_test_fpga_ready()) { - /* FPGA not ready, do nothing. */ - printf("%s: FPGA not ready, aborting.\n", __func__); - return; - } - - /* brdmodrst */ - writel(0, &reset_manager_base->brg_mod_reset); - - /* Remap the bridges into memory map */ - writel(l3mask, SOCFPGA_L3REGS_ADDRESS); - } -} -#endif diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c new file mode 100644 index 0000000000..d8c858c833 --- /dev/null +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -0,0 +1,383 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/io.h> +#include <asm/arch/fpga_manager.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <wait_bit.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \ + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \ + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \ + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \ + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \ + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK) + +void socfpga_reset_uart(int assert) +{ + unsigned int com_port; + + com_port = uart_com_port(gd->fdt_blob); + + if (com_port == SOCFPGA_UART1_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(UART1), assert); + else if (com_port == SOCFPGA_UART0_ADDRESS) + socfpga_per_reset(SOCFPGA_RESET(UART0), assert); +} + +static const u32 per0fpgamasks[] = { + ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | + ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK, + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | + ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK, + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | + ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK, + 0, /* i2c0 per1mod */ + 0, /* i2c1 per1mod */ + 0, /* i2c0_emac */ + 0, /* i2c1_emac */ + 0, /* i2c2_emac */ + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | + ALT_RSTMGR_PER0MODRST_NAND_SET_MSK, + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | + ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK, + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK | + ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK, + ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK, + ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK, + ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK, + ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK, + 0, /* uart0 per1mod */ + 0, /* uart1 per1mod */ +}; + +static const u32 per1fpgamasks[] = { + 0, /* emac0 per0mod */ + 0, /* emac1 per0mod */ + 0, /* emac2 per0mod */ + ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK, + ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK, + ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */ + ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */ + ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */ + 0, /* nand per0mod */ + 0, /* qspi per0mod */ + 0, /* sdmmc per0mod */ + 0, /* spim0 per0mod */ + 0, /* spim1 per0mod */ + 0, /* spis0 per0mod */ + 0, /* spis1 per0mod */ + ALT_RSTMGR_PER1MODRST_UART0_SET_MSK, + ALT_RSTMGR_PER1MODRST_UART1_SET_MSK, +}; + +struct bridge_cfg { + int compat_id; + u32 mask_noc; + u32 mask_rstmgr; +}; + +static const struct bridge_cfg bridge_cfg_tbl[] = { + { + COMPAT_ALTERA_SOCFPGA_H2F_BRG, + ALT_SYSMGR_NOC_H2F_SET_MSK, + ALT_RSTMGR_BRGMODRST_H2F_SET_MSK, + }, + { + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG, + ALT_SYSMGR_NOC_LWH2F_SET_MSK, + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK, + }, + { + COMPAT_ALTERA_SOCFPGA_F2H_BRG, + ALT_SYSMGR_NOC_F2H_SET_MSK, + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK, + }, + { + COMPAT_ALTERA_SOCFPGA_F2SDR0, + ALT_SYSMGR_NOC_F2SDR0_SET_MSK, + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK, + }, + { + COMPAT_ALTERA_SOCFPGA_F2SDR1, + ALT_SYSMGR_NOC_F2SDR1_SET_MSK, + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK, + }, + { + COMPAT_ALTERA_SOCFPGA_F2SDR2, + ALT_SYSMGR_NOC_F2SDR2_SET_MSK, + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK, + }, +}; + +/* Disable the watchdog (toggle reset to watchdog) */ +void socfpga_watchdog_disable(void) +{ + /* assert reset for watchdog */ + setbits_le32(&reset_manager_base->per1modrst, + ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); +} + +/* Release NOC ddr scheduler from reset */ +void socfpga_reset_deassert_noc_ddr_scheduler(void) +{ + clrbits_le32(&reset_manager_base->brgmodrst, + ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK); +} + +/* Check whether Watchdog in reset state? */ +int socfpga_is_wdt_in_reset(void) +{ + u32 val; + + val = readl(&reset_manager_base->per1modrst); + val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK; + + /* return 0x1 if watchdog in reset */ + return val; +} + +/* emacbase: base address of emac to enable/disable reset + * state: 0 - disable reset, !0 - enable reset + */ +void socfpga_emac_manage_reset(ulong emacbase, u32 state) +{ + ulong eccmask; + ulong emacmask; + + switch (emacbase) { + case SOCFPGA_EMAC0_ADDRESS: + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK; + emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK; + break; + case SOCFPGA_EMAC1_ADDRESS: + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK; + emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK; + break; + case SOCFPGA_EMAC2_ADDRESS: + eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK; + emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK; + break; + default: + error("emac base address unexpected! %lx", emacbase); + hang(); + break; + } + + if (state) { + /* Enable ECC OCP first */ + setbits_le32(&reset_manager_base->per0modrst, eccmask); + setbits_le32(&reset_manager_base->per0modrst, emacmask); + } else { + /* Disable ECC OCP first */ + clrbits_le32(&reset_manager_base->per0modrst, emacmask); + clrbits_le32(&reset_manager_base->per0modrst, eccmask); + } +} + +static int get_bridge_init_val(const void *blob, int compat_id) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, compat_id); + if (node < 0) + return 0; + + return fdtdec_get_uint(blob, node, "init-val", 0); +} + +/* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */ +int socfpga_reset_deassert_bridges_handoff(void) +{ + u32 mask_noc = 0, mask_rstmgr = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) { + if (get_bridge_init_val(gd->fdt_blob, + bridge_cfg_tbl[i].compat_id)) { + mask_noc |= bridge_cfg_tbl[i].mask_noc; + mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr; + } + } + + /* clear idle request to all bridges */ + setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc); + + /* Release bridges from reset state per handoff value */ + clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr); + + /* Poll until all idleack to 0, timeout at 1000ms */ + return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc, + false, 1000, false); +} + +void socfpga_reset_assert_fpga_connected_peripherals(void) +{ + u32 mask0 = 0; + u32 mask1 = 0; + u32 fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS; + int i; + + for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) { + if (readl(fpga_pinux_addr)) { + mask0 |= per0fpgamasks[i]; + mask1 |= per1fpgamasks[i]; + } + fpga_pinux_addr += sizeof(u32); + } + + setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK); + setbits_le32(&reset_manager_base->per1modrst, mask1); + setbits_le32(&reset_manager_base->per0modrst, mask0); +} + +/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */ +void socfpga_reset_deassert_osc1wd0(void) +{ + clrbits_le32(&reset_manager_base->per1modrst, + ALT_RSTMGR_PER1MODRST_WD0_SET_MSK); +} + +/* + * Assert or de-assert SoCFPGA reset manager reset. + */ +void socfpga_per_reset(u32 reset, int set) +{ + const u32 *reg; + u32 rstmgr_bank = RSTMGR_BANK(reset); + + switch (rstmgr_bank) { + case 0: + reg = &reset_manager_base->mpumodrst; + break; + case 1: + reg = &reset_manager_base->per0modrst; + break; + case 2: + reg = &reset_manager_base->per1modrst; + break; + case 3: + reg = &reset_manager_base->brgmodrst; + break; + case 4: + reg = &reset_manager_base->sysmodrst; + break; + + default: + return; + } + + if (set) + setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + else + clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); +} + +/* + * Assert reset on every peripheral but L4WD0. + * Watchdog must be kept intact to prevent glitches + * and/or hangs. + * For the Arria10, we disable all the peripherals except L4 watchdog0, + * L4 Timer 0, and ECC. + */ +void socfpga_per_reset_all(void) +{ + const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | + (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0)))); + unsigned mask_ecc_ocp = + ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | + ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | + ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | + ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK | + ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK | + ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | + ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | + ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK; + + /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */ + writel(~l4wd0, &reset_manager_base->per1modrst); + setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp); + + /* Finally disable the ECC_OCP */ + setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp); +} + +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +int socfpga_bridges_reset(int enable) +{ + /* For SoCFPGA-VT, this is NOP. */ + return 0; +} +#else +int socfpga_bridges_reset(int enable) +{ + int ret; + + /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps, + fpga2sdram) */ + /* set idle request to all bridges */ + writel(ALT_SYSMGR_NOC_H2F_SET_MSK | + ALT_SYSMGR_NOC_LWH2F_SET_MSK | + ALT_SYSMGR_NOC_F2H_SET_MSK | + ALT_SYSMGR_NOC_F2SDR0_SET_MSK | + ALT_SYSMGR_NOC_F2SDR1_SET_MSK | + ALT_SYSMGR_NOC_F2SDR2_SET_MSK, + &sysmgr_regs->noc_idlereq_set); + + /* Enable the NOC timeout */ + writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout); + + /* Poll until all idleack to 1 */ + ret = wait_for_bit(__func__, &sysmgr_regs->noc_idleack, + ALT_SYSMGR_NOC_H2F_SET_MSK | + ALT_SYSMGR_NOC_LWH2F_SET_MSK | + ALT_SYSMGR_NOC_F2H_SET_MSK | + ALT_SYSMGR_NOC_F2SDR0_SET_MSK | + ALT_SYSMGR_NOC_F2SDR1_SET_MSK | + ALT_SYSMGR_NOC_F2SDR2_SET_MSK, + true, 10000, false); + if (ret) + return ret; + + /* Poll until all idlestatus to 1 */ + ret = wait_for_bit(__func__, &sysmgr_regs->noc_idlestatus, + ALT_SYSMGR_NOC_H2F_SET_MSK | + ALT_SYSMGR_NOC_LWH2F_SET_MSK | + ALT_SYSMGR_NOC_F2H_SET_MSK | + ALT_SYSMGR_NOC_F2SDR0_SET_MSK | + ALT_SYSMGR_NOC_F2SDR1_SET_MSK | + ALT_SYSMGR_NOC_F2SDR2_SET_MSK, + true, 10000, false); + if (ret) + return ret; + + /* Put all bridges (except NOR DDR scheduler) into reset state */ + setbits_le32(&reset_manager_base->brgmodrst, + (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK | + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK | + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK)); + + /* Disable NOC timeout */ + writel(0, &sysmgr_regs->noc_timeout); + + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c new file mode 100644 index 0000000000..aa88adb414 --- /dev/null +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/fpga_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; +static const struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + +/* Assert or de-assert SoCFPGA reset manager reset. */ +void socfpga_per_reset(u32 reset, int set) +{ + const u32 *reg; + u32 rstmgr_bank = RSTMGR_BANK(reset); + + switch (rstmgr_bank) { + case 0: + reg = &reset_manager_base->mpu_mod_reset; + break; + case 1: + reg = &reset_manager_base->per_mod_reset; + break; + case 2: + reg = &reset_manager_base->per2_mod_reset; + break; + case 3: + reg = &reset_manager_base->brg_mod_reset; + break; + case 4: + reg = &reset_manager_base->misc_mod_reset; + break; + + default: + return; + } + + if (set) + setbits_le32(reg, 1 << RSTMGR_RESET(reset)); + else + clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); +} + +/* + * Assert reset on every peripheral but L4WD0. + * Watchdog must be kept intact to prevent glitches + * and/or hangs. + */ +void socfpga_per_reset_all(void) +{ + const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); + + writel(~l4wd0, &reset_manager_base->per_mod_reset); + writel(0xffffffff, &reset_manager_base->per2_mod_reset); +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +void socfpga_bridges_reset(int enable) +{ + /* For SoCFPGA-VT, this is NOP. */ + return; +} +#else + +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 +#define L3REGS_REMAP_OCRAM_MASK 0x01 + +void socfpga_bridges_reset(int enable) +{ + const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | + L3REGS_REMAP_HPS2FPGA_MASK | + L3REGS_REMAP_OCRAM_MASK; + + if (enable) { + /* brdmodrst */ + writel(0xffffffff, &reset_manager_base->brg_mod_reset); + } else { + writel(0, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + + /* Check signal from FPGA. */ + if (!fpgamgr_test_fpga_ready()) { + /* FPGA not ready, do nothing. We allow system to boot + * without FPGA ready. So, return 0 instead of error. */ + printf("%s: FPGA not ready, aborting.\n", __func__); + return; + } + + /* brdmodrst */ + writel(0, &reset_manager_base->brg_mod_reset); + + /* Remap the bridges into memory map */ + writel(l3mask, SOCFPGA_L3REGS_ADDRESS); + } + return; +} +#endif diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index fec4c7a991..71bae827a1 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -19,23 +19,32 @@ #include <asm/arch/sdram.h> #include <asm/arch/scu.h> #include <asm/arch/nic301.h> +#include <asm/sections.h> +#include <fdtdec.h> +#include <watchdog.h> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/pinmux.h> +#endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = +#endif + +static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; u32 spl_boot_device(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo); - switch (bsel & 0x7) { + switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { case 0x1: /* FPGA (HPS2FPGA Bridge) */ return BOOT_DEVICE_RAM; case 0x2: /* NAND Flash (1.8V) */ @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static void socfpga_nic301_slave_ns(void) { writel(0x1, &nic301_regs->lwhps2fpgaregs); @@ -127,7 +137,8 @@ void board_init_f(ulong dummy) debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ - cm_basic_init(cm_default_cfg); + if (cm_basic_init(cm_default_cfg)) + hang(); /* Enable bootrom to configure IOs. */ sysmgr_config_warmrstcfgio(1); @@ -182,3 +193,42 @@ void board_init_f(ulong dummy) /* Configure simple malloc base pointer into RAM. */ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024); } +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +void spl_board_init(void) +{ + /* configuring the clock based on handoff */ + cm_basic_init(gd->fdt_blob); + WATCHDOG_RESET(); + + config_dedicated_pins(gd->fdt_blob); + WATCHDOG_RESET(); + + /* Release UART from reset */ + socfpga_reset_uart(0); + + /* enable console uart printing */ + preloader_console_init(); +} + +void board_init_f(ulong dummy) +{ + /* + * Configure Clock Manager to use intosc clock instead external osc to + * ensure success watchdog operation. We do it as early as possible. + */ + cm_use_intosc(); + + socfpga_watchdog_disable(); + + arch_early_init_r(); + +#ifdef CONFIG_HW_WATCHDOG + /* release osc1 watchdog timer 0 from reset */ + socfpga_reset_deassert_osc1wd0(); + + /* reconfigure and enable the watchdog */ + hw_watchdog_init(); + WATCHDOG_RESET(); +#endif /* CONFIG_HW_WATCHDOG */ +} +#endif diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager_gen5.c index 75a65f3e62..3588a570a7 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager_gen5.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -21,7 +21,7 @@ static struct socfpga_system_manager *sysmgr_regs = */ static void populate_sysmgr_fpgaintf_module(void) { - uint32_t handoff_val = 0; + u32 handoff_val = 0; /* ISWGRP_HANDOFF_FPGAINTF */ writel(0, &sysmgr_regs->iswgrp_handoff[2]); @@ -56,7 +56,7 @@ static void populate_sysmgr_fpgaintf_module(void) */ void sysmgr_pinmux_init(void) { - uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0]; + u32 regs = (u32)&sysmgr_regs->emacio[0]; const u8 *sys_mgr_init_table; unsigned int len; int i; diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 8d9900e00b..7ced838d6a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -143,12 +143,16 @@ config MACH_SUN50I select SUNXI_GEN_SUN6I select SUNXI_HIGH_SRAM select SUPPORT_SPL + select FIT + select SPL_LOAD_FIT config MACH_SUN50I_H5 bool "sun50i (Allwinner H5)" select ARM64 select MACH_SUNXI_H3_H5 select SUNXI_HIGH_SRAM + select FIT + select SPL_LOAD_FIT endchoice diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index c67ffa5a23..940257b5ec 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -49,6 +49,7 @@ config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" select CPU_V7 select SPL + select SPL_BOARD_INIT if SPL select SUPPORT_SPL select TEGRA_COMMON select TEGRA_GPIO @@ -126,4 +127,20 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config CMD_ENTERRCM + bool "Enable 'enterrcm' command" + default y + help + Tegra's boot ROM supports a mode whereby code may be downloaded and + flash-programmed over a USB connection. On dev boards, this is + typically entered by holding down a "force recovery" button and + resetting the CPU. However, not all boards have such a button (one + example is the Compulab Trimslice), so a method to enter RCM from + software is useful. + + Even on boards other than Trimslice, controlling this over a UART + may be useful, e.g. to allow simple remote control without the need + for mechanical button actuators, or hooking up relays/... to the + button. + endif diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile index eb34c207ce..06072f23bd 100644 --- a/arch/arm/mach-uniphier/arm64/Makefile +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -9,5 +9,7 @@ obj-y += mem_map.o ifdef CONFIG_ARMV8_MULTIENTRY obj-y += smp.o smp_kick_cpus.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o +else +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += lowlevel_init.o endif endif diff --git a/arch/arm/mach-uniphier/arm64/lowlevel_init.S b/arch/arm/mach-uniphier/arm64/lowlevel_init.S new file mode 100644 index 0000000000..e52db1d7fc --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/lowlevel_init.S @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + /* LD20 needs the following code to boot. I do not know why. */ + mrs x0, sctlr_el1 + msr sctlr_el1, x0 + ret +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index 2564a02a62..e05d6bffd5 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -175,6 +175,7 @@ static const struct uniphier_initdata uniphier_initdata[] = { .nand_2cs = false, .sbc_init = uniphier_pxs2_sbc_init, .pll_init = uniphier_pxs3_pll_init, + .clk_init = uniphier_pxs3_clk_init, }, #endif }; diff --git a/arch/arm/mach-uniphier/boot-device/Makefile b/arch/arm/mach-uniphier/boot-device/Makefile index a54d2acb10..abb58a729a 100644 --- a/arch/arm/mach-uniphier/boot-device/Makefile +++ b/arch/arm/mach-uniphier/boot-device/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-device-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-device-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += boot-device-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-device-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += boot-device-pxs3.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE) += spl_board.o diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c new file mode 100644 index 0000000000..fe45a01cc2 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-device/boot-device-pxs3.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <linux/io.h> +#include <linux/kernel.h> + +#include "../sg-regs.h" +#include "boot-device.h" + +const struct uniphier_boot_device uniphier_pxs3_boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5, BBM Last Page)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5, BBM Last Page)"}, +}; + +const unsigned uniphier_pxs3_boot_device_count = + ARRAY_SIZE(uniphier_pxs3_boot_device_table); + +int uniphier_pxs3_boot_device_is_usb(u32 pinmon) +{ + return !!(readl(SG_PINMON2) & BIT(31)); +} diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 00809777b2..094f77b4d1 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -115,6 +115,16 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .have_internal_stm = 1, }, #endif +#if defined(CONFIG_ARCH_UNIPHIER_PXS3) + { + .soc_id = UNIPHIER_PXS3_ID, + .boot_device_sel_shift = 1, + .boot_device_table = uniphier_pxs3_boot_device_table, + .boot_device_count = &uniphier_pxs3_boot_device_count, + .boot_device_is_usb = uniphier_pxs3_boot_device_is_usb, + .have_internal_stm = 0, + }, +#endif }; UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_boot_device_info, uniphier_boot_device_info) diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h index f3fb2f32a8..c4ce3e50a3 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.h +++ b/arch/arm/mach-uniphier/boot-device/boot-device.h @@ -18,16 +18,19 @@ extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[]; extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[]; extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[]; +extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[]; extern const unsigned int uniphier_sld3_boot_device_count; extern const unsigned int uniphier_ld4_boot_device_count; extern const unsigned int uniphier_pro5_boot_device_count; extern const unsigned int uniphier_pxs2_boot_device_count; extern const unsigned int uniphier_ld11_boot_device_count; +extern const unsigned int uniphier_pxs3_boot_device_count; int uniphier_pxs2_boot_device_is_usb(u32 pinmon); int uniphier_ld11_boot_device_is_usb(u32 pinmon); int uniphier_ld20_boot_device_is_usb(u32 pinmon); +int uniphier_pxs3_boot_device_is_usb(u32 pinmon); unsigned int uniphier_pxs2_boot_device_fixup(unsigned int mode); unsigned int uniphier_ld11_boot_device_fixup(unsigned int mode); diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 41341970ec..dad035d03a 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-pxs3.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o endif diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index 36aa787984..0266e7e66b 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -33,7 +33,7 @@ void uniphier_ld11_clk_init(void) /* TODO: use "mmc-pwrseq-emmc" */ writel(1, SDCTRL_EMMC_HW_RESET); -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD { /* FIXME: the current clk driver can not handle parents */ u32 tmp; diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c index 62b6927732..def87c1aac 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld4.c +++ b/arch/arm/mach-uniphier/clk/clk-ld4.c @@ -31,7 +31,7 @@ void uniphier_ld4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_CLKCTRL_CEN_ETHER; #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; #endif #ifdef CONFIG_NAND_DENALI diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c index 92b73384ab..19be4f3145 100644 --- a/arch/arm/mach-uniphier/clk/clk-pro4.c +++ b/arch/arm/mach-uniphier/clk/clk-pro4.c @@ -46,7 +46,7 @@ void uniphier_pro4_clk_init(void) #ifdef CONFIG_UNIPHIER_ETH tmp |= SC_CLKCTRL_CEN_ETHER; #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; #endif #ifdef CONFIG_NAND_DENALI diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c new file mode 100644 index 0000000000..2dee857a18 --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" + +#define SDCTRL_EMMC_HW_RESET 0x59810280 + +void uniphier_pxs3_clk_init(void) +{ + /* TODO: use "mmc-pwrseq-emmc" */ + writel(1, SDCTRL_EMMC_HW_RESET); +} diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 4803d08038..d413d00f95 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -119,6 +119,7 @@ void uniphier_pro5_clk_init(void); void uniphier_pxs2_clk_init(void); void uniphier_ld11_clk_init(void); void uniphier_ld20_clk_init(void); +void uniphier_pxs3_clk_init(void); unsigned int uniphier_boot_device_raw(void); int uniphier_have_internal_stm(void); diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index dc94084c89..029da91f8f 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -70,6 +70,7 @@ /* Pin Monitor */ #define SG_PINMON0 (SG_DBG_BASE | 0x0100) +#define SG_PINMON2 (SG_DBG_BASE | 0x0108) #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19) #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19) diff --git a/arch/arm/mach-uniphier/soc-info.c b/arch/arm/mach-uniphier/soc-info.c index baf1be6a01..f9de3a9dda 100644 --- a/arch/arm/mach-uniphier/soc-info.c +++ b/arch/arm/mach-uniphier/soc-info.c @@ -26,7 +26,7 @@ unsigned int uniphier_get_soc_id(void) unsigned int uniphier_get_soc_model(void) { - return __uniphier_get_revision_field(0x3, 8); + return __uniphier_get_revision_field(0x7, 8); } unsigned int uniphier_get_soc_revision(void) diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index 4fcd01dfff..d72ff46113 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -11,8 +11,12 @@ choice config TARGET_ADP_AG101P bool "Support adp-ag101p" +config TARGET_ADP_AE3XX + bool "Support adp-ae3xx" + endchoice source "board/AndesTech/adp-ag101p/Kconfig" +source "board/AndesTech/adp-ae3xx/Kconfig" endmenu diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile index 7d5ae963ba..3a9ada10d6 100644 --- a/arch/nds32/cpu/n1213/Makefile +++ b/arch/nds32/cpu/n1213/Makefile @@ -12,3 +12,4 @@ extra-y = start.o obj-$(if $(filter ag101,$(SOC)),y) += ag101/ +obj-$(if $(filter ae3xx,$(SOC)),y) += ae3xx/ diff --git a/arch/nds32/cpu/n1213/ae3xx/Makefile b/arch/nds32/cpu/n1213/ae3xx/Makefile new file mode 100644 index 0000000000..07fa9429a9 --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/Makefile @@ -0,0 +1,18 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> +# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cpu.o timer.o +obj-y += lowlevel_init.o + +ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +obj-y += watchdog.o +endif diff --git a/arch/nds32/cpu/n1213/ae3xx/cpu.c b/arch/nds32/cpu/n1213/ae3xx/cpu.c new file mode 100644 index 0000000000..26f878fb5c --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/cpu.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* CPU specific code */ +#include <common.h> +#include <command.h> +#include <watchdog.h> +#include <asm/cache.h> + +#include <faraday/ftwdt010_wdt.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + /* turn off I/D-cache */ + cache_flush(); + icache_disable(); + dcache_disable(); + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + disable_interrupts(); + panic("AE3XX wdt not support yet.\n"); +} diff --git a/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S new file mode 100644 index 0000000000..d4bc2bcd43 --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.pic + +.text + +#include <common.h> +#include <config.h> + +#include <asm/macro.h> +#include <generated/asm-offsets.h> + +/* + * parameters for the SDRAM controller + */ +#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1) +#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2) +#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) +#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) +#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) +#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR) + +#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 +#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 +#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1 +#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 + +#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR +#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR + + +/* + * for Orca and Emerald + */ +#define BOARD_ID_REG 0x104 +#define BOARD_ID_FAMILY_MASK 0xfff000 +#define BOARD_ID_FAMILY_V5 0x556000 +#define BOARD_ID_FAMILY_K7 0x74b000 + +/* + * parameters for the static memory controller + */ +#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR) +#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR) + +#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG +#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING + +/* + * for Orca and Emerald + */ +#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) +#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 + +/* + * parameters for the pmu controoler + */ +#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0) + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +.macro wait_sdram + li $r0, CONFIG_FTSDMC021_BASE +1: + lwi $r1, [$r0+FTSDMC021_CR2] + bnez $r1, 1b +.endm + +.globl mem_init +mem_init: + move $r11, $lp + li $r0, SMC_BANK0_CR_A + lwi $r1, [$r0+#0x00] + ori $r1, $r1, 0x8f0 + xori $r1, $r1, 0x8f0 + /* 16-bit mode */ + ori $r1, $r1, 0x60 + li $r2, 0x00153153 + swi $r1, [$r0+#0x00] + swi $r2, [$r0+#0x04] + move $lp, $r11 + ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + jal remap + +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) + jal enable_fpu +#endif + ret $r10 + +remap: + move $r11, $lp +relo_base: + mfusr $r0, $pc + +#ifdef CONFIG_MEM_REMAP + li $r4, 0x00000000 + li $r5, 0x80000000 + la $r6, _end@GOTOFF +1: + lmw.bim $r12, [$r5], $r19 + smw.bim $r12, [$r4], $r19 + blt $r5, $r6, 1b +#endif /* #ifdef CONFIG_MEM_REMAP */ + move $lp, $r11 +2: + ret + + /* + * enable_fpu: + * Some of Andes CPU version support FPU coprocessor, if so, + * and toolchain support FPU instruction set, we should enable it. + */ +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) +enable_fpu: + mfsr $r0, $CPU_VER /* enable FPU if it exists */ + srli $r0, $r0, 3 + andi $r0, $r0, 1 + beqz $r0, 1f /* skip if no COP */ + mfsr $r0, $FUCOP_EXIST + srli $r0, $r0, 31 + beqz $r0, 1f /* skip if no FPU */ + mfsr $r0, $FUCOP_CTL + ori $r0, $r0, 1 + mtsr $r0, $FUCOP_CTL +1: + ret +#endif + +#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/nds32/cpu/n1213/ae3xx/timer.c b/arch/nds32/cpu/n1213/ae3xx/timer.c new file mode 100644 index 0000000000..a284bf5b1e --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/timer.c @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef CONFIG_TIMER +#include <common.h> +#include <asm/io.h> +#include <faraday/fttmr010.h> +#error "AE3XX timer only support DM flow" +#endif /* CONFIG_TIMER */ diff --git a/arch/nds32/cpu/n1213/ae3xx/watchdog.S b/arch/nds32/cpu/n1213/ae3xx/watchdog.S new file mode 100644 index 0000000000..956c5f8449 --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/watchdog.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch-ag101/ag101.h> +#include <linux/linkage.h> + +.text + +#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +ENTRY(turnoff_watchdog) +#error "AE3XX not support wdt yet" +ENDPROC(turnoff_watchdog) +#endif diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile index c21ce02828..07fa9429a9 100644 --- a/arch/nds32/cpu/n1213/ag101/Makefile +++ b/arch/nds32/cpu/n1213/ag101/Makefile @@ -11,10 +11,7 @@ # obj-y := cpu.o timer.o - -ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o -endif ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG obj-y += watchdog.o diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c index 31d72712f3..9da0b31b4b 100644 --- a/arch/nds32/cpu/n1213/ag101/cpu.c +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -31,16 +31,10 @@ int cleanup_before_linux(void) { disable_interrupts(); -#ifdef CONFIG_MMU /* turn off I/D-cache */ + cache_flush(); icache_disable(); dcache_disable(); - - /* flush I/D-cache */ - invalidate_icac(); - invalidate_dcac(); -#endif - return 0; } diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index abdd340479..452d814042 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -86,25 +86,7 @@ bnez $r1, 1b .endm -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl lowlevel_init -lowlevel_init: - move $r10, $lp - - led 0x0 - jal mem_init - - led 0x10 - jal remap - -#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) - led 0x1f - jal enable_fpu -#endif - - led 0x20 - ret $r10 - +.globl mem_init mem_init: move $r11, $lp @@ -124,9 +106,7 @@ mem_init: lwi $r1, [$r0+#0x00] ori $r1, $r1, 0x8f0 xori $r1, $r1, 0x8f0 - /* - * check board - */ + /* check board */ li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG lwi $r3, [$r3] li $r4, BOARD_ID_FAMILY_MASK @@ -134,29 +114,21 @@ mem_init: li $r4, BOARD_ID_FAMILY_K7 xor $r4, $r3, $r4 beqz $r4, use_flash_16bit_boot - /* - * 32-bit mode - */ + /* 32-bit mode */ use_flash_32bit_boot: ori $r1, $r1, 0x50 li $r2, 0x00151151 j sdram_b0_cr - /* - * 16-bit mode - */ + /* 16-bit mode */ use_flash_16bit_boot: ori $r1, $r1, 0x60 li $r2, 0x00153153 - /* - * SRAM bank0 config - */ + /* SRAM bank0 config */ sdram_b0_cr: swi $r1, [$r0+#0x00] swi $r2, [$r0+#0x04] - /* - * config AHB Controller - */ + /* config AHB Controller */ led 0x02 /* @@ -192,6 +164,21 @@ sdram_b0_cr: move $lp, $r11 ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + led 0x10 + jal remap +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) + led 0x1f + jal enable_fpu +#endif + led 0x20 + ret $r10 + remap: move $r11, $lp #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */ @@ -203,9 +190,7 @@ relo_base: mfusr $r0, $pc #endif /* __NDS32_N1213_43U1H__ */ - /* - * Remapping - */ + /* Remapping */ led 0x1a write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800 write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880 diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c index 758b354110..0c03a1029c 100644 --- a/arch/nds32/cpu/n1213/ag101/timer.c +++ b/arch/nds32/cpu/n1213/ag101/timer.c @@ -8,7 +8,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - +#ifndef CONFIG_TIMER #include <common.h> #include <asm/io.h> #include <faraday/fttmr010.h> @@ -189,3 +189,4 @@ ulong get_tbclk(void) return CONFIG_SYS_CLK_FREQ; #endif } +#endif /* CONFIG_TIMER */ diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 99971fdbdb..f9f999902c 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -114,11 +114,39 @@ reset_gp: set_ivb: li $r0, 0x0 - /* turn on BTB */ mtsr $r0, $misc_ctl /* set IVIC, vector size: 4 bytes, base: 0x0 */ mtsr $r0, $ivb +/* + * MMU_CTL NTC0 Cacheable/Write-Back + */ + li $r0, ~0x3 + mfsr $r1, $mr8 + and $r1, $r1, $r0 + mtsr $r1, $mr8 +#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) + li $r0, 0x4 + mfsr $r1, $mr0 + or $r1, $r1, $r0 + mtsr $r1, $mr0 +#endif + +#if !defined(CONFIG_SYS_ICACHE_OFF) + li $r0, 0x1 + mfsr $r1, $mr8 + or $r1, $r1, $r0 + mtsr $r1, $mr8 +#endif + +#if !defined(CONFIG_SYS_DCACHE_OFF) + li $r0, 0x2 + mfsr $r1, $mr8 + or $r1, $r1, $r0 + mtsr $r1, $mr8 +#endif + + jal mem_init #ifndef CONFIG_SKIP_LOWLEVEL_INIT jal lowlevel_init @@ -133,7 +161,6 @@ update_gp: ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4) add5.pc $gp #endif - /* * do critical initializations first (shall be in short time) * do self_relocation ASAP. @@ -161,11 +188,14 @@ update_gp: */ call_board_init_f: li $sp, CONFIG_SYS_INIT_SP_ADDR - li $r10, GD_SIZE /* get GD size */ - sub $sp, $sp, $r10 /* GD start addr */ - move $r10, $sp + move $r0, $sp + bal board_init_f_alloc_reserve + move $sp, $r0 + bal board_init_f_init_reserve +#ifdef CONFIG_DEBUG_UART + bal debug_uart_init +#endif li $r0, 0x00000000 - #ifdef __PIC__ #ifdef __NDS32_N1213_43U1H__ /* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */ @@ -201,12 +231,10 @@ stack_setup: la $r1, _end@GOTOFF move $r2, $r6 /* r2 <- scratch for copy_loop */ - copy_loop: - lwi.p $r7, [$r0], #4 - swi.p $r7, [$r2], #4 + lmw.bim $r11, [$r0], $r18 + smw.bim $r11, [$r2], $r18 blt $r0, $r1, copy_loop - /* * fix relocations related issues */ @@ -246,6 +274,8 @@ clbss_l: * initialization, now running from RAM. */ call_board_init_r: + bal invalidate_icache_all + bal flush_dcache_all la $r0, board_init_r@GOTOFF move $lp, $r0 /* offset of board_init_r() */ add $lp, $lp, $r9 /* real address of board_init_r() */ diff --git a/arch/nds32/dts/Makefile b/arch/nds32/dts/Makefile new file mode 100644 index 0000000000..1d6b19579c --- /dev/null +++ b/arch/nds32/dts/Makefile @@ -0,0 +1,15 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb +dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts new file mode 100644 index 0000000000..4221e4bf9a --- /dev/null +++ b/arch/nds32/dts/ae3xx.dts @@ -0,0 +1,72 @@ +/dts-v1/; +/ { + compatible = "nds32 ae3xx"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + ethernet0 = &mac0; + } ; + + chosen { + /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <30000000>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <25 4>; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x88000000 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + +}; diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts new file mode 100644 index 0000000000..99cde2f8b8 --- /dev/null +++ b/arch/nds32/dts/ag101p.dts @@ -0,0 +1,63 @@ +/dts-v1/; +/ { + compatible = "nds32 ag101p"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + ethernet0 = &mac0; + } ; + + chosen { + /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */ + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@99600000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x99600000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + no-loopback-test = <1>; + }; + + timer0: timer@98400000 { + compatible = "andestech,attmr010"; + reg = <0x98400000 0x1000>; + interrupts = <19 4>; + clock-frequency = <15000000>; + }; + + mac0: mac@90900000 { + compatible = "andestech,atmac100"; + reg = <0x90900000 0x1000>; + interrupts = <25 4>; + }; +}; diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h new file mode 100644 index 0000000000..b074e8489a --- /dev/null +++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 Andes Technology Corporation + * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AE3XX_H +#define __AE3XX_H + +/* Hardware register bases */ + +/* Static Memory Controller (SRAM) */ +#define CONFIG_FTSMC020_BASE 0xe0400000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0xf0c00000 +/* AHB-to-APB Bridge */ +#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 +/* Reserved */ +#define CONFIG_RESERVED_01_BASE 0xe0500000 +/* Reserved */ +#define CONFIG_RESERVED_02_BASE 0xf0800000 +/* Reserved */ +#define CONFIG_RESERVED_03_BASE 0xf0900000 +/* Ethernet */ +#define CONFIG_FTMAC100_BASE 0xe0100000 +/* Reserved */ +#define CONFIG_RESERVED_04_BASE 0xf1000000 + +/* APB Device definitions */ + +/* UART1 */ +#define CONFIG_FTUART010_01_BASE 0xf0200000 +/* UART2 */ +#define CONFIG_FTUART010_02_BASE 0xf0300000 +/* Counter/Timers */ +#define CONFIG_FTTMR010_BASE 0xf0400000 +/* Watchdog Timer */ +#define CONFIG_FTWDT010_BASE 0xf0500000 +/* Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0xf0600000 +/* GPIO */ +#define CONFIG_FTGPIO010_BASE 0xf0700000 +/* I2C */ +#define CONFIG_FTIIC010_BASE 0xf0a00000 +/* SD Controller */ +#define CONFIG_FTSDC010_BASE 0xf0e00000 + +/* The following address was not defined in Linux */ + +/* Synchronous Serial Port Controller (SSP) 01 */ +#define CONFIG_FTSSP010_01_BASE 0xf0d00000 +#endif /* __AE3XX_H */ diff --git a/arch/nds32/include/asm/bootm.h b/arch/nds32/include/asm/bootm.h new file mode 100644 index 0000000000..6b10c078df --- /dev/null +++ b/arch/nds32/include/asm/bootm.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef NDS32_BOOTM_H +#define NDS32_BOOTM_H + +extern void udc_disconnect(void); + +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +# define BOOTM_ENABLE_TAGS 1 +#else +# define BOOTM_ENABLE_TAGS 0 +#endif + +#ifdef CONFIG_SETUP_MEMORY_TAGS +# define BOOTM_ENABLE_MEMORY_TAGS 1 +#else +# define BOOTM_ENABLE_MEMORY_TAGS 0 +#endif + +#ifdef CONFIG_CMDLINE_TAG + #define BOOTM_ENABLE_CMDLINE_TAG 1 +#else + #define BOOTM_ENABLE_CMDLINE_TAG 0 +#endif + +#ifdef CONFIG_INITRD_TAG + #define BOOTM_ENABLE_INITRD_TAG 1 +#else + #define BOOTM_ENABLE_INITRD_TAG 0 +#endif + +#ifdef CONFIG_SERIAL_TAG + #define BOOTM_ENABLE_SERIAL_TAG 1 +void get_board_serial(struct tag_serialnr *serialnr); +#else + #define BOOTM_ENABLE_SERIAL_TAG 0 +static inline void get_board_serial(struct tag_serialnr *serialnr) +{ +} +#endif + +#ifdef CONFIG_REVISION_TAG + #define BOOTM_ENABLE_REVISION_TAG 1 +u32 get_board_rev(void); +#else + #define BOOTM_ENABLE_REVISION_TAG 0 +static inline u32 get_board_rev(void) +{ + return 0; +} +#endif + +#endif diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h index 9038821b48..7e9aac80ff 100644 --- a/arch/nds32/include/asm/cache.h +++ b/arch/nds32/include/asm/cache.h @@ -16,6 +16,7 @@ void icache_disable(void); int dcache_status(void); void dcache_enable(void); void dcache_disable(void); +void cache_flush(void); #define DEFINE_GET_SYS_REG(reg) \ static inline unsigned long GET_##reg(void) \ @@ -30,10 +31,24 @@ void dcache_disable(void); enum cache_t {ICACHE, DCACHE}; DEFINE_GET_SYS_REG(ICM_CFG); DEFINE_GET_SYS_REG(DCM_CFG); -#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ -#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) -#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ -#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) +/* I-cache sets (# of cache lines) per way */ +#define ICM_CFG_OFF_ISET 0 +/* I-cache ways */ +#define ICM_CFG_OFF_IWAY 3 +#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET) +#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY) +/* D-cache sets (# of cache lines) per way */ +#define DCM_CFG_OFF_DSET 0 +/* D-cache ways */ +#define DCM_CFG_OFF_DWAY 3 +#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET) +#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY) +/* I-cache line size */ +#define ICM_CFG_OFF_ISZ 6 +#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) +/* D-cache line size */ +#define DCM_CFG_OFF_DSZ 6 +#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) /* * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h index 054cc4837c..7289217164 100644 --- a/arch/nds32/include/asm/config.h +++ b/arch/nds32/include/asm/config.h @@ -8,5 +8,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_LMB #endif diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index 1959d7eb0b..99904f9ed5 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -13,6 +13,7 @@ extern unsigned int __machine_arch_type; /* see arch/arm/kernel/arch.c for a description of these */ #define MACH_TYPE_ADPAG101P 1 +#define MACH_TYPE_ADPAE3XX 2 #ifdef CONFIG_ARCH_ADPAG101P # ifdef machine_arch_type diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile index 1a0d26f2e1..c88ad726bc 100644 --- a/arch/nds32/lib/Makefile +++ b/arch/nds32/lib/Makefile @@ -11,4 +11,5 @@ obj-y += cache.o obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_GO) += boot.o obj-y += interrupts.o diff --git a/arch/nds32/lib/boot.c b/arch/nds32/lib/boot.c new file mode 100644 index 0000000000..f9c1c6b3ff --- /dev/null +++ b/arch/nds32/lib/boot.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <command.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long do_go_exec(ulong (*entry)(int, char * const []), + int argc, char * const argv[]) +{ + cleanup_before_linux(); + + return entry(argc, argv); +} diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 8b0b28fd99..4c95a418a8 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -11,9 +11,16 @@ #include <image.h> #include <u-boot/zlib.h> #include <asm/byteorder.h> +#include <asm/bootm.h> DECLARE_GLOBAL_DATA_PTR; +int arch_fixup_fdt(void *blob) +{ + return 0; +} + + #if defined(CONFIG_SETUP_MEMORY_TAGS) || \ defined(CONFIG_CMDLINE_TAG) || \ defined(CONFIG_INITRD_TAG) || \ @@ -67,6 +74,15 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) debug("## Transferring control to Linux (at address %08lx) ...\n", (ulong)theKernel); + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { +#ifdef CONFIG_OF_LIBFDT + debug("using: FDT\n"); + if (image_setup_linux(images)) { + printf("FDT creation failed! hanging..."); + hang(); + } +#endif + } else if (BOOTM_ENABLE_TAGS) { #if defined(CONFIG_SETUP_MEMORY_TAGS) || \ defined(CONFIG_CMDLINE_TAG) || \ defined(CONFIG_INITRD_TAG) || \ @@ -101,16 +117,17 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) udc_disconnect(); } #endif - + } cleanup_before_linux(); - - theKernel(0, machid, bd->bi_boot_params); + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + theKernel(0, machid, (unsigned long)images->ft_addr); + else + theKernel(0, machid, bd->bi_boot_params); /* does not return */ return 1; } - #if defined(CONFIG_SETUP_MEMORY_TAGS) || \ defined(CONFIG_CMDLINE_TAG) || \ defined(CONFIG_INITRD_TAG) || \ @@ -130,7 +147,6 @@ static void setup_start_tag(bd_t *bd) params = tag_next(params); } - #ifdef CONFIG_SETUP_MEMORY_TAGS static void setup_memory_tags(bd_t *bd) { @@ -148,7 +164,6 @@ static void setup_memory_tags(bd_t *bd) } #endif /* CONFIG_SETUP_MEMORY_TAGS */ - static void setup_commandline_tag(bd_t *bd, char *commandline) { char *p; @@ -176,7 +191,6 @@ static void setup_commandline_tag(bd_t *bd, char *commandline) params = tag_next(params); } - #ifdef CONFIG_INITRD_TAG static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end) { @@ -224,7 +238,6 @@ void setup_revision_tag(struct tag **in_params) } #endif /* CONFIG_REVISION_TAG */ - static void setup_end_tag(bd_t *bd) { params->hdr.tag = ATAG_NONE; diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c index 866dc1a98a..846948167f 100644 --- a/arch/nds32/lib/cache.c +++ b/arch/nds32/lib/cache.c @@ -7,32 +7,56 @@ */ #include <common.h> +#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +static inline unsigned long CACHE_SET(unsigned char cache) +{ + if (cache == ICACHE) + return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \ + >> ICM_CFG_OFF_ISET); + else + return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \ + >> DCM_CFG_OFF_DSET); +} + +static inline unsigned long CACHE_WAY(unsigned char cache) +{ + if (cache == ICACHE) + return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \ + >> ICM_CFG_OFF_IWAY); + else + return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \ + >> DCM_CFG_OFF_DWAY); +} static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) { if (cache == ICACHE) return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ - >> ICM_CFG_OFF_ISZ) - 1); + >> ICM_CFG_OFF_ISZ) - 1); else return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ - >> DCM_CFG_OFF_DSZ) - 1); + >> DCM_CFG_OFF_DSZ) - 1); } +#endif -void flush_dcache_range(unsigned long start, unsigned long end) +#ifndef CONFIG_SYS_ICACHE_OFF +void invalidate_icache_all(void) { - unsigned long line_size; + unsigned long end, line_size; + line_size = CACHE_LINE_SIZE(ICACHE); + end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE); + do { + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); - line_size = CACHE_LINE_SIZE(DCACHE); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); - while (end > start) { - asm volatile ( - "\n\tcctl %0, L1D_VA_WB" - "\n\tcctl %0, L1D_VA_INVAL" - : - : "r" (start) - ); - start += line_size; - } + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); + } while (end > 0); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -50,27 +74,6 @@ void invalidate_icache_range(unsigned long start, unsigned long end) } } -void invalidate_dcache_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(DCACHE); - while (end > start) { - asm volatile ( - "\n\tcctl %0, L1D_VA_INVAL" - : - : "r"(start) - ); - start += line_size; - } -} - -void flush_cache(unsigned long addr, unsigned long size) -{ - flush_dcache_range(addr, addr + size); - invalidate_icache_range(addr, addr + size); -} - void icache_enable(void) { asm volatile ( @@ -107,6 +110,81 @@ int icache_status(void) return ret; } +#else +void invalidate_icache_all(void) +{ +} + +void invalidate_icache_range(unsigned long start, unsigned long end) +{ +} + +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 0; +} + +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void dcache_wbinval_all(void) +{ + unsigned long end, line_size; + line_size = CACHE_LINE_SIZE(DCACHE); + end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE); + do { + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + + } while (end > 0); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_WB" + "\n\tcctl %0, L1D_VA_INVAL" : : "r" (start) + ); + start += line_size; + } +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_INVAL" : : "r"(start) + ); + start += line_size; + } +} + void dcache_enable(void) { asm volatile ( @@ -131,7 +209,6 @@ void dcache_disable(void) int dcache_status(void) { int ret; - asm volatile ( "mfsr $p0, $mr8\n\t" "andi %0, $p0, 0x02\n\t" @@ -139,6 +216,52 @@ int dcache_status(void) : : "memory" ); - return ret; } + +#else +void dcache_wbinval_all(void) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} + +#endif + + +void flush_dcache_all(void) +{ + dcache_wbinval_all(); +} + +void cache_flush(void) +{ + flush_dcache_all(); + invalidate_icache_all(); +} + + +void flush_cache(unsigned long addr, unsigned long size) +{ + flush_dcache_range(addr, addr + size); + invalidate_icache_range(addr, addr + size); +} diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 0033c35261..f37a9cbffb 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -32,6 +32,9 @@ config MPC85xx select CREATE_ARCH_SYMLINK select SYS_FSL_DDR select SYS_FSL_DDR_BE + imply USB_EHCI_HCD if USB + imply CMD_HASH + imply CMD_IRQ config MPC86xx bool "MPC86xx" @@ -44,9 +47,12 @@ config 8xx config 4xx bool "PPC4xx" select CREATE_ARCH_SYMLINK + imply CMD_IRQ endchoice +source "arch/powerpc/lib/Kconfig" + source "arch/powerpc/cpu/mpc512x/Kconfig" source "arch/powerpc/cpu/mpc5xx/Kconfig" source "arch/powerpc/cpu/mpc5xxx/Kconfig" diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index 98991c688b..933deebdae 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -9,7 +9,6 @@ obj-y := cpu.o obj-y += traps.o obj-y += cpu_init.o obj-y += fixed_sdram.o -obj-y += i2c.o obj-y += interrupts.o obj-y += iopin.o obj-y += serial.o diff --git a/arch/powerpc/cpu/mpc512x/i2c.c b/arch/powerpc/cpu/mpc512x/i2c.c deleted file mode 100644 index 15d519a116..0000000000 --- a/arch/powerpc/cpu/mpc512x/i2c.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2003 - 2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Based on the MPC5xxx code. - */ - -#include <common.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_HARD_I2C - -#include <i2c.h> - -/* by default set I2C bus 0 active */ -static unsigned int bus_num __attribute__ ((section (".data"))) = 0; - -#define I2C_TIMEOUT 100 -#define I2C_RETRIES 3 - -struct mpc512x_i2c_tap { - int scl2tap; - int tap2tap; -}; - -static int mpc_reg_in(volatile u32 *reg); -static void mpc_reg_out(volatile u32 *reg, int val, int mask); -static int wait_for_bb(void); -static int wait_for_pin(int *status); -static int do_address(uchar chip, char rdwr_flag); -static int send_bytes(uchar chip, char *buf, int len); -static int receive_bytes(uchar chip, char *buf, int len); -static int mpc_get_fdr(int); - -static int mpc_reg_in (volatile u32 *reg) -{ - int ret = in_be32(reg) >> 24; - - return ret; -} - -static void mpc_reg_out (volatile u32 *reg, int val, int mask) -{ - if (!mask) { - out_be32(reg, val << 24); - } else { - clrsetbits_be32(reg, mask << 24, (val & mask) << 24); - } -} - -static int wait_for_bb (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - int timeout = I2C_TIMEOUT; - int status; - - status = mpc_reg_in (®s->msr); - - while (timeout-- && (status & I2C_BB)) { - mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); - (void)mpc_reg_in(®s->mdr); - mpc_reg_out (®s->mcr, 0, I2C_STA); - mpc_reg_out (®s->mcr, 0, 0); - mpc_reg_out (®s->mcr, I2C_EN, 0); - - udelay (1000); - status = mpc_reg_in (®s->msr); - } - - return (status & I2C_BB); -} - -static int wait_for_pin (int *status) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - int timeout = I2C_TIMEOUT; - - *status = mpc_reg_in (®s->msr); - - while (timeout-- && !(*status & I2C_IF)) { - udelay (1000); - *status = mpc_reg_in (®s->msr); - } - - if (!(*status & I2C_IF)) { - return -1; - } - - mpc_reg_out (®s->msr, 0, I2C_IF); - - return 0; -} - -static int do_address (uchar chip, char rdwr_flag) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - int status; - - chip <<= 1; - - if (rdwr_flag) { - chip |= 1; - } - - mpc_reg_out (®s->mcr, I2C_TX, I2C_TX); - mpc_reg_out (®s->mdr, chip, 0); - - if (wait_for_pin (&status)) { - return -2; - } - - if (status & I2C_RXAK) { - return -3; - } - - return 0; -} - -static int send_bytes (uchar chip, char *buf, int len) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - int wrcount; - int status; - - for (wrcount = 0; wrcount < len; ++wrcount) { - - mpc_reg_out (®s->mdr, buf[wrcount], 0); - - if (wait_for_pin (&status)) { - break; - } - - if (status & I2C_RXAK) { - break; - } - - } - - return !(wrcount == len); -} - -static int receive_bytes (uchar chip, char *buf, int len) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - int dummy = 1; - int rdcount = 0; - int status; - int i; - - mpc_reg_out (®s->mcr, 0, I2C_TX); - - for (i = 0; i < len; ++i) { - buf[rdcount] = mpc_reg_in (®s->mdr); - - if (dummy) { - dummy = 0; - } else { - rdcount++; - } - - if (wait_for_pin (&status)) { - return -4; - } - } - - mpc_reg_out (®s->mcr, I2C_TXAK, I2C_TXAK); - buf[rdcount++] = mpc_reg_in (®s->mdr); - - if (wait_for_pin (&status)) { - return -5; - } - - mpc_reg_out (®s->mcr, 0, I2C_TXAK); - - return 0; -} - -/**************** I2C API ****************/ - -void i2c_init (int speed, int saddr) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - int i; - - for (i = 0; i < I2C_BUS_CNT; i++){ - volatile i2c512x_dev_t *regs = &im->i2c.dev[i]; - - mpc_reg_out (®s->mcr, 0, 0); - - /* Set clock */ - mpc_reg_out (®s->mfdr, mpc_get_fdr (speed), 0); - mpc_reg_out (®s->madr, saddr << 1, 0); - - /* Enable module */ - mpc_reg_out (®s->mcr, I2C_EN, I2C_INIT_MASK); - mpc_reg_out (®s->msr, 0, I2C_IF); - } - - /* Disable interrupts */ - out_be32(&im->i2c.icr, 0); - - /* Turn off filters */ - out_be32(&im->i2c.mifr, 0); -} - -static int mpc_get_fdr (int speed) -{ - static int fdr = -1; - - if (fdr == -1) { - ulong best_speed = 0; - ulong divider; - ulong ips, scl; - ulong bestmatch = 0xffffffffUL; - int best_i = 0, best_j = 0, i, j; - int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; - struct mpc512x_i2c_tap scltap[] = { - {4, 1}, - {4, 2}, - {6, 4}, - {6, 8}, - {14, 16}, - {30, 32}, - {62, 64}, - {126, 128} - }; - - ips = gd->arch.ips_clk; - for (i = 7; i >= 0; i--) { - for (j = 7; j >= 0; j--) { - scl = 2 * (scltap[j].scl2tap + - (SCL_Tap[i] - 1) * scltap[j].tap2tap - + 2); - if (ips <= speed*scl) { - if ((speed*scl - ips) < bestmatch) { - bestmatch = speed*scl - ips; - best_i = i; - best_j = j; - best_speed = ips/scl; - } - } - } - } - divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); - if (gd->flags & GD_FLG_RELOC) { - fdr = divider; - } else { - debug("%ld kHz, \n", best_speed / 1000); - return divider; - } - } - - return fdr; -} - -int i2c_probe (uchar chip) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - int i; - - for (i = 0; i < I2C_RETRIES; i++) { - mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); - - if (! do_address (chip, 0)) { - mpc_reg_out (®s->mcr, 0, I2C_STA); - udelay (500); - break; - } - - mpc_reg_out (®s->mcr, 0, I2C_STA); - udelay (500); - } - - return (i == I2C_RETRIES); -} - -int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - char xaddr[4]; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb ()) { - printf ("i2c_read: bus is busy\n"); - goto Done; - } - - mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); - if (do_address (chip, 0)) { - printf ("i2c_read: failed to address chip\n"); - goto Done; - } - - if (send_bytes (chip, &xaddr[4-alen], alen)) { - printf ("i2c_read: send_bytes failed\n"); - goto Done; - } - - mpc_reg_out (®s->mcr, I2C_RSTA, I2C_RSTA); - if (do_address (chip, 1)) { - printf ("i2c_read: failed to address chip\n"); - goto Done; - } - - if (receive_bytes (chip, (char *)buf, len)) { - printf ("i2c_read: receive_bytes failed\n"); - goto Done; - } - - ret = 0; -Done: - mpc_reg_out (®s->mcr, 0, I2C_STA); - return ret; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; - char xaddr[4]; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb ()) { - printf ("i2c_write: bus is busy\n"); - goto Done; - } - - mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); - if (do_address (chip, 0)) { - printf ("i2c_write: failed to address chip\n"); - goto Done; - } - - if (send_bytes (chip, &xaddr[4-alen], alen)) { - printf ("i2c_write: send_bytes failed\n"); - goto Done; - } - - if (send_bytes (chip, (char *)buf, len)) { - printf ("i2c_write: send_bytes failed\n"); - goto Done; - } - - ret = 0; -Done: - mpc_reg_out (®s->mcr, 0, I2C_STA); - return ret; -} - -int i2c_set_bus_num (unsigned int bus) -{ - if (bus >= I2C_BUS_CNT) { - return -1; - } - bus_num = bus; - - return 0; -} - -unsigned int i2c_get_bus_num (void) -{ - return bus_num; -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index 5d4922870b..6ba0dd492d 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -59,6 +59,7 @@ config TARGET_O3DNT config TARGET_DIGSY_MTC bool "Support digsy_mtc" + imply CMD_IRQ config TARGET_PCM030 bool "Support pcm030" diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile index 5c67e1d37d..88e3b2e3ae 100644 --- a/arch/powerpc/cpu/mpc5xxx/Makefile +++ b/arch/powerpc/cpu/mpc5xxx/Makefile @@ -9,7 +9,6 @@ extra-y = start.o extra-y += traps.o obj-y += io.o obj-y += firmware_sc_task_bestcomm.impl.o -obj-y += i2c.o obj-y += cpu.o obj-y += cpu_init.o obj-y += ide.o diff --git a/arch/powerpc/cpu/mpc5xxx/i2c.c b/arch/powerpc/cpu/mpc5xxx/i2c.c deleted file mode 100644 index 73601ae184..0000000000 --- a/arch/powerpc/cpu/mpc5xxx/i2c.c +++ /dev/null @@ -1,456 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_HARD_I2C - -#include <mpc5xxx.h> -#include <i2c.h> - -#if !defined(CONFIG_I2C_MULTI_BUS) -#if (CONFIG_SYS_I2C_MODULE == 2) -#define I2C_BASE MPC5XXX_I2C2 -#elif (CONFIG_SYS_I2C_MODULE == 1) -#define I2C_BASE MPC5XXX_I2C1 -#else -#error CONFIG_SYS_I2C_MODULE is not properly configured -#endif -#else -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = - CONFIG_SYS_SPD_BUS_NUM; -static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, - CONFIG_SYS_I2C_SPEED}; - -static const unsigned long i2c_dev[2] = { - MPC5XXX_I2C1, - MPC5XXX_I2C2, -}; - -#define I2C_BASE ((struct mpc5xxx_i2c *)i2c_dev[i2c_bus_num]) -#endif - -#define I2C_TIMEOUT 6667 -#define I2C_RETRIES 3 - -struct mpc5xxx_i2c_tap { - int scl2tap; - int tap2tap; -}; - -static int mpc_reg_in (volatile u32 *reg); -static void mpc_reg_out (volatile u32 *reg, int val, int mask); -static int wait_for_bb (void); -static int wait_for_pin (int *status); -static int do_address (uchar chip, char rdwr_flag); -static int send_bytes (uchar chip, char *buf, int len); -static int receive_bytes (uchar chip, char *buf, int len); -static int mpc_get_fdr (int); - -static int mpc_reg_in(volatile u32 *reg) -{ - int ret = *reg >> 24; - __asm__ __volatile__ ("eieio"); - return ret; -} - -static void mpc_reg_out(volatile u32 *reg, int val, int mask) -{ - int tmp; - - if (!mask) { - *reg = val << 24; - } else { - tmp = mpc_reg_in(reg); - *reg = ((tmp & ~mask) | (val & mask)) << 24; - } - __asm__ __volatile__ ("eieio"); - - return; -} - -static int wait_for_bb(void) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int timeout = I2C_TIMEOUT; - int status; - - status = mpc_reg_in(®s->msr); - - while (timeout-- && (status & I2C_BB)) { - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - (void)mpc_reg_in(®s->mdr); - mpc_reg_out(®s->mcr, 0, I2C_STA); - mpc_reg_out(®s->mcr, 0, 0); - mpc_reg_out(®s->mcr, I2C_EN, 0); - udelay(15); - status = mpc_reg_in(®s->msr); - } - - return (status & I2C_BB); -} - -static int wait_for_pin(int *status) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int timeout = I2C_TIMEOUT; - - *status = mpc_reg_in(®s->msr); - - while (timeout-- && !(*status & I2C_IF)) { - udelay(15); - *status = mpc_reg_in(®s->msr); - } - - if (!(*status & I2C_IF)) { - return -1; - } - - mpc_reg_out(®s->msr, 0, I2C_IF); - - return 0; -} - -static int do_address(uchar chip, char rdwr_flag) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int status; - - chip <<= 1; - - if (rdwr_flag) { - chip |= 1; - } - - mpc_reg_out(®s->mcr, I2C_TX, I2C_TX); - mpc_reg_out(®s->mdr, chip, 0); - - if (wait_for_pin(&status)) { - return -2; - } - - if (status & I2C_RXAK) { - return -3; - } - - return 0; -} - -static int send_bytes(uchar chip, char *buf, int len) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int wrcount; - int status; - - for (wrcount = 0; wrcount < len; ++wrcount) { - - mpc_reg_out(®s->mdr, buf[wrcount], 0); - - if (wait_for_pin(&status)) { - break; - } - - if (status & I2C_RXAK) { - break; - } - - } - - return !(wrcount == len); -} - -static int receive_bytes(uchar chip, char *buf, int len) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int dummy = 1; - int rdcount = 0; - int status; - int i; - - mpc_reg_out(®s->mcr, 0, I2C_TX); - - for (i = 0; i < len; ++i) { - buf[rdcount] = mpc_reg_in(®s->mdr); - - if (dummy) { - dummy = 0; - } else { - rdcount++; - } - - - if (wait_for_pin(&status)) { - return -4; - } - } - - mpc_reg_out(®s->mcr, I2C_TXAK, I2C_TXAK); - buf[rdcount++] = mpc_reg_in(®s->mdr); - - if (wait_for_pin(&status)) { - return -5; - } - - mpc_reg_out(®s->mcr, 0, I2C_TXAK); - - return 0; -} - -#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) - -#define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3)) -#define FDR432(x) (u8) ((x & 0x1C) >> 2) -/* - * Reset any i2c devices that may have been interrupted during a system reset. - * Normally this would be accomplished by clocking the line until SCL and SDA - * are released and then sending a start condtiion (From an Atmel datasheet). - * There is no direct access to the i2c pins so instead create start commands - * through the i2c interface. Send a start command then delay for the SDA Hold - * time, repeat this by disabling/enabling the bus a total of 9 times. - */ -static void send_reset(void) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int i; - u32 delay; - u8 fdr; - int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2}; - struct mpc5xxx_i2c_tap scltap[] = { - {4, 1}, - {4, 2}, - {6, 4}, - {6, 8}, - {14, 16}, - {30, 32}, - {62, 64}, - {126, 128} - }; - - fdr = (u8)mpc_reg_in(®s->mfdr); - - delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \ - scltap[FDR432(fdr)].tap2tap) + 3; - - for (i = 0; i < 9; i++) { - mpc_reg_out(®s->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK); - udelay(delay); - mpc_reg_out(®s->mcr, 0, I2C_INIT_MASK); - udelay(delay); - } - - mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); -} -#endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */ - -/**************** I2C API ****************/ - -void i2c_init(int speed, int saddr) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - - mpc_reg_out(®s->mcr, 0, 0); - mpc_reg_out(®s->madr, saddr << 1, 0); - - /* Set clock - */ - mpc_reg_out(®s->mfdr, mpc_get_fdr(speed), 0); - - /* Enable module - */ - mpc_reg_out(®s->mcr, I2C_EN, I2C_INIT_MASK); - mpc_reg_out(®s->msr, 0, I2C_IF); - -#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) - send_reset(); -#endif - return; -} - -static int mpc_get_fdr(int speed) -{ - static int fdr = -1; - - if (fdr == -1) { - ulong best_speed = 0; - ulong divider; - ulong ipb, scl; - ulong bestmatch = 0xffffffffUL; - int best_i = 0, best_j = 0, i, j; - int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; - struct mpc5xxx_i2c_tap scltap[] = { - {4, 1}, - {4, 2}, - {6, 4}, - {6, 8}, - {14, 16}, - {30, 32}, - {62, 64}, - {126, 128} - }; - - ipb = gd->arch.ipb_clk; - for (i = 7; i >= 0; i--) { - for (j = 7; j >= 0; j--) { - scl = 2 * (scltap[j].scl2tap + - (SCL_Tap[i] - 1) * scltap[j].tap2tap + 2); - if (ipb <= speed*scl) { - if ((speed*scl - ipb) < bestmatch) { - bestmatch = speed*scl - ipb; - best_i = i; - best_j = j; - best_speed = ipb/scl; - } - } - } - } - divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); - if (gd->flags & GD_FLG_RELOC) { - fdr = divider; - } else { - printf("%ld kHz, ", best_speed / 1000); - return divider; - } - } - - return fdr; -} - -int i2c_probe(uchar chip) -{ - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int i; - - for (i = 0; i < I2C_RETRIES; i++) { - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - - if (! do_address(chip, 0)) { - mpc_reg_out(®s->mcr, 0, I2C_STA); - udelay(500); - break; - } - - mpc_reg_out(®s->mcr, 0, I2C_STA); - udelay(500); - } - - return (i == I2C_RETRIES); -} - -int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - char xaddr[4]; - struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb()) { - printf("i2c_read: bus is busy\n"); - goto Done; - } - - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - if (do_address(chip, 0)) { - printf("i2c_read: failed to address chip\n"); - goto Done; - } - - if (send_bytes(chip, &xaddr[4-alen], alen)) { - printf("i2c_read: send_bytes failed\n"); - goto Done; - } - - mpc_reg_out(®s->mcr, I2C_RSTA, I2C_RSTA); - if (do_address(chip, 1)) { - printf("i2c_read: failed to address chip\n"); - goto Done; - } - - if (receive_bytes(chip, (char *)buf, len)) { - printf("i2c_read: receive_bytes failed\n"); - goto Done; - } - - ret = 0; -Done: - mpc_reg_out(®s->mcr, 0, I2C_STA); - return ret; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - char xaddr[4]; - struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; - int ret = -1; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - - if (wait_for_bb()) { - printf("i2c_write: bus is busy\n"); - goto Done; - } - - mpc_reg_out(®s->mcr, I2C_STA, I2C_STA); - if (do_address(chip, 0)) { - printf("i2c_write: failed to address chip\n"); - goto Done; - } - - if (send_bytes(chip, &xaddr[4-alen], alen)) { - printf("i2c_write: send_bytes failed\n"); - goto Done; - } - - if (send_bytes(chip, (char *)buf, len)) { - printf("i2c_write: send_bytes failed\n"); - goto Done; - } - - ret = 0; -Done: - mpc_reg_out(®s->mcr, 0, I2C_STA); - return ret; -} - -#if defined(CONFIG_I2C_MULTI_BUS) -int i2c_set_bus_num(unsigned int bus) -{ - if (bus > 1) - return -1; - - i2c_bus_num = bus; - i2c_init(i2c_bus_speed[bus], CONFIG_SYS_I2C_SLAVE); - return 0; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - i2c_init(speed, CONFIG_SYS_I2C_SLAVE); - return 0; -} - -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -unsigned int i2c_get_bus_speed(void) -{ - return i2c_bus_speed[i2c_bus_num]; -} -#endif - - -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c index 9003b774ff..d1f4349184 100644 --- a/arch/powerpc/cpu/mpc5xxx/ide.c +++ b/arch/powerpc/cpu/mpc5xxx/ide.c @@ -8,7 +8,7 @@ */ #include <common.h> -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) #include <mpc5xxx.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8260/Makefile b/arch/powerpc/cpu/mpc8260/Makefile index 83adc4c436..72dd8aba25 100644 --- a/arch/powerpc/cpu/mpc8260/Makefile +++ b/arch/powerpc/cpu/mpc8260/Makefile @@ -7,7 +7,7 @@ extra-y = start.o obj-y = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ - interrupts.o ether_fcc.o i2c.o commproc.o \ + interrupts.o ether_fcc.o commproc.o \ bedbug_603e.o pci.o spi.o kgdb.o obj-$(CONFIG_ETHER_ON_SCC) += ether_scc.o diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c index 484bd17745..ff69881089 100644 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ b/arch/powerpc/cpu/mpc8260/commproc.c @@ -41,10 +41,6 @@ m8260_cpm_reset(void) do { /* Spin until command processed */ __asm__ __volatile__ ("eieio"); } while ((immr->im_cpm.cp_cpcr & CPM_CR_FLG) && ++count < 1000000); - -#ifdef CONFIG_HARD_I2C - immr->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] = 0; -#endif } /* Allocate some memory from the dual ported ram. diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c deleted file mode 100644 index a0de101329..0000000000 --- a/arch/powerpc/cpu/mpc8260/i2c.c +++ /dev/null @@ -1,741 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <console.h> - -#if defined(CONFIG_HARD_I2C) - -#include <asm/cpm_8260.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_I2C_MULTI_BUS) -static unsigned int i2c_bus_num __attribute__ ((section(".data"))) = 0; -#endif /* CONFIG_I2C_MULTI_BUS */ - -/* uSec to wait between polls of the i2c */ -#define DELAY_US 100 -/* uSec to wait for the CPM to start processing the buffer */ -#define START_DELAY_US 1000 - -/* - * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the - * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP - */ -#define TOUT_LOOP 5 - -/* - * Set default values - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif - - -typedef void (*i2c_ecb_t) (int, int, void *); /* error callback function */ - -/* This structure keeps track of the bd and buffer space usage. */ -typedef struct i2c_state { - int rx_idx; /* index to next free Rx BD */ - int tx_idx; /* index to next free Tx BD */ - void *rxbd; /* pointer to next free Rx BD */ - void *txbd; /* pointer to next free Tx BD */ - int tx_space; /* number of Tx bytes left */ - unsigned char *tx_buf; /* pointer to free Tx area */ - i2c_ecb_t err_cb; /* error callback function */ - void *cb_data; /* private data to be passed */ -} i2c_state_t; - -/* flags for i2c_send() and i2c_receive() */ -#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ -#define I2CF_START_COND 0x02 /* tx: generate start condition */ -#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ - -/* return codes */ -#define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */ -#define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */ -#define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */ -#define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/rcv */ -#define I2CERR_IO_ERROR 5 /* had an error during comms */ - -/* error callback flags */ -#define I2CECB_RX_ERR 0x10 /* this is a receive error */ -#define I2CECB_RX_OV 0x02 /* receive overrun error */ -#define I2CECB_RX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ -#define I2CECB_TX_CL 0x01 /* transmit collision error */ -#define I2CECB_TX_UN 0x02 /* transmit underflow error */ -#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ -#define I2CECB_TX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ - -#define ERROR_I2C_NONE 0 -#define ERROR_I2C_LENGTH 1 - -#define I2C_WRITE_BIT 0x00 -#define I2C_READ_BIT 0x01 - -#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ - - -#define NUM_RX_BDS 4 -#define NUM_TX_BDS 4 -#define MAX_TX_SPACE 256 - -typedef struct I2C_BD { - unsigned short status; - unsigned short length; - unsigned char *addr; -} I2C_BD; - -#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ - -#define BD_I2C_TX_CL 0x0001 /* collision error */ -#define BD_I2C_TX_UN 0x0002 /* underflow error */ -#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */ -#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL) - -#define BD_I2C_RX_ERR BD_SC_OV - -/* - * Returns the best value of I2BRG to meet desired clock speed of I2C with - * input parameters (clock speed, filter, and predivider value). - * It returns computer speed value and the difference between it and desired - * speed. - */ -static inline int -i2c_roundrate(int hz, int speed, int filter, int modval, - int *brgval, int *totspeed) -{ - int moddiv = 1 << (5 - (modval & 3)), brgdiv, div; - - debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", - hz, speed, filter, modval); - - div = moddiv * speed; - brgdiv = (hz + div - 1) / div; - - debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv); - - *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter); - - if ((*brgval < 0) || (*brgval > 255)) { - debug("\t\trejected brgval=%d\n", *brgval); - return -1; - } - - brgdiv = 2 * (*brgval + 3 + (2 * filter)); - div = moddiv * brgdiv; - *totspeed = hz / div; - - debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed); - - return 0; -} - -/* - * Sets the I2C clock predivider and divider to meet required clock speed. - */ -static int i2c_setrate(int hz, int speed) -{ - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - int brgval, - modval, /* 0-3 */ - bestspeed_diff = speed, - bestspeed_brgval = 0, - bestspeed_modval = 0, - bestspeed_filter = 0, - totspeed, - filter = 0; /* Use this fixed value */ - - for (modval = 0; modval < 4; modval++) { - if (i2c_roundrate(hz, speed, filter, modval, &brgval, &totspeed) - == 0) { - int diff = speed - totspeed; - - if ((diff >= 0) && (diff < bestspeed_diff)) { - bestspeed_diff = diff; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; - } - } - } - - debug("[I2C] Best is:\n"); - debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", - hz, speed, bestspeed_filter, bestspeed_modval, bestspeed_brgval, - bestspeed_diff); - - i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | - (bestspeed_filter << 3); - i2c->i2c_i2brg = bestspeed_brgval & 0xff; - - debug("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, - i2c->i2c_i2brg); - - return 1; -} - -void i2c_init(int speed, int slaveadd) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - volatile iic_t *iip; - ulong rbase, tbase; - volatile I2C_BD *rxbd, *txbd; - uint dpaddr; - -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* - * call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif - - dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)]; - if (dpaddr == 0) { - /* need to allocate dual port ram */ - dpaddr = m8260_cpm_dpalloc(64 + - (NUM_RX_BDS * sizeof(I2C_BD)) + - (NUM_TX_BDS * sizeof(I2C_BD)) + - MAX_TX_SPACE, 64); - immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)] = - dpaddr; - } - - /* - * initialise data in dual port ram: - * - * dpaddr -> parameter ram (64 bytes) - * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) - * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) - * tx buffer (MAX_TX_SPACE bytes) - */ - - iip = (iic_t *)&immap->im_dprambase[dpaddr]; - memset((void *)iip, 0, sizeof(iic_t)); - - rbase = dpaddr + 64; - tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); - - /* Disable interrupts */ - i2c->i2c_i2mod = 0x00; - i2c->i2c_i2cmr = 0x00; - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2add = slaveadd; - - /* - * Set the I2C BRG Clock division factor from desired i2c rate - * and current CPU rate (we assume sccr dfbgr field is 0; - * divide BRGCLK by 1) - */ - debug("[I2C] Setting rate...\n"); - i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED); - - /* Set I2C controller in master mode */ - i2c->i2c_i2com = 0x01; - - /* Initialize Tx/Rx parameters */ - iip->iic_rbase = rbase; - iip->iic_tbase = tbase; - rxbd = (I2C_BD *)((unsigned char *) &immap-> - im_dprambase[iip->iic_rbase]); - txbd = (I2C_BD *)((unsigned char *) &immap-> - im_dprambase[iip->iic_tbase]); - - debug("[I2C] rbase = %04x\n", iip->iic_rbase); - debug("[I2C] tbase = %04x\n", iip->iic_tbase); - debug("[I2C] rxbd = %08x\n", (int) rxbd); - debug("[I2C] txbd = %08x\n", (int) txbd); - - /* Set big endian byte order */ - iip->iic_tfcr = 0x10; - iip->iic_rfcr = 0x10; - - /* Set maximum receive size. */ - iip->iic_mrblr = I2C_RXTX_LEN; - - cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE, - CPM_CR_I2C_SBLOCK, - 0x00, CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); - - /* Clear events and interrupts */ - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2cmr = 0x00; -} - -static -void i2c_newio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile iic_t *iip; - uint dpaddr; - - debug("[I2C] i2c_newio\n"); - - dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)]; - iip = (iic_t *)&immap->im_dprambase[dpaddr]; - state->rx_idx = 0; - state->tx_idx = 0; - state->rxbd = (void *)&immap->im_dprambase[iip->iic_rbase]; - state->txbd = (void *)&immap->im_dprambase[iip->iic_tbase]; - state->tx_space = MAX_TX_SPACE; - state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); - state->err_cb = NULL; - state->cb_data = NULL; - - debug("[I2C] rxbd = %08x\n", (int)state->rxbd); - debug("[I2C] txbd = %08x\n", (int)state->txbd); - debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf); - - /* clear the buffer memory */ - memset((char *) state->tx_buf, 0, MAX_TX_SPACE); -} - -static -int i2c_send(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, unsigned short size, unsigned char *dataout) -{ - volatile I2C_BD *txbd; - int i, j; - - debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", - address, secondary_address, flags, size); - - /* trying to send message larger than BD */ - if (size > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) - return I2CERR_NO_BUFFERS; - - txbd = (I2C_BD *)state->txbd; - txbd->addr = state->tx_buf; - - debug("[I2C] txbd = %08x\n", (int) txbd); - - if (flags & I2CF_START_COND) { - debug("[I2C] Formatting addresses...\n"); - if (flags & I2CF_ENABLE_SECONDARY) { - /* Length of message plus dest addresses */ - txbd->length = size + 2; - txbd->addr[0] = address << 1; - txbd->addr[1] = secondary_address; - i = 2; - } else { - /* Length of message plus dest address */ - txbd->length = size + 1; - /* Write destination address to BD */ - txbd->addr[0] = address << 1; - i = 1; - } - } else { - txbd->length = size; /* Length of message */ - i = 0; - } - - /* set up txbd */ - txbd->status = BD_SC_READY; - if (flags & I2CF_START_COND) - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - - /* Copy data to send into buffer */ - debug("[I2C] copy data...\n"); - for (j = 0; j < size; i++, j++) - txbd->addr[i] = dataout[j]; - - debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void *) (txbd + 1); - - return 0; -} - -static -int i2c_receive(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size_to_expect, unsigned char *datain) -{ - volatile I2C_BD *rxbd, *txbd; - - debug("[I2C] i2c_receive %02d %02d %02d\n", address, - secondary_address, flags); - - /* Expected to receive too much */ - if (size_to_expect > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS - || state->tx_space < 2) - return I2CERR_NO_BUFFERS; - - rxbd = (I2C_BD *) state->rxbd; - txbd = (I2C_BD *) state->txbd; - - debug("[I2C] rxbd = %08x\n", (int) rxbd); - debug("[I2C] txbd = %08x\n", (int) txbd); - - txbd->addr = state->tx_buf; - - /* set up TXBD for destination address */ - if (flags & I2CF_ENABLE_SECONDARY) { - txbd->length = 2; - txbd->addr[0] = address << 1; /* Write data */ - txbd->addr[1] = secondary_address; /* Internal address */ - txbd->status = BD_SC_READY; - } else { - txbd->length = 1 + size_to_expect; - txbd->addr[0] = (address << 1) | 0x01; - txbd->status = BD_SC_READY; - memset(&txbd->addr[1], 0, txbd->length); - } - - /* set up rxbd for reception */ - rxbd->status = BD_SC_EMPTY; - rxbd->length = size_to_expect; - rxbd->addr = datain; - - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) { - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - rxbd->status |= BD_SC_WRAP; - } - - debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, txbd->status, txbd->addr[0], txbd->addr[1]); - debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - rxbd->length, rxbd->status, rxbd->addr[0], rxbd->addr[1]); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void *) (txbd + 1); - state->rx_idx++; - state->rxbd = (void *) (rxbd + 1); - - return 0; -} - - -static -int i2c_doio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile iic_t *iip; - volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; - volatile I2C_BD *txbd, *rxbd; - int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0; - uint dpaddr; - - debug("[I2C] i2c_doio\n"); - - if (state->tx_idx <= 0 && state->rx_idx <= 0) { - debug("[I2C] No I/O is queued\n"); - return I2CERR_QUEUE_EMPTY; - } - - dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)]; - iip = (iic_t *)&immap->im_dprambase[dpaddr]; - iip->iic_rbptr = iip->iic_rbase; - iip->iic_tbptr = iip->iic_tbase; - - /* Enable I2C */ - debug("[I2C] Enabling I2C...\n"); - i2c->i2c_i2mod |= 0x01; - - /* Begin transmission */ - i2c->i2c_i2com |= 0x80; - - /* Loop until transmit & receive completed */ - - n = state->tx_idx; - - if (n > 0) { - - txbd = ((I2C_BD *) state->txbd) - n; - for (i = 0; i < n; i++) { - txtimeo += TOUT_LOOP * txbd->length; - txbd++; - } - - txbd--; /* wait until last in list is done */ - - debug("[I2C] Transmitting...(txbd=0x%08lx)\n", - (ulong) txbd); - - udelay(START_DELAY_US); /* give it time to start */ - while ((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) { - udelay(DELAY_US); - if (ctrlc()) - return -1; - __asm__ __volatile__("eieio"); - } - } - - n = state->rx_idx; - - if (txcnt < txtimeo && n > 0) { - - rxbd = ((I2C_BD *) state->rxbd) - n; - for (i = 0; i < n; i++) { - rxtimeo += TOUT_LOOP * rxbd->length; - rxbd++; - } - - rxbd--; /* wait until last in list is done */ - - debug("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong) rxbd); - - udelay(START_DELAY_US); /* give it time to start */ - while ((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) { - udelay(DELAY_US); - if (ctrlc()) - return -1; - __asm__ __volatile__("eieio"); - } - } - - /* Turn off I2C */ - i2c->i2c_i2mod &= ~0x01; - - n = state->tx_idx; - - if (n > 0) { - for (i = 0; i < n; i++) { - txbd = ((I2C_BD *) state->txbd) - (n - i); - b = txbd->status & BD_I2C_TX_ERR; - if (b != 0) { - if (state->err_cb != NULL) - (*state->err_cb) (I2CECB_TX_ERR | b, - i, state->cb_data); - if (rc == 0) - rc = I2CERR_IO_ERROR; - } - } - } - - n = state->rx_idx; - - if (n > 0) { - for (i = 0; i < n; i++) { - rxbd = ((I2C_BD *) state->rxbd) - (n - i); - b = rxbd->status & BD_I2C_RX_ERR; - if (b != 0) { - if (state->err_cb != NULL) - (*state->err_cb) (I2CECB_RX_ERR | b, - i, state->cb_data); - if (rc == 0) - rc = I2CERR_IO_ERROR; - } - } - } - - if ((txtimeo > 0 && txcnt >= txtimeo) || - (rxtimeo > 0 && rxcnt >= rxtimeo)) { - if (state->err_cb != NULL) - (*state->err_cb) (I2CECB_TIMEOUT, -1, state->cb_data); - if (rc == 0) - rc = I2CERR_TIMEOUT; - } - - return rc; -} - -static void i2c_probe_callback(int flags, int xnum, void *data) -{ - /* - * the only acceptable errors are a transmit NAK or a receive - * overrun - tx NAK means the device does not exist, rx OV - * means the device must have responded to the slave address - * even though the transfer failed - */ - if (flags == (I2CECB_TX_ERR | I2CECB_TX_NAK)) - *(int *) data |= 1; - if (flags == (I2CECB_RX_ERR | I2CECB_RX_OV)) - *(int *) data |= 2; -} - -int i2c_probe(uchar chip) -{ - i2c_state_t state; - int rc, err_flag; - uchar buf[1]; - - i2c_newio(&state); - - state.err_cb = i2c_probe_callback; - state.cb_data = (void *) &err_flag; - err_flag = 0; - - rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1, - buf); - - if (rc != 0) - return rc; /* probe failed */ - - rc = i2c_doio(&state); - - if (rc == 0) - return 0; /* device exists - read succeeded */ - - if (rc == I2CERR_TIMEOUT) - return -1; /* device does not exist - timeout */ - - if (rc != I2CERR_IO_ERROR || err_flag == 0) - return rc; /* probe failed */ - - if (err_flag & 1) - return -1; /* device does not exist - had transmit NAK */ - - return 0; /* device exists - had receive overrun */ -} - - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - i2c_state_t state; - uchar xaddr[4]; - int rc; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address - * and the extra bits end up in the "chip address" bit slots. - * This makes a 24WC08 (1Kbyte) chip look like four 256 byte - * chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, - &xaddr[4 - alen]); - if (rc != 0) { - printf("i2c_read: i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - printf("i2c_read: i2c_receive failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - printf("i2c_read: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - i2c_state_t state; - uchar xaddr[4]; - int rc; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones - * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address - * and the extra bits end up in the "chip address" bit slots. - * This makes a 24WC08 (1Kbyte) chip look like four 256 byte - * chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, - &xaddr[4 - alen]); - if (rc != 0) { - printf("i2c_write: first i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - printf("i2c_write: second i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - printf("i2c_write: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -#if defined(CONFIG_I2C_MULTI_BUS) -/* - * Functions for multiple I2C bus handling - */ -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -int i2c_set_bus_num(unsigned int bus) -{ - if (bus >= CONFIG_SYS_MAX_I2C_BUS) - return -1; - i2c_bus_num = bus; - return 0; -} - -#endif /* CONFIG_I2C_MULTI_BUS */ -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 02e43bc515..0772b7c4fb 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -49,6 +49,7 @@ config TARGET_MPC8349EMDS config TARGET_MPC8349ITX bool "Support MPC8349ITX" + imply CMD_IRQ config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 31c0964994..88d56a9a32 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -4,6 +4,14 @@ menu "mpc85xx CPU" config SYS_CPU default "mpc85xx" +config CMD_ERRATA + bool "Enable the 'errata' command" + depends on MPC85xx + default y + help + This enables the 'errata' command which displays a list of errata + work-arounds which are enabled for the current board. + choice prompt "Target select" optional @@ -124,6 +132,7 @@ config TARGET_P1010RDB_PA select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select SUPPORT_TPL + imply CMD_EEPROM config TARGET_P1010RDB_PB bool "Support P1010RDB_PB" @@ -131,6 +140,7 @@ config TARGET_P1010RDB_PB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select SUPPORT_TPL + imply CMD_EEPROM config TARGET_P1022DS bool "Support P1022DS" @@ -141,54 +151,63 @@ config TARGET_P1022DS config TARGET_P1023RDB bool "Support P1023RDB" select ARCH_P1023 + imply CMD_EEPROM config TARGET_P1020MBG bool "Support P1020MBG-PC" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1020RDB_PC bool "Support P1020RDB-PC" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1020RDB_PD bool "Support P1020RDB-PD" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1020UTM bool "Support P1020UTM" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1021RDB bool "Support P1021RDB" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1021 + imply CMD_EEPROM config TARGET_P1024RDB bool "Support P1024RDB" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1024 + imply CMD_EEPROM config TARGET_P1025RDB bool "Support P1025RDB" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1025 + imply CMD_EEPROM config TARGET_P2020RDB bool "Support P2020RDB-PC" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P2020 + imply CMD_EEPROM config TARGET_P1_TWR bool "Support p1_twr" @@ -211,6 +230,7 @@ config TARGET_T1024QDS select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1023RDB bool "Support T1023RDB" @@ -218,6 +238,7 @@ config TARGET_T1023RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1024RDB bool "Support T1024RDB" @@ -225,12 +246,14 @@ config TARGET_T1024RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1040QDS bool "Support T1040QDS" select ARCH_T1040 select BOARD_LATE_INIT if CHAIN_OF_TRUST select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1040RDB bool "Support T1040RDB" @@ -377,6 +400,7 @@ config ARCH_B4420 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 select FSL_IFC + imply CMD_EEPROM config ARCH_B4860 bool @@ -402,6 +426,7 @@ config ARCH_B4860 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 select FSL_IFC + imply CMD_EEPROM config ARCH_BSC9131 bool @@ -415,6 +440,7 @@ config ARCH_BSC9131 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_IFC + imply CMD_EEPROM config ARCH_BSC9132 bool @@ -432,6 +458,7 @@ config ARCH_BSC9132 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_IFC + imply CMD_EEPROM config ARCH_C29X bool @@ -565,6 +592,7 @@ config ARCH_P1010 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_IFC + imply CMD_EEPROM config ARCH_P1011 bool @@ -649,6 +677,7 @@ config ARCH_P1024 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_EEPROM config ARCH_P1025 bool @@ -678,6 +707,7 @@ config ARCH_P2020 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_EEPROM config ARCH_P2041 bool @@ -821,6 +851,7 @@ config ARCH_T1023 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC + imply CMD_EEPROM config ARCH_T1024 bool @@ -838,6 +869,7 @@ config ARCH_T1024 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC + imply CMD_EEPROM config ARCH_T1040 bool diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c index 2ba314a7f6..7c4519e4a4 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -10,7 +10,7 @@ #include <asm/io.h> -static u8 serdes_cfg_tbl[][4] = { +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1}, [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1}, @@ -45,7 +45,7 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl) if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; - for (i = 0; i < 4; i++) { + for (i = 0; i < SRDS_MAX_LANES; i++) { if (serdes_cfg_tbl[prtcl][i] != NONE) return 1; } diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index 6f81fee571..fc91a054f0 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -14,7 +14,6 @@ obj-y += cpu.o obj-y += cpu_init.o obj-y += fec.o obj-$(CONFIG_OF_LIBFDT) += fdt.o -obj-y += i2c.o obj-y += interrupts.o obj-y += scc.o obj-y += serial.o diff --git a/arch/powerpc/cpu/mpc8xx/i2c.c b/arch/powerpc/cpu/mpc8xx/i2c.c deleted file mode 100644 index 54d5cb5130..0000000000 --- a/arch/powerpc/cpu/mpc8xx/i2c.c +++ /dev/null @@ -1,672 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -#include <common.h> -#include <console.h> - -#ifdef CONFIG_HARD_I2C - -#include <commproc.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */ -#define TOUT_LOOP 1000000 - -#define NUM_RX_BDS 4 -#define NUM_TX_BDS 4 -#define MAX_TX_SPACE 256 -#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ - -typedef struct I2C_BD { - unsigned short status; - unsigned short length; - unsigned char *addr; -} I2C_BD; - -#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */ - -#define BD_I2C_TX_CL 0x0001 /* collision error */ -#define BD_I2C_TX_UN 0x0002 /* underflow error */ -#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */ -#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL) - -#define BD_I2C_RX_ERR BD_SC_OV - -typedef void (*i2c_ecb_t) (int, int); /* error callback function */ - -/* This structure keeps track of the bd and buffer space usage. */ -typedef struct i2c_state { - int rx_idx; /* index to next free Rx BD */ - int tx_idx; /* index to next free Tx BD */ - void *rxbd; /* pointer to next free Rx BD */ - void *txbd; /* pointer to next free Tx BD */ - int tx_space; /* number of Tx bytes left */ - unsigned char *tx_buf; /* pointer to free Tx area */ - i2c_ecb_t err_cb; /* error callback function */ -} i2c_state_t; - - -/* flags for i2c_send() and i2c_receive() */ -#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */ -#define I2CF_START_COND 0x02 /* tx: generate start condition */ -#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */ - -/* return codes */ -#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */ -#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */ -#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */ -#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */ - -/* error callback flags */ -#define I2CECB_RX_ERR 0x10 /* this is a receive error */ -#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */ -#define I2CECB_RX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TX_ERR 0x20 /* this is a transmit error */ -#define I2CECB_TX_CL 0x01 /* transmit collision error */ -#define I2CECB_TX_UN 0x02 /* transmit underflow error */ -#define I2CECB_TX_NAK 0x04 /* transmit no ack error */ -#define I2CECB_TX_MASK 0x0f /* mask for error bits */ -#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */ - -/* - * Returns the best value of I2BRG to meet desired clock speed of I2C with - * input parameters (clock speed, filter, and predivider value). - * It returns computer speed value and the difference between it and desired - * speed. - */ -static inline int -i2c_roundrate(int hz, int speed, int filter, int modval, - int *brgval, int *totspeed) -{ - int moddiv = 1 << (5 - (modval & 3)), brgdiv, div; - - debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n", - hz, speed, filter, modval); - - div = moddiv * speed; - brgdiv = (hz + div - 1) / div; - - debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv); - - *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter); - - if ((*brgval < 0) || (*brgval > 255)) { - debug("\t\trejected brgval=%d\n", *brgval); - return -1; - } - - brgdiv = 2 * (*brgval + 3 + (2 * filter)); - div = moddiv * brgdiv; - *totspeed = hz / div; - - debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed); - - return 0; -} - -/* - * Sets the I2C clock predivider and divider to meet required clock speed. - */ -static int i2c_setrate(int hz, int speed) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c; - int brgval, - modval, /* 0-3 */ - bestspeed_diff = speed, - bestspeed_brgval = 0, - bestspeed_modval = 0, - bestspeed_filter = 0, - totspeed, - filter = 0; /* Use this fixed value */ - - for (modval = 0; modval < 4; modval++) { - if (i2c_roundrate - (hz, speed, filter, modval, &brgval, &totspeed) == 0) { - int diff = speed - totspeed; - - if ((diff >= 0) && (diff < bestspeed_diff)) { - bestspeed_diff = diff; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; - } - } - } - - debug("[I2C] Best is:\n"); - debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n", - hz, - speed, - bestspeed_filter, - bestspeed_modval, - bestspeed_brgval, - bestspeed_diff); - - i2c->i2c_i2mod |= - ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3); - i2c->i2c_i2brg = bestspeed_brgval & 0xff; - - debug("[I2C] i2mod=%08x i2brg=%08x\n", - i2c->i2c_i2mod, - i2c->i2c_i2brg); - - return 1; -} - -void i2c_init(int speed, int slaveaddr) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - ulong rbase, tbase; - volatile I2C_BD *rxbd, *txbd; - uint dpaddr; - -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif - -#ifdef CONFIG_SYS_I2C_UCODE_PATCH - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#else - /* Disable relocation */ - iip->iic_rpbase = 0; -#endif - - dpaddr = CPM_I2C_BASE; - - /* - * initialise data in dual port ram: - * - * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) - * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) - * tx buffer (MAX_TX_SPACE bytes) - */ - - rbase = dpaddr; - tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD); - - /* Initialize Port B I2C pins. */ - cp->cp_pbpar |= 0x00000030; - cp->cp_pbdir |= 0x00000030; - cp->cp_pbodr |= 0x00000030; - - /* Disable interrupts */ - i2c->i2c_i2mod = 0x00; - i2c->i2c_i2cmr = 0x00; - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2add = slaveaddr; - - /* - * Set the I2C BRG Clock division factor from desired i2c rate - * and current CPU rate (we assume sccr dfbgr field is 0; - * divide BRGCLK by 1) - */ - debug("[I2C] Setting rate...\n"); - i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED); - - /* Set I2C controller in master mode */ - i2c->i2c_i2com = 0x01; - - /* Set SDMA bus arbitration level to 5 (SDCR) */ - immap->im_siu_conf.sc_sdcr = 0x0001; - - /* Initialize Tx/Rx parameters */ - iip->iic_rbase = rbase; - iip->iic_tbase = tbase; - rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]); - txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]); - - debug("[I2C] rbase = %04x\n", iip->iic_rbase); - debug("[I2C] tbase = %04x\n", iip->iic_tbase); - debug("[I2C] rxbd = %08x\n", (int)rxbd); - debug("[I2C] txbd = %08x\n", (int)txbd); - - /* Set big endian byte order */ - iip->iic_tfcr = 0x10; - iip->iic_rfcr = 0x10; - - /* Set maximum receive size. */ - iip->iic_mrblr = I2C_RXTX_LEN; - -#ifdef CONFIG_SYS_I2C_UCODE_PATCH - /* - * Initialize required parameters if using microcode patch. - */ - iip->iic_rbptr = iip->iic_rbase; - iip->iic_tbptr = iip->iic_tbase; - iip->iic_rstate = 0; - iip->iic_tstate = 0; -#else - cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__("eieio"); - } while (cp->cp_cpcr & CPM_CR_FLG); -#endif - - /* Clear events and interrupts */ - i2c->i2c_i2cer = 0xff; - i2c->i2c_i2cmr = 0x00; -} - -static void i2c_newio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - - debug("[I2C] i2c_newio\n"); - -#ifdef CONFIG_SYS_I2C_UCODE_PATCH - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - state->rx_idx = 0; - state->tx_idx = 0; - state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase]; - state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase]; - state->tx_space = MAX_TX_SPACE; - state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD); - state->err_cb = NULL; - - debug("[I2C] rxbd = %08x\n", (int)state->rxbd); - debug("[I2C] txbd = %08x\n", (int)state->txbd); - debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf); - - /* clear the buffer memory */ - memset((char *)state->tx_buf, 0, MAX_TX_SPACE); -} - -static int -i2c_send(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, unsigned short size, unsigned char *dataout) -{ - volatile I2C_BD *txbd; - int i, j; - - debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n", - address, secondary_address, flags, size); - - /* trying to send message larger than BD */ - if (size > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size)) - return I2CERR_NO_BUFFERS; - - txbd = (I2C_BD *) state->txbd; - txbd->addr = state->tx_buf; - - debug("[I2C] txbd = %08x\n", (int)txbd); - - if (flags & I2CF_START_COND) { - debug("[I2C] Formatting addresses...\n"); - if (flags & I2CF_ENABLE_SECONDARY) { - /* Length of msg + dest addr */ - txbd->length = size + 2; - - txbd->addr[0] = address << 1; - txbd->addr[1] = secondary_address; - i = 2; - } else { - /* Length of msg + dest addr */ - txbd->length = size + 1; - /* Write dest addr to BD */ - txbd->addr[0] = address << 1; - i = 1; - } - } else { - txbd->length = size; /* Length of message */ - i = 0; - } - - /* set up txbd */ - txbd->status = BD_SC_READY; - if (flags & I2CF_START_COND) - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - - /* Copy data to send into buffer */ - debug("[I2C] copy data...\n"); - for(j = 0; j < size; i++, j++) - txbd->addr[i] = dataout[j]; - - debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1]); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void *) (txbd + 1); - - return 0; -} - -static int -i2c_receive(i2c_state_t *state, - unsigned char address, - unsigned char secondary_address, - unsigned int flags, - unsigned short size_to_expect, unsigned char *datain) -{ - volatile I2C_BD *rxbd, *txbd; - - debug("[I2C] i2c_receive %02d %02d %02d\n", - address, secondary_address, flags); - - /* Expected to receive too much */ - if (size_to_expect > I2C_RXTX_LEN) - return I2CERR_MSG_TOO_LONG; - - /* no more free bds */ - if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS - || state->tx_space < 2) - return I2CERR_NO_BUFFERS; - - rxbd = (I2C_BD *) state->rxbd; - txbd = (I2C_BD *) state->txbd; - - debug("[I2C] rxbd = %08x\n", (int)rxbd); - debug("[I2C] txbd = %08x\n", (int)txbd); - - txbd->addr = state->tx_buf; - - /* set up TXBD for destination address */ - if (flags & I2CF_ENABLE_SECONDARY) { - txbd->length = 2; - txbd->addr[0] = address << 1; /* Write data */ - txbd->addr[1] = secondary_address; /* Internal address */ - txbd->status = BD_SC_READY; - } else { - txbd->length = 1 + size_to_expect; - txbd->addr[0] = (address << 1) | 0x01; - txbd->status = BD_SC_READY; - memset(&txbd->addr[1], 0, txbd->length); - } - - /* set up rxbd for reception */ - rxbd->status = BD_SC_EMPTY; - rxbd->length = size_to_expect; - rxbd->addr = datain; - - txbd->status |= BD_I2C_TX_START; - if (flags & I2CF_STOP_COND) { - txbd->status |= BD_SC_LAST | BD_SC_WRAP; - rxbd->status |= BD_SC_WRAP; - } - - debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - txbd->length, - txbd->status, - txbd->addr[0], - txbd->addr[1]); - debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n", - rxbd->length, - rxbd->status, - rxbd->addr[0], - rxbd->addr[1]); - - /* advance state */ - state->tx_buf += txbd->length; - state->tx_space -= txbd->length; - state->tx_idx++; - state->txbd = (void *) (txbd + 1); - state->rx_idx++; - state->rxbd = (void *) (rxbd + 1); - - return 0; -} - - -static int i2c_doio(i2c_state_t *state) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm; - volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c; - volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - volatile I2C_BD *txbd, *rxbd; - volatile int j = 0; - - debug("[I2C] i2c_doio\n"); - -#ifdef CONFIG_SYS_I2C_UCODE_PATCH - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - - if (state->tx_idx <= 0 && state->rx_idx <= 0) { - debug("[I2C] No I/O is queued\n"); - return I2CERR_QUEUE_EMPTY; - } - - iip->iic_rbptr = iip->iic_rbase; - iip->iic_tbptr = iip->iic_tbase; - - /* Enable I2C */ - debug("[I2C] Enabling I2C...\n"); - i2c->i2c_i2mod |= 0x01; - - /* Begin transmission */ - i2c->i2c_i2com |= 0x80; - - /* Loop until transmit & receive completed */ - - if (state->tx_idx > 0) { - txbd = ((I2C_BD*)state->txbd) - 1; - - debug("[I2C] Transmitting...(txbd=0x%08lx)\n", - (ulong)txbd); - - while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) { - if (ctrlc()) - return (-1); - - __asm__ __volatile__("eieio"); - } - } - - if ((state->rx_idx > 0) && (j < TOUT_LOOP)) { - rxbd = ((I2C_BD*)state->rxbd) - 1; - - debug("[I2C] Receiving...(rxbd=0x%08lx)\n", - (ulong)rxbd); - - while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) { - if (ctrlc()) - return (-1); - - __asm__ __volatile__("eieio"); - } - } - - /* Turn off I2C */ - i2c->i2c_i2mod &= ~0x01; - - if (state->err_cb != NULL) { - int n, i, b; - - /* - * if we have an error callback function, look at the - * error bits in the bd status and pass them back - */ - - if ((n = state->tx_idx) > 0) { - for (i = 0; i < n; i++) { - txbd = ((I2C_BD *) state->txbd) - (n - i); - if ((b = txbd->status & BD_I2C_TX_ERR) != 0) - (*state->err_cb) (I2CECB_TX_ERR | b, - i); - } - } - - if ((n = state->rx_idx) > 0) { - for (i = 0; i < n; i++) { - rxbd = ((I2C_BD *) state->rxbd) - (n - i); - if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) - (*state->err_cb) (I2CECB_RX_ERR | b, - i); - } - } - - if (j >= TOUT_LOOP) - (*state->err_cb) (I2CECB_TIMEOUT, 0); - } - - return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0; -} - -static int had_tx_nak; - -static void i2c_test_callback(int flags, int xnum) -{ - if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK)) - had_tx_nak = 1; -} - -int i2c_probe(uchar chip) -{ - i2c_state_t state; - int rc; - uchar buf[1]; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_newio(&state); - - state.err_cb = i2c_test_callback; - had_tx_nak = 0; - - rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1, - buf); - - if (rc != 0) - return (rc); - - rc = i2c_doio(&state); - - if ((rc != 0) && (rc != I2CERR_TIMEOUT)) - return (rc); - - return (had_tx_nak); -} - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - i2c_state_t state; - uchar xaddr[4]; - int rc; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones like - * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the - * extra bits end up in the "chip address" bit slots. This makes - * a 24WC08 (1Kbyte) chip look like four 256 byte chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, - &xaddr[4 - alen]); - if (rc != 0) { - printf("i2c_read: i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - printf("i2c_read: i2c_receive failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - printf("i2c_read: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - i2c_state_t state; - uchar xaddr[4]; - int rc; - - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; - -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW - /* - * EEPROM chips that implement "address overflow" are ones like - * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the - * extra bits end up in the "chip address" bit slots. This makes - * a 24WC08 (1Kbyte) chip look like four 256 byte chips. - * - * Note that we consider the length of the address field to still - * be one byte because the extra address bits are hidden in the - * chip address. - */ - chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); -#endif - - i2c_newio(&state); - - rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, - &xaddr[4 - alen]); - if (rc != 0) { - printf("i2c_write: first i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer); - if (rc != 0) { - printf("i2c_write: second i2c_send failed (%d)\n", rc); - return 1; - } - - rc = i2c_doio(&state); - if (rc != 0) { - printf("i2c_write: i2c_doio failed (%d)\n", rc); - return 1; - } - return 0; -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 38121c1427..77e8fd458e 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -137,6 +137,12 @@ config CMD_CHIP_CONFIG and control the CPU and peripehrals clocks. The programmed configuration is then used when the board boots. +config CMD_ECCTEST + bool "Enable the 'ecctest' command" + help + This command tests memory ECC by single and double error bit + injection. + source "board/amcc/acadia/Kconfig" source "board/amcc/bamboo/Kconfig" source "board/amcc/bubinga/Kconfig" diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 62ce816b13..76921eea9a 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -99,9 +99,7 @@ #define CONFIG_SPL_UBOOT_KEY_HASH NULL #endif /* ifdef CONFIG_SPL_BUILD */ -#define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL #ifndef CONFIG_SPL_BUILD /* diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 762b174b2d..ee537f4ac9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2523,7 +2523,11 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define MAX_SERDES 4 +#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) +#define SRDS_MAX_LANES 4 +#else #define SRDS_MAX_LANES 8 +#endif #define SRDS_MAX_BANK 2 typedef struct serdes_corenet { struct { diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig new file mode 100644 index 0000000000..987cec99cb --- /dev/null +++ b/arch/powerpc/lib/Kconfig @@ -0,0 +1,8 @@ +config CMD_IMMAP + bool "Enable various commands to dump IMMR information" + help + This enables various commands such as: + + siuinfo - print System Interface Unit (SIU) registers + memcinfo - print Memory Controller registers + sitinfo - print System Integration Timers (SIT) registers diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 4f68613a41..e09bd9a88a 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -33,9 +33,10 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o +obj-$(CONFIG_CMD_IMMAP) += immap.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o -obj-$(CONFIG_CMD_IDE) += ide.o +obj-$(CONFIG_IDE) += ide.o obj-y += stack.o obj-y += time.o diff --git a/cmd/immap.c b/arch/powerpc/lib/immap.c index 1414f9ad55..1414f9ad55 100644 --- a/cmd/immap.c +++ b/arch/powerpc/lib/immap.c diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9ead3ebccf..0cd981e73e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -589,6 +589,38 @@ config GENERATE_ACPI_TABLE endmenu +config HAVE_ACPI_RESUME + bool "Enable ACPI S3 resume" + help + Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping + state where all system context is lost except system memory. U-Boot + is responsible for restoring the machine state as it was before sleep. + It needs restore the memory controller, without overwriting memory + which is not marked as reserved. For the peripherals which lose their + registers, U-Boot needs to write the original value. When everything + is done, U-Boot needs to find out the wakeup vector provided by OSes + and jump there. + +config S3_VGA_ROM_RUN + bool "Re-run VGA option ROMs on S3 resume" + depends on HAVE_ACPI_RESUME + default y if HAVE_ACPI_RESUME + help + Execute VGA option ROMs in U-Boot when resuming from S3. Normally + this is needed when graphics console is being used in the kernel. + + Turning it off can reduce some resume time, but be aware that your + graphics console won't work without VGA options ROMs. Set it to N + if your kernel is only on a serial console. + +config STACK_SIZE + hex + depends on HAVE_ACPI_RESUME + default 0x1000 + help + Estimated U-Boot's runtime stack size that needs to be reserved + during an ACPI S3 resume. + config MAX_PIRQ_LINKS int default 8 diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 92a9023b0b..e1c84ce097 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -45,6 +45,7 @@ ifndef CONFIG_$(SPL_)X86_64 obj-$(CONFIG_SMP) += sipi_vector.o endif obj-y += turbo.o +obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.o ifeq ($(CONFIG_$(SPL_)X86_64),y) obj-y += x86_64/ diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index fa92d8852e..55ed7de781 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -8,7 +8,9 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <asm/acpi_s3.h> #include <asm/acpi_table.h> +#include <asm/io.h> #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> @@ -187,3 +189,48 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) else gnvs->iuart_en = 0; } + +#ifdef CONFIG_HAVE_ACPI_RESUME +/* + * The following two routines are called at a very early stage, even before + * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS + * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses + * of these two blocks are programmed by either U-Boot or FSP. + * + * It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S) + * on Intel BayTrail SoC already initializes these two base addresses so + * we are safe to access these registers here. + */ + +enum acpi_sleep_state chipset_prev_sleep_state(void) +{ + u32 pm1_sts; + u32 pm1_cnt; + u32 gen_pmcon1; + enum acpi_sleep_state prev_sleep_state = ACPI_S0; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1); + + debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) + prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt); + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +void chipset_clear_sleep_state(void) +{ + u32 pm1_cnt; + + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); +} +#endif diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 87ba849c1c..c58f6a86a8 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -11,18 +11,6 @@ #include <asm/mrccache.h> #include <asm/post.h> -static struct pci_device_id mmc_supported[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 }, - {}, -}; - -int cpu_mmc_init(bd_t *bis) -{ - return pci_mmc_init("ValleyView SDHCI", mmc_supported); -} - #ifndef CONFIG_EFI_APP int arch_cpu_init(void) { diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 8fa6953588..e13786efa5 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -25,6 +25,8 @@ #include <errno.h> #include <malloc.h> #include <syscon.h> +#include <asm/acpi_s3.h> +#include <asm/acpi_table.h> #include <asm/control_regs.h> #include <asm/coreboot_tables.h> #include <asm/cpu.h> @@ -179,6 +181,11 @@ int default_print_cpuinfo(void) cpu_has_64bit() ? "x86_64" : "x86", cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); +#ifdef CONFIG_HAVE_ACPI_RESUME + debug("ACPI previous sleep state: %s\n", + acpi_ss_string(gd->arch.prev_sleep_state)); +#endif + return 0; } @@ -198,10 +205,17 @@ __weak void board_final_cleanup(void) int last_stage_init(void) { - write_tables(); - board_final_cleanup(); +#if CONFIG_HAVE_ACPI_RESUME + struct acpi_fadt *fadt = acpi_find_fadt(); + + if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3) + acpi_resume(fadt); +#endif + + write_tables(); + return 0; } #endif @@ -264,6 +278,18 @@ int reserve_arch(void) high_table_reserve(); #endif +#ifdef CONFIG_HAVE_ACPI_RESUME + acpi_s3_reserve(); + +#ifdef CONFIG_HAVE_FSP + /* + * Save stack address to CMOS so that at next S3 boot, + * we can use it as the stack address for fsp_contiue() + */ + fsp_save_s3_stack(); +#endif /* CONFIG_HAVE_FSP */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + return 0; } #endif diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 0c2cea4ee9..c36a5892d5 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -16,11 +16,6 @@ #include <asm/arch/msg_port.h> #include <asm/arch/quark.h> -static struct pci_device_id mmc_supported[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, - {}, -}; - static void quark_setup_mtrr(void) { u32 base, mask; @@ -328,11 +323,6 @@ int arch_early_init_r(void) return 0; } -int cpu_mmc_init(bd_t *bis) -{ - return pci_mmc_init("Quark SDHCI", mmc_supported); -} - int arch_misc_init(void) { #ifdef CONFIG_ENABLE_MRC_CACHE diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index af3ffad385..c0681995bd 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -5,4 +5,4 @@ # obj-y += fsp_configs.o irq.o -obj-y += tnc.o topcliff.o +obj-y += tnc.o diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c deleted file mode 100644 index b76dd7de69..0000000000 --- a/arch/x86/cpu/queensbay/topcliff.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mmc.h> -#include <pci_ids.h> - -static struct pci_device_id mmc_supported[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, - {}, -}; - -int cpu_mmc_init(bd_t *bis) -{ - return pci_mmc_init("Topcliff SDHCI", mmc_supported); -} diff --git a/arch/x86/cpu/wakeup.S b/arch/x86/cpu/wakeup.S new file mode 100644 index 0000000000..066c9b1a55 --- /dev/null +++ b/arch/x86/cpu/wakeup.S @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * From coreboot src/arch/x86/wakeup.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi_s3.h> +#include <asm/processor.h> +#include <asm/processor-flags.h> + +#define RELOCATED(x) ((x) - __wakeup + WAKEUP_BASE) + +#define CODE_SEG (X86_GDT_ENTRY_16BIT_CS * X86_GDT_ENTRY_SIZE) +#define DATA_SEG (X86_GDT_ENTRY_16BIT_DS * X86_GDT_ENTRY_SIZE) + + .code32 + .globl __wakeup +__wakeup: + /* First prepare the jmp to the resume vector */ + mov 0x4(%esp), %eax /* vector */ + /* last 4 bits of linear addr are taken as offset */ + andw $0x0f, %ax + movw %ax, (__wakeup_offset) + mov 0x4(%esp), %eax + /* the rest is taken as segment */ + shr $4, %eax + movw %ax, (__wakeup_segment) + + /* Activate the right segment descriptor real mode */ + ljmp $CODE_SEG, $RELOCATED(1f) +1: + /* 16 bit code from here on... */ + .code16 + + /* + * Load the segment registers w/ properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ + mov $DATA_SEG, %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss + + /* Turn off protection */ + movl %cr0, %eax + andl $~X86_CR0_PE, %eax + movl %eax, %cr0 + + /* Now really going into real mode */ + ljmp $0, $RELOCATED(1f) +1: + movw $0x0, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* + * This is a FAR JMP to the OS waking vector. + * The C code changes the address to be correct. + */ + .byte 0xea + +__wakeup_offset = RELOCATED(.) + .word 0x0000 + +__wakeup_segment = RELOCATED(.) + .word 0x0000 + + .globl __wakeup_size +__wakeup_size: + .long . - __wakeup diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 18b310d39e..1ae058d7a9 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -189,6 +189,7 @@ u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; + use-lvl-write-cache; }; gpiob { @@ -196,6 +197,7 @@ u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; + use-lvl-write-cache; }; gpioc { @@ -203,6 +205,7 @@ u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; + use-lvl-write-cache; }; gpiod { @@ -210,6 +213,7 @@ u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; + use-lvl-write-cache; }; gpioe { @@ -217,6 +221,7 @@ u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; + use-lvl-write-cache; }; gpiof { @@ -224,6 +229,7 @@ u-boot,dm-pre-reloc; reg = <0xA0 0x20>; bank-name = "F"; + use-lvl-write-cache; }; }; }; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index e1d81a7283..aa8bfb8651 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -212,6 +212,7 @@ u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; + use-lvl-write-cache; }; gpiob { @@ -219,6 +220,7 @@ u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; + use-lvl-write-cache; }; gpioc { @@ -226,6 +228,7 @@ u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; + use-lvl-write-cache; }; gpiod { @@ -233,6 +236,7 @@ u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; + use-lvl-write-cache; }; gpioe { @@ -240,6 +244,7 @@ u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; + use-lvl-write-cache; }; gpiof { @@ -247,6 +252,7 @@ u-boot,dm-pre-reloc; reg = <0xA0 0x20>; bank-name = "F"; + use-lvl-write-cache; }; }; }; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index f0efe908e2..898e9c9b5f 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -199,6 +199,7 @@ u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; + use-lvl-write-cache; }; gpiob { @@ -206,6 +207,7 @@ u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; + use-lvl-write-cache; }; gpioc { @@ -213,6 +215,7 @@ u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; + use-lvl-write-cache; }; gpiod { @@ -220,6 +223,7 @@ u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; + use-lvl-write-cache; }; gpioe { @@ -227,6 +231,7 @@ u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; + use-lvl-write-cache; }; gpiof { @@ -234,6 +239,7 @@ u-boot,dm-pre-reloc; reg = <0xA0 0x20>; bank-name = "F"; + use-lvl-write-cache; }; }; }; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 75ee6ade7c..546981a9ac 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -201,6 +201,7 @@ u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; + use-lvl-write-cache; }; gpiob { @@ -208,6 +209,7 @@ u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; + use-lvl-write-cache; }; gpioc { @@ -215,6 +217,7 @@ u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; + use-lvl-write-cache; }; gpiod { @@ -222,6 +225,7 @@ u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; + use-lvl-write-cache; }; gpioe { @@ -229,6 +233,7 @@ u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; + use-lvl-write-cache; }; gpiof { @@ -236,6 +241,7 @@ u-boot,dm-pre-reloc; reg = <0xA0 0x20>; bank-name = "F"; + use-lvl-write-cache; }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index d51318bdf6..af64c6859c 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -35,7 +35,6 @@ /* GPIO E0 */ soc_gpio_s5_0@0 { gpio-offset = <0x80 0>; - pad-offset = <0x1d0>; mode-gpio; output-value = <0>; direction = <PIN_OUTPUT>; @@ -44,7 +43,6 @@ /* GPIO E1 */ soc_gpio_s5_1@0 { gpio-offset = <0x80 1>; - pad-offset = <0x210>; mode-gpio; output-value = <0>; direction = <PIN_OUTPUT>; @@ -53,7 +51,6 @@ /* GPIO E2 */ soc_gpio_s5_2@0 { gpio-offset = <0x80 2>; - pad-offset = <0x1e0>; mode-gpio; output-value = <0>; direction = <PIN_OUTPUT>; @@ -61,7 +58,6 @@ pin_usb_host_en0@0 { gpio-offset = <0x80 8>; - pad-offset = <0x260>; mode-gpio; output-value = <1>; direction = <PIN_OUTPUT>; @@ -69,7 +65,6 @@ pin_usb_host_en1@0 { gpio-offset = <0x80 9>; - pad-offset = <0x250>; mode-gpio; output-value = <1>; direction = <PIN_OUTPUT>; @@ -218,6 +213,7 @@ u-boot,dm-pre-reloc; reg = <0 0x20>; bank-name = "A"; + use-lvl-write-cache; }; gpiob { @@ -225,6 +221,7 @@ u-boot,dm-pre-reloc; reg = <0x20 0x20>; bank-name = "B"; + use-lvl-write-cache; }; gpioc { @@ -232,6 +229,7 @@ u-boot,dm-pre-reloc; reg = <0x40 0x20>; bank-name = "C"; + use-lvl-write-cache; }; gpiod { @@ -239,6 +237,7 @@ u-boot,dm-pre-reloc; reg = <0x60 0x20>; bank-name = "D"; + use-lvl-write-cache; }; gpioe { @@ -246,6 +245,7 @@ u-boot,dm-pre-reloc; reg = <0x80 0x20>; bank-name = "E"; + use-lvl-write-cache; }; gpiof { @@ -253,6 +253,7 @@ u-boot,dm-pre-reloc; reg = <0xA0 0x20>; bank-name = "F"; + use-lvl-write-cache; }; }; }; diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h new file mode 100644 index 0000000000..86aec0abe0 --- /dev/null +++ b/arch/x86/include/asm/acpi_s3.h @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ACPI_S3_H__ +#define __ASM_ACPI_S3_H__ + +#define WAKEUP_BASE 0x600 + +/* PM1_STATUS register */ +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define RTC_STS (1 << 10) +#define SLPBTN_STS (1 << 9) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMR_STS (1 << 0) + +/* PM1_CNT register */ +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 + +/* Memory size reserved for S3 resume */ +#define S3_RESERVE_SIZE 0x1000 + +#ifndef __ASSEMBLY__ + +extern char __wakeup[]; +extern int __wakeup_size; + +enum acpi_sleep_state { + ACPI_S0, + ACPI_S1, + ACPI_S2, + ACPI_S3, + ACPI_S4, + ACPI_S5, +}; + +/** + * acpi_ss_string() - get ACPI-defined sleep state string + * + * @pm1_cnt: ACPI-defined sleep state + * @return: a pointer to the sleep state string. + */ +static inline char *acpi_ss_string(enum acpi_sleep_state state) +{ + char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"}; + + return ss_string[state]; +} + +/** + * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register + * + * @pm1_cnt: PM1_CNT register value + * @return: ACPI-defined sleep state if given valid PM1_CNT register value, + * -EINVAL otherwise. + */ +static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) +{ + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + case SLP_TYP_S0: + return ACPI_S0; + case SLP_TYP_S1: + return ACPI_S1; + case SLP_TYP_S3: + return ACPI_S3; + case SLP_TYP_S4: + return ACPI_S4; + case SLP_TYP_S5: + return ACPI_S5; + } + + return -EINVAL; +} + +/** + * chipset_prev_sleep_state() - Get chipset previous sleep state + * + * This returns chipset previous sleep state from ACPI registers. + * Platform codes must supply this routine in order to support ACPI S3. + * + * @return ACPI_S0/S1/S2/S3/S4/S5. + */ +enum acpi_sleep_state chipset_prev_sleep_state(void); + +/** + * chipset_clear_sleep_state() - Clear chipset sleep state + * + * This clears chipset sleep state in ACPI registers. + * Platform codes must supply this routine in order to support ACPI S3. + */ +void chipset_clear_sleep_state(void); + +struct acpi_fadt; +/** + * acpi_resume() - Do ACPI S3 resume + * + * This calls U-Boot wake up assembly stub and jumps to OS's wake up vector. + * + * @fadt: FADT table pointer in the ACPI table + * @return: Never returns + */ +void acpi_resume(struct acpi_fadt *fadt); + +/** + * acpi_s3_reserve() - Reserve memory for ACPI S3 resume + * + * This copies memory where real mode interrupt handler stubs reside to the + * reserved place on the stack. + * + * This routine should be called by reserve_arch() before U-Boot is relocated + * when ACPI S3 resume is enabled. + * + * @return: 0 always + */ +int acpi_s3_reserve(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ACPI_S3_H__ */ diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index bbd80a1dd9..dd7a946b6c 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -316,4 +316,32 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); u32 acpi_fill_madt(u32 current); void acpi_create_gnvs(struct acpi_global_nvs *gnvs); +/** + * enter_acpi_mode() - enter into ACPI mode + * + * This programs the ACPI-defined PM1_CNT register to enable SCI interrupt + * so that the whole system swiches to ACPI mode. + * + * @pm1_cnt: PM1_CNT register I/O address + */ +void enter_acpi_mode(int pm1_cnt); ulong write_acpi_tables(ulong start); + +/** + * acpi_find_fadt() - find ACPI FADT table in the sytem memory + * + * This routine parses the ACPI table to locate the ACPI FADT table. + * + * @return: a pointer to the ACPI FADT table in the system memory + */ +struct acpi_fadt *acpi_find_fadt(void); + +/** + * acpi_find_wakeup_vector() - find OS installed wake up vector address + * + * This routine parses the ACPI table to locate the wake up vector installed + * by the OS previously. + * + * @return: wake up vector address installed by the OS + */ +void *acpi_find_wakeup_vector(struct acpi_fadt *); diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl index eb5ae76186..5600723084 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl @@ -8,6 +8,8 @@ */ Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) +#ifdef CONFIG_HAVE_ACPI_RESUME Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) +#endif Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h index 62a91051e4..ec4e9d5212 100644 --- a/arch/x86/include/asm/arch-baytrail/iomap.h +++ b/arch/x86/include/asm/arch-baytrail/iomap.h @@ -35,6 +35,27 @@ #define PMC_BASE_ADDRESS 0xfed03000 #define PMC_BASE_SIZE 0x400 +#define GEN_PMCON1 0x20 +#define UART_EN (1 << 24) +#define DISB (1 << 23) +#define MEM_SR (1 << 21) +#define SRS (1 << 20) +#define CTS (1 << 19) +#define MS4V (1 << 18) +#define PWR_FLR (1 << 16) +#define PME_B0_S5_DIS (1 << 15) +#define SUS_PWR_FLR (1 << 14) +#define WOL_EN_OVRD (1 << 13) +#define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +#define GEN_RST_STS (1 << 9) +#define RPS (1 << 2) +#define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +#define SLPSX_STR_POL_LOCK (1 << 18) +#define BIOS_PCI_EXP_EN (1 << 10) +#define PWRBTN_LVL (1 << 9) +#define SMI_LOCK (1 << 4) + /* Power Management Unit */ #define PUNIT_BASE_ADDRESS 0xfed05000 #define PUNIT_BASE_SIZE 0x800 @@ -62,6 +83,9 @@ #define ACPI_BASE_ADDRESS 0x0400 #define ACPI_BASE_SIZE 0x80 +#define PM1_STS 0x00 +#define PM1_CNT 0x04 + #define GPIO_BASE_ADDRESS 0x0500 #define GPIO_BASE_SIZE 0x100 diff --git a/arch/x86/include/asm/cmos_layout.h b/arch/x86/include/asm/cmos_layout.h new file mode 100644 index 0000000000..0a0a51e72d --- /dev/null +++ b/arch/x86/include/asm/cmos_layout.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CMOS_LAYOUT_H +#define __CMOS_LAYOUT_H + +/* + * The RTC internal registers and RAM is organized as two banks of 128 bytes + * each, called the standard and extended banks. The first 14 bytes of the + * standard bank contain the RTC time and date information along with four + * registers, A - D, that are used for configuration of the RTC. The extended + * bank contains a full 128 bytes of battery backed SRAM. + * + * For simplicity in U-Boot we only support CMOS in the standard bank, and + * its base address starts from offset 0x10, which leaves us 112 bytes space. + */ +#define CMOS_BASE 0x10 + +/* + * The file records all offsets off CMOS_BASE that is currently used by + * U-Boot for various reasons. It is put in such a unified place in order + * to be consistent across platforms. + */ + +/* stack address for S3 boot in a FSP configuration, 4 bytes */ +#define CMOS_FSP_STACK_ADDR CMOS_BASE + +#endif /* __CMOS_LAYOUT_H */ diff --git a/arch/x86/include/asm/early_cmos.h b/arch/x86/include/asm/early_cmos.h new file mode 100644 index 0000000000..cd2634d4cd --- /dev/null +++ b/arch/x86/include/asm/early_cmos.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EARLY_CMOS_H +#define __EARLY_CMOS_H + +/* CMOS actually resides in the RTC SRAM */ +#define CMOS_IO_PORT 0x70 + +/** + * cmos_read8() - Get 8-bit data stored at the given address + * + * This reads from CMOS for the 8-bit data stored at the given address. + * + * @addr: RTC SRAM address + * @return: 8-bit data stored at the given address + */ +u8 cmos_read8(u8 addr); + +/** + * cmos_read16() - Get 16-bit data stored at the given address + * + * This reads from CMOS for the 16-bit data stored at the given address. + * + * @addr: RTC SRAM address + * @return: 16-bit data stored at the given address + */ +u16 cmos_read16(u8 addr); + +/** + * cmos_read32() - Get 32-bit data stored at the given address + * + * This reads from CMOS for the 32-bit data stored at the given address. + * + * @addr: RTC SRAM address + * @return: 32-bit data stored at the given address + */ +u32 cmos_read32(u8 addr); + +#endif /* __EARLY_CMOS_H */ diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 4570bc7a4a..93a80fe2b6 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -99,6 +99,10 @@ struct arch_global_data { u32 high_table_ptr; u32 high_table_limit; #endif +#ifdef CONFIG_HAVE_ACPI_RESUME + int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */ + ulong backup_mem; /* Backup memory address for S3 */ +#endif }; #endif diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h index 6b774bdbe8..f627663f31 100644 --- a/arch/x86/include/asm/post.h +++ b/arch/x86/include/asm/post.h @@ -31,10 +31,12 @@ #define POST_MRC 0x2f #define POST_DRAM 0x30 #define POST_LAPIC 0x31 +#define POST_OS_RESUME 0x40 #define POST_RAM_FAILURE 0xea #define POST_BIST_FAILURE 0xeb #define POST_CAR_FAILURE 0xec +#define POST_RESUME_FAILURE 0xed /* Output a post code using al - value must be 0 to 0xff */ #ifdef __ASSEMBLY__ diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index d1b2388021..9e8208ba2b 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -15,6 +15,7 @@ * PIRQ routing table, Multi-Processor table and ACPI table. */ #define ROM_TABLE_ADDR 0xf0000 +#define ROM_TABLE_END 0xfffff #define ROM_TABLE_ALIGN 1024 diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index d2d603967e..d55455f2d0 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -54,6 +54,19 @@ u32 isa_map_rom(u32 bus_addr, int size); /* arch/x86/lib/... */ int video_bios_init(void); +/* arch/x86/lib/fsp/... */ + +/** + * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot + * + * At the end of pre-relocation phase, save the new stack address + * to CMOS and use it as the stack on next S3 boot for fsp_init() + * continuation function. + * + * @return: 0 if OK, -ve on error + */ +int fsp_save_s3_stack(void); + void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); void board_init_f_r(void) __attribute__ ((noreturn)); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index d1ad37af64..fe00d7573f 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o endif obj-y += cmd_boot.o obj-$(CONFIG_SEABIOS) += coreboot_table.o +obj-y += early_cmos.o obj-$(CONFIG_EFI) += efi/ obj-y += e820.o obj-y += gcc.o @@ -37,6 +38,7 @@ obj-$(CONFIG_INTEL_MID) += scu.o obj-y += sections.o obj-y += sfi.o obj-y += string.o +obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o ifndef CONFIG_QEMU obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o endif diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c new file mode 100644 index 0000000000..3175da828b --- /dev/null +++ b/arch/x86/lib/acpi_s3.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/acpi_s3.h> +#include <asm/acpi_table.h> +#include <asm/post.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void asmlinkage (*acpi_do_wakeup)(void *vector) = (void *)WAKEUP_BASE; + +static void acpi_jump_to_wakeup(void *vector) +{ + /* Copy wakeup trampoline in place */ + memcpy((void *)WAKEUP_BASE, __wakeup, __wakeup_size); + + printf("Jumping to OS waking vector %p\n", vector); + acpi_do_wakeup(vector); +} + +void acpi_resume(struct acpi_fadt *fadt) +{ + void *wake_vec; + + /* Turn on ACPI mode for S3 */ + enter_acpi_mode(fadt->pm1a_cnt_blk); + + wake_vec = acpi_find_wakeup_vector(fadt); + + /* + * Restore the memory content starting from address 0x1000 which is + * used for the real mode interrupt handler stubs. + */ + memcpy((void *)0x1000, (const void *)gd->arch.backup_mem, + S3_RESERVE_SIZE); + + post_code(POST_OS_RESUME); + acpi_jump_to_wakeup(wake_vec); +} + +int acpi_s3_reserve(void) +{ + /* adjust stack pointer for ACPI S3 resume backup memory */ + gd->start_addr_sp -= S3_RESERVE_SIZE; + gd->arch.backup_mem = gd->start_addr_sp; + + gd->start_addr_sp &= ~0xf; + + /* + * U-Boot sets up the real mode interrupt handler stubs starting from + * address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff) + * system memory is reported as system RAM in E820 table to the OS. + * (see install_e820_map() implementation for each platform). So OS + * can use these memories whatever it wants. + * + * If U-Boot is in an S3 resume path, care must be taken not to corrupt + * these memorie otherwise OS data gets lost. Testing shows that, on + * Microsoft Windows 10 on Intel Baytrail its wake up vector happens to + * be installed at the same address 0x1000. While on Linux its wake up + * vector does not overlap this memory range, but after resume kernel + * checks low memory range per config option CONFIG_X86_RESERVE_LOW + * which is 64K by default to see whether a memory corruption occurs + * during the suspend/resume (it's harmless, but warnings are shown + * in the kernel dmesg logs). + * + * We cannot simply mark the these memory as reserved in E820 table + * because such configuration makes GRUB complain: unable to allocate + * real mode page. Hence we choose to back up these memories to the + * place where we reserved on our stack for our S3 resume work. + * Before jumping to OS wake up vector, we need restore the original + * content there (see acpi_resume() above). + */ + if (gd->arch.prev_sleep_state == ACPI_S3) + memcpy((void *)gd->arch.backup_mem, (const void *)0x1000, + S3_RESERVE_SIZE); + + return 0; +} diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 355456dc19..01d5b6fff0 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -304,8 +304,10 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) header->checksum = table_compute_checksum((void *)mcfg, header->length); } -static void enter_acpi_mode(int pm1_cnt) +void enter_acpi_mode(int pm1_cnt) { + u16 val = inw(pm1_cnt); + /* * PM1_CNT register bit0 selects the power management event to be * either an SCI or SMI interrupt. When this bit is set, then power @@ -320,7 +322,7 @@ static void enter_acpi_mode(int pm1_cnt) * system, and expose ourselves to OSPM as working under ACPI mode * already, turn this bit on. */ - outw(PM1_CNT_SCI_EN, pm1_cnt); + outw(val | PM1_CNT_SCI_EN, pm1_cnt); } /* @@ -438,3 +440,81 @@ ulong write_acpi_tables(ulong start) return current; } + +static struct acpi_rsdp *acpi_valid_rsdp(struct acpi_rsdp *rsdp) +{ + if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0) + return NULL; + + debug("Looking on %p for valid checksum\n", rsdp); + + if (table_compute_checksum((void *)rsdp, 20) != 0) + return NULL; + debug("acpi rsdp checksum 1 passed\n"); + + if ((rsdp->revision > 1) && + (table_compute_checksum((void *)rsdp, rsdp->length) != 0)) + return NULL; + debug("acpi rsdp checksum 2 passed\n"); + + return rsdp; +} + +struct acpi_fadt *acpi_find_fadt(void) +{ + char *p, *end; + struct acpi_rsdp *rsdp = NULL; + struct acpi_rsdt *rsdt; + struct acpi_fadt *fadt = NULL; + int i; + + /* Find RSDP */ + for (p = (char *)ROM_TABLE_ADDR; p < (char *)ROM_TABLE_END; p += 16) { + rsdp = acpi_valid_rsdp((struct acpi_rsdp *)p); + if (rsdp) + break; + } + + if (rsdp == NULL) + return NULL; + + debug("RSDP found at %p\n", rsdp); + rsdt = (struct acpi_rsdt *)rsdp->rsdt_address; + + end = (char *)rsdt + rsdt->header.length; + debug("RSDT found at %p ends at %p\n", rsdt, end); + + for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { + fadt = (struct acpi_fadt *)rsdt->entry[i]; + if (strncmp((char *)fadt, "FACP", 4) == 0) + break; + fadt = NULL; + } + + if (fadt == NULL) + return NULL; + + debug("FADT found at %p\n", fadt); + return fadt; +} + +void *acpi_find_wakeup_vector(struct acpi_fadt *fadt) +{ + struct acpi_facs *facs; + void *wake_vec; + + debug("Trying to find the wakeup vector...\n"); + + facs = (struct acpi_facs *)fadt->firmware_ctrl; + + if (facs == NULL) { + debug("No FACS found, wake up from S3 not possible.\n"); + return NULL; + } + + debug("FACS found at %p\n", facs); + wake_vec = (void *)facs->firmware_waking_vector; + debug("OS waking vector is %p\n", wake_vec); + + return wake_vec; +} diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 75bab90225..ecd4f4e6c6 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -10,6 +10,8 @@ #include <common.h> #include <command.h> +#include <dm/device.h> +#include <dm/root.h> #include <errno.h> #include <fdt_support.h> #include <image.h> @@ -46,6 +48,13 @@ void bootm_announce_and_cleanup(void) #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); #endif + + /* + * Call remove function of all devices with a removal flag set. + * This may be useful for last-stage operations, like cancelling + * of DMA operation or releasing device internal buffers. + */ + dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); } #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index ceab3cf5e4..b1b4cd9613 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -6,6 +6,7 @@ #include <common.h> #include <vbe.h> +#include <asm/acpi_s3.h> #include <asm/coreboot_tables.h> #include <asm/e820.h> @@ -19,7 +20,11 @@ int high_table_reserve(void) gd->arch.high_table_ptr = gd->start_addr_sp; /* clear the memory */ - memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE); +#ifdef CONFIG_HAVE_ACPI_RESUME + if (gd->arch.prev_sleep_state != ACPI_S3) +#endif + memset((void *)gd->arch.high_table_ptr, 0, + CONFIG_HIGH_TABLE_SIZE); gd->start_addr_sp &= ~0xf; diff --git a/arch/x86/lib/early_cmos.c b/arch/x86/lib/early_cmos.c new file mode 100644 index 0000000000..fa0b3273a8 --- /dev/null +++ b/arch/x86/lib/early_cmos.c @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This library provides CMOS (inside RTC SRAM) access routines at a very + * early stage when driver model is not available yet. Only read access is + * provided. The 16-bit/32-bit read are compatible with driver model RTC + * uclass write ops, that data is stored in little-endian mode. + */ + +#include <common.h> +#include <asm/early_cmos.h> +#include <asm/io.h> + +u8 cmos_read8(u8 addr) +{ + outb(addr, CMOS_IO_PORT); + + return inb(CMOS_IO_PORT + 1); +} + +u16 cmos_read16(u8 addr) +{ + u16 value = 0; + u16 data; + int i; + + for (i = 0; i < sizeof(value); i++) { + data = cmos_read8(addr + i); + value |= data << (i << 3); + } + + return value; +} + +u32 cmos_read32(u8 addr) +{ + u32 value = 0; + u32 data; + int i; + + for (i = 0; i < sizeof(value); i++) { + data = cmos_read8(addr + i); + value |= data << (i << 3); + } + + return value; +} diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 66a388d601..3397bb83ea 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -5,7 +5,12 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> +#include <rtc.h> +#include <asm/acpi_s3.h> +#include <asm/cmos_layout.h> +#include <asm/early_cmos.h> #include <asm/io.h> #include <asm/mrccache.h> #include <asm/post.h> @@ -75,9 +80,41 @@ static __maybe_unused void *fsp_prepare_mrc_cache(void) return cache->data; } +#ifdef CONFIG_HAVE_ACPI_RESUME +int fsp_save_s3_stack(void) +{ + struct udevice *dev; + int ret; + + if (gd->arch.prev_sleep_state == ACPI_S3) + return 0; + + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) { + debug("Cannot find RTC: err=%d\n", ret); + return -ENODEV; + } + + /* Save the stack address to CMOS */ + ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); + if (ret) { + debug("Save stack address to CMOS: err=%d\n", ret); + return -EIO; + } + + return 0; +} +#endif + int arch_fsp_init(void) { void *nvs; + int stack = CONFIG_FSP_TEMP_RAM_ADDR; + int boot_mode = BOOT_FULL_CONFIG; +#ifdef CONFIG_HAVE_ACPI_RESUME + int prev_sleep_state = chipset_prev_sleep_state(); + gd->arch.prev_sleep_state = prev_sleep_state; +#endif if (!gd->arch.hob_list) { #ifdef CONFIG_ENABLE_MRC_CACHE @@ -85,12 +122,36 @@ int arch_fsp_init(void) #else nvs = NULL; #endif + +#ifdef CONFIG_HAVE_ACPI_RESUME + if (prev_sleep_state == ACPI_S3) { + if (nvs == NULL) { + /* If waking from S3 and no cache then */ + debug("No MRC cache found in S3 resume path\n"); + post_code(POST_RESUME_FAILURE); + /* Clear Sleep Type */ + chipset_clear_sleep_state(); + /* Reboot */ + debug("Rebooting..\n"); + reset_cpu(0); + /* Should not reach here.. */ + panic("Reboot System"); + } + + /* + * DM is not avaiable yet at this point, hence call + * CMOS access library which does not depend on DM. + */ + stack = cmos_read32(CMOS_FSP_STACK_ADDR); + boot_mode = BOOT_ON_S3_RESUME; + } +#endif /* * The first time we enter here, call fsp_init(). * Note the execution does not return to this function, * instead it jumps to fsp_continue(). */ - fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, BOOT_FULL_CONFIG, nvs); + fsp_init(stack, boot_mode, nvs); } else { /* * The second time we enter here, adjust the size of malloc() diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 8b880cd594..1a7af576d5 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -92,5 +92,17 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) entries[num_entries].type = E820_RESERVED; num_entries++; +#ifdef CONFIG_HAVE_ACPI_RESUME + /* + * Everything between U-Boot's stack and ram top needs to be + * reserved in order for ACPI S3 resume to work. + */ + entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; + entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \ + CONFIG_STACK_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; +#endif + return num_entries; } diff --git a/board/AndesTech/adp-ae3xx/Kconfig b/board/AndesTech/adp-ae3xx/Kconfig new file mode 100644 index 0000000000..8ec69d611a --- /dev/null +++ b/board/AndesTech/adp-ae3xx/Kconfig @@ -0,0 +1,18 @@ +if TARGET_ADP_AE3XX + +config SYS_CPU + default "n1213" + +config SYS_BOARD + default "adp-ae3xx" + +config SYS_VENDOR + default "AndesTech" + +config SYS_SOC + default "ae3xx" + +config SYS_CONFIG_NAME + default "adp-ae3xx" + +endif diff --git a/board/AndesTech/adp-ae3xx/MAINTAINERS b/board/AndesTech/adp-ae3xx/MAINTAINERS new file mode 100644 index 0000000000..02e5a19c9d --- /dev/null +++ b/board/AndesTech/adp-ae3xx/MAINTAINERS @@ -0,0 +1,6 @@ +ADP-AG101P BOARD +M: Andes <uboot@andestech.com> +S: Maintained +F: board/AndesTech/adp-ae3xx/ +F: include/configs/adp-ae3xx.h +F: configs/adp-ae3xx_defconfig diff --git a/board/AndesTech/adp-ae3xx/Makefile b/board/AndesTech/adp-ae3xx/Makefile new file mode 100644 index 0000000000..842dfb4dcb --- /dev/null +++ b/board/AndesTech/adp-ae3xx/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation <rick@andestech.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := adp-ae3xx.o diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/board/AndesTech/adp-ae3xx/adp-ae3xx.c new file mode 100644 index 0000000000..98ed4d9589 --- /dev/null +++ b/board/AndesTech/adp-ae3xx/adp-ae3xx.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +#include <netdev.h> +#endif +#include <linux/io.h> +#include <faraday/ftsdc010.h> +#include <faraday/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ +int board_init(void) +{ + /* + * refer to BOOT_PARAMETER_PA_BASE within + * "linux/arch/nds32/include/asm/misc_spec.h" + */ + printf("Board: %s\n" , CONFIG_SYS_BOARD); + gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX; + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + return 0; +} + +int dram_init(void) +{ + unsigned long sdram_base = PHYS_SDRAM_0; + unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; + unsigned long actual_size; + actual_size = get_ram_size((void *)sdram_base, expected_size); + gd->ram_size = actual_size; + if (expected_size != actual_size) { + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + } + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) +int board_eth_init(bd_t *bd) +{ + return ftmac100_initialize(bd); +} +#endif + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else { + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_DM_MMC +#ifdef CONFIG_FTSDC010 + ftsdc010_mmc_init(0); +#endif +#endif + return 0; +} diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index 805a266f63..a462941448 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -7,8 +7,10 @@ */ #include <common.h> +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) #include <netdev.h> -#include <asm/io.h> +#endif +#include <linux/io.h> #include <faraday/ftsdc010.h> #include <faraday/ftsmc020.h> @@ -25,6 +27,7 @@ int board_init(void) * refer to BOOT_PARAMETER_PA_BASE within * "linux/arch/nds32/include/asm/misc_spec.h" */ + printf("Board: %s\n" , CONFIG_SYS_BOARD); gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P; gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; @@ -59,10 +62,12 @@ int dram_init_banksize(void) return 0; } +#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) int board_eth_init(bd_t *bd) { return ftmac100_initialize(bd); } +#endif ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) { @@ -78,6 +83,8 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) int board_mmc_init(bd_t *bis) { +#ifdef CONFIG_FTSDC010 ftsdc010_mmc_init(0); +#endif return 0; } diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 5cc82c9473..b1ae079df4 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -684,7 +684,7 @@ int board_eth_init(bd_t *bis) return rv; } #endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */ -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(1, 0, 0, -1, -1); diff --git a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c index 31418a1f96..9205c22e0b 100644 --- a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c +++ b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c @@ -156,17 +156,7 @@ int board_init(void) int board_late_init(void) { - u8 mac[6]; - - /* Read Mac Address and set*/ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); - - /* Read MAC address */ - i2c_read(0x50, 0x0, 0, mac, 6); - - if (is_valid_ethaddr(mac)) - eth_setenv_enetaddr("ethaddr", mac); + printf("Cannot use I2C to get MAC address\n"); return 0; } diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig new file mode 100644 index 0000000000..b80cc6d6f9 --- /dev/null +++ b/board/altera/arria10-socdk/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SOCFPGA_ARRIA10 + +config SYS_CPU + default "armv7" + +config SYS_BOARD + default "socfpga_arria10" + +config SYS_VENDOR + default "altera" + +config SYS_SOC + default "socfpga_arria10" + +config SYS_CONFIG_NAME + default "socfpga_arria10" + +endif diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile new file mode 100644 index 0000000000..1d885cec1f --- /dev/null +++ b/board/altera/arria10-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c new file mode 100644 index 0000000000..85166336f9 --- /dev/null +++ b/board/altera/arria10-socdk/socfpga.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2015 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index c661c77f83..81c2aad1a5 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -212,7 +212,7 @@ int board_init(void) at91sam9x5ek_nand_hw_init(); #endif -#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD) at91_uhp_hw_init(); #endif #ifdef CONFIG_LCD diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index e90693feea..38577f30f1 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -632,7 +632,7 @@ void arch_preboot_os(void) leds_set_finish(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { int ret; diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 7b862355c8..0c647bbd3d 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -161,14 +161,7 @@ int dram_init(void) */ static void read_hw_id(hw_id_t hw_id) { - int i; - for (i = 0; i < HW_ID_ELEM_COUNT; ++i) - if (i2c_read(CONFIG_SYS_I2C_EEPROM, - hw_id_format[i].offset, - 2, - (uchar *)&hw_id[i][0], - hw_id_format[i].length) != 0) - printf("ERROR: can't read HW ID from EEPROM\n"); + printf("ERROR: can't read HW ID from EEPROM\n"); } @@ -221,7 +214,7 @@ static void compose_module_name(hw_id_t hw_id, char *buf) strcat(buf, tmp); } - +#if defined(CONFIG_SYS_I2C_SOFT) /* * Compose string with hostname. * buf is assumed to have enough space, and be null-terminated. @@ -237,7 +230,7 @@ static void compose_hostname(hw_id_t hw_id, char *buf) *p = tolower(*p); } - +#endif #ifdef CONFIG_OF_BOARD_SETUP /* @@ -270,15 +263,6 @@ int checkboard(void) hw_id_t hw_id_tmp; char module_name_tmp[MODULE_NAME_MAXLEN] = ""; - /* - * We need I2C to access HW ID data from EEPROM, so we call i2c_init() - * here despite the fact that it will be called again later on. We - * also use a little trick to silence I2C-related output. - */ - gd->flags |= GD_FLG_SILENT; - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - gd->flags &= ~GD_FLG_SILENT; - read_hw_id(hw_id_tmp); identify_module(hw_id_tmp); /* this sets gd->board_type */ compose_module_name(hw_id_tmp, module_name_tmp); @@ -311,7 +295,7 @@ int board_early_init_r(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) +#if defined(CONFIG_SYS_I2C_SOFT) uchar buf[6]; char str[18]; char hostname[MODULE_NAME_MAXLEN]; @@ -334,16 +318,16 @@ int misc_init_r(void) " device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET); } -#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) */ - if (!getenv("ethaddr")) - printf(LOG_PREFIX "MAC address not set, networking is not " - "operational\n"); - - /* set the hostname appropriate to the module we're running on */ hostname[0] = 0x00; + /* set the hostname appropriate to the module we're running on */ compose_hostname(hw_id, hostname); setenv("hostname", hostname); +#endif /* defined(CONFIG_SYS_I2C_SOFT) */ + if (!getenv("ethaddr")) + printf(LOG_PREFIX "MAC address not set, networking is not " + "operational\n"); + return 0; } #endif /* CONFIG_MISC_INIT_R */ diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 9c40ad7b2a..60097dc8c7 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -13,34 +13,6 @@ #ifdef CONFIG_CMD_BSP -static int do_i2c_test(char * const argv[]) -{ - unsigned char temp, temp1; - - printf("Starting I2C Test\n" - "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n" - "Please press any key to start\n\n"); - getc(); - - temp = 0xf0; /* set io 0-4 as output */ - i2c_write(CONFIG_SYS_I2C_IO, 3, 1, (uchar *)&temp, 1); - - printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" - "Press any key to stop\n\n"); - - while (!tstc()) { - i2c_read(CONFIG_SYS_I2C_IO, 0, 1, (uchar *)&temp, 1); - temp1 = (temp >> 4) & 0x03; - temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ - temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ - temp = temp1; - i2c_write(CONFIG_SYS_I2C_IO, 1, 1, (uchar *)&temp, 1); - } - getc(); - - return 0; -} - static int do_usb_test(char * const argv[]) { int i; @@ -387,9 +359,7 @@ static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) switch (argc) { case 2: - if (strncmp(argv[1], "i2c", 3) == 0) - rcode = do_i2c_test(argv); - else if (strncmp(argv[1], "led", 3) == 0) + if (strncmp(argv[1], "led", 3) == 0) rcode = do_led_test(argv); else if (strncmp(argv[1], "usb", 3) == 0) rcode = do_usb_test(argv); diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c b/board/compulab/cl-som-am57x/cl-som-am57x.c index 4701b71102..389eebb589 100644 --- a/board/compulab/cl-som-am57x/cl-som-am57x.c +++ b/board/compulab/cl-som-am57x/cl-som-am57x.c @@ -33,7 +33,7 @@ int board_init(void) return 0; } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC #define SB_SOM_CD_GPIO 187 #define SB_SOM_WP_GPIO 188 @@ -51,7 +51,7 @@ int board_mmc_init(bd_t *bis) return ret0 && ret1; } -#endif /* CONFIG_GENERIC_MMC */ +#endif /* CONFIG_MMC */ int misc_init_r(void) { diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 2d9dd9d808..f1691257e7 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -372,7 +372,7 @@ void set_muxconf_regs(void) cm_t3730_set_muxconf(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) #define SB_T35_WP_GPIO 59 int board_mmc_getcd(struct mmc *mmc) @@ -391,7 +391,7 @@ int board_mmc_init(bd_t *bis) } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c index b55ded054a..38eb641bc4 100644 --- a/board/compulab/cm_t3517/cm_t3517.c +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -115,7 +115,7 @@ int misc_init_r(void) return 0; } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) #define SB_T35_CD_GPIO 144 #define SB_T35_WP_GPIO 59 diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index 7b58fcd21f..6437718415 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -96,7 +96,7 @@ uint mmc_get_env_part(struct mmc *mmc) } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) #define SB_T54_CD_GPIO 228 #define SB_T54_WP_GPIO 229 @@ -181,7 +181,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 48d65e8b4f..730b8cac73 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -140,14 +140,14 @@ void set_muxconf_regs(void) MUX_TRICORDER(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index e3441cad4e..e389819e9d 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -29,9 +29,6 @@ int misc_init_r(void) { u32 tmp; - /* we use I2C-2 for on-board eeprom */ - i2c_set_bus_num(2); - tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE); printf("FPGA: %u-%u.%u.%u\n", (tmp & 0xFF000000) >> 24, diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile new file mode 100644 index 0000000000..6630fea012 --- /dev/null +++ b/board/engicam/common/Makefile @@ -0,0 +1,7 @@ +# Copyright (C) 2016 Amarula Solutions B.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c new file mode 100644 index 0000000000..af4ef28dac --- /dev/null +++ b/board/engicam/common/board.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki <jagan@amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mmc.h> +#include <asm/arch/sys_proto.h> + +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_ENV_IS_IN_MMC +static void mmc_late_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +int board_late_init(void) +{ + switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> + IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: +#ifdef CONFIG_ENV_IS_IN_MMC + mmc_late_init(); +#endif + setenv("modeboot", "mmcboot"); + break; + case IMX6_BMODE_NAND: + setenv("modeboot", "nandboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + setenv_fdt_file(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_VIDEO_IPUV3 + setup_display(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} diff --git a/board/engicam/common/board.h b/board/engicam/common/board.h new file mode 100644 index 0000000000..f364a23296 --- /dev/null +++ b/board/engicam/common/board.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ +void setenv_fdt_file(void); +void setup_gpmi_nand(void); +void setup_display(void); +#endif /* _BOARD_H_ */ diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c new file mode 100644 index 0000000000..ab0ab986bf --- /dev/null +++ b/board/engicam/common/spl.c @@ -0,0 +1,393 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki <jagan@amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/sizes.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> + +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/video.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart_pads[] = { +#ifdef CONFIG_MX6QDL + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +#elif CONFIG_MX6UL + IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), +#endif +}; + +#ifdef CONFIG_MX6QDL +/* + * Driving strength: + * 0x30 == 40 Ohm + * 0x28 == 48 Ohm + */ +#define IMX6DQ_DRIVE_STRENGTH 0x30 +#define IMX6SDL_DRIVE_STRENGTH 0x28 + +/* configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, + .dram_cas = IMX6DQ_DRIVE_STRENGTH, + .dram_ras = IMX6DQ_DRIVE_STRENGTH, + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, + .dram_reset = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, + .grp_addds = IMX6DQ_DRIVE_STRENGTH, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, + .grp_ddr_type = 0x000c0000, +}; + +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, + .dram_cas = IMX6SDL_DRIVE_STRENGTH, + .dram_ras = IMX6SDL_DRIVE_STRENGTH, + .dram_reset = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6SDL_DRIVE_STRENGTH, + .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, +}; + +/* mt41j256 */ +static struct mx6_ddr3_cfg mt41j256 = { + .mem_speed = 1066, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + .p0_mpwldectrl0 = 0x000E0009, + .p0_mpwldectrl1 = 0x0018000E, + .p1_mpwldectrl0 = 0x00000007, + .p1_mpwldectrl1 = 0x00000000, + .p0_mpdgctrl0 = 0x43280334, + .p0_mpdgctrl1 = 0x031C0314, + .p1_mpdgctrl0 = 0x4318031C, + .p1_mpdgctrl1 = 0x030C0258, + .p0_mprddlctl = 0x3E343A40, + .p1_mprddlctl = 0x383C3844, + .p0_mpwrdlctl = 0x40404440, + .p1_mpwrdlctl = 0x4C3E4446, +}; + +/* DDR 64bit */ +static struct mx6_ddr_sysinfo mem_q = { + .ddr_type = DDR_TYPE_DDR3, + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 2, + .rtt_wr = 2, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { + .p0_mpwldectrl0 = 0x001F0024, + .p0_mpwldectrl1 = 0x00110018, + .p1_mpwldectrl0 = 0x001F0024, + .p1_mpwldectrl1 = 0x00110018, + .p0_mpdgctrl0 = 0x4230022C, + .p0_mpdgctrl1 = 0x02180220, + .p1_mpdgctrl0 = 0x42440248, + .p1_mpdgctrl1 = 0x02300238, + .p0_mprddlctl = 0x44444A48, + .p1_mprddlctl = 0x46484A42, + .p0_mpwrdlctl = 0x38383234, + .p1_mpwrdlctl = 0x3C34362E, +}; + +/* DDR 64bit 1GB */ +static struct mx6_ddr_sysinfo mem_dl = { + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 1, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +/* DDR 32bit 512MB */ +static struct mx6_ddr_sysinfo mem_s = { + .dsize = 1, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 1, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; +#endif /* CONFIG_MX6QDL */ + +#ifdef CONFIG_MX6UL +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, +#ifdef TARGET_MX6UL_ISIOT + .rowaddr = 15, +#else + .rowaddr = 13, +#endif + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; +#endif /* CONFIG_MX6UL */ + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + +#ifdef CONFIG_MX6QDL + writel(0x00003F3F, &ccm->CCGR0); + writel(0x0030FC00, &ccm->CCGR1); + writel(0x000FC000, &ccm->CCGR2); + writel(0x3F300000, &ccm->CCGR3); + writel(0xFF00F300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003CC, &ccm->CCGR6); +#elif CONFIG_MX6UL + writel(0x00c03f3f, &ccm->CCGR0); + writel(0xfcffff00, &ccm->CCGR1); + writel(0x0cffffcc, &ccm->CCGR2); + writel(0x3f3c3030, &ccm->CCGR3); + writel(0xff00fffc, &ccm->CCGR4); + writel(0x033f30ff, &ccm->CCGR5); + writel(0x00c00fff, &ccm->CCGR6); +#endif +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void spl_dram_init(void) +{ +#ifdef CONFIG_MX6QDL + if (is_mx6solo()) { + mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); + } else if (is_mx6dl()) { + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); + } else if (is_mx6dq()) { + mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); + } +#elif CONFIG_MX6UL + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +#endif + + udelay(100); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + gpr_init(); + + /* iomux */ + SETUP_IOMUX_PADS(uart_pads); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c index 40f20a9bec..841ade98c5 100644 --- a/board/engicam/geam6ul/geam6ul.c +++ b/board/engicam/geam6ul/geam6ul.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <mmc.h> #include <asm/io.h> #include <asm/gpio.h> @@ -19,23 +20,9 @@ #include <asm/arch/sys_proto.h> #include <asm/imx-common/iomux-v3.h> -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +#include "../common/board.h" - return 0; -} +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_NAND_MXS @@ -45,29 +32,29 @@ int board_early_init_f(void) #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) static iomux_v3_cfg_t const nand_pads[] = { - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), }; -static void setup_gpmi_nand(void) +void setup_gpmi_nand(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + SETUP_IOMUX_PADS(nand_pads); clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | @@ -103,32 +90,13 @@ static void setup_gpmi_nand(void) } #endif /* CONFIG_NAND_MXS */ -int board_init(void) +void setenv_fdt_file(void) { - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); -#endif - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; + if (is_mx6ul()) + setenv("fdt_file", "imx6ul-geam-kit.dtb"); } #ifdef CONFIG_SPL_BUILD -#include <libfdt.h> -#include <spl.h> - -#include <asm/arch/crm_regs.h> -#include <asm/arch/mx6-ddr.h> - /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include <mmc.h> @@ -139,19 +107,19 @@ int dram_init(void) PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), /* VSELECT */ - MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), /* CD */ - MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RST_B */ - MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) @@ -186,8 +154,7 @@ int board_mmc_init(bd_t *bis) for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + SETUP_IOMUX_PADS(usdhc1_pads); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; @@ -207,111 +174,4 @@ int board_mmc_init(bd_t *bis) return 0; } #endif /* CONFIG_FSL_ESDHC */ - -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000030, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x000c0000, -}; - -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_ras = 0x00000030, - .dram_cas = 0x00000030, - .dram_odt0 = 0x00000030, - .dram_odt1 = 0x00000030, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000008, - .dram_sdqs0 = 0x00000038, - .dram_sdqs1 = 0x00000030, - .dram_reset = 0x00000030, -}; - -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00070007, - .p0_mpdgctrl0 = 0x41490145, - .p0_mprddlctl = 0x40404546, - .p0_mpwrdlctl = 0x4040524D, -}; - -struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs_density = 20, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, -}; - -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 800, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0xFFFFFFFF, &ccm->CCGR0); - writel(0xFFFFFFFF, &ccm->CCGR1); - writel(0xFFFFFFFF, &ccm->CCGR2); - writel(0xFFFFFFFF, &ccm->CCGR3); - writel(0xFFFFFFFF, &ccm->CCGR4); - writel(0xFFFFFFFF, &ccm->CCGR5); - writel(0xFFFFFFFF, &ccm->CCGR6); - writel(0xFFFFFFFF, &ccm->CCGR7); -} - -static void spl_dram_init(void) -{ - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} #endif /* CONFIG_SPL_BUILD */ diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS index 6116648e37..26b4b56d71 100644 --- a/board/engicam/icorem6/MAINTAINERS +++ b/board/engicam/icorem6/MAINTAINERS @@ -3,10 +3,8 @@ M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: board/engicam/icorem6 F: include/configs/imx6qdl_icore.h -F: configs/imx6q_icore_mmc_defconfig -F: configs/imx6q_icore_nand_defconfig -F: configs/imx6dl_icore_mmc_defconfig -F: configs/imx6dl_icore_nand_defconfig +F: configs/imx6qdl_icore_mmc_defconfig +F: configs/imx6qdl_icore_nand_defconfig F: arch/arm/dts/imx6qdl-icore.dtsi F: arch/arm/dts/imx6q-icore.dts F: arch/arm/dts/imx6dl-icore.dts diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index 171ec451a1..74cbbc5c56 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <mmc.h> #include <asm/io.h> #include <asm/gpio.h> @@ -20,16 +21,9 @@ #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/video.h> -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#include "../common/board.h" -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_NAND_MXS @@ -56,7 +50,7 @@ iomux_v3_cfg_t gpmi_pads[] = { IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), }; -static void setup_gpmi_nand(void) +void setup_gpmi_nand(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -149,7 +143,7 @@ struct display_info_t const displays[] = { size_t display_count = ARRAY_SIZE(displays); -static void setup_display(void) +void setup_display(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -198,43 +192,15 @@ static void setup_display(void) } #endif /* CONFIG_VIDEO_IPUV3 */ -int board_early_init_f(void) -{ - SETUP_IOMUX_PADS(uart4_pads); - - return 0; -} - -int board_init(void) +void setenv_fdt_file(void) { - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); -#endif - -#ifdef CONFIG_VIDEO_IPUV3 - setup_display(); -#endif - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; + if (is_mx6dq()) + setenv("fdt_file", "imx6q-icore.dtb"); + else if(is_mx6dl() || is_mx6solo()) + setenv("fdt_file", "imx6dl-icore.dtb"); } #ifdef CONFIG_SPL_BUILD -#include <libfdt.h> -#include <spl.h> - -#include <asm/arch/crm_regs.h> -#include <asm/arch/mx6-ddr.h> - /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include <mmc.h> @@ -307,273 +273,15 @@ int board_mmc_init(bd_t *bis) } #endif -/* - * Driving strength: - * 0x30 == 40 Ohm - * 0x28 == 48 Ohm - */ - -#define IMX6DQ_DRIVE_STRENGTH 0x30 -#define IMX6SDL_DRIVE_STRENGTH 0x28 - -/* configure MX6Q/DUAL mmdc DDR io registers */ -static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { - .dram_sdqs0 = 0x28, - .dram_sdqs1 = 0x28, - .dram_sdqs2 = 0x28, - .dram_sdqs3 = 0x28, - .dram_sdqs4 = 0x28, - .dram_sdqs5 = 0x28, - .dram_sdqs6 = 0x28, - .dram_sdqs7 = 0x28, - .dram_dqm0 = 0x28, - .dram_dqm1 = 0x28, - .dram_dqm2 = 0x28, - .dram_dqm3 = 0x28, - .dram_dqm4 = 0x28, - .dram_dqm5 = 0x28, - .dram_dqm6 = 0x28, - .dram_dqm7 = 0x28, - .dram_cas = 0x30, - .dram_ras = 0x30, - .dram_sdclk_0 = 0x30, - .dram_sdclk_1 = 0x30, - .dram_reset = 0x30, - .dram_sdcke0 = 0x3000, - .dram_sdcke1 = 0x3000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x30, - .dram_sdodt1 = 0x30, -}; - -/* configure MX6Q/DUAL mmdc GRP io registers */ -static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { - .grp_b0ds = 0x30, - .grp_b1ds = 0x30, - .grp_b2ds = 0x30, - .grp_b3ds = 0x30, - .grp_b4ds = 0x30, - .grp_b5ds = 0x30, - .grp_b6ds = 0x30, - .grp_b7ds = 0x30, - .grp_addds = 0x30, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ctlds = 0x30, - .grp_ddr_type = 0x000c0000, -}; - -/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ -struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { - .dram_sdclk_0 = 0x30, - .dram_sdclk_1 = 0x30, - .dram_cas = 0x30, - .dram_ras = 0x30, - .dram_reset = 0x30, - .dram_sdcke0 = 0x30, - .dram_sdcke1 = 0x30, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x30, - .dram_sdodt1 = 0x30, - .dram_sdqs0 = 0x28, - .dram_sdqs1 = 0x28, - .dram_sdqs2 = 0x28, - .dram_sdqs3 = 0x28, - .dram_sdqs4 = 0x28, - .dram_sdqs5 = 0x28, - .dram_sdqs6 = 0x28, - .dram_sdqs7 = 0x28, - .dram_dqm0 = 0x28, - .dram_dqm1 = 0x28, - .dram_dqm2 = 0x28, - .dram_dqm3 = 0x28, - .dram_dqm4 = 0x28, - .dram_dqm5 = 0x28, - .dram_dqm6 = 0x28, - .dram_dqm7 = 0x28, -}; - -/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ -struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x30, - .grp_ctlds = 0x30, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x28, - .grp_b1ds = 0x28, - .grp_b2ds = 0x28, - .grp_b3ds = 0x28, - .grp_b4ds = 0x28, - .grp_b5ds = 0x28, - .grp_b6ds = 0x28, - .grp_b7ds = 0x28, -}; - -/* mt41j256 */ -static struct mx6_ddr3_cfg mt41j256 = { - .mem_speed = 1066, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 0, -}; - -static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { - .p0_mpwldectrl0 = 0x000E0009, - .p0_mpwldectrl1 = 0x0018000E, - .p1_mpwldectrl0 = 0x00000007, - .p1_mpwldectrl1 = 0x00000000, - .p0_mpdgctrl0 = 0x43280334, - .p0_mpdgctrl1 = 0x031C0314, - .p1_mpdgctrl0 = 0x4318031C, - .p1_mpdgctrl1 = 0x030C0258, - .p0_mprddlctl = 0x3E343A40, - .p1_mprddlctl = 0x383C3844, - .p0_mpwrdlctl = 0x40404440, - .p1_mpwrdlctl = 0x4C3E4446, -}; - -/* DDR 64bit */ -static struct mx6_ddr_sysinfo mem_q = { - .ddr_type = DDR_TYPE_DDR3, - .dsize = 2, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 2, - .rtt_wr = 2, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { - .p0_mpwldectrl0 = 0x001F0024, - .p0_mpwldectrl1 = 0x00110018, - .p1_mpwldectrl0 = 0x001F0024, - .p1_mpwldectrl1 = 0x00110018, - .p0_mpdgctrl0 = 0x4230022C, - .p0_mpdgctrl1 = 0x02180220, - .p1_mpdgctrl0 = 0x42440248, - .p1_mpdgctrl1 = 0x02300238, - .p0_mprddlctl = 0x44444A48, - .p1_mprddlctl = 0x46484A42, - .p0_mpwrdlctl = 0x38383234, - .p1_mpwrdlctl = 0x3C34362E, -}; - -/* DDR 64bit 1GB */ -static struct mx6_ddr_sysinfo mem_dl = { - .dsize = 2, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 1, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -/* DDR 32bit 512MB */ -static struct mx6_ddr_sysinfo mem_s = { - .dsize = 1, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 1, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00003F3F, &ccm->CCGR0); - writel(0x0030FC00, &ccm->CCGR1); - writel(0x000FC000, &ccm->CCGR2); - writel(0x3F300000, &ccm->CCGR3); - writel(0xFF00F300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003CC, &ccm->CCGR6); -} - -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - -static void spl_dram_init(void) -{ - if (is_mx6solo()) { - mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); - } else if (is_mx6dl()) { - mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); - } else if (is_mx6dq()) { - mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); - mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); - } - - udelay(100); -} - -void board_init_f(ulong dummy) +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) { - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - gpr_init(); - - /* iomux */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); + if (is_mx6dq() && !strcmp(name, "imx6q-icore")) + return 0; + else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) + return 0; + else + return -1; } #endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS index 2d2295c3c5..74470ba59f 100644 --- a/board/engicam/icorem6_rqs/MAINTAINERS +++ b/board/engicam/icorem6_rqs/MAINTAINERS @@ -3,8 +3,7 @@ M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: board/engicam/icorem6_rqs F: include/configs/imx6qdl_icore_rqs.h -F: configs/imx6q_icore_rqs_mmc_defconfig -F: configs/imx6dl_icore_rqs_mmc_defconfig +F: configs/imx6qdl_icore_rqs_mmc_defconfig F: arch/arm/dts/imx6qdl-icore-rqs.dtsi F: arch/arm/dts/imx6q-icore-rqs.dts F: arch/arm/dts/imx6dl-icore-rqs.dts diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c index 01380f1269..c3c3173f51 100644 --- a/board/engicam/icorem6_rqs/icorem6_rqs.c +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -20,31 +20,9 @@ #include <asm/arch/sys_proto.h> #include <asm/imx-common/iomux-v3.h> -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart4_pads[] = { - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -}; - -int board_early_init_f(void) -{ - SETUP_IOMUX_PADS(uart4_pads); - - return 0; -} - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#include "../common/board.h" - return 0; -} +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_ENV_IS_IN_MMC int board_mmc_get_env_dev(int devno) @@ -52,59 +30,19 @@ int board_mmc_get_env_dev(int devno) /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ return (devno == 3) ? 1 : 0; } - -static void mmc_late_init(void) -{ - char cmd[32]; - char mmcblk[32]; - u32 dev_no = mmc_get_env_dev(); - - setenv_ulong("mmcdev", dev_no); - - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); - setenv("mmcroot", mmcblk); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); -} #endif -int board_late_init(void) +void setenv_fdt_file(void) { - switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> - IMX6_BMODE_SHIFT) { - case IMX6_BMODE_SD: - case IMX6_BMODE_ESD: - case IMX6_BMODE_MMC: - case IMX6_BMODE_EMMC: -#ifdef CONFIG_ENV_IS_IN_MMC - mmc_late_init(); -#endif - setenv("modeboot", "mmcboot"); - break; - default: - setenv("modeboot", ""); - break; - } - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; + if (is_mx6dq()) + setenv("fdt_file", "imx6q-icore-rqs.dtb"); + else if(is_mx6dl() || is_mx6solo()) + setenv("fdt_file", "imx6dl-icore-rqs.dtb"); } #ifdef CONFIG_SPL_BUILD -#include <libfdt.h> #include <spl.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/mx6-ddr.h> - /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include <mmc.h> @@ -219,273 +157,15 @@ void board_boot_order(u32 *spl_boot_list) #endif #endif -/* - * Driving strength: - * 0x30 == 40 Ohm - * 0x28 == 48 Ohm - */ - -#define IMX6DQ_DRIVE_STRENGTH 0x30 -#define IMX6SDL_DRIVE_STRENGTH 0x28 - -/* configure MX6Q/DUAL mmdc DDR io registers */ -static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { - .dram_sdqs0 = 0x28, - .dram_sdqs1 = 0x28, - .dram_sdqs2 = 0x28, - .dram_sdqs3 = 0x28, - .dram_sdqs4 = 0x28, - .dram_sdqs5 = 0x28, - .dram_sdqs6 = 0x28, - .dram_sdqs7 = 0x28, - .dram_dqm0 = 0x28, - .dram_dqm1 = 0x28, - .dram_dqm2 = 0x28, - .dram_dqm3 = 0x28, - .dram_dqm4 = 0x28, - .dram_dqm5 = 0x28, - .dram_dqm6 = 0x28, - .dram_dqm7 = 0x28, - .dram_cas = 0x30, - .dram_ras = 0x30, - .dram_sdclk_0 = 0x30, - .dram_sdclk_1 = 0x30, - .dram_reset = 0x30, - .dram_sdcke0 = 0x3000, - .dram_sdcke1 = 0x3000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x30, - .dram_sdodt1 = 0x30, -}; - -/* configure MX6Q/DUAL mmdc GRP io registers */ -static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { - .grp_b0ds = 0x30, - .grp_b1ds = 0x30, - .grp_b2ds = 0x30, - .grp_b3ds = 0x30, - .grp_b4ds = 0x30, - .grp_b5ds = 0x30, - .grp_b6ds = 0x30, - .grp_b7ds = 0x30, - .grp_addds = 0x30, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ctlds = 0x30, - .grp_ddr_type = 0x000c0000, -}; - -/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ -struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { - .dram_sdclk_0 = 0x30, - .dram_sdclk_1 = 0x30, - .dram_cas = 0x30, - .dram_ras = 0x30, - .dram_reset = 0x30, - .dram_sdcke0 = 0x30, - .dram_sdcke1 = 0x30, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x30, - .dram_sdodt1 = 0x30, - .dram_sdqs0 = 0x28, - .dram_sdqs1 = 0x28, - .dram_sdqs2 = 0x28, - .dram_sdqs3 = 0x28, - .dram_sdqs4 = 0x28, - .dram_sdqs5 = 0x28, - .dram_sdqs6 = 0x28, - .dram_sdqs7 = 0x28, - .dram_dqm0 = 0x28, - .dram_dqm1 = 0x28, - .dram_dqm2 = 0x28, - .dram_dqm3 = 0x28, - .dram_dqm4 = 0x28, - .dram_dqm5 = 0x28, - .dram_dqm6 = 0x28, - .dram_dqm7 = 0x28, -}; - -/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ -struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { - .grp_ddr_type = 0x000c0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x30, - .grp_ctlds = 0x30, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x28, - .grp_b1ds = 0x28, - .grp_b2ds = 0x28, - .grp_b3ds = 0x28, - .grp_b4ds = 0x28, - .grp_b5ds = 0x28, - .grp_b6ds = 0x28, - .grp_b7ds = 0x28, -}; - -/* mt41j256 */ -static struct mx6_ddr3_cfg mt41j256 = { - .mem_speed = 1066, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, - .SRT = 0, -}; - -static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { - .p0_mpwldectrl0 = 0x000E0009, - .p0_mpwldectrl1 = 0x0018000E, - .p1_mpwldectrl0 = 0x00000007, - .p1_mpwldectrl1 = 0x00000000, - .p0_mpdgctrl0 = 0x43280334, - .p0_mpdgctrl1 = 0x031C0314, - .p1_mpdgctrl0 = 0x4318031C, - .p1_mpdgctrl1 = 0x030C0258, - .p0_mprddlctl = 0x3E343A40, - .p1_mprddlctl = 0x383C3844, - .p0_mpwrdlctl = 0x40404440, - .p1_mpwrdlctl = 0x4C3E4446, -}; - -/* DDR 64bit */ -static struct mx6_ddr_sysinfo mem_q = { - .ddr_type = DDR_TYPE_DDR3, - .dsize = 2, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 2, - .rtt_wr = 2, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { - .p0_mpwldectrl0 = 0x001F0024, - .p0_mpwldectrl1 = 0x00110018, - .p1_mpwldectrl0 = 0x001F0024, - .p1_mpwldectrl1 = 0x00110018, - .p0_mpdgctrl0 = 0x4230022C, - .p0_mpdgctrl1 = 0x02180220, - .p1_mpdgctrl0 = 0x42440248, - .p1_mpdgctrl1 = 0x02300238, - .p0_mprddlctl = 0x44444A48, - .p1_mprddlctl = 0x46484A42, - .p0_mpwrdlctl = 0x38383234, - .p1_mpwrdlctl = 0x3C34362E, -}; - -/* DDR 64bit 1GB */ -static struct mx6_ddr_sysinfo mem_dl = { - .dsize = 2, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 1, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -/* DDR 32bit 512MB */ -static struct mx6_ddr_sysinfo mem_s = { - .dsize = 1, - .cs1_mirror = 0, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 1, - .ralat = 5, - .walat = 0, - .mif3_mode = 3, - .rst_to_cke = 0x23, - .sde_to_rst = 0x10, -}; - -static void ccgr_init(void) +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) { - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00003F3F, &ccm->CCGR0); - writel(0x0030FC00, &ccm->CCGR1); - writel(0x000FC000, &ccm->CCGR2); - writel(0x3F300000, &ccm->CCGR3); - writel(0xFF00F300, &ccm->CCGR4); - writel(0x0F0000C3, &ccm->CCGR5); - writel(0x000003CC, &ccm->CCGR6); -} - -static void gpr_init(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* enable AXI cache for VDOA/VPU/IPU */ - writel(0xF00000CF, &iomux->gpr[4]); - /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); -} - -static void spl_dram_init(void) -{ - if (is_mx6solo()) { - mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); - } else if (is_mx6dl()) { - mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); - mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); - } else if (is_mx6dq()) { - mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); - mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); - } - - udelay(100); -} - -void board_init_f(ulong dummy) -{ - ccgr_init(); - - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - gpr_init(); - - /* iomux */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); + if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) + return 0; + else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) + return 0; + else + return -1; } #endif +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c index 29a137dc81..105db73f6d 100644 --- a/board/engicam/isiotmx6ul/isiotmx6ul.c +++ b/board/engicam/isiotmx6ul/isiotmx6ul.c @@ -20,23 +20,9 @@ #include <asm/arch/sys_proto.h> #include <asm/imx-common/iomux-v3.h> -DECLARE_GLOBAL_DATA_PTR; - -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#include "../common/board.h" -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -int board_early_init_f(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); - - return 0; -} +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_NAND_MXS @@ -46,29 +32,29 @@ int board_early_init_f(void) #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) static iomux_v3_cfg_t const nand_pads[] = { - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), + IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), }; -static void setup_gpmi_nand(void) +void setup_gpmi_nand(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + SETUP_IOMUX_PADS(nand_pads); clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | @@ -110,73 +96,22 @@ int board_mmc_get_env_dev(int devno) /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ return (devno == 0) ? 0 : 1; } - -static void mmc_late_init(void) -{ - char cmd[32]; - char mmcblk[32]; - u32 dev_no = mmc_get_env_dev(); - - setenv_ulong("mmcdev", dev_no); - - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); - setenv("mmcroot", mmcblk); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); -} #endif -int board_late_init(void) +void setenv_fdt_file(void) { - switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> - IMX6_BMODE_SHIFT) { - case IMX6_BMODE_SD: - case IMX6_BMODE_ESD: - case IMX6_BMODE_MMC: - case IMX6_BMODE_EMMC: + if (is_mx6ul()) { #ifdef CONFIG_ENV_IS_IN_MMC - mmc_late_init(); + setenv("fdt_file", "imx6ul-isiot-emmc.dtb"); +#else + setenv("fdt_file", "imx6ul-isiot-nand.dtb"); #endif - setenv("modeboot", "mmcboot"); - break; - case IMX6_BMODE_NAND: - setenv("modeboot", "nandboot"); - break; - default: - setenv("modeboot", ""); - break; } - - return 0; -} - -int board_init(void) -{ - /* Address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - -#ifdef CONFIG_NAND_MXS - setup_gpmi_nand(); -#endif - return 0; -} - -int dram_init(void) -{ - gd->ram_size = imx_ddr_size(); - - return 0; } #ifdef CONFIG_SPL_BUILD -#include <libfdt.h> #include <spl.h> -#include <asm/arch/crm_regs.h> -#include <asm/arch/mx6-ddr.h> - /* MMC board initialization is needed till adding DM support in SPL */ #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) #include <mmc.h> @@ -187,31 +122,31 @@ int dram_init(void) PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), /* VSELECT */ - MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)), /* CD */ - MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RST_B */ - MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) @@ -252,14 +187,12 @@ int board_mmc_init(bd_t *bis) for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + SETUP_IOMUX_PADS(usdhc1_pads); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); break; case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc2_pads)); + SETUP_IOMUX_PADS(usdhc2_pads); gpio_direction_input(USDHC2_CD_GPIO); usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; @@ -305,110 +238,4 @@ void board_boot_order(u32 *spl_boot_list) } #endif #endif /* CONFIG_FSL_ESDHC */ - -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000030, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x000c0000, -}; - -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_ras = 0x00000030, - .dram_cas = 0x00000030, - .dram_odt0 = 0x00000030, - .dram_odt1 = 0x00000030, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000008, - .dram_sdqs0 = 0x00000038, - .dram_sdqs1 = 0x00000030, - .dram_reset = 0x00000030, -}; - -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00070007, - .p0_mpdgctrl0 = 0x41490145, - .p0_mprddlctl = 0x40404546, - .p0_mpwrdlctl = 0x4040524D, -}; - -struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs_density = 20, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, -}; - -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 800, - .density = 4, - .width = 16, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0x00c03f3f, &ccm->CCGR0); - writel(0xfcffff00, &ccm->CCGR1); - writel(0x0cffffcc, &ccm->CCGR2); - writel(0x3f3c3030, &ccm->CCGR3); - writel(0xff00fffc, &ccm->CCGR4); - writel(0x033f30ff, &ccm->CCGR5); - writel(0x00c00fff, &ccm->CCGR6); -} - -static void spl_dram_init(void) -{ - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} #endif /* CONFIG_SPL_BUILD */ diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index 66dc407bae..78a6b66110 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -18,17 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; int eeprom_write_enable(unsigned dev_addr, int state) { - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR) - return -1; - - if (state == 0) - setbits_be32(&im->gpio.gpdat, 0x00100000); - else - clrbits_be32(&im->gpio.gpdat, 0x00100000); - - return 0; + return -ENOSYS; } int board_early_init_f(void) diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 8a9a9be8ce..53b606ebb5 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -1,6 +1,19 @@ config CHAIN_OF_TRUST depends on !FIT_SIGNATURE && SECURE_BOOT imply CMD_BLOB + imply CMD_HASH if ARM select FSL_CAAM + select SPL_BOARD_INIT if (ARM && SPL) + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL bool default y + +config CMD_ESBC_VALIDATE + bool "Enable the 'esbc_validate' and 'esbc_halt' commands" + default y if CHAIN_OF_TRUST + help + This option enables two commands used for secure booting: + + esbc_validate - validate signature using RSA verification + esbc_halt - put the core in spin loop (Secure Boot Only) diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README index 92a83849ac..89e033e1c5 100644 --- a/board/freescale/m52277evb/README +++ b/board/freescale/m52277evb/README @@ -83,7 +83,6 @@ CONFIG_MCFTMR -- define to use DMA timer CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged CONFIG_SYS_I2C_SPEED -- define for I2C speed CONFIG_SYS_I2C_SLAVE -- define for I2C slave address diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index c2cc2d76e4..3318368623 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -88,7 +88,7 @@ int testdram(void) return (0); } -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #include <ata.h> int ide_preinit(void) { @@ -133,7 +133,7 @@ void ide_set_reset(int idereset) setbits_8(&ata->cr, 0x01); } } -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ #ifdef CONFIG_DRIVER_DM9000 diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index c1ed431190..2c6afadb9a 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -81,7 +81,7 @@ int testdram(void) return (0); } -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #include <ata.h> int ide_preinit(void) { @@ -126,4 +126,4 @@ void ide_set_reset(int idereset) setbits_8(&ata->cr, 0x01); } } -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 224e79c46a..2fca12c417 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -91,7 +91,6 @@ CONFIG_MCFTMR -- define to use DMA timer CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged CONFIG_SYS_I2C_SPEED -- define for I2C speed CONFIG_SYS_I2C_SLAVE -- define for I2C slave address diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index 582e0c3d9e..757f0abdd7 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -90,7 +90,6 @@ CONFIG_MCFTMR -- define to use DMA timer CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged CONFIG_SYS_I2C_SPEED -- define for I2C speed CONFIG_SYS_I2C_SLAVE -- define for I2C slave address diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README index c563ad99a7..4a8719333a 100644 --- a/board/freescale/m54455evb/README +++ b/board/freescale/m54455evb/README @@ -113,7 +113,6 @@ CONFIG_MCFTMR -- define to use DMA timer CONFIG_MCFPIT -- define to use PIT timer CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver -CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged CONFIG_SYS_I2C_SPEED -- define for I2C speed CONFIG_SYS_I2C_SLAVE -- define for I2C slave address diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index d6b0650b99..1e35970023 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -88,7 +88,7 @@ int testdram(void) return (0); } -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) #include <ata.h> int ide_preinit(void) diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README index 30c5dedafe..ce7b27b8b2 100644 --- a/board/freescale/m547xevb/README +++ b/board/freescale/m547xevb/README @@ -98,7 +98,6 @@ CONFIG_DOS_PARTITION -- enable DOS read/write CONFIG_SLTTMR -- define to use SLT timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged CONFIG_SYS_I2C_SPEED -- define for I2C speed CONFIG_SYS_I2C_SLAVE -- define for I2C slave address diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index f87579f193..d729056fd0 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -174,27 +174,6 @@ int dram_init(void) int misc_init_r(void) { - u8 tmp_val; - - /* Using this for DIU init before the driver in linux takes over - * Enable the TFP410 Encoder (I2C address 0x38) - */ - - i2c_set_bus_num(2); - tmp_val = 0xBF; - i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); - /* Verify if enabled */ - tmp_val = 0; - i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02x\n", tmp_val); - - tmp_val = 0x10; - i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); - /* Verify if enabled */ - tmp_val = 0; - i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); - debug("DVI Encoder Read: 0x%02x\n", tmp_val); - return 0; } diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg deleted file mode 100644 index be9f87f666..0000000000 --- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ - -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ - -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020e0774 0x000C0000 -DATA 4 0x020e0754 0x00000000 -DATA 4 0x020e04ac 0x00000030 -DATA 4 0x020e04b0 0x00000030 -DATA 4 0x020e0464 0x00000030 -DATA 4 0x020e0490 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0494 0x00000030 -DATA 4 0x020e04a0 0x00000000 -DATA 4 0x020e04b4 0x00000030 -DATA 4 0x020e04b8 0x00000030 -DATA 4 0x020e076c 0x00000030 -DATA 4 0x020e0750 0x00020000 -DATA 4 0x020e04bc 0x00000030 -DATA 4 0x020e04c0 0x00000030 -DATA 4 0x020e04c4 0x00000030 -DATA 4 0x020e04c8 0x00000030 -DATA 4 0x020e04cc 0x00000030 -DATA 4 0x020e04d0 0x00000030 -DATA 4 0x020e04d4 0x00000030 -DATA 4 0x020e04d8 0x00000030 -DATA 4 0x020e0760 0x00020000 -DATA 4 0x020e0764 0x00000030 -DATA 4 0x020e0770 0x00000030 -DATA 4 0x020e0778 0x00000030 -DATA 4 0x020e077c 0x00000030 -DATA 4 0x020e0780 0x00000030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e0470 0x00000030 -DATA 4 0x020e0474 0x00000030 -DATA 4 0x020e0478 0x00000030 -DATA 4 0x020e047c 0x00000030 -DATA 4 0x020e0480 0x00000030 -DATA 4 0x020e0484 0x00000030 -DATA 4 0x020e0488 0x00000030 -DATA 4 0x020e048c 0x00000030 -DATA 4 0x021b0800 0xa1390003 -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F -DATA 4 0x021b480c 0x001F001F -DATA 4 0x021b4810 0x001F001F -DATA 4 0x021b083c 0x4220021F -DATA 4 0x021b0840 0x0207017E -DATA 4 0x021b483c 0x4201020C -DATA 4 0x021b4840 0x01660172 -DATA 4 0x021b0848 0x4A4D4E4D -DATA 4 0x021b4848 0x4A4F5049 -DATA 4 0x021b0850 0x3F3C3D31 -DATA 4 0x021b4850 0x3238372B -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 -DATA 4 0x021b0004 0x0002002D -DATA 4 0x021b0008 0x00333030 -DATA 4 0x021b000c 0x3F435313 -DATA 4 0x021b0010 0xB66E8B63 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b0018 0x00001740 -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b002c 0x000026d2 -DATA 4 0x021b0030 0x00431023 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0x831A0000 -DATA 4 0x021b001c 0x04008032 -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x00048031 -DATA 4 0x021b001c 0x05208030 -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00011117 -DATA 4 0x021b4818 0x00011117 -DATA 4 0x021b0004 0x0002556D -DATA 4 0x021b0404 0x00011006 -DATA 4 0x021b001c 0x00000000 - -/* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg deleted file mode 100644 index bb6c60b4c3..0000000000 --- a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu <r64343@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ -DATA 4 0x020e05a8 0x00000030 -DATA 4 0x020e05b0 0x00000030 -DATA 4 0x020e0524 0x00000030 -DATA 4 0x020e051c 0x00000030 - -DATA 4 0x020e0518 0x00000030 -DATA 4 0x020e050c 0x00000030 -DATA 4 0x020e05b8 0x00000030 -DATA 4 0x020e05c0 0x00000030 - -DATA 4 0x020e05ac 0x00020030 -DATA 4 0x020e05b4 0x00020030 -DATA 4 0x020e0528 0x00020030 -DATA 4 0x020e0520 0x00020030 - -DATA 4 0x020e0514 0x00020030 -DATA 4 0x020e0510 0x00020030 -DATA 4 0x020e05bc 0x00020030 -DATA 4 0x020e05c4 0x00020030 - -DATA 4 0x020e056c 0x00020030 -DATA 4 0x020e0578 0x00020030 -DATA 4 0x020e0588 0x00020030 -DATA 4 0x020e0594 0x00020030 - -DATA 4 0x020e057c 0x00020030 -DATA 4 0x020e0590 0x00003000 -DATA 4 0x020e0598 0x00003000 -DATA 4 0x020e058c 0x00000000 - -DATA 4 0x020e059c 0x00003030 -DATA 4 0x020e05a0 0x00003030 -DATA 4 0x020e0784 0x00000030 -DATA 4 0x020e0788 0x00000030 - -DATA 4 0x020e0794 0x00000030 -DATA 4 0x020e079c 0x00000030 -DATA 4 0x020e07a0 0x00000030 -DATA 4 0x020e07a4 0x00000030 - -DATA 4 0x020e07a8 0x00000030 -DATA 4 0x020e0748 0x00000030 -DATA 4 0x020e074c 0x00000030 -DATA 4 0x020e0750 0x00020000 - -DATA 4 0x020e0758 0x00000000 -DATA 4 0x020e0774 0x00020000 -DATA 4 0x020e078c 0x00000030 -DATA 4 0x020e0798 0x000C0000 - -DATA 4 0x021b081c 0x33333333 -DATA 4 0x021b0820 0x33333333 -DATA 4 0x021b0824 0x33333333 -DATA 4 0x021b0828 0x33333333 - -DATA 4 0x021b481c 0x33333333 -DATA 4 0x021b4820 0x33333333 -DATA 4 0x021b4824 0x33333333 -DATA 4 0x021b4828 0x33333333 - -DATA 4 0x021b0018 0x00081740 - -DATA 4 0x021b001c 0x00008000 -DATA 4 0x021b000c 0x555A7974 -DATA 4 0x021b0010 0xDB538F64 -DATA 4 0x021b0014 0x01FF00DB -DATA 4 0x021b002c 0x000026D2 - -DATA 4 0x021b0030 0x005A1023 -DATA 4 0x021b0008 0x09444040 -DATA 4 0x021b0004 0x00025576 -DATA 4 0x021b0040 0x00000027 -DATA 4 0x021b0000 0x831A0000 - -DATA 4 0x021b001c 0x04088032 -DATA 4 0x021b001c 0x0408803A -DATA 4 0x021b001c 0x00008033 -DATA 4 0x021b001c 0x0000803B -DATA 4 0x021b001c 0x00428031 -DATA 4 0x021b001c 0x00428039 -DATA 4 0x021b001c 0x19308030 -DATA 4 0x021b001c 0x19308038 - -DATA 4 0x021b001c 0x04008040 -DATA 4 0x021b001c 0x04008048 -DATA 4 0x021b0800 0xA1380003 -DATA 4 0x021b4800 0xA1380003 -DATA 4 0x021b0020 0x00005800 -DATA 4 0x021b0818 0x00022227 -DATA 4 0x021b4818 0x00022227 - -DATA 4 0x021b083c 0x434B0350 -DATA 4 0x021b0840 0x034C0359 -DATA 4 0x021b483c 0x434B0350 -DATA 4 0x021b4840 0x03650348 -DATA 4 0x021b0848 0x4436383B -DATA 4 0x021b4848 0x39393341 -DATA 4 0x021b0850 0x35373933 -DATA 4 0x021b4850 0x48254A36 - -DATA 4 0x021b080c 0x001F001F -DATA 4 0x021b0810 0x001F001F - -DATA 4 0x021b480c 0x00440044 -DATA 4 0x021b4810 0x00440044 - -DATA 4 0x021b08b8 0x00000800 -DATA 4 0x021b48b8 0x00000800 - -DATA 4 0x021b001c 0x00000000 -DATA 4 0x021b0404 0x00011006 - -/* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F - -/* - * Setup CCM_CCOSR register as follows: - * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root - * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz - */ -DATA 4 0x020c4060 0x000000fb diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 80a77892c9..f4a5d9cff9 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -28,7 +28,6 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" -#include <asm/arch/mx6-ddr.h> #include <usb.h> DECLARE_GLOBAL_DATA_PTR; @@ -66,33 +65,33 @@ int dram_init(void) } static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), /* AR8031 PHY Reset */ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static void setup_iomux_enet(void) { - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + SETUP_IOMUX_PADS(enet_pads); /* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); @@ -102,98 +101,98 @@ static void setup_iomux_enet(void) } static iomux_v3_cfg_t const usdhc2_pads[] = { - MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ }; static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static iomux_v3_cfg_t const rgb_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static iomux_v3_cfg_t const bl_pads[] = { - MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static void enable_backlight(void) { - imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads)); + SETUP_IOMUX_PADS(bl_pads); gpio_direction_output(DISP0_PWR_EN, 1); } static void enable_rgb(struct display_info_t const *dev) { - imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); + SETUP_IOMUX_PADS(rgb_pads); enable_backlight(); } @@ -202,43 +201,56 @@ static void enable_lvds(struct display_info_t const *dev) enable_backlight(); } -static struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info mx6q_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +static struct i2c_pads_info mx6dl_i2c_pad_info1 = { .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, .gp = IMX_GPIO_NR(4, 13) } }; static void setup_spi(void) { - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + SETUP_IOMUX_PADS(ecspi1_pads); } iomux_v3_cfg_t const pcie_pads[] = { - MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ - MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */ }; static void setup_pcie(void) { - imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); + SETUP_IOMUX_PADS(pcie_pads); } iomux_v3_cfg_t const di0_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ + IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */ + IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */ + IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */ }; static void setup_iomux_uart(void) { - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + SETUP_IOMUX_PADS(uart1_pads); } #ifdef CONFIG_FSL_ESDHC @@ -292,20 +304,17 @@ int board_mmc_init(bd_t *bis) for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + SETUP_IOMUX_PADS(usdhc2_pads); gpio_direction_input(USDHC2_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); break; case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + SETUP_IOMUX_PADS(usdhc3_pads); gpio_direction_input(USDHC3_CD_GPIO); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); break; case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + SETUP_IOMUX_PADS(usdhc4_pads); usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); break; default: @@ -335,22 +344,19 @@ int board_mmc_init(bd_t *bis) switch (reg & 0x3) { case 0x1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + SETUP_IOMUX_PADS(usdhc2_pads); usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; break; case 0x2: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; break; case 0x3: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + SETUP_IOMUX_PADS(usdhc4_pads); usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; @@ -484,7 +490,7 @@ static void setup_display(void) int reg; /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ - imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); + SETUP_IOMUX_PADS(di0_pads); enable_ipu_clock(); imx_setup_hdmi(); @@ -555,18 +561,17 @@ int board_eth_init(bd_t *bis) #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static iomux_v3_cfg_t const usb_hc1_pads[] = { - MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static void setup_usb(void) { - imx_iomux_v3_setup_multiple_pads(usb_otg_pads, - ARRAY_SIZE(usb_otg_pads)); + SETUP_IOMUX_PADS(usb_otg_pads); /* * set daisy chain for otg_pin_id on 6q. @@ -574,8 +579,7 @@ static void setup_usb(void) */ imx_iomux_set_gpr_register(1, 13, 1, 0); - imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, - ARRAY_SIZE(usb_hc1_pads)); + SETUP_IOMUX_PADS(usb_hc1_pads); } int board_ehci_hcd_init(int port) @@ -631,8 +635,10 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - + if (is_mx6dq() || is_mx6dqp()) + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); + else + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif @@ -714,6 +720,7 @@ int checkboard(void) } #ifdef CONFIG_SPL_BUILD +#include <asm/arch/mx6-ddr.h> #include <spl.h> #include <libfdt.h> @@ -939,6 +946,92 @@ static int mx6qp_dcd_table[] = { 0x021b001c, 0x00000000, }; +static int mx6dl_dcd_table[] = { + 0x020e0774, 0x000C0000, + 0x020e0754, 0x00000000, + 0x020e04ac, 0x00000030, + 0x020e04b0, 0x00000030, + 0x020e0464, 0x00000030, + 0x020e0490, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e0494, 0x00000030, + 0x020e04a0, 0x00000000, + 0x020e04b4, 0x00000030, + 0x020e04b8, 0x00000030, + 0x020e076c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e04bc, 0x00000030, + 0x020e04c0, 0x00000030, + 0x020e04c4, 0x00000030, + 0x020e04c8, 0x00000030, + 0x020e04cc, 0x00000030, + 0x020e04d0, 0x00000030, + 0x020e04d4, 0x00000030, + 0x020e04d8, 0x00000030, + 0x020e0760, 0x00020000, + 0x020e0764, 0x00000030, + 0x020e0770, 0x00000030, + 0x020e0778, 0x00000030, + 0x020e077c, 0x00000030, + 0x020e0780, 0x00000030, + 0x020e0784, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e0470, 0x00000030, + 0x020e0474, 0x00000030, + 0x020e0478, 0x00000030, + 0x020e047c, 0x00000030, + 0x020e0480, 0x00000030, + 0x020e0484, 0x00000030, + 0x020e0488, 0x00000030, + 0x020e048c, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x4220021F, + 0x021b0840, 0x0207017E, + 0x021b483c, 0x4201020C, + 0x021b4840, 0x01660172, + 0x021b0848, 0x4A4D4E4D, + 0x021b4848, 0x4A4F5049, + 0x021b0850, 0x3F3C3D31, + 0x021b4850, 0x3238372B, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x0002002D, + 0x021b0008, 0x00333030, + 0x021b000c, 0x3F435313, + 0x021b0010, 0xB66E8B63, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x00431023, + 0x021b0040, 0x00000027, + 0x021b0000, 0x831A0000, + 0x021b001c, 0x04008032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x05208030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x0002556D, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + static void ddr_init(int *table, int size) { int i; @@ -953,6 +1046,8 @@ static void spl_dram_init(void) ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); else if (is_mx6dqp()) ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); + else if (is_mx6sdl()) + ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table)); } void board_init_f(ulong dummy) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 6ccdd4b33b..ecea5a529a 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -23,25 +23,17 @@ #include <i2c.h> #include <asm/imx-common/mxc_i2c.h> #include <asm/arch/crm_regs.h> -#include <usb.h> -#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) @@ -54,23 +46,8 @@ DECLARE_GLOBAL_DATA_PTR; (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, - .gp = IMX_GPIO_NR(4, 8), - }, - .sda = { - .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, - .gp = IMX_GPIO_NR(4, 9), - }, -}; -#endif +#ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi3_pads[] = { MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -87,6 +64,7 @@ static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); } +#endif int dram_init(void) { @@ -104,130 +82,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usb_otg1_pads[] = { - MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usb_otg2_pads[] = { - MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -#define IOX_SDI IMX_GPIO_NR(1, 9) -#define IOX_STCP IMX_GPIO_NR(1, 12) -#define IOX_SHCP IMX_GPIO_NR(1, 13) - -static iomux_v3_cfg_t const iox_pads[] = { - /* IOX_SDI */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_STCP */ - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_SHCP */ - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -/* - * PCIE_DIS_B --> Q0 - * PCIE_RST_B --> Q1 - * HDMI_RST_B --> Q2 - * PERI_RST_B --> Q3 - * SENSOR_RST_B --> Q4 - * ENET_RST_B --> Q5 - * PERI_3V3_EN --> Q6 - * LCD_PWR_EN --> Q7 - */ -enum qn { - PCIE_DIS_B, - PCIE_RST_B, - HDMI_RST_B, - PERI_RST_B, - SENSOR_RST_B, - ENET_RST_B, - PERI_3V3_EN, - LCD_PWR_EN, -}; - -enum qn_func { - qn_reset, - qn_enable, - qn_disable, -}; - -enum qn_level { - qn_low = 0, - qn_high = 1, -}; - -static enum qn_level seq[3][2] = { - {0, 1}, {1, 1}, {0, 0} -}; - -static enum qn_func qn_output[8] = { - qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, - qn_disable -}; - -static void iox74lv_init(void) -{ - int i; - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); -}; - #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -306,11 +160,13 @@ static int setup_lcd(void) imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); /* Reset LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); udelay(500); gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); return 0; @@ -346,17 +202,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -#ifdef CONFIG_FSL_ESDHC - -#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) -#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC1_BASE_ADDR, 0, 4}, - {USDHC3_BASE_ADDR}, -}; - int board_mmc_get_env_dev(int devno) { if (devno == 2) @@ -365,7 +210,7 @@ int board_mmc_get_env_dev(int devno) return devno; } -static int mmc_map_to_kernel_blk(int dev_no) +int mmc_map_to_kernel_blk(int dev_no) { if (dev_no == 1) dev_no++; @@ -373,106 +218,27 @@ static int mmc_map_to_kernel_blk(int dev_no) return dev_no; } -int board_mmc_getcd(struct mmc *mmc) +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* Assume uSDHC3 emmc is always present */ - break; - } - - return ret; -} + int ret; + unsigned int gpio; -int board_mmc_init(bd_t *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc2 USDHC3 (eMMC) - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); - gpio_direction_input(USDHC1_CD_GPIO); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); - gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); - gpio_direction_output(USDHC3_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC3_PWR_GPIO, 1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; + ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio); + if (ret) { + printf("GPIO: 'gpio_spi@0_5' not found\n"); + return -ENODEV; } - return 0; -} - -static int check_mmc_autodetect(void) -{ - char *autodetect_str = getenv("mmcautodetect"); - - if ((autodetect_str != NULL) && - (strcmp(autodetect_str, "yes") == 0)) { - return 1; + ret = gpio_request(gpio, "fec_rst"); + if (ret && ret != -EBUSY) { + printf("gpio: requesting pin %u failed\n", gpio); + return ret; } - return 0; -} - -static void mmc_late_init(void) -{ - char cmd[32]; - char mmcblk[32]; - u32 dev_no = mmc_get_env_dev(); - - if (!check_mmc_autodetect()) - return; - - setenv_ulong("mmcdev", dev_no); - - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", - mmc_map_to_kernel_blk(dev_no)); - setenv("mmcroot", mmcblk); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); -} - -#endif - -#ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - int ret; + gpio_direction_output(gpio, 0); + udelay(500); + gpio_direction_output(gpio, 1); setup_iomux_fec(); @@ -539,12 +305,6 @@ int board_early_init_f(void) { setup_iomux_uart(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, - ARRAY_SIZE(usb_otg1_pads)); - imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, - ARRAY_SIZE(usb_otg2_pads)); - return 0; } @@ -553,10 +313,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); - - iox74lv_init(); - #ifdef CONFIG_FEC_MXC setup_fec(); #endif @@ -580,29 +336,23 @@ int board_init(void) return 0; } -#ifdef CONFIG_POWER -#define I2C_PMIC 0 +#ifdef CONFIG_DM_PMIC int power_init_board(void) { - struct pmic *p; - int ret; - unsigned int reg, rev_id; + struct udevice *dev; + int ret, dev_id, rev_id; - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("PFUZE3000"); - ret = pmic_probe(p); - if (ret) + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) return ret; - pmic_reg_read(p, PFUZE3000_DEVICEID, ®); - pmic_reg_read(p, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - /* disable Low Power Mode during standby mode */ - pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1); + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); return 0; } @@ -612,10 +362,6 @@ int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; -#ifdef CONFIG_ENV_IS_IN_MMC - mmc_late_init(); -#endif - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); @@ -642,13 +388,3 @@ int checkboard(void) return 0; } - -#ifdef CONFIG_USB_EHCI_MX7 -int board_usb_phy_mode(int port) -{ - if (port == 0) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; -} -#endif diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig index ccce98e2ed..5d1bae41ac 100644 --- a/board/gateworks/gw_ventana/Kconfig +++ b/board/gateworks/gw_ventana/Kconfig @@ -9,4 +9,17 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "gw_ventana" +config CMD_EECONFIG + bool "Enable the 'econfig' command" + help + Provides access to EEPROM configuration on Gateworks Ventana + +config CMD_GSC + bool "Enable the 'gsc' command" + help + Provides access to the GSC configuration: + + gsc sleep - sleeps for a period of seconds + gsc wd - enables / disables the watchdog + endif diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index c4c2d23532..a68ec69f18 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1090,6 +1090,12 @@ void ft_board_pci_fixup(void *blob, bd_t *bd) } #endif /* if defined(CONFIG_CMD_PCI) */ +void ft_board_wdog_fixup(void *blob, const char *path) +{ + ft_delprop_path(blob, path, "ext-reset-output"); + ft_delprop_path(blob, path, "fsl,ext-reset-output"); +} + /* * called prior to booting kernel or by 'fdt boardsetup' command * @@ -1172,8 +1178,7 @@ int ft_board_setup(void *blob, bd_t *bd) /* GW51xx-E adds WDOG1_B external reset */ if (rev < 'E') - ft_delprop_path(blob, WDOG1_PATH, - "fsl,ext-reset-output"); + ft_board_wdog_fixup(blob, WDOG1_PATH); break; case GW52xx: @@ -1203,23 +1208,19 @@ int ft_board_setup(void *blob, bd_t *bd) strstr((const char *)info->model, "SP331-B")) gpio_cfg[board_type].usd_vsel = 0; - /* GW520x-E adds WDOG1_B external reset */ - if (info->model[4] == '0' && rev < 'E') - ft_delprop_path(blob, WDOG1_PATH, - "fsl,ext-reset-output"); - /* GW522x-B adds WDOG1_B external reset */ - if (info->model[4] == '2' && rev < 'B') - ft_delprop_path(blob, WDOG1_PATH, - "fsl,ext-reset-output"); + ft_board_wdog_fixup(blob, WDOG1_PATH); } + + /* GW520x-E adds WDOG1_B external reset */ + else if (info->model[4] == '0' && rev < 'E') + ft_board_wdog_fixup(blob, WDOG1_PATH); break; case GW53xx: /* GW53xx-E adds WDOG1_B external reset */ if (rev < 'E') - ft_delprop_path(blob, WDOG1_PATH, - "fsl,ext-reset-output"); + ft_board_wdog_fixup(blob, WDOG1_PATH); break; case GW54xx: @@ -1233,8 +1234,7 @@ int ft_board_setup(void *blob, bd_t *bd) /* GW54xx-E adds WDOG2_B external reset */ if (rev < 'E') - ft_delprop_path(blob, WDOG2_PATH, - "fsl,ext-reset-output"); + ft_board_wdog_fixup(blob, WDOG2_PATH); break; case GW551x: @@ -1283,8 +1283,7 @@ int ft_board_setup(void *blob, bd_t *bd) /* GW551x-C adds WDOG1_B external reset */ if (rev < 'C') - ft_delprop_path(blob, WDOG1_PATH, - "fsl,ext-reset-output"); + ft_board_wdog_fixup(blob, WDOG1_PATH); break; } diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index e400d1945a..b531786653 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -10,7 +10,6 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/ppc4xx-gpio.h> -#include <dtt.h> #include "405ep.h" #include <gdsys_fpga.h> @@ -61,8 +60,13 @@ struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; int misc_init_r(void) { - /* startup fans */ - dtt_init(); + /* + * Note: DTT has been removed. Please use UCLASS_THERMAL. + * + * startup fans + * + * dtt_init(); + */ return 0; } diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index 81b49659ff..1484469bb0 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -11,7 +11,6 @@ #include <asm/io.h> #include <asm/ppc4xx-gpio.h> -#include <dtt.h> #include <miiphy.h> #include "405ep.h" @@ -41,8 +40,13 @@ struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; int misc_init_r(void) { - /* startup fans */ - dtt_init(); + /* + * Note: DTT has been removed. Please use UCLASS_THERMAL. + * + * startup fans + * + * dtt_init(); + */ return 0; } diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c index ff0edb2547..ad88af2d46 100644 --- a/board/gdsys/405ep/neo.c +++ b/board/gdsys/405ep/neo.c @@ -10,7 +10,6 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/ppc4xx-gpio.h> -#include <dtt.h> #include "405ep.h" #include <gdsys_fpga.h> @@ -32,8 +31,13 @@ struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; int misc_init_r(void) { - /* startup fans */ - dtt_init(); + /* + * Note: DTT has been removed. Please use UCLASS_THERMAL. + * + * startup fans + * + * dtt_init(); + */ return 0; } diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index 0a7baaa9db..9ef965bbfa 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -26,7 +26,6 @@ #include <miiphy.h> #include <i2c.h> -#include <dtt.h> DECLARE_GLOBAL_DATA_PTR; @@ -70,8 +69,13 @@ static inline void blank_string(int size) */ int misc_init_r(void) { - /* startup fans */ - dtt_init(); + /* + * Note: DTT has been removed. Please use UCLASS_THERMAL. + * + * startup fans + * + * dtt_init(); + */ #ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 9a1a3a2f28..cb29c25c65 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -23,3 +23,8 @@ config SYS_CONFIG_NAME default "strider" endif + +config CMD_IOLOOP + bool "Enable 'ioloop' and 'ioreflect' commands" + help + These commands provide FPGA tests. diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c index 11d2d7f45f..fefcde87ae 100644 --- a/board/gumstix/duovero/duovero.c +++ b/board/gumstix/duovero/duovero.c @@ -24,7 +24,7 @@ static void setup_net_chip(void); #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #include <usb.h> #include <asm/arch/ehci.h> #include <asm/ehci-omap.h> @@ -110,7 +110,7 @@ void set_muxconf_regs(void) sizeof(struct pad_conf_entry)); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); @@ -206,7 +206,7 @@ int board_eth_init(bd_t *bis) return rc; } -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 0f0eb3acb8..47bce4daa6 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -341,7 +341,7 @@ int board_init(void) return 0; } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC static int init_dwmmc(void) { diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index 12358f1b61..1deb2bdd8b 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -19,7 +19,7 @@ #include <asm/arch/clock.h> #include <errno.h> #include <i2c.h> -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #include <usb.h> #include <asm/ehci-omap.h> #endif @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Address of the framebuffer in RAM. */ #define FB_START_ADDRESS 0x88000000 -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c index 348613736d..cd79e804a0 100644 --- a/board/ifm/ac14xx/ac14xx.c +++ b/board/ifm/ac14xx/ac14xx.c @@ -17,7 +17,6 @@ #include <i2c.h> #endif -static int eeprom_diag; static int mac_diag; static int gpio_diag; @@ -136,7 +135,6 @@ struct __attribute__ ((__packed__)) eeprom_layout { #define HW_COMP_MAINCPU 2 static struct eeprom_layout eeprom_content; -static int eeprom_was_read; /* has_been_read */ static int eeprom_is_valid; static int eeprom_version; @@ -153,53 +151,7 @@ static int eeprom_version; static int read_eeprom(void) { - int eeprom_datalen; - int ret; - - if (eeprom_was_read) - return 0; - - eeprom_is_valid = 0; - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uchar *)&eeprom_content, sizeof(eeprom_content)); - if (eeprom_diag) { - printf("DIAG: %s() read rc[%d], size[%d]\n", - __func__, ret, sizeof(eeprom_content)); - } - - if (ret != 0) - return -1; - - eeprom_was_read = 1; - - /* - * check validity of EEPROM content - * (check version, length, optionally checksum) - */ - eeprom_is_valid = 1; - eeprom_datalen = get_eeprom_field_int(eeprom_content.len); - eeprom_version = get_eeprom_field_int(eeprom_content.version); - - if (eeprom_diag) { - printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n", - __func__, eeprom_content.magic[0], - eeprom_content.magic[1], eeprom_content.magic[2], - eeprom_datalen, eeprom_version, eeprom_content.type); - } - if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0) - eeprom_is_valid = 0; - if (eeprom_datalen < sizeof(struct eeprom_layout) - 5) - eeprom_is_valid = 0; - if ((eeprom_version != 1) && (eeprom_version != 2)) - eeprom_is_valid = 0; - if (eeprom_content.type != HW_COMP_MAINCPU) - eeprom_is_valid = 0; - - if (eeprom_diag) - printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid); - - return ret; + return -ENOSYS; } int mac_read_from_eeprom(void) @@ -324,9 +276,6 @@ int misc_init_r(void) char *s; int want_recovery; - /* we use bus I2C-0 for the on-board eeprom */ - i2c_set_bus_num(0); - /* setup GPIO directions and initial values */ gpio_configure(); diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c index b8bc0459f8..6c33eeb022 100644 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -325,7 +325,7 @@ void pci_init_board(void) } #endif -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #ifdef CONFIG_IDE_RESET @@ -369,7 +369,7 @@ void ide_set_reset(int idereset) setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); } #endif /* CONFIG_IDE_RESET */ -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ #ifdef CONFIG_OF_BOARD_SETUP static void ft_delete_node(void *fdt, const char *compat) diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index d3914a1884..843d35eb2d 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -199,14 +199,14 @@ int board_eth_init(bd_t *bis) static inline void setup_net_chip(void) {} #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index ea24eaa5c0..52d2766e9a 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -259,7 +259,7 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) void init_ide_reset (void) { diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index 51b4571d40..f5a98b33e7 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -153,13 +153,8 @@ const iop_conf_t iop_conf_tab[4][32] = { { 0, 0, 0, 0, 0, 0 }, /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_HARD_I2C) - { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */ - { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */ -#else { 1, 0, 0, 0, 1, 1 }, /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */ -#endif { 0, 0, 0, 0, 0, 0 }, /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 079509c979..85785ffc02 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -76,10 +76,6 @@ static const u32 kwmpp_config[] = { MPP8_GPIO, /* SDA */ MPP9_GPIO, /* SCL */ #endif -#if defined(CONFIG_HARD_I2C) - MPP8_TW_SDA, - MPP9_TW_SCK, -#endif MPP10_UART0_TXD, MPP11_UART0_RXD, MPP12_GPO, /* Reserved */ diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 1aaeb8d75f..5d2d997e42 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -152,7 +152,7 @@ void set_muxconf_regs(void) MUX_AM3517EVM(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig index 03d272a806..68d40dcd62 100644 --- a/board/logicpd/omap3som/Kconfig +++ b/board/logicpd/omap3som/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "omap3_logic" +source "board/ti/common/Kconfig" + endif diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index ce17db6bf9..7990dd2513 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -229,14 +229,14 @@ int board_late_init(void) } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 0fad23af62..e91f874a2b 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -106,7 +106,7 @@ void set_muxconf_regs(void) MUX_ZOOM1_MDK(); } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/overo/overo.c b/board/overo/overo.c index 5e447262bc..adf33cfd37 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -27,7 +27,7 @@ #include <asm/mach-types.h> #include "overo.h" -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #include <usb.h> #include <asm/ehci-omap.h> #endif @@ -379,21 +379,21 @@ int board_eth_init(bd_t *bis) } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); } #endif -#if defined(CONFIG_USB_EHCI) +#if defined(CONFIG_USB_EHCI_HCD) static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, @@ -420,4 +420,4 @@ int ehci_hcd_stop(void) return omap_ehci_hcd_stop(); } -#endif /* CONFIG_USB_EHCI */ +#endif /* CONFIG_USB_EHCI_HCD */ diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index b371a40d32..3502bbf5a9 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -121,7 +121,7 @@ void set_muxconf_regs(void) } } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index 9db31d3312..371bcd9e6b 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -169,36 +169,6 @@ int misc_init_r(void) clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000); #endif -#if defined(CONFIG_HARD_I2C) - if (!getenv("ethaddr")) { - uchar buf[6]; - uchar ifm_oui[3] = { 0, 2, 1, }; - int ret; - - /* I2C-0 for on-board eeprom */ - i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM); - - /* Read ethaddr from EEPROM */ - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6); - if (ret != 0) { - printf("Error: Unable to read MAC from I2C" - " EEPROM at address %02X:%02X\n", - CONFIG_SYS_I2C_EEPROM_ADDR, - CONFIG_SYS_I2C_EEPROM_MAC_OFFSET); - return 1; - } - - /* Owned by IFM ? */ - if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) { - printf("Illegal MAC address in EEPROM: %pM\n", buf); - return 1; - } - - eth_setenv_enetaddr("ethaddr", buf); - } -#endif /* defined(CONFIG_HARD_I2C) */ - return 0; } diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c index 983559e81e..bdd980da91 100644 --- a/board/phytec/pcm030/pcm030.c +++ b/board/phytec/pcm030/pcm030.c @@ -176,7 +176,7 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif /* CONFIG_OF_BOARD_SETUP */ -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) #define GPIO_PSC2_4 0x02000000UL @@ -206,4 +206,4 @@ void ide_set_reset(int idereset) } else setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); } -#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ +#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */ diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c index 7a1a61e386..6cf54095f5 100644 --- a/board/quipos/cairo/cairo.c +++ b/board/quipos/cairo/cairo.c @@ -26,18 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; /* - * MUSB port on OMAP3EVM Rev >= E requires extvbus programming. - */ -u8 omap3_evm_need_extvbus(void) -{ - u8 retval = 0; - - /* TODO: verify if cairo handheld platform needs extvbus programming */ - - return retval; -} - -/* * Routine: board_init * Description: Early hardware init. */ @@ -62,7 +50,7 @@ void set_muxconf_regs(void) MUX_CAIRO(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c index 360e0a1a6f..d0b4537513 100644 --- a/board/renesas/r0p7734/r0p7734.c +++ b/board/renesas/r0p7734/r0p7734.c @@ -44,17 +44,7 @@ int board_init(void) int board_late_init(void) { - u8 mac[6]; - - /* Read Mac Address and set*/ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); - - /* Read MAC address */ - i2c_read(0x50, 0x10, 0, mac, 6); - - if (is_valid_ethaddr(mac)) - eth_setenv_enetaddr("ethaddr", mac); + printf("Cannot get MAC address from I2C\n"); return 0; } diff --git a/board/renesas/salvator-x/MAINTAINERS b/board/renesas/salvator-x/MAINTAINERS index abd05c88e0..f7b98fb097 100644 --- a/board/renesas/salvator-x/MAINTAINERS +++ b/board/renesas/salvator-x/MAINTAINERS @@ -3,4 +3,5 @@ M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> S: Maintained F: board/renesas/salvator-x/ F: include/configs/salvator-x.h -F: configs/salvator-x_defconfig +F: configs/r8a7795_salvator-x_defconfig +F: configs/r8a7796_salvator-x_defconfig diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 0164306b52..6270de4e40 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -1,8 +1,8 @@ /* * board/renesas/salvator-x/salvator-x.c - * This file is Salvator-X board support. + * This file is Salvator-X/Salvator-XS board support. * - * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015-2017 Renesas Electronics Corporation * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * SPDX-License-Identifier: GPL-2.0+ @@ -22,6 +22,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/rmobile.h> #include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> #include <i2c.h> #include <mmc.h> @@ -44,10 +45,21 @@ void s_init(void) writel(0xFFFFFFFF, CPGWPR); } -#define GSX_MSTP112 (1 << 12) /* 3DG */ -#define TMU0_MSTP125 (1 << 25) /* secure */ -#define TMU1_MSTP124 (1 << 24) /* non-secure */ -#define SCIF2_MSTP310 (1 << 10) /* SCIF2 */ +#define GSX_MSTP112 BIT(12) /* 3DG */ +#define TMU0_MSTP125 BIT(25) /* secure */ +#define TMU1_MSTP124 BIT(24) /* non-secure */ +#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ +#define ETHERAVB_MSTP812 BIT(12) +#define DVFS_MSTP926 BIT(26) +#define SD0_MSTP314 BIT(14) +#define SD1_MSTP313 BIT(13) +#define SD2_MSTP312 BIT(12) /* either MMC0 */ +#define SD3_MSTP311 BIT(11) /* either MMC1 */ + +#define SD0CKCR 0xE6150074 +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE6150268 +#define SD3CKCR 0xE615026C int board_early_init_f(void) { @@ -55,7 +67,22 @@ int board_early_init_f(void) mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); /* SCIF2 */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); + /* EHTERAVB */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); + /* eMMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); + /* SDHI0, 3 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311); + + writel(0, SD0CKCR); + writel(0, SD1CKCR); + writel(0, SD2CKCR); + writel(0, SD3CKCR); +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); +#endif return 0; } @@ -65,29 +92,203 @@ int board_early_init_f(void) /* -/W 32 Power resume control register 2 (3DG) */ #define SYSC_PWRONCR2 0xE618010C -DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; /* Init PFC controller */ +#if defined(CONFIG_R8A7795) r8a7795_pinmux_init(); +#elif defined(CONFIG_R8A7796) + r8a7796_pinmux_init(); +#endif +#if defined(CONFIG_R8A7795) /* GSX: force power and clock supply */ writel(0x0000001F, SYSC_PWRONCR2); while (readl(SYSC_PWRSR2) != 0x000003E0) mdelay(20); mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); +#endif + + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + +#ifdef CONFIG_RAVB + /* EtherAVB Enable */ + /* GPSR2 */ + gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); + gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); + gpio_request(GPIO_GFN_AVB_LINK, NULL); + gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); + gpio_request(GPIO_GFN_AVB_MAGIC, NULL); + gpio_request(GPIO_GFN_AVB_MDC, NULL); + + /* IPSR0 */ + gpio_request(GPIO_IFN_AVB_MDC, NULL); + gpio_request(GPIO_IFN_AVB_MAGIC, NULL); + gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); + gpio_request(GPIO_IFN_AVB_LINK, NULL); + gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); + gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); + /* IPSR1 */ + gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); + /* IPSR2 */ + gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); + /* IPSR3 */ + gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); + +#if defined(CONFIG_R8A7795) + /* USB2_OVC */ + gpio_request(GPIO_GP_6_15, NULL); + gpio_direction_input(GPIO_GP_6_15); + + /* USB2_PWEN */ + gpio_request(GPIO_GP_6_14, NULL); + gpio_direction_output(GPIO_GP_6_14, 1); + gpio_set_value(GPIO_GP_6_14, 1); +#endif + /* AVB_PHY_RST */ + gpio_request(GPIO_GP_2_10, NULL); + gpio_direction_output(GPIO_GP_2_10, 0); + mdelay(20); + gpio_set_value(GPIO_GP_2_10, 1); + udelay(1); +#endif return 0; } +static struct eth_pdata salvator_x_ravb_platdata = { + .iobase = 0xE6800000, + .phy_interface = 0, + .max_speed = 1000, +}; + +U_BOOT_DEVICE(salvator_x_ravb) = { + .name = "ravb", + .platdata = &salvator_x_ravb_platdata, +}; + +#ifdef CONFIG_SH_SDHI +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; + + /* SDHI0 */ + gpio_request(GPIO_GFN_SD0_DAT0, NULL); + gpio_request(GPIO_GFN_SD0_DAT1, NULL); + gpio_request(GPIO_GFN_SD0_DAT2, NULL); + gpio_request(GPIO_GFN_SD0_DAT3, NULL); + gpio_request(GPIO_GFN_SD0_CLK, NULL); + gpio_request(GPIO_GFN_SD0_CMD, NULL); + gpio_request(GPIO_GFN_SD0_CD, NULL); + gpio_request(GPIO_GFN_SD0_WP, NULL); + + gpio_request(GPIO_GP_5_2, NULL); + gpio_request(GPIO_GP_5_1, NULL); + gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ + gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_64BIT_BUF); + if (ret) + return ret; + + /* SDHI1/SDHI2 eMMC */ + gpio_request(GPIO_GFN_SD1_DAT0, NULL); + gpio_request(GPIO_GFN_SD1_DAT1, NULL); + gpio_request(GPIO_GFN_SD1_DAT2, NULL); + gpio_request(GPIO_GFN_SD1_DAT3, NULL); + gpio_request(GPIO_GFN_SD2_DAT0, NULL); + gpio_request(GPIO_GFN_SD2_DAT1, NULL); + gpio_request(GPIO_GFN_SD2_DAT2, NULL); + gpio_request(GPIO_GFN_SD2_DAT3, NULL); + gpio_request(GPIO_GFN_SD2_CLK, NULL); +#if defined(CONFIG_R8A7795) + gpio_request(GPIO_GFN_SD2_CMD, NULL); +#elif defined(CONFIG_R8A7796) + gpio_request(GPIO_FN_SD2_CMD, NULL); +#else +#error Only R8A7795 and R87796 is supported +#endif + gpio_request(GPIO_GP_5_3, NULL); + gpio_request(GPIO_GP_5_9, NULL); + gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ + gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1, + SH_SDHI_QUIRK_64BIT_BUF); + if (ret) + return ret; + +#if defined(CONFIG_R8A7795) + /* SDHI3 */ + gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */ + gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */ + gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */ + gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */ + gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */ + gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */ +#elif defined(CONFIG_R8A7796) + gpio_request(GPIO_FN_SD3_DAT0, NULL); /* GP_4_9 */ + gpio_request(GPIO_FN_SD3_DAT1, NULL); /* GP_4_10 */ + gpio_request(GPIO_FN_SD3_DAT2, NULL); /* GP_4_11 */ + gpio_request(GPIO_FN_SD3_DAT3, NULL); /* GP_4_12 */ + gpio_request(GPIO_FN_SD3_CLK, NULL); /* GP_4_7 */ + gpio_request(GPIO_FN_SD3_CMD, NULL); /* GP_4_8 */ +#else +#error Only R8A7795 and R87796 is supported +#endif + /* IPSR10 */ + gpio_request(GPIO_FN_SD3_CD, NULL); + gpio_request(GPIO_FN_SD3_WP, NULL); + + gpio_request(GPIO_GP_3_15, NULL); + gpio_request(GPIO_GP_3_14, NULL); + gpio_direction_output(GPIO_GP_3_15, 1); /* power on */ + gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2, + SH_SDHI_QUIRK_64BIT_BUF); + return ret; +} +#endif + int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = PHYS_SDRAM_1_SIZE; +#if (CONFIG_NR_DRAM_BANKS >= 2) + gd->ram_size += PHYS_SDRAM_2_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 3) + gd->ram_size += PHYS_SDRAM_3_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 4) + gd->ram_size += PHYS_SDRAM_4_SIZE; +#endif + + return 0; +} +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +#if (CONFIG_NR_DRAM_BANKS >= 2) + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 3) + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 4) + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; +#endif return 0; } @@ -103,15 +304,19 @@ const struct rmobile_sysinfo sysinfo = { void reset_cpu(ulong addr) { +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) + i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); +#else /* only CA57 ? */ writel(RST_CODE, RST_CA57RESCNT); +#endif } static const struct sh_serial_platdata serial_platdata = { .base = SCIF2_BASE, .type = PORT_SCIF, - .clk = 14745600, /* 0xE10000 */ - .clk_mode = EXT_CLK, + .clk = CONFIG_SH_SCIF_CLK_FREQ, + .clk_mode = INT_CLK, }; U_BOOT_DEVICE(salvator_x_scif2) = { diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 405ed3b923..49ed3248ad 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -71,7 +71,7 @@ int dram_init_banksize(void) return 0; } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC int board_mmc_init(bd_t *bis) { int ret; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 49e4db2de9..17626966aa 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -250,7 +250,7 @@ int board_eth_init(bd_t *bis) return 0; } -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC static int init_mmc(void) { #ifdef CONFIG_MMC_SDHCI diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 203136fb97..dc4dead20b 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -208,7 +208,7 @@ mode_cmd[BOOT_MODE_EXIT + 1] = { static void display_board_info(void) { -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC struct mmc *mmc = find_mmc_device(0); #endif vidinfo_t *vid = &panel_info; @@ -226,7 +226,7 @@ static void display_board_info(void) lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS); lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M); -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC if (mmc) { if (!mmc->capacity) mmc_init(mmc); diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 35ed398df6..12593830e9 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -72,7 +72,7 @@ int checkboard(void) } #endif -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC int board_mmc_init(bd_t *bis) { int i, ret, ret_sd = 0; diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index c730ac082b..027755de84 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -87,7 +87,7 @@ int checkboard(void) } #endif -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC int board_mmc_init(bd_t *bis) { int i, err; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1c8817375d..a512a201d0 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -72,7 +72,6 @@ F: configs/q8_a33_tablet_1024x600_defconfig F: include/configs/sun9i.h F: configs/Merrii_A80_Optimus_defconfig F: include/configs/sun50i.h -F: configs/pine64_plus_defconfig A20-OLIMEX-SOM-EVB BOARD M: Marcus Cooper <codekipper@gmail.com> @@ -263,6 +262,11 @@ M: Andre Przywara <andre.przywara@arm.com> S: Maintained F: configs/orangepi_pc2_defconfig +PINE64 BOARDS +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/pine64_plus_defconfig + R16 EVB PARROT BOARD M: Quentin Schulz <quentin.schulz@free-electrons.com> S: Maintained diff --git a/board/sunxi/README.pine64 b/board/sunxi/README.pine64 deleted file mode 100644 index 5553415270..0000000000 --- a/board/sunxi/README.pine64 +++ /dev/null @@ -1,98 +0,0 @@ -Pine64 board README -==================== - -The Pine64(+) is a single board computer equipped with an AArch64 capable ARMv8 -compliant Allwinner A64 SoC. -This chip has ARM Cortex A-53 cores and thus can run both in AArch32 -(compatible to 32-bit ARMv7) and AArch64 modes. Upon reset the SoC starts -in AArch32 mode and executes 32-bit code from the Boot ROM (BROM). -This has some implications on U-Boot. - -Quick start -============ -- Get hold of a boot0.img file (see below for more details). -- Get the boot0img tool source from the tools directory in [1] and compile - that on your host. -- Build U-Boot: -$ export CROSS_COMPILE=aarch64-linux-gnu- -$ make pine64_plus_defconfig -$ make -- You also need a compiled ARM Trusted Firmware (ATF) binary. Checkout the - "allwinner" branch from the github repository [2] and build it: -$ export CROSS_COMPILE=aarch64-linux-gnu- -$ make PLAT=sun50iw1p1 DEBUG=1 bl31 - The resulting binary is build/sun50iw1p1/debug/bl31.bin. - -Now put an empty (or disposable) micro SD card in your card reader and learn -its device file name, replacing /dev/sd<x> below with the result (that could -be /dev/mmcblk<x> as well): - -$ ./boot0img --device /dev/sd<x> -e -u u-boot.bin -B boot0.img \ - -d trampoline64:0x44000 -s bl31.bin -a 0x44008 -p 100 -(either copying the respective files to the working directory or specifying -the paths directly) - -This will create a new partition table (with a 100 MB FAT boot partition), -copies boot0.img, ATF and U-Boot to the proper locations on the SD card and -will fill in the magic Allwinner header to be recognized by boot0. -Prefix the above call with "sudo" if you don't have write access to the -uSD card. You can also use "-o output.img" instead of "--device /dev/sd<x>" -to create an image file and "dd" that to the uSD card. -Omitting the "-p" option will skip the partition table. - -Now put this uSD card in the board and power it on. You should be greeted by -the U-Boot prompt. - - -Main U-Boot -============ -The main U-Boot proper is a real 64-bit ARMv8 port and runs entirely in the -64-bit AArch64 mode. It can load any AArch64 code, EFI applications or arm64 -Linux kernel images (often named "Image") using the booti command. -Launching 32-bit code and kernels is technically possible, though not without -drawbacks (or hacks to avoid them) and currently not implemented. - -SPL support -============ -The main task of the SPL support is to bring up the DRAM controller and make -DRAM actually accessible. At the moment there is no documentation or source -code available which would do this. -There are currently two ways to overcome this situation: using a tainted 32-bit -SPL (involving some hacks and resulting in a non-redistributable binary, thus -not described here) or using the Allwinner boot0 blob. - -boot0 method -------------- -boot0 is Allwiner's secondary program loader and it can be used as some kind -of SPL replacement to get U-Boot up and running. -The binary is a 32 KByte blob and contained on every Pine64 image distributed -so far. It can be easily extracted from a micro SD card or an image file: -# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4 -where /dev/sd<x> is the device name of the uSD card or the name of the image -file. Apparently Allwinner allows re-distribution of this proprietary code -as-is. -For the time being this boot0 blob is the only redistributable way of making -U-Boot work on the Pine64. Beside loading the various parts of the (original) -firmware it also switches the core into AArch64 mode. -The original boot0 code looks for U-Boot at a certain place on an uSD card -(at 19096 KB), also it expects a header with magic bytes and a checksum. -There is a tool called boot0img[1] which takes a boot0.bin image and a compiled -U-Boot binary (plus other binaries) and will populate that header accordingly. -To make space for the magic header, the pine64_plus_defconfig will make sure -there is sufficient space at the beginning of the U-Boot binary. -boot0img will also take care of putting the different binaries at the right -places on the uSD card and works around unused, but mandatory parts by using -trampoline code. See the output of "boot0img -h" for more information. -boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead -fetching it from just behind the boot0 binary (-B option). - -FEL boot -========= -FEL is the name of the Allwinner defined USB boot protocol built-in the -mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely -by using the USB-OTG interface and a host port on another computer. -Since FEL boot does not work with boot0, it requires the libdram hack, which -is not described here. - -[1] https://github.com/apritzel/pine64/ -[2] https://github.com/apritzel/arm-trusted-firmware.git diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64 new file mode 100644 index 0000000000..c492f749b8 --- /dev/null +++ b/board/sunxi/README.sunxi64 @@ -0,0 +1,165 @@ +Allwinner 64-bit boards README +============================== + +Newer Allwinner SoCs feature ARMv8 cores (ARM Cortex-A53) with support for +both the 64-bit AArch64 mode and the ARMv7 compatible 32-bit AArch32 mode. +Examples are the Allwinner A64 (used for instance on the Pine64 board) or +the Allwinner H5 SoC (as used on the OrangePi PC 2). +These SoCs are wired to start in AArch32 mode on reset and execute 32-bit +code from the Boot ROM (BROM). As this has some implications on U-Boot, this +file describes how to make full use of the 64-bit capabilities. + +Quick Start / Overview +====================== +- Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below) +- Build U-Boot (see "SPL/U-Boot" below) +- Transfer to an uSD card (see "microSD card" below) +- Boot and enjoy! + +Building the firmware +===================== + +The Allwinner A64/H5 firmware consists of three parts: U-Boot's SPL, an +ARM Trusted Firmware (ATF) build and the U-Boot proper. +The SPL will load both ATF and U-Boot proper along with the right device +tree blob (.dtb) and will pass execution to ATF (in EL3), which in turn will +drop into the U-Boot proper (in EL2). +As the ATF binary will become part of the U-Boot image file, you will need +to build it first. + + ARM Trusted Firmware (ATF) +---------------------------- +Checkout the "allwinner" branch from the github repository [1] and build it: +$ export CROSS_COMPILE=aarch64-linux-gnu- +$ make PLAT=sun50iw1p1 DEBUG=1 bl31 +The resulting binary is build/sun50iw1p1/debug/bl31.bin. Either put the +location of this file into the BL31 environment variable or copy this to +the root of your U-Boot build directory (or create a symbolic link). +$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin + (adjust the actual path accordingly) + + SPL/U-Boot +------------ +Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM +enters the SPL still in AArch32 secure SVC mode, there is some shim code to +enter AArch64 very early. The rest of the SPL runs in AArch64 EL3. +U-Boot proper runs in EL2 and can load any AArch64 code (using the "go" +command), EFI applications (with "bootefi") or arm64 Linux kernel images +(often named "Image"), using the "booti" command. + +$ make clean +$ export CROSS_COMPILE=aarch64-linux-gnu- +$ make pine64_plus_defconfig +$ make + +This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb, +which contains the rest of the firmware. + + +Boot process +============ +The on-die BROM code will try several methods to load and execute the firmware. +On a typical board like the Pine64 this will result in the following boot order: + +1) Reading 32KB from sector 16 (@8K) of the microSD card to SRAM A1. If the +BROM finds the magic "eGON" header in the first bytes, it will execute that +code. If not (no SD card at all or invalid magic), it will: +2) Try to read 32KB from sector 16 (@8K) of memory connected to the MMC2 +controller, typically an on-board eMMC chip. If there is no eMMC or it does +not contain a valid boot header, it will: +3) Initialize the SPI0 controller and try to access a NOR flash connected to +it (using the CS0 pin). If a flash chip is found, the BROM will load the +first 32KB (from offset 0) into SRAM A1. Now it checks for the magic eGON +header and checksum and will execute the code upon finding it. If not, it will: +4) Initialize the USB OTG controller and will wait for a host to connect to +it, speaking the Allwinner proprietary (but deciphered) "FEL" USB protocol. + + +To boot the Pine64 board, you can use U-Boot and any of the described methods. + +FEL boot (USB OTG) +------------------ +FEL is the name of the Allwinner defined USB boot protocol built in the +mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely +by using the USB-OTG interface and a host port on another computer. +As the FEL mode is controlled by the boot ROM, it expects to be running in +AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the +feature is disabled in the configuration at the moment. + +microSD card +------------ +Transfer the SPL and the U-Boot FIT image directly to an uSD card: +# dd if=spl/sunxi-spl.bin of=/dev/sdx bs=8k seek=1 +# dd if=u-boot.itb of=/dev/sdx bs=8k seek=5 +# sync +(replace /dev/sdx with you SD card device file name, which could be +/dev/mmcblk[x] as well). + +Alternatively you can concatenate the SPL and the U-Boot FIT image into a +single file and transfer that instead: +$ cat spl/sunxi-spl.bin u-boot.itb > u-boot-sunxi-with-spl.bin +# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1 + +You can partition the microSD card, but leave the first MB unallocated (most +partitioning tools will do this anyway). + +NOR flash +--------- +Some boards (like the SoPine, Pinebook or the OrangePi PC2) come with a +soldered SPI NOR flash chip. On other boards like the Pine64 such a chip +can be connected to the SPI0/CS0 pins on the PI-2 headers. +Create the SPL and FIT image like described above for the SD card. +Now connect either an "A to A" USB cable to the upper USB port on the Pine64 +or get an adaptor and use a regular A-microB cable connected to it. Other +boards often have a proper micro-B USB socket connected to the USB OTB port. +Remove a microSD card from the slot and power on the board. +On your host computer download and build the sunxi-tools package[2], then +use "sunxi-fel" to access the board: +$ ./sunxi-fel ver -v -p +This should give you an output starting with: AWUSBFEX soc=00001689(A64) ... +Now use the sunxi-fel tool to write to the NOR flash: +$ ./sunxi-fel spiflash-write 0 spl/sunxi-spl.bin +$ ./sunxi-fel spiflash-write 32768 u-boot.itb +Now boot the board without an SD card inserted and you should see the +U-Boot prompt on the serial console. + +(Legacy) boot0 method +--------------------- +boot0 is Allwiner's secondary program loader and it can be used as some kind +of SPL replacement to get U-Boot up and running from an microSD card. +For some time using boot0 was the only option to get the Pine64 booted. +With working DRAM init code in U-Boot's SPL this is no longer necessary, +but this method is described here for the sake of completeness. +Please note that this method works only with the boot0 files shipped with +A64 based boards, the H5 uses an incompatible layout which is not supported +by this method. + +The boot0 binary is a 32 KByte blob and contained in the official Pine64 images +distributed by Pine64 or Allwinner. It can be easily extracted from a micro +SD card or an image file: +# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4 +where /dev/sd<x> is the device name of the uSD card or the name of the image +file. Apparently Allwinner allows re-distribution of this proprietary code +"as-is". +This boot0 blob takes care of DRAM initialisation and loads the remaining +firmware parts, then switches the core into AArch64 mode. +The original boot0 code looks for U-Boot at a certain place on an uSD card +(at 19096 KB), also it expects a header with magic bytes and a checksum. +There is a tool called boot0img[3] which takes a boot0.bin image and a compiled +U-Boot binary (plus other binaries) and will populate that header accordingly. +To make space for the magic header, the pine64_plus_defconfig will make sure +there is sufficient space at the beginning of the U-Boot binary. +boot0img will also take care of putting the different binaries at the right +places on the uSD card and works around unused, but mandatory parts by using +trampoline code. See the output of "boot0img -h" for more information. +boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead +fetching it from just behind the boot0 binary (-B option). +$ ./boot0img -o firmware.img -B boot0.img -u u-boot-dtb.bin -e -s bl31.bin \ +-a 0x44008 -d trampoline64:0x44000 +Then write this image to a microSD card, replacing /dev/sdx with the right +device file (see above): +$ dd if=firmware.img of=/dev/sdx bs=8k seek=1 + +[1] https://github.com/apritzel/arm-trusted-firmware.git +[2] git://github.com/linux-sunxi/sunxi-tools.git +[3] https://github.com/apritzel/pine64/ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 01de42d031..f79bd5c62c 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -284,7 +284,7 @@ void board_nand_init(void) } #endif -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC static void mmc_pinmux_setup(int sdc) { unsigned int pin; @@ -512,7 +512,6 @@ int board_mmc_init(bd_t *bis) void sunxi_board_init(void) { int power_failed = 0; - unsigned long ramsize; #ifdef CONFIG_SY8106A_POWER power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); @@ -573,9 +572,9 @@ void sunxi_board_init(void) #endif #endif printf("DRAM:"); - ramsize = sunxi_dram_init(); - printf(" %d MiB\n", (int)(ramsize >> 20)); - if (!ramsize) + gd->ram_size = sunxi_dram_init(); + printf(" %d MiB\n", (int)(gd->ram_size >> 20)); + if (!gd->ram_size) hang(); /* @@ -758,3 +757,32 @@ int ft_board_setup(void *blob, bd_t *bd) #endif return 0; } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + struct boot_file_head *spl = (void *)(ulong)SPL_ADDR; + const char *cmp_str = (void *)(ulong)SPL_ADDR; + + /* Check if there is a DT name stored in the SPL header and use that. */ + if (spl->dt_name_offset) { + cmp_str += spl->dt_name_offset; + } else { +#ifdef CONFIG_DEFAULT_DEVICE_TREE + cmp_str = CONFIG_DEFAULT_DEVICE_TREE; +#else + return 0; +#endif + }; + +/* Differentiate the two Pine64 board DTs by their DRAM size. */ + if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) { + if ((gd->ram_size > 512 * 1024 * 1024)) + return !strstr(name, "plus"); + else + return !!strstr(name, "plus"); + } else { + return strcmp(name, cmp_str); + } +} +#endif diff --git a/board/sunxi/mksunxi_fit_atf.sh b/board/sunxi/mksunxi_fit_atf.sh new file mode 100755 index 0000000000..b1d6e0e16a --- /dev/null +++ b/board/sunxi/mksunxi_fit_atf.sh @@ -0,0 +1,81 @@ +#!/bin/sh +# +# script to generate FIT image source for 64-bit sunxi boards with +# ARM Trusted Firmware and multiple device trees (given on the command line) +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +[ -z "$BL31" ] && BL31="bl31.bin" + +if [ ! -f $BL31 ]; then + echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2 + echo "Please read the section on ARM Trusted Firmware (ATF) in board/sunxi/README.sunxi64" >&2 + BL31=/dev/null +fi + +cat << __HEADER_EOF +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + + images { + uboot@1 { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x4a000000>; + }; + atf@1 { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x44000>; + entry = <0x44000>; + }; +__HEADER_EOF + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt@$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF + cnt=$((cnt+1)) +done + +cat << __CONF_HEADER_EOF + }; + configurations { + default = "config@1"; + +__CONF_HEADER_EOF + +cnt=1 +for dtname in $* +do + cat << __CONF_SECTION_EOF + config@$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "uboot@1"; + loadables = "atf@1"; + fdt = "fdt@$cnt"; + }; +__CONF_SECTION_EOF + cnt=$((cnt+1)) +done + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c index cba48d48fc..c5966e3571 100644 --- a/board/technexion/tao3530/tao3530.c +++ b/board/technexion/tao3530/tao3530.c @@ -179,7 +179,7 @@ void set_muxconf_regs(void) #endif } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); @@ -188,14 +188,14 @@ int board_mmc_init(bd_t *bis) } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); } #endif -#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { @@ -219,4 +219,4 @@ int ehci_hcd_stop(int index) { return omap_ehci_hcd_stop(); } -#endif /* CONFIG_USB_EHCI */ +#endif /* CONFIG_USB_EHCI_HCD */ diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index ad4b02a753..25aeebc8d0 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -19,7 +19,7 @@ #include <spl.h> #include <mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #include <usb.h> #include <asm/ehci-omap.h> #endif @@ -46,7 +46,7 @@ static const u32 gpmc_XR16L2751[] = { XR16L2751_GPMC_CONFIG6, }; -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 6b05541964..6e73ae114a 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -23,7 +23,7 @@ #include <i2c.h> #include <spartan3.h> #include <asm/gpio.h> -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #include <usb.h> #include <asm/ehci-omap.h> #endif @@ -95,7 +95,7 @@ static const u32 gpmc_fpga[] = { FPGA_GPMC_CONFIG6, }; -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 3e81521399..517965c0f0 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -72,7 +72,8 @@ void do_board_detect(void) enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) + if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS)) printf("ti_i2c_eeprom_init failed\n"); } #endif diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index faa95d7da8..5fa319d615 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -63,7 +63,7 @@ void set_muxconf_regs(void) MUX_AM3517CRANE(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index f633e2f85d..f44103d4d6 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -42,7 +42,8 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_TI_I2C_BOARD_DETECT void do_board_detect(void) { - if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) + if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, + CONFIG_EEPROM_CHIP_ADDRESS)) printf("ti_i2c_eeprom_init failed\n"); } #endif diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 6d444e09fa..3be697a6ea 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -661,7 +661,7 @@ err: } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index e90fe1aba8..00d127e21b 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -36,7 +36,7 @@ #include "beagle.h" #include <command.h> -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #include <usb.h> #include <asm/ehci-omap.h> #endif @@ -524,21 +524,21 @@ void set_muxconf_regs(void) MUX_BEAGLE(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); } #endif -#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { @@ -563,7 +563,7 @@ int ehci_hcd_stop(int index) return omap_ehci_hcd_stop(); } -#endif /* CONFIG_USB_EHCI */ +#endif /* CONFIG_USB_EHCI_HCD */ #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) int board_eth_init(bd_t *bis) diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 08c39d9409..1187cf5433 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -20,6 +20,7 @@ config TI_COMMON_CMD_OPTIONS imply CMD_BOOTZ imply CMD_DFU if USB_GADGET_DOWNLOAD imply CMD_DHCP + imply CMD_EEPROM imply CMD_EXT2 imply CMD_EXT4 imply CMD_EXT4_WRITE diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index d8e48dd3f8..8c02addd08 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -702,7 +702,7 @@ err: } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 4f132e5107..fe8e79312f 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -259,14 +259,14 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_CMD_NET */ -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 6e03f6bcd0..21aec8f065 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -196,7 +196,7 @@ s16 divn_val[16] = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { if (psc_enable_module(KS2_LPSC_MMC)) { diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 64d772ca6e..b6cc417333 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -20,7 +20,7 @@ #include "mux_data.h" -#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP) #include <sata.h> #include <usb.h> #include <asm/gpio.h> @@ -151,7 +151,7 @@ int board_eth_init(bd_t *bis) return 0; } -#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP) static void enable_host_clocks(void) { int auxclk; @@ -211,7 +211,7 @@ void set_muxconf_regs(void) sizeof(struct pad_conf_entry)); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); @@ -220,7 +220,7 @@ int board_mmc_init(bd_t *bis) } #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 187ff3cff4..72aabb242c 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -15,7 +15,7 @@ #include "panda_mux_data.h" -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #include <usb.h> #include <asm/arch/ehci.h> #include <asm/ehci-omap.h> @@ -287,7 +287,7 @@ void set_muxconf_regs(void) sizeof(struct pad_conf_entry)); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); @@ -301,7 +301,7 @@ void board_mmc_power_init(void) #endif #endif -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 0eb60e4271..bc8d32f161 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -73,7 +73,7 @@ void set_muxconf_regs(void) sizeof(struct pad_conf_entry)); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0, 0, 0, -1, -1); diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index e85794c60e..055a29d9c6 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -111,7 +111,7 @@ int board_init(void) return 0; } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(1, 0, 0, -1, -1); diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 5f57956ca3..d31eeb878a 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -131,14 +131,14 @@ void set_muxconf_regs(void) MUX_DEVKIT8000(); } -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { return omap_mmc_init(0, 0, 0, -1, -1); } #endif -#if defined(CONFIG_GENERIC_MMC) +#if defined(CONFIG_MMC) void board_mmc_power_init(void) { twl4030_power_mmc_init(0); diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index 92db093dbf..cb99afdb90 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -312,7 +312,7 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) #if defined (CONFIG_MINIFAP) #define SM501_POWER_MODE0_GATE 0x00000040UL @@ -486,20 +486,14 @@ int board_early_init_f (void) static int tfp410_read_reg(int reg, uchar *buf) { - if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) { - puts ("Error reading the chip.\n"); - return 1; - } - return 0; + puts("Error reading the chip.\n"); + return -ENOSYS; } static int tfp410_write_reg(int reg, uchar buf) { - if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) { - puts ("Error writing the chip.\n"); - return 1; - } - return 0; + puts("Error writing the chip.\n"); + return -ENOSYS; } typedef struct _tfp410_config { @@ -525,12 +519,9 @@ static int charon_last_stage_init(void) { volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *) MPC5XXX_LPB; - int oldbus = i2c_get_bus_num(); uchar buf; int i = 0; - i2c_set_bus_num(CONFIG_SYS_TFP410_BUS); - /* check version */ if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0) return -1; @@ -551,7 +542,6 @@ static int charon_last_stage_init(void) i++; } printf("TFP410 initialized.\n"); - i2c_set_bus_num(oldbus); /* set deadcycle for cs3 to 0 */ setbits_be32(&lpb->cs_deadcycle, 0xffffcfff); diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index 73227c1b15..e680b7b8ff 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -224,7 +224,7 @@ int misc_init_r(void) return 0; } -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) void init_ide_reset(void) { debug("init_ide_reset\n"); diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig index 74f004f53c..1fde4b29aa 100644 --- a/board/work-microwave/work_92105/Kconfig +++ b/board/work-microwave/work_92105/Kconfig @@ -12,4 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "work_92105" +config CMD_HD44760 + bool "Enable 'hd44780' LCD-control comand" + help + This controls the LCD driver. + endif diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c index 3d7438e527..37a736351c 100644 --- a/board/work-microwave/work_92105/work_92105_display.c +++ b/board/work-microwave/work_92105/work_92105_display.c @@ -346,4 +346,4 @@ U_BOOT_CMD( "HD44780 LCD driver control", hd44780_help_text ); -#endif /* CONFIG_CMD_HD44780 */ +#endif /* CONFIG_CMD_HD44760 */ diff --git a/cmd/Kconfig b/cmd/Kconfig index d9f7151bac..5ee52f62cc 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -314,6 +314,22 @@ config CMD_ENV_EXISTS Check if a variable is defined in the environment for use in shell scripting. +config CMD_ENV_CALLBACK + bool "env callbacks - print callbacks and their associated variables" + help + Some environment variable have callbacks defined by + U_BOOT_ENV_CALLBACK. These are called when the variable changes. + For example changing "baudrate" adjust the serial baud rate. This + command lists the currently defined callbacks. + +config CMD_ENV_FLAGS + bool "env flags -print variables that have non-default flags" + help + Some environment variables have special flags that control their + behaviour. For example, serial# can only be written once and cannot + be deleted. This command shows the variables that have special + flags. + endmenu menu "Memory commands" @@ -334,10 +350,59 @@ config CMD_MEMORY config CMD_CRC32 bool "crc32" + select HASH default y help Compute CRC32. +config CMD_EEPROM + bool "eeprom - EEPROM subsystem" + help + (deprecated, needs conversion to driver model) + Provides commands to read and write EEPROM (Electrically Erasable + Programmable Read Only Memory) chips that are connected over an + I2C bus. + +config CMD_EEPROM_LAYOUT + bool "Enable layout-aware eeprom commands" + depends on CMD_EEPROM + help + (deprecated, needs conversion to driver model) + When enabled, additional eeprom sub-commands become available. + + eeprom print - prints the contents of the eeprom in a human-readable + way (eeprom layout fields, and data formatted to be fit for human + consumption). + + eeprom update - allows user to update eeprom fields by specifying + the field name, and providing the new data in a human readable format + (same format as displayed by the eeprom print command). + + Both commands can either auto detect the layout, or be told which + layout to use. + + Feature API: + __weak int parse_layout_version(char *str) + - override to provide your own layout name parsing + __weak void __eeprom_layout_assign(struct eeprom_layout *layout, + int layout_version); + - override to setup the layout metadata based on the version + __weak int eeprom_layout_detect(unsigned char *data) + - override to provide your own algorithm for detecting layout + version + eeprom_field.c + - contains various printing and updating functions for common + types of eeprom fields. Can be used for defining + custom layouts. + +config EEPROM_LAYOUT_HELP_STRING + string "Tells user what layout names are supported" + depends on CMD_EEPROM_LAYOUT + default "<not defined>" + help + Help printed with the LAYOUT VERSIONS part of the 'eeprom' + command's help. + config CMD_MD5SUM bool "md5sum" default n @@ -373,6 +438,17 @@ config CMD_MEMINFO help Display memory information. +endmenu + +menu "Compression commands" + +config CMD_LZMADEC + bool "lzmadec" + select LZMA + help + Support decompressing an LZMA (Lempel-Ziv-Markov chain algorithm) + image from memory. + config CMD_UNZIP bool "unzip" help @@ -419,6 +495,57 @@ config CMD_DEMO option is to use sandbox and pass the -d point to sandbox's u-boot.dtb file. +config CMD_IDE + bool "ide - Support for IDE drivers" + select IDE + help + Provides an 'ide' command which allows accessing the IDE drive, + reseting the IDE interface, printing the partition table and + geting device info. It also enables the 'diskboot' command which + permits booting from an IDE drive. + +config CMD_IO + bool "io - Support for performing I/O accesses" + help + Provides an 'iod' command to display I/O space and an 'iow' command + to write values to the I/O space. This can be useful for manually + checking the state of devices during boot when debugging device + drivers, etc. + +config CMD_IOTRACE + bool "iotrace - Support for tracing I/O activity" + help + Provides an 'iotrace' command which supports recording I/O reads and + writes in a trace buffer in memory . It also maintains a checksum + of the trace records (even if space is exhausted) so that the + sequence of I/O accesses can be verified. + + When debugging drivers it is useful to see what I/O accesses were + done and in what order. + + Even if the individual accesses are of little interest it can be + useful to verify that the access pattern is consistent each time + an operation is performed. In this case a checksum can be used to + characterise the operation of a driver. The checksum can be compared + across different runs of the operation to verify that the driver is + working properly. + + In particular, when performing major refactoring of the driver, where + the access pattern should not change, the checksum provides assurance + that the refactoring work has not broken the driver. + + This works by sneaking into the io.h heder for an architecture and + redirecting I/O accesses through iotrace's tracing mechanism. + + For now no commands are provided to examine the trace buffer. The + format is fairly simple, so 'md' is a reasonable substitute. + + Note: The checksum feature is only useful for I/O regions where the + contents do not change outside of software control. Where this is not + suitable you can fall back to manually comparing the addresses. It + might be useful to enhance tracing to only checksum the accesses and + not the data read/written. + config CMD_LOADB bool "loadb" default y @@ -529,6 +656,48 @@ config CMD_FPGA help FPGA support. +config CMD_FPGA_LOADBP + bool "fpga loadbp - load partial bitstream (Xilinx only)" + depends on CMD_FPGA + help + Supports loading an FPGA device from a bitstream buffer containing + a partial bitstream. + +config CMD_FPGA_LOADFS + bool "fpga loadfs - load bitstream from FAT filesystem (Xilinx only)" + depends on CMD_FPGA + help + Supports loading an FPGA device from a FAT filesystem. + +config CMD_FPGA_LOADMK + bool "fpga loadmk - load bitstream from image" + depends on CMD_FPGA + help + Supports loading an FPGA device from a image generated by mkimage. + +config CMD_FPGA_LOADP + bool "fpga loadp - load partial bitstream" + depends on CMD_FPGA + help + Supports loading an FPGA device from a bitstream buffer containing + a partial bitstream. + +config CMD_FPGAD + bool "fpgad - dump FPGA registers" + help + (legacy, needs conversion to driver model) + Provides a way to dump FPGA registers by calling the board-specific + fpga_get_reg() function. This functions similarly to the 'md' + command. + +config CMD_FUSE + bool "fuse - support for the fuse subssystem" + help + (deprecated - needs conversion to driver model) + This allows reading, sensing, programming or overriding fuses + which control the behaviour of the device. The command uses the + fuse_...() API. + config CMD_REMOTEPROC bool "remoteproc" depends on REMOTEPROC @@ -540,6 +709,11 @@ config CMD_GPIO help GPIO support. +config CMD_FDC + bool "fdcboot - Boot from floppy device" + help + The 'fdtboot' command allows booting an image from a floppy disk. + endmenu @@ -647,6 +821,14 @@ config CMD_LINK_LOCAL help Acquire a network IP address using the link-local protocol +config CMD_ETHSW + bool "ethsw" + help + Allow control of L2 Ethernet switch commands. These are supported + by the vsc9953 Ethernet driver at present. Sub-commands allow + operations such as enabling / disabling a port and + viewing/maintaining the filtering database (FDB) + endmenu menu "Misc commands" @@ -727,6 +909,14 @@ config CMD_TIME help Run commands and summarize execution time. +config CMD_GETTIME + bool "gettime - read elapsed time" + help + Enable the 'gettime' command which reads the elapsed time since + U-Boot started running. This shows the time in seconds and + milliseconds. See also the 'bootstage' command which provides more + flexibility for boot timing. + # TODO: rename to CMD_SLEEP config CMD_MISC bool "sleep" @@ -869,6 +1059,15 @@ config CMD_BLOB generation/use as key for cryptographic operation. Key modifier should be 16 byte long. +config CMD_HASH + bool "Support 'hash' command" + select HASH + help + This provides a way to hash data in memory using various supported + algorithms (such as SHA1, MD5, CRC32). The computed digest can be + saved to memory or to an environment variable. It is also possible + to verify a hash against data in memory. + config CMD_TPM bool "Enable the 'tpm' command" depends on TPM @@ -957,6 +1156,15 @@ config CMD_FS_UUID help Enables fsuuid command for filesystem UUID. +config CMD_JFFS2 + bool "jffs2 command" + select FS_JFFS2 + help + Enables commands to support the JFFS2 (Journalling Flash File System + version 2) filesystem. This enables fsload, ls and fsinfo which + provide the ability to load files, list directories and obtain + filesystem information. + config CMD_MTDPARTS depends on ARCH_SUNXI bool "MTD partition support" @@ -995,6 +1203,23 @@ config CMD_DIAG available tests and running either all the tests, or specific tests identified by name. +config CMD_IRQ + bool "irq - Show information about interrupts" + depends on !ARM && !MIPS && !SH && !MPC512X + help + This enables two commands: + + interrupts - enable or disable interrupts + irqinfo - print device-specific interrupt information + +config CMD_KGDB + bool "kgdb - Allow debugging of U-Boot with gdb" + help + This enables a 'kgdb' command which allows gdb to connect to U-Boot + over a serial link for debugging purposes. This allows + single-stepping, inspecting variables, etc. This is supported only + on PowerPC at present. + endmenu config CMD_UBI diff --git a/cmd/Makefile b/cmd/Makefile index e98786807b..9ea56e9977 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -43,7 +43,6 @@ ifdef CONFIG_POST obj-$(CONFIG_CMD_DIAG) += diag.o endif obj-$(CONFIG_CMD_DISPLAY) += display.o -obj-$(CONFIG_CMD_DTT) += dtt.o obj-$(CONFIG_CMD_ECHO) += echo.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o obj-$(CONFIG_CMD_EEPROM) += eeprom.o @@ -69,7 +68,6 @@ obj-$(CONFIG_CMD_I2C) += i2c.o obj-$(CONFIG_CMD_IOTRACE) += iotrace.o obj-$(CONFIG_CMD_HASH) += hash.o obj-$(CONFIG_CMD_IDE) += ide.o disk.o -obj-$(CONFIG_CMD_IMMAP) += immap.o obj-$(CONFIG_CMD_INI) += ini.o obj-$(CONFIG_CMD_IRQ) += irq.o obj-$(CONFIG_CMD_ITEST) += itest.o @@ -129,9 +127,7 @@ obj-$(CONFIG_CMD_UBI) += ubi.o obj-$(CONFIG_CMD_UBIFS) += ubifs.o obj-$(CONFIG_CMD_UNIVERSE) += universe.o obj-$(CONFIG_CMD_UNZIP) += unzip.o -ifdef CONFIG_LZMA obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o -endif obj-$(CONFIG_CMD_USB) += usb.o disk.o obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o diff --git a/cmd/cramfs.c b/cmd/cramfs.c index 4e75de8f29..49ee36c74a 100644 --- a/cmd/cramfs.c +++ b/cmd/cramfs.c @@ -39,7 +39,7 @@ # define OFFSET_ADJUSTMENT (flash_info[id.num].start[0]) #endif -#ifndef CONFIG_CMD_JFFS2 +#ifndef CONFIG_FS_JFFS2 #include <linux/stat.h> char *mkmodestr(unsigned long mode, char *str) { @@ -70,7 +70,7 @@ char *mkmodestr(unsigned long mode, char *str) str[10] = '\0'; return str; } -#endif /* CONFIG_CMD_JFFS2 */ +#endif /* CONFIG_FS_JFFS2 */ extern int cramfs_check (struct part_info *info); extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename); diff --git a/cmd/dtt.c b/cmd/dtt.c deleted file mode 100644 index dd427a3d0b..0000000000 --- a/cmd/dtt.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <command.h> - -#include <dtt.h> -#include <i2c.h> -#include <tmu.h> -#include <linux/bug.h> - -#if defined CONFIG_DTT_SENSORS -static unsigned long sensor_initialized; - -static void _initialize_dtt(void) -{ - int i; - unsigned char sensors[] = CONFIG_DTT_SENSORS; - - for (i = 0; i < sizeof(sensors); i++) { - if ((sensor_initialized & (1 << i)) == 0) { - if (dtt_init_one(sensors[i]) != 0) { - printf("DTT%d: Failed init!\n", i); - continue; - } - sensor_initialized |= (1 << i); - } - } -} - -void dtt_init(void) -{ - int old_bus; - - /* switch to correct I2C bus */ - old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM); - - _initialize_dtt(); - - /* switch back to original I2C bus */ - I2C_SET_BUS(old_bus); -} -#endif - -int dtt_i2c(void) -{ -#if defined CONFIG_DTT_SENSORS - int i; - unsigned char sensors[] = CONFIG_DTT_SENSORS; - int old_bus; - - /* Force a compilation error, if there are more then 32 sensors */ - BUILD_BUG_ON(sizeof(sensors) > 32); - /* switch to correct I2C bus */ -#ifdef CONFIG_SYS_I2C - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_DTT_BUS_NUM); -#else - old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CONFIG_SYS_DTT_BUS_NUM); -#endif - - _initialize_dtt(); - - /* - * Loop through sensors, read - * temperature, and output it. - */ - for (i = 0; i < sizeof(sensors); i++) - printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i])); - - /* switch back to original I2C bus */ -#ifdef CONFIG_SYS_I2C - i2c_set_bus_num(old_bus); -#else - I2C_SET_BUS(old_bus); -#endif -#endif - - return 0; -} - -int dtt_tmu(void) -{ -#if defined CONFIG_TMU_CMD_DTT - int cur_temp; - - /* Sense and return latest thermal info */ - if (tmu_monitor(&cur_temp) == TMU_STATUS_INIT) { - puts("TMU is in unknown state, temperature is invalid\n"); - return -1; - } - printf("Current temperature: %u degrees Celsius\n", cur_temp); -#endif - return 0; -} - -int do_dtt(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) -{ - int err = 0; - - err |= dtt_i2c(); - err |= dtt_tmu(); - - return err; -} /* do_dtt() */ - -/***************************************************/ - -U_BOOT_CMD( - dtt, 1, 1, do_dtt, - "Read temperature from Digital Thermometer and Thermostat", - "" -); diff --git a/cmd/eeprom.c b/cmd/eeprom.c index 0a0e4a2c1c..c61b396a62 100644 --- a/cmd/eeprom.c +++ b/cmd/eeprom.c @@ -73,11 +73,9 @@ void eeprom_init(int bus) #endif /* I2C EEPROM */ -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) #if defined(CONFIG_SYS_I2C) if (bus >= 0) i2c_set_bus_num(bus); -#endif i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif } @@ -267,10 +265,6 @@ __weak int eeprom_parse_layout_version(char *str) static unsigned char eeprom_buf[CONFIG_SYS_EEPROM_SIZE]; -#ifndef CONFIG_EEPROM_LAYOUT_HELP_STRING -#define CONFIG_EEPROM_LAYOUT_HELP_STRING "<not defined>" -#endif - #endif enum eeprom_action { @@ -20,9 +20,7 @@ #define MAX_LEVEL 32 /* how deeply nested we will go */ #define SCRATCHPAD 1024 /* bytes of scratchpad memory */ -#ifndef CONFIG_CMD_FDT_MAX_DUMP -#define CONFIG_CMD_FDT_MAX_DUMP 64 -#endif +#define CMD_FDT_MAX_DUMP 64 /* * Global data (for the gd->bd) @@ -901,7 +899,7 @@ static void print_data(const void *data, int len) } if ((len %4) == 0) { - if (len > CONFIG_CMD_FDT_MAX_DUMP) + if (len > CMD_FDT_MAX_DUMP) printf("* 0x%p [0x%08x]", data, len); else { const __be32 *p; @@ -913,7 +911,7 @@ static void print_data(const void *data, int len) printf(">"); } } else { /* anything else... hexdump */ - if (len > CONFIG_CMD_FDT_MAX_DUMP) + if (len > CMD_FDT_MAX_DUMP) printf("* 0x%p [0x%08x]", data, len); else { const u8 *s; diff --git a/cmd/pcmcia.c b/cmd/pcmcia.c index 682d18f55d..044fb9e618 100644 --- a/cmd/pcmcia.c +++ b/cmd/pcmcia.c @@ -83,7 +83,7 @@ U_BOOT_CMD( #undef CHECK_IDE_DEVICE -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CHECK_IDE_DEVICE #endif diff --git a/common/Kconfig b/common/Kconfig index 1879aefaf8..5c39663f56 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -493,4 +493,16 @@ config BOARD_EARLY_INIT_F endmenu +menu "Security support" + +config HASH + bool # "Support hashing API (SHA1, SHA256, etc.)" + help + This provides a way to hash data in memory using various supported + algorithms (such as SHA1, MD5, CRC32). The API is defined in hash.h + and the algorithms it supports are defined in common/hash.c. See + also CMD_HASH for command-line access. + +endmenu + source "common/spl/Kconfig" diff --git a/common/Makefile b/common/Makefile index 14d01844ad..c7c8ea42c6 100644 --- a/common/Makefile +++ b/common/Makefile @@ -10,7 +10,7 @@ ifndef CONFIG_SPL_BUILD obj-y += init/ obj-y += main.o obj-y += exports.o -obj-y += hash.o +obj-$(CONFIG_HASH) += hash.o obj-$(CONFIG_HUSH_PARSER) += cli_hush.o obj-$(CONFIG_AUTOBOOT) += autoboot.o @@ -145,7 +145,6 @@ obj-y += dlmalloc.o ifdef CONFIG_SYS_MALLOC_F_LEN obj-y += malloc_simple.o endif -obj-$(CONFIG_CMD_IDE) += ide.o obj-y += image.o obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o diff --git a/common/board_f.c b/common/board_f.c index d9431ee79a..a212f2b539 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -184,7 +184,7 @@ __weak int dram_init_banksize(void) return 0; } -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) +#if defined(CONFIG_SYS_I2C) static int init_func_i2c(void) { puts("I2C: "); @@ -740,7 +740,9 @@ static const init_fnc_t init_sequence_f[] = { /* get CPU and bus clocks according to the environment variable */ get_clocks, /* get CPU and bus clocks (etc.) */ #endif +#if !defined(CONFIG_M68K) timer_init, /* initialize timer */ +#endif #if defined(CONFIG_BOARD_POSTCLK_INIT) board_postclk_init, #endif @@ -765,7 +767,7 @@ static const init_fnc_t init_sequence_f[] = { misc_init_f, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) +#if defined(CONFIG_SYS_I2C) init_func_i2c, #endif #if defined(CONFIG_HARD_SPI) diff --git a/common/board_r.c b/common/board_r.c index d69a33c4a3..fe7a70b589 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -23,9 +23,7 @@ #include <dm.h> #include <environment.h> #include <fdtdec.h> -#if defined(CONFIG_CMD_IDE) #include <ide.h> -#endif #include <initcall.h> #include <init_helpers.h> #ifdef CONFIG_PS2KBD @@ -432,7 +430,7 @@ static int initr_onenand(void) } #endif -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC static int initr_mmc(void) { puts("MMC: "); @@ -485,24 +483,7 @@ static int initr_env(void) /* Initialize from environment */ load_addr = getenv_ulong("loadaddr", 16, load_addr); -#if defined(CONFIG_SYS_EXTBDINFO) -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) -#if defined(CONFIG_I2CFAST) - /* - * set bi_iic_fast for linux taking environment variable - * "i2cfast" into account - */ - { - char *s = getenv("i2cfast"); - if (s && ((*s == 'y') || (*s == 'Y'))) { - gd->bd->bi_iic_fast[0] = 1; - gd->bd->bi_iic_fast[1] = 1; - } - } -#endif /* CONFIG_I2CFAST */ -#endif /* CONFIG_405GP, CONFIG_405EP */ -#endif /* CONFIG_SYS_EXTBDINFO */ return 0; } @@ -628,7 +609,7 @@ static int initr_post(void) } #endif -#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE) +#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE) static int initr_pcmcia(void) { puts("PCMCIA:"); @@ -637,7 +618,7 @@ static int initr_pcmcia(void) } #endif -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) static int initr_ide(void) { #ifdef CONFIG_IDE_8xx_PCCARD @@ -815,7 +796,7 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_ONENAND initr_onenand, #endif -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC initr_mmc, #endif #ifdef CONFIG_HAS_DATAFLASH @@ -887,10 +868,10 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_POST initr_post, #endif -#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE) +#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_IDE) initr_pcmcia, #endif -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) initr_ide, #endif #ifdef CONFIG_LAST_STAGE_INIT diff --git a/common/edid.c b/common/edid.c index e08e420920..19410aa4fc 100644 --- a/common/edid.c +++ b/common/edid.c @@ -85,6 +85,7 @@ static void decode_timing(u8 *buf, struct display_timing *timing) uint x_mm, y_mm; unsigned int ha, hbl, hso, hspw, hborder; unsigned int va, vbl, vso, vspw, vborder; + struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; /* Edid contains pixel clock in terms of 10KHz */ set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); @@ -111,6 +112,19 @@ static void decode_timing(u8 *buf, struct display_timing *timing) set_entry(&timing->vback_porch, vbl - vso - vspw); set_entry(&timing->vsync_len, vspw); + timing->flags = 0; + if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) + timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; + else + timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; + if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) + timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; + else + timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; + + if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) + timing->flags = DISPLAY_FLAGS_INTERLACED; + debug("Detailed mode clock %u Hz, %d mm x %d mm\n" " %04x %04x %04x %04x hborder %x\n" " %04x %04x %04x %04x vborder %x\n", @@ -122,6 +136,39 @@ static void decode_timing(u8 *buf, struct display_timing *timing) va + vbl, vborder); } +/** + * Check if HDMI vendor specific data block is present in CEA block + * @param info CEA extension block + * @return true if block is found + */ +static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) +{ + u8 end, i = 0; + + /* check for end of data block */ + end = info->dtd_offset; + if (end == 0) + end = 127; + if (end < 4 || end > 127) + return false; + end -= 4; + + while (i < end) { + /* Look for vendor specific data block of appropriate size */ + if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && + (EDID_CEA861_DB_LEN(*info, i) >= 5)) { + u8 *db = &info->data[i + 1]; + u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); + + if (oui == HDMI_IEEE_OUI) + return true; + } + i += EDID_CEA861_DB_LEN(*info, i) + 1; + } + + return false; +} + int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, int *panel_bits_per_colourp) { @@ -167,6 +214,15 @@ int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, ((edid->video_input_definition & 0x70) >> 3) + 4; } + timing->hdmi_monitor = false; + if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { + struct edid_cea861_info *info = + (struct edid_cea861_info *)(buf + sizeof(*edid)); + + if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) + timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); + } + return 0; } diff --git a/common/hash.c b/common/hash.c index b645298afc..a0eded98d0 100644 --- a/common/hash.c +++ b/common/hash.c @@ -473,5 +473,5 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, return 0; } -#endif -#endif +#endif /* CONFIG_CMD_HASH || CONFIG_CMD_SHA1SUM || CONFIG_CMD_CRC32) */ +#endif /* !USE_HOSTCC */ diff --git a/common/lcd.c b/common/lcd.c index 783626e3d5..2405146cf0 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -704,7 +704,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } break; #endif /* CONFIG_BMP_16BPP */ -#if defined(CONFIG_BMP_24BMP) +#if defined(CONFIG_BMP_24BPP) case 24: for (i = 0; i < height; ++i) { for (j = 0; j < width; j++) { @@ -716,7 +716,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) fb -= lcd_line_length + width * (bpix / 8); } break; -#endif /* CONFIG_BMP_24BMP */ +#endif /* CONFIG_BMP_24BPP */ #if defined(CONFIG_BMP_32BPP) case 32: for (i = 0; i < height; ++i) { diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f51ae2c484..eabb2d02ec 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -16,6 +16,14 @@ config SPL help If you want to build SPL as well as the normal image, say Y. +config SPL_BOARD_INIT + depends on SPL + bool "Call board-specific initialization in SPL" + help + If this option is enabled, U-Boot will call the function + spl_board_init() from board_init_r(). This function should be + provided by the board. + config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" depends on SPL @@ -179,6 +187,7 @@ config SPL_MD5_SUPPORT config SPL_SHA1_SUPPORT bool "Support SHA1" depends on SPL_FIT + select SHA1 help Enable this to support SHA1 in FIT images within SPL. A SHA1 checksum is a 160-bit (20-byte) hash value used to check that the @@ -190,6 +199,7 @@ config SPL_SHA1_SUPPORT config SPL_SHA256_SUPPORT bool "Support SHA256" depends on SPL_FIT + select SHA256 help Enable this to support SHA256 in FIT images within SPL. A SHA256 checksum is a 256-bit (32-byte) hash value used to check that the @@ -221,6 +231,8 @@ config SPL_CRYPTO_SUPPORT config SPL_HASH_SUPPORT bool "Support hashing drivers" + select SHA1 + select SHA256 depends on SPL help Enable hashing drivers in SPL. These drivers can be used to @@ -374,7 +386,7 @@ config SPL_LIBGENERIC_SUPPORT config SPL_MMC_SUPPORT bool "Support MMC" - depends on SPL && GENERIC_MMC + depends on SPL && MMC help Enable support for MMC (Multimedia Card) within SPL. This enables the MMC protocol implementation and allows any enabled drivers to @@ -693,6 +705,20 @@ config SPL_YMODEM_SUPPORT means of transmitting U-Boot over a serial line for using in SPL, with a checksum to ensure correctness. +config SPL_ATF_SUPPORT + bool "Support ARM Trusted Firmware" + depends on SPL && ARM64 + help + ATF(ARM Trusted Firmware) is a component for ARM arch64 which which + is loaded by SPL(which is considered as BL2 in ATF terminology). + More detail at: https://github.com/ARM-software/arm-trusted-firmware + +config SPL_ATF_TEXT_BASE + depends on SPL_ATF_SUPPORT + hex "ATF BL31 base address" + help + This is the base address in memory for ATF BL31 text and entry point. + config TPL_ENV_SUPPORT bool "Support an environment" depends on TPL @@ -729,7 +755,7 @@ config TPL_MPC8XXX_INIT_DDR_SUPPORT config TPL_MMC_SUPPORT bool "Support MMC" - depends on TPL + depends on TPL && MMC help Enable support for MMC within TPL. See SPL_MMC_SUPPORT for details. diff --git a/common/spl/Makefile b/common/spl/Makefile index 1933cbdfed..b3b34d6277 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -20,6 +20,7 @@ endif obj-$(CONFIG_SPL_UBI) += spl_ubi.o obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o +obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o diff --git a/common/spl/spl.c b/common/spl/spl.c index df984b8efd..0a49766f21 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -415,6 +415,11 @@ void board_init_r(gd_t *dummy1, ulong dummy2) gd->malloc_ptr / 1024); #endif + if (IS_ENABLED(CONFIG_SPL_ATF_SUPPORT)) { + debug("loaded - jumping to U-Boot via ATF BL31.\n"); + bl31_entry(); + } + debug("loaded - jumping to U-Boot...\n"); spl_board_prepare_for_boot(); jump_to_image_no_args(&spl_image); diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c new file mode 100644 index 0000000000..6e8f928044 --- /dev/null +++ b/common/spl/spl_atf.c @@ -0,0 +1,97 @@ +/* + * Reference to the ARM TF Project, + * plat/arm/common/arm_bl2_setup.c + * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights + * reserved. + * Copyright (C) 2016 Rockchip Electronic Co.,Ltd + * Written by Kever Yang <kever.yang@rock-chips.com> + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common.h> +#include <atf_common.h> +#include <errno.h> +#include <spl.h> + +static struct bl2_to_bl31_params_mem bl31_params_mem; +static struct bl31_params *bl2_to_bl31_params; + +/** + * bl2_plat_get_bl31_params() - prepare params for bl31. + * + * This function assigns a pointer to the memory that the platform has kept + * aside to pass platform specific and trusted firmware related information + * to BL31. This memory is allocated by allocating memory to + * bl2_to_bl31_params_mem structure which is a superset of all the + * structure whose information is passed to BL31 + * NOTE: This function should be called only once and should be done + * before generating params to BL31 + * + * @return bl31 params structure pointer + */ +struct bl31_params *bl2_plat_get_bl31_params(void) +{ + struct entry_point_info *bl33_ep_info; + + /* + * Initialise the memory for all the arguments that needs to + * be passed to BL31 + */ + memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem)); + + /* Assign memory for TF related information */ + bl2_to_bl31_params = &bl31_params_mem.bl31_params; + SET_PARAM_HEAD(bl2_to_bl31_params, ATF_PARAM_BL31, ATF_VERSION_1, 0); + + /* Fill BL31 related information */ + SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, + ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); + + /* Fill BL32 related information if it exists */ +#ifdef BL32_BASE + bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, ATF_PARAM_EP, + ATF_VERSION_1, 0); + bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, + ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); +#endif /* BL32_BASE */ + + /* Fill BL33 related information */ + bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; + bl33_ep_info = &bl31_params_mem.bl33_ep_info; + SET_PARAM_HEAD(bl33_ep_info, ATF_PARAM_EP, ATF_VERSION_1, + ATF_EP_NON_SECURE); + + /* BL33 expects to receive the primary CPU MPID (through x0) */ + bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); + bl33_ep_info->pc = CONFIG_SYS_TEXT_BASE; + bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXECPTIONS); + + bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, + ATF_PARAM_IMAGE_BINARY, ATF_VERSION_1, 0); + + return bl2_to_bl31_params; +} + +void raw_write_daif(unsigned int daif) +{ + __asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory"); +} + +void bl31_entry(void) +{ + struct bl31_params *bl31_params; + void (*entry)(struct bl31_params *params, void *plat_params) = NULL; + + bl31_params = bl2_plat_get_bl31_params(); + entry = (void *)CONFIG_SPL_ATF_TEXT_BASE; + + raw_write_daif(SPSR_EXCEPTION_MASK); + dcache_disable(); + + entry(bl31_params, NULL); +} diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index aae556f97d..4c42a96ca3 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -11,24 +11,30 @@ #include <libfdt.h> #include <spl.h> +#define FDT_ERROR ((ulong)(-1)) + static ulong fdt_getprop_u32(const void *fdt, int node, const char *prop) { const u32 *cell; int len; cell = fdt_getprop(fdt, node, prop, &len); - if (len != sizeof(*cell)) - return -1U; + if (!cell || len != sizeof(*cell)) + return FDT_ERROR; + return fdt32_to_cpu(*cell); } -static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp) +/* + * Iterate over all /configurations subnodes and call a platform specific + * function to find the matching configuration. + * Returns the node offset or a negative error number. + */ +static int spl_fit_find_config_node(const void *fdt) { - const char *name, *fdt_name; - int conf, node, fdt_node; - int len; + const char *name; + int conf, node, len; - *fdt_offsetp = 0; conf = fdt_path_offset(fdt, FIT_CONFS_PATH); if (conf < 0) { debug("%s: Cannot find /configurations node: %d\n", __func__, @@ -50,39 +56,69 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp) continue; debug("Selecting config '%s'", name); - fdt_name = fdt_getprop(fdt, node, FIT_FDT_PROP, &len); - if (!fdt_name) { - debug("%s: Cannot find fdt name property: %d\n", - __func__, len); - return -EINVAL; - } - debug(", fdt '%s'\n", fdt_name); - fdt_node = fdt_subnode_offset(fdt, images, fdt_name); - if (fdt_node < 0) { - debug("%s: Cannot find fdt node '%s': %d\n", - __func__, fdt_name, fdt_node); - return -EINVAL; + return node; + } + + return -ENOENT; +} + +/** + * spl_fit_get_image_node(): By using the matching configuration subnode, + * retrieve the name of an image, specified by a property name and an index + * into that. + * @fit: Pointer to the FDT blob. + * @images: Offset of the /images subnode. + * @type: Name of the property within the configuration subnode. + * @index: Index into the list of strings in this property. + * + * Return: the node offset of the respective image node or a negative + * error number. + */ +static int spl_fit_get_image_node(const void *fit, int images, + const char *type, int index) +{ + const char *name, *str; + int node, conf_node; + int len, i; + + conf_node = spl_fit_find_config_node(fit); + if (conf_node < 0) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("No matching DT out of these options:\n"); + for (node = fdt_first_subnode(fit, conf_node); + node >= 0; + node = fdt_next_subnode(fit, node)) { + name = fdt_getprop(fit, node, "description", &len); + printf(" %s\n", name); } +#endif + return conf_node; + } - *fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset"); - len = fdt_getprop_u32(fdt, fdt_node, "data-size"); - debug("FIT: Selected '%s'\n", name); + name = fdt_getprop(fit, conf_node, type, &len); + if (!name) { + debug("cannot find property '%s': %d\n", type, len); + return -EINVAL; + } - return len; + str = name; + for (i = 0; i < index; i++) { + str = strchr(str, '\0') + 1; + if (!str || (str - name >= len)) { + debug("no string for index %d\n", index); + return -E2BIG; + } } -#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - printf("No matching DT out of these options:\n"); - for (node = fdt_first_subnode(fdt, conf); - node >= 0; - node = fdt_next_subnode(fdt, node)) { - name = fdt_getprop(fdt, node, "description", &len); - printf(" %s\n", name); + debug("%s: '%s'\n", type, str); + node = fdt_subnode_offset(fit, images, str); + if (node < 0) { + debug("cannot find image node '%s': %d\n", str, node); + return -EINVAL; } -#endif - return -ENOENT; + return node; } static int get_aligned_image_offset(struct spl_load_info *info, int offset) @@ -123,19 +159,82 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, return (data_size + info->bl_len - 1) / info->bl_len; } +/** + * spl_load_fit_image(): load the image described in a certain FIT node + * @info: points to information about the device to load data from + * @sector: the start sector of the FIT image on the device + * @fit: points to the flattened device tree blob describing the FIT + * image + * @base_offset: the beginning of the data area containing the actual + * image data, relative to the beginning of the FIT + * @node: offset of the DT node describing the image to load (relative + * to @fit) + * @image_info: will be filled with information about the loaded image + * If the FIT node does not contain a "load" (address) property, + * the image gets loaded to the address pointed to by the + * load_addr member in this struct. + * + * Return: 0 on success or a negative error number. + */ +static int spl_load_fit_image(struct spl_load_info *info, ulong sector, + void *fit, ulong base_offset, int node, + struct spl_image_info *image_info) +{ + ulong offset; + size_t length; + ulong load_addr, load_ptr; + void *src; + ulong overhead; + int nr_sectors; + int align_len = ARCH_DMA_MINALIGN - 1; + + offset = fdt_getprop_u32(fit, node, "data-offset"); + if (offset == FDT_ERROR) + return -ENOENT; + offset += base_offset; + length = fdt_getprop_u32(fit, node, "data-size"); + if (length == FDT_ERROR) + return -ENOENT; + load_addr = fdt_getprop_u32(fit, node, "load"); + if (load_addr == FDT_ERROR && image_info) + load_addr = image_info->load_addr; + load_ptr = (load_addr + align_len) & ~align_len; + + overhead = get_aligned_image_overhead(info, offset); + nr_sectors = get_aligned_image_size(info, length, offset); + + if (info->read(info, sector + get_aligned_image_offset(info, offset), + nr_sectors, (void*)load_ptr) != nr_sectors) + return -EIO; + debug("image: dst=%lx, offset=%lx, size=%lx\n", load_ptr, offset, + (unsigned long)length); + + src = (void *)load_ptr + overhead; +#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS + board_fit_image_post_process(&src, &length); +#endif + + memcpy((void*)load_addr, src, length); + + if (image_info) { + image_info->load_addr = load_addr; + image_info->size = length; + image_info->entry_point = fdt_getprop_u32(fit, node, "entry"); + } + + return 0; +} + int spl_load_simple_fit(struct spl_image_info *spl_image, struct spl_load_info *info, ulong sector, void *fit) { int sectors; - ulong size, load; + ulong size; unsigned long count; - int node, images; - void *load_ptr; - int fdt_offset, fdt_len; - int data_offset, data_size; + struct spl_image_info image_info; + int node, images, ret; int base_offset, align_len = ARCH_DMA_MINALIGN - 1; - int src_sector; - void *dst, *src; + int index = 0; /* * Figure out where the external images start. This is the base for the @@ -168,90 +267,82 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (count == 0) return -EIO; - /* find the firmware image to load */ + /* find the node holding the images information */ images = fdt_path_offset(fit, FIT_IMAGES_PATH); if (images < 0) { debug("%s: Cannot find /images node: %d\n", __func__, images); return -1; } - node = fdt_first_subnode(fit, images); + + /* find the U-Boot image */ + node = spl_fit_get_image_node(fit, images, "firmware", 0); + if (node < 0) { + debug("could not find firmware image, trying loadables...\n"); + node = spl_fit_get_image_node(fit, images, "loadables", 0); + /* + * If we pick the U-Boot image from "loadables", start at + * the second image when later loading additional images. + */ + index = 1; + } if (node < 0) { - debug("%s: Cannot find first image node: %d\n", __func__, node); + debug("%s: Cannot find u-boot image node: %d\n", + __func__, node); return -1; } - /* Get its information and set up the spl_image structure */ - data_offset = fdt_getprop_u32(fit, node, "data-offset"); - data_size = fdt_getprop_u32(fit, node, "data-size"); - load = fdt_getprop_u32(fit, node, "load"); - debug("data_offset=%x, data_size=%x\n", data_offset, data_size); - spl_image->load_addr = load; - spl_image->entry_point = load; - spl_image->os = IH_OS_U_BOOT; - - /* - * Work out where to place the image. We read it so that the first - * byte will be at 'load'. This may mean we need to load it starting - * before then, since we can only read whole blocks. - */ - data_offset += base_offset; - sectors = get_aligned_image_size(info, data_size, data_offset); - load_ptr = (void *)load; - debug("U-Boot size %x, data %p\n", data_size, load_ptr); - dst = load_ptr; - - /* Read the image */ - src_sector = sector + get_aligned_image_offset(info, data_offset); - debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n", - dst, src_sector, sectors); - count = info->read(info, src_sector, sectors, dst); - if (count != sectors) - return -EIO; - debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset, - data_size); - src = dst + get_aligned_image_overhead(info, data_offset); + /* Load the image and set up the spl_image structure */ + ret = spl_load_fit_image(info, sector, fit, base_offset, node, + spl_image); + if (ret) + return ret; -#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS - board_fit_image_post_process((void **)&src, (size_t *)&data_size); -#endif - - memcpy(dst, src, data_size); + spl_image->os = IH_OS_U_BOOT; /* Figure out which device tree the board wants to use */ - fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset); - if (fdt_len < 0) - return fdt_len; + node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0); + if (node < 0) { + debug("%s: cannot find FDT node\n", __func__); + return node; + } /* - * Read the device tree and place it after the image. There may be - * some extra data before it since we can only read entire blocks. - * And also align the destination address to ARCH_DMA_MINALIGN. + * Read the device tree and place it after the image. + * Align the destination address to ARCH_DMA_MINALIGN. */ - dst = (void *)((load + data_size + align_len) & ~align_len); - fdt_offset += base_offset; - sectors = get_aligned_image_size(info, fdt_len, fdt_offset); - src_sector = sector + get_aligned_image_offset(info, fdt_offset); - count = info->read(info, src_sector, sectors, dst); - debug("Aligned fdt read: dst %p, src_sector = %x, sectors %x\n", - dst, src_sector, sectors); - if (count != sectors) - return -EIO; + image_info.load_addr = spl_image->load_addr + spl_image->size; + ret = spl_load_fit_image(info, sector, fit, base_offset, node, + &image_info); + if (ret < 0) + return ret; + + /* Now check if there are more images for us to load */ + for (; ; index++) { + node = spl_fit_get_image_node(fit, images, "loadables", index); + if (node < 0) + break; + + ret = spl_load_fit_image(info, sector, fit, base_offset, node, + &image_info); + if (ret < 0) + continue; + + /* + * If the "firmware" image did not provide an entry point, + * use the first valid entry point from the loadables. + */ + if (spl_image->entry_point == FDT_ERROR && + image_info.entry_point != FDT_ERROR) + spl_image->entry_point = image_info.entry_point; + } /* - * Copy the device tree so that it starts immediately after the image. - * After this we will have the U-Boot image and its device tree ready - * for us to start. + * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's + * Makefile will set it to 0 and it will end up as the entry point + * here. What it actually means is: use the load address. */ - debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset, - fdt_len); - src = dst + get_aligned_image_overhead(info, fdt_offset); - dst = load_ptr + data_size; - -#ifdef CONFIG_SPL_FIT_IMAGE_POST_PROCESS - board_fit_image_post_process((void **)&src, (size_t *)&fdt_len); -#endif - - memcpy(dst, src, fdt_len); + if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0) + spl_image->entry_point = spl_image->load_addr; return 0; } diff --git a/common/stdio.c b/common/stdio.c index 4d30017530..ee4f0bda9e 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -21,7 +21,7 @@ #include <logbuff.h> #endif -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) +#if defined(CONFIG_SYS_I2C) #include <i2c.h> #endif @@ -346,9 +346,6 @@ int stdio_add_devices(void) #ifdef CONFIG_SYS_I2C i2c_init_all(); #else -#if defined(CONFIG_HARD_I2C) - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif #endif #ifdef CONFIG_DM_VIDEO /* diff --git a/common/usb_storage.c b/common/usb_storage.c index 83279c449d..03171f74cb 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -100,7 +100,7 @@ struct us_data { trans_cmnd transport; /* transport routine */ }; -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD /* * The U-Boot EHCI driver can handle any transfer length as long as there is * enough free heap space left, but the SCSI READ(10) and WRITE(10) commands are diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig index 88964b30bd..42f085a47c 100644 --- a/configs/C29XPCIE_NAND_defconfig +++ b/configs/C29XPCIE_NAND_defconfig @@ -20,6 +20,7 @@ CONFIG_TPL_ENV_SUPPORT=y CONFIG_TPL_I2C_SUPPORT=y CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig index 58e618b628..99e2b33ac7 100644 --- a/configs/C29XPCIE_NOR_SECBOOT_defconfig +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -10,6 +10,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig index d0565032e8..26544f4ab6 100644 --- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig index 5b595b8425..41bf176650 100644 --- a/configs/C29XPCIE_SPIFLASH_defconfig +++ b/configs/C29XPCIE_SPIFLASH_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig index 62881024a8..70b447863d 100644 --- a/configs/C29XPCIE_defconfig +++ b/configs/C29XPCIE_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig index 96a7643ca4..735993b76d 100644 --- a/configs/CPCI2DP_defconfig +++ b/configs/CPCI2DP_defconfig @@ -5,6 +5,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig index 4d818d7b7c..550db77a17 100644 --- a/configs/CPCI4052_defconfig +++ b/configs/CPCI4052_defconfig @@ -9,7 +9,9 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig index 443eec675b..8e036d223b 100644 --- a/configs/Cyrus_P5020_defconfig +++ b/configs/Cyrus_P5020_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_NETDEVICES=y diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig index 7400f3978d..ee4da81d3e 100644 --- a/configs/Cyrus_P5040_defconfig +++ b/configs/Cyrus_P5040_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_NETDEVICES=y diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index e756401162..903eef536c 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index 4f9d97ee55..d657f863d0 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -12,6 +12,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 789dddb901..09640de1ec 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5253DEMO=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig index 5b3a2fe742..79941a1253 100644 --- a/configs/M5253EVBE_defconfig +++ b/configs/M5253EVBE_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_TARGET_M5253EVBE=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index 3aed04e813..221c70750b 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x04000000 CONFIG_TARGET_M54455EVB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666" CONFIG_BOOTDELAY=1 +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y @@ -16,6 +17,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index 6f624e6a00..557b87b78c 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_M54455EVB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333" CONFIG_BOOTDELAY=1 CONFIG_SYS_PROMPT="-> " +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y @@ -17,6 +18,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index ecc610b74b..9ad0564788 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_M54455EVB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666" CONFIG_BOOTDELAY=1 +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y @@ -16,6 +17,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index 93756b2e27..dc7af6cb19 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_M54455EVB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333" CONFIG_BOOTDELAY=1 +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y @@ -16,6 +17,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index f10027693d..eed2eabe68 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x4FE00000 CONFIG_TARGET_M54455EVB=y CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333" CONFIG_BOOTDELAY=1 +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y @@ -16,6 +17,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig index 833c263bb6..da3bbaeb14 100644 --- a/configs/MIP405T_defconfig +++ b/configs/MIP405T_defconfig @@ -11,6 +11,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -20,6 +22,7 @@ CONFIG_CMD_BSP=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig index 3da515295e..461416773c 100644 --- a/configs/MIP405_defconfig +++ b/configs/MIP405_defconfig @@ -11,6 +11,8 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -21,6 +23,7 @@ CONFIG_CMD_BSP=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index dbe060f001..38417e7964 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -16,5 +16,6 @@ CONFIG_CMD_EXT2=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 6470850e4e..54d8a3ea1d 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index a97ce25a28..9cec452cd5 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000" CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="MPC8349E-mITX> " +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -20,5 +21,6 @@ CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index c61f260dc3..9145ada7c7 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX" CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="MPC8349E-mITX> " +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -20,5 +21,6 @@ CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 774ecb81b5..787ac9dbce 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -17,5 +17,6 @@ CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 717fee1cfe..2f3e7b0162 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -17,5 +17,6 @@ CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig index 106a37dd9b..6c3a044e61 100644 --- a/configs/MPC8536DS_36BIT_defconfig +++ b/configs/MPC8536DS_36BIT_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8536DS=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y @@ -15,6 +16,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_FSL_DDR2=y diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig index 2e0b81cf89..761c1652b1 100644 --- a/configs/MPC8536DS_SDCARD_defconfig +++ b/configs/MPC8536DS_SDCARD_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -15,6 +16,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_FSL_DDR2=y diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig index 92d7247689..156c8590ba 100644 --- a/configs/MPC8536DS_SPIFLASH_defconfig +++ b/configs/MPC8536DS_SPIFLASH_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -15,6 +16,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_FSL_DDR2=y diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig index e835d6a620..589ad9edbc 100644 --- a/configs/MPC8536DS_defconfig +++ b/configs/MPC8536DS_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8536DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -14,6 +15,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_SYS_FSL_DDR2=y diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig index ec570dadbe..cef9c11209 100644 --- a/configs/MPC8540ADS_defconfig +++ b/configs/MPC8540ADS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8540ADS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -7,6 +8,7 @@ CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig index 9c685ff321..8268388d84 100644 --- a/configs/MPC8541CDS_defconfig +++ b/configs/MPC8541CDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8541CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -8,6 +9,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig index 36fd96f72f..09a9c0f90b 100644 --- a/configs/MPC8541CDS_legacy_defconfig +++ b/configs/MPC8541CDS_legacy_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8541CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -9,6 +10,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig index d8aa8e75f8..1798622e34 100644 --- a/configs/MPC8544DS_defconfig +++ b/configs/MPC8544DS_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8544DS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,6 +12,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 65a339f12f..277043e4a0 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_PHYS_64BIT=y CONFIG_OF_BOARD_SETUP=y @@ -9,6 +10,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 3b194e0cfe..a0c2f00652 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -8,6 +9,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 0e0acbb480..4ea1b9da92 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -9,6 +10,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig index da6ff47ece..00c7a76508 100644 --- a/configs/MPC8555CDS_defconfig +++ b/configs/MPC8555CDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8555CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -8,6 +9,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig index b5ffd59120..36da612318 100644 --- a/configs/MPC8555CDS_legacy_defconfig +++ b/configs/MPC8555CDS_legacy_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8555CDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -9,6 +10,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig index 68d0f5479d..2ceab0d4ee 100644 --- a/configs/MPC8560ADS_defconfig +++ b/configs/MPC8560ADS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8560ADS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -7,6 +8,7 @@ CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig index 701bff259a..c41712f490 100644 --- a/configs/MPC8568MDS_defconfig +++ b/configs/MPC8568MDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8568MDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -9,6 +10,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig index 4722dfe3e6..cbbf4bc1ee 100644 --- a/configs/MPC8569MDS_ATM_defconfig +++ b/configs/MPC8569MDS_ATM_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8569MDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,6 +12,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig index c5a7991d4d..45c4f547db 100644 --- a/configs/MPC8569MDS_defconfig +++ b/configs/MPC8569MDS_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8569MDS=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -10,6 +11,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig index a1640e3047..521badc5ad 100644 --- a/configs/MPC8572DS_36BIT_defconfig +++ b/configs/MPC8572DS_36BIT_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_SYS_FSL_DDR2=y # CONFIG_MMC is not set diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig index 1cb830f6a8..2821c8c40b 100644 --- a/configs/MPC8572DS_defconfig +++ b/configs/MPC8572DS_defconfig @@ -13,6 +13,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_SYS_FSL_DDR2=y # CONFIG_MMC is not set diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig index 7d719f81f5..b9cbafc887 100644 --- a/configs/MiniFAP_defconfig +++ b/configs/MiniFAP_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -19,9 +19,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig index 38101f05df..c0e9541b87 100644 --- a/configs/O2D300_defconfig +++ b/configs/O2D300_defconfig @@ -4,7 +4,6 @@ CONFIG_TARGET_O2D300=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig index 83006e5582..8cff44cf36 100644 --- a/configs/O2DNT2_RAMBOOT_defconfig +++ b/configs/O2DNT2_RAMBOOT_defconfig @@ -8,7 +8,6 @@ CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" CONFIG_AUTOBOOT_STOP_STR="++++++++++" -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig index 4202d85203..f29abb83bc 100644 --- a/configs/O2DNT2_defconfig +++ b/configs/O2DNT2_defconfig @@ -7,7 +7,6 @@ CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n" CONFIG_AUTOBOOT_STOP_STR="++++++++++" -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig index b84a1c8839..534cfe12e2 100644 --- a/configs/O2D_defconfig +++ b/configs/O2D_defconfig @@ -4,7 +4,6 @@ CONFIG_TARGET_O2D=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig index efcc769ff4..acf42abe29 100644 --- a/configs/O2I_defconfig +++ b/configs/O2I_defconfig @@ -4,7 +4,6 @@ CONFIG_TARGET_O2I=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig index abdc53df21..de647c76b9 100644 --- a/configs/O2MNT_O2M110_defconfig +++ b/configs/O2MNT_O2M110_defconfig @@ -5,7 +5,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\"" CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig index 06089fe3cf..b243e9cc0e 100644 --- a/configs/O2MNT_O2M112_defconfig +++ b/configs/O2MNT_O2M112_defconfig @@ -5,7 +5,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\"" CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig index 1ea3f3a09b..1584058289 100644 --- a/configs/O2MNT_O2M113_defconfig +++ b/configs/O2MNT_O2M113_defconfig @@ -5,7 +5,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\"" CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig index 0209085605..20bd31466e 100644 --- a/configs/O2MNT_defconfig +++ b/configs/O2MNT_defconfig @@ -4,7 +4,6 @@ CONFIG_TARGET_O2MNT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig index 5ce4140859..ea769e7edc 100644 --- a/configs/O3DNT_defconfig +++ b/configs/O3DNT_defconfig @@ -4,7 +4,6 @@ CONFIG_TARGET_O3DNT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig index e50bbb7e41..e297a0da5b 100644 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020MBG=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig index 45620a93b2..c8df31d1a0 100644 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020MBG=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig index 6d8041fed9..a5bdec3de2 100644 --- a/configs/P1020MBG-PC_SDCARD_defconfig +++ b/configs/P1020MBG-PC_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020MBG=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -23,6 +24,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig index c0dd859a03..a9bae76a4b 100644 --- a/configs/P1020MBG-PC_defconfig +++ b/configs/P1020MBG-PC_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020MBG=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -14,6 +15,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 4b94619350..56a0297520 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -27,6 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index b5837ca7a9..4d882264bb 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 59c05f894f..324c6a055c 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 85fbc05f0f..8e275e0bd5 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -16,6 +17,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index c817ff38fc..71c0c2d4bf 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 1a7f5cd5f7..9d994810cc 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 13e63c76fa..79cba1a071 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 19febe4cc9..11f5961bd4 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 698d362835..eb9d2635b9 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 67dbcface5..e6373f4200 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 7b58c085cb..60f5ab3206 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index ce1bfa2e24..30257b64f5 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig index b9bc52e75e..1d31e0fdc5 100644 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020UTM=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig index f25d19bb6f..031a7f2ced 100644 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020UTM=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig index b2535524a7..d401a8ce3e 100644 --- a/configs/P1020UTM-PC_SDCARD_defconfig +++ b/configs/P1020UTM-PC_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020UTM=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -23,6 +24,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig index 2e367099ed..c6e12d6c35 100644 --- a/configs/P1020UTM-PC_defconfig +++ b/configs/P1020UTM-PC_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020UTM=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -14,6 +15,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig index 034db7d95e..f6bbf7db4b 100644 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -27,6 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig index 7848b59340..bbeeba0bc8 100644 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig index 7b187cd123..ec326a089a 100644 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig index 82a2637bf4..42ab8b95b1 100644 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -16,6 +17,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig index a31cc06d07..a9af7462a1 100644 --- a/configs/P1021RDB-PC_NAND_defconfig +++ b/configs/P1021RDB-PC_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig index b74bc65302..ca77237cf4 100644 --- a/configs/P1021RDB-PC_SDCARD_defconfig +++ b/configs/P1021RDB-PC_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig index 48f66b211a..86052a4c7d 100644 --- a/configs/P1021RDB-PC_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig index c7d109cb56..6aff0a0a9d 100644 --- a/configs/P1021RDB-PC_defconfig +++ b/configs/P1021RDB-PC_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1021RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig index 77436fefd5..9c83a469a8 100644 --- a/configs/P1022DS_36BIT_NAND_defconfig +++ b/configs/P1022DS_36BIT_NAND_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig index fee2a7b4d3..e1f9a9888d 100644 --- a/configs/P1022DS_36BIT_SDCARD_defconfig +++ b/configs/P1022DS_36BIT_SDCARD_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig index 1601239ee9..25521d8787 100644 --- a/configs/P1022DS_36BIT_SPIFLASH_defconfig +++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig index c2bdc48409..58335cbab0 100644 --- a/configs/P1022DS_36BIT_defconfig +++ b/configs/P1022DS_36BIT_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig index f02457fac1..04bb7a13cd 100644 --- a/configs/P1022DS_NAND_defconfig +++ b/configs/P1022DS_NAND_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig index a35f53bdbf..af7b4dbd5e 100644 --- a/configs/P1022DS_SDCARD_defconfig +++ b/configs/P1022DS_SDCARD_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig index 30ac31e44a..22c3b6b278 100644 --- a/configs/P1022DS_SPIFLASH_defconfig +++ b/configs/P1022DS_SPIFLASH_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig index 45a1f912b0..c0864a44e9 100644 --- a/configs/P1022DS_defconfig +++ b/configs/P1022DS_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig index 5a45c7b4c9..c53b7e0819 100644 --- a/configs/P1023RDB_defconfig +++ b/configs/P1023RDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1023RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -8,10 +9,12 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=-1 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +# CONFIG_CMD_EEPROM is not set CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig index 80880d6daa..5b2773abc6 100644 --- a/configs/P1024RDB_36BIT_defconfig +++ b/configs/P1024RDB_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1024RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -16,6 +17,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig index d832d3c070..3a563f5c32 100644 --- a/configs/P1024RDB_NAND_defconfig +++ b/configs/P1024RDB_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig index 9343fbba1e..69348a6069 100644 --- a/configs/P1024RDB_SDCARD_defconfig +++ b/configs/P1024RDB_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig index a500b09d66..ae12d7c03e 100644 --- a/configs/P1024RDB_SPIFLASH_defconfig +++ b/configs/P1024RDB_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig index 5253acf01f..56bd118dd5 100644 --- a/configs/P1024RDB_defconfig +++ b/configs/P1024RDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1024RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig index 23c57c787c..50ac75d701 100644 --- a/configs/P1025RDB_36BIT_defconfig +++ b/configs/P1025RDB_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1025RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -16,6 +17,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig index b6d0dc663d..221d4ae9f2 100644 --- a/configs/P1025RDB_NAND_defconfig +++ b/configs/P1025RDB_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -27,6 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig index 3165ca1b61..43fed3530e 100644 --- a/configs/P1025RDB_SDCARD_defconfig +++ b/configs/P1025RDB_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig index a8901c15bf..672b7bbbf9 100644 --- a/configs/P1025RDB_SPIFLASH_defconfig +++ b/configs/P1025RDB_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig index d8cb2cbb28..22bfb2edcf 100644 --- a/configs/P1025RDB_defconfig +++ b/configs/P1025RDB_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1025RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index e0fdd36b51..86a38b85e2 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -28,6 +29,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 218a00afc8..f67d7cd586 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index e7c491a4a9..ee8227a5ba 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 4de5745d2e..e40e371bf5 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y @@ -16,6 +17,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 332dc8071d..4b2651c8e6 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_TPL_LIBGENERIC_SUPPORT=y CONFIG_TPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -26,6 +27,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 0275b6c303..f4cb697687 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 400c813887..5091022f81 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -25,6 +26,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index e4038c6c73..df1dbffaa4 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig index fbf3227fc0..cd78de7b4b 100644 --- a/configs/PATI_defconfig +++ b/configs/PATI_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_PROMPT="pati=> " # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ECHO is not set # CONFIG_CMD_ITEST is not set @@ -20,6 +21,7 @@ CONFIG_SYS_PROMPT="pati=> " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_BSP=y +CONFIG_CMD_IRQ=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig index 4c2d558b85..07f1b54ae9 100644 --- a/configs/PIP405_defconfig +++ b/configs/PIP405_defconfig @@ -11,8 +11,11 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y +CONFIG_CMD_FDC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig index 5b679760e6..e30a720688 100644 --- a/configs/PLU405_defconfig +++ b/configs/PLU405_defconfig @@ -9,6 +9,8 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig index 0dd9ca7ff6..cdc54aedcb 100644 --- a/configs/PMC405DE_defconfig +++ b/configs/PMC405DE_defconfig @@ -10,6 +10,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig index 6b8854b5d8..6ef60587b6 100644 --- a/configs/PMC440_defconfig +++ b/configs/PMC440_defconfig @@ -10,6 +10,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y @@ -20,6 +21,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_BSP=y CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +# CONFIG_CMD_IRQ is not set CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig index bf239bd104..c22bf9ce8c 100644 --- a/configs/T1040D4RDB_NAND_defconfig +++ b/configs/T1040D4RDB_NAND_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig index e6a5b83f7f..63010c546c 100644 --- a/configs/T1040D4RDB_SDCARD_defconfig +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index b0edffaacf..47582578cf 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_DM=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig index e99809be3d..2a872b930f 100644 --- a/configs/T1040D4RDB_SPIFLASH_defconfig +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig index 355d6ab3f0..82d6140518 100644 --- a/configs/T1040D4RDB_defconfig +++ b/configs/T1040D4RDB_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig index 6ebde4d2df..063ae20c83 100644 --- a/configs/T1040QDS_DDR4_defconfig +++ b/configs/T1040QDS_DDR4_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_BMP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index e437cdac35..a75ee03bcf 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_BMP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig index 7b96193c85..5d8cdf1383 100644 --- a/configs/T1040QDS_defconfig +++ b/configs/T1040QDS_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_BMP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index a427cf18c4..b3e9c412b9 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index 2d2585f8c1..7b2187cf9c 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index c15f600d50..f16834b85c 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_DM=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index f0c60001c3..9f5a8c4e9c 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index 1fca4a411b..7d6ed1bb72 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -18,6 +18,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index d38b221697..8e7b677725 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +# CONFIG_CMD_IRQ is not set CONFIG_FSL_CAAM=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index c039f95d9d..fac743f55c 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +# CONFIG_CMD_IRQ is not set CONFIG_FSL_CAAM=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index f7c3788b55..f8296387c4 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -19,6 +19,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +# CONFIG_CMD_IRQ is not set CONFIG_DM=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index c00421f525..ca7a38b7d2 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +# CONFIG_CMD_IRQ is not set CONFIG_FSL_CAAM=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 3fd4236ae7..2829d06d27 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +# CONFIG_CMD_IRQ is not set CONFIG_FSL_CAAM=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 595fbbb613..424eda104e 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +# CONFIG_CMD_IRQ is not set CONFIG_FSL_CAAM=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig index d0cd50a63c..5e6f9c951f 100644 --- a/configs/TQM5200S_HIGHBOOT_defconfig +++ b/configs/TQM5200S_HIGHBOOT_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -15,9 +15,9 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig index 5324a9a11c..d0c352faa1 100644 --- a/configs/TQM5200S_defconfig +++ b/configs/TQM5200S_defconfig @@ -7,7 +7,7 @@ CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -15,9 +15,9 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig index 2f933e6cab..ed74408b98 100644 --- a/configs/TQM5200_B_HIGHBOOT_defconfig +++ b/configs/TQM5200_B_HIGHBOOT_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -19,9 +19,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig index f204484f59..cc9968cacb 100644 --- a/configs/TQM5200_B_defconfig +++ b/configs/TQM5200_B_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -19,9 +19,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig index db9bb8a30d..35d486033b 100644 --- a/configs/TQM5200_STK100_defconfig +++ b/configs/TQM5200_STK100_defconfig @@ -10,7 +10,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -19,9 +19,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig index eec60f1be4..783c39a052 100644 --- a/configs/TQM5200_defconfig +++ b/configs/TQM5200_defconfig @@ -9,7 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -18,9 +18,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig index 89f2ecb104..ccb68b24c5 100644 --- a/configs/TQM823L_LCD_defconfig +++ b/configs/TQM823L_LCD_defconfig @@ -7,12 +7,14 @@ CONFIG_BOOTDELAY=5 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig index e2681ad715..c588948e11 100644 --- a/configs/TQM823L_defconfig +++ b/configs/TQM823L_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig index 829942ef62..0490828504 100644 --- a/configs/TQM823M_defconfig +++ b/configs/TQM823M_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index b03f79ef39..ef73ed40c8 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -6,6 +6,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -13,6 +14,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig index 2c24844683..0e42d8c4fe 100644 --- a/configs/TQM850L_defconfig +++ b/configs/TQM850L_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig index a6882aab4d..a464fe507a 100644 --- a/configs/TQM850M_defconfig +++ b/configs/TQM850M_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig index 8be81ae2a4..aa370012f5 100644 --- a/configs/TQM855L_defconfig +++ b/configs/TQM855L_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig index ea0ad4df9f..faab826a24 100644 --- a/configs/TQM855M_defconfig +++ b/configs/TQM855M_defconfig @@ -5,11 +5,14 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig index e65b01fc36..b18cf31ddd 100644 --- a/configs/TQM860L_defconfig +++ b/configs/TQM860L_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig index 5c69085fdb..fe2fe6d38c 100644 --- a/configs/TQM860M_defconfig +++ b/configs/TQM860M_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig index f3d077c4bd..6f5f772d32 100644 --- a/configs/TQM862L_defconfig +++ b/configs/TQM862L_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig index 3069dcbadd..44307760ee 100644 --- a/configs/TQM862M_defconfig +++ b/configs/TQM862M_defconfig @@ -5,11 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig index c3297773af..d8922900d4 100644 --- a/configs/TQM866M_defconfig +++ b/configs/TQM866M_defconfig @@ -5,10 +5,13 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_LED_STATUS=y diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig index 4ecdf6db83..48421e3cfe 100644 --- a/configs/TQM885D_defconfig +++ b/configs/TQM885D_defconfig @@ -5,7 +5,9 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig index e0493a12fb..9d26e94615 100644 --- a/configs/TTTech_defconfig +++ b/configs/TTTech_defconfig @@ -7,12 +7,14 @@ CONFIG_BOOTDELAY=5 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig index 2efc09d534..e210643aa4 100644 --- a/configs/TWR-P1025_defconfig +++ b/configs/TWR-P1025_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1_TWR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -9,11 +10,13 @@ CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" CONFIG_BOOTDELAY=10 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig index da538afb52..2fc8d86046 100644 --- a/configs/UCP1020_SPIFLASH_defconfig +++ b/configs/UCP1020_SPIFLASH_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_DATE=y CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT2=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index c7ec446867..63f1a9d005 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_DATE=y CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT2=y diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig index 23d33a649f..c19c11d162 100644 --- a/configs/VOM405_defconfig +++ b/configs/VOM405_defconfig @@ -6,6 +6,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig index 8d636e03d2..a461b809c6 100644 --- a/configs/a3m071_defconfig +++ b/configs/a3m071_defconfig @@ -10,6 +10,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/a4m072_defconfig b/configs/a4m072_defconfig index ce5edcbf01..4fbffb6edc 100644 --- a/configs/a4m072_defconfig +++ b/configs/a4m072_defconfig @@ -7,7 +7,7 @@ CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="asdfg" -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig index c3ee19945c..3100da6c6e 100644 --- a/configs/a4m2k_defconfig +++ b/configs/a4m2k_defconfig @@ -11,6 +11,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/ac14xx_defconfig b/configs/ac14xx_defconfig index e3b7793e04..6855331860 100644 --- a/configs/ac14xx_defconfig +++ b/configs/ac14xx_defconfig @@ -5,11 +5,11 @@ CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_PROMPT="ac14xx> " CONFIG_CMD_ASKENV=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig index a30e34dea3..652d01eb08 100644 --- a/configs/acadia_defconfig +++ b/configs/acadia_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig new file mode 100644 index 0000000000..cbef412764 --- /dev/null +++ b/configs/adp-ae3xx_defconfig @@ -0,0 +1,28 @@ +CONFIG_NDS32=y +CONFIG_TARGET_ADP_AE3XX=y +CONFIG_DEFAULT_DEVICE_TREE="ae3xx" +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_PROMPT="NDS32 # " +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_DATE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_MMC=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_BAUDRATE=38400 +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_MTD=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_FTMAC100=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_TIMER=y +CONFIG_AE3XX_TIMER=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 48d08cc44b..22b1182fef 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -1,9 +1,12 @@ CONFIG_NDS32=y CONFIG_TARGET_ADP_AG101P=y +CONFIG_DEFAULT_DEVICE_TREE="ag101p" +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="NDS32 # " CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y @@ -12,4 +15,12 @@ CONFIG_CMD_FAT=y CONFIG_MMC=y CONFIG_MTD_NOR_FLASH=y CONFIG_BAUDRATE=38400 +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_DM_ETH=y +CONFIG_FTMAC100=y +CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_TIMER=y +CONFIG_AG101P_TIMER=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index b8e2864ff4..04dda72532 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index dfbb812d65..590673b37c 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -29,6 +29,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index c3237f51e4..962bb65443 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -48,4 +48,3 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0451 CONFIG_G_DNL_PRODUCT_NUM=0xd022 CONFIG_RSA=y -CONFIG_SPL_OF_LIBFDT=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 000099eb1f..55ed8f3654 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MUSB_NEW_SUPPORT=y CONFIG_SPL_OS_BOOT=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 994540d6f0..bae1dfec23 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_AUTOBOOT is not set # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig index 81fec1e082..2a0987e555 100644 --- a/configs/am3517_crane_defconfig +++ b/configs/am3517_crane_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index fa203f8834..6a307066eb 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -16,6 +16,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 65d5d837bb..84766e8674 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -13,6 +13,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 50cca204c3..a98a97fa42 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -20,6 +20,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index 2550aeecb7..40055f04d8 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -50,3 +50,4 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_AR933X_UART=y CONFIG_DM_SPI=y CONFIG_ATH79_SPI=y +CONFIG_LZMA=y diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 0753221d7f..05f1699748 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -46,3 +46,4 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_ATH79_SPI=y +CONFIG_LZMA=y diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig index fd30665753..ebefd126a8 100644 --- a/configs/ap325rxa_defconfig +++ b/configs/ap325rxa_defconfig @@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ECHO is not set # CONFIG_CMD_ITEST is not set diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig index 75cf53fe21..41c8be9120 100644 --- a/configs/ap_sh4a_4a_defconfig +++ b/configs/ap_sh4a_4a_defconfig @@ -13,7 +13,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_CMD_ENV_EXISTS is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set -CONFIG_CMD_I2C=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ECHO is not set # CONFIG_CMD_ITEST is not set diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 648be92fcb..74cea3170e 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -38,6 +38,7 @@ CONFIG_PMIC_AS3722=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index d4dc1d3865..f586773761 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_APALIS_IMX6=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set @@ -40,7 +41,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig index 87affc0bdb..42abbbd49d 100644 --- a/configs/apalis_imx6_nospl_com_defconfig +++ b/configs/apalis_imx6_nospl_com_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_APALIS_IMX6=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set @@ -33,7 +34,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig index 97a4d2c1ed..18f0d02e55 100644 --- a/configs/apalis_imx6_nospl_it_defconfig +++ b/configs/apalis_imx6_nospl_it_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_APALIS_IMX6=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set @@ -33,7 +34,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index a31b912968..8557df9c3f 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -37,6 +37,7 @@ CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index 71839f575e..7474fdd994 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="BIOS> " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig index e2061a2cce..8bc1770ec2 100644 --- a/configs/apx4devkit_defconfig +++ b/configs/apx4devkit_defconfig @@ -14,18 +14,17 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_MMC_MXS=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/arches_defconfig b/configs/arches_defconfig index 4477bab5ee..e0621f0ca7 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/aria_defconfig b/configs/aria_defconfig index 963661ab2d..0613dd16fb 100644 --- a/configs/aria_defconfig +++ b/configs/aria_defconfig @@ -5,11 +5,11 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index a2cde44386..0f2aa16e0e 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -34,4 +34,5 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig index 26654426ed..0ac39eabd2 100644 --- a/configs/aspenite_defconfig +++ b/configs/aspenite_defconfig @@ -6,7 +6,6 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index d5e84308d6..888bb334bf 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -5,9 +5,11 @@ CONFIG_BOOTDELAY=1 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="URMEL > " CONFIG_CMD_I2C=y +CONFIG_CMD_FPGA_LOADMK=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/atngw100_defconfig b/configs/atngw100_defconfig index 1e85f0af33..17db763867 100644 --- a/configs/atngw100_defconfig +++ b/configs/atngw100_defconfig @@ -19,6 +19,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MMC=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/atngw100mkii_defconfig b/configs/atngw100mkii_defconfig index 2fa5b6954d..887c5fb8d7 100644 --- a/configs/atngw100mkii_defconfig +++ b/configs/atngw100mkii_defconfig @@ -19,6 +19,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MMC=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/atstk1002_defconfig b/configs/atstk1002_defconfig index 49182e33c4..0fa7969e47 100644 --- a/configs/atstk1002_defconfig +++ b/configs/atstk1002_defconfig @@ -17,5 +17,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MMC=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig index 44d91984bb..41ce230481 100644 --- a/configs/bamboo_defconfig +++ b/configs/bamboo_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig index 4f045903bf..61336d38f0 100644 --- a/configs/bcm911360_entphn-ns_defconfig +++ b/configs/bcm911360_entphn-ns_defconfig @@ -18,4 +18,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_OF_LIBFDT=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig index 2469792f68..cbef3d8365 100644 --- a/configs/bcm911360_entphn_defconfig +++ b/configs/bcm911360_entphn_defconfig @@ -18,4 +18,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_OF_LIBFDT=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig index 83afce41d6..b124206361 100644 --- a/configs/bcm911360k_defconfig +++ b/configs/bcm911360k_defconfig @@ -18,4 +18,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig index b21fea4331..f271fa06e5 100644 --- a/configs/bcm958300k-ns_defconfig +++ b/configs/bcm958300k-ns_defconfig @@ -18,4 +18,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig index 83afce41d6..b124206361 100644 --- a/configs/bcm958300k_defconfig +++ b/configs/bcm958300k_defconfig @@ -18,4 +18,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig index 83afce41d6..b124206361 100644 --- a/configs/bcm958305k_defconfig +++ b/configs/bcm958305k_defconfig @@ -18,4 +18,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_OF_LIBFDT=y diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig index a639336d94..c2713c61fa 100644 --- a/configs/bcm958622hr_defconfig +++ b/configs/bcm958622hr_defconfig @@ -13,7 +13,10 @@ CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_HASH=y CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y +CONFIG_SHA1=y +CONFIG_SHA256=y CONFIG_OF_LIBFDT=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 0365246ee5..76359c9d2f 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index 17c6008669..7811273e92 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -26,6 +26,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index 225271cd96..1765ec4fa9 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -26,6 +26,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index c15070e804..c5b1e9c062 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index 5664421c12..a963802b56 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -15,8 +15,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y -# CONFIG_MMC is not set -CONFIG_GENERIC_MMC=y +CONFIG_MMC=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 7d92c13940..1bdbf90495 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -57,4 +57,5 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_STORAGE=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_LCD=y +CONFIG_OMAP_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 9abe61760e..ed7432d7f4 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -57,4 +57,5 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_STORAGE=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_LCD=y +CONFIG_OMAP_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 79bb9057bf..02b5ff60e2 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -65,4 +65,5 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_STORAGE=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_LCD=y +CONFIG_OMAP_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig index e2e7ce0e62..69cf9e09b2 100644 --- a/configs/bubinga_defconfig +++ b/configs/bubinga_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig index 92985ab3d6..d8a419cda2 100644 --- a/configs/cam5200_defconfig +++ b/configs/cam5200_defconfig @@ -7,14 +7,13 @@ CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig index 32bc58ee9b..d7577a44ff 100644 --- a/configs/cam5200_niosflash_defconfig +++ b/configs/cam5200_niosflash_defconfig @@ -7,14 +7,13 @@ CONFIG_BOOTDELAY=5 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig index 1f6f18d601..87eb205d0c 100644 --- a/configs/canmb_defconfig +++ b/configs/canmb_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_CANMB=y CONFIG_BOOTDELAY=5 CONFIG_CMD_ASKENV=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index e76736afc4..2b59fd329b 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index 77dac784e3..76e861a3a2 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -37,4 +37,5 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index dd6fd498b7..c1b4486d87 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/charon_defconfig b/configs/charon_defconfig index ec22a6368f..2e4ad658e0 100644 --- a/configs/charon_defconfig +++ b/configs/charon_defconfig @@ -9,7 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -20,6 +20,7 @@ CONFIG_CMD_BMP=y CONFIG_CMD_BSP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig index ed419a34d1..ef76033779 100644 --- a/configs/cl-som-am57x_defconfig +++ b/configs/cl-som-am57x_defconfig @@ -9,6 +9,9 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig index 7d8d01aaaa..860d23e553 100644 --- a/configs/cm5200_defconfig +++ b/configs/cm5200_defconfig @@ -6,7 +6,6 @@ CONFIG_BOOTDELAY=5 CONFIG_SILENT_CONSOLE=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -16,6 +15,7 @@ CONFIG_CMD_SNTP=y CONFIG_CMD_BSP=y CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 33b53160a7..fb2f9fa5d3 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -23,6 +23,9 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set @@ -52,7 +55,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 4d0d03e68b..dbb1c3b886 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -23,6 +23,9 @@ CONFIG_SYS_PROMPT="CM-T335 # " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_PART=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig index c1cb2c0421..9b8159669a 100644 --- a/configs/cm_t3517_defconfig +++ b/configs/cm_t3517_defconfig @@ -10,6 +10,9 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T3517 # " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3" # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig index b9a79408a2..29405f8a1b 100644 --- a/configs/cm_t35_defconfig +++ b/configs/cm_t35_defconfig @@ -12,6 +12,9 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CM-T3x # " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3" # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y @@ -35,6 +38,7 @@ CONFIG_LED_STATUS_BOOT=0 CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y CONFIG_OF_LIBFDT=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 6ef980ab69..bec96aec98 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -26,6 +26,9 @@ CONFIG_SYS_PROMPT="CM-T43 # " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index d7fd995f7a..eef2f89dc3 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_OMAP54XX=y CONFIG_TARGET_CM_T54=y +CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296 # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 @@ -15,6 +16,9 @@ CONFIG_SYS_PROMPT="CM-T54 # " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3" # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_PART=y @@ -37,5 +41,6 @@ CONFIG_EFI_PARTITION=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 6ab2b9d6ef..6c105767fc 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -7,6 +7,7 @@ CONFIG_TARGET_COLIBRI_IMX6=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set @@ -40,7 +41,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig index 93897fff96..bd2ac24d4a 100644 --- a/configs/colibri_imx6_nospl_defconfig +++ b/configs/colibri_imx6_nospl_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_TARGET_COLIBRI_IMX6=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set @@ -33,7 +34,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 5f6114ed6d..db0224b929 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -41,6 +41,7 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 0071a923e4..41cc0ed340 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -32,6 +32,7 @@ CONFIG_DFU_RAM=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 78c478f420..cc9c4eee61 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -46,6 +47,7 @@ CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig index 6c46ac8bf7..cff3f45f38 100644 --- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_TPM=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig index 0c1181f67d..f155089349 100644 --- a/configs/controlcenterd_36BIT_SDCARD_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y @@ -24,6 +25,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_TPM=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig index bc2e7b4331..614cdb6201 100644 --- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01" CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_CONTROLCENTERD=y CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP" CONFIG_BOOTDELAY=-2 @@ -9,13 +10,17 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_HASH is not set CONFIG_CMD_TPM=y +# CONFIG_CMD_IRQ is not set CONFIG_DOS_PARTITION=y CONFIG_DM=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_TPM_AUTH_SESSIONS=y CONFIG_TPM=y +CONFIG_SHA1=y diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig index 7ec77a1102..da657f142f 100644 --- a/configs/controlcenterd_TRAILBLAZER_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01" CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_CONTROLCENTERD=y CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH" CONFIG_BOOTDELAY=-2 @@ -9,13 +10,17 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_HASH is not set CONFIG_CMD_TPM=y +# CONFIG_CMD_IRQ is not set CONFIG_DOS_PARTITION=y CONFIG_DM=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_TPM_AUTH_SESSIONS=y CONFIG_TPM=y +CONFIG_SHA1=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index e1c4f0c999..037f338993 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 90cf139a79..8b51073030 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_PART=y CONFIG_CMD_SF=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index ec6d1a445d..36e6608c43 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -34,6 +34,7 @@ CONFIG_OF_EMBED=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 54ace36a99..a0b5c752cc 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -9,6 +9,8 @@ CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="d2v2> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y @@ -27,5 +29,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index d87310130c..bb92c438fb 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index f50a949972..1120182052 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_BOOTZ=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 8aae0e15dc..739cfa96cf 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig index 703f1a5c72..bb65369aaa 100644 --- a/configs/dbau1000_defconfig +++ b/configs/dbau1000_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig index 3fb0967e67..98b0d40c7b 100644 --- a/configs/dbau1100_defconfig +++ b/configs/dbau1100_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig index ad095cfdbe..cdf5477407 100644 --- a/configs/dbau1500_defconfig +++ b/configs/dbau1500_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # " # CONFIG_CMD_ELF is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_SAVEENV is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig index 1c16ed2a4b..b75807d113 100644 --- a/configs/devconcenter_defconfig +++ b/configs/devconcenter_defconfig @@ -14,6 +14,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 074be13c04..06874c9da0 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -9,6 +9,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y @@ -21,6 +22,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_DM_GPIO=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 7edcb08324..617228f91f 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_MMC_OMAP_HS=y diff --git a/configs/digsy_mtc_RAMBOOT_defconfig b/configs/digsy_mtc_RAMBOOT_defconfig index 0d11eec75a..cda75d6e03 100644 --- a/configs/digsy_mtc_RAMBOOT_defconfig +++ b/configs/digsy_mtc_RAMBOOT_defconfig @@ -13,7 +13,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -21,7 +21,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_DIAG=y diff --git a/configs/digsy_mtc_defconfig b/configs/digsy_mtc_defconfig index dc17ab4406..da9cec81a3 100644 --- a/configs/digsy_mtc_defconfig +++ b/configs/digsy_mtc_defconfig @@ -11,7 +11,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR=" " CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -19,7 +19,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_DIAG=y diff --git a/configs/digsy_mtc_rev5_RAMBOOT_defconfig b/configs/digsy_mtc_rev5_RAMBOOT_defconfig index 4ab11c755b..1bba630083 100644 --- a/configs/digsy_mtc_rev5_RAMBOOT_defconfig +++ b/configs/digsy_mtc_rev5_RAMBOOT_defconfig @@ -13,7 +13,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -21,7 +21,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_DIAG=y diff --git a/configs/digsy_mtc_rev5_defconfig b/configs/digsy_mtc_rev5_defconfig index 1f3f3c8bb6..3491fdd5f1 100644 --- a/configs/digsy_mtc_rev5_defconfig +++ b/configs/digsy_mtc_rev5_defconfig @@ -13,7 +13,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -21,7 +21,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_DIAG=y diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig index c3574e1996..f92bf1e727 100644 --- a/configs/dlvision-10g_defconfig +++ b/configs/dlvision-10g_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING=" dlvision-10g 0.06" CONFIG_4xx=y CONFIG_TARGET_DLVISION_10G=y CONFIG_FIT=y +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 @@ -21,6 +22,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig index f9f07ee8f1..32d8708ea4 100644 --- a/configs/dlvision_defconfig +++ b/configs/dlvision_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING=" dlvision 0.02" CONFIG_4xx=y CONFIG_TARGET_DLVISION=y CONFIG_FIT=y +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 @@ -18,6 +19,7 @@ CONFIG_LOOPW=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index a363292350..abe6a6379f 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -7,6 +7,7 @@ CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -16,10 +17,12 @@ CONFIG_CMD_PING=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index e1ce9a5089..a70458872d 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -14,10 +14,12 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 2ecdd3c8f6..0e50b3109e 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -65,3 +65,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 +CONFIG_OMAP_WATCHDOG=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index c8b8ce3dd0..8f3ffcf5ba 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -6,6 +6,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_USB=y @@ -23,5 +24,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 16f0585657..46ac56797f 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_DS109=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y @@ -18,3 +19,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index c956ce04ef..4e17bb91a3 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_SPL_OF_TRANSLATE=y @@ -40,4 +41,5 @@ CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig index 840b3f2057..9e0ac20985 100644 --- a/configs/duovero_defconfig +++ b/configs/duovero_defconfig @@ -26,5 +26,6 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index c5563a4461..7c51cc485c 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index 2f3d814163..d567b899ca 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ECO5-PK # " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y @@ -24,5 +25,7 @@ CONFIG_CMD_UBI=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_OMAP is not set CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig index e7b4810b5a..bb67881a25 100644 --- a/configs/edb9315a_defconfig +++ b/configs/edb9315a_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y # CONFIG_DOS_PARTITION is not set CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index cc83b68d04..d67b548977 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -9,9 +9,11 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="EDMiniV2> " +CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -21,4 +23,5 @@ CONFIG_ISO_PARTITION=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 7e0b1923b8..b6911fd717 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -65,3 +65,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 +CONFIG_OMAP_WATCHDOG=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index d5e08889d0..197052dba6 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig index b4f334a436..24470f311a 100644 --- a/configs/fo300_defconfig +++ b/configs/fo300_defconfig @@ -12,7 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -21,9 +21,9 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_BSP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig index b47bfb5c24..6886298ff6 100644 --- a/configs/glacier_defconfig +++ b/configs/glacier_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig index 7e6957053d..ccb77bc2fd 100644 --- a/configs/glacier_ramboot_defconfig +++ b/configs/glacier_ramboot_defconfig @@ -13,6 +13,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index dbd81331a8..4dfb895351 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -7,6 +7,7 @@ CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="GoFlexHome> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -17,10 +18,12 @@ CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 761d75896d..5627a18631 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index 97bb976803..75e980979c 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -6,7 +6,6 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set @@ -19,5 +18,6 @@ CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/grasshopper_defconfig b/configs/grasshopper_defconfig index 2944d73af5..024231dbc6 100644 --- a/configs/grasshopper_defconfig +++ b/configs/grasshopper_defconfig @@ -14,4 +14,5 @@ CONFIG_CMD_ASKENV=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index 7d91fad27e..2c6f52494a 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index c09d3a61e1..570819d3e5 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_USB=y @@ -18,10 +19,13 @@ CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_LZMA=y CONFIG_OF_LIBFDT=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index dfabb6bb39..0d0d1421c8 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -4,12 +4,15 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_GW_VENTANA=y +CONFIG_CMD_EECONFIG=y +CONFIG_CMD_GSC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_VIDEO=y CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_CMD_HDMIDETECT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -19,6 +22,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index f95aa44390..8f6618901d 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -4,12 +4,15 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_GW_VENTANA=y +CONFIG_CMD_EECONFIG=y +CONFIG_CMD_GSC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_VIDEO=y CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_CMD_HDMIDETECT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -19,6 +22,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 169570d8fd..5545171bb3 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -4,6 +4,8 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_GW_VENTANA=y +CONFIG_CMD_EECONFIG=y +CONFIG_CMD_GSC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y @@ -11,6 +13,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_VIDEO=y CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_CMD_HDMIDETECT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -20,6 +23,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig index b85ed59806..9d3698c555 100644 --- a/configs/h2200_defconfig +++ b/configs/h2200_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_H2200=y CONFIG_FIT=y +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig index 9ff43da384..6833e477d2 100644 --- a/configs/haleakala_defconfig +++ b/configs/haleakala_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 6163353621..e9b8ac26a6 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -34,6 +34,7 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index afb0154fcd..aea06769f4 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" hrcon 0.01" CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -15,6 +16,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FPGAD=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index ce8b7972a4..8e911d49a0 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" hrcon dh 0.01" CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -14,6 +15,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FPGAD=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 2e08690981..cc9011d05c 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -8,6 +8,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_USB=y @@ -17,10 +18,13 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_LZMA=y CONFIG_OF_LIBFDT=y diff --git a/configs/icon_defconfig b/configs/icon_defconfig index b47b15d8d6..0a28a95e75 100644 --- a/configs/icon_defconfig +++ b/configs/icon_defconfig @@ -13,6 +13,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 409c836fd6..3e48380bc7 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -13,10 +13,13 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_LZMA=y CONFIG_OF_LIBFDT=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 165e2eb495..2a8c239d69 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -13,6 +13,7 @@ CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n" CONFIG_AUTOBOOT_DELAY_STR="ids" +CONFIG_CMD_ENV_FLAGS=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set @@ -21,6 +22,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig index ed3e7c56d6..224bedb1d6 100644 --- a/configs/imx31_phycore_defconfig +++ b/configs/imx31_phycore_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_IMX31_PHYCORE=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="uboot> " +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig index 7de703e4c1..c881b8fdcc 100644 --- a/configs/imx31_phycore_eet_defconfig +++ b/configs/imx31_phycore_eet_defconfig @@ -4,6 +4,7 @@ CONFIG_VIDEO=y CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/imx6dl_icore_mmc_defconfig b/configs/imx6dl_icore_mmc_defconfig deleted file mode 100644 index 6b67156ca5..0000000000 --- a/configs/imx6dl_icore_mmc_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MX6Q_ICORE=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set -CONFIG_VIDEO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" -CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" -CONFIG_SPL=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="icorem6qdl> " -# CONFIG_CMD_IMLS is not set -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -# CONFIG_BLK is not set -CONFIG_SYS_I2C_MXC=y -# CONFIG_DM_MMC_OPS is not set -CONFIG_FEC_MXC=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_MXC_UART=y -CONFIG_IMX_THERMAL=y -CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig deleted file mode 100644 index 2099370aa3..0000000000 --- a/configs/imx6dl_icore_nand_defconfig +++ /dev/null @@ -1,45 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MX6Q_ICORE=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set -CONFIG_VIDEO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" -CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb" -CONFIG_SPL=y -CONFIG_SPL_DMA_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="icorem6qdl> " -# CONFIG_CMD_IMLS is not set -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_I2C=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_UBI=y -# CONFIG_BLK is not set -CONFIG_SYS_I2C_MXC=y -# CONFIG_DM_MMC_OPS is not set -CONFIG_NAND_MXS=y -CONFIG_FEC_MXC=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_MXC_UART=y -CONFIG_IMX_THERMAL=y -CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6dl_icore_rqs_mmc_defconfig b/configs/imx6dl_icore_rqs_mmc_defconfig deleted file mode 100644 index 1a7d8efced..0000000000 --- a/configs/imx6dl_icore_rqs_mmc_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MX6Q_ICORE_RQS=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore-rqs" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" -CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6dl-icore-rqs.dtb" -CONFIG_SPL=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="icorem6qdl-rqs> " -# CONFIG_CMD_IMLS is not set -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -# CONFIG_BLK is not set -CONFIG_SYS_I2C_MXC=y -# CONFIG_DM_MMC_OPS is not set -CONFIG_FEC_MXC=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_MXC_UART=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig deleted file mode 100644 index 45d5fcec58..0000000000 --- a/configs/imx6q_icore_nand_defconfig +++ /dev/null @@ -1,45 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MX6Q_ICORE=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set -CONFIG_VIDEO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" -CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y -CONFIG_FIT_VERBOSE=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" -CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb" -CONFIG_SPL=y -CONFIG_SPL_DMA_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="icorem6qdl> " -# CONFIG_CMD_IMLS is not set -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_I2C=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_UBI=y -# CONFIG_BLK is not set -CONFIG_SYS_I2C_MXC=y -# CONFIG_DM_MMC_OPS is not set -CONFIG_NAND_MXS=y -CONFIG_FEC_MXC=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_MXC_UART=y -CONFIG_IMX_THERMAL=y -CONFIG_VIDEO_IPUV3=y diff --git a/configs/imx6q_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index adb0472811..b6b1b4bc04 100644 --- a/configs/imx6q_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -10,12 +10,12 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore" +CONFIG_OF_LIST="imx6q-icore imx6dl-icore" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6q-icore.dtb" CONFIG_SPL=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6qdl_icore_rqs_mmc_defconfig index aef6d364ac..08e6784b4c 100644 --- a/configs/imx6q_icore_rqs_mmc_defconfig +++ b/configs/imx6qdl_icore_rqs_mmc_defconfig @@ -9,12 +9,12 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" +CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb" CONFIG_SPL=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 35610c6f82..8751a36e27 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -14,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb" CONFIG_SPL=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index 7010d3d1e3..704c0c0374 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -13,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb" CONFIG_SPL=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 58c56f51ee..1f501cb021 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -14,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb" CONFIG_SPL=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6ul_isiot_mmc_defconfig b/configs/imx6ul_isiot_mmc_defconfig index 89bd8a04a8..5214479dcc 100644 --- a/configs/imx6ul_isiot_mmc_defconfig +++ b/configs/imx6ul_isiot_mmc_defconfig @@ -14,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb" CONFIG_SPL=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index f7240cc953..1b28336f36 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -13,7 +13,6 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND" CONFIG_BOOTDELAY=3 -CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-nand.dtb" CONFIG_SPL=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 0f115066db..8daf4332ca 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -9,6 +9,8 @@ CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y @@ -27,5 +29,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/inka4x0_defconfig b/configs/inka4x0_defconfig index 174719c367..c263cf61c5 100644 --- a/configs/inka4x0_defconfig +++ b/configs/inka4x0_defconfig @@ -3,12 +3,12 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_INKA4X0=y CONFIG_BOOTDELAY=1 CONFIG_LOOPW=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y diff --git a/configs/intip_defconfig b/configs/intip_defconfig index da4f3f4730..d6c85c8de1 100644 --- a/configs/intip_defconfig +++ b/configs/intip_defconfig @@ -16,6 +16,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/io64_defconfig b/configs/io64_defconfig index 9026ac8702..c586f00bf9 100644 --- a/configs/io64_defconfig +++ b/configs/io64_defconfig @@ -17,6 +17,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/io_defconfig b/configs/io_defconfig index 5dca2b121c..d1b5a03180 100644 --- a/configs/io_defconfig +++ b/configs/io_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING=" io 0.06" CONFIG_4xx=y CONFIG_TARGET_IO=y CONFIG_FIT=y +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 @@ -20,6 +21,7 @@ CONFIG_LOOPW=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig index c74df944a6..c34d98b930 100644 --- a/configs/iocon_defconfig +++ b/configs/iocon_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING=" iocon 0.06" CONFIG_4xx=y CONFIG_TARGET_IOCON=y CONFIG_FIT=y +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -16,12 +17,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_LOOPW=y +CONFIG_CMD_FPGAD=y CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DIAG=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig index 72ceb5ea43..705236eb7b 100644 --- a/configs/ipam390_defconfig +++ b/configs/ipam390_defconfig @@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig index cac9326b6c..f86170d346 100644 --- a/configs/ipek01_defconfig +++ b/configs/ipek01_defconfig @@ -7,14 +7,14 @@ CONFIG_BOOTDELAY=5 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_LOOPW=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +CONFIG_CMD_IRQ=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 2c3f1748d8..982aec48e7 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig index 406bdcd696..43b0c418a4 100644 --- a/configs/katmai_defconfig +++ b/configs/katmai_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_KATMAI=y CONFIG_CMD_CHIP_CONFIG=y +CONFIG_CMD_ECCTEST=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -10,6 +11,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig index 0ed41c388e..5eaa7e3c86 100644 --- a/configs/kilauea_defconfig +++ b/configs/kilauea_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index 49080a8abc..df7dac8c37 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index 678558e549..4b9cdb7f47 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index 2c5ed605b7..79952774ae 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index e9f4414dfc..c923aa62ab 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_KMP204X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,12 +16,16 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_JFFS2=y +# CONFIG_CMD_IRQ is not set CONFIG_CMD_UBI=y CONFIG_DOS_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 3a351ef78b..0a22f8d204 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_KM8360=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 9f5f6674d9..af0df7ef22 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 01d940a388..6cbecf600f 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_KM8360=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig index a8bd490509..e4ff6d791b 100644 --- a/configs/kmlion1_defconfig +++ b/configs/kmlion1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_KMP204X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,12 +16,16 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_JFFS2=y +# CONFIG_CMD_IRQ is not set CONFIG_CMD_UBI=y CONFIG_DOS_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index 0b4f10a257..eb70cd600a 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index f14e37a27a..6874e02315 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig index a35aee97d1..ed90f9d5b6 100644 --- a/configs/kmsugp1_defconfig +++ b/configs/kmsugp1_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index ce4b97e545..ecd297d8c6 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig index bb932c0037..c5edce8e4f 100644 --- a/configs/kmsuv31_defconfig +++ b/configs/kmsuv31_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 746af8c724..9e20c026fa 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 0f5fca78d7..2c6e00e296 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 83650558b9..a0a723861f 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index e6b1684408..465a6be8e7 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index a123b37546..c2f216bd51 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index f09647132d..e550cf250a 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -27,4 +27,5 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_USB=y CONFIG_OF_LIBFDT=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index a6995abc60..2124273e1c 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index a680706fa2..617c522851 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -9,6 +9,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index fd889580a4..0106e9ad0d 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 26c9210545..99df6e0818 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 447808040c..f08e7bfa87 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index a5ebe0e4a5..70839e6f01 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -9,6 +9,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index efdb0f105d..ed79c97121 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index f642fc7206..5ce37fdfb4 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 8804149fc3..1d55003d67 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -30,5 +31,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 918d2e973f..75fe55d819 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -21,5 +22,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/luan_defconfig b/configs/luan_defconfig index 1ee1e6f135..16b3a9c005 100644 --- a/configs/luan_defconfig +++ b/configs/luan_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig index 429a81f6b7..09365d4c9c 100644 --- a/configs/lwmon5_defconfig +++ b/configs/lwmon5_defconfig @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y @@ -31,6 +32,7 @@ CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_CONSOLE_EXTRA_INFO=y CONFIG_OF_LIBFDT=y diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig index 6acbd77d5f..fbd106ef92 100644 --- a/configs/m28evk_defconfig +++ b/configs/m28evk_defconfig @@ -22,7 +22,6 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y -CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_GPIO=y CONFIG_CMD_DHCP=y @@ -40,5 +39,6 @@ CONFIG_MMC_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig index b0379b8e63..a7bf29731e 100644 --- a/configs/m53evk_defconfig +++ b/configs/m53evk_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig index adeab1a0e9..a267c9a55f 100644 --- a/configs/ma5d4evk_defconfig +++ b/configs/ma5d4evk_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPI_FLASH=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig index 47198fc56a..b462ee9c93 100644 --- a/configs/makalu_defconfig +++ b/configs/makalu_defconfig @@ -10,6 +10,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index a7f14bde19..a342bec808 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -6,6 +6,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="malta # " # CONFIG_AUTOBOOT is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 9b04e0be31..ac560460eb 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -7,6 +7,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="maltael # " # CONFIG_AUTOBOOT is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 237b3ab333..e4e21d0f0f 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -5,6 +5,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="malta # " # CONFIG_AUTOBOOT is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index fe5e00c259..0b9f665f10 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -6,6 +6,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="maltael # " # CONFIG_AUTOBOOT is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 77a4035384..acc43ad94a 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL" CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -32,4 +33,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_THERMAL=y +CONFIG_USB=y CONFIG_OF_LIBFDT=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 332eddfa38..61c436e22c 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL" CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -33,4 +34,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_DM_THERMAL=y +CONFIG_USB=y CONFIG_OF_LIBFDT=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index 3cc1a2ba14..09dbc781c6 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -29,10 +29,12 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT_OMAP=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig index ebf5415464..3937fe8b44 100644 --- a/configs/mecp5123_defconfig +++ b/configs/mecp5123_defconfig @@ -6,13 +6,12 @@ CONFIG_BOOTDELAY=5 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index a811506f29..e30ac758dd 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -32,6 +32,7 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y diff --git a/configs/mgcoge3ne_defconfig b/configs/mgcoge3ne_defconfig index 22c8b31810..58d6656df3 100644 --- a/configs/mgcoge3ne_defconfig +++ b/configs/mgcoge3ne_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC8260=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_KM82XX=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig index 341c56c755..2add8828b8 100644 --- a/configs/mgcoge3un_defconfig +++ b/configs/mgcoge3un_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/mgcoge_defconfig b/configs/mgcoge_defconfig index 875c17e61b..c4f39b38c7 100644 --- a/configs/mgcoge_defconfig +++ b/configs/mgcoge_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC8260=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_KM82XX=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 131d6f5862..4a137007bf 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=-1 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_OS_BOOT=y @@ -27,6 +28,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 8dac1d72fb..aa50e88422 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -10,6 +10,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_HAVE_ACPI_RESUME=y CONFIG_SEABIOS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/motionpro_defconfig b/configs/motionpro_defconfig index 91384a6259..c4006bca5f 100644 --- a/configs/motionpro_defconfig +++ b/configs/motionpro_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_MOTIONPRO=y CONFIG_OF_BOARD_SETUP=y CONFIG_VERSION_VARIABLE=y @@ -8,13 +9,13 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" CONFIG_CMD_ASKENV=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_BEDBUG=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig index c0af8127b5..5bb78076ad 100644 --- a/configs/mpc5121ads_defconfig +++ b/configs/mpc5121ads_defconfig @@ -6,19 +6,20 @@ CONFIG_BOOTDELAY=5 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig index ad46e02e94..e28fa19227 100644 --- a/configs/mpc5121ads_rev2_defconfig +++ b/configs/mpc5121ads_rev2_defconfig @@ -7,20 +7,21 @@ CONFIG_BOOTDELAY=5 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/ms7720se_defconfig b/configs/ms7720se_defconfig index b31962a8f8..30e52692d0 100644 --- a/configs/ms7720se_defconfig +++ b/configs/ms7720se_defconfig @@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/ms7722se_defconfig b/configs/ms7722se_defconfig index cb50b46148..92f3158dae 100644 --- a/configs/ms7722se_defconfig +++ b/configs/ms7722se_defconfig @@ -20,5 +20,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set +CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index 08e400cc4e..c4a6f2063f 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -12,10 +12,12 @@ CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="mt_ventoux => " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y +CONFIG_CMD_FPGA_LOADMK=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -29,6 +31,7 @@ CONFIG_CMD_UBI=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT_OMAP=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y diff --git a/configs/munices_defconfig b/configs/munices_defconfig index ddd5c43de2..0e2b188a51 100644 --- a/configs/munices_defconfig +++ b/configs/munices_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC5xxx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_MUNICES=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index feaa0876ef..795de14740 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -30,5 +30,6 @@ CONFIG_LED_STATUS_BOOT=0 CONFIG_LED_STATUS_CMD=y CONFIG_MMC_MXS=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index 2e71dd9742..7eb1791d6c 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -28,5 +28,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MMC_MXS=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index d7a1d684c8..710ae4711d 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -37,5 +37,6 @@ CONFIG_MMC_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index c5fe5595bc..95ac31adaf 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -38,5 +38,6 @@ CONFIG_MMC_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index f878bafa00..3b955401ca 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -37,5 +37,6 @@ CONFIG_MMC_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index 5203349c7a..1b5de66553 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -37,5 +37,6 @@ CONFIG_MMC_MXS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig index 655a1a5224..0da348adff 100644 --- a/configs/mx35pdk_defconfig +++ b/configs/mx35pdk_defconfig @@ -21,5 +21,6 @@ CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index d7e5404048..3f57c88a88 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_FUSE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index c34beb74e2..b180f54075 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_CMD_HDMIDETECT=y CONFIG_VIDEO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig deleted file mode 100644 index 0254a53bf9..0000000000 --- a/configs/mx6dlsabresd_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_TARGET_MX6SABRESD=y -CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -CONFIG_CMD_DFU=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_DFU_MMC=y -CONFIG_DFU_SF=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PCI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_G_DNL_MANUFACTURER="FSL" -CONFIG_G_DNL_VENDOR_NUM=0x0525 -CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index c4301e1f0a..a54279978f 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig deleted file mode 100644 index cef7f1a5b3..0000000000 --- a/configs/mx6qsabresd_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_TARGET_MX6SABRESD=y -CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -CONFIG_CMD_DFU=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_DFU_MMC=y -CONFIG_DFU_SF=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PCI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_G_DNL_MANUFACTURER="FSL" -CONFIG_G_DNL_VENDOR_NUM=0x0525 -CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_OF_LIBFDT=y diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig index 7a46a448b5..0e0edefab7 100644 --- a/configs/mx6sabresd_spl_defconfig +++ b/configs/mx6sabresd_spl_defconfig @@ -9,7 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6QDL" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index a87dec8e3a..949ce91804 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -39,5 +39,4 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 41ecf92322..60a4431083 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -40,5 +40,4 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 0701e1d324..52faae43e4 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -6,6 +6,7 @@ CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y # CONFIG_CMD_BMODE is not set CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -30,13 +31,35 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_STORAGE=y @@ -46,4 +69,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 -CONFIG_OF_LIBFDT=y +CONFIG_ERRNO_STR=y diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig index 2e8b5bedd3..c678e7558a 100644 --- a/configs/mx7dsabresd_secure_defconfig +++ b/configs/mx7dsabresd_secure_defconfig @@ -1,11 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_TARGET_MX7DSABRESD=y +CONFIG_VIDEO=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y # CONFIG_CMD_BMODE is not set -CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -31,15 +33,35 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_STORAGE=y @@ -49,4 +71,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 -CONFIG_OF_LIBFDT=y +CONFIG_ERRNO_STR=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 7a02538301..a57cc9724c 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nas220> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -17,6 +18,7 @@ CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y @@ -24,5 +26,6 @@ CONFIG_EFI_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/neo_defconfig b/configs/neo_defconfig index fbb2da47f0..6ca5b4ee65 100644 --- a/configs/neo_defconfig +++ b/configs/neo_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING=" neo 0.02" CONFIG_4xx=y CONFIG_TARGET_NEO=y CONFIG_FIT=y +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 @@ -18,6 +19,7 @@ CONFIG_LOOPW=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 5e41e02a02..ab8eb958ca 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -9,6 +9,8 @@ CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="2big2> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y @@ -27,5 +29,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 2d04fb5979..66db6447ac 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -9,6 +9,8 @@ CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y @@ -27,5 +29,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 6c730fc7d8..04abc9405b 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -9,6 +9,8 @@ CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y @@ -27,5 +29,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 0a00e0529a..5f79e6f0e2 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -9,6 +9,8 @@ CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 4b3c851842..a81ad0b1e8 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -9,6 +9,8 @@ CONFIG_CONSOLE_MUX=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y @@ -27,5 +29,6 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 9b16bf48b0..5744ede776 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 83bbf8e02f..dca89ec34e 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 69cf637eea..a19d093710 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 2e9ee2e293..edf4b6377a 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index f3dd324dce..0f7532062a 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 5a825d6e22..45a5acb96c 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index a970eb5961..49b963c64f 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_FAT_SUPPORT=y +CONFIG_CMD_HDMIDETECT=y CONFIG_VIDEO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -21,6 +22,7 @@ CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 4a0f9455cb..ae39818e4b 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -7,6 +7,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nsa310s => " CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_USB=y @@ -16,10 +17,13 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_LZMA=y CONFIG_OF_LIBFDT=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 42fe120786..c01d5f5285 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -52,6 +52,7 @@ CONFIG_TEGRA114_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index dab4cc1443..fed24ec90d 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -36,6 +36,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_PHY_SAMSUNG=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index a28058ad6a..f4e9e9af5b 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_MAX77686=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 46846b2ccc..64971c139c 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -34,6 +34,7 @@ CONFIG_LED_STATUS_CMD=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 1b61d1d8b9..227f1d1ca3 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig index 911021b747..6194a66ce7 100644 --- a/configs/omap3_ha_defconfig +++ b/configs/omap3_ha_defconfig @@ -24,5 +24,6 @@ CONFIG_CMD_FAT=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 561bdfbceb..aa7035821e 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -1,11 +1,11 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_LOGIC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit" -CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y @@ -16,29 +16,15 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="OMAP Logic # " -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set -CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y -CONFIG_CMD_SPI=y -CONFIG_CMD_I2C=y +# CONFIG_CMD_USB is not set # CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y -CONFIG_EFI_PARTITION=y CONFIG_OF_CONTROL=y # CONFIG_BLK is not set CONFIG_DM_I2C=y diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig index daea034ba9..3be4a1d0b3 100644 --- a/configs/omap3_overo_defconfig +++ b/configs/omap3_overo_defconfig @@ -42,5 +42,6 @@ CONFIG_EFI_PARTITION=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index af459fcfde..8fdf76076c 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -25,5 +25,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 865845ee9c..bd799b7dc3 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_OMAP54XX=y CONFIG_TARGET_OMAP5_UEVM=y +CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296 # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_ARMV7_LPAE=y CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -36,6 +37,7 @@ CONFIG_DFU_RAM=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GADGET=y CONFIG_USB_DWC3_OMAP=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 752ff5d860..ff5e06de29 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -13,10 +13,11 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5 CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_IMLS is not set +# CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 2abf3ab6a1..1471872833 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -16,9 +17,11 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 8b3f25fd95..b62852a10c 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -16,9 +17,11 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index ba774738fc..d57b6962d5 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -7,6 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -16,9 +17,11 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 4f8f659321..1a9d6cddc3 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -75,7 +75,6 @@ CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index 213f036266..d6271b8d55 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -7,6 +7,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 0ff4c13aa0..d78f4450e8 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 4dfb02db20..e409a3909b 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -38,6 +38,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index e49a42f45b..daf9165659 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -33,6 +33,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 0ad0974d34..9386df83a8 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -31,6 +31,7 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig index d19908ca8f..0ef8750d66 100644 --- a/configs/pcm030_LOWBOOT_defconfig +++ b/configs/pcm030_LOWBOOT_defconfig @@ -4,11 +4,10 @@ CONFIG_TARGET_PCM030=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000" CONFIG_BOOTDELAY=3 -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y -CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig index ef5c85888c..3869991f9e 100644 --- a/configs/pcm030_defconfig +++ b/configs/pcm030_defconfig @@ -4,11 +4,10 @@ CONFIG_TARGET_PCM030=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="uboot> " -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y -CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 4392c6e1d3..f278075b44 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -28,6 +28,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_PART=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 72a263187f..5fa60b7785 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -28,6 +28,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_PART=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index 1dbc0a8ce8..1e72e91ede 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index c8219b5543..c55537c032 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_HDMIDETECT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" CONFIG_BOOTDELAY=3 diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig index f45a90caf9..4ef0df1aa8 100644 --- a/configs/pdm360ng_defconfig +++ b/configs/pdm360ng_defconfig @@ -10,13 +10,11 @@ CONFIG_SILENT_CONSOLE=y # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y -CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 4c46f1ebdd..6d4d8ada49 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -29,6 +29,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_PART=y diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig index ab4415e522..f34dfe9fdb 100644 --- a/configs/picosam9g45_defconfig +++ b/configs/picosam9g45_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_LCD=y CONFIG_OF_LIBFDT=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 92bda60095..593e24a836 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" +CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_SPL=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index 0c6c65e9d8..f0fdde713a 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -27,4 +27,5 @@ CONFIG_SPL_DM=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 92441b3c23..7cf2722740 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index 7235922a94..954908e9aa 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 029ecc8dc8..57ebc0694c 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -14,10 +14,12 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 206ba472fa..a50d9ed99b 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig index 77aeb9239f..a0faba50ff 100644 --- a/configs/portl2_defconfig +++ b/configs/portl2_defconfig @@ -12,12 +12,14 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index c40684a81d..67bdfd63f2 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -72,3 +72,4 @@ CONFIG_G_DNL_PRODUCT_NUM=0x02d2 # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_SYS_CONSOLE_BG_COL=0xff CONFIG_SYS_CONSOLE_FG_COL=0x00 +CONFIG_OMAP_WATCHDOG=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 7f9ba871dc..f4640b906a 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_QEMU_PPCE500=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -15,6 +16,7 @@ CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 02e6af1342..36d0185268 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -32,6 +32,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 73ee7b69ba..b648326041 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -13,6 +13,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_PART=y CONFIG_CMD_SF=y diff --git a/configs/qemu-x86_efi_payload32_defconfig b/configs/qemu-x86_efi_payload32_defconfig index 4f6803d448..e092dbdef6 100644 --- a/configs/qemu-x86_efi_payload32_defconfig +++ b/configs/qemu-x86_efi_payload32_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_PART=y CONFIG_CMD_SF=y diff --git a/configs/qemu-x86_efi_payload64_defconfig b/configs/qemu-x86_efi_payload64_defconfig index b354ba1c7c..f8f6295617 100644 --- a/configs/qemu-x86_efi_payload64_defconfig +++ b/configs/qemu-x86_efi_payload64_defconfig @@ -11,6 +11,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_PART=y CONFIG_CMD_SF=y diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig index e748f02c1d..6835cf1c5c 100644 --- a/configs/qemu_mips64_defconfig +++ b/configs/qemu_mips64_defconfig @@ -4,6 +4,7 @@ CONFIG_CPU_MIPS64_R1=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mips64 # " +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set @@ -14,3 +15,4 @@ CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_LZMA=y diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig index b2d2a0bc76..60bd6164fc 100644 --- a/configs/qemu_mips64el_defconfig +++ b/configs/qemu_mips64el_defconfig @@ -5,6 +5,7 @@ CONFIG_CPU_MIPS64_R1=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mips64el # " +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set @@ -15,3 +16,4 @@ CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_LZMA=y diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig index 3ef02a40c9..c6f08b4efb 100644 --- a/configs/qemu_mips_defconfig +++ b/configs/qemu_mips_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_QEMU_MIPS=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mips # " +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set @@ -12,3 +13,4 @@ CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_LZMA=y diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig index 08415958e2..b8c206971d 100644 --- a/configs/qemu_mipsel_defconfig +++ b/configs/qemu_mipsel_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_LITTLE_ENDIAN=y CONFIG_BOOTDELAY=10 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="qemu-mipsel # " +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set @@ -13,3 +14,4 @@ CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y +CONFIG_LZMA=y diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig index c5c3d52718..91b08dc24f 100644 --- a/configs/r0p7734_defconfig +++ b/configs/r0p7734_defconfig @@ -13,7 +13,6 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_CMD_ENV_EXISTS is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set -CONFIG_CMD_I2C=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ECHO is not set # CONFIG_CMD_ITEST is not set diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index 3bd3d213bf..ba68b504d0 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -1,6 +1,7 @@ CONFIG_SH=y CONFIG_TARGET_R2DPLUS=y CONFIG_BOOTDELAY=-1 +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig index 999470c26c..2a37db824d 100644 --- a/configs/r7780mp_defconfig +++ b/configs/r7780mp_defconfig @@ -10,6 +10,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EDITENV is not set # CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FPGA is not set diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig new file mode 100644 index 0000000000..60e0b720bb --- /dev/null +++ b/configs/r8a7795_salvator-x_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_RCAR_GEN3=y +CONFIG_TARGET_SALVATOR_X=y +CONFIG_DEFAULT_FDT_FILE=r8a7795-salvator-x.dtb +CONFIG_VERSION_VARIABLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_FDT=y +CONFIG_R8A7795=y +CONFIG_SH_SDHI=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_NET=y +CONFIG_CMD_NFS=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_HOST=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_RCAR_GEN3=y +CONFIG_DOS_PARTITION=y +CONFIG_MMC=y +CONFIG_GENERIC_MMC=y +CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig new file mode 100644 index 0000000000..d6f1840eab --- /dev/null +++ b/configs/r8a7796_salvator-x_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_RCAR_GEN3=y +CONFIG_TARGET_SALVATOR_X=y +CONFIG_DEFAULT_FDT_FILE=r8a7796-salvator-x.dtb +CONFIG_VERSION_VARIABLE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_FDT=y +CONFIG_R8A7796=y +CONFIG_SH_SDHI=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_NET=y +CONFIG_CMD_NFS=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_HOST=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_RCAR_GEN3=y +CONFIG_DOS_PARTITION=y +CONFIG_MMC=y +CONFIG_GENERIC_MMC=y +CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y +CONFIG_RENESAS_RAVB=y diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig index be2beb72a9..7c62f6956c 100644 --- a/configs/rainier_defconfig +++ b/configs/rainier_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig index 0c0559a3af..621e414e7a 100644 --- a/configs/rainier_ramboot_defconfig +++ b/configs/rainier_ramboot_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 01848c5702..f77d4d4087 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -65,3 +65,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 +CONFIG_OMAP_WATCHDOG=y diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig index 425b2fe98c..78b004f462 100644 --- a/configs/redwood_defconfig +++ b/configs/redwood_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/salvator-x_defconfig b/configs/salvator-x_defconfig deleted file mode 100644 index b1500296da..0000000000 --- a/configs/salvator-x_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_RCAR_GEN3=y -CONFIG_TARGET_SALVATOR_X=y -CONFIG_VERSION_VARIABLE=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -CONFIG_DOS_PARTITION=y -# CONFIG_MMC is not set diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig index 9694632d2c..239bfdd66b 100644 --- a/configs/sama5d2_ptc_nandflash_defconfig +++ b/configs/sama5d2_ptc_nandflash_defconfig @@ -19,4 +19,5 @@ CONFIG_CMD_SF=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig index 30e8500edf..21014b937c 100644 --- a/configs/sama5d2_ptc_spiflash_defconfig +++ b/configs/sama5d2_ptc_spiflash_defconfig @@ -20,4 +20,5 @@ CONFIG_CMD_SF=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5417057664..f39d03e472 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -22,12 +22,15 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_ENV_CALLBACK=y +CONFIG_CMD_ENV_FLAGS=y CONFIG_CMD_MD5SUM=y CONFIG_LOOPW=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_DEMO=y +CONFIG_CMD_IDE=y CONFIG_CMD_GPT=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -42,6 +45,7 @@ CONFIG_CMD_CDP=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_ETHSW=y CONFIG_CMD_BMP=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index b30e16508f..519e91f623 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -22,12 +22,15 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_ENV_CALLBACK=y +CONFIG_CMD_ENV_FLAGS=y CONFIG_CMD_MD5SUM=y CONFIG_LOOPW=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_DEMO=y +CONFIG_CMD_IDE=y CONFIG_CMD_GPT=y CONFIG_CMD_PART=y CONFIG_CMD_SF=y @@ -105,7 +108,6 @@ CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y # CONFIG_MMC is not set -CONFIG_GENERIC_MMC=y CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 3061e5a9d9..761cfb6f7b 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -21,6 +21,7 @@ CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_SILENT_CONSOLE=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y @@ -29,12 +30,15 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_ENV_CALLBACK=y +CONFIG_CMD_ENV_FLAGS=y CONFIG_CMD_MD5SUM=y CONFIG_LOOPW=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_DEMO=y +CONFIG_CMD_IDE=y CONFIG_CMD_GPT=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index ff5a0823d4..80531fe6d4 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MMC_MXS=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_OF_LIBFDT=y diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig index 08679f03ee..6348f7d2e4 100644 --- a/configs/sbc8548_PCI_33_PCIE_defconfig +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -12,6 +13,8 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig index 650535ac25..acb3092b7c 100644 --- a/configs/sbc8548_PCI_33_defconfig +++ b/configs/sbc8548_PCI_33_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -12,6 +13,8 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig index cadb269cc2..195d472e67 100644 --- a/configs/sbc8548_PCI_66_PCIE_defconfig +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -12,6 +13,8 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig index c89a0a0b20..c107213d8c 100644 --- a/configs/sbc8548_PCI_66_defconfig +++ b/configs/sbc8548_PCI_66_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -12,6 +13,8 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig index 3ffbe5bd48..185825efc9 100644 --- a/configs/sbc8548_defconfig +++ b/configs/sbc8548_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,6 +12,8 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +# CONFIG_CMD_HASH is not set +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig index e2a8e3c762..827f4eeccb 100644 --- a/configs/sc_sps_1_defconfig +++ b/configs/sc_sps_1_defconfig @@ -24,5 +24,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MMC_MXS=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 9e50f702bf..00fc117f4a 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -31,6 +31,7 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig index b21e369473..a0163792e4 100644 --- a/configs/sequoia_defconfig +++ b/configs/sequoia_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig index ffdf6c4787..b6802f23f5 100644 --- a/configs/sequoia_ramboot_defconfig +++ b/configs/sequoia_ramboot_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/sh7763rdp_defconfig b/configs/sh7763rdp_defconfig index ec0275ee55..028616666c 100644 --- a/configs/sh7763rdp_defconfig +++ b/configs/sh7763rdp_defconfig @@ -21,5 +21,6 @@ CONFIG_VERSION_VARIABLE=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_MISC is not set +CONFIG_CMD_JFFS2=y CONFIG_MTD_NOR_FLASH=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index b3280557ca..ac7217dcba 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_IDE=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y @@ -19,9 +20,12 @@ CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_ISO_PARTITION=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_LZMA=y CONFIG_OF_LIBFDT=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 293b08eaba..d161c3bb88 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index ff52a3757a..c51df50678 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -48,6 +48,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_VIDEO_BRIDGE=y CONFIG_ERRNO_STR=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 0ea2393bf6..8050f24fbb 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -66,6 +66,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_VIDCONSOLE_AS_LCD=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig new file mode 100644 index 0000000000..46bda478d5 --- /dev/null +++ b/configs/socfpga_arria10_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_arria10" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" +CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" +CONFIG_SPL=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_DOS_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SYS_NS16550=y +CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index fb9bae404b..18186e83db 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -19,6 +19,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 9e00d65034..5def6d5991 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_VIDEO=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -19,11 +20,14 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +# CONFIG_USB_EHCI_HCD is not set CONFIG_USB_STORAGE=y CONFIG_CONSOLE_EXTRA_INFO=y CONFIG_OF_LIBFDT=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index d9fd8ca362..716f8c00e6 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -66,6 +66,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_VIDCONSOLE_AS_LCD=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index aaa85022ed..48989aaea6 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BAUDRATE=38400 CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 51a50856a9..d293d39d7b 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" strider con 0.01" CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -17,6 +18,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FPGAD=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 9524c9c6f2..e0040e9e38 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" strider con dp 0.01" CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -17,6 +18,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FPGAD=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 090d7e8efc..7d372ffac7 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" strider cpu 0.01" CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -17,6 +18,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FPGAD=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index ec715f1180..5d304b3f8b 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_IDENT_STRING=" strider cpu dp 0.01" CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -17,6 +18,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FPGAD=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index f476a23dd0..e5e100a950 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_SUVD3=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig index 5f56a516ff..d34634381e 100644 --- a/configs/sycamore_defconfig +++ b/configs/sycamore_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig index 21c4c89212..3b37eb9e5f 100644 --- a/configs/t3corp_defconfig +++ b/configs/t3corp_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_T3CORP=y CONFIG_CMD_CHIP_CONFIG=y +CONFIG_CMD_ECCTEST=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 @@ -12,6 +13,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig index 24244134c7..feb8fe690f 100644 --- a/configs/tao3530_defconfig +++ b/configs/tao3530_defconfig @@ -24,5 +24,6 @@ CONFIG_CMD_FAT=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index e4622830ca..da042ae03f 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_MX6=y CONFIG_TARGET_TBS2910=y CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_PRE_CON_BUF_ADDR=0x7c000000 diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index cd9b507803..91fd3d5f9f 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -33,4 +33,5 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 1dd8a1ec20..5c394b73f5 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -32,6 +32,7 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index dd61ead647..914f70fd6a 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -65,3 +65,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Siemens AG" CONFIG_G_DNL_VENDOR_NUM=0x0908 CONFIG_G_DNL_PRODUCT_NUM=0x02d2 +CONFIG_OMAP_WATCHDOG=y diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index 3c7e6ff4ba..65314df133 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -45,3 +45,4 @@ CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_LZMA=y diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index 6e4e6f7c44..cd31cf39aa 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 9cd54811e1..dee295ee35 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index 5b4c506557..6e8e84225e 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -10,6 +10,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index c842af7720..3ec25c8217 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -11,6 +11,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index cff6e1045e..eb609e12a4 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index 740d01f989..f824018849 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -12,6 +12,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index e24912e0c2..4dc6b9e291 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -16,6 +16,7 @@ CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068" CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig index 14a8eb4ea6..65b2b5a210 100644 --- a/configs/tricorder_defconfig +++ b/configs/tricorder_defconfig @@ -9,6 +9,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="OMAP3 Tricorder # " # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig index 290e97902c..a5d1bab015 100644 --- a/configs/tricorder_flash_defconfig +++ b/configs/tricorder_flash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 455f4b2819..e4074a0bd7 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -37,4 +37,5 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SFLASH=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index fa998f81b6..c3e5a9eace 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index a6093bc029..515656de1c 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC83xx=y +CONFIG_CMD_IMMAP=y CONFIG_TARGET_TUXX1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -11,10 +12,12 @@ CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/twister_defconfig b/configs/twister_defconfig index ba7b68b317..124506a448 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="twister => " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y @@ -26,6 +27,7 @@ CONFIG_CMD_UBI=y CONFIG_MMC_OMAP_HS=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT_OMAP=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 43256177be..a71a75751f 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -8,6 +8,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y +CONFIG_CMD_FUSE=y # CONFIG_CMD_SETEXPR is not set CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig index db4c47c3d2..c75e547b7f 100644 --- a/configs/v38b_defconfig +++ b/configs/v38b_defconfig @@ -3,15 +3,16 @@ CONFIG_MPC5xxx=y CONFIG_TARGET_V38B=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_CMD_I2C=y +CONFIG_CMD_IDE=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y +CONFIG_CMD_IRQ=y CONFIG_MAC_PARTITION=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig index 27b29fb94e..f8b9d7e61b 100644 --- a/configs/vct_platinum_defconfig +++ b/configs/vct_platinum_defconfig @@ -4,6 +4,7 @@ CONFIG_VCT_PLATINUM=y CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_PROMPT="$ " +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -14,4 +15,5 @@ CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig index 4896c6b459..5d4cccccba 100644 --- a/configs/vct_platinum_onenand_defconfig +++ b/configs/vct_platinum_onenand_defconfig @@ -6,6 +6,7 @@ CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_USB=y @@ -14,7 +15,9 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig index 0e4964b5b3..5a5edd8260 100644 --- a/configs/vct_platinum_onenand_small_defconfig +++ b/configs/vct_platinum_onenand_small_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_SYS_NS16550=y diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig index aff3d2be65..5efe2236a3 100644 --- a/configs/vct_platinumavc_defconfig +++ b/configs/vct_platinumavc_defconfig @@ -4,6 +4,7 @@ CONFIG_VCT_PLATINUMAVC=y CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_PROMPT="VCT# " +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig index d690e19a1d..1f0a3f8b49 100644 --- a/configs/vct_platinumavc_onenand_defconfig +++ b/configs/vct_platinumavc_onenand_defconfig @@ -6,12 +6,14 @@ CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_SYS_NS16550=y diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig index 5b443cfbb5..9e2fcbf6d0 100644 --- a/configs/vct_platinumavc_onenand_small_defconfig +++ b/configs/vct_platinumavc_onenand_small_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_SYS_NS16550=y diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig index d5927b383b..24f776b49f 100644 --- a/configs/vct_premium_defconfig +++ b/configs/vct_premium_defconfig @@ -4,6 +4,7 @@ CONFIG_VCT_PREMIUM=y CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_PROMPT="$ " +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -14,4 +15,5 @@ CONFIG_CMD_FAT=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig index e0c8a7176e..ac9cf36f68 100644 --- a/configs/vct_premium_onenand_defconfig +++ b/configs/vct_premium_onenand_defconfig @@ -6,6 +6,7 @@ CONFIG_BOOTDELAY=5 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_USB=y @@ -14,7 +15,9 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig index 8eca0a5597..6e649ec0d7 100644 --- a/configs/vct_premium_onenand_small_defconfig +++ b/configs/vct_premium_onenand_small_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_CMD_JFFS2=y CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set CONFIG_SYS_NS16550=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 1b0e646474..97960e720e 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 486861b461..8d3e54e8d7 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -30,6 +30,7 @@ CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index 9198f65eaa..47193094dd 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -10,6 +10,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index ba4e5965ca..f1dc19a543 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -10,6 +10,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y +CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index dc7f2c6697..c8da54d9b6 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_ATMEL_USBA=y diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig index 5f56a516ff..d34634381e 100644 --- a/configs/walnut_defconfig +++ b/configs/walnut_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index f4c9b6bc76..b4b3283829 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_VIDEO=y +CONFIG_CMD_HDMIDETECT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" # CONFIG_CONSOLE_MUX is not set diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig index 6c27b36235..3ebfb79895 100644 --- a/configs/whistler_defconfig +++ b/configs/whistler_defconfig @@ -27,4 +27,5 @@ CONFIG_SPL_DM=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig index fdc2b2aa22..22172c57b3 100644 --- a/configs/woodburn_sd_defconfig +++ b/configs/woodburn_sd_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 CONFIG_HUSH_PARSER=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index ebcae43e3f..06b31baeea 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -4,14 +4,17 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y +CONFIG_CMD_HD44760=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig index ad9100e0f5..2b81535c29 100644 --- a/configs/wtk_defconfig +++ b/configs/wtk_defconfig @@ -7,12 +7,14 @@ CONFIG_BOOTDELAY=5 # CONFIG_CONSOLE_MUX is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_IDE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_SNTP=y CONFIG_CMD_BMP=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y +CONFIG_CMD_JFFS2=y CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y # CONFIG_MMC is not set diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 01565ec33b..2e5d5f1ae8 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -20,6 +20,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y +CONFIG_CMD_FPGA_LOADMK=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -36,6 +37,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_OF_LIBFDT=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig index ce1ad56c0b..398d32f701 100644 --- a/configs/xfi3_defconfig +++ b/configs/xfi3_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MMC_MXS=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_OF_LIBFDT=y diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig index 6aa049c450..1f90e3db26 100644 --- a/configs/xilinx-ppc405-generic_defconfig +++ b/configs/xilinx-ppc405-generic_defconfig @@ -18,6 +18,7 @@ CONFIG_LOOPW=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_OF_EMBED=y # CONFIG_MMC is not set diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig index c9a1e2b087..f1f723490f 100644 --- a/configs/xilinx-ppc440-generic_defconfig +++ b/configs/xilinx-ppc440-generic_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_JFFS2=y CONFIG_CMD_DIAG=y CONFIG_OF_EMBED=y CONFIG_NETCONSOLE=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 0796e81b90..bfb5c04153 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 3711ac86db..4ba1ac6488 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_OS_BOOT=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig index 9dd082bfdd..b89e2471db 100644 --- a/configs/xpedite1000_defconfig +++ b/configs/xpedite1000_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -14,6 +15,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig index 909efb1c08..2788db0830 100644 --- a/configs/xpedite517x_defconfig +++ b/configs/xpedite517x_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -15,6 +16,9 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y +CONFIG_CMD_JFFS2=y +CONFIG_CMD_IRQ=y +CONFIG_DS4510=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig index e1fdfeb759..904f7b9bc5 100644 --- a/configs/xpedite520x_defconfig +++ b/configs/xpedite520x_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_XPEDITE520X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -8,6 +9,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -15,6 +17,9 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_JFFS2=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig index 41dee5d839..45fe128a55 100644 --- a/configs/xpedite537x_defconfig +++ b/configs/xpedite537x_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_XPEDITE537X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -8,6 +9,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y +CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -15,7 +17,11 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_JFFS2=y +# CONFIG_CMD_IRQ is not set CONFIG_SYS_FSL_DDR2=y +CONFIG_DS4510=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig index 785eeef875..cad0d239e9 100644 --- a/configs/xpedite550x_defconfig +++ b/configs/xpedite550x_defconfig @@ -1,5 +1,6 @@ CONFIG_PPC=y CONFIG_MPC85xx=y +# CONFIG_CMD_ERRATA is not set CONFIG_TARGET_XPEDITE550X=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -16,6 +17,9 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_DATE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_JFFS2=y +# CONFIG_CMD_IRQ is not set # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig index 1eb3eef3ad..d15ee20ba7 100644 --- a/configs/yellowstone_defconfig +++ b/configs/yellowstone_defconfig @@ -10,6 +10,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig index 237a7ca5a7..935854cb80 100644 --- a/configs/yosemite_defconfig +++ b/configs/yosemite_defconfig @@ -10,6 +10,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig index 10fbafcb4b..127f1e0da1 100644 --- a/configs/yucca_defconfig +++ b/configs/yucca_defconfig @@ -9,6 +9,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y CONFIG_LOOPW=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig index 06e915c1dc..0b38f2b1af 100644 --- a/configs/zipitz2_defconfig +++ b/configs/zipitz2_defconfig @@ -19,5 +19,6 @@ CONFIG_PXA_SERIAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y +CONFIG_LZMA=y CONFIG_OF_LIBFDT=y # CONFIG_EFI_LOADER is not set diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig index 54e8dde1cf..7a939036d9 100644 --- a/configs/zmx25_defconfig +++ b/configs/zmx25_defconfig @@ -18,4 +18,5 @@ CONFIG_CMD_FAT=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 4093618325..2d7fffc1f4 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -16,6 +16,10 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 3c3a5b29b0..7ca69a973c 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -12,6 +12,10 @@ CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index c59d7f5c54..44e6850d8b 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -12,12 +12,17 @@ CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index c73bacb18f..825346abd6 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -12,12 +12,17 @@ CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index ececcb4f95..a1ef49f250 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -15,6 +15,10 @@ CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 980382ce69..dc49372e48 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -14,6 +14,10 @@ CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 48caf31683..16cd613110 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -11,6 +11,10 @@ CONFIG_SPL=y CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 23bcb0e446..4396db0eb1 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -13,6 +13,10 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 26a5320b61..2887ca4167 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -16,6 +16,10 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index af7fe65be1..e5be0d141e 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -12,12 +12,17 @@ CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 index 604e5b9686..0245da0488 100644 --- a/doc/README.JFFS2 +++ b/doc/README.JFFS2 @@ -10,6 +10,9 @@ fsinfo - print information about file systems ls - list files in a directory chpart - change active partition +If you do now need the commands, you can enable the filesystem separately +with CONFIG_FS_JFFS2 and call the jffs2 functions yourself. + If you boot from a partition which is mounted writable, and you update your boot environment by replacing single files on that partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS. Scanning diff --git a/doc/README.omap-reset-time b/doc/README.omap-reset-time deleted file mode 100644 index 0c974bacae..0000000000 --- a/doc/README.omap-reset-time +++ /dev/null @@ -1,20 +0,0 @@ -README on how reset time on OMAPs should be calculated - -CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC: -Most OMAPs' provide a way to specify the time for -which the reset should be held low while the voltages -and Oscillator outputs stabilize. - -This time is mostly board and PMIC dependent. Hence the -boards are expected to specify a pre-computed time -using the above option, (the details on how to compute -the value are given below) without which a default time -as specified by CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC -is used. - -The value for CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC -can be computed using a summation of the below 3 parameters --1- Time taken by the Osciallator to stop and restart --2- PMIC OTP time --3- Voltage ramp time, which can be derived using the -PMIC slew rate and value of voltage ramp needed. diff --git a/doc/README.x86 b/doc/README.x86 index a38cc1bc6c..c69dc1c511 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -1014,12 +1014,12 @@ compile ACPI DSDT table written in ASL format to AML format. You can get the compiler via "apt-get install iasl" if you are on Ubuntu or download the source from [17] to compile one by yourself. -Current ACPI support in U-Boot is not complete. More features will be added -in the future. The status as of today is: +Current ACPI support in U-Boot is basically complete. More optional features +can be added in the future. The status as of today is: * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables. * Support one static DSDT table only, compiled by Intel ACPI compiler. - * Support S0/S5, reboot and shutdown from OS. + * Support S0/S3/S4/S5, reboot and shutdown from OS. * Support booting a pre-installed Ubuntu distribution via 'zboot' command. * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with the help of SeaBIOS using legacy interface (non-UEFI mode). @@ -1027,9 +1027,6 @@ in the future. The status as of today is: of SeaBIOS using legacy interface (non-UEFI mode). * Support ACPI interrupts with SCI only. -Features not supported so far (to make it a complete ACPI solution): - * S3 (Suspend to RAM), S4 (Suspend to Disk). - Features that are optional: * Dynamic AML bytecodes insertion at run-time. We may need this to support SSDT table generation and DSDT fix up. @@ -1046,6 +1043,21 @@ command from the OS. For other platform boards, ACPI support status can be checked by examining their board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y. +The S3 sleeping state is a low wake latency sleeping state defined by ACPI +spec where all system context is lost except system memory. To test S3 resume +with a Linux kernel, simply run "echo mem > /sys/power/state" and kernel will +put the board to S3 state where the power is off. So when the power button is +pressed again, U-Boot runs as it does in cold boot and detects the sleeping +state via ACPI register to see if it is S3, if yes it means we are waking up. +U-Boot is responsible for restoring the machine state as it is before sleep. +When everything is done, U-Boot finds out the wakeup vector provided by OSes +and jump there. To determine whether ACPI S3 resume is supported, check to +see if CONFIG_HAVE_ACPI_RESUME is set for that specific board. + +Note for testing S3 resume with Windows, correct graphics driver must be +installed for your platform, otherwise you won't find "Sleep" option in +the "Power" submenu from the Windows start menu. + EFI Support ----------- U-Boot supports booting as a 32-bit or 64-bit EFI payload, e.g. with UEFI. diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt index 14e316f72c..2988a52aa1 100644 --- a/doc/uImage.FIT/howto.txt +++ b/doc/uImage.FIT/howto.txt @@ -44,6 +44,27 @@ image source file mkimage + dtc transfer to target + ---------------> image file --------------------> bootm image data file(s) +SPL usage +--------- + +The SPL can make use of the new image format as well, this traditionally +is used to ship multiple device tree files within one image. Code in the SPL +will choose the one matching the current board and append this to the +U-Boot proper binary to be automatically used up by it. +Aside from U-Boot proper and one device tree blob the SPL can load multiple, +arbitrary image files as well. These binaries should be specified in their +own subnode under the /images node, which should then be referenced from one or +multiple /configurations subnodes. The required images must be enumerated in +the "loadables" property as a list of strings. + +If a platform specific image source file (.its) is shipped with the U-Boot +source, it can be specified using the CONFIG_SPL_FIT_SOURCE Kconfig symbol. +In this case it will be automatically used by U-Boot's Makefile to generate +the image. +If a static source file is not flexible enough, CONFIG_SPL_FIT_GENERATOR +can point to a script which generates this image source file during +the build process. It gets passed a list of device tree files (taken from the +CONFIG_OF_LIST symbol). Example 1 -- old-style (non-FDT) kernel booting ----------------------------------------------- diff --git a/doc/uImage.FIT/multi_spl.its b/doc/uImage.FIT/multi_spl.its new file mode 100644 index 0000000000..e5551d42b7 --- /dev/null +++ b/doc/uImage.FIT/multi_spl.its @@ -0,0 +1,89 @@ +/dts-v1/; + +/* + * (Bogus) example FIT image description file demonstrating the usage + * of multiple images loaded by the SPL. + * Several binaries will be loaded at their respective load addresses. + * Finally the one image specifying an entry point will be entered by the SPL. + */ + +/ { + description = "multiple firmware blobs and U-Boot, loaded by SPL"; + #address-cells = <0x1>; + + images { + + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x4a000000>; + }; + + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x18000>; + entry = <0x18000>; + }; + + mgmt-firmware { + description = "arisc management processor firmware"; + type = "firmware"; + arch = "or1k"; + compression = "none"; + load = <0x40000>; + }; + + fdt@1 { + description = "Pine64+ DT"; + type = "flat_dt"; + compression = "none"; + load = <0x4fa00000>; + arch = "arm64"; + }; + + fdt@2 { + description = "Pine64 DT"; + type = "flat_dt"; + compression = "none"; + load = <0x4fa00000>; + arch = "arm64"; + }; + + kernel { + description = "4.7-rc5 kernel"; + type = "kernel"; + compression = "none"; + load = <0x40080000>; + arch = "arm64"; + }; + + initrd { + description = "Debian installer initrd"; + type = "ramdisk"; + compression = "none"; + load = <0x4fe00000>; + arch = "arm64"; + }; + }; + + configurations { + default = "config@1"; + + config@1 { + description = "sun50i-a64-pine64-plus"; + loadables = "uboot", "atf", "kernel", "initrd"; + fdt = "fdt@1"; + }; + + config@2 { + description = "sun50i-a64-pine64"; + loadables = "uboot", "atf", "mgmt-firmware"; + fdt = "fdt@2"; + }; + }; +}; diff --git a/drivers/Kconfig b/drivers/Kconfig index a5f24d72da..a736386a0d 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -30,8 +30,6 @@ source "drivers/fpga/Kconfig" source "drivers/gpio/Kconfig" -source "drivers/hwmon/Kconfig" - source "drivers/i2c/Kconfig" source "drivers/input/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 691642023d..058bccb761 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -74,8 +74,8 @@ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-y += firmware/ obj-$(CONFIG_FPGA) += fpga/ -obj-y += hwmon/ obj-y += misc/ +obj-$(CONFIG_MMC) += mmc/ obj-y += pcmcia/ obj-y += dfu/ obj-$(CONFIG_X86) += pch/ @@ -86,7 +86,6 @@ obj-y += spmi/ obj-y += sysreset/ obj-y += timer/ obj-y += tpm/ -obj-y += twserial/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 6cbe1454b8..931defd2ae 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -59,3 +59,11 @@ config DWC_AHCI Synopsys DWC AHCI module. endmenu + +config IDE + bool "Support IDE controllers" + help + Enables support for IDE (Integrated Drive Electronics) hard drives. + This allows access to raw blocks and filesystems on an IDE drive + from U-Boot. See also CMD_IDE which provides an 'ide' command for + performing various IDE operations. diff --git a/drivers/block/Makefile b/drivers/block/Makefile index d89c8b0574..06450966b1 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_DM_SCSI) += scsi-uclass.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o +obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_IDE_FTIDE020) += ftide020.o obj-$(CONFIG_LIBATA) += libata.o obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o diff --git a/common/ide.c b/drivers/block/ide.c index ac5b91c01a..ac5b91c01a 100644 --- a/common/ide.c +++ b/drivers/block/ide.c diff --git a/drivers/block/sil680.c b/drivers/block/sil680.c index 3ca64b980d..b1db257838 100644 --- a/drivers/block/sil680.c +++ b/drivers/block/sil680.c @@ -17,7 +17,7 @@ * incorrect for the target board (e.g. the sequoia board requires 0). * #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 * - * #define CONFIG_CMD_IDE + * #define CONFIG_IDE * #undef CONFIG_IDE_8xx_DIRECT * #undef CONFIG_IDE_LED * #undef CONFIG_IDE_RESET diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index cc0043b990..3c6ab42f7d 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -152,6 +152,15 @@ void device_free(struct udevice *dev) devres_release_probe(dev); } +static bool flags_remove(uint flags, uint drv_flags) +{ + if ((flags & DM_REMOVE_NORMAL) || + (flags & (drv_flags & (DM_FLAG_ACTIVE_DMA | DM_FLAG_OS_PREPARE)))) + return true; + + return false; +} + int device_remove(struct udevice *dev, uint flags) { const struct driver *drv; @@ -178,9 +187,7 @@ int device_remove(struct udevice *dev, uint flags) * Remove the device if called with the "normal" remove flag set, * or if the remove flag matches any of the drivers remove flags */ - if (drv->remove && - ((flags & DM_REMOVE_NORMAL) || - (flags & (drv->flags & DM_FLAG_ACTIVE_DMA)))) { + if (drv->remove && flags_remove(flags, drv->flags)) { ret = drv->remove(dev); if (ret) goto err_remove; @@ -194,8 +201,7 @@ int device_remove(struct udevice *dev, uint flags) } } - if ((flags & DM_REMOVE_NORMAL) || - (flags & (drv->flags & DM_FLAG_ACTIVE_DMA))) { + if (flags_remove(flags, drv->flags)) { device_free(dev); dev->seq = -1; diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 31889598e8..181a1e5e99 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -1,5 +1,7 @@ config FSL_CAAM bool "Freescale Crypto Driver Support" + select SHA_HW_ACCEL + imply CMD_HASH help Enables the Freescale's Cryptographic Accelerator and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses diff --git a/drivers/gpio/74x164_gpio.c b/drivers/gpio/74x164_gpio.c index 750eedfffd..53a639ae65 100644 --- a/drivers/gpio/74x164_gpio.c +++ b/drivers/gpio/74x164_gpio.c @@ -156,8 +156,7 @@ static int gen_74x164_probe(struct udevice *dev) ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret) { - dev_err(dev, "No oe-pins property\n"); - goto free_buf; + dev_dbg(dev, "No oe-pins property\n"); } uc_priv->bank_name = str; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 325d053931..15135e538d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -95,6 +95,14 @@ config MSM_GPIO - APQ8016 - MSM8916 +config OMAP_GPIO + bool "TI OMAP GPIO driver" + depends on ARCH_OMAP2PLUS + default y + help + Support GPIO controllers on the TI OMAP3/4/5 and related (such as + AM335x/AM43xx/AM57xx/DRA7xx/etc) families of SoCs. + config PM8916_GPIO bool "Qualcomm PM8916 PMIC GPIO/keypad driver" depends on DM_GPIO && PMIC_PM8916 diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 8b782260bc..0a9eb03fd0 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -46,22 +46,31 @@ struct ich6_bank_priv { uint16_t use_sel; uint16_t io_sel; uint16_t lvl; + u32 lvl_write_cache; + bool use_lvl_write_cache; }; #define GPIO_USESEL_OFFSET(x) (x) #define GPIO_IOSEL_OFFSET(x) (x + 4) #define GPIO_LVL_OFFSET(x) (x + 8) -static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value) +static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset, + int value) { u32 val; - val = inl(base); + if (bank->use_lvl_write_cache) + val = bank->lvl_write_cache; + else + val = inl(bank->lvl); + if (value) val |= (1UL << offset); else val &= ~(1UL << offset); - outl(val, base); + outl(val, bank->lvl); + if (bank->use_lvl_write_cache) + bank->lvl_write_cache = val; return 0; } @@ -112,6 +121,7 @@ static int ich6_gpio_probe(struct udevice *dev) struct ich6_bank_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct ich6_bank_priv *bank = dev_get_priv(dev); + const void *prop; uc_priv->gpio_count = GPIO_PER_BANK; uc_priv->bank_name = plat->bank_name; @@ -119,6 +129,14 @@ static int ich6_gpio_probe(struct udevice *dev) bank->io_sel = plat->base_addr + 4; bank->lvl = plat->base_addr + 8; + prop = fdt_getprop(gd->fdt_blob, dev->of_offset, + "use-lvl-write-cache", NULL); + if (prop) + bank->use_lvl_write_cache = true; + else + bank->use_lvl_write_cache = false; + bank->lvl_write_cache = 0; + return 0; } @@ -160,7 +178,7 @@ static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, if (ret) return ret; - return _ich6_gpio_set_value(bank->lvl, offset, value); + return _ich6_gpio_set_value(bank, offset, value); } static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) @@ -170,6 +188,8 @@ static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) int r; tmplong = inl(bank->lvl); + if (bank->use_lvl_write_cache) + tmplong |= bank->lvl_write_cache; r = (tmplong & (1UL << offset)) ? 1 : 0; return r; } @@ -178,7 +198,7 @@ static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, int value) { struct ich6_bank_priv *bank = dev_get_priv(dev); - return _ich6_gpio_set_value(bank->lvl, offset, value); + return _ich6_gpio_set_value(bank, offset, value); } static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c index a0eac137c2..ad8da9ef28 100644 --- a/drivers/gpio/sh_pfc.c +++ b/drivers/gpio/sh_pfc.c @@ -66,17 +66,18 @@ static void gpio_write_raw_reg(void *mapped_reg, } static int gpio_read_bit(struct pinmux_data_reg *dr, + unsigned long offset, unsigned long in_pos) { unsigned long pos; pos = dr->reg_width - (in_pos + 1); - debug("read_bit: addr = %lx, pos = %ld, " - "r_width = %ld\n", dr->reg, pos, dr->reg_width); + debug("read_bit: addr = %lx, pos = %ld, r_width = %ld\n", + dr->reg + offset, pos, dr->reg_width); - return - (gpio_read_raw_reg(dr->mapped_reg + 0x4, dr->reg_width) >> pos) & 1; + return (gpio_read_raw_reg(dr->mapped_reg + offset, + dr->reg_width) >> pos) & 1; } static void gpio_write_bit(struct pinmux_data_reg *dr, @@ -559,12 +560,16 @@ static int sh_gpio_direction_output(unsigned offset, int value) static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio) { struct pinmux_data_reg *dr = NULL; - int bit = 0; + int bit = 0, offset = 0; if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0) return -1; +#if defined(CONFIG_RCAR_GEN3) + if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_INPUT) + offset += 4; +#endif - return gpio_read_bit(dr, bit); + return gpio_read_bit(dr, offset, bit); } static int sh_gpio_get(unsigned offset) diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig deleted file mode 100644 index e69de29bb2..0000000000 --- a/drivers/hwmon/Kconfig +++ /dev/null diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile deleted file mode 100644 index b4fb057c16..0000000000 --- a/drivers/hwmon/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2001 -# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -#ccflags-y += -DDEBUG - -obj-$(CONFIG_DTT_ADM1021) += adm1021.o -obj-$(CONFIG_DTT_ADT7460) += adt7460.o -obj-$(CONFIG_DTT_DS1621) += ds1621.o -obj-$(CONFIG_DTT_DS1722) += ds1722.o -obj-$(CONFIG_DTT_DS1775) += ds1775.o -obj-$(CONFIG_DTT_DS620) += ds620.o -obj-$(CONFIG_DTT_LM63) += lm63.o -obj-$(CONFIG_DTT_LM73) += lm73.o -obj-$(CONFIG_DTT_LM75) += lm75.o -obj-$(CONFIG_DTT_LM81) += lm81.o diff --git a/drivers/hwmon/adm1021.c b/drivers/hwmon/adm1021.c deleted file mode 100644 index 99e942b499..0000000000 --- a/drivers/hwmon/adm1021.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2003 - * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au - * - * based on dtt/lm75.c which is ... - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Analog Devices's ADM1021 - * "Low Cost Microprocessor System Temperature Monitor" - */ - -#include <common.h> - -#include <i2c.h> -#include <dtt.h> - -#define DTT_READ_LOC_VALUE 0x00 -#define DTT_READ_REM_VALUE 0x01 -#define DTT_READ_STATUS 0x02 -#define DTT_READ_CONFIG 0x03 -#define DTT_READ_CONVRATE 0x04 -#define DTT_READ_LOC_HIGHLIM 0x05 -#define DTT_READ_LOC_LOWLIM 0x06 -#define DTT_READ_REM_HIGHLIM 0x07 -#define DTT_READ_REM_LOWLIM 0x08 -#define DTT_READ_DEVID 0xfe - -#define DTT_WRITE_CONFIG 0x09 -#define DTT_WRITE_CONVRATE 0x0a -#define DTT_WRITE_LOC_HIGHLIM 0x0b -#define DTT_WRITE_LOC_LOWLIM 0x0c -#define DTT_WRITE_REM_HIGHLIM 0x0d -#define DTT_WRITE_REM_LOWLIM 0x0e -#define DTT_WRITE_ONESHOT 0x0f - -#define DTT_STATUS_BUSY 0x80 /* 1=ADC Converting */ -#define DTT_STATUS_LHIGH 0x40 /* 1=Local High Temp Limit Tripped */ -#define DTT_STATUS_LLOW 0x20 /* 1=Local Low Temp Limit Tripped */ -#define DTT_STATUS_RHIGH 0x10 /* 1=Remote High Temp Limit Tripped */ -#define DTT_STATUS_RLOW 0x08 /* 1=Remote Low Temp Limit Tripped */ -#define DTT_STATUS_OPEN 0x04 /* 1=Remote Sensor Open-Circuit */ - -#define DTT_CONFIG_ALERT_MASKED 0x80 /* 0=ALERT Enabled, 1=ALERT Masked */ -#define DTT_CONFIG_STANDBY 0x40 /* 0=Run, 1=Standby */ - -#define DTT_ADM1021_DEVID 0x41 - -typedef - struct { - uint i2c_addr:7; /* 7bit i2c chip address */ - uint conv_rate:3; /* conversion rate */ - uint enable_alert:1; /* enable alert output pin */ - uint enable_local:1; /* enable internal temp sensor */ - uint max_local:8; /* internal temp maximum */ - uint min_local:8; /* internal temp minimum */ - uint enable_remote:1; /* enable remote temp sensor */ - uint max_remote:8; /* remote temp maximum */ - uint min_remote:8; /* remote temp minimum */ - } -dtt_cfg_t; - -dtt_cfg_t dttcfg[] = CONFIG_SYS_DTT_ADM1021; - -int -dtt_read (int sensor, int reg) -{ - dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; - uchar data; - - if (i2c_read(dcp->i2c_addr, reg, 1, &data, 1) != 0) - return -1; - - return (int)data; -} /* dtt_read() */ - -int -dtt_write (int sensor, int reg, int val) -{ - dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; - uchar data; - - data = (uchar)(val & 0xff); - - if (i2c_write(dcp->i2c_addr, reg, 1, &data, 1) != 0) - return 1; - - return 0; -} /* dtt_write() */ - -int -dtt_init_one(int sensor) -{ - dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; - int reg, val; - - if (((sensor & 1) == 0 ? dcp->enable_local : dcp->enable_remote) == 0) - return 1; /* sensor is disabled (or rather ignored) */ - - /* - * Setup High Limit register - */ - if ((sensor & 1) == 0) { - reg = DTT_WRITE_LOC_HIGHLIM; - val = dcp->max_local; - } - else { - reg = DTT_WRITE_REM_HIGHLIM; - val = dcp->max_remote; - } - if (dtt_write (sensor, reg, val) != 0) - return 1; - - /* - * Setup Low Limit register - */ - if ((sensor & 1) == 0) { - reg = DTT_WRITE_LOC_LOWLIM; - val = dcp->min_local; - } - else { - reg = DTT_WRITE_REM_LOWLIM; - val = dcp->min_remote; - } - if (dtt_write (sensor, reg, val) != 0) - return 1; - - /* shouldn't hurt if the rest gets done twice */ - - /* - * Setup Conversion Rate register - */ - if (dtt_write (sensor, DTT_WRITE_CONVRATE, dcp->conv_rate) != 0) - return 1; - - /* - * Setup configuraton register - */ - val = 0; /* running */ - if (dcp->enable_alert == 0) - val |= DTT_CONFIG_ALERT_MASKED; /* mask ALERT pin */ - if (dtt_write (sensor, DTT_WRITE_CONFIG, val) != 0) - return 1; - - return 0; -} /* dtt_init_one() */ - -int -dtt_get_temp (int sensor) -{ - signed char val; - - if ((sensor & 1) == 0) - val = dtt_read(sensor, DTT_READ_LOC_VALUE); - else - val = dtt_read(sensor, DTT_READ_REM_VALUE); - - return (int) val; -} /* dtt_get_temp() */ diff --git a/drivers/hwmon/adt7460.c b/drivers/hwmon/adt7460.c deleted file mode 100644 index 9b2c5b69ce..0000000000 --- a/drivers/hwmon/adt7460.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid, ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <dtt.h> - -#define ADT7460_ADDRESS 0x2c -#define ADT7460_INVALID 128 -#define ADT7460_CONFIG 0x40 -#define ADT7460_REM1_TEMP 0x25 -#define ADT7460_LOCAL_TEMP 0x26 -#define ADT7460_REM2_TEMP 0x27 - -int dtt_read(int sensor, int reg) -{ - u8 dir = reg; - u8 data; - - if (i2c_read(ADT7460_ADDRESS, dir, 1, &data, 1) == -1) - return -1; - if (data == ADT7460_INVALID) - return -1; - - return data; -} - -int dtt_write(int sensor, int reg, int val) -{ - u8 dir = reg; - u8 data = val; - - if (i2c_write(ADT7460_ADDRESS, dir, 1, &data, 1) == -1) - return -1; - - return 0; -} - -int dtt_init_one(int sensor) -{ - printf("ADT7460 at I2C address 0x%2x\n", ADT7460_ADDRESS); - - if (dtt_write(0, ADT7460_CONFIG, 1) == -1) { - puts("Error initialiting ADT7460\n"); - return -1; - } - - return 0; -} - -int dtt_get_temp(int sensor) -{ - int aux; - u8 table[] = - { ADT7460_REM1_TEMP, ADT7460_LOCAL_TEMP, ADT7460_REM2_TEMP }; - - if (sensor > 2) { - puts("DTT sensor does not exist\n"); - return -1; - } - - aux = dtt_read(0, table[sensor]); - if (aux == -1) { - puts("DTT temperature read failed\n"); - return -1; - } - - return aux; -} diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c deleted file mode 100644 index 66947a664e..0000000000 --- a/drivers/hwmon/ds1621.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat. - */ - -#include <common.h> -#include <i2c.h> -#include <dtt.h> - -/* - * Device code - */ -#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */ -#define DTT_READ_TEMP 0xAA -#define DTT_READ_COUNTER 0xA8 -#define DTT_READ_SLOPE 0xA9 -#define DTT_WRITE_START_CONV 0xEE -#define DTT_WRITE_STOP_CONV 0x22 -#define DTT_TEMP_HIGH 0xA1 -#define DTT_TEMP_LOW 0xA2 -#define DTT_CONFIG 0xAC - -/* - * Config register bits - */ -#define DTT_CONFIG_1SHOT 0x01 -#define DTT_CONFIG_POLARITY 0x02 -#define DTT_CONFIG_R0 0x04 /* ds1631 only */ -#define DTT_CONFIG_R1 0x08 /* ds1631 only */ -#define DTT_CONFIG_NVB 0x10 -#define DTT_CONFIG_TLF 0x20 -#define DTT_CONFIG_THF 0x40 -#define DTT_CONFIG_DONE 0x80 - - -int dtt_read(int sensor, int reg) -{ - int dlen; - uchar data[2]; - - /* Calculate sensor address and command */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/ - - /* Prepare to handle 2 byte result */ - switch(reg) { - case DTT_READ_TEMP: - case DTT_TEMP_HIGH: - case DTT_TEMP_LOW: - dlen = 2; - break; - default: - dlen = 1; - } - - /* Now try to read the register */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return 1; - - /* Handle 2 byte result */ - if (dlen == 2) - return (short)((data[0] << 8) | data[1]); - - return (int)data[0]; -} - - -int dtt_write(int sensor, int reg, int val) -{ - int dlen; - uchar data[2]; - - /* Calculate sensor address and register */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); - - /* Handle various data sizes. */ - switch(reg) { - case DTT_READ_TEMP: - case DTT_TEMP_HIGH: - case DTT_TEMP_LOW: - dlen = 2; - data[0] = (char)((val >> 8) & 0xff); /* MSB first */ - data[1] = (char)(val & 0xff); - break; - case DTT_WRITE_START_CONV: - case DTT_WRITE_STOP_CONV: - dlen = 0; - data[0] = (char)0; - data[1] = (char)0; - break; - default: - dlen = 1; - data[0] = (char)(val & 0xff); - } - - /* Write value to device */ - if (i2c_write(sensor, reg, 1, data, dlen) != 0) - return 1; - - /* Poll NV memory busy bit in case write was to register stored in EEPROM */ - while(i2c_reg_read(sensor, DTT_CONFIG) & DTT_CONFIG_NVB) - ; - - return 0; -} - - -int dtt_init_one(int sensor) -{ - int val; - - /* Setup High Temp */ - val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) - return 1; - - /* Setup Low Temp - hysteresis */ - val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) - return 1; - - /* - * Setup configuraton register - * - * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES - * - * We run in polled mode, since there isn't any way to know if this - * lousy device is ready to provide temperature readings on power up. - */ - val = 0x9; - if (dtt_write(sensor, DTT_CONFIG, val) != 0) - return 1; - - return 0; -} - -int dtt_get_temp(int sensor) -{ - int i; - - /* Start a conversion, may take up to 1 second. */ - dtt_write(sensor, DTT_WRITE_START_CONV, 0); - for (i = 0; i <= 10; i++) { - udelay(100000); - if (dtt_read(sensor, DTT_CONFIG) & DTT_CONFIG_DONE) - break; - } - - return (dtt_read(sensor, DTT_READ_TEMP) / 256); -} diff --git a/drivers/hwmon/ds1722.c b/drivers/hwmon/ds1722.c deleted file mode 100644 index c46958846c..0000000000 --- a/drivers/hwmon/ds1722.c +++ /dev/null @@ -1,137 +0,0 @@ -#include <common.h> -#include <asm/ic/ssi.h> -#include <ds1722.h> - -static void ds1722_select(int dev) -{ - ssi_set_interface(4096, 0, 0, 0); - ssi_chip_select(0); - udelay(1); - ssi_chip_select(dev); - udelay(1); -} - - -u8 ds1722_read(int dev, int addr) -{ - u8 res; - - ds1722_select(dev); - - ssi_tx_byte(addr); - res = ssi_rx_byte(); - - ssi_chip_select(0); - - return res; -} - -void ds1722_write(int dev, int addr, u8 data) -{ - ds1722_select(dev); - - ssi_tx_byte(0x80|addr); - ssi_tx_byte(data); - - ssi_chip_select(0); -} - - -u16 ds1722_temp(int dev, int resolution) -{ - static int useconds[] = { - 75000, 150000, 300000, 600000, 1200000 - }; - char temp; - u16 res; - - - /* set up the desired resulotion ... */ - ds1722_write(dev, 0, 0xe0 | (resolution << 1)); - - /* wait while the chip measures the tremperature */ - udelay(useconds[resolution]); - - res = (temp = ds1722_read(dev, 2)) << 8; - - if (temp < 0) { - temp = (16 - (ds1722_read(dev, 1) >> 4)) & 0x0f; - } else { - temp = (ds1722_read(dev, 1) >> 4); - } - - switch (temp) { - case 0: - /* .0000 */ - break; - case 1: - /* .0625 */ - res |=1; - break; - case 2: - /* .1250 */ - res |=1; - break; - case 3: - /* .1875 */ - res |=2; - break; - case 4: - /* .2500 */ - res |=3; - break; - case 5: - /* .3125 */ - res |=3; - break; - case 6: - /* .3750 */ - res |=4; - break; - case 7: - /* .4375 */ - res |=4; - break; - case 8: - /* .5000 */ - res |=5; - break; - case 9: - /* .5625 */ - res |=6; - break; - case 10: - /* .6250 */ - res |=6; - break; - case 11: - /* .6875 */ - res |=7; - break; - case 12: - /* .7500 */ - res |=8; - break; - case 13: - /* .8125 */ - res |=8; - break; - case 14: - /* .8750 */ - res |=9; - break; - case 15: - /* .9375 */ - res |=9; - break; - } - return res; - -} - -int ds1722_probe(int dev) -{ - u16 temp = ds1722_temp(dev, DS1722_RESOLUTION_12BIT); - printf("%d.%d deg C\n\n", (char)(temp >> 8), temp & 0xff); - return 0; -} diff --git a/drivers/hwmon/ds1775.c b/drivers/hwmon/ds1775.c deleted file mode 100644 index b95b130d92..0000000000 --- a/drivers/hwmon/ds1775.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat - */ - -#include <common.h> - -#include <i2c.h> -#include <dtt.h> - -#define DTT_I2C_DEV_CODE CONFIG_SYS_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */ -#define DTT_READ_TEMP 0x0 -#define DTT_CONFIG 0x1 -#define DTT_TEMP_HYST 0x2 -#define DTT_TEMP_OS 0x3 - -int dtt_read(int sensor, int reg) -{ - int dlen; - uchar data[2]; - - /* - * Calculate sensor address and command - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */ - - /* - * Prepare to handle 2 byte result - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) - dlen = 2; - else - dlen = 1; - - /* - * Now try to read the register - */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return 1; - - /* - * Handle 2 byte result - */ - if (dlen == 2) - return ((int)((short)data[1] + (((short)data[0]) << 8))); - - return (int) data[0]; -} - - -int dtt_write(int sensor, int reg, int val) -{ - int dlen; - uchar data[2]; - - /* - * Calculate sensor address and register - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); - - /* - * Handle various data sizes - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) { - dlen = 2; - data[0] = (char)((val >> 8) & 0xff); /* MSB first */ - data[1] = (char)(val & 0xff); - } else { - dlen = 1; - data[0] = (char)(val & 0xff); - } - - /* - * Write value to device - */ - if (i2c_write(sensor, reg, 1, data, dlen) != 0) - return 1; - - return 0; -} - - -int dtt_init_one(int sensor) -{ - int val; - - /* - * Setup High Temp - */ - val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_OS, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ - - /* - * Setup Low Temp - hysteresis - */ - val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ - - /* - * Setup configuraton register - * - * Fault Tolerance limits 4, Thermometer resolution bits is 9, - * Polarity = Active Low,continuous conversion mode, Thermostat - * mode is interrupt mode - */ - val = 0xa; - if (dtt_write(sensor, DTT_CONFIG, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ - - return 0; -} - -int dtt_get_temp(int sensor) -{ - return (dtt_read(sensor, DTT_READ_TEMP) / 256); -} diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c deleted file mode 100644 index 1ecc3da799..0000000000 --- a/drivers/hwmon/ds620.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * DS620 DTT support - * - * (C) Copyright 2014 3ADEV <http://www.3adev.com> - * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat. - */ - -#include <common.h> -#include <i2c.h> -#include <dtt.h> - -/* - * Device code - */ -#define DTT_I2C_DEV_CODE 0x48 -#define DTT_START_CONVERT 0x51 -#define DTT_TEMP 0xAA -#define DTT_CONFIG 0xAC - -/* - * Config register MSB bits - */ -#define DTT_CONFIG_1SHOT 0x01 -#define DTT_CONFIG_AUTOC 0x02 -#define DTT_CONFIG_R0 0x04 /* always 1 */ -#define DTT_CONFIG_R1 0x08 /* always 1 */ -#define DTT_CONFIG_TLF 0x10 -#define DTT_CONFIG_THF 0x20 -#define DTT_CONFIG_NVB 0x40 -#define DTT_CONFIG_DONE 0x80 - -#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor & 0x07)) - -int dtt_init_one(int sensor) -{ - uint8_t config = DTT_CONFIG_1SHOT - | DTT_CONFIG_R0 - | DTT_CONFIG_R1; - return i2c_write(CHIP(sensor), DTT_CONFIG, 1, &config, 1); -} - -int dtt_get_temp(int sensor) -{ - uint8_t status; - uint8_t temp[2]; - - /* Start a conversion, may take up to 1 second. */ - i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0); - do { - if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, &status, 1)) - /* bail out if I2C error */ - status |= DTT_CONFIG_DONE; - } while (!(status & DTT_CONFIG_DONE)); - if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2)) - /* bail out if I2C error */ - return -274; /* below absolute zero == error */ - - return ((int16_t)(temp[1] | (temp[0] << 8))) >> 7; -} diff --git a/drivers/hwmon/lm63.c b/drivers/hwmon/lm63.c deleted file mode 100644 index 053c785fc5..0000000000 --- a/drivers/hwmon/lm63.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * based on lm75.c by Bill Hunter - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * National LM63/LM64 Temperature Sensor - * Main difference: LM 64 has -16 Kelvin temperature offset - */ - -#include <common.h> -#include <i2c.h> -#include <dtt.h> - -#define DTT_I2C_LM63_ADDR 0x4C /* National LM63 device */ - -#define DTT_READ_TEMP_RMT_MSB 0x01 -#define DTT_CONFIG 0x03 -#define DTT_READ_TEMP_RMT_LSB 0x10 -#define DTT_TACHLIM_LSB 0x48 -#define DTT_TACHLIM_MSB 0x49 -#define DTT_FAN_CONFIG 0x4A -#define DTT_PWM_FREQ 0x4D -#define DTT_PWM_LOOKUP_BASE 0x50 - -struct pwm_lookup_entry { - u8 temp; - u8 pwm; -}; - -/* - * Device code - */ - -int dtt_read(int sensor, int reg) -{ - int dlen; - uchar data[2]; - - /* - * Calculate sensor address and register. - */ - if (!sensor) - sensor = DTT_I2C_LM63_ADDR; /* legacy config */ - - dlen = 1; - - /* - * Now try to read the register. - */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return -1; - - return (int)data[0]; -} /* dtt_read() */ - -int dtt_write(int sensor, int reg, int val) -{ - int dlen; - uchar data[2]; - - /* - * Calculate sensor address and register. - */ - if (!sensor) - sensor = DTT_I2C_LM63_ADDR; /* legacy config */ - - dlen = 1; - data[0] = (char)(val & 0xff); - - /* - * Write value to register. - */ - if (i2c_write(sensor, reg, 1, data, dlen) != 0) - return 1; - - return 0; -} /* dtt_write() */ - -static int is_lm64(int sensor) -{ - return sensor && (sensor != DTT_I2C_LM63_ADDR); -} - -int dtt_init_one(int sensor) -{ - int i; - int val; - - struct pwm_lookup_entry pwm_lookup[] = CONFIG_DTT_PWM_LOOKUPTABLE; - - /* - * Set PWM Frequency to 2.5% resolution - */ - val = 20; - if (dtt_write(sensor, DTT_PWM_FREQ, val) != 0) - return 1; - - /* - * Set Tachometer Limit - */ - val = CONFIG_DTT_TACH_LIMIT; - if (dtt_write(sensor, DTT_TACHLIM_LSB, val & 0xff) != 0) - return 1; - if (dtt_write(sensor, DTT_TACHLIM_MSB, (val >> 8) & 0xff) != 0) - return 1; - - /* - * Make sure PWM Lookup-Table is writeable - */ - if (dtt_write(sensor, DTT_FAN_CONFIG, 0x20) != 0) - return 1; - - /* - * Setup PWM Lookup-Table - */ - for (i = 0; i < ARRAY_SIZE(pwm_lookup); i++) { - int address = DTT_PWM_LOOKUP_BASE + 2 * i; - val = pwm_lookup[i].temp; - if (is_lm64(sensor)) - val -= 16; - if (dtt_write(sensor, address, val) != 0) - return 1; - val = dtt_read(sensor, address); - val = pwm_lookup[i].pwm; - if (dtt_write(sensor, address + 1, val) != 0) - return 1; - } - - /* - * Enable PWM Lookup-Table, PWM Clock 360 kHz, Tachometer Mode 2 - */ - val = 0x02; - if (dtt_write(sensor, DTT_FAN_CONFIG, val) != 0) - return 1; - - /* - * Enable Tach input - */ - val = dtt_read(sensor, DTT_CONFIG) | 0x04; - if (dtt_write(sensor, DTT_CONFIG, val) != 0) - return 1; - - return 0; -} - -int dtt_get_temp(int sensor) -{ - s16 temp = (dtt_read(sensor, DTT_READ_TEMP_RMT_MSB) << 8) - | (dtt_read(sensor, DTT_READ_TEMP_RMT_LSB)); - - if (is_lm64(sensor)) - temp += 16 << 8; - - /* Ignore LSB for now, U-Boot only prints natural numbers */ - return temp >> 8; -} diff --git a/drivers/hwmon/lm73.c b/drivers/hwmon/lm73.c deleted file mode 100644 index c15c7514d8..0000000000 --- a/drivers/hwmon/lm73.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Larry Johnson, lrj@acm.org - * - * based on dtt/lm75.c which is ... - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * National Semiconductor LM73 Temperature Sensor - */ - -#include <common.h> -#include <i2c.h> -#include <dtt.h> - -/* - * Device code - */ -#define DTT_I2C_DEV_CODE 0x48 /* National Semi's LM73 device */ -#define DTT_READ_TEMP 0x0 -#define DTT_CONFIG 0x1 -#define DTT_TEMP_HIGH 0x2 -#define DTT_TEMP_LOW 0x3 -#define DTT_CONTROL 0x4 -#define DTT_ID 0x7 - -int dtt_read(int const sensor, int const reg) -{ - int dlen; - uint8_t data[2]; - - /* - * Validate 'reg' param and get register size. - */ - switch (reg) { - case DTT_CONFIG: - case DTT_CONTROL: - dlen = 1; - break; - case DTT_READ_TEMP: - case DTT_TEMP_HIGH: - case DTT_TEMP_LOW: - case DTT_ID: - dlen = 2; - break; - default: - return -1; - } - /* - * Try to read the register at the calculated sensor address. - */ - if (0 != - i2c_read(DTT_I2C_DEV_CODE + (sensor & 0x07), reg, 1, data, dlen)) - return -1; - /* - * Handle 2 byte result. - */ - if (2 == dlen) - return (int)((unsigned)data[0] << 8 | (unsigned)data[1]); - - return (int)data[0]; -} /* dtt_read() */ - -int dtt_write(int const sensor, int const reg, int const val) -{ - int dlen; - uint8_t data[2]; - - /* - * Validate 'reg' param and handle register size - */ - switch (reg) { - case DTT_CONFIG: - case DTT_CONTROL: - dlen = 1; - data[0] = (uint8_t) val; - break; - case DTT_TEMP_HIGH: - case DTT_TEMP_LOW: - dlen = 2; - data[0] = (uint8_t) (val >> 8); /* MSB first */ - data[1] = (uint8_t) val; - break; - default: - return -1; - } - /* - * Write value to register at the calculated sensor address. - */ - return 0 != i2c_write(DTT_I2C_DEV_CODE + (sensor & 0x07), reg, 1, data, - dlen); -} /* dtt_write() */ - -int dtt_init_one(int const sensor) -{ - int val; - - /* - * Validate the Identification register - */ - if (0x0190 != dtt_read(sensor, DTT_ID)) - return -1; - /* - * Setup THIGH (upper-limit) and TLOW (lower-limit) registers - */ - val = CONFIG_SYS_DTT_MAX_TEMP << 7; - if (dtt_write(sensor, DTT_TEMP_HIGH, val)) - return -1; - - val = CONFIG_SYS_DTT_MIN_TEMP << 7; - if (dtt_write(sensor, DTT_TEMP_LOW, val)) - return -1; - /* - * Setup configuraton register - */ - /* config = alert active low, disabled, and reset */ - val = 0x64; - if (dtt_write(sensor, DTT_CONFIG, val)) - return -1; - /* - * Setup control/status register - */ - /* control = temp resolution 0.25C */ - val = 0x00; - if (dtt_write(sensor, DTT_CONTROL, val)) - return -1; - - dtt_read(sensor, DTT_CONTROL); /* clear temperature flags */ - return 0; -} /* dtt_init_one() */ - -int dtt_get_temp(int const sensor) -{ - int const ret = dtt_read(sensor, DTT_READ_TEMP); - - if (ret < 0) { - printf("DTT temperature read failed.\n"); - return 0; - } - return (int)((int16_t) ret + 0x0040) >> 7; -} /* dtt_get_temp() */ diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c deleted file mode 100644 index 462f902dad..0000000000 --- a/drivers/hwmon/lm75.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * On Semiconductor's LM75 Temperature Sensor - */ - -#include <common.h> -#include <i2c.h> -#include <dtt.h> - -/* - * Device code - */ -#if defined(CONFIG_SYS_I2C_DTT_ADDR) -#define DTT_I2C_DEV_CODE CONFIG_SYS_I2C_DTT_ADDR -#else -#define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */ -#endif -#define DTT_READ_TEMP 0x0 -#define DTT_CONFIG 0x1 -#define DTT_TEMP_HYST 0x2 -#define DTT_TEMP_SET 0x3 - -int dtt_read(int sensor, int reg) -{ - int dlen; - uchar data[2]; - -#ifdef CONFIG_DTT_AD7414 - /* - * On AD7414 the first value upon bootup is not read correctly. - * This is most likely because of the 800ms update time of the - * temp register in normal update mode. To get current values - * each time we issue the "dtt" command including upon powerup - * we switch into one-short mode. - * - * Issue one-shot mode command - */ - dtt_write(sensor, DTT_CONFIG, 0x64); -#endif - - /* Validate 'reg' param */ - if((reg < 0) || (reg > 3)) - return -1; - - /* Calculate sensor address and register. */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); - - /* Prepare to handle 2 byte result. */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HYST) || - (reg == DTT_TEMP_SET)) - dlen = 2; - else - dlen = 1; - - /* Now try to read the register. */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return -1; - - /* Handle 2 byte result. */ - if (dlen == 2) - return ((int)((short)data[1] + (((short)data[0]) << 8))); - - return (int)data[0]; -} /* dtt_read() */ - - -int dtt_write(int sensor, int reg, int val) -{ - int dlen; - uchar data[2]; - - /* Validate 'reg' param */ - if ((reg < 0) || (reg > 3)) - return 1; - - /* Calculate sensor address and register. */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); - - /* Handle 2 byte values. */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HYST) || - (reg == DTT_TEMP_SET)) { - dlen = 2; - data[0] = (char)((val >> 8) & 0xff); /* MSB first */ - data[1] = (char)(val & 0xff); - } else { - dlen = 1; - data[0] = (char)(val & 0xff); - } - - /* Write value to register. */ - if (i2c_write(sensor, reg, 1, data, dlen) != 0) - return 1; - - return 0; -} /* dtt_write() */ - - -int dtt_init_one(int sensor) -{ - int val; - - /* Setup TSET ( trip point ) register */ - val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */ - if (dtt_write(sensor, DTT_TEMP_SET, val) != 0) - return 1; - - /* Setup THYST ( untrip point ) register - Hysteresis */ - val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) - return 1; - - /* Setup configuraton register */ -#ifdef CONFIG_DTT_AD7414 - /* config = alert active low and disabled */ - val = 0x60; -#else - /* config = 6 sample integration, int mode, active low, and enable */ - val = 0x18; -#endif - if (dtt_write(sensor, DTT_CONFIG, val) != 0) - return 1; - - return 0; -} /* dtt_init_one() */ - -int dtt_get_temp(int sensor) -{ - int const ret = dtt_read(sensor, DTT_READ_TEMP); - - if (ret < 0) { - printf("DTT temperature read failed.\n"); - return 0; - } - return (int)((int16_t) ret / 256); -} /* dtt_get_temp() */ diff --git a/drivers/hwmon/lm81.c b/drivers/hwmon/lm81.c deleted file mode 100644 index bcc8d3293b..0000000000 --- a/drivers/hwmon/lm81.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Enginnering <hs@denx.de> - * - * based on dtt/lm75.c which is ... - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * On Semiconductor's LM81 Temperature Sensor - */ - -#include <common.h> -#include <i2c.h> -#include <dtt.h> - -/* - * Device code - */ -#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */ -#define DTT_READ_TEMP 0x27 -#define DTT_CONFIG_TEMP 0x4b -#define DTT_TEMP_MAX 0x39 -#define DTT_TEMP_HYST 0x3a -#define DTT_CONFIG 0x40 - -int dtt_read(int sensor, int reg) -{ - int dlen = 1; - uchar data[2]; - - /* - * Calculate sensor address and register. - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */ - - /* - * Now try to read the register. - */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return -1; - - return (int)data[0]; -} /* dtt_read() */ - - -int dtt_write(int sensor, int reg, int val) -{ - uchar data; - - /* - * Calculate sensor address and register. - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */ - - data = (char)(val & 0xff); - - /* - * Write value to register. - */ - if (i2c_write(sensor, reg, 1, &data, 1) != 0) - return 1; - - return 0; -} /* dtt_write() */ - -#define DTT_MANU 0x3e -#define DTT_REV 0x3f -#define DTT_CONFIG 0x40 -#define DTT_ADR 0x48 - -int dtt_init_one(int sensor) -{ - int man; - int adr; - int rev; - - if (dtt_write (sensor, DTT_CONFIG, 0x01) < 0) - return 1; - /* The LM81 needs 400ms to get the correct values ... */ - udelay (400000); - man = dtt_read (sensor, DTT_MANU); - if (man != 0x01) - return 1; - adr = dtt_read (sensor, DTT_ADR); - if (adr < 0) - return 1; - rev = dtt_read (sensor, DTT_REV); - if (rev < 0) - return 1; - - debug ("DTT: Found LM81@%x Rev: %d\n", adr, rev); - return 0; -} /* dtt_init_one() */ - - -#define TEMP_FROM_REG(temp) \ - ((temp)<256?((((temp)&0x1fe) >> 1) * 10) + ((temp) & 1) * 5: \ - ((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5) \ - -int dtt_get_temp(int sensor) -{ - int val = dtt_read (sensor, DTT_READ_TEMP); - int tmpcnf = dtt_read (sensor, DTT_CONFIG_TEMP); - - return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10; -} /* dtt_get_temp() */ diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index a1406baa87..ff3dc25927 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -284,15 +284,6 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int break; } - -#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT - /* Call board specific i2c bus reset routine AFTER the bus has been - * initialized. Use either this callpoint or i2c_init_board; - * which is called before i2c_init operations. - * For details about this problem see doc/I2C_Edge_Conditions. - */ - i2c_board_late_init(); -#endif } static int diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c index b35d0d2d9c..4da959fa53 100644 --- a/drivers/i2c/fti2c010.c +++ b/drivers/i2c/fti2c010.c @@ -146,15 +146,6 @@ static void fti2c010_init(struct i2c_adapter *adap, int speed, int slaveaddr) set_i2c_bus_speed(chip, speed); /* slave init, don't care */ - -#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT - /* Call board specific i2c bus reset routine AFTER the bus has been - * initialized. Use either this callpoint or i2c_init_board; - * which is called before fti2c010_init operations. - * For details about this problem see doc/I2C_Edge_Conditions. - */ - i2c_board_late_init(); -#endif } /* diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 13ec0e63b1..b68e82770b 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -69,10 +69,6 @@ DECLARE_GLOBAL_DATA_PTR; #define I2SR_IIF_CLEAR (0 << 1) #endif -#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) -#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" -#endif - #ifdef I2C_QUIRK_REG static u16 i2c_clk_div[60][2] = { { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a23737ab78..4b8397a890 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -122,7 +122,7 @@ static int wait_for_bb(struct i2c *i2c_base, int waitdelay) u16 stat; writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP34XX) while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { #else /* Read RAW status */ @@ -153,7 +153,7 @@ static u16 wait_for_event(struct i2c *i2c_base, int waitdelay) do { udelay(waitdelay); -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP34XX) status = readw(&i2c_base->stat); #else /* Read RAW status */ @@ -338,7 +338,7 @@ retry: /* own address */ writew(slaveadd, &i2c_base->oa); -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have * an 'irqstatus_raw' register and we shall have to poll 'stat' diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 1aae4bcd07..ecca159d14 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -75,6 +75,14 @@ config CROS_EC_SPI provides a faster and more robust interface than I2C but the bugs are less interesting. +config DS4510 + bool "Enable support for DS4510 CPU supervisor" + help + Enable support for the Maxim DS4510 CPU supervisor. It has an + integrated 64-byte EEPROM, four programmable non-volatile I/O pins + and a configurable timer for the supervisor function. The device is + connected over I2C. + config FSL_SEC_MON bool "Enable FSL SEC_MON Driver" help diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c index d7c9bd73c8..55f8936513 100644 --- a/drivers/misc/ds4510.c +++ b/drivers/misc/ds4510.c @@ -12,12 +12,7 @@ #include <common.h> #include <i2c.h> #include <command.h> -#include <ds4510.h> - -/* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_DS4510_ADDR -#define CONFIG_SYS_I2C_DS4510_ADDR (~0) -#endif +#include "ds4510.h" enum { DS4510_CMD_INFO, @@ -35,7 +30,7 @@ enum { /* * Write to DS4510, taking page boundaries into account */ -int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) +static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) { int wrlen; int i = 0; @@ -64,7 +59,7 @@ int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) /* * General read from DS4510 */ -int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) +static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) { return i2c_read(chip, offset, 1, buf, count); } @@ -74,7 +69,7 @@ int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) * nv = 0 - Writes to SEEPROM registers behave like EEPROM * nv = 1 - Writes to SEEPROM registers behave like SRAM */ -int ds4510_see_write(uint8_t chip, uint8_t nv) +static int ds4510_see_write(uint8_t chip, uint8_t nv) { uint8_t data; @@ -92,7 +87,7 @@ int ds4510_see_write(uint8_t chip, uint8_t nv) /* * Write de-assertion of reset signal delay */ -int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) +static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) { uint8_t data; @@ -108,7 +103,7 @@ int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) /* * Write pullup characteristics of IO pins */ -int ds4510_pullup_write(uint8_t chip, uint8_t val) +static int ds4510_pullup_write(uint8_t chip, uint8_t val) { val &= DS4510_IO_MASK; @@ -118,7 +113,7 @@ int ds4510_pullup_write(uint8_t chip, uint8_t val) /* * Read pullup characteristics of IO pins */ -int ds4510_pullup_read(uint8_t chip) +static int ds4510_pullup_read(uint8_t chip) { uint8_t val; @@ -131,7 +126,7 @@ int ds4510_pullup_read(uint8_t chip) /* * Write drive level of IO pins */ -int ds4510_gpio_write(uint8_t chip, uint8_t val) +static int ds4510_gpio_write(uint8_t chip, uint8_t val) { uint8_t data; int i; @@ -155,7 +150,7 @@ int ds4510_gpio_write(uint8_t chip, uint8_t val) /* * Read drive level of IO pins */ -int ds4510_gpio_read(uint8_t chip) +static int ds4510_gpio_read(uint8_t chip) { uint8_t data; int val = 0; @@ -175,7 +170,7 @@ int ds4510_gpio_read(uint8_t chip) /* * Read physical level of IO pins */ -int ds4510_gpio_read_val(uint8_t chip) +static int ds4510_gpio_read_val(uint8_t chip) { uint8_t val; @@ -185,8 +180,6 @@ int ds4510_gpio_read_val(uint8_t chip) return val & DS4510_IO_MASK; } -#ifdef CONFIG_CMD_DS4510 -#ifdef CONFIG_CMD_DS4510_INFO /* * Display DS4510 information */ @@ -240,7 +233,6 @@ static int ds4510_info(uint8_t chip) return 0; } -#endif /* CONFIG_CMD_DS4510_INFO */ cmd_tbl_t cmd_ds4510[] = { U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""), @@ -248,33 +240,25 @@ cmd_tbl_t cmd_ds4510[] = { U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""), U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""), U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""), -#ifdef CONFIG_CMD_DS4510_INFO U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""), -#endif -#ifdef CONFIG_CMD_DS4510_RST U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""), -#endif -#ifdef CONFIG_CMD_DS4510_MEM U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""), U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""), U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""), -#endif }; int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR; + static uint8_t chip = 0x51; cmd_tbl_t *c; ulong ul_arg2 = 0; ulong ul_arg3 = 0; int tmp; -#ifdef CONFIG_CMD_DS4510_MEM ulong addr; ulong off; ulong cnt; int end; int (*rw_func)(uint8_t, int, uint8_t *, int); -#endif c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510)); @@ -324,15 +308,10 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else tmp &= ~(1 << ul_arg2); return ds4510_pullup_write(chip, tmp); -#ifdef CONFIG_CMD_DS4510_INFO case DS4510_CMD_INFO: return ds4510_info(chip); -#endif -#ifdef CONFIG_CMD_DS4510_RST case DS4510_CMD_RSTDELAY: return ds4510_rstdelay_write(chip, ul_arg2); -#endif -#ifdef CONFIG_CMD_DS4510_MEM case DS4510_CMD_EEPROM: end = DS4510_EEPROM + DS4510_EEPROM_SIZE; off = DS4510_EEPROM; @@ -345,13 +324,11 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) end = DS4510_SRAM + DS4510_SRAM_SIZE; off = DS4510_SRAM; break; -#endif default: /* We should never get here... */ return 1; } -#ifdef CONFIG_CMD_DS4510_MEM /* Only eeprom, seeprom, and sram commands should make it here */ if (strcmp(argv[2], "read") == 0) rw_func = ds4510_mem_read; @@ -370,7 +347,6 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } return rw_func(chip, off, (uint8_t *)addr, cnt); -#endif } U_BOOT_CMD( @@ -378,10 +354,8 @@ U_BOOT_CMD( "ds4510 eeprom/seeprom/sram/gpio access", "device [dev]\n" " - show or set current device address\n" -#ifdef CONFIG_CMD_DS4510_INFO "ds4510 info\n" " - display ds4510 info\n" -#endif "ds4510 output pin 0|1\n" " - set pin low or high-Z\n" "ds4510 input pin\n" @@ -390,12 +364,9 @@ U_BOOT_CMD( " - disable/enable pullup on specified pin\n" "ds4510 nv 0|1\n" " - make gpio and seeprom writes volatile/non-volatile" -#ifdef CONFIG_CMD_DS4510_RST "\n" "ds4510 rstdelay 0-3\n" " - set reset output delay" -#endif -#ifdef CONFIG_CMD_DS4510_MEM "\n" "ds4510 eeprom read addr off cnt\n" "ds4510 eeprom write addr off cnt\n" @@ -406,6 +377,4 @@ U_BOOT_CMD( "ds4510 sram read addr off cnt\n" "ds4510 sram write addr off cnt\n" " - read/write 'cnt' bytes at SRAM offset 'off'" -#endif ); -#endif /* CONFIG_CMD_DS4510 */ diff --git a/include/ds4510.h b/drivers/misc/ds4510.h index e54db35265..a6c6c58cc4 100644 --- a/include/ds4510.h +++ b/drivers/misc/ds4510.h @@ -50,14 +50,4 @@ #define DS4510_SRAM 0xfa #define DS4510_SRAM_SIZE 0x06 -int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count); -int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count); -int ds4510_see_write(uint8_t chip, uint8_t nv); -int ds4510_rstdelay_write(uint8_t chip, uint8_t delay); -int ds4510_pullup_write(uint8_t chip, uint8_t val); -int ds4510_pullup_read(uint8_t chip); -int ds4510_gpio_write(uint8_t chip, uint8_t val); -int ds4510_gpio_read(uint8_t chip); -int ds4510_gpio_read_val(uint8_t chip); - #endif /* __DS4510_H_ */ diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6ac26dd137..0dd4443602 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -10,10 +10,6 @@ config MMC If you want MMC/SD/SDIO support, you should say Y here and also to your specific host controller driver. -config GENERIC_MMC - bool "Generic MMC driver framework" - default MMC - config DM_MMC bool "Enable MMC controllers using Driver Model" depends on DM @@ -138,6 +134,7 @@ config MMC_PCI config MMC_OMAP_HS bool "TI OMAP High Speed Multimedia Card Interface support" + select DM_MMC_OPS if DM_MMC help This selects the TI OMAP High Speed Multimedia card Interface. If you have an omap2plus board with a Multimedia Card slot, diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index de91f1423b..a078649899 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -5,17 +5,24 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_DM_MMC -obj-$(CONFIG_GENERIC_MMC) += mmc-uclass.o -endif +obj-y += mmc.o +obj-$(CONFIG_DM_MMC) += mmc-uclass.o ifndef CONFIG_BLK -obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o +obj-y += mmc_legacy.o +endif + +obj-$(CONFIG_SUPPORT_EMMC_BOOT) += mmc_boot.o + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o +obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o +else +obj-y += mmc_write.o endif obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o - obj-$(CONFIG_MMC_DW) += dw_mmc.o obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o @@ -23,10 +30,6 @@ obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o -obj-$(CONFIG_GENERIC_MMC) += mmc.o -ifdef CONFIG_SUPPORT_EMMC_BOOT -obj-$(CONFIG_GENERIC_MMC) += mmc_boot.o -endif obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o @@ -42,13 +45,6 @@ obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o -obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o -else -obj-$(CONFIG_GENERIC_MMC) += mmc_write.o -endif - # SDHCI obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index 852255782f..86e36a9c28 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -28,7 +28,7 @@ int atmel_sdhci_init(void *regbase, u32 id) host->name = "atmel_sdhci"; host->ioaddr = regbase; - host->quirks = 0; + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; max_clk = at91_get_periph_generated_clk(id); if (!max_clk) { printf("%s: Failed to get the proper clock\n", __func__); @@ -74,7 +74,7 @@ static int atmel_sdhci_probe(struct udevice *dev) host->name = dev->name; host->ioaddr = (void *)dev_get_addr(dev); - host->quirks = 0; + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", 4); diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index 9edb668e14..dd784290bc 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -347,7 +347,7 @@ static int dmmc_init(struct mmc *mmc) return 0; } -/* Set buswidth or clock as indicated by the GENERIC_MMC framework */ +/* Set buswidth or clock as indicated by the MMC framework */ static int dmmc_set_ios(struct mmc *mmc) { struct davinci_mmc *host = mmc->priv; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index c136ab0ec8..0b21ec6efc 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -326,11 +326,17 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) } } } - +#ifndef CONFIG_DM_MMC static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); +#else +static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct omap_hsmmc_data *priv = dev_get_priv(dev); +#endif struct hsmmc *mmc_base; unsigned int flags, mmc_stat; ulong start; @@ -558,9 +564,17 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, return 0; } +#ifndef CONFIG_DM_MMC static int omap_hsmmc_set_ios(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); +#else +static int omap_hsmmc_set_ios(struct udevice *dev) +{ + struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; +#endif struct hsmmc *mmc_base; unsigned int dsor = 0; ulong start; @@ -617,9 +631,9 @@ static int omap_hsmmc_set_ios(struct mmc *mmc) #ifdef OMAP_HSMMC_USE_GPIO #ifdef CONFIG_DM_MMC -static int omap_hsmmc_getcd(struct mmc *mmc) +static int omap_hsmmc_getcd(struct udevice *dev) { - struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct omap_hsmmc_data *priv = dev_get_priv(dev); int value; value = dm_gpio_get_value(&priv->cd_gpio); @@ -632,9 +646,9 @@ static int omap_hsmmc_getcd(struct mmc *mmc) return value; } -static int omap_hsmmc_getwp(struct mmc *mmc) +static int omap_hsmmc_getwp(struct udevice *dev) { - struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct omap_hsmmc_data *priv = dev_get_priv(dev); int value; value = dm_gpio_get_value(&priv->wp_gpio); @@ -674,6 +688,16 @@ static int omap_hsmmc_getwp(struct mmc *mmc) #endif #endif +#ifdef CONFIG_DM_MMC +static const struct dm_mmc_ops omap_hsmmc_ops = { + .send_cmd = omap_hsmmc_send_cmd, + .set_ios = omap_hsmmc_set_ios, +#ifdef OMAP_HSMMC_USE_GPIO + .get_cd = omap_hsmmc_getcd, + .get_wp = omap_hsmmc_getwp, +#endif +}; +#else static const struct mmc_ops omap_hsmmc_ops = { .send_cmd = omap_hsmmc_send_cmd, .set_ios = omap_hsmmc_set_ios, @@ -683,6 +707,7 @@ static const struct mmc_ops omap_hsmmc_ops = { .getwp = omap_hsmmc_getwp, #endif }; +#endif #ifndef CONFIG_DM_MMC int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, @@ -835,7 +860,6 @@ static int omap_hsmmc_probe(struct udevice *dev) struct mmc *mmc; cfg->name = "OMAP SD/MMC"; - cfg->ops = &omap_hsmmc_ops; priv->base_addr = plat->base_addr; #ifdef OMAP_HSMMC_USE_GPIO priv->cd_inverted = plat->cd_inverted; @@ -857,7 +881,7 @@ static int omap_hsmmc_probe(struct udevice *dev) mmc->dev = dev; upriv->mmc = mmc; - return 0; + return omap_hsmmc_init_setup(mmc); } #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) @@ -901,6 +925,7 @@ U_BOOT_DRIVER(omap_hsmmc) = { #ifdef CONFIG_BLK .bind = omap_hsmmc_bind, #endif + .ops = &omap_hsmmc_ops, .probe = omap_hsmmc_probe, .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data), .flags = DM_FLAG_PRE_RELOC, diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index e39b476834..6db89779ba 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -6,37 +6,71 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <malloc.h> +#include <mapmem.h> #include <sdhci.h> #include <asm/pci.h> -int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported) +struct pci_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct pci_mmc_priv { + struct sdhci_host host; + void *base; +}; + +static int pci_mmc_probe(struct udevice *dev) { - struct sdhci_host *mmc_host; - u32 iobase; + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct pci_mmc_plat *plat = dev_get_platdata(dev); + struct pci_mmc_priv *priv = dev_get_priv(dev); + struct sdhci_host *host = &priv->host; + u32 ioaddr; int ret; - int i; - - for (i = 0; ; i++) { - struct udevice *dev; - - ret = pci_find_device_id(mmc_supported, i, &dev); - if (ret) - return ret; - mmc_host = malloc(sizeof(struct sdhci_host)); - if (!mmc_host) - return -ENOMEM; - - mmc_host->name = name; - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); - mmc_host->ioaddr = (void *)(ulong)iobase; - mmc_host->quirks = 0; - mmc_host->max_clk = 0; - ret = add_sdhci(mmc_host, 0, 0); - if (ret) - return ret; - } - - return 0; + + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &ioaddr); + host->ioaddr = map_sysmem(ioaddr, 0); + host->name = dev->name; + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + if (ret) + return ret; + host->mmc = &plat->mmc; + host->mmc->priv = &priv->host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + return sdhci_probe(dev); } + +static int pci_mmc_bind(struct udevice *dev) +{ + struct pci_mmc_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +U_BOOT_DRIVER(pci_mmc) = { + .name = "pci_mmc", + .id = UCLASS_MMC, + .bind = pci_mmc_bind, + .probe = pci_mmc_probe, + .ops = &sdhci_ops, + .priv_auto_alloc_size = sizeof(struct pci_mmc_priv), + .platdata_auto_alloc_size = sizeof(struct pci_mmc_plat), +}; + +static struct pci_device_id mmc_supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1) }, + {}, +}; + +U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported); diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index 2253bbc518..dc86d108a6 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -7,8 +7,10 @@ #include <common.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/sizes.h> #include <dm/device.h> +#include <libfdt.h> #include <mmc.h> #include <sdhci.h> @@ -17,7 +19,7 @@ #define SDHCI_CDNS_HRS04_ACK BIT(26) #define SDHCI_CDNS_HRS04_RD BIT(25) #define SDHCI_CDNS_HRS04_WR BIT(24) -#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12 +#define SDHCI_CDNS_HRS04_RDATA_SHIFT 16 #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 @@ -34,6 +36,9 @@ #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 +#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b +#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c +#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d struct sdhci_cdns_plat { struct mmc_config cfg; @@ -41,11 +46,31 @@ struct sdhci_cdns_plat { void __iomem *hrs_addr; }; -static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, - u8 addr, u8 data) +struct sdhci_cdns_phy_cfg { + const char *property; + u8 addr; +}; + +static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { + { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, + { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, + { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, }, + { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, }, + { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, }, + { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, }, + { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, }, + { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, }, + { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, }, + { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, }, + { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, +}; + +static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, + u8 addr, u8 data) { void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04; u32 tmp; + int ret; tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); @@ -54,17 +79,36 @@ static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, tmp |= SDHCI_CDNS_HRS04_WR; writel(tmp, reg); + ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10); + if (ret) + return ret; + tmp &= ~SDHCI_CDNS_HRS04_WR; writel(tmp, reg); + + return 0; } -static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat) +static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat, + const void *fdt, int nodeoffset) { - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2); - sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3); + const u32 *prop; + int ret, i; + + for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) { + prop = fdt_getprop(fdt, nodeoffset, + sdhci_cdns_phy_cfgs[i].property, NULL); + if (!prop) + continue; + + ret = sdhci_cdns_write_phy_reg(plat, + sdhci_cdns_phy_cfgs[i].addr, + fdt32_to_cpu(*prop)); + if (ret) + return ret; + } + + return 0; } static int sdhci_cdns_bind(struct udevice *dev) @@ -76,6 +120,7 @@ static int sdhci_cdns_bind(struct udevice *dev) static int sdhci_cdns_probe(struct udevice *dev) { + DECLARE_GLOBAL_DATA_PTR; struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_cdns_plat *plat = dev_get_platdata(dev); struct sdhci_host *host = dev_get_priv(dev); @@ -94,7 +139,9 @@ static int sdhci_cdns_probe(struct udevice *dev) host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; - sdhci_cdns_phy_init(plat); + ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev->of_offset); + if (ret) + return ret; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index b745977b3f..161a6b1399 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -332,8 +332,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) */ if (host->clk_mul) { for (div = 1; div <= 1024; div++) { - if ((host->max_clk * host->clk_mul / div) - <= clock) + if ((host->max_clk / div) <= clock) break; } @@ -547,6 +546,14 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, #ifndef CONFIG_DM_MMC_OPS cfg->ops = &sdhci_ops; #endif + + /* Check whether the clock multiplier is supported or not */ + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> + SDHCI_CLOCK_MUL_SHIFT; + } + if (host->max_clk == 0) { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> @@ -555,6 +562,8 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; host->max_clk *= 1000000; + if (host->clk_mul) + host->max_clk *= host->clk_mul; } if (host->max_clk == 0) { printf("%s: Hardware doesn't specify base clock frequency\n", @@ -590,11 +599,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { if (!(caps & SDHCI_CAN_DO_8BIT)) cfg->host_caps &= ~MMC_MODE_8BIT; - - /* Find out whether clock multiplier is supported */ - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); - host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> - SDHCI_CLOCK_MUL_SHIFT; } if (host->host_caps) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 9cd0d94cbd..d49bf572f8 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -123,6 +123,11 @@ config FEC_MXC This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. +config FTMAC100 + bool "Ftmac100 Ethernet Support" + help + This MAC is present in Andestech SoCs. + config MVPP2 bool "Marvell Armada 375/7K/8K network interface support" depends on ARMADA_375 || ARMADA_8K @@ -225,4 +230,12 @@ config GMAC_ROCKCHIP This driver provides Rockchip SoCs network support based on the Synopsys Designware driver. +config RENESAS_RAVB + bool "Renesas Ethernet AVB MAC" + depends on DM_ETH && RCAR_GEN3 + select PHYLIB + help + This driver implements support for the Ethernet AVB block in + Renesas M3 and H3 SoCs. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index aedb2cc90d..0aaac6bd81 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_RTL8169) += rtl8169.o obj-$(CONFIG_ETH_SANDBOX) += sandbox.o obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o obj-$(CONFIG_SH_ETHER) += sh_eth.o +obj-$(CONFIG_RENESAS_RAVB) += ravb.o obj-$(CONFIG_SMC91111) += smc91111.o obj-$(CONFIG_SMC911X) += smc911x.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 910879ba3e..08bea8b052 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -563,7 +563,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register for i.MX6UL */ - if (!is_mx6ul()) { + if (!is_mx6ul() && !is_mx6ull()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i); @@ -1023,6 +1023,7 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, struct eth_device *edev; struct fec_priv *fec; unsigned char ethaddr[6]; + char mac[16]; uint32_t start; int ret = 0; @@ -1085,12 +1086,18 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, fec->phy_id = phy_id; #endif eth_register(edev); + /* only support one eth device, the index number pointed by dev_id */ + edev->index = fec->dev_id; - if (fec_get_hwaddr(dev_id, ethaddr) == 0) { - debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); + if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) { + debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); - if (!getenv("ethaddr")) - eth_setenv_enetaddr("ethaddr", ethaddr); + if (fec->dev_id) + sprintf(mac, "eth%daddr", fec->dev_id); + else + strcpy(mac, "ethaddr"); + if (!getenv(mac)) + eth_setenv_enetaddr(mac, ethaddr); } return ret; err4: diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 1fc7da9a3e..b79c467e69 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -11,24 +11,29 @@ #include <common.h> #include <malloc.h> #include <net.h> -#include <asm/io.h> +#include <linux/io.h> #include "ftmac100.h" - +#ifdef CONFIG_DM_ETH +#include <dm.h> +DECLARE_GLOBAL_DATA_PTR; +#endif #define ETH_ZLEN 60 struct ftmac100_data { struct ftmac100_txdes txdes[1]; struct ftmac100_rxdes rxdes[PKTBUFSRX]; int rx_index; + const char *name; + phys_addr_t iobase; }; /* * Reset MAC */ -static void ftmac100_reset (struct eth_device *dev) +static void ftmac100_reset(struct ftmac100_data *priv) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; debug ("%s()\n", __func__); @@ -41,9 +46,10 @@ static void ftmac100_reset (struct eth_device *dev) /* * Set MAC address */ -static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac) +static void ftmac100_set_mac(struct ftmac100_data *priv , + const unsigned char *mac) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; unsigned int maddr = mac[0] << 8 | mac[1]; unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; @@ -53,29 +59,22 @@ static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac) writel (laddr, &ftmac100->mac_ladr); } -static void ftmac100_set_mac_from_env (struct eth_device *dev) -{ - eth_getenv_enetaddr ("ethaddr", dev->enetaddr); - - ftmac100_set_mac (dev, dev->enetaddr); -} - /* - * disable transmitter, receiver + * Disable MAC */ -static void ftmac100_halt (struct eth_device *dev) +static void _ftmac100_halt(struct ftmac100_data *priv) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; - + struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; debug ("%s()\n", __func__); - writel (0, &ftmac100->maccr); } -static int ftmac100_init (struct eth_device *dev, bd_t *bd) +/* + * Initialize MAC + */ +static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6]) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; - struct ftmac100_data *priv = dev->priv; + struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; struct ftmac100_txdes *txdes = priv->txdes; struct ftmac100_rxdes *rxdes = priv->rxdes; unsigned int maccr; @@ -83,11 +82,11 @@ static int ftmac100_init (struct eth_device *dev, bd_t *bd) debug ("%s()\n", __func__); - ftmac100_reset (dev); + ftmac100_reset(priv); /* set the ethernet address */ + ftmac100_set_mac(priv, enetaddr); - ftmac100_set_mac_from_env (dev); /* disable all interrupts */ @@ -136,25 +135,37 @@ static int ftmac100_init (struct eth_device *dev, bd_t *bd) } /* - * Get a data block via Ethernet + * Free receiving buffer */ -static int ftmac100_recv (struct eth_device *dev) +static int _ftmac100_free_pkt(struct ftmac100_data *priv) +{ + struct ftmac100_rxdes *curr_des; + curr_des = &priv->rxdes[priv->rx_index]; + /* release buffer to DMA */ + curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN; + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + return 0; +} + +/* + * Receive a data block via Ethernet + */ +static int __ftmac100_recv(struct ftmac100_data *priv) { - struct ftmac100_data *priv = dev->priv; struct ftmac100_rxdes *curr_des; unsigned short rxlen; curr_des = &priv->rxdes[priv->rx_index]; if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN) - return -1; + return 0; if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR | FTMAC100_RXDES0_CRC_ERR | FTMAC100_RXDES0_FTL | FTMAC100_RXDES0_RUNT | FTMAC100_RXDES0_RX_ODD_NB)) { - return -1; + return 0; } rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0); @@ -162,26 +173,15 @@ static int ftmac100_recv (struct eth_device *dev) debug ("%s(): RX buffer %d, %x received\n", __func__, priv->rx_index, rxlen); - /* pass the packet up to the protocol layers. */ - - net_process_received_packet((void *)curr_des->rxdes2, rxlen); - - /* release buffer to DMA */ - - curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN; - - priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; - - return 0; + return rxlen; } /* * Send a data block via Ethernet */ -static int ftmac100_send(struct eth_device *dev, void *packet, int length) +static int _ftmac100_send(struct ftmac100_data *priv, void *packet, int length) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; - struct ftmac100_data *priv = dev->priv; + struct ftmac100 *ftmac100 = (struct ftmac100 *)priv->iobase; struct ftmac100_txdes *curr_des = priv->txdes; ulong start; @@ -224,25 +224,69 @@ static int ftmac100_send(struct eth_device *dev, void *packet, int length) return 0; } +#ifndef CONFIG_DM_ETH +/* + * disable transmitter, receiver + */ +static void ftmac100_halt(struct eth_device *dev) +{ + struct ftmac100_data *priv = dev->priv; + return _ftmac100_halt(priv); +} + +static int ftmac100_init(struct eth_device *dev, bd_t *bd) +{ + struct ftmac100_data *priv = dev->priv; + return _ftmac100_init(priv , dev->enetaddr); +} + +static int _ftmac100_recv(struct ftmac100_data *priv) +{ + struct ftmac100_rxdes *curr_des; + unsigned short len; + curr_des = &priv->rxdes[priv->rx_index]; + len = __ftmac100_recv(priv); + if (len) { + /* pass the packet up to the protocol layers. */ + net_process_received_packet((void *)curr_des->rxdes2, len); + _ftmac100_free_pkt(priv); + } + return len ? 1 : 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftmac100_recv(struct eth_device *dev) +{ + struct ftmac100_data *priv = dev->priv; + return _ftmac100_recv(priv); +} + +/* + * Send a data block via Ethernet + */ +static int ftmac100_send(struct eth_device *dev, void *packet, int length) +{ + struct ftmac100_data *priv = dev->priv; + return _ftmac100_send(priv , packet , length); +} + int ftmac100_initialize (bd_t *bd) { struct eth_device *dev; struct ftmac100_data *priv; - dev = malloc (sizeof *dev); if (!dev) { printf ("%s(): failed to allocate dev\n", __func__); goto out; } - /* Transmit and receive descriptors should align to 16 bytes */ - priv = memalign (16, sizeof (struct ftmac100_data)); if (!priv) { printf ("%s(): failed to allocate priv\n", __func__); goto free_dev; } - memset (dev, 0, sizeof (*dev)); memset (priv, 0, sizeof (*priv)); @@ -253,7 +297,7 @@ int ftmac100_initialize (bd_t *bd) dev->send = ftmac100_send; dev->recv = ftmac100_recv; dev->priv = priv; - + priv->iobase = dev->iobase; eth_register (dev); return 1; @@ -263,3 +307,135 @@ free_dev: out: return 0; } +#endif + +#ifdef CONFIG_DM_ETH +static int ftmac100_start(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct ftmac100_data *priv = dev_get_priv(dev); + + return _ftmac100_init(priv, plat->enetaddr); +} + +static void ftmac100_stop(struct udevice *dev) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + _ftmac100_halt(priv); +} + +static int ftmac100_send(struct udevice *dev, void *packet, int length) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + int ret; + ret = _ftmac100_send(priv , packet , length); + return ret ? 0 : -ETIMEDOUT; +} + +static int ftmac100_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + struct ftmac100_rxdes *curr_des; + curr_des = &priv->rxdes[priv->rx_index]; + int len; + len = __ftmac100_recv(priv); + if (len) + *packetp = (void *)curr_des->rxdes2; + + return len ? len : -EAGAIN; +} + +static int ftmac100_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + _ftmac100_free_pkt(priv); + return 0; +} + +int ftmac100_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + eth_getenv_enetaddr("ethaddr", pdata->enetaddr); + return 0; +} + +static const char *dtbmacaddr(u32 ifno) +{ + int node, len; + char enet[16]; + const char *mac; + const char *path; + if (gd->fdt_blob == NULL) { + printf("%s: don't have a valid gd->fdt_blob!\n", __func__); + return NULL; + } + node = fdt_path_offset(gd->fdt_blob, "/aliases"); + if (node < 0) + return NULL; + + sprintf(enet, "ethernet%d", ifno); + path = fdt_getprop(gd->fdt_blob, node, enet, NULL); + if (!path) { + printf("no alias for %s\n", enet); + return NULL; + } + node = fdt_path_offset(gd->fdt_blob, path); + mac = fdt_getprop(gd->fdt_blob, node, "mac-address", &len); + if (mac && is_valid_ethaddr((u8 *)mac)) + return mac; + + return NULL; +} + +static int ftmac100_ofdata_to_platdata(struct udevice *dev) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *mac; + pdata->iobase = dev_get_addr(dev); + priv->iobase = pdata->iobase; + mac = dtbmacaddr(0); + if (mac) + memcpy(pdata->enetaddr , mac , 6); + + return 0; +} + +static int ftmac100_probe(struct udevice *dev) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + priv->name = dev->name; + return 0; +} + +static int ftmac100_bind(struct udevice *dev) +{ + return device_set_name(dev, dev->name); +} + +static const struct eth_ops ftmac100_ops = { + .start = ftmac100_start, + .send = ftmac100_send, + .recv = ftmac100_recv, + .stop = ftmac100_stop, + .free_pkt = ftmac100_free_pkt, +}; + +static const struct udevice_id ftmac100_ids[] = { + { .compatible = "andestech,atmac100" }, + { } +}; + +U_BOOT_DRIVER(ftmac100) = { + .name = "nds32_mac", + .id = UCLASS_ETH, + .of_match = ftmac100_ids, + .bind = ftmac100_bind, + .ofdata_to_platdata = ftmac100_ofdata_to_platdata, + .probe = ftmac100_probe, + .ops = &ftmac100_ops, + .priv_auto_alloc_size = sizeof(struct ftmac100_data), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c new file mode 100644 index 0000000000..ab45a31d6a --- /dev/null +++ b/drivers/net/ravb.c @@ -0,0 +1,601 @@ +/* + * drivers/net/ravb.c + * This file is driver for Renesas Ethernet AVB. + * + * Copyright (C) 2015-2017 Renesas Electronics Corporation + * + * Based on the SuperH Ethernet driver. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <miiphy.h> +#include <malloc.h> +#include <linux/mii.h> +#include <wait_bit.h> +#include <asm/io.h> + +/* Registers */ +#define RAVB_REG_CCC 0x000 +#define RAVB_REG_DBAT 0x004 +#define RAVB_REG_CSR 0x00C +#define RAVB_REG_APSR 0x08C +#define RAVB_REG_RCR 0x090 +#define RAVB_REG_TGC 0x300 +#define RAVB_REG_TCCR 0x304 +#define RAVB_REG_RIC0 0x360 +#define RAVB_REG_RIC1 0x368 +#define RAVB_REG_RIC2 0x370 +#define RAVB_REG_TIC 0x378 +#define RAVB_REG_ECMR 0x500 +#define RAVB_REG_RFLR 0x508 +#define RAVB_REG_ECSIPR 0x518 +#define RAVB_REG_PIR 0x520 +#define RAVB_REG_GECMR 0x5b0 +#define RAVB_REG_MAHR 0x5c0 +#define RAVB_REG_MALR 0x5c8 + +#define CCC_OPC_CONFIG BIT(0) +#define CCC_OPC_OPERATION BIT(1) +#define CCC_BOC BIT(20) + +#define CSR_OPS 0x0000000F +#define CSR_OPS_CONFIG BIT(1) + +#define TCCR_TSRQ0 BIT(0) + +#define RFLR_RFL_MIN 0x05EE + +#define PIR_MDI BIT(3) +#define PIR_MDO BIT(2) +#define PIR_MMD BIT(1) +#define PIR_MDC BIT(0) + +#define ECMR_TRCCM BIT(26) +#define ECMR_RZPF BIT(20) +#define ECMR_PFR BIT(18) +#define ECMR_RXF BIT(17) +#define ECMR_RE BIT(6) +#define ECMR_TE BIT(5) +#define ECMR_DM BIT(1) +#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF) + +/* DMA Descriptors */ +#define RAVB_NUM_BASE_DESC 16 +#define RAVB_NUM_TX_DESC 8 +#define RAVB_NUM_RX_DESC 8 + +#define RAVB_TX_QUEUE_OFFSET 0 +#define RAVB_RX_QUEUE_OFFSET 4 + +#define RAVB_DESC_DT(n) ((n) << 28) +#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7) +#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9) +#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa) +#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc) +#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3) +#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf) + +#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0) +#define RAVB_DESC_DS_MASK 0xfff + +#define RAVB_RX_DESC_MSC_MC BIT(23) +#define RAVB_RX_DESC_MSC_CEEF BIT(22) +#define RAVB_RX_DESC_MSC_CRL BIT(21) +#define RAVB_RX_DESC_MSC_FRE BIT(20) +#define RAVB_RX_DESC_MSC_RTLF BIT(19) +#define RAVB_RX_DESC_MSC_RTSF BIT(18) +#define RAVB_RX_DESC_MSC_RFE BIT(17) +#define RAVB_RX_DESC_MSC_CRC BIT(16) +#define RAVB_RX_DESC_MSC_MASK (0xff << 16) + +#define RAVB_RX_DESC_MSC_RX_ERR_MASK \ + (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \ + RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF) + +#define RAVB_TX_TIMEOUT_MS 1000 + +struct ravb_desc { + u32 ctrl; + u32 dptr; +}; + +struct ravb_rxdesc { + struct ravb_desc data; + struct ravb_desc link; + u8 __pad[48]; + u8 packet[PKTSIZE_ALIGN]; +}; + +struct ravb_priv { + struct ravb_desc base_desc[RAVB_NUM_BASE_DESC]; + struct ravb_desc tx_desc[RAVB_NUM_TX_DESC]; + struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC]; + u32 rx_desc_idx; + u32 tx_desc_idx; + + struct phy_device *phydev; + struct mii_dev *bus; + void __iomem *iobase; +}; + +static inline void ravb_flush_dcache(u32 addr, u32 len) +{ + flush_dcache_range(addr, addr + len); +} + +static inline void ravb_invalidate_dcache(u32 addr, u32 len) +{ + u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1); + u32 end = roundup(addr + len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); +} + +static int ravb_send(struct udevice *dev, void *packet, int len) +{ + struct ravb_priv *eth = dev_get_priv(dev); + struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx]; + unsigned int start; + + /* Update TX descriptor */ + ravb_flush_dcache((uintptr_t)packet, len); + memset(desc, 0x0, sizeof(*desc)); + desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len); + desc->dptr = (uintptr_t)packet; + ravb_flush_dcache((uintptr_t)desc, sizeof(*desc)); + + /* Restart the transmitter if disabled */ + if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0)) + setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0); + + /* Wait until packet is transmitted */ + start = get_timer(0); + while (get_timer(start) < RAVB_TX_TIMEOUT_MS) { + ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); + if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE) + break; + udelay(10); + }; + + if (get_timer(start) >= RAVB_TX_TIMEOUT_MS) + return -ETIMEDOUT; + + eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1); + return 0; +} + +static int ravb_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ravb_priv *eth = dev_get_priv(dev); + struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx]; + int len; + u8 *packet; + + /* Check if the rx descriptor is ready */ + ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); + if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY) + return -EAGAIN; + + /* Check for errors */ + if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) { + desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK; + return -EAGAIN; + } + + len = desc->data.ctrl & RAVB_DESC_DS_MASK; + packet = (u8 *)(uintptr_t)desc->data.dptr; + ravb_invalidate_dcache((uintptr_t)packet, len); + + *packetp = packet; + return len; +} + +static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct ravb_priv *eth = dev_get_priv(dev); + struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx]; + + /* Make current descriptor available again */ + desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN); + ravb_flush_dcache((uintptr_t)desc, sizeof(*desc)); + + /* Point to the next descriptor */ + eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC; + desc = ð->rx_desc[eth->rx_desc_idx]; + ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); + + return 0; +} + +static int ravb_reset(struct udevice *dev) +{ + struct ravb_priv *eth = dev_get_priv(dev); + + /* Set config mode */ + writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC); + + /* Check the operating mode is changed to the config mode. */ + return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR, + CSR_OPS_CONFIG, true, 100, true); +} + +static void ravb_base_desc_init(struct ravb_priv *eth) +{ + const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc); + int i; + + /* Initialize all descriptors */ + memset(eth->base_desc, 0x0, desc_size); + + for (i = 0; i < RAVB_NUM_BASE_DESC; i++) + eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS; + + ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size); + + /* Register the descriptor base address table */ + writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT); +} + +static void ravb_tx_desc_init(struct ravb_priv *eth) +{ + const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc); + int i; + + /* Initialize all descriptors */ + memset(eth->tx_desc, 0x0, desc_size); + eth->tx_desc_idx = 0; + + for (i = 0; i < RAVB_NUM_TX_DESC; i++) + eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY; + + /* Mark the end of the descriptors */ + eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX; + eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc; + ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size); + + /* Point the controller to the TX descriptor list. */ + eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX; + eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc; + ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET], + sizeof(struct ravb_desc)); +} + +static void ravb_rx_desc_init(struct ravb_priv *eth) +{ + const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc); + int i; + + /* Initialize all descriptors */ + memset(eth->rx_desc, 0x0, desc_size); + eth->rx_desc_idx = 0; + + for (i = 0; i < RAVB_NUM_RX_DESC; i++) { + eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY | + RAVB_DESC_DS(PKTSIZE_ALIGN); + eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet; + + eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX; + eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1]; + } + + /* Mark the end of the descriptors */ + eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX; + eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc; + ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size); + + /* Point the controller to the rx descriptor list */ + eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX; + eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc; + ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET], + sizeof(struct ravb_desc)); +} + +static int ravb_phy_config(struct udevice *dev) +{ + struct ravb_priv *eth = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct phy_device *phydev; + int reg; + + phydev = phy_connect(eth->bus, pdata->phy_interface, + dev, PHY_INTERFACE_MODE_RGMII_ID); + if (!phydev) + return -ENODEV; + + eth->phydev = phydev; + + /* 10BASE is not supported for Ethernet AVB MAC */ + phydev->supported &= ~(SUPPORTED_10baseT_Full + | SUPPORTED_10baseT_Half); + if (pdata->max_speed != 1000) { + phydev->supported &= ~(SUPPORTED_1000baseT_Half + | SUPPORTED_1000baseT_Full); + reg = phy_read(phydev, -1, MII_CTRL1000); + reg &= ~(BIT(9) | BIT(8)); + phy_write(phydev, -1, MII_CTRL1000, reg); + } + + phy_config(phydev); + + return 0; +} + +/* Set Mac address */ +static int ravb_write_hwaddr(struct udevice *dev) +{ + struct ravb_priv *eth = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + unsigned char *mac = pdata->enetaddr; + + writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3], + eth->iobase + RAVB_REG_MAHR); + + writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR); + + return 0; +} + +/* E-MAC init function */ +static int ravb_mac_init(struct ravb_priv *eth) +{ + /* Disable MAC Interrupt */ + writel(0, eth->iobase + RAVB_REG_ECSIPR); + + /* Recv frame limit set register */ + writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR); + + return 0; +} + +/* AVB-DMAC init function */ +static int ravb_dmac_init(struct udevice *dev) +{ + struct ravb_priv *eth = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + int ret = 0; + + /* Set CONFIG mode */ + ret = ravb_reset(dev); + if (ret) + return ret; + + /* Disable all interrupts */ + writel(0, eth->iobase + RAVB_REG_RIC0); + writel(0, eth->iobase + RAVB_REG_RIC1); + writel(0, eth->iobase + RAVB_REG_RIC2); + writel(0, eth->iobase + RAVB_REG_TIC); + + /* Set little endian */ + clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC); + + /* AVB rx set */ + writel(0x18000001, eth->iobase + RAVB_REG_RCR); + + /* FIFO size set */ + writel(0x00222210, eth->iobase + RAVB_REG_TGC); + + /* Delay CLK: 2ns */ + if (pdata->max_speed == 1000) + writel(BIT(14), eth->iobase + RAVB_REG_APSR); + + return 0; +} + +static int ravb_config(struct udevice *dev) +{ + struct ravb_priv *eth = dev_get_priv(dev); + struct phy_device *phy; + u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE; + int ret; + + /* Configure AVB-DMAC register */ + ravb_dmac_init(dev); + + /* Configure E-MAC registers */ + ravb_mac_init(eth); + ravb_write_hwaddr(dev); + + /* Configure phy */ + ret = ravb_phy_config(dev); + if (ret) + return ret; + + phy = eth->phydev; + + ret = phy_startup(phy); + if (ret) + return ret; + + /* Set the transfer speed */ + if (phy->speed == 100) + writel(0, eth->iobase + RAVB_REG_GECMR); + else if (phy->speed == 1000) + writel(1, eth->iobase + RAVB_REG_GECMR); + + /* Check if full duplex mode is supported by the phy */ + if (phy->duplex) + mask |= ECMR_DM; + + writel(mask, eth->iobase + RAVB_REG_ECMR); + + phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19); + + return 0; +} + +int ravb_start(struct udevice *dev) +{ + struct ravb_priv *eth = dev_get_priv(dev); + int ret; + + ret = ravb_reset(dev); + if (ret) + return ret; + + ravb_base_desc_init(eth); + ravb_tx_desc_init(eth); + ravb_rx_desc_init(eth); + + ret = ravb_config(dev); + if (ret) + return ret; + + /* Setting the control will start the AVB-DMAC process. */ + writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC); + + return 0; +} + +static void ravb_stop(struct udevice *dev) +{ + ravb_reset(dev); +} + +static int ravb_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ravb_priv *eth = dev_get_priv(dev); + struct mii_dev *mdiodev; + void __iomem *iobase; + int ret; + + iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE); + eth->iobase = iobase; + + mdiodev = mdio_alloc(); + if (!mdiodev) { + ret = -ENOMEM; + goto err_mdio_alloc; + } + + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + bb_miiphy_buses[0].priv = eth; + snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name); + + ret = mdio_register(mdiodev); + if (ret < 0) + goto err_mdio_register; + + eth->bus = miiphy_get_dev_by_name(dev->name); + + return 0; + +err_mdio_register: + mdio_free(mdiodev); +err_mdio_alloc: + unmap_physmem(eth->iobase, MAP_NOCACHE); + return ret; +} + +static int ravb_remove(struct udevice *dev) +{ + struct ravb_priv *eth = dev_get_priv(dev); + + free(eth->phydev); + mdio_unregister(eth->bus); + mdio_free(eth->bus); + unmap_physmem(eth->iobase, MAP_NOCACHE); + + return 0; +} + +int ravb_bb_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct ravb_priv *eth = bus->priv; + + setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); + + return 0; +} + +int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct ravb_priv *eth = bus->priv; + + clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); + + return 0; +} + +int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct ravb_priv *eth = bus->priv; + + if (v) + setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); + else + clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); + + return 0; +} + +int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct ravb_priv *eth = bus->priv; + + *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3; + + return 0; +} + +int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct ravb_priv *eth = bus->priv; + + if (v) + setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); + else + clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); + + return 0; +} + +int ravb_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(10); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "ravb", + .init = ravb_bb_init, + .mdio_active = ravb_bb_mdio_active, + .mdio_tristate = ravb_bb_mdio_tristate, + .set_mdio = ravb_bb_set_mdio, + .get_mdio = ravb_bb_get_mdio, + .set_mdc = ravb_bb_set_mdc, + .delay = ravb_bb_delay, + }, +}; +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); + +static const struct eth_ops ravb_ops = { + .start = ravb_start, + .send = ravb_send, + .recv = ravb_recv, + .free_pkt = ravb_free_pkt, + .stop = ravb_stop, + .write_hwaddr = ravb_write_hwaddr, +}; + +U_BOOT_DRIVER(eth_ravb) = { + .name = "ravb", + .id = UCLASS_ETH, + .probe = ravb_probe, + .remove = ravb_remove, + .ops = &ravb_ops, + .priv_auto_alloc_size = sizeof(struct ravb_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 57204c4f3f..75fb093337 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -35,8 +35,22 @@ #include <video_fb.h> #include <linux/screen_info.h> +#ifdef CONFIG_X86 +#include <asm/acpi_s3.h> +DECLARE_GLOBAL_DATA_PTR; +#endif + __weak bool board_should_run_oprom(struct udevice *dev) { +#if defined(CONFIG_X86) && defined(CONFIG_HAVE_ACPI_RESUME) + if (gd->arch.prev_sleep_state == ACPI_S3) { + if (IS_ENABLED(CONFIG_S3_VGA_ROM_RUN)) + return true; + else + return false; + } +#endif + return true; } diff --git a/drivers/pcmcia/marubun_pcmcia.c b/drivers/pcmcia/marubun_pcmcia.c index afd6df6440..739d7545da 100644 --- a/drivers/pcmcia/marubun_pcmcia.c +++ b/drivers/pcmcia/marubun_pcmcia.c @@ -17,7 +17,7 @@ #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) #define CONFIG_PCMCIA #endif diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index 1b41e39158..dae5560f8c 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -9,7 +9,7 @@ #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c index 45dcb54d71..edff50f630 100644 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ b/drivers/pcmcia/tqm8xx_pcmcia.c @@ -15,7 +15,7 @@ #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index f0321c4057..ebc14a31f1 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -53,6 +53,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins", pin_data, size >> 2)) { dev_err(dev, "Error reading pin data.\n"); + devm_kfree(dev, pin_data); return -EINVAL; } @@ -78,6 +79,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) if ((mux_reg == -1) || (conf_reg == -1)) { dev_err(dev, "Error mux_reg or conf_reg\n"); + devm_kfree(dev, pin_data); return -EINVAL; } @@ -166,6 +168,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) } } + devm_kfree(dev, pin_data); + return 0; } diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index a7d56e605d..d8c107e206 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -311,6 +311,7 @@ config SY8106A_VOUT1_VOLT config TWL4030_POWER depends on OMAP34XX bool "Enable driver for TI TWL4030 power management chip" + imply CMD_POWEROFF ---help--- The TWL4030 in a combination audio CODEC/power management with GPIO and it is commonly used with the OMAP3 family of processors diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 87c3d9cae2..438681da7a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_RTC_PCF2127) += pcf2127.o obj-$(CONFIG_RTC_PL031) += pl031.o obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o -obj-$(CONFIG_RTC_RTC4543) += rtc4543.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o diff --git a/drivers/rtc/rtc4543.c b/drivers/rtc/rtc4543.c deleted file mode 100644 index 8d36edd65a..0000000000 --- a/drivers/rtc/rtc4543.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2008, 2009 - * Andreas Pfefferle, DENX Software Engineering, ap@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include <common.h> -#include <command.h> -#include <config.h> -#include <rtc.h> -#include <tws.h> - -#if defined(CONFIG_CMD_DATE) - -/* - * Note: The acrobatics below is due to the hideously ingenius idea of - * the chip designers. As the chip does not allow register - * addressing, all values need to be read and written in one go. Sure - * enough, the 'wday' field (0-6) is transferred using the economic - * number of 4 bits right in the middle of the packet..... - */ - -int rtc_get(struct rtc_time *tm) -{ - int rel = 0; - uchar buffer[7]; - - memset(buffer, 0, 7); - - /* Read 52 bits into our buffer */ - tws_read(buffer, 52); - - tm->tm_sec = bcd2bin( buffer[0] & 0x7F); - tm->tm_min = bcd2bin( buffer[1] & 0x7F); - tm->tm_hour = bcd2bin( buffer[2] & 0x3F); - tm->tm_wday = bcd2bin( buffer[3] & 0x07); - tm->tm_mday = bcd2bin((buffer[3] & 0xF0) >> 4 | (buffer[4] & 0x0F) << 4); - tm->tm_mon = bcd2bin((buffer[4] & 0x30) >> 4 | (buffer[5] & 0x0F) << 4); - tm->tm_year = bcd2bin((buffer[5] & 0xF0) >> 4 | (buffer[6] & 0x0F) << 4) + 2000; - tm->tm_yday = 0; - tm->tm_isdst = 0; - - if (tm->tm_sec & 0x80) { - puts("### Warning: RTC Low Voltage - date/time not reliable\n"); - rel = -1; - } - - debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, - tm->tm_hour, tm->tm_min, tm->tm_sec); - - return rel; -} - -int rtc_set(struct rtc_time *tm) -{ - uchar buffer[7]; - uchar tmp; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, - tm->tm_hour, tm->tm_min, tm->tm_sec); - - memset(buffer, 0, 7); - buffer[0] = bin2bcd(tm->tm_sec); - buffer[1] = bin2bcd(tm->tm_min); - buffer[2] = bin2bcd(tm->tm_hour); - buffer[3] = bin2bcd(tm->tm_wday); - tmp = bin2bcd(tm->tm_mday); - buffer[3] |= (tmp & 0x0F) << 4; - buffer[4] = (tmp & 0xF0) >> 4; - tmp = bin2bcd(tm->tm_mon); - buffer[4] |= (tmp & 0x0F) << 4; - buffer[5] = (tmp & 0xF0) >> 4; - tmp = bin2bcd(tm->tm_year % 100); - buffer[5] |= (tmp & 0x0F) << 4; - buffer[6] = (tmp & 0xF0) >> 4; - - /* Write the resulting 52 bits to device */ - tws_write(buffer, 52); - - return 0; -} - -void rtc_reset(void) -{ - struct rtc_time tmp; - - tmp.tm_sec = 0; - tmp.tm_min = 0; - tmp.tm_hour = 0; - tmp.tm_wday = 4; - tmp.tm_mday = 1; - tmp.tm_mon = 1; - tmp.tm_year = 2000; - rtc_set(&tmp); -} - -#endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index ca55df78b7..0eb7c02561 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -175,21 +175,17 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) +#if defined(CONFIG_ARCH_OMAP2PLUS) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif serial_out(UART_MCRVAL, &com_port->mcr); serial_out(ns16550_getfcr(com_port), &com_port->fcr); if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); -#if defined(CONFIG_OMAP) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ - defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) - +#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); -#endif /* CONFIG_OMAP */ +#endif #if defined(CONFIG_SOC_KEYSTONE) serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); #endif diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 43c028ebe6..c2b9c5f12f 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -349,7 +349,7 @@ static int serial_pre_remove(struct udevice *dev) #if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER) struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); - if (stdio_deregister_dev(upriv->sdev, 0)) + if (stdio_deregister_dev(upriv->sdev, true)) return -EPERM; #endif diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 348f544d0a..4d27122243 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -226,7 +226,8 @@ struct uart_port { # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) + defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) || \ + defined(CONFIG_R8A7796) # if defined(CONFIG_SCIF_A) # define SCIF_ORER 0x0200 # else diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f3f7dbe089..bef864f46e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -197,6 +197,12 @@ config OMAP3_SPI endif # if DM_SPI +config SOFT_SPI + bool "Soft SPI driver" + help + Enable Soft SPI driver. This driver is to use GPIO simulate + the SPI protocol. + config FSL_ESPI bool "Freescale eSPI driver" help diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 893fe33b66..bf2e99b5cc 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -617,6 +617,22 @@ static int ich_spi_probe(struct udevice *dev) return 0; } +static int ich_spi_remove(struct udevice *bus) +{ + struct ich_spi_priv *ctlr = dev_get_priv(bus); + + /* + * Configure SPI controller so that the Linux MTD driver can fully + * access the SPI NOR chip + */ + ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); + ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); + ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); + ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); + + return 0; +} + static int ich_spi_set_speed(struct udevice *bus, uint speed) { struct ich_spi_priv *priv = dev_get_priv(bus); @@ -700,4 +716,6 @@ U_BOOT_DRIVER(ich_spi) = { .priv_auto_alloc_size = sizeof(struct ich_spi_priv), .child_pre_probe = ich_spi_child_pre_probe, .probe = ich_spi_probe, + .remove = ich_spi_remove, + .flags = DM_FLAG_OS_PREPARE, }; diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h index bd0a820809..dcb8a9048f 100644 --- a/drivers/spi/ich.h +++ b/drivers/spi/ich.h @@ -102,13 +102,6 @@ enum { }; enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -enum { ICH_MAX_CMD_LEN = 5, }; @@ -124,8 +117,55 @@ struct spi_trans { uint32_t offset; }; +#define SPI_OPCODE_WRSR 0x01 +#define SPI_OPCODE_PAGE_PROGRAM 0x02 +#define SPI_OPCODE_READ 0x03 +#define SPI_OPCODE_WRDIS 0x04 +#define SPI_OPCODE_RDSR 0x05 #define SPI_OPCODE_WREN 0x06 #define SPI_OPCODE_FAST_READ 0x0b +#define SPI_OPCODE_ERASE_SECT 0x20 +#define SPI_OPCODE_READ_ID 0x9f +#define SPI_OPCODE_ERASE_BLOCK 0xd8 + +#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 +#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 +#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 +#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 + +#define SPI_OPMENU_0 SPI_OPCODE_WRSR +#define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS + +#define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM +#define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS + +#define SPI_OPMENU_2 SPI_OPCODE_READ +#define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS + +#define SPI_OPMENU_3 SPI_OPCODE_RDSR +#define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS + +#define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT +#define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS + +#define SPI_OPMENU_5 SPI_OPCODE_READ_ID +#define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS + +#define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK +#define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS + +#define SPI_OPMENU_7 SPI_OPCODE_FAST_READ +#define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS + +#define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN) +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) enum ich_version { ICHV_7, diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 76d376ac44..3caea151c5 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -568,7 +568,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, priv->freq = max_hz; priv->mode = mode; priv->wordlen = priv->slave.wordlen; -#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED +#if 0 + /* Please migrate to DM_SPI support for this feature. */ priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; #endif diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 0509094555..d137bfdca0 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -16,14 +16,16 @@ #include <dm.h> #include <errno.h> #include <malloc.h> +#include <linux/math64.h> #include <thermal.h> #include <imx_thermal.h> /* board will busyloop until this many degrees C below CPU max temperature */ #define TEMPERATURE_HOT_DELTA 5 /* CPU maxT - 5C */ #define FACTOR0 10000000 -#define FACTOR1 15976 -#define FACTOR2 4297157 +#define FACTOR1 15423 +#define FACTOR2 4148468 +#define OFFSET 3580661 #define MEASURE_FREQ 327 #define TEMPERATURE_MIN -40 #define TEMPERATURE_HOT 85 @@ -54,39 +56,43 @@ static int read_cpu_temperature(struct udevice *dev) struct thermal_data *priv = dev_get_priv(dev); u32 fuse = priv->fuse; int t1, n1; - u32 c1, c2; - u64 temp64; + s64 c1, c2; + s64 temp64; + s32 rem; /* * Sensor data layout: * [31:20] - sensor value @ 25C * We use universal formula now and only need sensor value @ 25C - * slope = 0.4297157 - (0.0015976 * 25C fuse) + * slope = 0.4445388 - (0.0016549 * 25C fuse) */ n1 = fuse >> 20; t1 = 25; /* t1 always 25C */ /* * Derived from linear interpolation: - * slope = 0.4297157 - (0.0015976 * 25C fuse) + * slope = 0.4445388 - (0.0016549 * 25C fuse) * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0 - * (Nmeas - n1) / (Tmeas - t1) = slope + * offset = 3.580661 + * offset = OFFSET / 1000000 + * (Nmeas - n1) / (Tmeas - t1 - offset) = slope * We want to reduce this down to the minimum computation necessary * for each temperature read. Also, we want Tmeas in millicelsius * and we don't want to lose precision from integer division. So... - * Tmeas = (Nmeas - n1) / slope + t1 - * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1 - * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1 - * Let constant c1 = (-1000 / slope) - * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1 - * Let constant c2 = n1 *c1 + 1000 * t1 - * milli_Tmeas = c2 - Nmeas * c1 + * Tmeas = (Nmeas - n1) / slope + t1 + offset + * milli_Tmeas = 1000000 * (Nmeas - n1) / slope + 1000000 * t1 + OFFSET + * milli_Tmeas = -1000000 * (n1 - Nmeas) / slope + 1000000 * t1 + OFFSET + * Let constant c1 = (-1000000 / slope) + * milli_Tmeas = (n1 - Nmeas) * c1 + 1000000 * t1 + OFFSET + * Let constant c2 = n1 *c1 + 1000000 * t1 + * milli_Tmeas = (c2 - Nmeas * c1) + OFFSET + * Tmeas = ((c2 - Nmeas * c1) + OFFSET) / 1000000 */ temp64 = FACTOR0; - temp64 *= 1000; - do_div(temp64, FACTOR1 * n1 - FACTOR2); + temp64 *= 1000000; + temp64 = div_s64_rem(temp64, FACTOR1 * n1 - FACTOR2, &rem); c1 = temp64; - c2 = n1 * c1 + 1000 * t1; + c2 = n1 * c1 + 1000000 * t1; /* * now we only use single measure, every time we read @@ -118,8 +124,8 @@ static int read_cpu_temperature(struct udevice *dev) >> TEMPSENSE0_TEMP_CNT_SHIFT; writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); - /* milli_Tmeas = c2 - Nmeas * c1 */ - temperature = (long)(c2 - n_meas * c1)/1000; + /* Tmeas = (c2 - Nmeas * c1 + OFFSET) / 1000000 */ + temperature = div_s64_rem(c2 - n_meas * c1 + OFFSET, 1000000, &rem); /* power down anatop thermal sensor */ writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index e03852396b..17e7dfe245 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -74,4 +74,16 @@ config ARC_TIMER usually at least one of them exists. Either of them is supported in U-Boot. +config AG101P_TIMER + bool "AG101P timer support" + depends on TIMER && NDS32 + help + Select this to enable a timer for AG01P devices. + +config AE3XX_TIMER + bool "AE3XX timer support" + depends on TIMER && NDS32 + help + Select this to enable a timer for AE3XX devices. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index bfe65fcb48..ced7bd66bd 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -12,3 +12,5 @@ obj-$(CONFIG_OMAP_TIMER) += omap-timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o +obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o +obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o diff --git a/drivers/timer/ae3xx_timer.c b/drivers/timer/ae3xx_timer.c new file mode 100644 index 0000000000..7ccb3eb446 --- /dev/null +++ b/drivers/timer/ae3xx_timer.c @@ -0,0 +1,117 @@ +/* + * Andestech ATCPIT100 timer driver + * + * (C) Copyright 2016 + * Rick Chen, NDS32 Software Engineering, rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define REG32_TMR(x) (*(unsigned long *) ((plat->regs) + (x>>2))) + +/* + * Definition of register offsets + */ + +/* ID and Revision Register */ +#define ID_REV 0x0 + +/* Configuration Register */ +#define CFG 0x10 + +/* Interrupt Enable Register */ +#define INT_EN 0x14 +#define CH_INT_EN(c , i) ((1<<i)<<(4*c)) + +/* Interrupt Status Register */ +#define INT_STA 0x18 +#define CH_INT_STA(c , i) ((1<<i)<<(4*c)) + +/* Channel Enable Register */ +#define CH_EN 0x1C +#define CH_TMR_EN(c , t) ((1<<t)<<(4*c)) + +/* Ch n Control REgister */ +#define CH_CTL(n) (0x20+0x10*n) +/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */ +#define APB_CLK (1<<3) +/* Channel mode , bit 0~2 */ +#define TMR_32 1 +#define TMR_16 2 +#define TMR_8 3 +#define PWM 4 + +#define CH_REL(n) (0x24+0x10*n) +#define CH_CNT(n) (0x28+0x10*n) + +struct atctmr_timer_regs { + u32 id_rev; /* 0x00 */ + u32 reservd[3]; /* 0x04 ~ 0x0c */ + u32 cfg; /* 0x10 */ + u32 int_en; /* 0x14 */ + u32 int_st; /* 0x18 */ + u32 ch_en; /* 0x1c */ + u32 ch0_ctrl; /* 0x20 */ + u32 ch0_reload; /* 0x24 */ + u32 ch0_cntr; /* 0x28 */ + u32 reservd1; /* 0x2c */ + u32 ch1_ctrl; /* 0x30 */ + u32 ch1_reload; /* 0x34 */ + u32 int_mask; /* 0x38 */ +}; + +struct atftmr_timer_platdata { + unsigned long *regs; +}; + +static int atftmr_timer_get_count(struct udevice *dev, u64 *count) +{ + struct atftmr_timer_platdata *plat = dev->platdata; + u32 val; + val = ~(REG32_TMR(CH_CNT(1))+0xffffffff); + *count = timer_conv_64(val); + return 0; +} + +static int atctmr_timer_probe(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev->platdata; + REG32_TMR(CH_REL(1)) = 0xffffffff; + REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32; + REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0); + return 0; +} + +static int atctme_timer_ofdata_to_platdata(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev_get_platdata(dev); + plat->regs = map_physmem(dev_get_addr(dev) , 0x100 , MAP_NOCACHE); + return 0; +} + +static const struct timer_ops ag101p_timer_ops = { + .get_count = atftmr_timer_get_count, +}; + +static const struct udevice_id ag101p_timer_ids[] = { + { .compatible = "andestech,atcpit100" }, + {} +}; + +U_BOOT_DRIVER(altera_timer) = { + .name = "ae3xx_timer", + .id = UCLASS_TIMER, + .of_match = ag101p_timer_ids, + .ofdata_to_platdata = atctme_timer_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), + .probe = atctmr_timer_probe, + .ops = &ag101p_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c new file mode 100644 index 0000000000..163402f8ce --- /dev/null +++ b/drivers/timer/ag101p_timer.c @@ -0,0 +1,122 @@ +/* + * Andestech ATFTMR010 timer driver + * + * (C) Copyright 2016 + * Rick Chen, NDS32 Software Engineering, rick@andestech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Timer Control Register + */ +#define T3_UPDOWN (1 << 11) +#define T2_UPDOWN (1 << 10) +#define T1_UPDOWN (1 << 9) +#define T3_OFENABLE (1 << 8) +#define T3_CLOCK (1 << 7) +#define T3_ENABLE (1 << 6) +#define T2_OFENABLE (1 << 5) +#define T2_CLOCK (1 << 4) +#define T2_ENABLE (1 << 3) +#define T1_OFENABLE (1 << 2) +#define T1_CLOCK (1 << 1) +#define T1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define T3_OVERFLOW (1 << 8) +#define T3_MATCH2 (1 << 7) +#define T3_MATCH1 (1 << 6) +#define T2_OVERFLOW (1 << 5) +#define T2_MATCH2 (1 << 4) +#define T2_MATCH1 (1 << 3) +#define T1_OVERFLOW (1 << 2) +#define T1_MATCH2 (1 << 1) +#define T1_MATCH1 (1 << 0) + +struct atftmr_timer_regs { + u32 t1_counter; /* 0x00 */ + u32 t1_load; /* 0x04 */ + u32 t1_match1; /* 0x08 */ + u32 t1_match2; /* 0x0c */ + u32 t2_counter; /* 0x10 */ + u32 t2_load; /* 0x14 */ + u32 t2_match1; /* 0x18 */ + u32 t2_match2; /* 0x1c */ + u32 t3_counter; /* 0x20 */ + u32 t3_load; /* 0x24 */ + u32 t3_match1; /* 0x28 */ + u32 t3_match2; /* 0x2c */ + u32 cr; /* 0x30 */ + u32 int_state; /* 0x34 */ + u32 int_mask; /* 0x38 */ +}; + +struct atftmr_timer_platdata { + struct atftmr_timer_regs *regs; +}; + +static int atftmr_timer_get_count(struct udevice *dev, u64 *count) +{ + struct atftmr_timer_platdata *plat = dev->platdata; + struct atftmr_timer_regs *const regs = plat->regs; + u32 val; + val = readl(®s->t3_counter); + *count = timer_conv_64(val); + return 0; +} + +static int atftmr_timer_probe(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev->platdata; + struct atftmr_timer_regs *const regs = plat->regs; + u32 cr; + writel(0, ®s->t3_load); + writel(0, ®s->t3_counter); + writel(TIMER_LOAD_VAL, ®s->t3_match1); + writel(TIMER_LOAD_VAL, ®s->t3_match2); + /* disable interrupts */ + writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask); + cr = readl(®s->cr); + cr |= (T3_ENABLE|T3_UPDOWN); + writel(cr, ®s->cr); + return 0; +} + +static int atftme_timer_ofdata_to_platdata(struct udevice *dev) +{ + struct atftmr_timer_platdata *plat = dev_get_platdata(dev); + plat->regs = map_physmem(dev_get_addr(dev), + sizeof(struct atftmr_timer_regs), + MAP_NOCACHE); + return 0; +} + +static const struct timer_ops ag101p_timer_ops = { + .get_count = atftmr_timer_get_count, +}; + +static const struct udevice_id ag101p_timer_ids[] = { + { .compatible = "andestech,attmr010" }, + {} +}; + +U_BOOT_DRIVER(altera_timer) = { + .name = "ag101p_timer", + .id = UCLASS_TIMER, + .of_match = ag101p_timer_ids, + .ofdata_to_platdata = atftme_timer_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata), + .probe = atftmr_timer_probe, + .ops = &ag101p_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/twserial/Makefile b/drivers/twserial/Makefile deleted file mode 100644 index 7cc7c4de82..0000000000 --- a/drivers/twserial/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2009 -# Detlev Zundel, DENX Software Engineering, dzu@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_SOFT_TWS) += soft_tws.o diff --git a/drivers/twserial/soft_tws.c b/drivers/twserial/soft_tws.c deleted file mode 100644 index d0bf93d902..0000000000 --- a/drivers/twserial/soft_tws.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define TWS_IMPLEMENTATION -#include <common.h> - -/*=====================================================================*/ -/* Public Functions */ -/*=====================================================================*/ - -/*----------------------------------------------------------------------- - * Read bits - */ -int tws_read(uchar *buffer, int len) -{ - int rem = len; - uchar accu, shift; - - debug("tws_read: buffer %p len %d\n", buffer, len); - - /* Configure the data pin for input */ - tws_data_config_output(0); - - /* Disable WR, i.e. setup a read */ - tws_wr(0); - udelay(1); - - /* Rise CE */ - tws_ce(1); - udelay(1); - - for (; rem > 0; ) { - for (shift = 0, accu = 0; - (rem > 0) && (shift < 8); - rem--, shift++) { - tws_clk(1); - udelay(10); - accu |= (tws_data_read() << shift); /* LSB first */ - tws_clk(0); - udelay(10); - } - *buffer++ = accu; - } - - /* Lower CE */ - tws_ce(0); - - return len - rem; -} - - -/*----------------------------------------------------------------------- - * Write bits - */ -int tws_write(uchar *buffer, int len) -{ - int rem = len; - uchar accu, shift; - - debug("tws_write: buffer %p len %d\n", buffer, len); - - /* Configure the data pin for output */ - tws_data_config_output(1); - - /* Enable WR, i.e. setup a write */ - tws_wr(1); - udelay(1); - - /* Rise CE */ - tws_ce(1); - udelay(1); - - for (; rem > 0; ) { - for (shift = 0, accu = *buffer++; - (rem > 0) && (shift < 8); - rem--, shift++) { - tws_data(accu & 0x01); /* LSB first */ - tws_clk(1); - udelay(10); - tws_clk(0); - udelay(10); - accu >>= 1; - } - } - - /* Lower CE */ - tws_ce(0); - - return len - rem; -} diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index 9d6cf8ce7b..4abef5d5c8 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -622,10 +622,12 @@ static int mcs7830_recv(struct eth_device *eth) int len; len = mcs7830_recv_common(ueth, buf); - if (len <= 0) + if (len >= 0) { net_process_received_packet(buf, len); + return 0; + } - return 0; + return len; } /* diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index fb5aa6f889..b824eec41d 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -57,6 +57,7 @@ endif # USB_XHCI_HCD config USB_EHCI_HCD bool "EHCI HCD (USB 2.0) support" + default y if ARCH_MX5 || ARCH_MX6 select USB_HOST ---help--- The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 @@ -74,12 +75,6 @@ config USB_EHCI_HCD You may want to read <file:Documentation/usb/ehci.txt>. -config USB_EHCI - bool - default USB_EHCI_HCD - ---help--- - TODO: rename after most boards switch to Kconfig - if USB_EHCI_HCD config USB_EHCI_ATMEL @@ -90,8 +85,8 @@ config USB_EHCI_ATMEL Enables support for the on-chip EHCI controller on Atmel chips. config USB_EHCI_MARVELL - bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller" - depends on ARCH_MVEBU + bool "Support for Marvell on-chip EHCI USB controller" + depends on ARCH_MVEBU || KIRKWOOD || ORION5X default y ---help--- Enables support for the on-chip EHCI controller on MVEBU SoCs. @@ -110,6 +105,14 @@ config USB_EHCI_MX7 ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. +config USB_EHCI_OMAP + bool "Support for OMAP3+ on-chip EHCI USB controller" + depends on ARCH_OMAP2PLUS + default y + ---help--- + Enables support for the on-chip EHCI controller on OMAP3 and later + SoCs. + if USB_EHCI_MX7 config MXC_USB_OTG_HACTIVE @@ -130,6 +133,14 @@ config USB_EHCI_MSM This driver supports combination of Chipidea USB controller and Synapsys USB PHY in host mode only. +config USB_EHCI_RCAR_GEN3 + bool "Support for Renesas RCar M3/H3 EHCI USB controller" + depends on RCAR_GEN3 + default y + ---help--- + Enables support for the on-chip EHCI controller on Renesas + R8A7795 and R8A7796 SoCs. + config USB_EHCI_ZYNQ bool "Support for Xilinx Zynq on-chip EHCI USB controller" depends on ARCH_ZYNQ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf54c2..4ece0a2e4b 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o # echi -obj-$(CONFIG_USB_EHCI) += ehci-hcd.o +obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o ifdef CONFIG_MPC512X @@ -51,6 +51,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o +obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci diff --git a/drivers/usb/host/ehci-rcar_gen3.c b/drivers/usb/host/ehci-rcar_gen3.c new file mode 100644 index 0000000000..525e7f3573 --- /dev/null +++ b/drivers/usb/host/ehci-rcar_gen3.c @@ -0,0 +1,106 @@ +/* + * drivers/usb/host/ehci-rcar_gen3. + * This file is EHCI HCD (Host Controller Driver) for USB. + * + * Copyright (C) 2015-2017 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <usb/ehci-ci.h> +#include "ehci.h" + +#define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000)) + +#define EHCI_USBCMD 0x120 + +#define CORE_SPD_RSM_TIMSET 0x30c +#define CORE_OC_TIMSET 0x310 + +/* Register offset */ +#define AHB_OFFSET 0x200 + +#define BASE_HSUSB 0xE6590000 +#define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */ +#define SUSPM 0x4000 +#define SUSPM_NORMAL BIT(14) +#define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */ +#define USB0SEL 0x00000030 +#define USB0SEL_EHCI 0x00000010 + +#define SMSTPCR7 0xE615014C +#define SMSTPCR700 BIT(0) /* EHCI3 */ +#define SMSTPCR701 BIT(1) /* EHCI2 */ +#define SMSTPCR702 BIT(2) /* EHCI1 */ +#define SMSTPCR703 BIT(3) /* EHCI0 */ +#define SMSTPCR704 BIT(4) /* HSUSB */ + +#define AHB_PLL_RST BIT(1) + +#define USBH_INTBEN BIT(2) +#define USBH_INTAEN BIT(1) + +#define AHB_INT_ENABLE 0x200 +#define AHB_USBCTR 0x20c + +int ehci_hcd_stop(int index) +{ +#if defined(CONFIG_R8A7795) + const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700; +#else + const u32 mask = SMSTPCR703 | SMSTPCR702; +#endif + const u32 base = RCAR_GEN3_USB_BASE(index); + int ret; + + /* Reset EHCI */ + setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET); + ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD, + CMD_RESET, false, 10, true); + if (ret) { + printf("ehci-rcar: reset failed (index=%i, ret=%i).\n", + index, ret); + } + + setbits_le32(SMSTPCR7, BIT(3 - index)); + + if ((readl(SMSTPCR7) & mask) == mask) + setbits_le32(SMSTPCR7, SMSTPCR704); + + return 0; +} + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + const void __iomem *base = + (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index); + struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base; + + clrbits_le32(SMSTPCR7, BIT(3 - index)); + clrbits_le32(SMSTPCR7, SMSTPCR704); + + *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uintptr_t)*hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + /* Enable interrupt */ + setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN); + writel(0x014e029b, base + CORE_SPD_RSM_TIMSET); + writel(0x000209ab, base + CORE_OC_TIMSET); + + /* Choice USB0SEL */ + clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI); + + /* Clock & Reset */ + clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST); + + /* low power status */ + clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL); + + return 0; +} diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index 9245126ed6..2f2b4b90de 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -9,11 +9,13 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <wait_bit.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> +#include <asm/arch/i2c.h> #include <usb.h> #include <i2c.h> @@ -81,14 +83,20 @@ struct otg_regs { static struct otg_regs *otg = (struct otg_regs *)USB_BASE; static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE; -static int isp1301_set_value(int reg, u8 value) +static int isp1301_set_value(struct udevice *dev, int reg, u8 value) { +#ifndef CONFIG_DM_I2C return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1); +#else + return dm_i2c_write(dev, reg, &value, 1); +#endif } -static void isp1301_configure(void) +static void isp1301_configure(struct udevice *dev) { +#ifndef CONFIG_DM_I2C i2c_set_bus_num(I2C_2); +#endif /* * LPC32XX only supports DAT_SE0 USB mode @@ -96,23 +104,23 @@ static void isp1301_configure(void) */ /* Disable transparent UART mode first */ - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN); + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN); - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG); - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG); - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0); - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET, + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG); + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG); + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0); + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET, MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL); - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0); - isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0); - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0); + isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0); + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN); - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, OTG1_DM_PULLUP | OTG1_DP_PULLUP); - isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0); - isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0); - isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0); + isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0); + isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0); + isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0); /* Enable usb_need_clk clock after transceiver is initialized */ setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); @@ -149,6 +157,15 @@ static int usbpll_setup(void) int usb_cpu_init(void) { u32 ret; + struct udevice *dev = NULL; + +#ifdef CONFIG_DM_I2C + ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev); + if (ret) { + debug("%s: No bus %d\n", __func__, I2C_2); + return ret; + } +#endif /* * USB pins routing setup is done by "lpc32xx_usb_init()" and should @@ -167,7 +184,7 @@ int usb_cpu_init(void) return ret; /* Configure ISP1301 */ - isp1301_configure(); + isp1301_configure(dev); /* setup USB clocks and PLL */ ret = usbpll_setup(); @@ -188,21 +205,32 @@ int usb_cpu_init(void) return ret; setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); return 0; } int usb_cpu_stop(void) { + struct udevice *dev = NULL; + int ret = 0; + +#ifdef CONFIG_DM_I2C + ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev); + if (ret) { + debug("%s: No bus %d\n", __func__, I2C_2); + return ret; + } +#endif + /* vbus off */ - isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); + isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN); - return 0; + return ret; } int usb_cpu_init_fail(void) diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h index 9244977579..4dae83ed68 100644 --- a/drivers/usb/musb-new/linux-compat.h +++ b/drivers/usb/musb-new/linux-compat.h @@ -30,7 +30,7 @@ #define CONFIG_SOC_OMAP3430 #endif -#ifdef CONFIG_OMAP4430 +#ifdef CONFIG_OMAP44XX #define CONFIG_ARCH_OMAP4 #endif diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 684ad9539a..ba22dfe6cb 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -441,7 +441,7 @@ static int omap2430_musb_enable(struct musb *musb) twl6030_usb_device_settings(); #endif -#ifdef CONFIG_OMAP4430 +#ifdef CONFIG_OMAP44XX u32 *usbotghs_control = (u32 *)((*ctrl)->control_usbotghs_ctrl); *usbotghs_control = USBOTGHS_CONTROL_AVALID | USBOTGHS_CONTROL_VBUSVALID | USBOTGHS_CONTROL_IDDIG; diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c index 97da529b44..57889ef0e7 100644 --- a/drivers/usb/musb/omap3.c +++ b/drivers/usb/musb/omap3.c @@ -55,7 +55,7 @@ static struct omap3_otg_regs *otg; #define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001 /* OMAP4430 has an internal PHY, use it */ -#ifdef CONFIG_OMAP4430 +#ifdef CONFIG_OMAP44XX #define OMAP3_OTG_INTERFSEL_OMAP 0x0000 #else #define OMAP3_OTG_INTERFSEL_OMAP 0x0001 @@ -118,11 +118,11 @@ int musb_platform_init(void) stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY; writel(stdby, &otg->forcestdby); -#ifdef CONFIG_OMAP3_EVM +#ifdef CONFIG_TARGET_OMAP3_EVM musb_cfg.extvbus = omap3_evm_need_extvbus(); #endif -#ifdef CONFIG_OMAP4430 +#ifdef CONFIG_OMAP44XX u32 *usbotghs_control = (u32 *)((*ctrl)->control_usbotghs_ctrl); *usbotghs_control = 0x15; diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h index ae645c72de..d91ad0a85b 100644 --- a/drivers/usb/musb/omap3.h +++ b/drivers/usb/musb/omap3.h @@ -32,7 +32,7 @@ int musb_platform_init(void); -#ifdef CONFIG_OMAP3_EVM +#ifdef CONFIG_TARGET_OMAP3_EVM extern u8 omap3_evm_need_extvbus(void); #endif diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 446cca90d4..61dfed8c06 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -619,4 +619,13 @@ config LCD CONFIG option. See the README for details. Drives which have been converted to driver model will instead used CONFIG_DM_VIDEO. +config VIDEO_DW_HDMI + bool + help + Enables the common driver code for the Designware HDMI TX + block found in SoCs from various vendors. + As this does not provide any functionality by itself (but + rather requires a SoC-specific glue driver to call it), it + can not be enabled from the configuration menu. + endmenu diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a80af3104d..58f5de5200 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_VIDEO_VESA) += vesa.o obj-$(CONFIG_FORMIKE) += formike.o obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_AM335X_LCD) += am335x-fb.o +obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ obj-${CONFIG_EXYNOS_FB} += exynos/ diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index 8a53109823..6039d676c5 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -414,13 +414,9 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); - /* - * TODO(sjg@chromium.org>: Need to check for HDMI / DVI - * inv_val |= (edid->hdmi_monitor_detected ? - * HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : - * HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE); - */ - inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE; + inv_val |= (edid->hdmi_monitor ? + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE); inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; @@ -459,7 +455,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, } /* hdmi initialization step b.4 */ -static void hdmi_enable_video_path(struct dw_hdmi *hdmi) +static void hdmi_enable_video_path(struct dw_hdmi *hdmi, bool audio) { uint clkdis; @@ -484,8 +480,10 @@ static void hdmi_enable_video_path(struct dw_hdmi *hdmi) clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); - clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; - hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); + if (audio) { + clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; + hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); + } } /* workaround to clear the overflow condition */ @@ -716,7 +714,8 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) { int ret; - debug("hdmi, mode info : clock %d hdis %d vdis %d\n", + debug("%s, mode info : clock %d hdis %d vdis %d\n", + edid->hdmi_monitor ? "hdmi" : "dvi", edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ); hdmi_av_composer(hdmi, edid); @@ -725,11 +724,13 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) if (ret) return ret; - hdmi_enable_video_path(hdmi); + hdmi_enable_video_path(hdmi, edid->hdmi_monitor); - hdmi_audio_fifo_reset(hdmi); - hdmi_audio_set_format(hdmi); - hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); + if (edid->hdmi_monitor) { + hdmi_audio_fifo_reset(hdmi); + hdmi_audio_set_format(hdmi); + hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); + } hdmi_video_packetize(hdmi); hdmi_video_sample(hdmi); diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 9267b28781..80e399f7d7 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -35,6 +35,7 @@ config DISPLAY_ROCKCHIP_LVDS config DISPLAY_ROCKCHIP_HDMI bool "HDMI port" + select VIDEO_DW_HDMI depends on VIDEO_ROCKCHIP help This enables High-Definition Multimedia Interface display support. diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index c742902ddb..cd54b12a4e 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -9,6 +9,6 @@ ifdef CONFIG_VIDEO_ROCKCHIP obj-y += rk_vop.o obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o -obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o +obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o endif diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile index b8afd892ad..dbaab61b59 100644 --- a/drivers/video/sunxi/Makefile +++ b/drivers/video/sunxi/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o +obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve.o ../videomodes.o obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 92c9d06054..de768ba94a 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -14,6 +14,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/lcdc.h> #include <asm/arch/pwm.h> +#include <asm/arch/tve.h> #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> @@ -929,63 +930,19 @@ static void sunxi_tvencoder_mode_set(void) switch (sunxi_display.monitor) { case sunxi_monitor_vga: - writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | - SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) | - SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl); - writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0); - writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0); - writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1); + tvencoder_mode_set(tve, tve_mode_vga); break; case sunxi_monitor_composite_pal_nc: - writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq); - /* Fall through */ + tvencoder_mode_set(tve, tve_mode_composite_pal_nc); + break; case sunxi_monitor_composite_pal: - writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | - SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) | - SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) | - SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl); - writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0); - writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0); - writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter); - writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num); - writel(SUNXI_TVE_LINE_NUM_PAL, &tve->line_num); - writel(SUNXI_TVE_BLANK_BLACK_LEVEL_PAL, &tve->blank_black_level); - writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1); - writel(SUNXI_TVE_CBR_LEVEL_PAL, &tve->cbr_level); - writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width); - writel(SUNXI_TVE_UNKNOWN2_PAL, &tve->unknown2); - writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num); - writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain); - writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width); - writel(SUNXI_TVE_RESYNC_NUM_PAL, &tve->resync_num); - writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para); + tvencoder_mode_set(tve, tve_mode_composite_pal); break; case sunxi_monitor_composite_pal_m: - writel(SUNXI_TVE_CHROMA_FREQ_PAL_M, &tve->chroma_freq); - writel(SUNXI_TVE_COLOR_BURST_PAL_M, &tve->color_burst); - /* Fall through */ + tvencoder_mode_set(tve, tve_mode_composite_pal_m); + break; case sunxi_monitor_composite_ntsc: - writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | - SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) | - SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) | - SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl); - writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0); - writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0); - writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter); - writel(SUNXI_TVE_PORCH_NUM_NTSC, &tve->porch_num); - writel(SUNXI_TVE_LINE_NUM_NTSC, &tve->line_num); - writel(SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC, &tve->blank_black_level); - writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1); - writel(SUNXI_TVE_CBR_LEVEL_NTSC, &tve->cbr_level); - writel(SUNXI_TVE_BURST_PHASE_NTSC, &tve->burst_phase); - writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width); - writel(SUNXI_TVE_UNKNOWN2_NTSC, &tve->unknown2); - writel(SUNXI_TVE_SYNC_VBI_LEVEL_NTSC, &tve->sync_vbi_level); - writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num); - writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain); - writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width); - writel(SUNXI_TVE_RESYNC_NUM_NTSC, &tve->resync_num); - writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para); + tvencoder_mode_set(tve, tve_mode_composite_ntsc); break; case sunxi_monitor_none: case sunxi_monitor_dvi: @@ -995,14 +952,6 @@ static void sunxi_tvencoder_mode_set(void) } } -static void sunxi_tvencoder_enable(void) -{ - struct sunxi_tve_reg * const tve = - (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; - - setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE); -} - #endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */ static void sunxi_drc_init(void) @@ -1080,6 +1029,8 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, int __maybe_unused clk_div, clk_double; struct sunxi_lcdc_reg * const lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; + struct sunxi_tve_reg * __maybe_unused const tve = + (struct sunxi_tve_reg *)SUNXI_TVE0_BASE; switch (sunxi_display.monitor) { case sunxi_monitor_none: @@ -1134,7 +1085,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, sunxi_tvencoder_mode_set(); sunxi_composer_enable(); lcdc_enable(lcdc, sunxi_display.depth); - sunxi_tvencoder_enable(); + tvencoder_enable(tve); #elif defined CONFIG_VIDEO_VGA_VIA_LCD sunxi_composer_mode_set(mode, address); sunxi_lcdc_tcon0_mode_set(mode, true); @@ -1153,7 +1104,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, sunxi_tvencoder_mode_set(); sunxi_composer_enable(); lcdc_enable(lcdc, sunxi_display.depth); - sunxi_tvencoder_enable(); + tvencoder_enable(tve); #endif break; } diff --git a/drivers/video/sunxi/tve.c b/drivers/video/sunxi/tve.c new file mode 100644 index 0000000000..adea78a69a --- /dev/null +++ b/drivers/video/sunxi/tve.c @@ -0,0 +1,86 @@ +/* + * TV encoder driver for Allwinner SoCs. + * + * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be> + * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <asm/arch/tve.h> +#include <asm/io.h> + +void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode) +{ + switch (mode) { + case tve_mode_vga: + writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | + SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) | + SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl); + writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0); + writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0); + writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1); + break; + case tve_mode_composite_pal_nc: + writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq); + /* Fall through */ + case tve_mode_composite_pal: + writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | + SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) | + SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) | + SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl); + writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0); + writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0); + writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter); + writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num); + writel(SUNXI_TVE_LINE_NUM_PAL, &tve->line_num); + writel(SUNXI_TVE_BLANK_BLACK_LEVEL_PAL, + &tve->blank_black_level); + writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1); + writel(SUNXI_TVE_CBR_LEVEL_PAL, &tve->cbr_level); + writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width); + writel(SUNXI_TVE_UNKNOWN2_PAL, &tve->unknown2); + writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num); + writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain); + writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width); + writel(SUNXI_TVE_RESYNC_NUM_PAL, &tve->resync_num); + writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para); + break; + case tve_mode_composite_pal_m: + writel(SUNXI_TVE_CHROMA_FREQ_PAL_M, &tve->chroma_freq); + writel(SUNXI_TVE_COLOR_BURST_PAL_M, &tve->color_burst); + /* Fall through */ + case tve_mode_composite_ntsc: + writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) | + SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) | + SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) | + SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl); + writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0); + writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0); + writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter); + writel(SUNXI_TVE_PORCH_NUM_NTSC, &tve->porch_num); + writel(SUNXI_TVE_LINE_NUM_NTSC, &tve->line_num); + writel(SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC, + &tve->blank_black_level); + writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1); + writel(SUNXI_TVE_CBR_LEVEL_NTSC, &tve->cbr_level); + writel(SUNXI_TVE_BURST_PHASE_NTSC, &tve->burst_phase); + writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width); + writel(SUNXI_TVE_UNKNOWN2_NTSC, &tve->unknown2); + writel(SUNXI_TVE_SYNC_VBI_LEVEL_NTSC, &tve->sync_vbi_level); + writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num); + writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain); + writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width); + writel(SUNXI_TVE_RESYNC_NUM_NTSC, &tve->resync_num); + writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para); + break; + } +} + +void tvencoder_enable(struct sunxi_tve_reg * const tve) +{ + setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE); +} diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 32a4e7f8a9..f803067da3 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -316,7 +316,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, } break; #endif /* CONFIG_BMP_16BPP */ -#if defined(CONFIG_BMP_24BMP) +#if defined(CONFIG_BMP_24BPP) case 24: for (i = 0; i < height; ++i) { for (j = 0; j < width; j++) { @@ -328,7 +328,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, fb -= priv->line_length + width * (bpix / 8); } break; -#endif /* CONFIG_BMP_24BMP */ +#endif /* CONFIG_BMP_24BPP */ #if defined(CONFIG_BMP_32BPP) case 32: for (i = 0; i < height; ++i) { diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index bdaf5d4101..22a7c4f801 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -12,6 +12,14 @@ config BCM2835_WDT This provides basic infrastructure to support BCM2835/2836 watchdog hardware, with a max timeout of ~15secs. +config OMAP_WATCHDOG + bool "TI OMAP watchdog driver" + depends on ARCH_OMAP2PLUS + select HW_WATCHDOG + default y if AM33XX + help + Say Y here to enable the OMAP3+ watchdog driver. + config ULP_WATCHDOG bool "i.MX7ULP watchdog" help diff --git a/fs/Makefile b/fs/Makefile index 5c90656ba1..5770f41c0b 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_FS_CBFS) += cbfs/ obj-$(CONFIG_CMD_CRAMFS) += cramfs/ obj-$(CONFIG_FS_EXT4) += ext4/ obj-y += fat/ -obj-$(CONFIG_CMD_JFFS2) += jffs2/ +obj-$(CONFIG_FS_JFFS2) += jffs2/ obj-$(CONFIG_CMD_REISER) += reiserfs/ obj-$(CONFIG_SANDBOX) += sandbox/ obj-$(CONFIG_CMD_UBIFS) += ubifs/ diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 56540031d6..a71bad1cbc 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -1250,7 +1250,7 @@ int file_fat_detectfs(void) return 1; } -#if defined(CONFIG_CMD_IDE) || \ +#if defined(CONFIG_IDE) || \ defined(CONFIG_CMD_SATA) || \ defined(CONFIG_SCSI) || \ defined(CONFIG_CMD_USB) || \ diff --git a/fs/jffs2/Kconfig b/fs/jffs2/Kconfig index e69de29bb2..1b9ecdd8cc 100644 --- a/fs/jffs2/Kconfig +++ b/fs/jffs2/Kconfig @@ -0,0 +1,7 @@ +config FS_JFFS2 + bool "Enable JFFS2 filesystem support" + help + This provides support for reading images from JFFS2 (Journalling + Flash File System version 2). JFFS2 is a log-structured file system + for use with flash memory devices. It supports raw NAND devices, + hard links and compression. diff --git a/include/atf_common.h b/include/atf_common.h new file mode 100644 index 0000000000..8c513e7c3e --- /dev/null +++ b/include/atf_common.h @@ -0,0 +1,183 @@ +/* + * This is from the ARM TF Project, + * Repository: https://github.com/ARM-software/arm-trusted-firmware.git + * File: include/common/bl_common.h + * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights + * reserved. + * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __BL_COMMON_H__ +#define __BL_COMMON_H__ + +#define ATF_PARAM_EP 0x01 +#define ATF_PARAM_IMAGE_BINARY 0x02 +#define ATF_PARAM_BL31 0x03 + +#define ATF_VERSION_1 0x01 + +#define ATF_EP_SECURE 0x0 +#define ATF_EP_NON_SECURE 0x1 + +#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ + (_p)->h.type = (uint8_t)(_type); \ + (_p)->h.version = (uint8_t)(_ver); \ + (_p)->h.size = (uint16_t)sizeof(*_p); \ + (_p)->h.attr = (uint32_t)(_attr) ; \ + } while (0) + +#define MODE_RW_SHIFT 0x4 +#define MODE_RW_MASK 0x1 +#define MODE_RW_64 0x0 +#define MODE_RW_32 0x1 + +#define MODE_EL_SHIFT 0x2 +#define MODE_EL_MASK 0x3 +#define MODE_EL3 0x3 +#define MODE_EL2 0x2 +#define MODE_EL1 0x1 +#define MODE_EL0 0x0 + +#define MODE_SP_SHIFT 0x0 +#define MODE_SP_MASK 0x1 +#define MODE_SP_EL0 0x0 +#define MODE_SP_ELX 0x1 + +#define SPSR_DAIF_SHIFT 6 +#define SPSR_DAIF_MASK 0x0f + +#define SPSR_64(el, sp, daif) \ + (MODE_RW_64 << MODE_RW_SHIFT | \ + ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ + ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ + ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) + +#define SPSR_FIQ (1 << 6) +#define SPSR_IRQ (1 << 7) +#define SPSR_SERROR (1 << 8) +#define SPSR_DEBUG (1 << 9) +#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG) + +#define DAIF_FIQ_BIT (1<<0) +#define DAIF_IRQ_BIT (1<<1) +#define DAIF_ABT_BIT (1<<2) +#define DAIF_DBG_BIT (1<<3) +#define DISABLE_ALL_EXECPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Structure used for telling the next BL how much of a particular type of + * memory is available for its use and how much is already used. + ******************************************************************************/ +struct aapcs64_params { + unsigned long arg0; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; + unsigned long arg4; + unsigned long arg5; + unsigned long arg6; + unsigned long arg7; +}; + +/*************************************************************************** + * This structure provides version information and the size of the + * structure, attributes for the structure it represents + ***************************************************************************/ +struct param_header { + uint8_t type; /* type of the structure */ + uint8_t version; /* version of this structure */ + uint16_t size; /* size of this structure in bytes */ + uint32_t attr; /* attributes: unused bits SBZ */ +}; + +/***************************************************************************** + * This structure represents the superset of information needed while + * switching exception levels. The only two mechanisms to do so are + * ERET & SMC. Security state is indicated using bit zero of header + * attribute + * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start + * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while + * processing SMC to jump to BL31. + *****************************************************************************/ +struct entry_point_info { + struct param_header h; + uintptr_t pc; + uint32_t spsr; + struct aapcs64_params args; +}; + +/***************************************************************************** + * Image info binary provides information from the image loader that + * can be used by the firmware to manage available trusted RAM. + * More advanced firmware image formats can provide additional + * information that enables optimization or greater flexibility in the + * common firmware code + *****************************************************************************/ +struct atf_image_info { + struct param_header h; + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ +}; + +/***************************************************************************** + * The image descriptor struct definition. + *****************************************************************************/ +struct image_desc { + /* Contains unique image id for the image. */ + unsigned int image_id; + /* + * This member contains Image state information. + * Refer IMAGE_STATE_XXX defined above. + */ + unsigned int state; + uint32_t copied_size; /* image size copied in blocks */ + struct atf_image_info atf_image_info; + struct entry_point_info ep_info; +}; + +/******************************************************************************* + * This structure represents the superset of information that can be passed to + * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be + * populated only if BL2 detects its presence. A pointer to a structure of this + * type should be passed in X0 to BL31's cold boot entrypoint. + * + * Use of this structure and the X0 parameter is not mandatory: the BL31 + * platform code can use other mechanisms to provide the necessary information + * about BL32 and BL33 to the common and SPD code. + * + * BL31 image information is mandatory if this structure is used. If either of + * the optional BL32 and BL33 image information is not provided, this is + * indicated by the respective image_info pointers being zero. + ******************************************************************************/ +struct bl31_params { + struct param_header h; + struct atf_image_info *bl31_image_info; + struct entry_point_info *bl32_ep_info; + struct atf_image_info *bl32_image_info; + struct entry_point_info *bl33_ep_info; + struct atf_image_info *bl33_image_info; +}; + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31, e.g. while passing control to it from BL2, bl31_params + * and other platform specific params + ******************************************************************************/ +struct bl2_to_bl31_params_mem { + struct bl31_params bl31_params; + struct atf_image_info bl31_image_info; + struct atf_image_info bl32_image_info; + struct atf_image_info bl33_image_info; + struct entry_point_info bl33_ep_info; + struct entry_point_info bl32_ep_info; + struct entry_point_info bl31_ep_info; +}; + +#endif /*__ASSEMBLY__*/ + +#endif /* __BL_COMMON_H__ */ diff --git a/include/common.h b/include/common.h index 83e4037a86..45f190a600 100644 --- a/include/common.h +++ b/include/common.h @@ -499,9 +499,19 @@ void reset_phy (void); void fdc_hw_init (void); /* $(BOARD)/eeprom.c */ +#ifdef CONFIG_CMD_EEPROM void eeprom_init (int bus); int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); +#else +/* + * Some EEPROM code is depecated because it used the legacy I2C interface. Add + * some macros here so we don't have to touch every one of those uses + */ +#define eeprom_init(bus) +#define eeprom_read(dev_addr, offset, buffer, cnt) ((void)-ENOSYS) +#define eeprom_write(dev_addr, offset, buffer, cnt) ((void)-ENOSYS) +#endif /* * Set this up regardless of board diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index bc0bc2b6c8..b1f41abf4f 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -13,18 +13,6 @@ * Alphabetical list of all possible commands. */ -#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */ -#define CONFIG_CMD_EEPROM /* EEPROM read/write support */ -#define CONFIG_CMD_FDC /* Floppy Disk Support */ -#define CONFIG_CMD_FUSE /* Device fuse support */ -#define CONFIG_CMD_GETTIME /* Get time since boot */ -#define CONFIG_CMD_HASH /* calculate hash / digest */ -#define CONFIG_CMD_IDE /* IDE harddisk support */ -#define CONFIG_CMD_IMMAP /* IMMR dump support */ -#define CONFIG_CMD_IO /* Access to X86 IO space */ -#define CONFIG_CMD_IRQ /* irqinfo */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_KGDB /* kgdb */ #define CONFIG_CMD_MFSL /* FSL support for Microblaze */ #define CONFIG_CMD_MTDPARTS /* mtd parts support */ #define CONFIG_CMD_NAND /* NAND support */ diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 0e01e8240d..4b2c493ae3 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -186,16 +186,16 @@ BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI #endif -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide) #define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV #else #define BOOTENV_SHARED_IDE #define BOOTENV_DEV_IDE \ - BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE + BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE #define BOOTENV_DEV_NAME_IDE \ - BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_CMD_IDE + BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE #endif #if defined(CONFIG_CMD_PCI_ENUM) || defined(CONFIG_DM_PCI) diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 7aa5b02396..5a698a8349 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -43,7 +43,7 @@ #endif /* Rather than repeat this expression each time, add a define for it */ -#if defined(CONFIG_CMD_IDE) || \ +#if defined(CONFIG_IDE) || \ defined(CONFIG_CMD_SATA) || \ defined(CONFIG_SCSI) || \ defined(CONFIG_CMD_USB) || \ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index abfdbc9276..2226aba674 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -702,30 +702,19 @@ unsigned long get_board_ddr_clk(void); /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * USB */ #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 6f333e75ef..59b2252e6f 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -228,7 +228,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 /* I2C EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -294,8 +293,6 @@ extern unsigned long get_sdram_size(void); /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO /* @@ -328,15 +325,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_HAS_FSL_DR_USB diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 9097932581..407e499de1 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -417,7 +417,6 @@ combinations. this should be removed later #define CONFIG_SYS_EEPROM_BUS_NUM 0 /* enable read and write access to EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -476,8 +475,7 @@ combinations. this should be removed later #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif -#define CONFIG_USB_EHCI /* USB */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_HAS_FSL_DR_USB @@ -522,16 +520,8 @@ combinations. this should be removed later /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index f95c3b9eeb..398d0e0550 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -371,7 +371,6 @@ /* I2C EEPROM */ /* enable read and write access to EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -437,16 +436,8 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index c3b2353f5f..6d2919ff55 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -46,8 +46,6 @@ * Command line configuration. */ #define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM #undef CONFIG_WATCHDOG /* watchdog disabled */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index deb6f826e1..ab4b060906 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -61,9 +61,6 @@ * Command line configuration. */ #define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_EEPROM #define CONFIG_SUPPORT_VFAT diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 7f5eecaad5..fc9b26ff46 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -36,7 +36,6 @@ #define CONFIG_BOOTP_HOSTNAME /* Command line configuration */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO #define CONFIG_HOSTNAME M52277EVB @@ -88,7 +87,6 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 #define CONFIG_SYS_USB_EHCI_CPU_INIT #endif diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index b1a49b07c3..3efd7e59cf 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -37,9 +37,8 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE /* ATA */ # define CONFIG_IDE_RESET 1 # define CONFIG_IDE_PREINIT 1 diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index 380221e732..4f7a19b5d3 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -46,7 +46,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE /* ATA */ #define CONFIG_IDE_RESET 1 diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 1817571efe..f4d970d0d8 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -37,7 +37,6 @@ #define CONFIG_BOOTP_HOSTNAME /* Command line configuration */ -#undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_NAND #define CONFIG_CMD_REGINFO @@ -60,7 +59,7 @@ #define CONFIG_MII_INIT 1 #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_SYS_RX_ETH_BUFFER 2 -#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN #define CONFIG_SYS_TX_ETH_BUFFER 2 #define CONFIG_HAS_ETH1 @@ -166,7 +165,6 @@ /* I2c */ #undef CONFIG_SYS_FSL_I2C -#undef CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SPEED 80000 diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 553e877ae7..7d6edda361 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -36,7 +36,6 @@ #define CONFIG_BOOTP_HOSTNAME /* Command line configuration */ -#undef CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO /* Network configuration */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 806f00555f..39ba94065a 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -36,8 +36,6 @@ #define CONFIG_BOOTP_HOSTNAME /* Command line configuration */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #undef CONFIG_CMD_PCI #define CONFIG_CMD_REGINFO diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 30db7edde8..b13809f88a 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -46,10 +46,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_PCI #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SAVES diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 493e3fa646..fbe033afb1 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -366,7 +366,6 @@ #define CONFIG_HAS_FSL_DR_USB #define CONFIG_SYS_SCCR_USBDRCM 3 -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_PHY_TYPE "utmi" #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index d782fc3cf1..ea99aead45 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -320,7 +320,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 719c27966a..46f09d6b60 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -148,7 +148,6 @@ /* * Support USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL /* Current USB implementation supports the only USB controller, @@ -479,7 +478,6 @@ boards, we say we have two, but don't display a message if we find only one. */ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_SDRAM #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ @@ -487,10 +485,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SUPPORT_VFAT #endif -#ifdef CONFIG_COMPACT_FLASH - #define CONFIG_CMD_IDE -#endif - #ifdef CONFIG_SATA_SIL3114 #define CONFIG_CMD_SATA #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 85b7c48fdf..fcced0eb86 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -376,7 +376,6 @@ extern int board_pci_host_broken(void); #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index d39dc1b465..607b9266d2 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -651,7 +651,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index aeb9f0bbaf..18b6b4e13e 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -589,8 +589,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) @@ -609,9 +607,7 @@ */ #define CONFIG_HAS_FSL_MPH_USB #ifdef CONFIG_HAS_FSL_MPH_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index c5d581589a..0f96ac0242 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -315,7 +315,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 4509a6d707..029aa572ce 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -342,7 +342,6 @@ extern unsigned long get_clock_freq(void); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 8f7e056606..9b2f8364d5 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -348,7 +348,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) @@ -359,9 +358,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * USB */ -#define CONFIG_USB_EHCI -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_PCI #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_PCI_EHCI_DEVICE 0 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index df50fa3cce..43e05516ab 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -461,7 +461,6 @@ extern unsigned long get_clock_freq(void); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 67093dfa31..96a125c323 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -340,7 +340,6 @@ extern unsigned long get_clock_freq(void); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 8170b9f17d..8d026addb3 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -354,7 +354,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 0bc71d4ae6..618d5377fc 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -355,7 +355,6 @@ extern unsigned long get_clock_freq(void); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 81d2d4f931..eb7db20b7f 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -448,7 +448,6 @@ extern unsigned long get_clock_freq(void); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index e6aca11e50..79e11bb6f8 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -547,8 +547,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) @@ -559,9 +557,8 @@ /* * USB */ -#define CONFIG_USB_EHCI -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_PCI #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_PCI_EHCI_DEVICE 0 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 95b42208e9..220b07040e 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -589,7 +589,6 @@ extern unsigned long get_sdram_size(void); #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ #endif /* enable read and write access to EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -670,9 +669,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_HAS_FSL_DR_USB #if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif @@ -727,22 +724,14 @@ extern unsigned long get_sdram_size(void); /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #undef CONFIG_WATCHDOG /* watchdog disabled */ -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ || defined(CONFIG_FSL_SATA) #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index db66c309e7..3d12c84ce9 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -593,8 +593,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI @@ -606,9 +604,7 @@ */ #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 787b8d206e..719043d5a1 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -241,7 +241,6 @@ extern unsigned long get_clock_freq(void); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) @@ -253,9 +252,7 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c3e3fae44f..b008e3d9e2 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -580,8 +580,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #ifdef CONFIG_PCI #define CONFIG_CMD_PCI @@ -594,7 +592,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_HAS_FSL_MPH_USB #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -605,12 +602,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/PATI.h b/include/configs/PATI.h index e53db2485b..1f26ac4c2d 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -38,8 +38,6 @@ */ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IRQ #define CONFIG_BOOTCOMMAND "" /* autoboot command */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 6c74b00cd5..393a02dd78 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -37,12 +37,8 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE #define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FDC #define CONFIG_SCSI #define CONFIG_CMD_SDRAM #define CONFIG_CMD_SAVES diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 4bb07d8bd4..78ce91d089 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -55,10 +55,7 @@ * Command line configuration. */ #define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE #define CONFIG_CMD_NAND -#define CONFIG_CMD_EEPROM #define CONFIG_SUPPORT_VFAT diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index d889306653..a94e790b95 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -48,8 +48,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IRQ #define CONFIG_CMD_PCI #undef CONFIG_WATCHDOG /* watchdog disabled */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index b9599b5e3b..54a1a2546f 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -163,26 +163,6 @@ #define CONFIG_SYS_EEPROM_WREN 1 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52 -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the TMP401 - */ -#define CONFIG_DTT_SENSORS { 0, 1 } - -/* - * The PMC440 uses a TI TMP401 temperature sensor. This part - * is basically compatible to the ADM1021 that is supported - * by U-Boot. - * - * - i2c addr 0x4c - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 70 deg - * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg - */ -#define CONFIG_DTT_ADM1021 -#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } - #define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \ "\\\"painit\\\" to preboot command" @@ -258,8 +238,6 @@ /* Partitions */ -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_REGINFO diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 4da829d838..2209cfdb96 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -637,7 +637,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -780,9 +779,6 @@ unsigned long get_board_ddr_clk(void); /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI @@ -866,12 +862,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #include <asm/fsl_secure_boot.h> #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 3b55404cda..025e7de8d0 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -641,7 +641,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -790,9 +789,6 @@ unsigned long get_board_ddr_clk(void); /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI @@ -885,12 +881,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #include <asm/fsl_secure_boot.h> #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index b2810b65f9..3953145030 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -527,9 +527,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -631,7 +629,6 @@ unsigned long get_board_ddr_clk(void); /* Enable VSC9953 L2 Switch driver */ #define CONFIG_VSC9953 -#define CONFIG_CMD_ETHSW #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 @@ -661,21 +658,12 @@ unsigned long get_board_ddr_clk(void); /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5577408015..0035e67544 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -637,9 +637,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -750,7 +748,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_VSC9953 -#define CONFIG_CMD_ETHSW #ifdef CONFIG_TARGET_T1040RDB #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 @@ -774,20 +771,12 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a32ddeed1d..e792ec5c9d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -12,7 +12,6 @@ #define __T208xQDS_H #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_USB_EHCI #if defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ @@ -702,7 +701,7 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_HAS_FSL_DR_USB @@ -745,20 +744,12 @@ unsigned long get_board_ddr_clk(void); /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 90ce554035..fdafeeb38f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -12,7 +12,6 @@ #define __T2080RDB_H #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_USB_EHCI #define CONFIG_FSL_SATA_V2 /* High Level Configuration Options */ @@ -652,7 +651,7 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_HAS_FSL_DR_USB @@ -691,19 +690,12 @@ unsigned long get_board_ddr_clk(void); /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 9d4baaa79f..dc3ebfa7fa 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -498,16 +498,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_HAS_FSL_DR_USB diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index cc1f79940c..0d9cdfb510 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -272,8 +272,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #ifdef CONFIG_PCI #define CONFIG_CMD_PCI @@ -685,7 +683,6 @@ unsigned long get_board_ddr_clk(void); /* * USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_HAS_FSL_DR_USB @@ -697,12 +694,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #define __USB_PHY_TYPE utmi diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 13f4ef67e1..e1f04459c4 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -124,8 +124,7 @@ #ifndef CONFIG_CAM5200 /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) + CONFIG_SYS_POST_CPU) #endif #ifdef CONFIG_POST @@ -144,8 +143,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI @@ -155,7 +152,6 @@ #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) - #define CONFIG_CMD_IDE #endif #if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ @@ -279,54 +275,6 @@ #endif /* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-Boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * HW-Monitor configuration on Mini-FAP - */ -#if defined (CONFIG_MINIFAP) -#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C -#endif - -/* List of I2C addresses to be verified by POST */ -#if defined (CONFIG_MINIFAP) -#undef CONFIG_SYS_POST_I2C_ADDRS -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ - CONFIG_SYS_I2C_HWMON_ADDR, \ - CONFIG_SYS_I2C_SLAVE} -#endif - -/* * Flash configuration */ #define CONFIG_SYS_FLASH_BASE 0xFC000000 @@ -545,18 +493,6 @@ #endif /* - * RTC configuration - */ -#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) -# define CONFIG_RTC_M41T11 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 -# define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base - year */ -#else -# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ -#endif - -/* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index f56bd239af..74636b9162 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -91,8 +91,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index ed08d972f8..6b345c427c 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -89,8 +89,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index e3c2cca3c3..a79dabef61 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -184,13 +184,6 @@ #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - /* * TSEC */ @@ -280,9 +273,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index c2b35fd196..b4ed561544 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -84,8 +84,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 76b52ab6b1..1dc13295ff 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -84,8 +84,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 10ba21d97d..b4c3a79387 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -86,8 +86,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 7cfc351191..14b76a66bc 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -115,9 +115,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 7569cd1e83..f55fe56abb 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -86,8 +86,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index d2cb4b9a87..52c4d68693 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -86,8 +86,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 03ad2e63a0..06981c9861 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -89,8 +89,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 485bd6c8a6..3f87d8aa11 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -89,8 +89,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 2906fcfca4..975f4b76dc 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -129,9 +129,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_NETCONSOLE diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index eaf0741071..184cb62e19 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -125,8 +125,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE /* * Miscellaneous configurable options diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index c60743acd0..b2feccfd39 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -129,27 +129,6 @@ #define CONFIG_HWCONFIG -#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ -#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ -#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */ -/* - * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details). - * there will be one entry in this array for each two (dummy) sensors in - * CONFIG_DTT_SENSORS. - * - * For uCP1020 module: - * - only one ADM1021/NCT72 - * - i2c addr 0x41 - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT output disabled - * - local temp sensor enabled, min set to 0 deg, max set to 85 deg - * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg - */ -#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \ - 0x02, 0, 1, 0, 85, 1, 0, 85} } - -#define CONFIG_CMD_DTT - /* * These can be toggled for performance analysis, otherwise use default. */ @@ -442,10 +421,7 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_ERRATA /* * USB @@ -453,11 +429,9 @@ #define CONFIG_HAS_FSL_DR_USB #if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index fbadcd17f1..a180b381cf 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -53,8 +53,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM #undef CONFIG_WATCHDOG /* watchdog disabled */ diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index 07f74db089..82b9ff471d 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -388,7 +388,6 @@ * SPL related defines */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_TEXT_BASE 0xfc000000 /* Place BSS for SPL near end of SDRAM */ diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index 79099518e7..6a26269807 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -81,8 +81,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -146,25 +144,6 @@ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_EEPROM_WREN 1 -#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4 - -/* * Flash configuration */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index ee015bb83d..4eb8f39aaf 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -336,29 +336,12 @@ #define CONFIG_CMDLINE_EDITING 1 /* command line history */ -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_I2C_MULTI_BUS - -/* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - /* * IIM - IC Identification Module */ #undef CONFIG_FSL_IIM /* - * EEPROM configuration for Atmel AT24C01: - * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 - -/* * Ethernet configuration */ #define CONFIG_MPC512x_FEC 1 @@ -384,10 +367,6 @@ #define CONFIG_LOADS_ECHO 1 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 -#define CONFIG_CMD_EEPROM -#undef CONFIG_CMD_FUSE -#undef CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 9f35e71d0c..0be310d4a3 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -124,14 +124,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ @@ -160,7 +152,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT #define CONFIG_CMD_NAND /*----------------------------------------------------------------------- diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h new file mode 100644 index 0000000000..6bfc08e5af --- /dev/null +++ b/include/configs/adp-ae3xx.h @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch-ae3xx/ae3xx.h> + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SKIP_TRUNOFF_WATCHDOG + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_PANIC_HANG + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SERVERIP + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x00500000 +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_SEPARATE +#define CONFIG_OF_EMBED +#endif +#else + +#define CONFIG_SYS_TEXT_BASE 0x80000000 +#endif + +/* + * Timer + */ +#define CONFIG_SYS_CLK_FREQ 39062500 +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_FTRTC010_EXTCLK + +#ifndef CONFIG_FTRTC010_EXTCLK +#define CONFIG_FTRTC010_PCLK +#endif + +#ifdef CONFIG_FTRTC010_EXTCLK +#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ +#else +#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ +#endif + +#define TIMER_LOAD_VAL 0xffffffff + +/* + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/* + * Real Time Clock Divider + * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) + */ +#define OSC_5MHZ (5*1000000) +#define OSC_CLK (4*OSC_5MHZ) +#define RTC_DIV_COUNT (0.5) /* Why?? */ + +/* + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#endif +#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ + +/* + * SD (MMC) controller + */ +#define CONFIG_FTSDC010 +#define CONFIG_FTSDC010_NUMBER 1 +#define CONFIG_FTSDC010_SDIO + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * Size of malloc() pool + */ +/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) + +/* + * Physical Memory Map + */ +#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ + +#define PHYS_SDRAM_1 \ + (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ + +#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ + +#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ + GENERATED_GBL_DATA_SIZE) + +/* + * Load address and memory test area should agree with + * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x300000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) + +/* + * Static memory controller configuration + */ +#define CONFIG_FTSMC020 + +#ifdef CONFIG_FTSMC020 +#include <faraday/ftsmc020.h> + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ +#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(1) | \ + FTSMC020_TPR_CTW(1) | \ + FTSMC020_TPR_ATI(1) | \ + FTSMC020_TPR_AT2(1) | \ + FTSMC020_TPR_WTC(1) | \ + FTSMC020_TPR_AHT(1) | \ + FTSMC020_TPR_TRNA(1)) +#endif + +/* + * FLASH on ADP_AG101P is connected to BANK0 + * Just disalbe the other BANK to avoid detection error. + */ +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (0x00) +#define FTSMC020_BANK1_TIMING (0x00) +#endif /* CONFIG_FTSMC020 */ + +/* + * FLASH and environment organization + */ +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL + +/* support JEDEC */ +#ifdef CONFIG_CFI_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#endif + +/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board + */ +#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif +#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} + +/* max number of sectors on one chip */ +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) +#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) +#define CONFIG_ENV_SIZE 8192 +#define CONFIG_ENV_OVERWRITE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +/* Increase max gunzip size */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + +#endif /* __CONFIG_H */ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index b42fcfa8d5..4cef64e3c5 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -20,14 +20,13 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_GENERIC_GLOBAL_DATA +#define CONFIG_CMDLINE_EDITING -/* - * Definitions related to passing arguments to kernel. - */ -#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG /* send initrd params */ +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SERVERIP #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_MEM_REMAP @@ -35,6 +34,10 @@ #ifdef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0x00500000 +#ifdef CONFIG_OF_CONTROL +#undef CONFIG_OF_SEPARATE +#define CONFIG_OF_EMBED +#endif #else #ifdef CONFIG_MEM_REMAP #define CONFIG_SYS_TEXT_BASE 0x80000000 @@ -87,16 +90,12 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 +#endif #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ /* - * Ethernet - */ -#define CONFIG_FTMAC100 - - -/* * SD (MMC) controller */ #define CONFIG_FTSDC010 @@ -348,7 +347,9 @@ * There are 4 banks supported for this Controller, * but we have only 1 bank connected to flash on board */ +#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT #define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} /* max number of sectors on one chip */ @@ -362,4 +363,15 @@ #define CONFIG_ENV_SIZE 8192 #define CONFIG_ENV_OVERWRITE +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ + +/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +/* Increase max gunzip size */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + #endif /* __CONFIG_H */ diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 52f8475669..f320792cfd 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -36,7 +36,6 @@ #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -#define CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP /* SATA Configs */ @@ -55,8 +54,6 @@ #define CONFIG_BOUNCE_BUFFER /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_STORAGE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/alt.h b/include/configs/alt.h index d8a66f2d7d..16525087f1 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -81,7 +81,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 51c3d493c8..0c6d2880da 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -176,7 +176,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -291,6 +290,8 @@ * DM support in SPL */ #ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_DM_MMC_OPS #undef CONFIG_TIMER #undef CONFIG_DM_USB #endif diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index bc0943fdfd..247679eee3 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -262,6 +262,7 @@ */ #ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_MMC +#undef CONFIG_DM_MMC_OPS #undef CONFIG_TIMER #endif diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 6855f62865..2c4033ca59 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -64,7 +64,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 8be49af9f1..eb768b9e97 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -16,9 +16,6 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ - #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ #include <asm/arch/cpu.h> /* get chip and board defs */ @@ -104,7 +101,6 @@ #endif /* CONFIG_USB_AM35X */ /* commands to include */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_NAND /* NAND support */ @@ -253,7 +249,6 @@ /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200800 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 7490f2b5ea..829dd3ecb9 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -13,10 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ - -#define CONFIG_OMAP - #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ @@ -49,9 +45,6 @@ /* Hardware drivers */ -/* OMAP GPIO configuration */ -#define CONFIG_OMAP_GPIO - /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550_SERIAL @@ -307,7 +300,6 @@ /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_TEXT_BASE 0x40200000 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 1feb946834..25f63e8311 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -23,7 +23,6 @@ #endif /* I2C Configuration */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 6962039c3a..b379e0839d 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -31,6 +31,10 @@ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + #define CONFIG_SYS_OMAP_ABE_SYSCK /* Define the default GPT table for eMMC */ diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 01406640b0..450a2ebc11 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -51,8 +51,6 @@ */ #if defined(CONFIG_440) #endif -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO /* diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 8ae3c77942..2284b8bc66 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -33,7 +33,6 @@ #define CONFIG_BOOTCOMMAND "sf probe;" \ "mtdparts default;" \ "bootm 0x9f650000" -#define CONFIG_LZMA #define MTDIDS_DEFAULT "nor0=spi-flash.0" #define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ diff --git a/include/configs/ap143.h b/include/configs/ap143.h index a2c31a2fd5..2950783097 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -37,7 +37,6 @@ #define CONFIG_BOOTCOMMAND "sf probe;" \ "mtdparts default;" \ "bootm 0x9f680000" -#define CONFIG_LZMA #define MTDIDS_DEFAULT "nor0=spi-flash.0" #define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 1cd4d32c6d..b3c22cf4a4 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -14,7 +14,6 @@ #define CONFIG_AP325RXA 1 #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_IDE #define CONFIG_BOOTARGS "console=ttySC2,38400" diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index 5f5882dc8e..440505dd1f 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV #define CONFIG_BOOTARGS "console=ttySC4,115200" @@ -35,20 +34,6 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -/* I2C */ -#define CONFIG_SH_SH7734_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_SYS_MAX_I2C_BUS 2 -#define CONFIG_SYS_I2C_MODULE 0 -#define CONFIG_SYS_I2C_SPEED 400000 /* 400 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x50 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 500000000 -#define CONFIG_SH_I2C_BASE0 0xFFC70000 -#define CONFIG_SH_I2C_BASE1 0xFFC71000 - /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* Monitor Command Prompt */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index c6c956e1ee..2c49729caa 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_MMC_ENV_PART 1 /* USB host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* PCI host support */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index c1c0f592d2..9220d04e79 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* OCOTP Configs */ -#define CONFIG_CMD_FUSE #ifdef CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP #endif @@ -134,7 +133,6 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_CMD_HDMIDETECT #define CONFIG_CONSOLE_MUX #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index e2acc6e8c9..cdb50cc28b 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_MMC_ENV_PART 1 /* USB host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* PCI host support */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 40a82b884b..073f3b4fef 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -54,8 +54,6 @@ /* * U-Boot Commands */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ #define CONFIG_CMD_MTDPARTS /* MTD partition support */ #define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_NAND_LOCK_UNLOCK diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index a4c7847dab..cce39f27c7 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -79,12 +79,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 -#endif - /* Boot Linux */ #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTCOMMAND "run bootcmd_nand" diff --git a/include/configs/aria.h b/include/configs/aria.h index 94f6605d46..0a7ef9919e 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -340,32 +340,12 @@ #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_I2C_MULTI_BUS - -/* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#if 0 -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#endif - /* * IIM - IC Identification Module */ #undef CONFIG_FSL_IIM /* - * EEPROM configuration for Atmel AT24C32A-10TQ-2.7: - * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 - -/* * Ethernet configuration */ #define CONFIG_MPC512x_FEC 1 @@ -392,10 +372,6 @@ #define CONFIG_LOADS_ECHO 1 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 -#define CONFIG_CMD_EEPROM -#undef CONFIG_CMD_FUSE -#undef CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 4d16d33585..7360e11ff1 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -202,8 +202,6 @@ #define CONFIG_RTC_M41T11 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 8899579faa..61989d6bab 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -59,11 +59,7 @@ /* Define which commands should be available at u-boot command prompt */ -#if ENABLE_JFFS -#define CONFIG_CMD_JFFS2 -#endif #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMDLINE_EDITING #define CONFIG_MCFRTC diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index e7b9ad245c..411d7412af 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -197,7 +197,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #define CONFIG_SYS_MASTER_CLOCK 132096000 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 52a051a137..33cc5fc7aa 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -51,7 +51,7 @@ #define CONFIG_CMD_NAND /* - * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0) + * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) * NB: in this case, USB 1.1 devices won't be recognized. */ @@ -99,7 +99,7 @@ /* USB */ #ifdef CONFIG_CMD_USB -#ifndef CONFIG_USB_EHCI +#ifndef CONFIG_USB_EHCI_HCD #define CONFIG_USB_ATMEL #define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW @@ -191,7 +191,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #define CONFIG_SYS_MASTER_CLOCK 132096000 diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 4c27225d84..bf13d937fb 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -74,7 +74,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_JFFS2 #define CONFIG_ATMEL_USART #define CONFIG_MACB diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 64d7c45aad..a7f5e06c68 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -93,7 +93,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_JFFS2 #define CONFIG_ATMEL_USART #define CONFIG_MACB diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 3c03ed3eb1..c8e9340af2 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -95,7 +95,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_JFFS2 #define CONFIG_ATMEL_USART #define CONFIG_MACB diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 768e8fbfa4..66e8cd5e9a 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -100,7 +100,7 @@ /* * Environment settings */ -#define CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE SZ_512 #define CONFIG_ENV_OFFSET 0 diff --git a/include/configs/baltos.h b/include/configs/baltos.h index c65eeedb53..fe4ac05f38 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -229,7 +229,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index 924a351c38..71b1b96ec4 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -330,7 +330,6 @@ DEFAULT_LINUX_BOOT_ENV \ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h index d9b88fa2d3..957cd9e0ba 100644 --- a/include/configs/bcm_ep_board.h +++ b/include/configs/bcm_ep_board.h @@ -67,10 +67,7 @@ #define CONFIG_FAT_WRITE /* SHA hashing */ -#define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 /* Enable Time Command */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h index cc32861169..f3d7a2fad2 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -39,7 +39,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 0c1a54d7ba..521d097f8a 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -20,9 +20,6 @@ #define CONFIG_LCD_DT_SIMPLEFB #define LCD_BPP LCD_COLOR32 -#define CONFIG_HW_WATCHDOG -#define CONFIG_OMAP_WATCHDOG - /* Bootcount using the RTC block */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 #define CONFIG_BOOTCOUNT_LIMIT diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 49f223a32a..99846890e0 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -21,7 +21,7 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4) -#define CONFIG_BMP_24BMP +#define CONFIG_BMP_24BPP #define CONFIG_BMP_32BPP /* memory */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 3742514a6e..7907310084 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -13,7 +13,6 @@ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ #define CONFIG_AM33XX -#define CONFIG_OMAP #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ @@ -76,8 +75,6 @@ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 #define CONFIG_SYS_I2C_OMAP24XX -/* GPIO */ -#define CONFIG_OMAP_GPIO /* * Our platforms make use of SPL to initalize the hardware (primarily @@ -108,7 +105,6 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN /* General parts of the framework, required. */ -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #endif /* ! __BUR_AM335X_COMMON_H__ */ diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 6e2fd33563..f5d108e359 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -299,7 +299,6 @@ /* * U-Boot commands */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_SAVES #ifndef CONFIG_DRIVER_TI_EMAC diff --git a/include/configs/canmb.h b/include/configs/canmb.h index c70979ed1a..b7c74b4264 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -46,7 +46,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IMMAP #define CONFIG_CMD_REGINFO /* diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index a330372d19..b495d0645b 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -261,18 +261,6 @@ #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - -#if defined(CONFIG_ARCHES) -#define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */ -#endif - #if !defined(CONFIG_ARCHES) /* RTC configuration */ #define CONFIG_RTC_M41T62 @@ -373,17 +361,14 @@ * Commands additional to the ones defined in amcc-common.h */ #if defined(CONFIG_ARCHES) -#define CONFIG_CMD_DTT #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM #elif defined(CONFIG_CANYONLANDS) -#define CONFIG_CMD_DTT #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_SATA #define CONFIG_CMD_SDRAM #elif defined(CONFIG_GLACIER) -#define CONFIG_CMD_DTT #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index e338f9bdd2..f1b5a71edf 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -43,7 +43,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 8185926590..fd8df46776 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -38,7 +38,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index e05db3ed8a..cad1357f5c 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -61,8 +61,6 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index f515db038d..20168b22b6 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -188,6 +188,7 @@ */ #ifdef CONFIG_SPL_BUILD #undef CONFIG_DM_MMC +#undef CONFIG_DM_MMC_OPS #undef CONFIG_TIMER #undef CONFIG_DM_USB #endif diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index 3000453563..96e5c9cdd5 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -60,8 +60,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_BUS 3 -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EEPROM_LAYOUT #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_EEPROM_SIZE 256 diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 0c51d2a288..3397aaf2eb 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -24,7 +24,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_PCI /* I2C */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 0073cb5373..3777a0d863 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -21,7 +21,6 @@ /* * Supported commands */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO /* @@ -44,7 +43,7 @@ /* * POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C) +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU) #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) /* List of I2C addresses to be verified by POST */ #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \ @@ -200,16 +199,6 @@ "-(config)" /* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ -#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ -#define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */ - -/* * RTC configuration */ #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index f5f3df3ad6..dd8010cd48 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -258,14 +258,10 @@ #define CONFIG_VIDEO_BMP_LOGO /* EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 256 -#define CONFIG_CMD_EEPROM_LAYOUT -#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3" - #endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 9a8e1302c5..3fb9daebbc 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -153,16 +153,12 @@ /* Status LED polarity is inversed, so init it in the "off" state */ /* EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 256 -#define CONFIG_CMD_EEPROM_LAYOUT -#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3" - #ifndef CONFIG_SPL_BUILD /* * Enable PCA9555 at I2C0-0x26. diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index dfdad6c3d0..ee7c9de969 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -22,8 +22,6 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_SDRC /* The chip has SDRC controller */ @@ -77,8 +75,6 @@ /* USB */ #define CONFIG_USB_OMAP3 -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_USB_MUSB_UDC #define CONFIG_TWL4030_USB @@ -248,14 +244,7 @@ #define CONFIG_SPLASHIMAGE_GUARD -/* GPIO banks */ -#ifdef CONFIG_LED_STATUS -#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ -#endif - /* Display Configuration */ -#define CONFIG_OMAP3_GPIO_2 -#define CONFIG_OMAP3_GPIO_5 #define CONFIG_VIDEO_OMAP3 #define LCD_BPP LCD_COLOR16 @@ -273,7 +262,6 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC @@ -317,14 +305,10 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 256 -#define CONFIG_CMD_EEPROM_LAYOUT -#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index e12dc020ff..dd78b0c7e8 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -13,7 +13,6 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_CM_T3517 /* working with CM-T3517 */ #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -80,15 +79,11 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#define CONFIG_OMAP_GPIO - /* USB */ #define CONFIG_USB_MUSB_AM35X #ifndef CONFIG_USB_MUSB_AM35X #define CONFIG_USB_OMAP3 -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 #else /* !CONFIG_USB_MUSB_AM35X */ @@ -250,14 +245,7 @@ /* Status LED */ #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ -/* GPIO banks */ -#ifdef CONFIG_LED_STATUS -#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ -#endif - /* Display Configuration */ -#define CONFIG_OMAP3_GPIO_2 -#define CONFIG_OMAP3_GPIO_5 #define CONFIG_VIDEO_OMAP3 #define LCD_BPP LCD_COLOR16 @@ -269,14 +257,10 @@ #define CONFIG_OMAP3_SPI /* EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 256 -#define CONFIG_CMD_EEPROM_LAYOUT -#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3" - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 4f44a6752e..1e63098d5f 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -150,14 +150,10 @@ #define CONFIG_SPL_SPI_LOAD /* EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 256 -#define CONFIG_CMD_EEPROM_LAYOUT -#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3" - #endif /* __CONFIG_CM_T43_H */ diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index 477aa07bd8..14042ada7d 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -58,8 +58,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) /* USB UHH support options */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -69,16 +67,12 @@ /* Enabled commands */ /* EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 256 -#define CONFIG_CMD_EEPROM_LAYOUT -#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3" - /* USB Networking options */ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX @@ -86,9 +80,6 @@ #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_MCS7830 -/* Max time to hold reset on this board, see doc/README.omap-reset-time */ -#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 - /* * Miscellaneous configurable options */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 9c4085245a..0882ef8f89 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -52,7 +52,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* OCOTP Configs */ -#define CONFIG_CMD_FUSE #ifdef CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP #endif @@ -115,7 +114,6 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_CMD_HDMIDETECT #define CONFIG_CONSOLE_MUX #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 62a404a7b1..587963963a 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -51,7 +51,6 @@ /* * Bootloader Components Configuration */ -#define CONFIG_CMD_ENV /* I2C support */ #ifdef CONFIG_SYS_I2C diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 023e75cf33..03f6863169 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_I2C_TEGRA /* USB host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index bc1904418d..853cd52878 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -33,7 +33,6 @@ #define CONFIG_SYS_MMC_ENV_PART 1 /* USB host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index c7f174839f..6e8cd914b3 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -20,7 +20,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_CMD_FUSE #ifdef CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP #endif @@ -191,7 +190,6 @@ #endif /* USB Host Support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_VF #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index b52f300af9..6641408fcb 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -185,7 +185,6 @@ #define CONFIG_PCA9698 /* NXP PCA9698 */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -199,8 +198,6 @@ #define CONFIG_SF_DEFAULT_MODE 0 #endif -#define CONFIG_SHA1 - /* * MMC */ @@ -291,7 +288,6 @@ /* * USB */ -#define CONFIG_USB_EHCI #define CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI_FSL @@ -345,8 +341,6 @@ #ifndef CONFIG_TRAILBLAZER -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO /* diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index add5f90cc2..a04af31284 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -17,7 +17,6 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_BOARD_LATE_INIT #define CONFIG_LAST_STAGE_INIT -#define CONFIG_SPL_BOARD_INIT /* * TEXT_BASE needs to be below 16MiB, since this area is scrubbed @@ -33,7 +32,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_I2C #define CONFIG_CMD_PCI #define CONFIG_CMD_SCSI diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f42ba795ea..7bbe31ceea 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -593,8 +593,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI @@ -608,7 +606,6 @@ #define CONFIG_HAS_FSL_MPH_USB #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -619,12 +616,6 @@ #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - /* * Miscellaneous configurable options */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index bb1d0d7715..3847a19cad 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -96,8 +96,6 @@ #define CONFIG_AT91_WANTS_COMMON_PHY /* USB */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 /* USB DFU support */ @@ -150,7 +148,6 @@ #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K) -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_ECC diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 904da1a8ac..a23da191ab 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -411,8 +411,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI @@ -426,7 +424,6 @@ #define CONFIG_HAS_FSL_MPH_USB #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 9442c05943..e0bbf94f0e 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -273,7 +273,6 @@ /* * U-Boot commands */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_SAVES #ifdef CONFIG_CMD_BDI @@ -302,13 +301,11 @@ !defined(CONFIG_USE_SPIFLASH) #define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_ENV #endif #ifndef CONFIG_DIRECT_NOR_BOOT /* defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index f3ff9e7494..96a2df806a 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -35,7 +35,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 6e2561cb5a..699c03f844 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -23,7 +23,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 1cdefa0549..0f0ab01f62 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -24,7 +24,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_PCI /* SPI NOR flash default params, used by sf commands */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 676dfc996b..0890a4db62 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -24,7 +24,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_PCI #define CONFIG_SCSI diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index fc8a3ec7dc..821aa9dec1 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -25,7 +25,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_SATA diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index e788f9c635..9db3380a95 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -69,13 +69,7 @@ #ifdef CONFIG_DBAU1550 -#undef CONFIG_CMD_IDE #undef CONFIG_CMD_PCMCIA - -#else - -#define CONFIG_CMD_IDE - #endif /* diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 6e95064fe1..a8b6802235 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -110,7 +110,6 @@ #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE #define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND /* @@ -181,7 +180,6 @@ /* SPL will use SRAM as stack */ #define CONFIG_SPL_STACK 0x0000FFF8 -#define CONFIG_SPL_BOARD_INIT /* Use the framework and generic lib */ #define CONFIG_SPL_FRAMEWORK diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e72cee0c00..c892b5faa9 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -16,7 +16,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 /* @@ -92,7 +91,6 @@ /* partition */ /* commands to include */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ #undef CONFIG_SUPPORT_RAW_INITRD diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 2b56945dd9..6710507a8d 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -85,9 +85,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ #define CONFIG_CMD_PCI #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SAVES @@ -206,36 +203,6 @@ #define CONFIG_BOOTCOMMAND "run mtcb_start" /* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * RTC configuration - */ -#if defined(CONFIG_DIGSY_REV5) -#define CONFIG_SYS_I2C_RTC_ADDR 0x56 -#define CONFIG_RTC_RV3029 -/* Enable 5k Ohm trickle charge resistor */ -#define CONFIG_SYS_RV3029_TCR 0x20 -#else -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */ -#endif - -/* * Flash configuration */ #define CONFIG_SYS_FLASH_CFI 1 diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index e32651f541..59ba0afb29 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -31,9 +31,6 @@ #define PLLMR0_DEFAULT PLLMR0_266_133_66 #define PLLMR1_DEFAULT PLLMR1_266_133_66 -/* new uImage format support */ -#define CONFIG_FIT_DISABLE_SHA256 - #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ /* @@ -57,9 +54,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IRQ /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) @@ -111,13 +105,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 4 /* Temp sensor/hwmon/dtt */ -#define CONFIG_SYS_DTT_BUS_NUM 4 -#define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */ -#define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\ - { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } -#define CONFIG_DTT_TACH_LIMIT 0xa10 #define CONFIG_SYS_ICS8N3QV01_I2C {1, 3} #define CONFIG_SYS_SIL1178_I2C {0, 2} diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index 2b7d62b034..11397bd8e9 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -29,9 +29,6 @@ #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -/* new uImage format support */ -#define CONFIG_FIT_DISABLE_SHA256 - #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ /* @@ -55,9 +52,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IRQ /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 9450b62e4a..470e26256a 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -28,9 +28,7 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_NAND -#define CONFIG_CMD_IDE #define CONFIG_SYS_MVFS #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 69429ed34e..3b56fd6739 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -23,7 +23,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_NAND /* * mv-common.h should be defined after CMD configs since it used them @@ -80,7 +79,6 @@ /* * File system */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBIFS #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index a9ca0231f5..17608a54cd 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -41,6 +41,10 @@ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + #define CONFIG_SYS_OMAP_ABE_SYSCK #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/draco.h b/include/configs/draco.h index 896d14f99a..ba6a43062a 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -45,9 +45,6 @@ #define CONFIG_FACTORYSET -/* Watchdog */ -#define CONFIG_OMAP_WATCHDOG - /* Define own nand partitions */ #define CONFIG_ENV_OFFSET_REDUND 0x2E0000 #define CONFIG_ENV_SIZE_REDUND 0x2000 diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index b97c6c4240..11c842d952 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -46,7 +46,6 @@ #define CONFIG_USB_ETHER_SMSC95XX /* Extra Commands */ -#define CONFIG_CMD_ENV /* Enable that for switching of boot partitions */ /* Disabled by default as some sub-commands can brick eMMC */ /*#define CONFIG_SUPPORT_EMMC_BOOT */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index d1d4bf0156..aaba5d8eab 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -23,7 +23,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV /* I2C */ #define CONFIG_SYS_I2C @@ -74,8 +73,6 @@ #endif #if !defined(CONFIG_USB_XHCI_HCD) -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MARVELL #define CONFIG_EHCI_IS_TDI #endif diff --git a/include/configs/duovero.h b/include/configs/duovero.h index 4bb81e5d9c..f142231689 100644 --- a/include/configs/duovero.h +++ b/include/configs/duovero.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS /* USB UHH support options */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index b6a758f0b2..f88045436f 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -33,7 +33,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB2.0 Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 3a5b5c7285..53ee1adc0b 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -128,7 +128,6 @@ /* * U-Boot commands */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_SAVES #ifdef CONFIG_CMD_BDI @@ -169,7 +168,6 @@ !defined(CONFIG_USE_SPIFLASH) #define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_ENV #endif /* additions for new relocation code, must added to all boards */ diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h index 03cc74c596..3d7a168bc4 100644 --- a/include/configs/eco5pk.h +++ b/include/configs/eco5pk.h @@ -15,8 +15,6 @@ #include "tam3517-common.h" -#undef CONFIG_USB_EHCI -#undef CONFIG_USB_EHCI_OMAP #undef CONFIG_USB_OMAP3 /* Our console port is port3 */ diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index f8fb97b08e..2404441860 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV #define CONFIG_BOOTARGS "console=ttySC0,115200" diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 2fc85983e0..def28f2cf1 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -76,7 +76,6 @@ #define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ /* Monitor configuration */ -#define CONFIG_CMD_JFFS2 #define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index f7ac3027dd..cc5cc7bac6 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x00040000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_UBOOT_BASE 0xfff90000 #define CONFIG_SYS_UBOOT_START 0x00800000 #define CONFIG_SYS_TEXT_BASE 0x00800000 @@ -120,7 +119,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_IDE /* * Network @@ -141,7 +139,7 @@ /* * IDE */ -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define __io #define CONFIG_IDE_PREINIT /* ED Mini V has an IDE-compatible SATA connector for port 1 */ @@ -171,8 +169,6 @@ * Common USB/EHCI configuration */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_MARVELL #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE #define CONFIG_SUPPORT_VFAT #endif /* CONFIG_CMD_USB */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 68d48b2e6a..749a9e3bc1 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/espt.h b/include/configs/espt.h index ace71862dd..845bcc1c9a 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -18,7 +18,6 @@ * Command line configuration. */ #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 40c57948cc..a0152a4a43 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -116,9 +116,6 @@ #define CONFIG_SYS_DCACHE_OFF #endif -/* Watchdog */ -#define CONFIG_OMAP_WATCHDOG - /* Define own nand partitions */ #define CONFIG_ENV_OFFSET_REDUND 0xB80000 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 481051c9c6..e7f7a7cbe6 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -84,7 +84,6 @@ #define CONFIG_AT91_GPIO /* Command line configuration */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_NAND diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 5411e5ff49..6915dc1a48 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -26,7 +26,6 @@ /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA -#define CONFIG_SHA_HW_ACCEL /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD @@ -42,12 +41,8 @@ /* select serial console configuration */ #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_CMD_HASH - /* Thermal Management Unit */ #define CONFIG_EXYNOS_TMU -#define CONFIG_CMD_DTT -#define CONFIG_TMU_CMD_DTT /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 @@ -137,10 +132,7 @@ #endif /*CONFIG_CMD_NET*/ /* SHA hashing */ -#define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 /* Enable Time Command */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index aee9fea9da..8e8cdf359b 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index fee46add80..7e03dd63ee 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -147,7 +147,6 @@ * Commands additional to the ones defined in amcc-common.h */ #define CONFIG_CMD_PCI -#undef CONFIG_CMD_EEPROM /* * PCI stuff diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 776910c6cd..f60a0298d6 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -47,7 +47,6 @@ #define CONFIG_MXC_GPIO #define CONFIG_MXC_UART -#define CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP /* SATA Configs */ @@ -68,8 +67,6 @@ /* USB Configs */ #ifdef CONFIG_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index f9bced3f8f..d1635b098e 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -43,9 +43,7 @@ * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_NAND -#define CONFIG_CMD_IDE #define CONFIG_SYS_MVFS /* Picks up Filesystem from mv-common.h */ /* diff --git a/include/configs/gose.h b/include/configs/gose.h index 8956841fbe..8a1d6d3407 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -78,7 +78,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 3ec7649a1d..f2260eae56 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -82,7 +82,6 @@ #define CONFIG_ENV_SIZE 0x4000 #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_ARMADA100 #define CONFIG_EHCI_IS_TDI #endif /* CONFIG_CMD_USB */ diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index abc4214bc0..83b78907f2 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -86,7 +86,6 @@ * Command line configuration. */ /* add useful commands */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO #define CONFIG_AUTO_COMPLETE diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 92eded6cda..2227eead62 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -8,7 +8,6 @@ #define __CONFIG_H /* SPL */ -#define CONFIG_SPL_BOARD_INIT /* Location in NAND to read U-Boot from */ #define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M) @@ -141,9 +140,6 @@ #define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ -#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ -#define CONFIG_CMD_GSC -#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ #define CONFIG_CMD_UNZIP /* gzwrite */ #define CONFIG_RBTREE @@ -156,8 +152,6 @@ #define CONFIG_ARP_TIMEOUT 200UL /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_SMSC95XX @@ -178,7 +172,6 @@ #define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_LOGO #define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_CMD_HDMIDETECT #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP #define CONFIG_VIDEO_BMP_LOGO diff --git a/include/configs/h2200.h b/include/configs/h2200.h index d8724f86a7..530a88e9e1 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -109,7 +109,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } -#define CONFIG_FIT_DISABLE_SHA256 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 1a5d4b1dd5..c17d7fad79 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 584ce52bd0..0fb6fb3b60 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -73,7 +73,6 @@ #define CONFIG_FS_EXT4 /* Command line configuration */ -#define CONFIG_CMD_ENV #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 5574e7715a..405129b7e2 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -26,9 +26,6 @@ #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#define CONFIG_CMD_FPGAD -#define CONFIG_CMD_IOLOOP - /* * System Clock Setup */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 2cf0027d9c..a5782f3300 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -23,13 +23,11 @@ * Compression configuration */ #define CONFIG_BZIP2 -#define CONFIG_LZMA /* * Commands configuration */ #define CONFIG_SYS_MVFS -#define CONFIG_CMD_IDE /* * mv-common.h should be defined after CMD configs since it used them @@ -88,14 +86,14 @@ /* * SATA driver configuration */ -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define __io #define CONFIG_IDE_PREINIT #define CONFIG_MVSATA_IDE_USE_PORT0 #define CONFIG_MVSATA_IDE_USE_PORT1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ /* * RTC driver configuration diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index 950a7195fd..63e50606d7 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -25,14 +25,12 @@ * Compression configuration */ #define CONFIG_BZIP2 -#define CONFIG_LZMA #define CONFIG_LZO /* * Commands configuration */ #define CONFIG_SYS_MVFS -#define CONFIG_CMD_ENV #define CONFIG_CMD_NAND /* @@ -88,7 +86,6 @@ /* * File system */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBIFS #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 6b6bbbd5c0..7bedcb94d7 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -165,7 +165,6 @@ #define CONFIG_TSEC2 #define CONFIG_TSEC_ENET #define CONFIG_HARD_SPI -#define CONFIG_HARD_I2C /* * NOR FLASH setup @@ -414,7 +413,6 @@ */ #define CONFIG_CMD_NAND #define CONFIG_CMDLINE_EDITING -#define CONFIG_CMD_JFFS2 #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME @@ -445,7 +443,6 @@ #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" #define CONFIG_FDTFILE "ids8313/ids8313.dtb" #define CONFIG_LOADADDR 0x400000 -#define CONFIG_CMD_ENV_FLAGS #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" /* Initial Memory map for Linux*/ @@ -542,8 +539,5 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x9 #define CONFIG_IMAGE_FORMAT_LEGACY -#define CONFIG_CMD_HASH -#define CONFIG_SHA1 -#define CONFIG_SHA256 #endif /* __CONFIG_H */ diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index b8a867c7ba..18d8d2fd3d 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -159,7 +159,6 @@ /* * U-Boot commands */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 0a66720a7d..739af03e88 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -48,7 +48,6 @@ /*********************************************************** * Command definition ***********************************************************/ -#define CONFIG_CMD_EEPROM #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \ diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index 5a28b15afc..741bdfa807 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -42,12 +42,9 @@ "fit_image=fit.itb\0" \ "console=ttymxc3\0" \ "fdt_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ - "mmcdev=0\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ @@ -64,7 +61,7 @@ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ - "mmcboot=echo Booting from mmc ...; " \ + "_mmcboot=run mmcargs; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ @@ -79,6 +76,20 @@ "else " \ "bootm; " \ "fi\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadfit; then " \ + "run fitboot; " \ + "else " \ + "if run loadimage; then " \ + "run _mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi\0" \ "nandboot=echo Booting from nand ...; " \ "if mtdparts; then " \ "echo Starting nand boot ...; " \ @@ -90,25 +101,7 @@ "nand read ${fdt_addr} dtb 0x100000; " \ "bootm ${loadaddr} - ${fdt_addr}\0" -#ifdef CONFIG_NAND_MXS -# define CONFIG_BOOTCOMMAND "run nandboot" -#else -# define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadfit; then " \ - "run fitboot; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi" -#endif +#define CONFIG_BOOTCOMMAND "run $modeboot" /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 @@ -133,8 +126,6 @@ /* FIT */ #ifdef CONFIG_FIT # define CONFIG_HASH_VERIFY -# define CONFIG_SHA1 -# define CONFIG_SHA256 # define CONFIG_IMAGE_FORMAT_LEGACY #endif diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h index 3358320e66..f52865b5a0 100644 --- a/include/configs/imx6qdl_icore_rqs.h +++ b/include/configs/imx6qdl_icore_rqs.h @@ -37,7 +37,6 @@ "fit_image=fit.itb\0" \ "console=ttymxc3\0" \ "fdt_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "mmcpart=1\0" \ @@ -109,8 +108,6 @@ /* FIT */ #ifdef CONFIG_FIT # define CONFIG_HASH_VERIFY -# define CONFIG_SHA1 -# define CONFIG_SHA256 # define CONFIG_IMAGE_FORMAT_LEGACY #endif diff --git a/include/configs/imx6ul_geam.h b/include/configs/imx6ul_geam.h index 8bffacde4d..2e12b97767 100644 --- a/include/configs/imx6ul_geam.h +++ b/include/configs/imx6ul_geam.h @@ -41,12 +41,9 @@ "fit_image=fit.itb\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x87800000\0" \ "boot_fdt=try\0" \ - "mmcdev=0\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ @@ -63,7 +60,7 @@ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ - "mmcboot=echo Booting from mmc ...; " \ + "_mmcboot=run mmcargs; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ @@ -78,6 +75,20 @@ "else " \ "bootm; " \ "fi\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadfit; then " \ + "run fitboot; " \ + "else " \ + "if run loadimage; then " \ + "run _mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi\0" \ "nandboot=echo Booting from nand ...; " \ "if mtdparts; then " \ "echo Starting nand boot ...; " \ @@ -89,24 +100,7 @@ "nand read ${fdt_addr} dtb 0x100000; " \ "bootm ${loadaddr} - ${fdt_addr}\0" -#ifdef CONFIG_NAND_MXS -# define CONFIG_BOOTCOMMAND "run nandboot" -#else -# define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadfit; then " \ - "run fitboot; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi" -#endif +#define CONFIG_BOOTCOMMAND "run $modeboot" /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 @@ -131,8 +125,6 @@ /* FIT */ #ifdef CONFIG_FIT # define CONFIG_HASH_VERIFY -# define CONFIG_SHA1 -# define CONFIG_SHA256 # define CONFIG_IMAGE_FORMAT_LEGACY #endif diff --git a/include/configs/imx6ul_isiot.h b/include/configs/imx6ul_isiot.h index 4009648628..76ae159da3 100644 --- a/include/configs/imx6ul_isiot.h +++ b/include/configs/imx6ul_isiot.h @@ -42,7 +42,6 @@ "splashpos=m,m\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x87800000\0" \ "boot_fdt=try\0" \ "mmcpart=1\0" \ @@ -126,8 +125,6 @@ /* FIT */ #ifdef CONFIG_FIT # define CONFIG_HASH_VERIFY -# define CONFIG_SHA1 -# define CONFIG_SHA256 # define CONFIG_IMAGE_FORMAT_LEGACY #endif diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 5ee9c2bcb4..d651eff4b2 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -72,7 +72,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE #define CONFIG_CMD_PCI #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ @@ -219,86 +218,6 @@ #define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444 /* - * RTC configuration - */ -#define CONFIG_RTC_RTC4543 1 /* use external RTC */ - -/* - * Software (bit-bang) three wire serial configuration - * - * Note that we need the ifdefs because otherwise compilation of - * mkimage.c fails. - */ -#define CONFIG_SOFT_TWS 1 - -#ifdef TWS_IMPLEMENTATION -#include <mpc5xxx.h> -#include <asm/io.h> - -#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */ -#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */ -#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */ -#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */ - -static inline void tws_ce(unsigned bit) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - if (bit) - setbits_8(&wu_gpio->dvo, TWS_CE); - else - clrbits_8(&wu_gpio->dvo, TWS_CE); -} - -static inline void tws_wr(unsigned bit) -{ - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - if (bit) - setbits_8(&wu_gpio->dvo, TWS_WR); - else - clrbits_8(&wu_gpio->dvo, TWS_WR); -} - -static inline void tws_clk(unsigned bit) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - if (bit) - setbits_8(&gpio->sint_dvo, TWS_CLK); - else - clrbits_8(&gpio->sint_dvo, TWS_CLK); -} - -static inline void tws_data(unsigned bit) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - if (bit) - setbits_8(&gpio->sint_dvo, TWS_DATA); - else - clrbits_8(&gpio->sint_dvo, TWS_DATA); -} - -static inline unsigned tws_data_read(void) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - return !!(in_8(&gpio->sint_ival) & TWS_DATA); -} - -static inline void tws_data_config_output(unsigned output) -{ - struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - if (output) - setbits_8(&gpio->sint_ddr, TWS_DATA); - else - clrbits_8(&gpio->sint_ddr, TWS_DATA); -} -#endif /* TWS_IMPLEMENTATION */ - -/* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ diff --git a/include/configs/intip.h b/include/configs/intip.h index f1f840923b..036fd20eb4 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -218,13 +218,6 @@ #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 -/* I2C SYSMON */ -#define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ -#define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 50, 20 }, { 60, 40 } } -#define CONFIG_DTT_TACH_LIMIT 0xa10 - /* RTC configuration */ #define CONFIG_RTC_DS1337 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 @@ -272,7 +265,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM diff --git a/include/configs/io.h b/include/configs/io.h index 3e44a8c607..3fde912bcf 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -31,9 +31,6 @@ #define PLLMR0_DEFAULT PLLMR0_266_133_66 #define PLLMR1_DEFAULT PLLMR1_266_133_66 -/* new uImage format support */ -#define CONFIG_FIT_DISABLE_SHA256 - #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ /* @@ -57,9 +54,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IRQ /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) @@ -93,11 +87,6 @@ #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 /* Temp sensor/hwmon/dtt */ -#define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ -#define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 50, 20 }, { 60, 40 } } -#define CONFIG_DTT_TACH_LIMIT 0xa10 /* * FLASH organization diff --git a/include/configs/io64.h b/include/configs/io64.h index 8e754fc10b..1b58f04540 100644 --- a/include/configs/io64.h +++ b/include/configs/io64.h @@ -327,14 +327,6 @@ #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 -/* Temp sensor/hwmon/dtt */ -#define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */ -#define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ - { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } -#define CONFIG_DTT_TACH_LIMIT 0xa10 - /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ @@ -373,7 +365,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 9c3be78bc7..99e920b46a 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -33,9 +33,6 @@ #define PLLMR0_DEFAULT PLLMR0_266_133_66 #define PLLMR1_DEFAULT PLLMR1_266_133_66 -/* new uImage format support */ -#define CONFIG_FIT_DISABLE_SHA256 - #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ /* @@ -57,9 +54,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_FPGAD -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IRQ /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 5caf02e8d9..a3c0cfa60a 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -241,7 +241,6 @@ /* * U-Boot commands */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_SAVES #ifdef CONFIG_CMD_BDI @@ -273,7 +272,6 @@ /* defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index aff4adf5d0..c6390dbdbe 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -88,8 +88,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE /* IDE harddisk support */ -#define CONFIG_CMD_IRQ /* irqinfo */ #define CONFIG_CMD_PCI /* pciinfo */ #define CONFIG_SYS_LOWBOOT 1 @@ -150,29 +148,6 @@ #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - #define CONFIG_SYS_FLASH_BASE 0xFC000000 #define CONFIG_SYS_FLASH_SIZE 0x01000000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index b31ba6a4ee..89f6cbc85b 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -34,7 +34,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 0d97317c7f..4461623118 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -127,25 +127,6 @@ #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" #endif -#if 0 -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 -#endif - /* * Flash configuration */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 3143b631ce..3f39a26d3b 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -123,31 +123,6 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ -/* I2C DTT */ -#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ -#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ -/* - * standard dtt sensor configuration - bottom bit will determine local or - * remote sensor of the ADM1021, the rest determines index into - * CONFIG_SYS_DTT_ADM1021 array below. - */ -#define CONFIG_DTT_SENSORS { 0, 1 } - -/* - * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). - * there will be one entry in this array for each two (dummy) sensors in - * CONFIG_DTT_SENSORS. - * - * For Katmai board: - * - only one ADM1021 - * - i2c addr 0x18 - * - conversion rate 0x02 = 0.25 conversions/second - * - ALERT ouput disabled - * - local temp sensor enabled, min set to 0 deg, max set to 85 deg - * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg - */ -#define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } - /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -170,7 +145,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM diff --git a/include/configs/kc1.h b/include/configs/kc1.h index 85bc0e3fb7..408e5634b6 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -24,13 +24,6 @@ #define CONFIG_SYS_PL310_BASE 0x48242000 /* - * Platform - */ - -#define CONFIG_OMAP -#define CONFIG_OMAP4430 - -/* * Board */ @@ -61,12 +54,6 @@ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) /* - * GPIO - */ - -#define CONFIG_OMAP_GPIO - -/* * I2C */ @@ -103,7 +90,6 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT /* * Console diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 1f5c2ad234..a91a6a9ee5 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -317,11 +317,6 @@ #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 -/* Standard DTT sensor configuration */ -#define CONFIG_DTT_DS1775 1 -#define CONFIG_DTT_SENSORS { 0 } -#define CONFIG_SYS_I2C_DTT_ADDR 0x48 - /* RTC configuration */ #define CONFIG_RTC_DS1338 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 872e2b3403..c2b38d8af6 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -13,9 +13,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MTDPARTS #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 8293607c9c..0d50538a8e 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -14,7 +14,6 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_CMD_DTT #define CONFIG_JFFS2_CMDLINE /* standard km ethernet_present for piggy */ diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 35ec0972bf..7d69224bd1 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -215,13 +215,6 @@ #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/ -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM 1 - #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 9bfcfdefe9..664a64c55a 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -370,7 +370,6 @@ int get_scl(void); * additionnal command line configuration. */ #define CONFIG_CMD_PCI -#define CONFIG_CMD_ERRATA /* we don't need flash support */ #undef CONFIG_FLASH_CFI_MTD diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h index aeece20bda..09c3aa9ca8 100644 --- a/include/configs/km82xx.h +++ b/include/configs/km82xx.h @@ -268,13 +268,6 @@ int get_sda(void); int get_scl(void); #endif -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_HYSTERESIS 3 -#define CONFIG_SYS_DTT_BUS_NUM 2 - #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_IMMR 0xF0000000 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 1ca564f983..2166e2c8f2 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -78,7 +78,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 9e9d879541..66e65c878c 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -43,8 +43,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_IDE #ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */ #endif @@ -120,7 +118,6 @@ */ #ifdef CONFIG_CMD_I2C /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ diff --git a/include/configs/lager.h b/include/configs/lager.h index b619d153c9..bf1352d941 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -80,7 +80,6 @@ #define CONFIG_SYS_TMU_CLK_DIV 4 /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 2294106802..016d54f138 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -137,8 +137,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_STORAGE #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 861cbc3299..bd9b0d30a5 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -84,7 +84,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* Command line configuration */ -#define CONFIG_CMD_ENV #undef CONFIG_CMD_IMLS #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 8d7e54305d..5b8500b91b 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -61,7 +61,6 @@ /* EEPROM */ #define CONFIG_ID_EEPROM -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@ -115,7 +114,6 @@ /*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 35d17b96f4..d6839c0916 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -305,16 +305,6 @@ #define CONFIG_MISC_INIT_R -/* Hash command with SHA acceleration supported in hardware */ - -#ifdef CONFIG_FSL_CAAM - -#define CONFIG_CMD_HASH - -#define CONFIG_SHA_HW_ACCEL - -#endif - #include <asm/fsl_secure_boot.h> #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5fcaf857fb..8cf4eaa021 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -402,7 +402,6 @@ unsigned long get_board_ddr_clk(void); /*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -571,12 +570,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MISC_INIT_R -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #include <asm/fsl_secure_boot.h> #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 2a20dec9ab..f0033b85d8 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -40,7 +40,6 @@ /*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif @@ -435,12 +434,6 @@ #define CONFIG_MISC_INIT_R -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #include <asm/fsl_secure_boot.h> #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 05419fe9fb..1b0106d5ab 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -174,9 +174,6 @@ #endif /* Command line configuration */ -#ifndef SPL_NO_ENV -#define CONFIG_CMD_ENV -#endif /* MMC */ #ifndef SPL_NO_MMC @@ -301,10 +298,4 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 47a544c90c..b66b8ac72c 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -149,9 +149,6 @@ #endif /* Command line configuration */ -#ifndef SPL_NO_ENV -#define CONFIG_CMD_ENV -#endif /* MMC */ #ifndef SPL_NO_MMC @@ -240,10 +237,4 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 7b73139879..b044768883 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -167,7 +167,6 @@ unsigned long long get_qixis_addr(void); #endif /* Command line configuration */ -#define CONFIG_CMD_ENV /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) @@ -237,10 +236,4 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#endif - #endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 84e9db2648..d0b0aa93e4 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -327,7 +327,6 @@ unsigned long get_board_ddr_clk(void); /* EEPROM */ #define CONFIG_ID_EEPROM -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index c20a7f437c..2dab065be1 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -321,7 +321,6 @@ unsigned long get_board_sys_clk(void); /* EEPROM */ #define CONFIG_ID_EEPROM -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index ce6d7c9998..43e4a325b4 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -38,8 +38,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_IDE /* * mv-common.h should be defined after CMD configs since it used them @@ -147,7 +145,7 @@ #undef CONFIG_RESET_PHY_R #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #undef CONFIG_IDE_LED #undef CONFIG_SYS_IDE_MAXBUS #define CONFIG_SYS_IDE_MAXBUS 1 diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 911192da7a..8971096a98 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -362,7 +362,6 @@ /* * USB/EHCI */ -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 #define CONFIG_EHCI_MMIO_BIG_ENDIAN @@ -382,8 +381,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index f6fa599e6b..c4717238bb 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -16,7 +16,6 @@ /* U-Boot Commands */ #define CONFIG_FAT_WRITE -#define CONFIG_CMD_EEPROM #define CONFIG_CMD_NAND #define CONFIG_CMD_NAND_TRIMFFS @@ -63,11 +62,6 @@ #define CONFIG_FEC_MXC #endif -/* EEPROM */ -#ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#endif - /* RTC */ #ifdef CONFIG_CMD_DATE /* Use the internal RTC in the MXS chip */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index d85de5fa17..b237cea1da 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -162,7 +162,6 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX5 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX @@ -219,7 +218,6 @@ */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_TEXT_BASE 0x70008000 #define CONFIG_SPL_PAD_TO 0x8000 #define CONFIG_SPL_STACK 0x70004000 diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h index db58f735bc..6dc1fb047e 100644 --- a/include/configs/ma5d4evk.h +++ b/include/configs/ma5d4evk.h @@ -102,8 +102,6 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 /* USB device */ @@ -208,7 +206,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #define CONFIG_SPL_SPI_LOAD diff --git a/include/configs/makalu.h b/include/configs/makalu.h index da5cfa19d3..a92bc43538 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -189,11 +189,6 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* Standard DTT sensor configuration */ -#define CONFIG_DTT_DS1775 1 -#define CONFIG_DTT_SENSORS { 0 } -#define CONFIG_SYS_I2C_DTT_ADDR 0x48 - /* RTC configuration */ #define CONFIG_RTC_X1205 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f @@ -232,7 +227,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT #define CONFIG_CMD_PCI /* POST support */ diff --git a/include/configs/malta.h b/include/configs/malta.h index fcee37400d..1f977cb71a 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -101,7 +101,6 @@ /* * Commands */ -#define CONFIG_CMD_IDE #define CONFIG_CMD_PCI #define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h new file mode 100644 index 0000000000..68874dc029 --- /dev/null +++ b/include/configs/manroland/mpc5200-common.h @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2009 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MANROLAND_MPC52XX__COMMON_H +#define __MANROLAND_MPC52XX__COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5200 1 /* MPC5200 CPU */ + +/* ... running at 33.000000MHz */ +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\ + 230400 } + +#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */ +# define CONFIG_SYS_LOWBOOT 1 +#endif + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ + +/* + * Flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xFF800000 + +#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ + +#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_AMD_RESET + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ +#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE +#else +#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 +#endif + +#define CONFIG_SYS_MONITOR_LEN (192 << 10) +#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/*use Hardware WDT */ +#define CONFIG_HW_WATCHDOG + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Various low-level settings + */ +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE + +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +/* 8Mbit SRAM @0x80100000 */ +#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE + +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ + +#define CONFIG_IDE_PREINIT 1 + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 + +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#define CONFIG_ATAPI 1 + +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" +#define CONFIG_OF_IDE_FIXUP + +#endif /* __MANROLAND_MPC52XX__COMMON_H */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index cdb3a473ea..b82a684cc9 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -23,7 +23,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV /* I2C */ #define CONFIG_SYS_I2C diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 9e5c29f92f..fca1af9d2b 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -14,7 +14,6 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #include "imx6_spl.h" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) #define CONFIG_SPL_OS_BOOT @@ -98,8 +97,6 @@ "128k@0x19C0000(swupdate-kernel-dtb.nor)" /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_STORAGE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mcx.h b/include/configs/mcx.h index e4f2a02dcf..0c237a59cb 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -12,9 +12,6 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP3_MCX /* working with mcx */ -#define CONFIG_OMAP_GPIO #define CONFIG_MACH_TYPE MACH_TYPE_MCX @@ -76,10 +73,6 @@ 115200} /* EHCI */ -#define CONFIG_OMAP3_GPIO_2 -#define CONFIG_OMAP3_GPIO_5 -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER @@ -87,7 +80,6 @@ #define CONFIG_USB_ETHER_MCS7830 /* commands to include */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_UBIFS @@ -296,7 +288,6 @@ /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 1a9cb675df..17a97dfc3a 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -241,27 +241,12 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ -#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ - /* * IIM - IC Identification Module */ #undef CONFIG_FSL_IIM /* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ -#define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */ - -/* * Ethernet configuration */ #define CONFIG_MPC512x_FEC 1 @@ -280,7 +265,7 @@ /* * Environment */ -#define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */ +#define CONFIG_ENV_IS_NOWHERE /* Store env in I2C EEPROM */ #define CONFIG_ENV_SIZE 0x1000 #define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */ @@ -288,10 +273,6 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_EEPROM -#undef CONFIG_CMD_FUSE -#undef CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index b9b666fd3e..d2165828d3 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -29,7 +29,6 @@ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ /* USB host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index f1734c0e21..12a4dfce6b 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -26,8 +26,6 @@ #define GICD_BASE 0xc4301000 #define GICC_BASE 0xc4302000 -#define CONFIG_CMD_ENV - /* Monitor Command Prompt */ /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index e8fe2f673c..cc7f81955e 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -168,11 +168,9 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL #if defined(FLASH) -# define CONFIG_CMD_JFFS2 # undef CONFIG_CMD_UBIFS # if !defined(RAMENV) @@ -186,7 +184,6 @@ # define CONFIG_CMD_SAVES # endif #else -# undef CONFIG_CMD_JFFS2 # undef CONFIG_CMD_UBIFS #endif #endif @@ -275,7 +272,6 @@ /* SPL part */ #define CONFIG_CMD_SPL #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 136db0dd26..75633f66ef 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -33,11 +33,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO /* @@ -256,21 +251,6 @@ #define CONFIG_SYS_ATA_STRIDE 4 /* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* select I2C module #2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ - -/* * RTC configuration */ #define CONFIG_RTC_DS1337 1 @@ -284,12 +264,6 @@ #define LED_ON 0x00000010 /* - * Temperature sensor - */ -#define CONFIG_DTT_LM75 1 -#define CONFIG_DTT_SENSORS { 0x49 } - -/* * Environment settings */ #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index dafb724e3f..e11a0e628a 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -327,29 +327,12 @@ #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#if 0 -#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ -#endif - /* * IIM - IC Identification Module */ #undef CONFIG_FSL_IIM /* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ - -/* * Ethernet configuration */ #define CONFIG_MPC512x_FEC 1 @@ -369,7 +352,6 @@ */ #if defined(CONFIG_CMD_USB) -#define CONFIG_USB_EHCI /* Enable EHCI Support */ #define CONFIG_USB_EHCI_FSL /* On a FSL platform */ #define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */ #define CONFIG_EHCI_DESC_BIG_ENDIAN @@ -396,13 +378,8 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_REGINFO -#undef CONFIG_CMD_FUSE - #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif @@ -433,10 +410,10 @@ "1m(u-boot);" \ "mpc5121.nand:-(data)" -#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) +#if defined(CONFIG_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) #define CONFIG_SUPPORT_VFAT -#endif /* defined(CONFIG_CMD_IDE) */ +#endif /* defined(CONFIG_IDE) */ /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index 0015be980b..2855c00723 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -14,7 +14,6 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_IDE #define CONFIG_BOOTARGS "console=ttySC0,115200" #define CONFIG_BOOTFILE "/boot/zImage" diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 26472e9474..de6e58a71e 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -12,7 +12,6 @@ #define CONFIG_CPU_SH7722 1 #define CONFIG_MS7722SE 1 -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_SDRAM #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index dfebde20ec..ed83eeba54 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -24,7 +24,6 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_AUTO_COMPLETE -#define CONFIG_OMAP3_GPIO_4 #define CONFIG_HOSTNAME mt_ventoux /* @@ -40,7 +39,6 @@ /* * FPGA */ -#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_FPGA #define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 diff --git a/include/configs/munices.h b/include/configs/munices.h index 1679430951..ad2d69e6a5 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -26,7 +26,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IMMAP #define CONFIG_CMD_REGINFO #if defined(CONFIG_CMD_KGDB) diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 814f0dd7ca..13bd6cff3d 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -121,7 +121,6 @@ * Common USB/EHCI configuration */ #if defined(CONFIG_CMD_USB) && !defined(CONFIG_DM) -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ #define CONFIG_SUPPORT_VFAT #endif /* CONFIG_CMD_USB */ @@ -129,7 +128,6 @@ * File system */ #ifdef CONFIG_SYS_MVFS -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBIFS #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h index 83c559ed66..a2f68ad70a 100644 --- a/include/configs/mv-plug-common.h +++ b/include/configs/mv-plug-common.h @@ -22,14 +22,11 @@ */ #ifdef CONFIG_SYS_MVFS #define CONFIG_BZIP2 -#define CONFIG_LZMA #endif /* CONFIG_SYS_MVFS */ /* * Commands configuration */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_IDE /* * Extra file system diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index a11a491fe6..8949ee64db 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -102,6 +102,10 @@ /* RTC */ #define CONFIG_RTC_IMXDI +/* Fuse API support */ +#define CONFIG_FSL_IIM +#define CONFIG_CMD_FUSE + /* Ethernet Configs */ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 79d92bb06a..e60b96f7dc 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -199,7 +199,6 @@ #define CONFIG_SYS_NAND_LARGEPAGE /* EHCI driver */ -#define CONFIG_USB_EHCI #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #define CONFIG_EHCI_IS_TDI #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index dfd7ea9d45..4513adf2c4 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -33,7 +33,6 @@ * Hardware drivers */ #define CONFIG_FSL_IIM -#define CONFIG_CMD_FUSE #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE @@ -73,7 +72,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX5 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 3094402d15..151c4b3faf 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -45,7 +45,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX5 #define CONFIG_USB_STORAGE #define CONFIG_USB_HOST_ETHER diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 945be5835b..1b6d868d04 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -42,7 +42,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1F /* USB Configs */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX5 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 21ac3fc357..1a8ab4ee33 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -78,7 +78,6 @@ #define CONFIG_FSL_USDHC /* Fuses */ -#define CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP /* Secure boot (HAB) support */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 84fdf656cd..bc22f56d1d 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -40,12 +40,9 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IMX_HDMI -#define CONFIG_CMD_HDMIDETECT #define CONFIG_IMX_VIDEO_SKIP /* USB */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 9f42735571..de5dc1c451 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -128,8 +128,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index ef7675c688..635c04acf9 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -15,8 +15,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 598ab9aa2e..a8c0e03582 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -63,8 +63,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 2fff7995ea..6ab76bb8fa 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -159,8 +159,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 971f6c2f31..3e73dad9a3 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -149,8 +149,6 @@ #define CONFIG_PHY_ATHEROS #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index dafa946e47..b39ab729d8 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -167,8 +167,6 @@ #define CONFIG_PHY_ATHEROS #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 240d3a226c..2c40decf49 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -186,8 +186,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 9a20c7732d..fe460109d1 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -59,7 +59,6 @@ #define CONFIG_FSL_USDHC /* Fuses */ -#define CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP #define CONFIG_ARMV7_SECURE_BASE 0x00900000 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 9c3cec1992..39291a2ffd 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -34,20 +34,12 @@ /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - #undef CONFIG_BOOTM_NETBSD #undef CONFIG_BOOTM_PLAN9 #undef CONFIG_BOOTM_RTEMS /* I2C configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ @@ -195,9 +187,6 @@ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -/* MXC SPI driver support */ -#define CONFIG_MXC_SPI - /* * If want to use nand, define CONFIG_NAND_MXS and rework board * to support nand, since emmc has pin conflicts with nand @@ -230,12 +219,9 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_IMX_THERMAL diff --git a/include/configs/mxs.h b/include/configs/mxs.h index fdf596f82f..041dcde38e 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -126,16 +126,6 @@ #endif #endif -/* I2C */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXS -#define CONFIG_HARD_I2C -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 400000 -#endif -#endif - /* LCD */ #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_MXS @@ -168,7 +158,6 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_IS_TDI #endif diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 861cb5df57..dfa81223c4 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -42,7 +42,6 @@ * Commands configuration */ #define CONFIG_CMD_NAND -#define CONFIG_CMD_IDE #define CONFIG_SYS_LONGHELP #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING @@ -94,7 +93,6 @@ * USB/EHCI */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ #define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ #define CONFIG_EHCI_IS_TDI #define CONFIG_SUPPORT_VFAT @@ -103,7 +101,6 @@ /* * File system */ -#define CONFIG_CMD_JFFS2 #define CONFIG_JFFS2_NAND #define CONFIG_JFFS2_LZO #define CONFIG_CMD_UBIFS diff --git a/include/configs/neo.h b/include/configs/neo.h index 9115e251b1..5a8a5c2422 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -31,9 +31,6 @@ #define PLLMR0_DEFAULT PLLMR0_266_133_66_33 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -/* new uImage format support */ -#define CONFIG_FIT_DISABLE_SHA256 - #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ /* @@ -57,9 +54,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IRQ /* * SDRAM configuration (please see cpu/ppc/sdram.[ch]) @@ -100,13 +94,6 @@ #define CONFIG_RTC_DS1337 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* Temp sensor/hwmon/dtt */ -#define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ -#define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 50, 20 }, { 60, 40 } } -#define CONFIG_DTT_TACH_LIMIT 0xa10 - /* * FLASH organization */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index cacc1b81f0..00b84f757a 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -74,8 +74,6 @@ #define CONFIG_PHY_MICREL_KSZ9021 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_MCS7830 @@ -95,7 +93,6 @@ #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) #define CONFIG_BMP_16BPP #define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_CMD_HDMIDETECT #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index f51bfc34c1..5e2d5991e7 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -22,10 +22,6 @@ /* * High Level Configuration Options */ - -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP3430 /* which is in a 3430 */ -#define CONFIG_OMAP3_RX51 /* working with RX51 */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ #define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 @@ -129,7 +125,6 @@ #define CONFIG_TWL4030_LED #define CONFIG_TWL4030_KEYPAD -#define CONFIG_OMAP_GPIO #define GPIO_SLIDE 71 /* diff --git a/include/configs/novena.h b/include/configs/novena.h index df0efbca92..6cb1807a8e 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -17,7 +17,6 @@ #include "mx6_common.h" /* U-Boot Commands */ -#define CONFIG_CMD_EEPROM #define CONFIG_FAT_WRITE #define CONFIG_CMD_PCI #define CONFIG_CMD_SATA @@ -135,8 +134,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX @@ -159,7 +156,6 @@ #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_CMD_HDMIDETECT #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP #endif diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index eba31c4abf..bc67270af7 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -21,11 +21,9 @@ /* compression configuration */ #define CONFIG_BZIP2 -#define CONFIG_LZMA /* commands configuration */ #define CONFIG_SYS_MVFS -#define CONFIG_CMD_IDE /* * mv-common.h should be defined after CMD configs since it used them @@ -80,12 +78,12 @@ #endif /* CONFIG_CMD_NET */ /* SATA driver configuration */ -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define __io #define CONFIG_IDE_PREINIT #define CONFIG_MVSATA_IDE_USE_PORT0 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ /* RTC driver configuration */ #ifdef CONFIG_CMD_DATE diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index d9d4f2d583..b5357ea15c 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -39,7 +39,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index e2881a7177..1b4200bcbf 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -68,7 +68,6 @@ /* * Supported commands */ -#define CONFIG_CMD_EEPROM #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif @@ -173,27 +172,6 @@ #endif /* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration: - * - * O2DNT board is equiped with Ramtron FRAM device FM24CL16 - * 16 Kib Ferroelectric Nonvolatile serial RAM memory - * organized as 2048 x 8 bits and addressable as eight I2C devices - * 0x50 ... 0x57 each 256 bytes in size - * - */ -#define CONFIG_SYS_I2C_FRAM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -/* * There is no write delay with FRAM, write operations are performed at bus * speed. Thus, no status polling or write delay is needed. */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 6cc7dd16a2..afc7c5e35f 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -188,7 +188,6 @@ #define CONFIG_LIB_HW_RAND /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 40b48f70ab..ba29f3e7d1 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -41,7 +41,6 @@ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS /* DFU */ @@ -62,7 +61,6 @@ /* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ #undef CONFIG_EXYNOS_TMU -#undef CONFIG_TMU_CMD_DTT #define CONFIG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c69b32531c..0d48d4ecc1 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -55,9 +55,7 @@ #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 /* USB EHCI */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 @@ -66,10 +64,6 @@ #define CONFIG_USB_ETHER_MCS7830 #define CONFIG_USB_ETHER_SMSC95XX -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ -#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ - /* commands to include */ #define MTDIDS_DEFAULT "nand0=nand" diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index bf5b2f5139..53bfc13264 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -25,8 +25,6 @@ * ---------------------------------------------------------------------------- */ -#define CONFIG_CMD_JFFS2 - #define CONFIG_CMD_NAND /* ---------------------------------------------------------------------------- @@ -83,13 +81,9 @@ /* * High level configuration options */ -#define CONFIG_OMAP /* This is TI OMAP core */ -#define CONFIG_OMAP_GPIO #define CONFIG_SDRC /* The chip has SDRC controller */ -#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */ - /* * Clock related definitions */ @@ -321,7 +315,6 @@ #define CONFIG_SPL_BSS_START_ADDR 0x80000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_OMAP3_ID_NAND #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 70d337e6f1..59da726bd6 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -37,11 +37,6 @@ #endif #endif -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */ -#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ -#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ - /* USB */ #define CONFIG_USB_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 772fc60c9c..f8978037f2 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -23,6 +23,7 @@ * DM support in SPL */ #undef CONFIG_DM_MMC +#undef CONFIG_DM_MMC_OPS #undef OMAP_HSMMC_USE_GPIO /* select serial console configuration for SPL */ @@ -49,10 +50,6 @@ /* Hardware drivers */ -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO 96..128 is in GPIO bank 4 */ -#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ - #define CONFIG_USB_OMAP3 /* commands to include */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index ebf7dd0c01..111aec58d3 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -40,18 +40,9 @@ #define CONFIG_TWL4030_LED /* USB EHCI */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -/* Initialize GPIOs by default */ -#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */ -#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ -#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */ -#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ - /* commands to include */ #ifdef CONFIG_NAND diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index ba7d3cdef5..efee5b0c3f 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -35,10 +35,6 @@ /* TWL4030 LED */ #define CONFIG_TWL4030_LED -/* Initialize GPIOs by default */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ -#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ - /* * NS16550 Configuration */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index aa27a9e68a..6c869c4c07 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -13,11 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ - #define CONFIG_NAND #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include <asm/arch/cpu.h> /* get chip and board defs */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index a6078daca6..e1263b68bc 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -17,8 +17,6 @@ */ /* USB UHH support options */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 533bb02c5e..d8b0c023b9 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -52,8 +52,6 @@ #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 /* USB UHH support options */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -68,9 +66,6 @@ #define CONSOLEDEV "ttyO2" -/* Max time to hold reset on this board, see doc/README.omap-reset-time */ -#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 - #define CONFIG_SCSI #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 0cc0042bca..9db4eeb54e 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -284,7 +284,6 @@ /* * U-Boot commands */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_SAVES #ifdef CONFIG_CMD_BDI #define CONFIG_CLOCKS @@ -309,7 +308,6 @@ !defined(CONFIG_USE_SPIFLASH) #define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_ENV #endif /* SD/MMC */ @@ -330,7 +328,6 @@ #ifndef CONFIG_DIRECT_NOR_BOOT /* defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 19660db080..89e963d524 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -26,9 +26,7 @@ * Commands configuration */ #define CONFIG_SYS_MVFS -#define CONFIG_CMD_ENV #define CONFIG_CMD_NAND -#define CONFIG_CMD_IDE /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index b4d2b0a871..0582fa3688 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -43,7 +43,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* OCOTP Configs */ -#define CONFIG_CMD_IMXOTP #define CONFIG_IMX_OTP #define IMX_OTP_BASE OCOTP_BASE_ADDR #define IMX_OTP_ADDR_MAX 0x7F @@ -55,8 +54,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -93,7 +90,6 @@ #define CONFIG_PHY_SMSC #ifndef CONFIG_SPL -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_BUS 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d995d0448c..71b4f40921 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -631,7 +631,6 @@ #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 /* enable read and write access to EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -814,7 +813,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO /* @@ -823,9 +821,7 @@ #define CONFIG_HAS_FSL_DR_USB #if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index dad0616517..fd644f22da 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -230,7 +230,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 /* enable read and write access to EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -385,7 +384,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO /* @@ -394,9 +392,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_HAS_FSL_DR_USB #if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 897add3dd0..b106439071 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -33,7 +33,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB2.0 Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 3cf0c87be4..22fc122cc3 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -33,7 +33,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB2.0 Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 76fb7cec87..974fd3f59f 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -34,7 +34,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB2.0 Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 2e8cbd94cf..87a8557ea9 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index f6bd4fec88..efbcbd2e05 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -148,6 +148,4 @@ * Command line configuration. */ -#undef CONFIG_CMD_IDE - #endif /* __CONFIG_H */ diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 6d8a2338a2..6da17be11c 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -49,8 +49,6 @@ Serial console configuration /* * Command line configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_PCI #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ @@ -121,31 +119,6 @@ IPB Bus clocking configuration. #define CONFIG_SYS_XLB_PIPELINING 1 /*--------------------------------------------------------------------------- - I2C configuration ----------------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/*--------------------------------------------------------------------------- - EEPROM CAT24WC32 configuration ----------------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */ -#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_SIZE 2048 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15 - -/*--------------------------------------------------------------------------- -RTC configuration ----------------------------------------------------------------------------*/ -#define RTC -#define CONFIG_RTC_PCF8563 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/*--------------------------------------------------------------------------- Flash configuration ---------------------------------------------------------------------------*/ @@ -172,11 +145,10 @@ RTC configuration Environment settings ---------------------------------------------------------------------------*/ -/* pcm030 ships with environment is EEPROM by default */ -#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ /*beginning of the EEPROM */ -#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE +#define CONFIG_ENV_SIZE 2048 #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index ea3872f5c9..fc75ca85c5 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -108,7 +108,6 @@ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* I2C Configuration */ -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 51b489a809..8c0e26486f 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -91,7 +91,6 @@ #define CONFIG_SYS_RTC_BUS_NUM 2 /* EEPROM (24FC256) */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_BUS 2 diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index f622be62b7..39018ac62f 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -86,9 +86,6 @@ #define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)" /* Various command support */ -#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */ -#define CONFIG_CMD_GSC -#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */ #define CONFIG_RBTREE /* Physical Memory Map */ diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 501611dde7..676d55f5e8 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -302,34 +302,11 @@ #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400 /* - * I2C - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -/* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* * IIM - IC Identification Module */ #undef CONFIG_FSL_IIM /* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM addr */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Write Mode */ - -/* - * MAC addr in EEPROM - */ -#define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10 -/* * Enabled only to delete "ethaddr" before testing * "ethaddr" setting from EEPROM */ @@ -345,12 +322,6 @@ #define CONFIG_HAS_ETH0 /* - * Configure on-board RTC - */ -#define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 @@ -367,11 +338,8 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_CMD_EEPROM #define CONFIG_CMD_REGINFO -#undef CONFIG_CMD_FUSE - /* * Miscellaneous configurable options */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 2cb6f56f7d..9c8720bee9 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -107,7 +107,6 @@ /* I2C Configuration */ #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 26b1b1147c..8d78f49c96 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -37,8 +37,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 733768aa7b..998a7a344b 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -98,8 +98,6 @@ #define CONFIG_AT91_WANTS_COMMON_PHY /* USB */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ diff --git a/include/configs/platinum.h b/include/configs/platinum.h index 6687c38c99..9c2182cbea 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -52,8 +52,6 @@ #define CONFIG_PHYLIB /* USB config */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 911cad8cdd..ff396eceb9 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -29,7 +29,6 @@ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ /* USB host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index b220d14dd8..41d5722490 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -226,7 +226,6 @@ #endif -#define CONFIG_CMD_JFFS2 1 #define CONFIG_JFFS2_CMDLINE 1 #define CONFIG_JFFS2_NAND 1 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 22b3c2e2d1..5e58b6b021 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -69,7 +69,6 @@ */ #define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_JFFS2 1 #define CONFIG_JFFS2_CMDLINE 1 #define CONFIG_JFFS2_NAND 1 #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index 36f6e95ced..f94e74f0fc 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -29,7 +29,6 @@ * Commands configuration */ #define CONFIG_SYS_MVFS -#define CONFIG_CMD_ENV #define CONFIG_CMD_NAND /* @@ -78,7 +77,6 @@ /* * File system */ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBIFS #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ diff --git a/include/configs/porter.h b/include/configs/porter.h index fabab73680..ac21411178 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -82,7 +82,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 57f034f0df..e8e0c7edd8 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -42,9 +42,6 @@ #define CONFIG_FACTORYSET -/* Watchdog */ -#define CONFIG_OMAP_WATCHDOG - #ifndef CONFIG_SPL_BUILD /* Use common default */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 59a793babe..abdc93c7d2 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -50,8 +50,6 @@ #define CONFIG_SYS_NS16550_COM1 0xb40003f8 #define CONFIG_CONS_INDEX 1 -#define CONFIG_CMD_IDE - #ifdef CONFIG_SYS_BIG_ENDIAN #define CONFIG_IDE_SWAP_IO #endif @@ -123,6 +121,4 @@ #define MEM_SIZE 128 -#define CONFIG_LZMA - #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 28b791acdd..f1e096fddd 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -50,8 +50,6 @@ #define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8 #define CONFIG_CONS_INDEX 1 -#define CONFIG_CMD_IDE - #ifdef CONFIG_SYS_BIG_ENDIAN #define CONFIG_IDE_SWAP_IO #endif @@ -123,6 +121,4 @@ #define MEM_SIZE 128 -#define CONFIG_LZMA - #endif /* __CONFIG_H */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index ffd776f6bf..c26810723e 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -127,7 +127,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* * Command line configuration. */ -#define CONFIG_CMD_IRQ #ifdef CONFIG_PCI #define CONFIG_CMD_PCI diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 687befdad3..3509c2f659 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -25,10 +25,9 @@ * - AHCI controller is supported for QEMU '-M q35' target * * Default configuraion is to support the QEMU default x86 target - * Undefine CONFIG_CMD_IDE to support q35 target + * Undefine CONFIG_IDE to support q35 target */ -#define CONFIG_CMD_IDE -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_IDE_MAXDEVICE 4 #define CONFIG_SYS_ATA_BASE_ADDR 0 diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h index 642572fc95..6212dbae21 100644 --- a/include/configs/r0p7734.h +++ b/include/configs/r0p7734.h @@ -17,7 +17,6 @@ #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV #define CONFIG_BOOTARGS "console=ttySC3,115200" @@ -40,20 +39,6 @@ # define CONFIG_SMC911X_BASE (0x84000000) #endif -/* I2C */ -#define CONFIG_SH_SH7734_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_SYS_MAX_I2C_BUS 2 -#define CONFIG_SYS_I2C_MODULE 0 -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x50 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 500000000 -#define CONFIG_SH_I2C_BASE0 0xFFC70000 -#define CONFIG_SH_I2C_BASE1 0xFFC7100 - /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* Monitor Command Prompt */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 64fc5b2f03..744d567805 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -12,7 +12,6 @@ * Command line configuration. */ #define CONFIG_CMD_PCI -#define CONFIG_CMD_IDE #define CONFIG_CMD_SH_ZIMAGEBOOT /* SCIF */ diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 2efe36f854..bb79a9ffea 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -22,7 +22,6 @@ */ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_PCI -#define CONFIG_CMD_IDE #define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 @@ -120,7 +119,7 @@ #endif /* Compact flash Support */ -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) #define CONFIG_IDE_RESET 1 #define CONFIG_SYS_PIO_MODE 1 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ @@ -131,6 +130,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ #define CONFIG_IDE_SWAP_IO -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ #endif /* __R7780RP_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 99fe1616e5..0820f6fc7a 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -49,9 +49,6 @@ #define CONFIG_FACTORYSET -/* Watchdog */ -#define CONFIG_OMAP_WATCHDOG - /* Define own nand partitions */ #define CONFIG_ENV_OFFSET_REDUND 0x2E0000 #define CONFIG_ENV_SIZE_REDUND 0x2000 diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 056aea3fdb..e73bc61856 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -2,7 +2,7 @@ * include/configs/rcar-gen3-common.h * This file is R-Car Gen3 common configuration file. * - * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015-2017 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,7 +17,6 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE -#define CONFIG_CMD_FDT #define CONFIG_REMAKE_ELF @@ -34,7 +33,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -#define CONFIG_OF_LIBFDT #undef CONFIG_SHOW_BOOT_PROGRESS @@ -52,13 +50,34 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* MEMORY */ -#define CONFIG_SYS_TEXT_BASE 0x49000000 +#define CONFIG_SYS_TEXT_BASE 0x50000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0) -#define CONFIG_SYS_SDRAM_BASE (0x48000000) -#define CONFIG_SYS_SDRAM_SIZE (1024u * 1024 * 1024 - 0x08000000) -#define CONFIG_SYS_LOAD_ADDR (0x48080000) -#define CONFIG_NR_DRAM_BANKS 1 +#define DRAM_RSV_SIZE 0x08000000 +#if defined(CONFIG_R8A7795) +#define CONFIG_NR_DRAM_BANKS 4 +#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) +#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) +#define PHYS_SDRAM_2 0x500000000 +#define PHYS_SDRAM_2_SIZE 0x40000000u +#define PHYS_SDRAM_3 0x600000000 +#define PHYS_SDRAM_3_SIZE 0x40000000u +#define PHYS_SDRAM_4 0x700000000 +#define PHYS_SDRAM_4_SIZE 0x40000000u +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE +#elif defined(CONFIG_R8A7796) +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) +#define PHYS_SDRAM_1_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define PHYS_SDRAM_2 0x0600000000 +#define PHYS_SDRAM_2_SIZE 0x80000000u +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE +#endif +#define CONFIG_SYS_LOAD_ADDR 0x48080000 +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_SDRAM_SIZE #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) @@ -81,7 +100,7 @@ #define CONFIG_BOOTCOMMAND \ "tftp 0x48080000 Image; " \ - "tftp 0x48000000 Image-r8a7795-salvator-x.dtb; " \ + "tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \ "booti 0x48080000 - 0x48000000" #endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index c5e508e4ab..81a1553390 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SPL_BOARD_INIT #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index e7a8f724f1..4cf71fa17e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -23,7 +23,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SPL_BOARD_INIT #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x0 once return from SPL */ diff --git a/include/configs/rut.h b/include/configs/rut.h index 8cfb73d781..e676a5acd4 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -110,10 +110,6 @@ #endif /* CONFIG_SPL_BUILD */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_HW_WATCHDOG -#endif - #if defined(CONFIG_VIDEO) #define CONFIG_VIDEO_DA8XX #define CONFIG_SPLASH_SCREEN diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 398b3aa343..b25a7ea344 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -97,16 +97,6 @@ #define CONFIG_PHY_MICREL #endif -#if 0 /* Disable until the I2C driver will be updated */ - -/* I2C Configs */ -#define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_BASE I2C0_BASE_ADDR -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #if 0 /* Disable until the FLASH will be implemented */ #define CONFIG_SYS_USE_NAND #endif @@ -127,7 +117,6 @@ #define CONFIG_LOADADDR 0xC307FFC0 #define CONFIG_BOOTARGS "console=ttyLF0 root=/dev/ram rw" -#define CONFIG_CMD_ENV #define CONFIG_EXTRA_ENV_SETTINGS \ "boot_scripts=boot.scr.uimg boot.scr\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 81a7226d62..0ac3900326 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -20,21 +20,27 @@ #define CONFIG_SCIF_CONSOLE #define CONFIG_CONS_SCIF2 #define CONFIG_CONS_INDEX 2 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ /* [A] Hyper Flash */ /* use to RPC(SPI Multi I/O Bus Controller) */ -#define CONFIG_ENV_IS_NOWHERE + +/* Ethernet RAVB */ +#define CONFIG_NET_MULTI +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI /* Board Clock */ /* XTAL_CLK : 33.33MHz */ #define RCAR_XTAL_CLK 33333333u #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ -/* CPclk 16.66MHz, S3D2 133.33MHz */ +/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) #define CONFIG_S3D2_CLK_FREQ (266666666u/2) +#define CONFIG_S3D4_CLK_FREQ (266666666u/4) /* Generic Timer Definitions (use in assembler source) */ #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ @@ -44,9 +50,39 @@ #define GICD_BASE 0xF1010000 #define GICC_BASE 0xF1020000 +/* i2c */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x60 +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 + +/* USB */ +#ifdef CONFIG_R8A7795 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#else +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* SDHI */ +#define CONFIG_SH_SDHI_FREQ 200000000 + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 + /* Module stop status bits */ /* MFIS, SCIF1 */ #define CONFIG_SMSTP2_ENA 0x00002040 +/* SCIF2 */ +#define CONFIG_SMSTP3_ENA 0x00000400 /* INTC-AP, IRQC */ #define CONFIG_SMSTP4_ENA 0x00000180 diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h index 16bafc0990..57fa67d234 100644 --- a/include/configs/sama5d2_ptc.h +++ b/include/configs/sama5d2_ptc.h @@ -66,8 +66,6 @@ #define CONFIG_CMD_USB #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #endif @@ -117,7 +115,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_SERIALFLASH diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index f044f0e6de..42fb1e11d0 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -79,7 +79,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_MMC diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index b4a62bd63a..074c7568f0 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -97,7 +97,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_MMC diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 509457b9bf..9540a4a0ff 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -126,7 +126,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_MMC diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index c584b0b9e3..f1cf65f42c 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -75,7 +75,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_MMC diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 91f286b647..09a9757e6e 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -73,7 +73,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_MMC diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 37c6132b8a..c62b45e51c 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -18,7 +18,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_IO_TRACE -#define CONFIG_CMD_IOTRACE #endif #ifndef CONFIG_TIMER @@ -29,7 +28,6 @@ #define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_CMD_PCI -#define CONFIG_CMD_IO #define CONFIG_FS_FAT #define CONFIG_FAT_WRITE @@ -100,18 +98,10 @@ #define CONFIG_BOOTP_SERVERIP #define CONFIG_IP_DEFRAG -/* Can't boot elf images */ - -#define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY -#define CONFIG_SHA1 -#define CONFIG_SHA256 #define CONFIG_CMD_SANDBOX -#define CONFIG_CMD_ENV_FLAGS -#define CONFIG_CMD_ENV_CALLBACK - #define CONFIG_BOOTARGS "" #ifndef SANDBOX_NO_SDL @@ -159,12 +149,8 @@ #define CONFIG_GZIP_COMPRESSED #define CONFIG_BZIP2 #define CONFIG_LZO -#define CONFIG_LZMA - -#define CONFIG_CMD_LZMADEC #ifndef CONFIG_SPL_BUILD -#define CONFIG_CMD_IDE #define CONFIG_SYS_IDE_MAXBUS 1 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 #define CONFIG_SYS_IDE_MAXDEVICE 2 diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h index 2aaa3ab976..93b595dd10 100644 --- a/include/configs/sandbox_spl.h +++ b/include/configs/sandbox_spl.h @@ -8,8 +8,6 @@ #include <configs/sandbox.h> -#define CONFIG_SPL_BOARD_INIT - #define CONFIG_SPL_FRAMEWORK #endif diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 207b59118d..afc2c7dfe9 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -37,7 +37,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index f5b03caf83..7a120ed5a6 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -159,14 +159,6 @@ #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - /* * Default environment variables */ @@ -192,16 +184,13 @@ /* USB */ #ifdef CONFIG_440EPX - -#undef CONFIG_USB_EHCI /* OHCI by default */ - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_PPC4XX #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_EHCI_DESC_BIG_ENDIAN -#else /* CONFIG_USB_EHCI */ +#else /* CONFIG_USB_EHCI_HCD */ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_OHCI_BE_CONTROLLER @@ -222,7 +211,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT #define CONFIG_CMD_NAND #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 69073e8a66..2186f21f7a 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -18,7 +18,6 @@ * Command line configuration. */ #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_JFFS2 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01" #define CONFIG_ENV_OVERWRITE 1 diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index a111057313..9d2c106d46 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -90,13 +90,13 @@ /* * SATA driver configuration */ -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define __io #define CONFIG_IDE_PREINIT #define CONFIG_MVSATA_IDE_USE_PORT0 #define CONFIG_MVSATA_IDE_USE_PORT1 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/shmin.h b/include/configs/shmin.h index bc1eba32ff..995f76a1ea 100644 --- a/include/configs/shmin.h +++ b/include/configs/shmin.h @@ -16,7 +16,6 @@ /* #define CONFIG_T_SH7706LSR 1 */ #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV #define CONFIG_BOOTARGS "console=ttySC0,115200" diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 508b849472..9161867675 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -15,7 +15,6 @@ #define __CONFIG_SIEMENS_AM33X_COMMON_H #define CONFIG_AM33XX -#define CONFIG_OMAP #include <asm/arch/omap.h> @@ -128,7 +127,6 @@ #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_AM33XX_BCH #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS @@ -548,13 +546,6 @@ #endif #endif -#define CONFIG_OMAP_GPIO - -/* Gpio cmd support */ - -/* Watchdog */ -#define CONFIG_HW_WATCHDOG - /* Reboot after 60 sec if bootcmd fails */ #define CONFIG_RESET_TO_RETRY #define CONFIG_BOOT_RETRY_TIME 60 diff --git a/include/configs/silk.h b/include/configs/silk.h index 4fc270fcc2..84108fd523 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -82,7 +82,6 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index e09dfe6dd3..1236da724e 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -233,7 +233,6 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SYS_USE_NANDFLASH 1 #define CONFIG_SPL_NAND_DRIVERS diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 952c6f546f..99b5b23d29 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -61,8 +61,6 @@ #define CONFIG_TFTP_TSIZE /* USB */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 /* MMC */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 5214827ad9..6b065c9dc7 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -19,12 +19,6 @@ #define CONFIG_ARM_ARCH_CP15_ERRATA /* - * Platform - */ - -#define CONFIG_OMAP - -/* * Board */ @@ -62,17 +56,6 @@ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) /* - * GPIO - */ - -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP3_GPIO_2 -#define CONFIG_OMAP3_GPIO_3 -#define CONFIG_OMAP3_GPIO_4 -#define CONFIG_OMAP3_GPIO_5 -#define CONFIG_OMAP3_GPIO_6 - -/* * I2C */ @@ -104,7 +87,6 @@ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h new file mode 100644 index 0000000000..7ea780b48b --- /dev/null +++ b/include/configs/socfpga_arria10_socdk.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2015-2017 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__ + +#include <asm/arch/base_addr_a10.h> +/* U-Boot Commands */ +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * U-Boot general configurations + */ +/* Cache options */ +#define CONFIG_SYS_DCACHE_OFF + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 +#endif + +/* + * U-Boot environment configurations + */ +#define CONFIG_ENV_IS_IN_MMC + +/* + * arguments passed to the bootz command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 107c6d5b66..bdc6512959 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -32,9 +32,13 @@ #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ +#endif #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ @@ -101,13 +105,14 @@ /* * FPGA Driver */ +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 #ifdef CONFIG_CMD_FPGA #define CONFIG_FPGA #define CONFIG_FPGA_ALTERA #define CONFIG_FPGA_SOCFPGA #define CONFIG_FPGA_COUNT 1 #endif - +#endif /* * L4 OSC1 Timer 0 */ @@ -207,11 +212,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_NS16550_CLK 1000000 -#else +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS #define CONFIG_SYS_NS16550_CLK 100000000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS +#define CONFIG_SYS_NS16550_CLK 50000000 #endif #define CONFIG_CONS_INDEX 1 @@ -298,7 +306,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index e208f45649..251dd0e901 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -12,8 +12,6 @@ #define CONFIG_FAT_WRITE #define CONFIG_HW_WATCHDOG -#define CONFIG_CMD_EEPROM - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 76b4038d50..bfd4e5fe3f 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -210,13 +210,6 @@ /* I2C W83782G HW-Monitoring IC */ #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ -/* I2C temp sensor */ -/* Socrates uses Maxim's DS75, which is compatible with LM75 */ -#define CONFIG_DTT_LM75 1 -#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 125 -#define CONFIG_SYS_DTT_LOW_TEMP -55 -#define CONFIG_SYS_DTT_HYSTERESIS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* @@ -286,8 +279,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM #define CONFIG_CMD_SDRAM #define CONFIG_CMD_REGINFO diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 75fd27a373..86e14ffac8 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -97,7 +97,6 @@ * Command support defines */ #define CONFIG_CMD_NAND -#define CONFIG_CMD_ENV #define CONFIG_CMD_SAVES /* diff --git a/include/configs/stout.h b/include/configs/stout.h index 90258c2f42..16f3ce8647 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -84,7 +84,6 @@ #define CONFIG_SYS_TMU_CLK_DIV 4 /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_RMOBILE #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 diff --git a/include/configs/strider.h b/include/configs/strider.h index 1298808b13..994ac73e13 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -28,9 +28,6 @@ #define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_CMD_FPGAD -#define CONFIG_CMD_IOLOOP - /* * System Clock Setup */ diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 3dfd95ad77..bd349694c6 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -12,7 +12,7 @@ * A10 specific configuration */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_SUNXI #endif diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 1b7bfb6c22..b7b67a1ddc 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -11,7 +11,7 @@ * A64 specific configuration */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_SUNXI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index ec8f3199ba..0535d6a7f3 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -12,7 +12,7 @@ * High Level Configuration Options */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_SUNXI #endif diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h index 6c1eca4d26..8b9adb1be6 100644 --- a/include/configs/sun6i.h +++ b/include/configs/sun6i.h @@ -15,7 +15,7 @@ * A31 specific configuration */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_SUNXI #endif diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 5455901efe..12c96230c2 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -13,7 +13,7 @@ * A20 specific configuration */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_SUNXI #endif diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index 6ac42acaea..47f2813240 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -13,7 +13,7 @@ * A23 specific configuration */ -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_EHCI_SUNXI #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 997a92c8be..f042f0d0c2 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -32,6 +32,10 @@ # define CONFIG_MACH_TYPE_COMPAT_REV 1 #endif +#ifdef CONFIG_ARM64 +#define CONFIG_BUILD_TARGET "u-boot.itb" +#endif + /* Serial & console */ #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ @@ -185,12 +189,17 @@ #endif #ifdef CONFIG_SUNXI_HIGH_SRAM -#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB */ +#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ +#ifdef CONFIG_ARM64 +/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ +#define LOW_LEVEL_SRAM_STACK 0x00054000 +#else #define LOW_LEVEL_SRAM_STACK 0x00018000 +#endif /* !CONFIG_ARM64 */ #else -#define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */ +#define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ #endif diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index 964115f980..ed5aaa2a63 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -349,7 +349,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_ECCTEST #define CONFIG_CMD_PCI #define CONFIG_CMD_SDRAM diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 55b8e3ebfc..260cdee001 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -241,8 +241,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #ifdef CONFIG_PCI #define CONFIG_CMD_PCI diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 0bdf52eb68..0b87c9ca97 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -13,8 +13,6 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP_GPIO #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -43,7 +41,6 @@ /* * DDR related */ -#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) /* @@ -69,15 +66,11 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} /* EHCI */ -#define CONFIG_OMAP3_GPIO_5 -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 /* commands to include */ #define CONFIG_CMD_NAND /* NAND support */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 @@ -176,7 +169,6 @@ /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_CONSOLE #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_SOFTECC diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 9bb4a1a8c0..f994d2dbf3 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -16,9 +16,6 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ - -#define CONFIG_OMAP_GPIO #define CONFIG_SDRC /* Has an SDRC controller */ @@ -64,13 +61,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ -#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ -#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ -#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ -#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ - /* commands to include */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ @@ -238,8 +228,6 @@ */ /* USB EHCI */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 @@ -256,7 +244,6 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 4505be8eaf..bed2a5c3c0 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -246,7 +246,6 @@ #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512) -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SYS_USE_NANDFLASH 1 #define CONFIG_SPL_NAND_DRIVERS diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index b4a14eae7c..84ca1c443e 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -69,7 +69,6 @@ #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_CMD_HDMIDETECT #endif /* PCI */ @@ -93,8 +92,6 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 06d8720df2..6406d39698 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -33,7 +33,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/tec.h b/include/configs/tec.h index b380a69bdf..8ffdbec9d1 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -29,7 +29,6 @@ #define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ /* USB host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index ab4136ab13..1a4a7e2320 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -123,9 +123,6 @@ #endif /* remove USB */ -#ifdef CONFIG_USB_EHCI -#undef CONFIG_USB_EHCI -#endif #ifdef CONFIG_USB_EHCI_TEGRA #undef CONFIG_USB_EHCI_TEGRA #endif diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 5107a1f609..6982eaa1af 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -87,11 +87,8 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_CMD_ENTERRCM - /* Defines for SPL */ #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ CONFIG_SPL_TEXT_BASE) diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 2a671e84ec..27cae9d528 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -23,7 +23,6 @@ /* * Commands configuration */ -#define CONFIG_CMD_ENV #define CONFIG_CMD_SATA /* diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 8c37d7cace..cea84acd03 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -42,9 +42,6 @@ #define CONFIG_FACTORYSET -/* Watchdog */ -#define CONFIG_OMAP_WATCHDOG - /* Define own nand partitions */ #define CONFIG_ENV_OFFSET_REDUND 0x2E0000 #define CONFIG_ENV_SIZE_REDUND 0x2000 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index baf818ba1a..a4066a8494 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -18,7 +18,6 @@ #define CONFIG_TI81XX #define CONFIG_TI814X -#define CONFIG_OMAP #include <asm/arch/omap.h> @@ -110,8 +109,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ -#define CONFIG_OMAP_GPIO - /** * Physical Memory Map */ @@ -159,8 +156,6 @@ #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT - /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index b7ec200e06..2303970d88 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -12,7 +12,6 @@ #define CONFIG_TI81XX #define CONFIG_TI816X -#define CONFIG_OMAP #define CONFIG_ARCH_CPU_INIT @@ -50,7 +49,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ #define CONFIG_CMD_ASKENV -#define CONFIG_OMAP_GPIO #define CONFIG_FS_FAT @@ -124,8 +122,6 @@ #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT - #define CONFIG_SYS_TEXT_BASE 0x80800000 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index e4c3c807f2..bf44121a0f 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -47,10 +47,6 @@ */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 -/* Enable the HW watchdog, since we can use this with bootcount */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_OMAP_WATCHDOG - /* * SPL related defines. The Public RAM memory map the ROM defines the * area between 0x402F0400 and 0x4030B800 as a download area and diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1561d54c9a..0bd3c9f94c 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -216,7 +216,6 @@ #endif /* General parts of the framework, required. */ -#define CONFIG_SPL_BOARD_INIT #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_BASE diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 868464cd32..3161c50abb 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -208,7 +208,6 @@ /* U-Boot command configuration */ #define CONFIG_CMD_SAVES #define CONFIG_CMD_UBIFS -#define CONFIG_CMD_EEPROM /* U-Boot general configuration */ #define CONFIG_MISC_INIT_R diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h index de14b8575a..b4565daf41 100644 --- a/include/configs/ti_armv7_omap.h +++ b/include/configs/ti_armv7_omap.h @@ -12,9 +12,6 @@ #ifndef __CONFIG_TI_ARMV7_OMAP_H__ #define __CONFIG_TI_ARMV7_OMAP_H__ -/* Common defines for all OMAP architecture based SoCs */ -#define CONFIG_OMAP - /* I2C IP block */ #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 @@ -23,9 +20,6 @@ /* SPI IP Block */ #define CONFIG_OMAP3_SPI -/* GPIO block */ -#define CONFIG_OMAP_GPIO - /* * GPMC NAND block. We support 1 device and the physical address to * access CS0 at is 0x8000000. diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index b85db500b5..1a6551e24d 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -12,10 +12,6 @@ #ifndef __CONFIG_TI_OMAP4_COMMON_H #define __CONFIG_TI_OMAP4_COMMON_H -/* - * High Level Configuration Options - */ -#define CONFIG_OMAP4430 1 /* which is in a 4430 */ #define CONFIG_MISC_INIT_R #ifndef CONFIG_SYS_L2CACHE_OFF diff --git a/include/configs/titanium.h b/include/configs/titanium.h index 2c05f9c930..79e37e2cef 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -50,8 +50,6 @@ #define CONFIG_PHY_MICREL_KSZ9021 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 23160bd88d..a28922585c 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -44,10 +44,6 @@ #undef CONFIG_SPL_FPGA_SUPPORT /* FPGA commands that we don't use */ -#undef CONFIG_CMD_FPGA_LOADMK -#undef CONFIG_CMD_FPGA_LOADP -#undef CONFIG_CMD_FPGA_LOADBP -#undef CONFIG_CMD_FPGA_LOADFS /* Extras */ #define CONFIG_CMD_MEMTEST diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index d39dd92198..fc99dbd91e 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -36,7 +36,6 @@ "console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" #define CONFIG_BOOTCOMMAND \ "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" -#define CONFIG_LZMA #define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x10000 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index e662e65204..0b362559f2 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -57,19 +57,11 @@ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_SPEED 100000 -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM75 -#define CONFIG_DTT_MAX_TEMP 70 -#define CONFIG_DTT_MIN_TEMP -30 -#define CONFIG_DTT_HYSTERESIS 3 -#define CONFIG_CMD_DTT - /* I2C EEPROM (M24C64) */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_CMD_EEPROM #define CONFIG_POWER #define CONFIG_POWER_I2C @@ -81,8 +73,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) @@ -373,8 +363,5 @@ #endif /* Support at least the sensor on TQMa6 SOM */ -#if !defined(CONFIG_DTT_SENSORS) -#define CONFIG_DTT_SENSORS { 0 } -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 3d6e4383e1..69e9079339 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CONFIG_DTT_SENSORS { 0, 1 } - #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index b9cc5d632f..4ab4c6559d 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -7,10 +7,6 @@ #ifndef __CONFIG_TQMA6_WRU4_H #define __CONFIG_TQMA6_WRU4_H -/* DTT sensors */ -#define CONFIG_DTT_SENSORS { 0, 1 } -#define CONFIG_SYS_DTT_BUS_NUM 2 - /* Ethernet */ #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "FEC" diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 9741ca5fc9..d18a333d01 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -16,9 +16,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ - #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM @@ -49,14 +46,6 @@ /* Hardware drivers */ -/* GPIO support */ -#define CONFIG_OMAP_GPIO - -/* GPIO banks */ -#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */ - -/* LED support */ - /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) @@ -77,7 +66,6 @@ /* EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_BUS_NUM 1 @@ -116,8 +104,6 @@ #define CONFIG_CMD_UBIFS /* UBIFS commands */ #define CONFIG_LZO /* LZO is needed for UBIFS */ -#undef CONFIG_CMD_JFFS2 /* JFFS2 Support */ - /* needed for ubi */ #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ @@ -284,7 +270,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 2c37107a3c..ab9c5c3ab8 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/twister.h b/include/configs/twister.h index 30ad241f7f..94dde90e60 100644 --- a/include/configs/twister.h +++ b/include/configs/twister.h @@ -43,9 +43,5 @@ 0x600000) #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_SPL_BOARD_INIT - -/* gpio 55 is used as SPL_OS_BOOT_KEY */ -#define CONFIG_OMAP3_GPIO_2 #endif /* __CONFIG_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index cdc5b0018a..bc57e8a73a 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -176,7 +176,7 @@ #define CONFIG_BOOTFILE "Image.gz" #define LINUXBOOT_CMD "booti" #define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0" -#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" +#define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0" #else #define CONFIG_BOOTFILE "zImage" #define LINUXBOOT_CMD "bootz" @@ -246,6 +246,11 @@ "nand write $loadaddr 0 0x00020000 && " \ "tftpboot $third_image && " \ "nand write $loadaddr 0x00020000 0x000e0000\0" \ + "usbupdate=usb start &&" \ + "tftpboot $second_image && " \ + "usb write $loadaddr 0 100 && " \ + "tftpboot $third_image && " \ + "usb write $loadaddr 100 700\0" \ BOOT_IMAGES \ LINUXBOOT_ENV_SETTINGS @@ -284,8 +289,6 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE #endif -#define CONFIG_SPL_BOARD_INIT - #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 /* subtract sizeof(struct image_header) */ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 58b62d2448..e25bf99e1c 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_FSL_ESDHC_NUM 1 /* USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX5 #define CONFIG_MXC_USB_PORT 1 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) @@ -54,7 +53,6 @@ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ /* Fuse */ -#define CONFIG_CMD_FUSE #define CONFIG_FSL_IIM /* U-Boot memory offsets */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index cc0007827d..2bd6cc11ae 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -73,9 +73,6 @@ /* * Command line configuration. */ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_SDRAM #define CONFIG_TIMESTAMP /* Print image info with timestamp */ @@ -135,27 +132,6 @@ #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 - -/* - * RTC configuration - */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* * Flash configuration - use CFI driver */ #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ diff --git a/include/configs/vct.h b/include/configs/vct.h index 9db6fee6e7..7b04e65d70 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -77,7 +77,6 @@ /* * Commands */ -#define CONFIG_CMD_EEPROM /* * Only Premium/Platinum have ethernet support right now @@ -99,7 +98,6 @@ /* * USB/EHCI */ -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ #define CONFIG_USB_EHCI_VCT /* on VCT platform */ #define CONFIG_EHCI_MMIO_BIG_ENDIAN #define CONFIG_EHCI_DESC_BIG_ENDIAN @@ -236,7 +234,6 @@ int vct_gpio_get(int pin); */ #if defined(CONFIG_VCT_ONENAND) #define CONFIG_SYS_USE_UBI -#define CONFIG_CMD_JFFS2 #define CONFIG_RBTREE #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_MTD_PARTITIONS @@ -255,10 +252,6 @@ int vct_gpio_get(int pin); * (NOR/OneNAND) usage and Linux kernel booting. */ #if defined(CONFIG_VCT_SMALL_IMAGE) -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IRQ -#undef CONFIG_CMD_LOADY #undef CONFIG_CMD_REGINFO #undef CONFIG_CMD_STRINGS #undef CONFIG_CMD_TERMINAL diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 9e83863c0a..850a9bd49a 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -34,7 +34,6 @@ #define CONFIG_SPI_FLASH_SIZE (4 << 20) /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 0e851a1b10..1ab6476f3c 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index ae13246478..11cb53587c 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -125,7 +125,6 @@ #endif /*#define CONFIG_MENU_SHOW*/ -#define CONFIG_CMD_ENV /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 3e7dc9b685..2460294d88 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -20,7 +20,6 @@ /* Enable passing of ATAGs */ #define CONFIG_CMDLINE_TAG -#define CONFIG_CMD_FUSE #ifdef CONFIG_CMD_FUSE #define CONFIG_MXC_OCOTP #endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h index c146f773db..dc35b289d4 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -66,8 +66,6 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #endif diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 9a517a9738..78e14b38c1 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -76,8 +76,6 @@ #define CONFIG_PHY_ATHEROS #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ae18bd6338..1aed81fc14 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -351,10 +351,6 @@ #define CONFIG_CMD_PCI #endif -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV -#endif - /* Pass Ethernet MAC to VxWorks */ #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 47daf724ab..2a6c6fbb70 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -50,8 +50,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 @@ -76,7 +74,6 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IPUV3_CLK 260000000 -#define CONFIG_CMD_HDMIDETECT #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP #endif diff --git a/include/configs/warp.h b/include/configs/warp.h index 5274b274a4..afe3eaed46 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -58,8 +58,6 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/whistler.h b/include/configs/whistler.h index 429e5b6a32..9f350d556a 100644 --- a/include/configs/whistler.h +++ b/include/configs/whistler.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* USB Host support */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA /* USB networking support */ diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h index eb42d8c347..bab7fdf93c 100644 --- a/include/configs/woodburn_sd.h +++ b/include/configs/woodburn_sd.h @@ -22,7 +22,6 @@ */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds" -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_TEXT_BASE 0x10002300 #define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 82f4af9c93..56f53b9732 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -74,7 +74,6 @@ * I2C EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 @@ -85,14 +84,6 @@ #define CONFIG_RTC_DS1374 /* - * I2C Temperature Sensor (DTT) - */ - -#define CONFIG_CMD_DTT -#define CONFIG_DTT_SENSORS { 0, 1 } -#define CONFIG_DTT_DS620 - -/* * U-Boot General Configurations */ #define CONFIG_SYS_LONGHELP @@ -143,7 +134,6 @@ #define CONFIG_LPC32XX_SSP #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 #define CONFIG_CMD_MAX6957 -#define CONFIG_CMD_HD44760 /* * Environment */ @@ -173,7 +163,6 @@ #define CONFIG_SPL_TEXT_BASE 0x00000000 /* SPL will use SRAM as stack */ #define CONFIG_SPL_STACK 0x0000FFF8 -#define CONFIG_SPL_BOARD_INIT /* Use the framework and generic lib */ #define CONFIG_SPL_FRAMEWORK /* SPL will use serial */ diff --git a/include/configs/x600.h b/include/configs/x600.h index 6e52e56222..c7d32fedb3 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -100,15 +100,12 @@ #define CONFIG_FPGA_COUNT 1 /* USB EHCI options */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SPEAR #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* * Command support defines */ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FPGA_LOADMK #define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_NAND #define CONFIG_CMD_SAVES diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 653a30d3bd..b5ef8b5c56 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -70,11 +70,7 @@ /*----------------------------------------------------------------------- * Command line configuration. */ -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_IO -#define CONFIG_CMD_IRQ #define CONFIG_CMD_PCI -#define CONFIG_CMD_GETTIME #define CONFIG_SCSI #define CONFIG_CMD_ZBOOT @@ -134,7 +130,6 @@ /*----------------------------------------------------------------------- * USB configuration */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_PCI #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index ea4b739d0b..e8a0c1c33d 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -24,12 +24,8 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) /*Cmd*/ -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO -#undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_MTDPARTS -#undef CONFIG_CMD_DTT -#undef CONFIG_CMD_EEPROM /*Misc*/ #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -78,7 +74,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO 1 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 30b5b34520..1b43620540 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -52,7 +52,6 @@ { 4800, 9600, 19200, 38400, 57600, 115200 } /* Command line configuration */ -#define CONFIG_CMD_ENV #define CONFIG_MP /* BOOTP options */ @@ -184,7 +183,6 @@ /* EEPROM */ #ifdef CONFIG_ZYNQMP_EEPROM -# define CONFIG_CMD_EEPROM # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 # define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 @@ -271,7 +269,6 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT /* u-boot is like dtb */ #define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 8d018da23e..4194b66c66 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -44,7 +44,6 @@ #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_CMD_EEPROM #define CONFIG_ZYNQ_EEPROM_BUS 5 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20 diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index 2a7a48d21d..93afb2062f 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -175,9 +175,6 @@ extern void out32(unsigned int, unsigned long); /* * Command configuration */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_PCI /* diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 447fd9557a..07f26544fd 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -87,17 +87,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ CONFIG_SYS_POST_I2C) -#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ - CONFIG_SYS_I2C_DS4510_ADDR, \ - CONFIG_SYS_I2C_EEPROM_ADDR, \ - CONFIG_SYS_I2C_LM90_ADDR, \ - CONFIG_SYS_I2C_PCA9553_ADDR, \ - CONFIG_SYS_I2C_PCA953X_ADDR0, \ - CONFIG_SYS_I2C_PCA953X_ADDR1, \ - CONFIG_SYS_I2C_PCA953X_ADDR2, \ - CONFIG_SYS_I2C_PCA953X_ADDR3, \ - CONFIG_SYS_I2C_PEX8518_ADDR, \ - CONFIG_SYS_I2C_RTC_ADDR} /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ #define I2C_ADDR_IGNORE_LIST {0x50} @@ -232,9 +221,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 /* I2C DS1631 temperature sensor */ -#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 -#define CONFIG_DTT_DS1621 -#define CONFIG_DTT_SENSORS { 0 } #define CONFIG_SYS_I2C_LM90_ADDR 0x4c /* I2C EEPROM - AT24C128B */ @@ -248,10 +234,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 -/* GPIO/EEPROM/SRAM */ -#define CONFIG_DS4510 -#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 - /* GPIO */ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 @@ -502,12 +484,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Command configuration. */ -#define CONFIG_CMD_DS4510 -#define CONFIG_CMD_DS4510_INFO -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index ffc0d009ba..2645006b37 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -287,8 +287,6 @@ /* * Command configuration. */ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 48f07b08c0..abbaeaad10 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -81,16 +81,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ CONFIG_SYS_POST_I2C) -#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ - CONFIG_SYS_I2C_DS4510_ADDR, \ - CONFIG_SYS_I2C_EEPROM_ADDR, \ - CONFIG_SYS_I2C_LM90_ADDR, \ - CONFIG_SYS_I2C_PCA953X_ADDR0, \ - CONFIG_SYS_I2C_PCA953X_ADDR1, \ - CONFIG_SYS_I2C_PCA953X_ADDR2, \ - CONFIG_SYS_I2C_PCA953X_ADDR3, \ - CONFIG_SYS_I2C_PEX8518_ADDR, \ - CONFIG_SYS_I2C_RTC_ADDR} /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ #define I2C_ADDR_IGNORE_LIST {0x50} @@ -229,9 +219,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 /* I2C DS1631 temperature sensor */ -#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 -#define CONFIG_DTT_DS1621 -#define CONFIG_DTT_SENSORS { 0 } #define CONFIG_SYS_I2C_LM90_ADDR 0x4c /* I2C EEPROM - AT24C128B */ @@ -245,10 +232,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 -/* GPIO/EEPROM/SRAM */ -#define CONFIG_DS4510 -#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 - /* GPIO */ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 @@ -354,11 +337,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * Command configuration. */ -#define CONFIG_CMD_DS4510 -#define CONFIG_CMD_DS4510_INFO -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 2793a9bfb9..254fc12cf6 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -219,8 +219,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 /* I2C DS7505 temperature sensor */ -#define CONFIG_DTT_LM75 -#define CONFIG_DTT_SENSORS { 0 } #define CONFIG_SYS_I2C_LM75_ADDR 0x48 /* I2C ADT7461 temperature sensor */ @@ -332,16 +330,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * USB */ -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* * Command configuration. */ -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NAND #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO diff --git a/include/configs/xpress.h b/include/configs/xpress.h index e3ae4e8f74..e13b792f38 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -64,8 +64,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */ /* USB Configs */ -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 77648d78bc..d9c09b80cd 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -131,14 +131,6 @@ #define CONFIG_ENV_OFFSET 0x0 #endif /* CONFIG_ENV_IS_IN_EEPROM */ -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - /* * Default environment variables */ @@ -184,7 +176,6 @@ /* * Commands additional to the ones defined in amcc-common.h */ -#define CONFIG_CMD_DTT #define CONFIG_CMD_PCI #ifdef CONFIG_440EP diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 841cc6dbb2..9b3769b5f1 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -42,7 +42,6 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_SYS_TEXT_BASE 0x0 -#define CONFIG_LZMA /* LZMA compression support */ /* * Serial Console Configuration @@ -54,7 +53,6 @@ /* * Bootloader Components Configuration */ -#define CONFIG_CMD_ENV /* * MMC Card Configuration diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index c61c353901..c1daf65621 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -82,7 +82,6 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ #define CONFIG_USB_EHCI_MXC #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 51edd463a1..df4765c076 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -145,7 +145,6 @@ /* EEPROM */ #ifdef CONFIG_ZYNQ_EEPROM -# define CONFIG_CMD_EEPROM # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 # define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 @@ -260,10 +259,6 @@ #define CONFIG_FPGA #define CONFIG_FPGA_XILINX #define CONFIG_FPGA_ZYNQPL -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_FPGA_LOADP -#define CONFIG_CMD_FPGA_LOADBP -#define CONFIG_CMD_FPGA_LOADFS /* FIT support */ #define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */ @@ -284,7 +279,6 @@ /* SPL part */ #define CONFIG_CMD_SPL #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds" diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 1488fd8b2f..808967cee3 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -14,7 +14,6 @@ #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_I2C1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_CMD_EEPROM #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50 #define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA #define CONFIG_DISPLAY diff --git a/include/dm/device.h b/include/dm/device.h index 079ec57003..df02e41df3 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -55,6 +55,12 @@ struct driver_info; #define DM_FLAG_ACTIVE_DMA (1 << 9) /* + * Call driver remove function to do some final configuration, before + * U-Boot exits and the OS is started + */ +#define DM_FLAG_OS_PREPARE (1 << 10) + +/* * One or multiple of these flags are passed to device_remove() so that * a selective device removal as specified by the remove-stage and the * driver flags can be done. @@ -66,10 +72,13 @@ enum { /* Remove devices with active DMA */ DM_REMOVE_ACTIVE_DMA = DM_FLAG_ACTIVE_DMA, + /* Remove devices which need some final OS preparation steps */ + DM_REMOVE_OS_PREPARE = DM_FLAG_OS_PREPARE, + /* Add more use cases here */ /* Remove devices with any active flag */ - DM_REMOVE_ACTIVE_ALL = DM_REMOVE_ACTIVE_DMA, + DM_REMOVE_ACTIVE_ALL = DM_REMOVE_ACTIVE_DMA | DM_REMOVE_OS_PREPARE, }; /** diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h new file mode 100644 index 0000000000..a7a1a50f33 --- /dev/null +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7D_H +#define __DT_BINDINGS_CLOCK_IMX7D_H + +#define IMX7D_OSC_24M_CLK 0 +#define IMX7D_PLL_ARM_MAIN 1 +#define IMX7D_PLL_ARM_MAIN_CLK 2 +#define IMX7D_PLL_ARM_MAIN_SRC 3 +#define IMX7D_PLL_ARM_MAIN_BYPASS 4 +#define IMX7D_PLL_SYS_MAIN 5 +#define IMX7D_PLL_SYS_MAIN_CLK 6 +#define IMX7D_PLL_SYS_MAIN_SRC 7 +#define IMX7D_PLL_SYS_MAIN_BYPASS 8 +#define IMX7D_PLL_SYS_MAIN_480M 9 +#define IMX7D_PLL_SYS_MAIN_240M 10 +#define IMX7D_PLL_SYS_MAIN_120M 11 +#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 +#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 +#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 +#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 +#define IMX7D_PLL_SYS_PFD0_196M 16 +#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 +#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 +#define IMX7D_PLL_SYS_PFD1_166M 19 +#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 +#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 +#define IMX7D_PLL_SYS_PFD2_135M 22 +#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 +#define IMX7D_PLL_SYS_PFD3_CLK 24 +#define IMX7D_PLL_SYS_PFD4_CLK 25 +#define IMX7D_PLL_SYS_PFD5_CLK 26 +#define IMX7D_PLL_SYS_PFD6_CLK 27 +#define IMX7D_PLL_SYS_PFD7_CLK 28 +#define IMX7D_PLL_ENET_MAIN 29 +#define IMX7D_PLL_ENET_MAIN_CLK 30 +#define IMX7D_PLL_ENET_MAIN_SRC 31 +#define IMX7D_PLL_ENET_MAIN_BYPASS 32 +#define IMX7D_PLL_ENET_MAIN_500M 33 +#define IMX7D_PLL_ENET_MAIN_250M 34 +#define IMX7D_PLL_ENET_MAIN_125M 35 +#define IMX7D_PLL_ENET_MAIN_100M 36 +#define IMX7D_PLL_ENET_MAIN_50M 37 +#define IMX7D_PLL_ENET_MAIN_40M 38 +#define IMX7D_PLL_ENET_MAIN_25M 39 +#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 +#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 +#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 +#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 +#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 +#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 +#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 +#define IMX7D_PLL_DRAM_MAIN 47 +#define IMX7D_PLL_DRAM_MAIN_CLK 48 +#define IMX7D_PLL_DRAM_MAIN_SRC 49 +#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 +#define IMX7D_PLL_DRAM_MAIN_533M 51 +#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 +#define IMX7D_PLL_AUDIO_MAIN 53 +#define IMX7D_PLL_AUDIO_MAIN_CLK 54 +#define IMX7D_PLL_AUDIO_MAIN_SRC 55 +#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 +#define IMX7D_PLL_VIDEO_MAIN_CLK 57 +#define IMX7D_PLL_VIDEO_MAIN 58 +#define IMX7D_PLL_VIDEO_MAIN_SRC 59 +#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 +#define IMX7D_USB_MAIN_480M_CLK 61 +#define IMX7D_ARM_A7_ROOT_CLK 62 +#define IMX7D_ARM_A7_ROOT_SRC 63 +#define IMX7D_ARM_A7_ROOT_CG 64 +#define IMX7D_ARM_A7_ROOT_DIV 65 +#define IMX7D_ARM_M4_ROOT_CLK 66 +#define IMX7D_ARM_M4_ROOT_SRC 67 +#define IMX7D_ARM_M4_ROOT_CG 68 +#define IMX7D_ARM_M4_ROOT_DIV 69 +#define IMX7D_ARM_M0_ROOT_CLK 70 +#define IMX7D_ARM_M0_ROOT_SRC 71 +#define IMX7D_ARM_M0_ROOT_CG 72 +#define IMX7D_ARM_M0_ROOT_DIV 73 +#define IMX7D_MAIN_AXI_ROOT_CLK 74 +#define IMX7D_MAIN_AXI_ROOT_SRC 75 +#define IMX7D_MAIN_AXI_ROOT_CG 76 +#define IMX7D_MAIN_AXI_ROOT_DIV 77 +#define IMX7D_DISP_AXI_ROOT_CLK 78 +#define IMX7D_DISP_AXI_ROOT_SRC 79 +#define IMX7D_DISP_AXI_ROOT_CG 80 +#define IMX7D_DISP_AXI_ROOT_DIV 81 +#define IMX7D_ENET_AXI_ROOT_CLK 82 +#define IMX7D_ENET_AXI_ROOT_SRC 83 +#define IMX7D_ENET_AXI_ROOT_CG 84 +#define IMX7D_ENET_AXI_ROOT_DIV 85 +#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 +#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 +#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 +#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 +#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 +#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 +#define IMX7D_AHB_CHANNEL_ROOT_CG 92 +#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 +#define IMX7D_DRAM_PHYM_ROOT_CLK 94 +#define IMX7D_DRAM_PHYM_ROOT_SRC 95 +#define IMX7D_DRAM_PHYM_ROOT_CG 96 +#define IMX7D_DRAM_PHYM_ROOT_DIV 97 +#define IMX7D_DRAM_ROOT_CLK 98 +#define IMX7D_DRAM_ROOT_SRC 99 +#define IMX7D_DRAM_ROOT_CG 100 +#define IMX7D_DRAM_ROOT_DIV 101 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 +#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 +#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 +#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 +#define IMX7D_DRAM_ALT_ROOT_CLK 106 +#define IMX7D_DRAM_ALT_ROOT_SRC 107 +#define IMX7D_DRAM_ALT_ROOT_CG 108 +#define IMX7D_DRAM_ALT_ROOT_DIV 109 +#define IMX7D_USB_HSIC_ROOT_CLK 110 +#define IMX7D_USB_HSIC_ROOT_SRC 111 +#define IMX7D_USB_HSIC_ROOT_CG 112 +#define IMX7D_USB_HSIC_ROOT_DIV 113 +#define IMX7D_PCIE_CTRL_ROOT_CLK 114 +#define IMX7D_PCIE_CTRL_ROOT_SRC 115 +#define IMX7D_PCIE_CTRL_ROOT_CG 116 +#define IMX7D_PCIE_CTRL_ROOT_DIV 117 +#define IMX7D_PCIE_PHY_ROOT_CLK 118 +#define IMX7D_PCIE_PHY_ROOT_SRC 119 +#define IMX7D_PCIE_PHY_ROOT_CG 120 +#define IMX7D_PCIE_PHY_ROOT_DIV 121 +#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 +#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 +#define IMX7D_EPDC_PIXEL_ROOT_CG 124 +#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 +#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 +#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 +#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 +#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 +#define IMX7D_MIPI_DSI_ROOT_CLK 130 +#define IMX7D_MIPI_DSI_ROOT_SRC 131 +#define IMX7D_MIPI_DSI_ROOT_CG 132 +#define IMX7D_MIPI_DSI_ROOT_DIV 133 +#define IMX7D_MIPI_CSI_ROOT_CLK 134 +#define IMX7D_MIPI_CSI_ROOT_SRC 135 +#define IMX7D_MIPI_CSI_ROOT_CG 136 +#define IMX7D_MIPI_CSI_ROOT_DIV 137 +#define IMX7D_MIPI_DPHY_ROOT_CLK 138 +#define IMX7D_MIPI_DPHY_ROOT_SRC 139 +#define IMX7D_MIPI_DPHY_ROOT_CG 140 +#define IMX7D_MIPI_DPHY_ROOT_DIV 141 +#define IMX7D_SAI1_ROOT_CLK 142 +#define IMX7D_SAI1_ROOT_SRC 143 +#define IMX7D_SAI1_ROOT_CG 144 +#define IMX7D_SAI1_ROOT_DIV 145 +#define IMX7D_SAI2_ROOT_CLK 146 +#define IMX7D_SAI2_ROOT_SRC 147 +#define IMX7D_SAI2_ROOT_CG 148 +#define IMX7D_SAI2_ROOT_DIV 149 +#define IMX7D_SAI3_ROOT_CLK 150 +#define IMX7D_SAI3_ROOT_SRC 151 +#define IMX7D_SAI3_ROOT_CG 152 +#define IMX7D_SAI3_ROOT_DIV 153 +#define IMX7D_SPDIF_ROOT_CLK 154 +#define IMX7D_SPDIF_ROOT_SRC 155 +#define IMX7D_SPDIF_ROOT_CG 156 +#define IMX7D_SPDIF_ROOT_DIV 157 +#define IMX7D_ENET1_REF_ROOT_CLK 158 +#define IMX7D_ENET1_REF_ROOT_SRC 159 +#define IMX7D_ENET1_REF_ROOT_CG 160 +#define IMX7D_ENET1_REF_ROOT_DIV 161 +#define IMX7D_ENET1_TIME_ROOT_CLK 162 +#define IMX7D_ENET1_TIME_ROOT_SRC 163 +#define IMX7D_ENET1_TIME_ROOT_CG 164 +#define IMX7D_ENET1_TIME_ROOT_DIV 165 +#define IMX7D_ENET2_REF_ROOT_CLK 166 +#define IMX7D_ENET2_REF_ROOT_SRC 167 +#define IMX7D_ENET2_REF_ROOT_CG 168 +#define IMX7D_ENET2_REF_ROOT_DIV 169 +#define IMX7D_ENET2_TIME_ROOT_CLK 170 +#define IMX7D_ENET2_TIME_ROOT_SRC 171 +#define IMX7D_ENET2_TIME_ROOT_CG 172 +#define IMX7D_ENET2_TIME_ROOT_DIV 173 +#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 +#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 +#define IMX7D_ENET_PHY_REF_ROOT_CG 176 +#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 +#define IMX7D_EIM_ROOT_CLK 178 +#define IMX7D_EIM_ROOT_SRC 179 +#define IMX7D_EIM_ROOT_CG 180 +#define IMX7D_EIM_ROOT_DIV 181 +#define IMX7D_NAND_ROOT_CLK 182 +#define IMX7D_NAND_ROOT_SRC 183 +#define IMX7D_NAND_ROOT_CG 184 +#define IMX7D_NAND_ROOT_DIV 185 +#define IMX7D_QSPI_ROOT_CLK 186 +#define IMX7D_QSPI_ROOT_SRC 187 +#define IMX7D_QSPI_ROOT_CG 188 +#define IMX7D_QSPI_ROOT_DIV 189 +#define IMX7D_USDHC1_ROOT_CLK 190 +#define IMX7D_USDHC1_ROOT_SRC 191 +#define IMX7D_USDHC1_ROOT_CG 192 +#define IMX7D_USDHC1_ROOT_DIV 193 +#define IMX7D_USDHC2_ROOT_CLK 194 +#define IMX7D_USDHC2_ROOT_SRC 195 +#define IMX7D_USDHC2_ROOT_CG 196 +#define IMX7D_USDHC2_ROOT_DIV 197 +#define IMX7D_USDHC3_ROOT_CLK 198 +#define IMX7D_USDHC3_ROOT_SRC 199 +#define IMX7D_USDHC3_ROOT_CG 200 +#define IMX7D_USDHC3_ROOT_DIV 201 +#define IMX7D_CAN1_ROOT_CLK 202 +#define IMX7D_CAN1_ROOT_SRC 203 +#define IMX7D_CAN1_ROOT_CG 204 +#define IMX7D_CAN1_ROOT_DIV 205 +#define IMX7D_CAN2_ROOT_CLK 206 +#define IMX7D_CAN2_ROOT_SRC 207 +#define IMX7D_CAN2_ROOT_CG 208 +#define IMX7D_CAN2_ROOT_DIV 209 +#define IMX7D_I2C1_ROOT_CLK 210 +#define IMX7D_I2C1_ROOT_SRC 211 +#define IMX7D_I2C1_ROOT_CG 212 +#define IMX7D_I2C1_ROOT_DIV 213 +#define IMX7D_I2C2_ROOT_CLK 214 +#define IMX7D_I2C2_ROOT_SRC 215 +#define IMX7D_I2C2_ROOT_CG 216 +#define IMX7D_I2C2_ROOT_DIV 217 +#define IMX7D_I2C3_ROOT_CLK 218 +#define IMX7D_I2C3_ROOT_SRC 219 +#define IMX7D_I2C3_ROOT_CG 220 +#define IMX7D_I2C3_ROOT_DIV 221 +#define IMX7D_I2C4_ROOT_CLK 222 +#define IMX7D_I2C4_ROOT_SRC 223 +#define IMX7D_I2C4_ROOT_CG 224 +#define IMX7D_I2C4_ROOT_DIV 225 +#define IMX7D_UART1_ROOT_CLK 226 +#define IMX7D_UART1_ROOT_SRC 227 +#define IMX7D_UART1_ROOT_CG 228 +#define IMX7D_UART1_ROOT_DIV 229 +#define IMX7D_UART2_ROOT_CLK 230 +#define IMX7D_UART2_ROOT_SRC 231 +#define IMX7D_UART2_ROOT_CG 232 +#define IMX7D_UART2_ROOT_DIV 233 +#define IMX7D_UART3_ROOT_CLK 234 +#define IMX7D_UART3_ROOT_SRC 235 +#define IMX7D_UART3_ROOT_CG 236 +#define IMX7D_UART3_ROOT_DIV 237 +#define IMX7D_UART4_ROOT_CLK 238 +#define IMX7D_UART4_ROOT_SRC 239 +#define IMX7D_UART4_ROOT_CG 240 +#define IMX7D_UART4_ROOT_DIV 241 +#define IMX7D_UART5_ROOT_CLK 242 +#define IMX7D_UART5_ROOT_SRC 243 +#define IMX7D_UART5_ROOT_CG 244 +#define IMX7D_UART5_ROOT_DIV 245 +#define IMX7D_UART6_ROOT_CLK 246 +#define IMX7D_UART6_ROOT_SRC 247 +#define IMX7D_UART6_ROOT_CG 248 +#define IMX7D_UART6_ROOT_DIV 249 +#define IMX7D_UART7_ROOT_CLK 250 +#define IMX7D_UART7_ROOT_SRC 251 +#define IMX7D_UART7_ROOT_CG 252 +#define IMX7D_UART7_ROOT_DIV 253 +#define IMX7D_ECSPI1_ROOT_CLK 254 +#define IMX7D_ECSPI1_ROOT_SRC 255 +#define IMX7D_ECSPI1_ROOT_CG 256 +#define IMX7D_ECSPI1_ROOT_DIV 257 +#define IMX7D_ECSPI2_ROOT_CLK 258 +#define IMX7D_ECSPI2_ROOT_SRC 259 +#define IMX7D_ECSPI2_ROOT_CG 260 +#define IMX7D_ECSPI2_ROOT_DIV 261 +#define IMX7D_ECSPI3_ROOT_CLK 262 +#define IMX7D_ECSPI3_ROOT_SRC 263 +#define IMX7D_ECSPI3_ROOT_CG 264 +#define IMX7D_ECSPI3_ROOT_DIV 265 +#define IMX7D_ECSPI4_ROOT_CLK 266 +#define IMX7D_ECSPI4_ROOT_SRC 267 +#define IMX7D_ECSPI4_ROOT_CG 268 +#define IMX7D_ECSPI4_ROOT_DIV 269 +#define IMX7D_PWM1_ROOT_CLK 270 +#define IMX7D_PWM1_ROOT_SRC 271 +#define IMX7D_PWM1_ROOT_CG 272 +#define IMX7D_PWM1_ROOT_DIV 273 +#define IMX7D_PWM2_ROOT_CLK 274 +#define IMX7D_PWM2_ROOT_SRC 275 +#define IMX7D_PWM2_ROOT_CG 276 +#define IMX7D_PWM2_ROOT_DIV 277 +#define IMX7D_PWM3_ROOT_CLK 278 +#define IMX7D_PWM3_ROOT_SRC 279 +#define IMX7D_PWM3_ROOT_CG 280 +#define IMX7D_PWM3_ROOT_DIV 281 +#define IMX7D_PWM4_ROOT_CLK 282 +#define IMX7D_PWM4_ROOT_SRC 283 +#define IMX7D_PWM4_ROOT_CG 284 +#define IMX7D_PWM4_ROOT_DIV 285 +#define IMX7D_FLEXTIMER1_ROOT_CLK 286 +#define IMX7D_FLEXTIMER1_ROOT_SRC 287 +#define IMX7D_FLEXTIMER1_ROOT_CG 288 +#define IMX7D_FLEXTIMER1_ROOT_DIV 289 +#define IMX7D_FLEXTIMER2_ROOT_CLK 290 +#define IMX7D_FLEXTIMER2_ROOT_SRC 291 +#define IMX7D_FLEXTIMER2_ROOT_CG 292 +#define IMX7D_FLEXTIMER2_ROOT_DIV 293 +#define IMX7D_SIM1_ROOT_CLK 294 +#define IMX7D_SIM1_ROOT_SRC 295 +#define IMX7D_SIM1_ROOT_CG 296 +#define IMX7D_SIM1_ROOT_DIV 297 +#define IMX7D_SIM2_ROOT_CLK 298 +#define IMX7D_SIM2_ROOT_SRC 299 +#define IMX7D_SIM2_ROOT_CG 300 +#define IMX7D_SIM2_ROOT_DIV 301 +#define IMX7D_GPT1_ROOT_CLK 302 +#define IMX7D_GPT1_ROOT_SRC 303 +#define IMX7D_GPT1_ROOT_CG 304 +#define IMX7D_GPT1_ROOT_DIV 305 +#define IMX7D_GPT2_ROOT_CLK 306 +#define IMX7D_GPT2_ROOT_SRC 307 +#define IMX7D_GPT2_ROOT_CG 308 +#define IMX7D_GPT2_ROOT_DIV 309 +#define IMX7D_GPT3_ROOT_CLK 310 +#define IMX7D_GPT3_ROOT_SRC 311 +#define IMX7D_GPT3_ROOT_CG 312 +#define IMX7D_GPT3_ROOT_DIV 313 +#define IMX7D_GPT4_ROOT_CLK 314 +#define IMX7D_GPT4_ROOT_SRC 315 +#define IMX7D_GPT4_ROOT_CG 316 +#define IMX7D_GPT4_ROOT_DIV 317 +#define IMX7D_TRACE_ROOT_CLK 318 +#define IMX7D_TRACE_ROOT_SRC 319 +#define IMX7D_TRACE_ROOT_CG 320 +#define IMX7D_TRACE_ROOT_DIV 321 +#define IMX7D_WDOG1_ROOT_CLK 322 +#define IMX7D_WDOG_ROOT_SRC 323 +#define IMX7D_WDOG_ROOT_CG 324 +#define IMX7D_WDOG_ROOT_DIV 325 +#define IMX7D_CSI_MCLK_ROOT_CLK 326 +#define IMX7D_CSI_MCLK_ROOT_SRC 327 +#define IMX7D_CSI_MCLK_ROOT_CG 328 +#define IMX7D_CSI_MCLK_ROOT_DIV 329 +#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 +#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 +#define IMX7D_AUDIO_MCLK_ROOT_CG 332 +#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 +#define IMX7D_WRCLK_ROOT_CLK 334 +#define IMX7D_WRCLK_ROOT_SRC 335 +#define IMX7D_WRCLK_ROOT_CG 336 +#define IMX7D_WRCLK_ROOT_DIV 337 +#define IMX7D_CLKO1_ROOT_SRC 338 +#define IMX7D_CLKO1_ROOT_CG 339 +#define IMX7D_CLKO1_ROOT_DIV 340 +#define IMX7D_CLKO2_ROOT_SRC 341 +#define IMX7D_CLKO2_ROOT_CG 342 +#define IMX7D_CLKO2_ROOT_DIV 343 +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 +#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 +#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 +#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 +#define IMX7D_SAI1_ROOT_PRE_DIV 357 +#define IMX7D_SAI2_ROOT_PRE_DIV 358 +#define IMX7D_SAI3_ROOT_PRE_DIV 359 +#define IMX7D_SPDIF_ROOT_PRE_DIV 360 +#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 +#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 +#define IMX7D_EIM_ROOT_PRE_DIV 366 +#define IMX7D_NAND_ROOT_PRE_DIV 367 +#define IMX7D_QSPI_ROOT_PRE_DIV 368 +#define IMX7D_USDHC1_ROOT_PRE_DIV 369 +#define IMX7D_USDHC2_ROOT_PRE_DIV 370 +#define IMX7D_USDHC3_ROOT_PRE_DIV 371 +#define IMX7D_CAN1_ROOT_PRE_DIV 372 +#define IMX7D_CAN2_ROOT_PRE_DIV 373 +#define IMX7D_I2C1_ROOT_PRE_DIV 374 +#define IMX7D_I2C2_ROOT_PRE_DIV 375 +#define IMX7D_I2C3_ROOT_PRE_DIV 376 +#define IMX7D_I2C4_ROOT_PRE_DIV 377 +#define IMX7D_UART1_ROOT_PRE_DIV 378 +#define IMX7D_UART2_ROOT_PRE_DIV 379 +#define IMX7D_UART3_ROOT_PRE_DIV 380 +#define IMX7D_UART4_ROOT_PRE_DIV 381 +#define IMX7D_UART5_ROOT_PRE_DIV 382 +#define IMX7D_UART6_ROOT_PRE_DIV 383 +#define IMX7D_UART7_ROOT_PRE_DIV 384 +#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 +#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 +#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 +#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 +#define IMX7D_PWM1_ROOT_PRE_DIV 389 +#define IMX7D_PWM2_ROOT_PRE_DIV 390 +#define IMX7D_PWM3_ROOT_PRE_DIV 391 +#define IMX7D_PWM4_ROOT_PRE_DIV 392 +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 +#define IMX7D_SIM1_ROOT_PRE_DIV 395 +#define IMX7D_SIM2_ROOT_PRE_DIV 396 +#define IMX7D_GPT1_ROOT_PRE_DIV 397 +#define IMX7D_GPT2_ROOT_PRE_DIV 398 +#define IMX7D_GPT3_ROOT_PRE_DIV 399 +#define IMX7D_GPT4_ROOT_PRE_DIV 400 +#define IMX7D_TRACE_ROOT_PRE_DIV 401 +#define IMX7D_WDOG_ROOT_PRE_DIV 402 +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 +#define IMX7D_WRCLK_ROOT_PRE_DIV 405 +#define IMX7D_CLKO1_ROOT_PRE_DIV 406 +#define IMX7D_CLKO2_ROOT_PRE_DIV 407 +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 +#define IMX7D_LVDS1_IN_CLK 410 +#define IMX7D_LVDS1_OUT_SEL 411 +#define IMX7D_LVDS1_OUT_CLK 412 +#define IMX7D_CLK_DUMMY 413 +#define IMX7D_GPT_3M_CLK 414 +#define IMX7D_OCRAM_CLK 415 +#define IMX7D_OCRAM_S_CLK 416 +#define IMX7D_WDOG2_ROOT_CLK 417 +#define IMX7D_WDOG3_ROOT_CLK 418 +#define IMX7D_WDOG4_ROOT_CLK 419 +#define IMX7D_SDMA_CORE_CLK 420 +#define IMX7D_USB1_MAIN_480M_CLK 421 +#define IMX7D_USB_CTRL_CLK 422 +#define IMX7D_USB_PHY1_CLK 423 +#define IMX7D_USB_PHY2_CLK 424 +#define IMX7D_IPG_ROOT_CLK 425 +#define IMX7D_SAI1_IPG_CLK 426 +#define IMX7D_SAI2_IPG_CLK 427 +#define IMX7D_SAI3_IPG_CLK 428 +#define IMX7D_PLL_AUDIO_TEST_DIV 429 +#define IMX7D_PLL_AUDIO_POST_DIV 430 +#define IMX7D_PLL_VIDEO_TEST_DIV 431 +#define IMX7D_PLL_VIDEO_POST_DIV 432 +#define IMX7D_MU_ROOT_CLK 433 +#define IMX7D_SEMA4_HS_ROOT_CLK 434 +#define IMX7D_PLL_DRAM_TEST_DIV 435 +#define IMX7D_ADC_ROOT_CLK 436 +#define IMX7D_CLK_ARM 437 +#define IMX7D_CKIL 438 +#define IMX7D_OCOTP_CLK 439 +#define IMX7D_CLK_END 440 +#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h new file mode 100644 index 0000000000..acb0bbf4f9 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define QSPI_RESET 38 +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +#define QSPI_OCP_RESET 46 +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define L4WD0_RESET 64 +#define L4WD1_RESET 65 +#define L4SYSTIMER0_RESET 66 +#define L4SYSTIMER1_RESET 67 +#define SPTIMER0_RESET 68 +#define SPTIMER1_RESET 69 +/* 70-71 is reserved */ +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is reserved */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is reserved */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 +#define GPIO2_RESET 90 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 +#define F2SSDRAM0_RESET 99 +#define F2SSDRAM1_RESET 100 +#define F2SSDRAM2_RESET 101 +#define DDRSCH_RESET 102 + +/* SYSMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +/* 130 is reserved */ +#define FPGAMGR_RESET 131 +#define S2F_RESET 132 +#define SYSDBG_RESET 133 +#define OCRAM_OCP_RESET 134 + +/* COLDMODRST */ +#define CLKMGRCOLD_RESET 160 +/* 161-162 is reserved */ +#define S2FCOLD_RESET 163 +#define TIMESTAMPCOLD_RESET 164 +#define TAPCOLD_RESET 165 +#define HMCCOLD_RESET 166 +#define IOMGRCOLD_RESET 167 + +/* NRSTMODRST */ +#define NRSTPINOE_RESET 192 + +/* DBGMODRST */ +#define DBG_RESET 224 +#endif diff --git a/include/dtt.h b/include/dtt.h deleted file mode 100644 index 173159dc62..0000000000 --- a/include/dtt.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Digital Thermometers and Thermostats. - */ -#ifndef _DTT_H_ -#define _DTT_H_ - -#if defined(CONFIG_DTT_ADM1021) || \ - defined(CONFIG_DTT_ADT7460) || \ - defined(CONFIG_DTT_DS1621) || \ - defined(CONFIG_DTT_DS1775) || \ - defined(CONFIG_DTT_DS620) || \ - defined(CONFIG_DTT_LM63) || \ - defined(CONFIG_DTT_LM73) || \ - defined(CONFIG_DTT_LM75) || \ - defined(CONFIG_DTT_LM81) - -#define CONFIG_DTT /* We have a DTT */ - -#ifndef CONFIG_DTT_ADM1021 -#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */ -#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */ -#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */ - -#ifndef CONFIG_SYS_DTT_MAX_TEMP -#define CONFIG_SYS_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP -#endif - -#ifndef CONFIG_SYS_DTT_HYSTERESIS -#define CONFIG_SYS_DTT_HYSTERESIS 5 /* 5 C */ -#endif -#endif /* CONFIG_DTT_ADM1021 */ - -extern void dtt_init(void); -extern int dtt_init_one(int); -extern int dtt_read(int sensor, int reg); -extern int dtt_write(int sensor, int reg, int val); -extern int dtt_get_temp(int sensor); -#endif - -#endif /* _DTT_H_ */ diff --git a/include/edid.h b/include/edid.h index 8b022fa98a..a9f2f3d3ab 100644 --- a/include/edid.h +++ b/include/edid.h @@ -19,6 +19,9 @@ #define EDID_SIZE 128 #define EDID_EXT_SIZE 256 +/* OUI of HDMI vendor specific data block */ +#define HDMI_IEEE_OUI 0x000c03 + #define GET_BIT(_x, _pos) \ (((_x) >> (_pos)) & 1) #define GET_BITS(_x, _pos_msb, _pos_lsb) \ @@ -234,6 +237,13 @@ struct edid1_info { unsigned char checksum; } __attribute__ ((__packed__)); +enum edid_cea861_db_types { + EDID_CEA861_DB_AUDIO = 0x01, + EDID_CEA861_DB_VIDEO = 0x02, + EDID_CEA861_DB_VENDOR = 0x03, + EDID_CEA861_DB_SPEAKER = 0x04, +}; + struct edid_cea861_info { unsigned char extension_tag; #define EDID_CEA861_EXTENSION_TAG 0x02 @@ -251,6 +261,10 @@ struct edid_cea861_info { #define EDID_CEA861_DTD_COUNT(_x) \ GET_BITS(((_x).dtd_count), 3, 0) unsigned char data[124]; +#define EDID_CEA861_DB_TYPE(_x, offset) \ + GET_BITS((_x).data[offset], 7, 5) +#define EDID_CEA861_DB_LEN(_x, offset) \ + GET_BITS((_x).data[offset], 4, 0) } __attribute__ ((__packed__)); /** diff --git a/include/fdtdec.h b/include/fdtdec.h index b0e5b2767d..3000ecbb58 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -967,6 +967,7 @@ struct display_timing { struct timing_entry vsync_len; /* ver. sync len */ enum display_flags flags; /* display flags */ + bool hdmi_monitor; /* is hdmi monitor? */ }; /** diff --git a/include/i2c.h b/include/i2c.h index cd7f61e1c1..2c1643d650 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -571,9 +571,6 @@ void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs); #if !defined(CONFIG_SYS_RTC_BUS_NUM) #define CONFIG_SYS_RTC_BUS_NUM 0 #endif -#if !defined(CONFIG_SYS_DTT_BUS_NUM) -#define CONFIG_SYS_DTT_BUS_NUM 0 -#endif #if !defined(CONFIG_SYS_SPD_BUS_NUM) #define CONFIG_SYS_SPD_BUS_NUM 0 #endif @@ -706,9 +703,6 @@ void i2c_early_init_f(void); #endif void i2c_init(int speed, int slaveaddr); void i2c_init_board(void); -#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT -void i2c_board_late_init(void); -#endif #ifdef CONFIG_SYS_I2C /* diff --git a/include/image.h b/include/image.h index 3f26f9bd1f..8d380e0e84 100644 --- a/include/image.h +++ b/include/image.h @@ -29,6 +29,9 @@ struct lmb; #define IMAGE_ENABLE_FIT 1 #define IMAGE_ENABLE_OF_LIBFDT 1 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ +#define CONFIG_FIT_ENABLE_SHA256_SUPPORT +#define CONFIG_SHA1 +#define CONFIG_SHA256 #define IMAGE_ENABLE_IGNORE 0 #define IMAGE_INDENT_STRING "" @@ -62,24 +65,13 @@ struct lmb; # ifdef CONFIG_SPL_SHA1_SUPPORT # define IMAGE_ENABLE_SHA1 1 # endif -# ifdef CONFIG_SPL_SHA256_SUPPORT -# define IMAGE_ENABLE_SHA256 1 -# endif # else # define CONFIG_CRC32 /* FIT images need CRC32 support */ -# define CONFIG_SHA1 /* and SHA1 */ -# define CONFIG_SHA256 /* and SHA256 */ # define IMAGE_ENABLE_CRC32 1 # define IMAGE_ENABLE_MD5 1 # define IMAGE_ENABLE_SHA1 1 -# define IMAGE_ENABLE_SHA256 1 # endif -#ifdef CONFIG_FIT_DISABLE_SHA256 -#undef CONFIG_SHA256 -#undef IMAGE_ENABLE_SHA256 -#endif - #ifndef IMAGE_ENABLE_CRC32 #define IMAGE_ENABLE_CRC32 0 #endif @@ -92,7 +84,10 @@ struct lmb; #define IMAGE_ENABLE_SHA1 0 #endif -#ifndef IMAGE_ENABLE_SHA256 +#if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \ + defined(CONFIG_SPL_SHA256_SUPPORT) +#define IMAGE_ENABLE_SHA256 1 +#else #define IMAGE_ENABLE_SHA256 0 #endif diff --git a/include/mmc.h b/include/mmc.h index fad12d608c..8346b0e19e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -585,18 +585,6 @@ int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); int mmc_get_env_dev(void); -struct pci_device_id; - -/** - * pci_mmc_init() - set up PCI MMC devices - * - * This finds all the matching PCI IDs and sets them up as MMC devices. - * - * @name: Name to use for devices - * @mmc_supported: PCI IDs to search for, terminated by {0, 0} - */ -int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported); - /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 diff --git a/include/pcmcia.h b/include/pcmcia.h index c8a730c4d0..aaaf6511a8 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -16,7 +16,7 @@ * or try to generate a useful default */ #if defined(CONFIG_CMD_PCMCIA) || \ - (defined(CONFIG_CMD_IDE) && \ + (defined(CONFIG_IDE) && \ (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) @@ -268,7 +268,7 @@ extern u_int *pcmcia_pgcrx[]; #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) extern int check_ide_device(int slot); #endif diff --git a/include/spl.h b/include/spl.h index d1638e9d7c..ffadce93c7 100644 --- a/include/spl.h +++ b/include/spl.h @@ -267,4 +267,5 @@ int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr); int spl_mmc_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev); +void bl31_entry(void); #endif diff --git a/include/tws.h b/include/tws.h deleted file mode 100644 index 7dd5268125..0000000000 --- a/include/tws.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TWS_H_ -#define _TWS_H_ - -/* - * Read/Write interface: - * buffer: Where to read/write the data - * len: How many bits to read/write - * - * Returns: 0 on success, not 0 on failure - */ -int tws_read(uchar *buffer, int len); -int tws_write(uchar *buffer, int len); - -#endif /* _TWS_H_ */ diff --git a/include/usb.h b/include/usb.h index 02a0ccdd77..62f051fe53 100644 --- a/include/usb.h +++ b/include/usb.h @@ -187,7 +187,8 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); -#if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_HOST || defined(CONFIG_DM_USB) +#if defined CONFIG_USB_EHCI_HCD || defined CONFIG_USB_MUSB_HOST \ + || defined(CONFIG_DM_USB) struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, int elementsize, void *buffer, int interval); int destroy_int_queue(struct usb_device *dev, struct int_queue *queue); diff --git a/lib/Kconfig b/lib/Kconfig index db0915153c..09670f031c 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -148,6 +148,14 @@ config LZ4 frame format currently (2015) implemented in the Linux kernel (generated by 'lz4 -l'). The two formats are incompatible. +config LZMA + bool "Enable LZMA decompression support" + help + This enables support for LZMA (Lempel-Ziv-Markov chain algorithm), + a dictionary compression algorithm that provides a high compression + ratio and fairly fast decompression speed. See also + CONFIG_CMD_LZMADEC which provides a decode command. + config LZO bool endmenu diff --git a/lib/Makefile b/lib/Makefile index 23e9f1ef11..328b4a25c3 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -44,9 +44,9 @@ obj-$(CONFIG_BITREVERSE) += bitrev.o obj-y += list_sort.o endif -obj-$(CONFIG_$(SPL_)RSA) += rsa/ -obj-$(CONFIG_$(SPL_)SHA1) += sha1.o -obj-$(CONFIG_$(SPL_)SHA256) += sha256.o +obj-$(CONFIG_RSA) += rsa/ +obj-$(CONFIG_SHA1) += sha1.o +obj-$(CONFIG_SHA256) += sha256.o obj-$(CONFIG_SPL_SAVEENV) += qsort.o obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/ diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn index 7b2cffce52..90dc149df3 100644 --- a/scripts/Makefile.extrawarn +++ b/scripts/Makefile.extrawarn @@ -58,9 +58,23 @@ endif KBUILD_CFLAGS += $(warning) +dtc-warning-2 += $(call dtc-option,-Wnode_name_chars_strict) +dtc-warning-2 += $(call dtc-option,-Wproperty_name_chars_strict) + +dtc-warning := $(dtc-warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +dtc-warning += $(dtc-warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) +dtc-warning += $(dtc-warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS))) + +DTC_FLAGS += $(dtc-warning) + else # Disable noisy checks by default DTC_FLAGS += $(call dtc-option,-Wno-unit_address_vs_reg) +DTC_FLAGS += $(call dtc-option,-Wno-simple_bus_reg) +DTC_FLAGS += $(call dtc-option,-Wno-unit_address_format) +DTC_FLAGS += $(call dtc-option,-Wno-pci_bridge) +DTC_FLAGS += $(call dtc-option,-Wno-pci_device_bus_num) +DTC_FLAGS += $(call dtc-option,-Wno-pci_device_reg) endif diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 23be324369..774aa89a3f 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -308,10 +308,10 @@ $(obj)/%.dtb.S: $(obj)/%.dtb quiet_cmd_dtc = DTC $@ # Modified for U-Boot -# Bring in any U-Boot-specific include after the '/dts-v1/;' header +# Bring in any U-Boot-specific include at the end of the file cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ cat $< $(if $(u_boot_dtsi),\ - | sed '/^\/ {$$/{x;s%$$%\#include \"$(u_boot_dtsi)\"%;G;}') | \ + | sed "$$ a\#include \"$(u_boot_dtsi)\"") | \ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; \ $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) $(DTC_FLAGS) \ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 182b3002c1..135706f21d 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -304,7 +304,8 @@ $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage) quiet_cmd_mksunxiboot = MKSUNXI $@ -cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@ +cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \ + --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@ $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mksunxiboot) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7646bb6842..e8f49ebe5d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -236,7 +236,6 @@ CONFIG_BL1_SIZE CONFIG_BL2_OFFSET CONFIG_BL2_SIZE CONFIG_BMP_16BPP -CONFIG_BMP_24BMP CONFIG_BMP_24BPP CONFIG_BMP_32BPP CONFIG_BOARDDIR @@ -384,48 +383,6 @@ CONFIG_CM922T_XA10 CONFIG_CMDLINE_EDITING CONFIG_CMDLINE_PS_SUPPORT CONFIG_CMDLINE_TAG -CONFIG_CMD_DS4510 -CONFIG_CMD_DS4510_INFO -CONFIG_CMD_DS4510_MEM -CONFIG_CMD_DS4510_RST -CONFIG_CMD_DTT -CONFIG_CMD_ECCTEST -CONFIG_CMD_EECONFIG -CONFIG_CMD_EEPROM -CONFIG_CMD_EEPROM_LAYOUT -CONFIG_CMD_ENTERRCM -CONFIG_CMD_ENV -CONFIG_CMD_ENV_CALLBACK -CONFIG_CMD_ENV_FLAGS -CONFIG_CMD_ERRATA -CONFIG_CMD_ESBC_VALIDATE -CONFIG_CMD_ETHSW -CONFIG_CMD_FDC -CONFIG_CMD_FDT_MAX_DUMP -CONFIG_CMD_FPGAD -CONFIG_CMD_FPGA_LOADBP -CONFIG_CMD_FPGA_LOADFS -CONFIG_CMD_FPGA_LOADMK -CONFIG_CMD_FPGA_LOADP -CONFIG_CMD_FUSE -CONFIG_CMD_GETTIME -CONFIG_CMD_GSC -CONFIG_CMD_HASH -CONFIG_CMD_HD44760 -CONFIG_CMD_HD44780 -CONFIG_CMD_HDMIDETECT -CONFIG_CMD_IDE -CONFIG_CMD_IMMAP -CONFIG_CMD_IMXOTP -CONFIG_CMD_IMX_FUSE -CONFIG_CMD_IO -CONFIG_CMD_IOLOOP -CONFIG_CMD_IOTRACE -CONFIG_CMD_IRQ -CONFIG_CMD_JFFS2 -CONFIG_CMD_KGDB -CONFIG_CMD_LOADY -CONFIG_CMD_LZMADEC CONFIG_CMD_MAX6957 CONFIG_CMD_MEM CONFIG_CMD_MFSL @@ -617,7 +574,6 @@ CONFIG_DEEP_SLEEP CONFIG_DEFAULT CONFIG_DEFAULT_CONSOLE CONFIG_DEFAULT_IMMR -CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC CONFIG_DEFAULT_SPI_BUS CONFIG_DEFAULT_SPI_CS CONFIG_DEFAULT_SPI_MODE @@ -687,22 +643,7 @@ CONFIG_DRIVE_MMC CONFIG_DRIVE_SATA CONFIG_DRIVE_TYPES CONFIG_DRIVE_USB -CONFIG_DS4510 CONFIG_DSP_CLUSTER_START -CONFIG_DTT -CONFIG_DTT_AD7414 -CONFIG_DTT_ADM1021 -CONFIG_DTT_DS1621 -CONFIG_DTT_DS1775 -CONFIG_DTT_DS620 -CONFIG_DTT_HYSTERESIS -CONFIG_DTT_LM63 -CONFIG_DTT_LM75 -CONFIG_DTT_MAX_TEMP -CONFIG_DTT_MIN_TEMP -CONFIG_DTT_PWM_LOOKUPTABLE -CONFIG_DTT_SENSORS -CONFIG_DTT_TACH_LIMIT CONFIG_DUOVERO CONFIG_DV_USBPHY_CTL CONFIG_DWC2_DFLT_SPEED_FULL @@ -767,7 +708,6 @@ CONFIG_EDB93XX_SDCS2 CONFIG_EDB93XX_SDCS3 CONFIG_EEPRO100 CONFIG_EEPRO100_SROM_WRITE -CONFIG_EEPROM_LAYOUT_HELP_STRING CONFIG_EFLASH_PROTSECTORS CONFIG_EHCI_DESC_BIG_ENDIAN CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -949,7 +889,6 @@ CONFIG_FFUART CONFIG_FILE CONFIG_FIRMWARE_OFFSET CONFIG_FIRMWARE_SIZE -CONFIG_FIT_DISABLE_SHA256 CONFIG_FIXED_PHY CONFIG_FIXED_PHY_ADDR CONFIG_FIXED_SDHCI_ALIGNED_BUFFER @@ -1134,7 +1073,6 @@ CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_H264_FREQ CONFIG_H8300 CONFIG_HALEAKALA -CONFIG_HARD_I2C CONFIG_HARD_SPI CONFIG_HASH_VERIFY CONFIG_HAS_DATAFLASH @@ -1320,7 +1258,6 @@ CONFIG_HW_ENV_SETTINGS CONFIG_HW_WATCHDOG CONFIG_HW_WATCHDOG_TIMEOUT_MS CONFIG_I2C -CONFIG_I2CFAST CONFIG_I2C_CHIPADDRESS CONFIG_I2C_CMD_TREE CONFIG_I2C_ENV_EEPROM_BUS @@ -1637,7 +1574,6 @@ CONFIG_LUAN CONFIG_LWMON5 CONFIG_LXT971_NO_SLEEP CONFIG_LYNXKDI -CONFIG_LZMA CONFIG_M41T94_SPI_CS CONFIG_M520x CONFIG_M52277EVB @@ -1980,33 +1916,12 @@ CONFIG_OF_SPI CONFIG_OF_SPI_FLASH CONFIG_OF_STDOUT_PATH CONFIG_OF_SUPPORT_OLD_DEVICE_TREES -CONFIG_OMAP -CONFIG_OMAP3430 -CONFIG_OMAP3_AM3517CRANE -CONFIG_OMAP3_DEVKIT8000 -CONFIG_OMAP3_EVM -CONFIG_OMAP3_GPIO_2 -CONFIG_OMAP3_GPIO_3 -CONFIG_OMAP3_GPIO_4 -CONFIG_OMAP3_GPIO_5 -CONFIG_OMAP3_GPIO_6 -CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID -CONFIG_OMAP3_MCX -CONFIG_OMAP3_MICRON_DDR -CONFIG_OMAP3_RX51 -CONFIG_OMAP3_SPI_D0_D1_SWAPPED -CONFIG_OMAP3_ZOOM1 -CONFIG_OMAP4430 CONFIG_OMAP_EHCI_PHY1_RESET_GPIO CONFIG_OMAP_EHCI_PHY2_RESET_GPIO CONFIG_OMAP_EHCI_PHY3_RESET_GPIO -CONFIG_OMAP_GPIO -CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC CONFIG_OMAP_USB2PHY2_HOST CONFIG_OMAP_USB3PHY1_HOST CONFIG_OMAP_USB_PHY -CONFIG_OMAP_VC_I2C_HS_MCODE -CONFIG_OMAP_WATCHDOG CONFIG_OPTREX_BW CONFIG_ORIGEN CONFIG_OS1_ENV_ADDR @@ -2377,7 +2292,6 @@ CONFIG_RTC_MV CONFIG_RTC_MXS CONFIG_RTC_PCF8563 CONFIG_RTC_PT7C4338 -CONFIG_RTC_RTC4543 CONFIG_RTC_RV3029 CONFIG_RTC_RX8025 CONFIG_RTC_X1205 @@ -2396,6 +2310,7 @@ CONFIG_S3C24XX_TACLS CONFIG_S3C24XX_TWRPH0 CONFIG_S3C24XX_TWRPH1 CONFIG_S3D2_CLK_FREQ +CONFIG_S3D4_CLK_FREQ CONFIG_S5P CONFIG_S5PC100 CONFIG_S5PC110 @@ -2610,7 +2525,6 @@ CONFIG_SOFT_I2C_GPIO_SCL CONFIG_SOFT_I2C_GPIO_SDA CONFIG_SOFT_I2C_READ_REPEATED_START CONFIG_SOFT_SPI -CONFIG_SOFT_TWS CONFIG_SOURCE CONFIG_SPARSE_RCU_POINTER CONFIG_SPDDRAM_SILENT @@ -3483,12 +3397,6 @@ CONFIG_SYS_DSPI_CTAR4 CONFIG_SYS_DSPI_CTAR5 CONFIG_SYS_DSPI_CTAR6 CONFIG_SYS_DSPI_CTAR7 -CONFIG_SYS_DTT_ADM1021 -CONFIG_SYS_DTT_BUS_NUM -CONFIG_SYS_DTT_HYSTERESIS -CONFIG_SYS_DTT_LOW_TEMP -CONFIG_SYS_DTT_MAX_TEMP -CONFIG_SYS_DTT_MIN_TEMP CONFIG_SYS_DUART_RST CONFIG_SYS_DV_CLKMODE CONFIG_SYS_DV_NOR_BOOT_CFG @@ -3543,7 +3451,6 @@ CONFIG_SYS_EXTBDINFO CONFIG_SYS_EXTRA_ENV_RELOC CONFIG_SYS_EXT_SERIAL_CLOCK CONFIG_SYS_FAST_CLK -CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN CONFIG_SYS_FAULT_ECHO_LINK_DOWN CONFIG_SYS_FAULT_MII_ADDR CONFIG_SYS_FCC_PSMR @@ -4223,7 +4130,6 @@ CONFIG_SYS_I2C_BASE2 CONFIG_SYS_I2C_BASE3 CONFIG_SYS_I2C_BASE4 CONFIG_SYS_I2C_BASE5 -CONFIG_SYS_I2C_BOARD_LATE_INIT CONFIG_SYS_I2C_BOOT_EEPROM_ADDR CONFIG_SYS_I2C_BUSES CONFIG_SYS_I2C_BUS_MAX @@ -4231,13 +4137,10 @@ CONFIG_SYS_I2C_CLK_OFFSET CONFIG_SYS_I2C_DAVINCI CONFIG_SYS_I2C_DIRECT_BUS CONFIG_SYS_I2C_DPMEM_OFFSET -CONFIG_SYS_I2C_DS1621_ADDR -CONFIG_SYS_I2C_DS4510_ADDR CONFIG_SYS_I2C_DSPIC_2_ADDR CONFIG_SYS_I2C_DSPIC_ADDR CONFIG_SYS_I2C_DSPIC_IO_ADDR CONFIG_SYS_I2C_DSPIC_KEYB_ADDR -CONFIG_SYS_I2C_DTT_ADDR CONFIG_SYS_I2C_DVI_ADDR CONFIG_SYS_I2C_DVI_BUS_NUM CONFIG_SYS_I2C_EARLY_INIT @@ -6150,7 +6053,6 @@ CONFIG_TIZEN CONFIG_TI_KEYSTONE_SERDES CONFIG_TI_KSNAV CONFIG_TI_SPI_MMAP -CONFIG_TMU_CMD_DTT CONFIG_TMU_TIMER CONFIG_TOTAL5200 CONFIG_TPL_DRIVERS_MISC_SUPPORT @@ -6307,7 +6209,6 @@ CONFIG_USB_EHCI_KIRKWOOD CONFIG_USB_EHCI_MX5 CONFIG_USB_EHCI_MXC CONFIG_USB_EHCI_MXS -CONFIG_USB_EHCI_OMAP CONFIG_USB_EHCI_PCI CONFIG_USB_EHCI_PPC4XX CONFIG_USB_EHCI_RMOBILE diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py index 035dbf5cac..b7f960c755 100644 --- a/test/py/tests/test_env.py +++ b/test/py/tests/test_env.py @@ -164,6 +164,7 @@ def test_env_echo_exists(state_test_env): value = state_test_env.env[var] validate_set(state_test_env, var, value) +@pytest.mark.buildconfigspec('cmd_echo') def test_env_echo_non_existent(state_test_env): """Test echoing a variable that doesn't exist.""" @@ -179,6 +180,7 @@ def test_env_printenv_non_existent(state_test_env): response = c.run_command('printenv %s' % var) assert(response == '## Error: "%s" not defined' % var) +@pytest.mark.buildconfigspec('cmd_echo') def test_env_unset_non_existent(state_test_env): """Test unsetting a nonexistent variable.""" @@ -202,6 +204,7 @@ def test_env_set_existing(state_test_env): set_var(state_test_env, var, value) validate_set(state_test_env, var, value) +@pytest.mark.buildconfigspec('cmd_echo') def test_env_unset_existing(state_test_env): """Test unsetting a variable.""" diff --git a/test/py/tests/test_shell_basics.py b/test/py/tests/test_shell_basics.py index 702e5e27e0..0024d5f7f6 100644 --- a/test/py/tests/test_shell_basics.py +++ b/test/py/tests/test_shell_basics.py @@ -4,6 +4,10 @@ # Test basic shell functionality, such as commands separate by semi-colons. +import pytest + +pytestmark = pytest.mark.buildconfigspec('cmd_echo') + def test_shell_execute(u_boot_console): """Test any shell command.""" diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c index 0f0b003a83..db0f10ec29 100644 --- a/tools/mksunxiboot.c +++ b/tools/mksunxiboot.c @@ -48,8 +48,8 @@ int gen_check_sum(struct boot_file_head *head_p) #define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) #define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) -#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */ -#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head)) +#define SUNXI_SRAM_SIZE 0x8000 /* SoC with smaller size are limited before */ +#define SRAM_LOAD_MAX_SIZE (SUNXI_SRAM_SIZE - sizeof(struct boot_file_head)) /* * BROM (at least on A10 and A20) requires NAND-images to be explicitly aligned @@ -70,11 +70,40 @@ int main(int argc, char *argv[]) struct boot_img img; unsigned file_size; int count; + char *tool_name = argv[0]; + char *default_dt = NULL; - if (argc < 2) { - printf("\tThis program makes an input bin file to sun4i " \ - "bootable image.\n" \ - "\tUsage: %s input_file out_putfile\n", argv[0]); + /* a sanity check */ + if ((sizeof(img.header) % 32) != 0) { + fprintf(stderr, "ERROR: the SPL header must be a multiple "); + fprintf(stderr, "of 32 bytes.\n"); + return EXIT_FAILURE; + } + + /* process optional command line switches */ + while (argc >= 2 && argv[1][0] == '-') { + if (strcmp(argv[1], "--default-dt") == 0) { + if (argc >= 3) { + default_dt = argv[2]; + argv += 2; + argc -= 2; + continue; + } + fprintf(stderr, "ERROR: no --default-dt arg\n"); + return EXIT_FAILURE; + } else { + fprintf(stderr, "ERROR: bad option '%s'\n", argv[1]); + return EXIT_FAILURE; + } + } + + if (argc < 3) { + printf("This program converts an input binary file to a sunxi bootable image.\n"); + printf("\nUsage: %s [options] input_file output_file\n", + tool_name); + printf("Where [options] may be:\n"); + printf(" --default-dt arg - 'arg' is the default device tree name\n"); + printf(" (CONFIG_DEFAULT_DEVICE_TREE).\n"); return EXIT_FAILURE; } @@ -122,6 +151,18 @@ int main(int argc, char *argv[]) memcpy(img.header.spl_signature, SPL_SIGNATURE, 3); /* "sunxi" marker */ img.header.spl_signature[3] = SPL_HEADER_VERSION; + if (default_dt) { + if (strlen(default_dt) + 1 <= sizeof(img.header.string_pool)) { + strcpy((char *)img.header.string_pool, default_dt); + img.header.dt_name_offset = + cpu_to_le32(offsetof(struct boot_file_head, + string_pool)); + } else { + printf("WARNING: The SPL header is too small\n"); + printf(" and has no space to store the dt name.\n"); + } + } + gen_check_sum(&img.header); count = write(fd_out, &img, le32_to_cpu(img.header.length)); |