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-rw-r--r--Kconfig12
-rw-r--r--Makefile4
-rw-r--r--arch/Kconfig4
-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/cpu/armv8/zynqmp/Kconfig8
-rw-r--r--arch/arm/cpu/armv8/zynqmp/Makefile1
-rw-r--r--arch/arm/cpu/armv8/zynqmp/cpu.c28
-rw-r--r--arch/arm/cpu/armv8/zynqmp/psu_spl_init.c80
-rw-r--r--arch/arm/cpu/armv8/zynqmp/spl.c8
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/zynq-7000.dtsi3
-rw-r--r--arch/arm/dts/zynq-cc108.dts1
-rw-r--r--arch/arm/dts/zynq-topic-miami.dts1
l---------arch/arm/dts/zynq-zc770-xm011-x16.dts1
-rw-r--r--arch/arm/dts/zynqmp-mini-emmc.dts76
-rw-r--r--arch/arm/dts/zynqmp-mini-nand.dts109
-rw-r--r--arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h27
-rw-r--r--arch/arm/include/asm/arch-zynqmp/sys_proto.h2
-rw-r--r--arch/arm/mach-davinci/Kconfig84
-rw-r--r--arch/arm/mach-stm32/Kconfig1
-rw-r--r--arch/arm/mach-tegra/tegra20/crypto.c7
-rw-r--r--arch/arm/mach-zynq/ddrc.c2
-rw-r--r--arch/arm/mach-zynq/lowlevel_init.S2
-rw-r--r--arch/arm/mach-zynq/ps7_spl_init.c4
-rw-r--r--arch/arm/mach-zynq/slcr.c2
-rw-r--r--arch/arm/mach-zynq/spl.c2
-rw-r--r--arch/arm/mach-zynq/timer.c2
-rw-r--r--arch/m68k/include/asm/config.h2
-rw-r--r--arch/powerpc/include/asm/config.h2
-rw-r--r--arch/x86/cpu/quark/smc.c13
-rw-r--r--arch/x86/include/asm/acpi_table.h9
-rw-r--r--arch/x86/include/asm/arch-tangier/acpi/southcluster.asl2
-rw-r--r--arch/x86/include/asm/bootparam.h1
-rw-r--r--arch/x86/lib/acpi_table.c12
-rw-r--r--arch/x86/lib/zimage.c15
-rw-r--r--board/google/Kconfig1
-rw-r--r--board/xilinx/zynq/board.c1
-rw-r--r--board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c800
-rw-r--r--board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c782
-rw-r--r--board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c776
-rw-r--r--board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c818
-rw-r--r--board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c767
-rw-r--r--board/xilinx/zynqmp/xil_io.h12
-rw-r--r--board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c975
-rw-r--r--board/xilinx/zynqmp/zynqmp.c21
-rw-r--r--cmd/aes.c44
-rw-r--r--cmd/bdinfo.c2
-rw-r--r--common/spl/spl.c2
-rw-r--r--configs/am335x_baltos_defconfig1
-rw-r--r--configs/cm_t3517_defconfig1
-rw-r--r--configs/eco5pk_defconfig1
-rw-r--r--configs/kc1_defconfig1
-rw-r--r--configs/microblaze-generic_defconfig8
-rw-r--r--configs/mt_ventoux_defconfig1
-rw-r--r--configs/omapl138_lcdk_defconfig1
-rw-r--r--configs/sniper_defconfig1
-rw-r--r--configs/syzygy_hub_defconfig15
-rw-r--r--configs/topic_miami_defconfig7
-rw-r--r--configs/topic_miamilite_defconfig7
-rw-r--r--configs/topic_miamiplus_defconfig7
-rw-r--r--configs/twister_defconfig1
-rw-r--r--configs/xilinx_zynqmp_ep_defconfig5
-rw-r--r--configs/xilinx_zynqmp_mini_emmc_defconfig44
-rw-r--r--configs/xilinx_zynqmp_mini_nand_defconfig43
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig5
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig5
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig5
-rw-r--r--configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig5
-rw-r--r--configs/xilinx_zynqmp_zcu102_rev1_0_defconfig5
-rw-r--r--configs/xilinx_zynqmp_zcu102_revA_defconfig5
-rw-r--r--configs/xilinx_zynqmp_zcu102_revB_defconfig5
-rw-r--r--configs/zynq_cc108_defconfig15
-rw-r--r--configs/zynq_cse_qspi_defconfig2
-rw-r--r--configs/zynq_microzed_defconfig14
-rw-r--r--configs/zynq_picozed_defconfig14
-rw-r--r--configs/zynq_z_turn_defconfig14
-rw-r--r--configs/zynq_zc702_defconfig16
-rw-r--r--configs/zynq_zc706_defconfig16
-rw-r--r--configs/zynq_zc770_xm010_defconfig17
-rw-r--r--configs/zynq_zc770_xm011_defconfig21
-rw-r--r--configs/zynq_zc770_xm011_x16_defconfig44
-rw-r--r--configs/zynq_zc770_xm012_defconfig9
-rw-r--r--configs/zynq_zc770_xm013_defconfig9
-rw-r--r--configs/zynq_zed_defconfig15
-rw-r--r--configs/zynq_zybo_defconfig14
-rw-r--r--doc/README.zynq10
-rw-r--r--drivers/clk/clk_stm32f.c6
-rw-r--r--drivers/i2c/Kconfig14
-rw-r--r--drivers/misc/qfw.c8
-rw-r--r--drivers/mtd/nand/Kconfig1
-rw-r--r--drivers/mtd/nand/arasan_nfc.c186
-rw-r--r--drivers/net/mvpp2.c2
-rw-r--r--fs/btrfs/super.c4
-rw-r--r--include/configs/am3517_crane.h2
-rw-r--r--include/configs/am3517_evm.h2
-rw-r--r--include/configs/baltos.h2
-rw-r--r--include/configs/bur_am335x_common.h2
-rw-r--r--include/configs/calimain.h14
-rw-r--r--include/configs/cm_t35.h2
-rw-r--r--include/configs/cm_t3517.h2
-rw-r--r--include/configs/da850evm.h14
-rw-r--r--include/configs/ipam390.h14
-rw-r--r--include/configs/kc1.h2
-rw-r--r--include/configs/legoev3.h14
-rw-r--r--include/configs/mcx.h2
-rw-r--r--include/configs/microblaze-generic.h8
-rw-r--r--include/configs/nokia_rx51.h2
-rw-r--r--include/configs/omapl138_lcdk.h14
-rw-r--r--include/configs/siemens-am33x-common.h2
-rw-r--r--include/configs/sniper.h2
-rw-r--r--include/configs/stm32f746-disco.h1
-rw-r--r--include/configs/tam3517-common.h2
-rw-r--r--include/configs/tao3530.h2
-rw-r--r--include/configs/ti_armv7_omap.h2
-rw-r--r--include/configs/tricorder.h2
-rw-r--r--include/configs/x86-common.h2
-rw-r--r--include/configs/xilinx_zynqmp.h10
-rw-r--r--include/configs/xilinx_zynqmp_mini.h45
-rw-r--r--include/configs/xilinx_zynqmp_mini_emmc.h23
-rw-r--r--include/configs/xilinx_zynqmp_mini_nand.h24
-rw-r--r--include/configs/zynq-common.h6
-rw-r--r--include/configs/zynq_cse.h1
-rw-r--r--include/uboot_aes.h8
-rw-r--r--lib/aes.c13
-rw-r--r--scripts/config_whitelist.txt17
-rw-r--r--scripts/kconfig/mconf.c2
126 files changed, 6027 insertions, 401 deletions
diff --git a/Kconfig b/Kconfig
index 9b8a807799..f713c6a9b1 100644
--- a/Kconfig
+++ b/Kconfig
@@ -83,6 +83,18 @@ config DISTRO_DEFAULTS
Select this to enable various options and commands which are suitable
for building u-boot for booting general purpose Linux distributions.
+config SYS_BOOT_GET_CMDLINE
+ bool "Enable kernel command line setup"
+ help
+ Enables allocating and saving kernel cmdline in space between
+ "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
+config SYS_BOOT_GET_KBD
+ bool "Enable kernel board information setup"
+ help
+ Enables allocating and saving a kernel copy of the bd_info in
+ space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
+
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default y if DM
diff --git a/Makefile b/Makefile
index 7195219503..ab3453dceb 100644
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
#
VERSION = 2018
-PATCHLEVEL = 01
+PATCHLEVEL = 03
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
diff --git a/arch/Kconfig b/arch/Kconfig
index 762230cd56..5d57d6da2c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -26,6 +26,8 @@ config ARM
config M68K
bool "M68000 architecture"
select HAVE_PRIVATE_LIBGCC
+ select SYS_BOOT_GET_CMDLINE
+ select SYS_BOOT_GET_KBD
config MICROBLAZE
bool "MicroBlaze architecture"
@@ -53,6 +55,8 @@ config PPC
bool "PowerPC architecture"
select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL
+ select SYS_BOOT_GET_CMDLINE
+ select SYS_BOOT_GET_KBD
config RISCV
bool "riscv architecture"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a423aa9629..b730bcb9af 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -803,18 +803,16 @@ config ARCH_ZYNQ
select SPL_BOARD_INIT if SPL
select SPL_OF_CONTROL if SPL
select DM
- select DM_ETH
- select DM_GPIO
+ select DM_ETH if NET
select SPL_DM if SPL
- select DM_MMC
+ select DM_MMC if MMC
select DM_SPI
select DM_SERIAL
select DM_SPI_FLASH
select SPL_SEPARATE_BSS if SPL
select DM_USB if USB
- select BLK
select CLK
- select SPL_CLK
+ select SPL_CLK if SPL
select CLK_ZYNQ
imply CMD_CLK
imply FAT_WRITE
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 3f922b4097..9e521ed874 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -68,6 +68,12 @@ config PMUFW_INIT_FILE
config ZYNQMP_USB
bool "Configure ZynqMP USB"
+config ZYNQMP_NO_DDR
+ bool "Disable DDR MMU mapping"
+ help
+ This option configures MMU with no DDR to avoid speculative
+ access to DDR memory where DDR is not present.
+
config SYS_MALLOC_F_LEN
default 0x600
@@ -107,7 +113,7 @@ config SPL_ZYNQMP_ALT_BOOTMODE
choice
prompt "Boot mode"
depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
- default JTAG
+ default JTAG_MODE
config JTAG_MODE
bool "JTAG_MODE"
diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index 72dee3ded4..dde1a0f658 100644
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -9,3 +9,4 @@ obj-y += clk.o
obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
+obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index f026cb4511..bc77dd03c3 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -17,20 +17,24 @@
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region zynqmp_mem_map[] = {
+#if !defined(CONFIG_ZYNQMP_NO_DDR)
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
- }, {
+ },
+#endif
+ {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x70000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
+ },
+ {
.virt = 0xf8000000UL,
.phys = 0xf8000000UL,
.size = 0x07e00000UL,
@@ -48,20 +52,24 @@ static struct mm_region zynqmp_mem_map[] = {
#endif
.virt = 0x400000000UL,
.phys = 0x400000000UL,
- .size = 0x200000000UL,
+ .size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x600000000UL,
- .phys = 0x600000000UL,
+ },
+#if !defined(CONFIG_ZYNQMP_NO_DDR)
+ {
+ .virt = 0x800000000UL,
+ .phys = 0x800000000UL,
.size = 0x800000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xe00000000UL,
- .phys = 0xe00000000UL,
- .size = 0xf200000000UL,
+ },
+#endif
+ {
+ .virt = 0x1000000000UL,
+ .phys = 0x1000000000UL,
+ .size = 0xf000000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
diff --git a/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c b/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c
new file mode 100644
index 0000000000..28d39570b3
--- /dev/null
+++ b/arch/arm/cpu/armv8/zynqmp/psu_spl_init.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2018 Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/psu_init_gpl.h>
+
+#define PSU_MASK_POLL_TIME 1100000
+
+int __maybe_unused mask_pollonvalue(unsigned long add, u32 mask, u32 value)
+{
+ int i = 0;
+
+ while ((__raw_readl(add) & mask) != value) {
+ if (i == PSU_MASK_POLL_TIME)
+ return 0;
+ i++;
+ }
+ return 1;
+}
+
+__weak int mask_poll(u32 add, u32 mask)
+{
+ int i = 0;
+ unsigned long addr = add;
+
+ while (!(__raw_readl(addr) & mask)) {
+ if (i == PSU_MASK_POLL_TIME)
+ return 0;
+ i++;
+ }
+ return 1;
+}
+
+__weak u32 mask_read(u32 add, u32 mask)
+{
+ unsigned long addr = add;
+
+ return __raw_readl(addr) & mask;
+}
+
+__weak void mask_delay(u32 delay)
+{
+ udelay(delay);
+}
+
+__weak void psu_mask_write(unsigned long offset, unsigned long mask,
+ unsigned long val)
+{
+ unsigned long regval = 0;
+
+ regval = readl(offset);
+ regval &= ~(mask);
+ regval |= (val & mask);
+ writel(regval, offset);
+}
+
+__weak void prog_reg(unsigned long addr, unsigned long mask,
+ unsigned long shift, unsigned long value)
+{
+ int rdata = 0;
+
+ rdata = readl(addr);
+ rdata = rdata & (~mask);
+ rdata = rdata | (value << shift);
+ writel(rdata, addr);
+}
+
+__weak int psu_init(void)
+{
+ /*
+ * This function is overridden by the one in
+ * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+ */
+ return -1;
+}
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 41b0070a5e..bc7313a88b 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -129,14 +129,6 @@ u32 spl_boot_mode(const u32 boot_device)
}
}
-__weak void psu_init(void)
-{
- /*
- * This function is overridden by the one in
- * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
- */
-}
-
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index da0ae0d242..ebbc0ca51e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -147,6 +147,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zybo.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb \
+ zynqmp-mini-emmc.dtb \
+ zynqmp-mini-nand.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zcu102-rev1.0.dtb \
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index d9774d85d1..7ef102ad05 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -50,7 +50,8 @@
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&intc>;
- reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+ reg = <0xf8891000 0x1000>,
+ <0xf8893000 0x1000>;
};
regulator_vccpint: fixedregulator {
diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts
index a55e82b210..4804da5235 100644
--- a/arch/arm/dts/zynq-cc108.dts
+++ b/arch/arm/dts/zynq-cc108.dts
@@ -100,6 +100,7 @@
};
&uart0 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts
index 79a3671a8e..bf421f6653 100644
--- a/arch/arm/dts/zynq-topic-miami.dts
+++ b/arch/arm/dts/zynq-topic-miami.dts
@@ -13,7 +13,6 @@
compatible = "topic,miami", "xlnx,zynq-7000";
aliases {
- ethernet0 = &gem0;
serial0 = &uart0;
spi0 = &qspi;
i2c0 = &i2c0;
diff --git a/arch/arm/dts/zynq-zc770-xm011-x16.dts b/arch/arm/dts/zynq-zc770-xm011-x16.dts
new file mode 120000
index 0000000000..5bd6af39a4
--- /dev/null
+++ b/arch/arm/dts/zynq-zc770-xm011-x16.dts
@@ -0,0 +1 @@
+zynq-zc770-xm011.dts \ No newline at end of file
diff --git a/arch/arm/dts/zynqmp-mini-emmc.dts b/arch/arm/dts/zynqmp-mini-emmc.dts
new file mode 100644
index 0000000000..e65934046b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-emmc.dts
@@ -0,0 +1,76 @@
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI EMMC";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &dcc;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sdhci0: sdhci@ff160000 {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ xlnx,device_id = <0>;
+ };
+
+ sdhci1: sdhci@ff170000 {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ xlnx,device_id = <1>;
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
new file mode 100644
index 0000000000..16e5f55ebc
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -0,0 +1,109 @@
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI NAND";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &dcc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x40000000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ nand0: nand@ff100000 {
+ compatible = "arasan,nfc-v3p10";
+ status = "okay";
+ reg = <0x0 0xff100000 0x1000>;
+ clock-names = "clk_sys", "clk_flash";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ arasan,has-mdma;
+ num-cs = <2>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x0 0x400000>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x0 0x400000 0x1400000>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x0 0x1800000 0x400000>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x0 0x1C00000 0x1400000>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x0 0x3000000 0x400000>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand-misc";
+ reg = <0x0 0x3400000 0xFCC00000>;
+ };
+ partition@6 { /* for testing purpose */
+ label = "nand1-fsbl-uboot";
+ reg = <0x1 0x0 0x400000>;
+ };
+ partition@7 { /* for testing purpose */
+ label = "nand1-linux";
+ reg = <0x1 0x400000 0x1400000>;
+ };
+ partition@8 { /* for testing purpose */
+ label = "nand1-device-tree";
+ reg = <0x1 0x1800000 0x400000>;
+ };
+ partition@9 { /* for testing purpose */
+ label = "nand1-rootfs";
+ reg = <0x1 0x1C00000 0x1400000>;
+ };
+ partition@10 { /* for testing purpose */
+ label = "nand1-bitstream";
+ reg = <0x1 0x3000000 0x400000>;
+ };
+ partition@11 { /* for testing purpose */
+ label = "nand1-misc";
+ reg = <0x1 0x3400000 0xFCC00000>;
+ };
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h b/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h
new file mode 100644
index 0000000000..1f7d4f7659
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h
@@ -0,0 +1,27 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PSU_INIT_GPL_H_ /* prevent circular inclusions */
+#define _PSU_INIT_GPL_H_
+
+#include <asm/io.h>
+#include <common.h>
+
+int mask_pollonvalue(unsigned long add, u32 mask, u32 value);
+
+int mask_poll(u32 add, u32 mask);
+
+u32 mask_read(u32 add, u32 mask);
+
+void mask_delay(u32 delay);
+
+void psu_mask_write(unsigned long offset, unsigned long mask,
+ unsigned long val);
+
+void prog_reg(unsigned long addr, unsigned long mask,
+ unsigned long shift, unsigned long value);
+
+int psu_init(void);
+
+#endif /* _PSU_INIT_GPL_H_ */
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index ad28568633..084d55a2b0 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -33,8 +33,6 @@ enum {
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
-void psu_init(void);
-
void handoff_setup(void);
void zynqmp_pmufw_version(void);
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 51a70e0571..30752839a3 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -54,7 +54,6 @@ config SYS_DA850_DDR_INIT
config SOC_DA850
bool
select SOC_DA8XX
- select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
config SOC_DA8XX
bool
@@ -63,6 +62,89 @@ config SOC_DA8XX
config MACH_DAVINCI_DA850_EVM
bool
+if SYS_DA850_PLL_INIT
+comment "DA850 PLL Initialization Parameters"
+
+config SYS_DV_CLKMODE
+ int "PLLCTL Clock Mode"
+ default 0
+ help
+ Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
+
+config SYS_DA850_PLL0_POSTDIV
+ int "PLLC0 PLL Post-Divider"
+ default 1
+ help
+ Value written to PLLC0 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL0_PLLDIV1
+ hex "PLLC0 Divider 1"
+ default 0x8000
+ help
+ Value written to PLLC0 Divider 1 register
+
+config SYS_DA850_PLL0_PLLDIV2
+ hex "PLLC0 Divider 2"
+ default 0x8001
+ help
+ Value written to PLLC0 Divider 2 register
+
+config SYS_DA850_PLL0_PLLDIV3
+ hex "PLLC0 Divider 3"
+ default 0x8002
+ help
+ Value written to PLLC0 Divider 3 register
+
+config SYS_DA850_PLL0_PLLDIV4
+ hex "PLLC0 Divider 4"
+ default 0x8003
+ help
+ Value written to PLLC0 Divider 4 register
+
+config SYS_DA850_PLL0_PLLDIV5
+ hex "PLLC0 Divider 5"
+ default 0x8002
+ help
+ Value written to PLLC0 Divider 5 register
+
+config SYS_DA850_PLL0_PLLDIV6
+ hex "PLLC0 Divider 6"
+ default 0x8000
+ help
+ Value written to PLLC0 Divider 6 register
+
+config SYS_DA850_PLL0_PLLDIV7
+ hex "PLLC0 Divider 7"
+ default 0x8005
+ help
+ Value written to PLLC0 Divider 7 register
+
+config SYS_DA850_PLL1_POSTDIV
+ hex "PLLC1 PLL Post-Divider"
+ default 1
+ help
+ Value written to PLLC1 PLL Post-Divider Control Register
+
+config SYS_DA850_PLL1_PLLDIV1
+ hex "PLLC1 Divider 2"
+ default 0x8000
+ help
+ Value written to PLLC1 Divider 1 register
+
+config SYS_DA850_PLL1_PLLDIV2
+ hex "PLLC1 Divider 2"
+ default 0x8001
+ help
+ Value written to PLLC1 Divider 2 register
+
+config SYS_DA850_PLL1_PLLDIV3
+ hex "PLLC1 Divider 3"
+ default 0x8002
+ help
+ Value written to PLLC1 Divider 3 register
+
+endif
+
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/ea20/Kconfig"
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 5f7a2b5669..f79b1a2c70 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -29,6 +29,7 @@ config STM32F7
select STM32_SERIAL
select SUPPORT_SPL
select SPL
+ select SPL_BOARD_INIT
select SPL_CLK
select SPL_DM
select SPL_DM_SEQ_ALIAS
diff --git a/arch/arm/mach-tegra/tegra20/crypto.c b/arch/arm/mach-tegra/tegra20/crypto.c
index eae79217d4..58d6662f6d 100644
--- a/arch/arm/mach-tegra/tegra20/crypto.c
+++ b/arch/arm/mach-tegra/tegra20/crypto.c
@@ -50,6 +50,7 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
u32 num_aes_blocks)
{
u8 tmp_data[AES_KEY_LENGTH];
+ u8 iv[AES_KEY_LENGTH] = {0};
u8 left[AES_KEY_LENGTH];
u8 k1[AES_KEY_LENGTH];
u8 *cbc_chain_data;
@@ -61,7 +62,7 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
for (i = 0; i < AES_KEY_LENGTH; i++)
tmp_data[i] = 0;
- aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1);
+ aes_cbc_encrypt_blocks(key_schedule, iv, tmp_data, left, 1);
left_shift_vector(left, k1, sizeof(left));
@@ -102,6 +103,7 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
{
u32 num_aes_blocks;
u8 key_schedule[AES_EXPAND_KEY_LENGTH];
+ u8 iv[AES_KEY_LENGTH] = {0};
debug("encrypt_and_sign: length = %d\n", length);
@@ -116,7 +118,8 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
if (oper & SECURITY_ENCRYPT) {
/* Perform this in place, resulting in src being encrypted. */
debug("encrypt_and_sign: begin encryption\n");
- aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks);
+ aes_cbc_encrypt_blocks(key_schedule, iv, src, src,
+ num_aes_blocks);
debug("encrypt_and_sign: end encryption\n");
}
diff --git a/arch/arm/mach-zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c
index bde52d6562..047a7b4d9c 100644
--- a/arch/arm/mach-zynq/ddrc.c
+++ b/arch/arm/mach-zynq/ddrc.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
- * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved.
+ * Copyright (C) 2012 - 2017 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/mach-zynq/lowlevel_init.S b/arch/arm/mach-zynq/lowlevel_init.S
index 6d714b711c..e5ec9bea55 100644
--- a/arch/arm/mach-zynq/lowlevel_init.S
+++ b/arch/arm/mach-zynq/lowlevel_init.S
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
+ * Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c
index 6dc4e0364d..ba2dad759c 100644
--- a/arch/arm/mach-zynq/ps7_spl_init.c
+++ b/arch/arm/mach-zynq/ps7_spl_init.c
@@ -58,7 +58,7 @@ static void perf_start_clock(void)
}
/* Compute mask for given delay in miliseconds*/
-static int get_number_of_cycles_for_delay(unsigned int delay)
+static unsigned long get_number_of_cycles_for_delay(unsigned long delay)
{
return (APU_FREQ / (2 * 1000)) * delay;
}
@@ -92,7 +92,7 @@ int __weak ps7_config(unsigned long *ps7_config_init)
unsigned long mask;
unsigned int numargs;
int i;
- int delay;
+ unsigned long delay;
for (;;) {
opcode = ptr[0];
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index ba453a7024..0b263fac58 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013 Xilinx Inc.
+ * Copyright (c) 2013 - 2017 Xilinx Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 1672fa05c2..b7e6d98f08 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index b1bb3b80e1..493d608a5b 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -3,7 +3,7 @@
* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
*
* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
- * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
+ * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved.
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
index 9c4d3fb8fd..fd0b5513ee 100644
--- a/arch/m68k/include/asm/config.h
+++ b/arch/m68k/include/asm/config.h
@@ -11,7 +11,5 @@
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#define CONFIG_SYS_BOOT_GET_CMDLINE
-#define CONFIG_SYS_BOOT_GET_KBD
#endif
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 6aec815c71..67e4b48a96 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -31,8 +31,6 @@
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-#define CONFIG_SYS_BOOT_GET_CMDLINE
-#define CONFIG_SYS_BOOT_GET_KBD
#ifndef CONFIG_MAX_MEM_MAPPED
#if defined(CONFIG_E500) || \
diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c
index 3ffe92b67b..0195b56a52 100644
--- a/arch/x86/cpu/quark/smc.c
+++ b/arch/x86/cpu/quark/smc.c
@@ -17,15 +17,6 @@
#include "hte.h"
#include "smc.h"
-/* t_rfc values (in picoseconds) per density */
-static const uint32_t t_rfc[5] = {
- 90000, /* 512Mb */
- 110000, /* 1Gb */
- 160000, /* 2Gb */
- 300000, /* 4Gb */
- 350000, /* 8Gb */
-};
-
/* t_ck clock period in picoseconds per speed index 800, 1066, 1333 */
static const uint32_t t_ck[3] = {
2500,
@@ -35,8 +26,12 @@ static const uint32_t t_ck[3] = {
/* Global variables */
static const uint16_t ddr_wclk[] = {193, 158};
+#ifdef BACKUP_WCTL
static const uint16_t ddr_wctl[] = {1, 217};
+#endif
+#ifdef BACKUP_WCMD
static const uint16_t ddr_wcmd[] = {1, 220};
+#endif
#ifdef BACKUP_RCVN
static const uint16_t ddr_rcvn[] = {129, 498};
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 80038504dd..d5d77cc011 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -330,6 +330,15 @@ void enter_acpi_mode(int pm1_cnt);
ulong write_acpi_tables(ulong start);
/**
+ * acpi_get_rsdp_addr() - get ACPI RSDP table address
+ *
+ * This routine returns the ACPI RSDP table address in the system memory.
+ *
+ * @return: ACPI RSDP table address
+ */
+ulong acpi_get_rsdp_addr(void);
+
+/**
* acpi_find_fadt() - find ACPI FADT table in the sytem memory
*
* This routine parses the ACPI table to locate the ACPI FADT table.
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index 2b3b897c5b..5289b14957 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -284,7 +284,7 @@ Device (PCI0)
Return (STA_VISIBLE)
}
- Method (_CRS, 0, NotSerialized)
+ Method (_CRS, 0, Serialized)
{
Name (RBUF, ResourceTemplate ()
{
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index 48b138c6b0..90768a99ce 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -66,6 +66,7 @@ struct setup_header {
__u64 pref_address;
__u32 init_size;
__u32 handover_offset;
+ __u64 acpi_rsdp_addr;
} __attribute__((packed));
struct sys_desc_table {
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 3eb101105b..0d448cffc9 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -27,6 +27,9 @@
*/
extern const unsigned char AmlCode[];
+/* ACPI RSDP address to be used in boot parameters */
+static ulong acpi_rsdp_addr;
+
static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
struct acpi_xsdt *xsdt)
{
@@ -357,8 +360,7 @@ void enter_acpi_mode(int pm1_cnt)
}
/*
- * QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/acpi_table.c
+ * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c
*/
ulong write_acpi_tables(ulong start)
{
@@ -461,6 +463,7 @@ ulong write_acpi_tables(ulong start)
debug("current = %x\n", current);
+ acpi_rsdp_addr = (unsigned long)rsdp;
debug("ACPI: done\n");
/* Don't touch ACPI hardware on HW reduced platforms */
@@ -476,6 +479,11 @@ ulong write_acpi_tables(ulong start)
return current;
}
+ulong acpi_get_rsdp_addr(void)
+{
+ return acpi_rsdp_addr;
+}
+
static struct acpi_rsdp *acpi_valid_rsdp(struct acpi_rsdp *rsdp)
{
if (strncmp((char *)rsdp, RSDP_SIG, sizeof(RSDP_SIG) - 1) != 0)
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 00172dc7c1..2a82bc83d6 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -14,6 +14,7 @@
*/
#include <common.h>
+#include <asm/acpi_table.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/zimage.h>
@@ -246,14 +247,20 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
hdr->setup_move_size = 0x9100;
}
-#if defined(CONFIG_INTEL_MID)
- hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
-#endif
-
/* build command line at COMMAND_LINE_OFFSET */
build_command_line(cmd_line, auto_boot);
}
+#ifdef CONFIG_INTEL_MID
+ if (bootproto >= 0x0207)
+ hdr->hardware_subarch = X86_SUBARCH_INTEL_MID;
+#endif
+
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+ if (bootproto >= 0x020e)
+ hdr->acpi_rsdp_addr = acpi_get_rsdp_addr();
+#endif
+
setup_video(&setup_base->screen_info);
return 0;
diff --git a/board/google/Kconfig b/board/google/Kconfig
index e56c026ef6..766db1b449 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -31,7 +31,6 @@ config TARGET_CHROMEBOOK_LINK64
config TARGET_CHROMEBOX_PANTHER
bool "Chromebox panther (not available)"
- select n
help
Note: At present this must be used with coreboot. See README.x86
for instructions.
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index e59038106a..fb8eab07d7 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 - 2018 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
new file mode 100644
index 0000000000..3dd3785e49
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c
@@ -0,0 +1,800 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B00, 0x00000071U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B00, 0x00000303U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01ED844DU),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B00, 0x00000303U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000012A0U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003F01U, 0x00000201U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00002902U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000903U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000305U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000304U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000380U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000221U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000220U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000002E0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000002E1U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000240U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000240U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000280U),
+ EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ }
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
new file mode 100644
index 0000000000..f7ca84e58d
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c
@@ -0,0 +1,782 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+ EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+ EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+ EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+ EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001611U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001605U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001604U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+ EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000001U),
+ EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ }
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
new file mode 100644
index 0000000000..245bef356b
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c
@@ -0,0 +1,776 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+ EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+ EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600701U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016D400DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00000610U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00000611U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x000006E1U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00000621U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00000620U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001660U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001661U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000705U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000704U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U),
+ EMIT_MASKWRITE(0xE000E018, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E010, 0x03E00000U, 0x02400000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ }
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
new file mode 100644
index 0000000000..4471e1b46f
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c
@@ -0,0 +1,818 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+ EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+ EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+ EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+ EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+ EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+ EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+ EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+ EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000A01U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001402U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000602U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00100102U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x004C0000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x016E800DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003902DU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00032022U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003341CU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00036438U),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ADU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009CU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x000000B8U),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000139U),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x0000011DU),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x00000122U),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x0000012EU),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000EDU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DCU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000F8U),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000260U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000608U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000640U),
+ EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001608U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001640U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001620U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001621U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x000016A0U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001600U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000016E0U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000016E1U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U),
+ EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU),
+ EMIT_MASKWRITE(0xE000E010, 0x03EFFFFFU, 0x000000F0U),
+ EMIT_MASKWRITE(0xE2000000, 0x0000FFFFU, 0x000000F0U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKWRITE(0xE000A204, 0xFFFFFFFFU, 0x00000001U),
+ EMIT_MASKWRITE(0xE000A000, 0xFFFFFFFFU, 0xFFFE0000U),
+ EMIT_MASKWRITE(0xE000A208, 0xFFFFFFFFU, 0x00000001U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ }
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
new file mode 100644
index 0000000000..7827daad9a
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c
@@ -0,0 +1,767 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/ps7_init_gpl.h>
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x27087290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+ EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_2_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_pll_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+ EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+ EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
+ EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+ EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+ EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
+ EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000001U),
+ EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100801U),
+ EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
+ EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00001401U),
+ EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+ EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00600702U),
+ EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000401U),
+ EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00400500U),
+ EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+ EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01DE408DU),
+ EMIT_MASKWRITE(0xF8000304, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+ EMIT_MASKWRITE(0xF8006004, 0x1FFFFFFFU, 0x00081081U),
+ EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+ EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+ EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+ EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159BU),
+ EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E438D2U),
+ EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+ EMIT_MASKWRITE(0xF8006020, 0xFFFFFFFCU, 0x27287290U),
+ EMIT_MASKWRITE(0xF8006024, 0x0FFFFFFFU, 0x0000003CU),
+ EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+ EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+ EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+ EMIT_MASKWRITE(0xF8006038, 0x00001FC3U, 0x00000000U),
+ EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+ EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+ EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+ EMIT_MASKWRITE(0xF8006048, 0x3FFFFFFFU, 0x0003C248U),
+ EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+ EMIT_MASKWRITE(0xF8006058, 0x0001FFFFU, 0x00000101U),
+ EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+ EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+ EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+ EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+ EMIT_MASKWRITE(0xF80060A0, 0x00FFFFFFU, 0x00008000U),
+ EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+ EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+ EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+ EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+ EMIT_MASKWRITE(0xF80060B4, 0x000007FFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+ EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+ EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006118, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800611C, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006120, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF8006124, 0x7FFFFFFFU, 0x40000001U),
+ EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00039C1BU),
+ EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00037C35U),
+ EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0003942FU),
+ EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00038C1FU),
+ EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+ EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009BU),
+ EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B5U),
+ EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x000000AFU),
+ EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009FU),
+ EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x0000013CU),
+ EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000134U),
+ EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000013AU),
+ EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000138U),
+ EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DBU),
+ EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F5U),
+ EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000EFU),
+ EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DFU),
+ EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x10040080U),
+ EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+ EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8006208, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF800620C, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006210, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006214, 0x000F03FFU, 0x000803FFU),
+ EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+ EMIT_MASKWRITE(0xF80062A8, 0x00000FF7U, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+ EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+ EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+ EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+ EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+ EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+ EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+ EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+ EMIT_MASKWRITE(0xF8000B6C, 0x000073FFU, 0x00000209U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000021U),
+ EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+ EMIT_MASKWRITE(0xF8000B70, 0x07FFFFFFU, 0x00000823U),
+ EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001602U),
+ EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
+ EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x000006E1U),
+ EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x000006E0U),
+ EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x000007A0U),
+ EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00000702U),
+ EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00000703U),
+ EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00000720U),
+ EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00000721U),
+ EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x000007C0U),
+ EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x000007C1U),
+ EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00000740U),
+ EMIT_MASKWRITE(0xF80007B8, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007BC, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000661U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000660U),
+ EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x000006A0U),
+ EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x000006A0U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
+ EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU),
+ EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
+ EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U),
+ EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
+ EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_MASKDELAY(0xF8F00200, 1),
+ EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_1_0[] = {
+ EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+ EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+ EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+ EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+ EMIT_EXIT(),
+};
+
+static unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+static unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+static unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+static unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+static unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int ps7_post_config(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret = -1;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ret = ps7_config(ps7_post_config_1_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ret = ps7_config(ps7_post_config_2_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ } else {
+ ret = ps7_config(ps7_post_config_3_0);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ }
+ return PS7_INIT_SUCCESS;
+}
+
+int ps7_init(void)
+{
+ unsigned long si_ver = ps7GetSiliconVersion();
+ int ret;
+
+ if (si_ver == PCW_SILICON_VERSION_1) {
+ ps7_mio_init_data = ps7_mio_init_data_1_0;
+ ps7_pll_init_data = ps7_pll_init_data_1_0;
+ ps7_clock_init_data = ps7_clock_init_data_1_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+
+ } else if (si_ver == PCW_SILICON_VERSION_2) {
+ ps7_mio_init_data = ps7_mio_init_data_2_0;
+ ps7_pll_init_data = ps7_pll_init_data_2_0;
+ ps7_clock_init_data = ps7_clock_init_data_2_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+
+ } else {
+ ps7_mio_init_data = ps7_mio_init_data_3_0;
+ ps7_pll_init_data = ps7_pll_init_data_3_0;
+ ps7_clock_init_data = ps7_clock_init_data_3_0;
+ ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+ ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+ }
+
+ ret = ps7_config(ps7_mio_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_pll_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_clock_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_ddr_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+
+ ret = ps7_config(ps7_peripherals_init_data);
+ if (ret != PS7_INIT_SUCCESS)
+ return ret;
+ return PS7_INIT_SUCCESS;
+}
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index 679d234b07..0e4f81064c 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -11,18 +11,6 @@
#define xil_printf(...)
-void Xil_ICacheEnable(void)
-{}
-
-void Xil_DCacheEnable(void)
-{}
-
-void Xil_ICacheDisable(void)
-{}
-
-void Xil_DCacheDisable(void)
-{}
-
void Xil_Out32(unsigned long addr, unsigned long val)
{
writel(val, addr);
diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
new file mode 100644
index 0000000000..758eed6eb7
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c
@@ -0,0 +1,975 @@
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015900U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x80008E69U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015900U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x80008E69U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+ psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000600U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
+ psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+ psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
+ psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85610U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41980B06U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28210008U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F09U);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+ psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
+
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U);
+ psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U);
+ psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U);
+ psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x5DB80000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U);
+ psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+ mask_delay(1);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U);
+ mask_delay(5);
+ psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U);
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U);
+ psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U);
+ psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U);
+ psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
+ psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
+ psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
+ psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
+ psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U);
+ psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
+ psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
+ psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
+ psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U);
+ psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
+ psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U);
+ psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
+ psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
+ psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
+ psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U);
+ psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000400U, 0x00000400U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU);
+ psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU);
+ psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU);
+ psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U);
+ psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U);
+ psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U);
+ psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U);
+ psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U);
+ psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU);
+ psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U);
+ psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U);
+ psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U);
+ psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U);
+ psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U);
+ psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U);
+ psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U);
+ psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U);
+ psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U);
+ psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U);
+ psu_mask_write(0xFD480094, 0x00004200U, 0x00004200U);
+ psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U);
+ psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED021U);
+ psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U);
+ psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U);
+ psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U);
+ psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U);
+ psu_mask_write(0xFD48013C, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U);
+ psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U);
+ psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U);
+ psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U);
+ psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U);
+ psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+ mask_poll(0xFD40A3E4, 0x00000010U);
+ mask_poll(0xFD40E3E4, 0x00000010U);
+ psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
+ psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
+ psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+ psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U);
+ psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+ psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+ psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ prog_reg(0xFD070010U, 0x00000008U, 0x00000003U, 0x00000001U);
+ prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+ prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000819U);
+ prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+ while ((Xil_In32(0xFD070018) & 0x1) == 1)
+ ;
+ prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+ prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000899U);
+ prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+ while ((Xil_In32(0xFD070018) & 0x1) == 1)
+ ;
+ prog_reg(0xFD070010U, 0x00000030U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD070010U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD070010U, 0x0000F000U, 0x0000000CU, 0x00000006U);
+ prog_reg(0xFD070014U, 0x0003FFFFU, 0x00000000U, 0x00000819U);
+ prog_reg(0xFD070010U, 0x80000000U, 0x0000001FU, 0x00000001U);
+ while ((Xil_In32(0xFD070018) & 0x1) == 1)
+ ;
+ prog_reg(0xFD070010U, 0x00000008U, 0x00000003U, 0x00000000U);
+ Xil_Out32(0xFD0701B0U, 0x00000001U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0004FE01);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80000FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x100091C7U);
+ Xil_Out32(0xFD080018U, 0x00F01EF2U);
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ Xil_Out32(0xFD080018U, 0x00F12302U);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD070180U, 0x01000040U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0;
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ /* xil_printf("#SERDES initialization timed out\n\r");*/
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+
+ if ((p_code >= 0x26) && (p_code <= 0x3C))
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if ((n_code >= 0x26) && (n_code <= 0x3C))
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if ((i_code >= 0xC) && (i_code <= 0x12))
+ match_ical_code[i_code - 0xC] += 1;
+
+ if ((r_code >= 0x6) && (r_code <= 0xC))
+ match_rcal_code[r_code - 0x6] += 1;
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 8)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 8) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 8) | 0x40
+ | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 8) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ unsigned int tmp_regval;
+
+ tmp_regval = Xil_In32(0xFD690040);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690040, tmp_regval);
+
+ tmp_regval = Xil_In32(0xFD690030);
+ tmp_regval &= ~0x00000001;
+ Xil_Out32(0xFD690030, tmp_regval);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index c198a4d920..ff0b3c75f5 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -13,6 +13,7 @@
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/psu_init_gpl.h>
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>
@@ -237,15 +238,16 @@ static char *zynqmp_get_silicon_idcode_name(void)
int board_early_init_f(void)
{
+ int ret = 0;
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
zynqmp_pmufw_version();
#endif
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
- psu_init();
+#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
+ ret = psu_init();
#endif
- return 0;
+ return ret;
}
#define ZYNQMP_VERSION_SIZE 9
@@ -346,6 +348,7 @@ int board_late_init(void)
u8 bootmode;
const char *mode;
char *new_targets;
+ char *env_targets;
int ret;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
@@ -418,10 +421,16 @@ int board_late_init(void)
* One terminating char + one byte for space between mode
* and default boot_targets
*/
- new_targets = calloc(1, strlen(mode) +
- strlen(env_get("boot_targets")) + 2);
+ env_targets = env_get("boot_targets");
+ if (env_targets) {
+ new_targets = calloc(1, strlen(mode) +
+ strlen(env_targets) + 2);
+ sprintf(new_targets, "%s %s", mode, env_targets);
+ } else {
+ new_targets = calloc(1, strlen(mode) + 2);
+ sprintf(new_targets, "%s", mode);
+ }
- sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
env_set("boot_targets", new_targets);
return 0;
diff --git a/cmd/aes.c b/cmd/aes.c
index ee1ae13c06..9d1a740bee 100644
--- a/cmd/aes.c
+++ b/cmd/aes.c
@@ -28,13 +28,13 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static int do_aes(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- uint32_t key_addr, src_addr, dst_addr, len;
- uint8_t *key_ptr, *src_ptr, *dst_ptr;
+ uint32_t key_addr, iv_addr, src_addr, dst_addr, len;
+ uint8_t *key_ptr, *iv_ptr, *src_ptr, *dst_ptr;
uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
uint32_t aes_blocks;
int enc;
- if (argc != 6)
+ if (argc != 7)
return CMD_RET_USAGE;
if (!strncmp(argv[1], "enc", 3))
@@ -45,11 +45,13 @@ static int do_aes(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
return CMD_RET_USAGE;
key_addr = simple_strtoul(argv[2], NULL, 16);
- src_addr = simple_strtoul(argv[3], NULL, 16);
- dst_addr = simple_strtoul(argv[4], NULL, 16);
- len = simple_strtoul(argv[5], NULL, 16);
+ iv_addr = simple_strtoul(argv[3], NULL, 16);
+ src_addr = simple_strtoul(argv[4], NULL, 16);
+ dst_addr = simple_strtoul(argv[5], NULL, 16);
+ len = simple_strtoul(argv[6], NULL, 16);
key_ptr = (uint8_t *)key_addr;
+ iv_ptr = (uint8_t *)iv_addr;
src_ptr = (uint8_t *)src_addr;
dst_ptr = (uint8_t *)dst_addr;
@@ -60,9 +62,11 @@ static int do_aes(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
if (enc)
- aes_cbc_encrypt_blocks(key_exp, src_ptr, dst_ptr, aes_blocks);
+ aes_cbc_encrypt_blocks(key_exp, iv_ptr, src_ptr, dst_ptr,
+ aes_blocks);
else
- aes_cbc_decrypt_blocks(key_exp, src_ptr, dst_ptr, aes_blocks);
+ aes_cbc_decrypt_blocks(key_exp, iv_ptr, src_ptr, dst_ptr,
+ aes_blocks);
return 0;
}
@@ -70,20 +74,22 @@ static int do_aes(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
/***************************************************/
#ifdef CONFIG_SYS_LONGHELP
static char aes_help_text[] =
- "enc key src dst len - Encrypt block of data $len bytes long\n"
- " at address $src using a key at address\n"
- " $key and store the result at address\n"
- " $dst. The $len size must be multiple of\n"
- " 16 bytes and $key must be 16 bytes long.\n"
- "aes dec key src dst len - Decrypt block of data $len bytes long\n"
- " at address $src using a key at address\n"
- " $key and store the result at address\n"
- " $dst. The $len size must be multiple of\n"
- " 16 bytes and $key must be 16 bytes long.";
+ "enc key iv src dst len - Encrypt block of data $len bytes long\n"
+ " at address $src using a key at address\n"
+ " $key with initialization vector at address\n"
+ " $iv. Store the result at address $dst.\n"
+ " The $len size must be multiple of 16 bytes.\n"
+ " The $key and $iv must be 16 bytes long.\n"
+ "aes dec key iv src dst len - Decrypt block of data $len bytes long\n"
+ " at address $src using a key at address\n"
+ " $key with initialization vector at address\n"
+ " $iv. Store the result at address $dst.\n"
+ " The $len size must be multiple of 16 bytes.\n"
+ " The $key and $iv must be 16 bytes long.";
#endif
U_BOOT_CMD(
- aes, 6, 1, do_aes,
+ aes, 7, 1, do_aes,
"AES 128 CBC encryption",
aes_help_text
);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index c7ebad17d1..de6fc48987 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -377,6 +377,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
print_bi_dram(bd);
+ print_num("relocaddr", gd->relocaddr);
+ print_num("reloc off", gd->reloc_off);
#if defined(CONFIG_CMD_NET)
print_eth_ip_addr();
print_mhz("ethspeed", bd->bi_ethspeed);
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 2ebab8f0c2..b1ce56d0d0 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -479,7 +479,7 @@ void preloader_console_init(void)
#ifndef CONFIG_SPL_DISABLE_BANNER_PRINT
puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
- U_BOOT_TIME ")\n");
+ U_BOOT_TIME " " U_BOOT_TZ ")\n");
#endif
#ifdef CONFIG_SPL_DISPLAY_PRINT
spl_display_print();
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 548e045e92..97e600138c 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -47,6 +47,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
+CONFIG_SYS_OMAP24_I2C_SPEED=1000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_PHYLIB=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index fa78bde0bb..c1e1153a7c 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -31,6 +31,7 @@ CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),256k(u-boot-env),4m(kernel),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index c5b5c9b927..c371020079 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -26,6 +26,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader-nand),1024k(uboot-nand),256k(params-nand),5120k(kernel),-(ubifs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index e828405156..b4a5ce610b 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -34,6 +34,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index cc80e8a027..ca68a81a5b 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -43,8 +43,16 @@ CONFIG_OF_EMBED=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM=y
CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_PHY_DAVICOM=y
+CONFIG_PHY_LXT=y
+CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_XILINX_EMACLITE=y
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index 3dd8adb5ce..d7e54441b5 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -31,6 +31,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 944be2b56e..a693fbaad7 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_OMAPL138_LCDK=y
+CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index a3bae56cda..84ba175f6a 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -35,6 +35,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 8bdc4be67d..c4c1e93812 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -6,16 +6,16 @@ CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
@@ -28,20 +28,17 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index aabd705da0..1e1a3ddb49 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -7,11 +7,12 @@ CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
@@ -25,13 +26,11 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 7228283b3c..1e51bc5c87 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -7,11 +7,12 @@ CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
@@ -25,13 +26,11 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index d511a94283..7dd07c7e48 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -7,11 +7,12 @@ CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
@@ -23,13 +24,11 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_EMBED=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 03db9df150..f49c234ac8 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -31,6 +31,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_OMAP24_I2C_SPEED=400000
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index 1fc0fabd92..ce8bc0b0ec 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -69,6 +69,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_mini_emmc_defconfig b/configs/xilinx_zynqmp_mini_emmc_defconfig
new file mode 100644
index 0000000000..5d854d9b8b
--- /dev/null
+++ b/configs/xilinx_zynqmp_mini_emmc_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
new file mode 100644
index 0000000000..d6e2eb8a16
--- /dev/null
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_MMC is not set
+CONFIG_NAND=y
+CONFIG_NAND_ARASAN=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index 6914767187..814ff3805f 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -62,6 +62,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 67a6d9ae9b..67e659640d 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -58,6 +58,11 @@ CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SST=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index 15b301dca1..9bc0b77c2c 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -50,6 +50,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index ac565ecf8f..01a0ac0d76 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -43,6 +43,11 @@ CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xff000000
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index c761d4948f..075508993e 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -64,6 +64,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 43b533fdb9..404b15c54a 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -64,6 +64,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index c2d0ddbcf9..dbdda089b8 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -64,6 +64,11 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index bdba0d1cc9..5082208b9c 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -4,15 +4,15 @@ CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@@ -21,18 +21,12 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
@@ -41,6 +35,9 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0000000
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 9659faefbf..d4baeaa0c5 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -48,8 +48,6 @@ CONFIG_OF_EMBED=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_SPL_BLK is not set
-# CONFIG_ZYNQ_GPIO is not set
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index fc21eb8f67..c1762b07c2 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -3,14 +3,15 @@ CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
@@ -25,21 +26,15 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
@@ -47,6 +42,9 @@ CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index f36e7bd849..0c7006a5e9 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -3,11 +3,12 @@ CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
@@ -21,22 +22,19 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_USB=y
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index c727b2acbf..c315b917dc 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -4,14 +4,15 @@ CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
@@ -22,20 +23,14 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
@@ -43,6 +38,9 @@ CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 0d0efc223d..5fadf5074e 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -2,19 +2,20 @@ CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC702"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
@@ -30,21 +31,15 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
@@ -53,6 +48,9 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 4b186c9fff..f024147f2f 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -2,19 +2,20 @@ CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC706"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
@@ -30,21 +31,15 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
@@ -53,6 +48,9 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 897ca91e56..125f97d004 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,20 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010"
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
@@ -25,19 +25,13 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
@@ -47,6 +41,9 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 2b8a12ee69..80fb3d9c0d 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,13 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011"
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
+CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
@@ -23,16 +26,20 @@ CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_ZYNQ=y
-CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_REGEX=y
+CONFIG_LIB_RAND=y
diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
new file mode 100644
index 0000000000..d53f223be4
--- /dev/null
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM011 x16"
+CONFIG_SPL_STACK_R_ADDR=0x200000
+# CONFIG_SPL_FAT_SUPPORT is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011-x16"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Zynq> "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_DM_MMC=y
+CONFIG_NAND=y
+CONFIG_NAND_ZYNQ=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xe0001000
+CONFIG_DEBUG_UART_CLOCK=50000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_REGEX=y
+CONFIG_LIB_RAND=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index d53fe94db3..09ae04be34 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,13 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM012"
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
@@ -30,8 +32,13 @@ CONFIG_CMD_CACHE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SERIAL=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index e6445f735c..36922ffcd4 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,13 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
@@ -29,7 +31,9 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_BLK=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
@@ -37,6 +41,9 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index c18f056deb..a1403a34ef 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -3,16 +3,16 @@ CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
-CONFIG_CMD_BOOTZ=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
@@ -26,21 +26,15 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
@@ -48,6 +42,9 @@ CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SERIAL=y
CONFIG_ZYNQ_QSPI=y
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 21f8c08fd8..50b28d8518 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -5,14 +5,15 @@ CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
@@ -29,26 +30,23 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
+CONFIG_DM_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
CONFIG_ZYNQ_GEM=y
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_DEBUG_UART_BASE=0xe0001000
diff --git a/doc/README.zynq b/doc/README.zynq
index b89c39edac..cc5c0de217 100644
--- a/doc/README.zynq
+++ b/doc/README.zynq
@@ -57,23 +57,21 @@ bootmode strings at runtime.
- Added basic board configurations support.
- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
-- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013
+- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013
- Added zynq drivers:
serial - drivers/serial/serial_zynq.c
net - drivers/net/zynq_gem.c
mmc - drivers/mmc/zynq_sdhci.c
- mmc - drivers/mmc/zynq_sdhci.c
- spi- drivers/spi/zynq_spi.c
+ spi - drivers/spi/zynq_spi.c
+ qspi - drivers/spi/zynq_qspi.c
i2c - drivers/i2c/zynq_i2c.c
+ nand - drivers/mtd/nand/zynq_nand.c
- Done proper cleanups on board configurations
- Added basic FDT support for zynq boards
- d-cache support for zynq_gem.c
6. TODO
-- Add zynq boards support - zc770_xm011
-- Add zynq qspi controller driver
-- Add zynq nand controller driver
- Add FDT support on individual drivers
[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 06827fec75..926b249ff3 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -337,6 +337,11 @@ static unsigned long stm32_clk_get_rate(struct clk *clk)
}
}
+static ulong stm32_set_rate(struct clk *clk, ulong rate)
+{
+ return 0;
+}
+
static int stm32_clk_enable(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);
@@ -464,6 +469,7 @@ static struct clk_ops stm32_clk_ops = {
.of_xlate = stm32_clk_of_xlate,
.enable = stm32_clk_enable,
.get_rate = stm32_clk_get_rate,
+ .set_rate = stm32_set_rate,
};
U_BOOT_DRIVER(stm32fx_clk) = {
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 0630712e4a..17d21bbc42 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -162,6 +162,20 @@ config SYS_I2C_OMAP24XX
help
Add support for the OMAP2+ I2C driver.
+if SYS_I2C_OMAP24XX
+config SYS_OMAP24_I2C_SLAVE
+ int "I2C Slave addr channel 0"
+ default 1
+ help
+ OMAP24xx I2C Slave address channel 0
+
+config SYS_OMAP24_I2C_SPEED
+ int "I2C Slave channel 0 speed"
+ default 100000
+ help
+ OMAP24xx Slave speed channel 0
+endif
+
config SYS_I2C_RCAR_IIC
bool "Renesas RCar Gen3 IIC driver"
depends on RCAR_GEN3 && DM_I2C
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
index a8af9e0c53..9a5480349e 100644
--- a/drivers/misc/qfw.c
+++ b/drivers/misc/qfw.c
@@ -222,6 +222,14 @@ out:
free(table_loader);
return addr;
}
+
+ulong acpi_get_rsdp_addr(void)
+{
+ struct fw_file *file;
+
+ file = qemu_fwcfg_find_file("etc/acpi/rsdp");
+ return file->addr;
+}
#endif
/* Read configuration item using fw_cfg PIO interface */
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 78a39abf75..97ec6cf5f9 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -123,6 +123,7 @@ endif
config NAND_ARASAN
bool "Configure Arasan Nand"
+ select SYS_NAND_SELF_INIT
imply CMD_NAND
help
This enables Nand driver support for Arasan nand flash
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 14b27337b6..3c9a0215c5 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -21,6 +21,7 @@
struct arasan_nand_info {
void __iomem *nand_base;
u32 page;
+ bool on_die_ecc_enabled;
};
struct nand_regs {
@@ -64,6 +65,7 @@ struct arasan_nand_command_format {
};
#define ONDIE_ECC_FEATURE_ADDR 0x90
+#define ENABLE_ONDIE_ECC 0x08
#define ARASAN_PROG_RD_MASK 0x00000001
#define ARASAN_PROG_BLK_ERS_MASK 0x00000004
@@ -206,6 +208,51 @@ static const struct arasan_ecc_matrix ecc_matrix[] = {
{16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
};
+static struct nand_ecclayout ondie_nand_oob_64 = {
+ .eccbytes = 32,
+
+ .eccpos = {
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 56, 57, 58, 59, 60, 61, 62, 63
+ },
+
+ .oobfree = {
+ { .offset = 4, .length = 4 },
+ { .offset = 20, .length = 4 },
+ { .offset = 36, .length = 4 },
+ { .offset = 52, .length = 4 }
+ }
+};
+
+/*
+ * bbt decriptors for chips with on-die ECC and
+ * chips with 64-byte OOB
+ */
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 4,
+ .len = 4,
+ .veroffs = 20,
+ .maxblocks = 4,
+ .pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+ .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+ NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+ .offs = 4,
+ .len = 4,
+ .veroffs = 20,
+ .maxblocks = 4,
+ .pattern = mirror_pattern
+};
+
static u8 buf_data[READ_BUFF_SIZE];
static u32 buf_index;
@@ -265,6 +312,7 @@ static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
{
struct nand_chip *chip = mtd_to_nand(mtd);
+ struct arasan_nand_info *nand = nand_get_controller_data(chip);
u32 reg_val, i, pktsize, pktnum;
u32 *bufptr = (u32 *)buf;
u32 timeout;
@@ -293,15 +341,17 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
pktsize;
writel(reg_val, &arasan_nand_base->pkt_reg);
- arasan_nand_enable_ecc();
- addr_cycles = arasan_nand_get_addrcycle(mtd);
- if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
- return ERR_ADDR_CYCLE;
+ if (!nand->on_die_ecc_enabled) {
+ arasan_nand_enable_ecc();
+ addr_cycles = arasan_nand_get_addrcycle(mtd);
+ if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
+ return ERR_ADDR_CYCLE;
- writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
- NAND_CMD_RNDOUT | (addr_cycles <<
- ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
- &arasan_nand_base->ecc_sprcmd_reg);
+ writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
+ NAND_CMD_RNDOUT | (addr_cycles <<
+ ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
+ &arasan_nand_base->ecc_sprcmd_reg);
+ }
writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
while (rdcount < pktnum) {
@@ -363,17 +413,19 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
&arasan_nand_base->intsts_reg);
- if (readl(&arasan_nand_base->intsts_reg) &
- ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
- printf("arasan rd_page:sbiterror\n");
- return -1;
- }
+ if (!nand->on_die_ecc_enabled) {
+ if (readl(&arasan_nand_base->intsts_reg) &
+ ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
+ printf("arasan rd_page:sbiterror\n");
+ return -1;
+ }
- if (readl(&arasan_nand_base->intsts_reg) &
- ARASAN_NAND_INT_STS_ERR_EN_MASK) {
- mtd->ecc_stats.failed++;
- printf("arasan rd_page:multibiterror\n");
- return -1;
+ if (readl(&arasan_nand_base->intsts_reg) &
+ ARASAN_NAND_INT_STS_ERR_EN_MASK) {
+ mtd->ecc_stats.failed++;
+ printf("arasan rd_page:multibiterror\n");
+ return -1;
+ }
}
return 0;
@@ -460,12 +512,14 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
writel(reg_val, &arasan_nand_base->pkt_reg);
- arasan_nand_enable_ecc();
- column_addr_cycles = (chip->onfi_params.addr_cycles &
- ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
- ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
- writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
- &arasan_nand_base->ecc_sprcmd_reg);
+ if (!nand->on_die_ecc_enabled) {
+ arasan_nand_enable_ecc();
+ column_addr_cycles = (chip->onfi_params.addr_cycles &
+ ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
+ ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
+ writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
+ &arasan_nand_base->ecc_sprcmd_reg);
+ }
writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
while (rdcount < pktnum) {
@@ -1032,19 +1086,56 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1);
}
+static void arasan_check_ondie(struct mtd_info *mtd)
+{
+ struct nand_chip *nand_chip = mtd_to_nand(mtd);
+ struct arasan_nand_info *nand = nand_get_controller_data(nand_chip);
+ u8 maf_id, dev_id;
+ u8 get_feature[4];
+ u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
+ u32 i;
+
+ /* Send the command for reading device ID */
+ nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
+
+ /* Read manufacturer and device IDs */
+ maf_id = nand_chip->read_byte(mtd);
+ dev_id = nand_chip->read_byte(mtd);
+
+ if ((maf_id == NAND_MFR_MICRON) &&
+ ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) ||
+ (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) ||
+ (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) ||
+ (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) ||
+ (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) {
+ nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
+ ONDIE_ECC_FEATURE_ADDR, -1);
+
+ nand_chip->write_buf(mtd, &set_feature[0], 4);
+ nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
+ ONDIE_ECC_FEATURE_ADDR, -1);
+
+ for (i = 0; i < 4; i++)
+ get_feature[i] = nand_chip->read_byte(mtd);
+
+ if (get_feature[0] & ENABLE_ONDIE_ECC)
+ nand->on_die_ecc_enabled = true;
+ else
+ printf("%s: Unable to enable OnDie ECC\n", __func__);
+
+ /* Use the BBT pattern descriptors */
+ nand_chip->bbt_td = &bbt_main_descr;
+ nand_chip->bbt_md = &bbt_mirror_descr;
+ }
+}
+
static int arasan_nand_ecc_init(struct mtd_info *mtd)
{
int found = -1;
- u32 regval, eccpos_start, i;
+ u32 regval, eccpos_start, i, eccaddr;
struct nand_chip *nand_chip = mtd_to_nand(mtd);
- nand_chip->ecc.mode = NAND_ECC_HW;
- nand_chip->ecc.hwctl = NULL;
- nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
- nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
- nand_chip->ecc.read_oob = arasan_nand_read_oob;
- nand_chip->ecc.write_oob = arasan_nand_write_oob;
-
for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
if ((ecc_matrix[i].pagesize == mtd->writesize) &&
(ecc_matrix[i].ecc_codeword_size >=
@@ -1061,7 +1152,10 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
if (found < 0)
return 1;
- regval = ecc_matrix[found].eccaddr |
+ eccaddr = mtd->writesize + mtd->oobsize -
+ ecc_matrix[found].eccsize;
+
+ regval = eccaddr |
(ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
(ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
writel(regval, &arasan_nand_base->ecc_reg);
@@ -1126,9 +1220,29 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
goto fail;
}
- if (arasan_nand_ecc_init(mtd)) {
- printf("%s: nand_ecc_init failed\n", __func__);
- goto fail;
+ nand_chip->ecc.mode = NAND_ECC_HW;
+ nand_chip->ecc.hwctl = NULL;
+ nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
+ nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
+ nand_chip->ecc.read_oob = arasan_nand_read_oob;
+ nand_chip->ecc.write_oob = arasan_nand_write_oob;
+
+ arasan_check_ondie(mtd);
+
+ /*
+ * If on die supported, then give priority to on-die ecc and use
+ * it instead of controller ecc.
+ */
+ if (nand->on_die_ecc_enabled) {
+ nand_chip->ecc.strength = 1;
+ nand_chip->ecc.size = mtd->writesize;
+ nand_chip->ecc.bytes = 0;
+ nand_chip->ecc.layout = &ondie_nand_oob_64;
+ } else {
+ if (arasan_nand_ecc_init(mtd)) {
+ printf("%s: nand_ecc_init failed\n", __func__);
+ goto fail;
+ }
}
if (nand_scan_tail(mtd)) {
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 233c98b66c..e3d31a560d 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4722,7 +4722,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
- u64 mdio_addr;
+ phys_addr_t mdio_addr;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 2529c2b3b6..7e2528c4fb 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -147,8 +147,8 @@ static int btrfs_check_super(struct btrfs_super_block *sb)
if (sb->sys_chunk_array_size < sizeof(struct btrfs_key) +
sizeof(struct btrfs_chunk)) {
- printf("%s: system chunk array too small %u < %lu\n", __func__,
- sb->sys_chunk_array_size, (u32) sizeof(struct btrfs_key)
+ printf("%s: system chunk array too small %u < %zu\n", __func__,
+ sb->sys_chunk_array_size, sizeof(struct btrfs_key)
+ sizeof(struct btrfs_chunk));
ret = -1;
}
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 16212ef9fb..35e7f9df58 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -97,8 +97,6 @@
#endif /* CONFIG_USB_AM35X */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* Board NAND Info.
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index ac5070d8cf..4d94078d1c 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -56,8 +56,6 @@
#endif /* CONFIG_USB_MUSB_AM35X */
/* I2C */
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* Ethernet */
#define CONFIG_DRIVER_TI_EMAC
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 939ee3b4ad..75dd0c5e26 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -39,8 +39,6 @@
#define CONFIG_MTD_DEVICE
/* I2C configuration */
-#undef CONFIG_SYS_OMAP24_I2C_SPEED
-#define CONFIG_SYS_OMAP24_I2C_SPEED 1000
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00080000
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 15c481d421..ca0440ecfe 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -70,8 +70,6 @@
/* I2C */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* Our platforms make use of SPL to initalize the hardware (primarily
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 7dfc1fa1ec..4c2f6ba2d5 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -39,20 +39,6 @@
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM \
((calimain_get_osc_freq() == 25000000) ? 23 : 24)
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 3c64cb575c..deb26fbaff 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -80,8 +80,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index fe8b39a65b..12fa1861a2 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -89,8 +89,6 @@
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 2a6916b92e..4fbfc72bdb 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -74,20 +74,6 @@
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 21
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 618bf72da3..a6fa4585f3 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -56,20 +56,6 @@
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 24
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 94c3d0ad29..1d1f2dbb22 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -58,8 +58,6 @@
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
/*
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 3439cbe090..b60498a538 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -52,20 +52,6 @@
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 21
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index f0ab990e14..552b51704c 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -79,8 +79,6 @@
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* RTC */
#define CONFIG_RTC_DS1337
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 41e6790d68..16481cb7ce 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -212,14 +212,6 @@
#if defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII 1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
-# define CONFIG_PHY_ATHEROS 1
-# define CONFIG_PHY_BROADCOM 1
-# define CONFIG_PHY_DAVICOM 1
-# define CONFIG_PHY_LXT 1
-# define CONFIG_PHY_MARVELL 1
-# define CONFIG_PHY_NATSEMI 1
-# define CONFIG_PHY_REALTEK 1
-# define CONFIG_PHY_VITESSE 1
#else
# undef CONFIG_MII
#endif
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 00509e8508..6312ed737c 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -95,8 +95,6 @@
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* TWL4030
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 2cb99119a1..c9b42a8c3c 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -58,20 +58,6 @@
/*
* PLL configuration
*/
-#define CONFIG_SYS_DV_CLKMODE 0
-#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
-#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
-#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
-#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
-
-#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
-#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
-#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
-#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003
#define CONFIG_SYS_DA850_PLL0_PLLM 37
#define CONFIG_SYS_DA850_PLL1_PLLM 21
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 85b64123a0..44c85cd7fa 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -97,8 +97,6 @@
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 0ed72cf901..1966a72f6b 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -59,8 +59,6 @@
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
/*
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 301ab0f8f2..3e952c2acd 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -72,7 +72,6 @@
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_SPL_LEN 0x00008000
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 7f05cb07ca..f266c39485 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -67,8 +67,6 @@
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 0e9fe68175..eb89e56151 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -63,8 +63,6 @@
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
/*
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index da5fc8108f..80d4476cf0 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -13,8 +13,6 @@
#define __CONFIG_TI_ARMV7_OMAP_H__
/* I2C IP block */
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/*
* GPMC NAND block. We support 1 device and the physical address to
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index f892a5712c..0298b56353 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -58,8 +58,6 @@
/* I2C */
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* EEPROM */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 994214ea48..e8f680f129 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -62,8 +62,10 @@
* Command line configuration.
*/
+#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 9997fd0959..858649db51 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -76,11 +76,14 @@
#ifdef CONFIG_NAND_ARASAN
# define CONFIG_SYS_MAX_NAND_DEVICE 1
-# define CONFIG_SYS_NAND_SELF_INIT
# define CONFIG_SYS_NAND_ONFI_DETECTION
# define CONFIG_MTD_DEVICE
#endif
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_ZYNQMP_PSU_INIT_ENABLED
+#endif
+
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR 0x8000000
@@ -133,11 +136,6 @@
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_PHY_MARVELL
-# define CONFIG_PHY_NATSEMI
-# define CONFIG_PHY_TI
-# define CONFIG_PHY_VITESSE
-# define CONFIG_PHY_REALTEK
# define PHY_ANEG_TIMEOUT 20000
#endif
diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h
new file mode 100644
index 0000000000..268d7b7d52
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_mini.h
@@ -0,0 +1,45 @@
+/*
+ * Configuration for Xilinx ZynqMP Flash utility
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_H
+#define __CONFIG_ZYNQMP_MINI_H
+
+#include <configs/xilinx_zynqmp.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#undef CONFIG_CMD_ENV
+#undef CONFIG_MP
+#undef CONFIG_SYS_INIT_SP_ADDR
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_MTD_DEVICE
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_VXWORKS
+#undef CONFIG_BOOTM_LINUX
+#undef CONFIG_BOARD_LATE_INIT
+
+/* BOOTP options */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+#undef CONFIG_BOOTP_MAY_FAIL
+#undef CONFIG_BOOTP_PXE
+#undef CONFIG_CMD_UNZIP
+
+#undef CONFIG_NR_DRAM_BANKS
+
+#endif /* __CONFIG_ZYNQMP_MINI_H */
diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h
new file mode 100644
index 0000000000..6f56cf61a6
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_mini_emmc.h
@@ -0,0 +1,23 @@
+/*
+ * Configuration for Xilinx ZynqMP eMMC Flash utility
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_EMMC_H
+#define __CONFIG_ZYNQMP_MINI_EMMC_H
+
+#include <configs/xilinx_zynqmp_mini.h>
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN 0x800000
+#define CONFIG_SYS_LONGHELP
+
+#endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */
diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h
new file mode 100644
index 0000000000..8c13f4742d
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_mini_nand.h
@@ -0,0 +1,24 @@
+/*
+ * Configuration for Xilinx ZynqMP Nand Flash utility
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_NAND_H
+#define __CONFIG_ZYNQMP_MINI_NAND_H
+
+#include <configs/xilinx_zynqmp_mini.h>
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_SIZE 0x1000000
+#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
+#define CONFIG_SYS_MALLOC_LEN 0x800000
+
+#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 28cee15b37..d341042073 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
- * (C) Copyright 2013 Xilinx, Inc.
+ * (C) Copyright 2013 - 2018 Xilinx, Inc.
*
* Common configuration options for all Zynq boards.
*
@@ -38,9 +38,6 @@
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_PHY_MARVELL
-# define CONFIG_PHY_REALTEK
-# define CONFIG_PHY_XILINX
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_HOSTNAME
@@ -160,7 +157,6 @@
#define CONFIG_PREBOOT
/* Boot configuration */
-#define CONFIG_BOOTCOMMAND "run $modeboot || run distro_bootcmd"
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
/* Distro boot enablement */
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
index dd65b52343..f0f19a67bf 100644
--- a/include/configs/zynq_cse.h
+++ b/include/configs/zynq_cse.h
@@ -19,7 +19,6 @@
/* Undef unneeded configs */
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_BOARD_LATE_INIT
-#undef CONFIG_BOOTCOMMAND
#undef CONFIG_ENV_SIZE
#undef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
diff --git a/include/uboot_aes.h b/include/uboot_aes.h
index 6315c02aa9..b651bca1c9 100644
--- a/include/uboot_aes.h
+++ b/include/uboot_aes.h
@@ -75,20 +75,24 @@ void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst);
* aes_cbc_encrypt_blocks() - Encrypt multiple blocks of data with AES CBC.
*
* @key_exp Expanded key to use
+ * @iv Initialization vector
* @src Source data to encrypt
* @dst Destination buffer
* @num_aes_blocks Number of AES blocks to encrypt
*/
-void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks);
/**
* Decrypt multiple blocks of data with AES CBC.
*
* @key_exp Expanded key to use
+ * @iv Initialization vector
* @src Source data to decrypt
* @dst Destination buffer
* @num_aes_blocks Number of AES blocks to decrypt
*/
-void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks);
#endif /* _AES_REF_H_ */
diff --git a/lib/aes.c b/lib/aes.c
index d6144e61d6..2b0849c7e0 100644
--- a/lib/aes.c
+++ b/lib/aes.c
@@ -601,12 +601,11 @@ void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst)
*dst++ = *src++ ^ *cbc_chain_data++;
}
-void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks)
+void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
{
- u8 zero_key[AES_KEY_LENGTH] = { 0 };
u8 tmp_data[AES_KEY_LENGTH];
- /* Convenient array of 0's for IV */
- u8 *cbc_chain_data = zero_key;
+ u8 *cbc_chain_data = iv;
u32 i;
for (i = 0; i < num_aes_blocks; i++) {
@@ -628,13 +627,15 @@ void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks)
}
}
-void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks)
+void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+ u32 num_aes_blocks)
{
u8 tmp_data[AES_KEY_LENGTH], tmp_block[AES_KEY_LENGTH];
/* Convenient array of 0's for IV */
- u8 cbc_chain_data[AES_KEY_LENGTH] = { 0 };
+ u8 cbc_chain_data[AES_KEY_LENGTH];
u32 i;
+ memcpy(cbc_chain_data, iv, AES_KEY_LENGTH);
for (i = 0; i < num_aes_blocks; i++) {
debug("encrypt_object: block %d of %d\n", i, num_aes_blocks);
debug_print_vector("AES Src", AES_KEY_LENGTH, src);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index efcb251e44..ef83c00c1b 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2250,8 +2250,6 @@ CONFIG_SYS_BOOTM_LEN
CONFIG_SYS_BOOTPARAMS_LEN
CONFIG_SYS_BOOTSZ
CONFIG_SYS_BOOT_BLOCK
-CONFIG_SYS_BOOT_GET_CMDLINE
-CONFIG_SYS_BOOT_GET_KBD
CONFIG_SYS_BOOT_RAMDISK_HIGH
CONFIG_SYS_BR0_64M
CONFIG_SYS_BR0_8M
@@ -2440,21 +2438,9 @@ CONFIG_SYS_DA850_DDR2_SDBCR2
CONFIG_SYS_DA850_DDR2_SDRCR
CONFIG_SYS_DA850_DDR2_SDTIMR
CONFIG_SYS_DA850_DDR2_SDTIMR2
-CONFIG_SYS_DA850_PLL0_PLLDIV1
-CONFIG_SYS_DA850_PLL0_PLLDIV2
-CONFIG_SYS_DA850_PLL0_PLLDIV3
-CONFIG_SYS_DA850_PLL0_PLLDIV4
-CONFIG_SYS_DA850_PLL0_PLLDIV5
-CONFIG_SYS_DA850_PLL0_PLLDIV6
-CONFIG_SYS_DA850_PLL0_PLLDIV7
CONFIG_SYS_DA850_PLL0_PLLM
-CONFIG_SYS_DA850_PLL0_POSTDIV
CONFIG_SYS_DA850_PLL0_PREDIV
-CONFIG_SYS_DA850_PLL1_PLLDIV1
-CONFIG_SYS_DA850_PLL1_PLLDIV2
-CONFIG_SYS_DA850_PLL1_PLLDIV3
CONFIG_SYS_DA850_PLL1_PLLM
-CONFIG_SYS_DA850_PLL1_POSTDIV
CONFIG_SYS_DA850_SYSCFG_SUSPSRC
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
CONFIG_SYS_DAVINCI_I2C_SLAVE
@@ -2697,7 +2683,6 @@ CONFIG_SYS_DSPI_CTAR4
CONFIG_SYS_DSPI_CTAR5
CONFIG_SYS_DSPI_CTAR6
CONFIG_SYS_DSPI_CTAR7
-CONFIG_SYS_DV_CLKMODE
CONFIG_SYS_DV_NOR_BOOT_CFG
CONFIG_SYS_EBI_CFGR_VAL
CONFIG_SYS_EBI_CSA_VAL
@@ -3896,12 +3881,10 @@ CONFIG_SYS_NVRAM_SIZE
CONFIG_SYS_OBIR
CONFIG_SYS_OHCI_BE_CONTROLLER
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-CONFIG_SYS_OMAP24_I2C_SLAVE
CONFIG_SYS_OMAP24_I2C_SLAVE1
CONFIG_SYS_OMAP24_I2C_SLAVE2
CONFIG_SYS_OMAP24_I2C_SLAVE3
CONFIG_SYS_OMAP24_I2C_SLAVE4
-CONFIG_SYS_OMAP24_I2C_SPEED
CONFIG_SYS_OMAP24_I2C_SPEED1
CONFIG_SYS_OMAP24_I2C_SPEED2
CONFIG_SYS_OMAP24_I2C_SPEED3
diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c
index 953d5c75e5..315ce2c7cb 100644
--- a/scripts/kconfig/mconf.c
+++ b/scripts/kconfig/mconf.c
@@ -379,7 +379,7 @@ static void update_text(char *buf, size_t start, size_t end, void *_data)
data->targets[k] = pos->target;
k++;
} else {
- strcpy(header, " ");
+ sprintf(header, " ");
}
memcpy(buf + pos->offset, header, sizeof(header) - 1);