diff options
| -rw-r--r-- | arch/arm/cpu/arm1136/mx31/generic.c | 30 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx31/imx-regs.h | 25 |
2 files changed, 53 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index fa07fec60d..9b7a7a24c1 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -106,11 +106,37 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +struct mx3_cpu_type mx31_cpu_type[] = { + { .srev = 0x00, .v = "1.0" }, + { .srev = 0x10, .v = "1.1" }, + { .srev = 0x11, .v = "1.1" }, + { .srev = 0x12, .v = "1.15" }, + { .srev = 0x13, .v = "1.15" }, + { .srev = 0x14, .v = "1.2" }, + { .srev = 0x15, .v = "1.2" }, + { .srev = 0x28, .v = "2.0" }, + { .srev = 0x29, .v = "2.0" }, +}; + +char *get_cpu_rev(void) +{ + u32 i, srev; + + /* read SREV register from IIM module */ + struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR; + srev = readl(&iim->iim_srev); + + for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) + if (srev == mx31_cpu_type[i].srev) + return mx31_cpu_type[i].v; + return "unknown"; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { - printf("CPU: Freescale i.MX31 at %d MHz\n", - mx31_get_mcu_main_clk() / 1000000); + printf("CPU: Freescale i.MX31 rev %s at %d MHz\n", + get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000); return 0; } #endif diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 37337f2877..0eeaf39ab2 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -84,6 +84,29 @@ struct wdog_regs { u16 wrsr; /* Reset Status */ }; +/* IIM Control Registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; +}; + +struct mx3_cpu_type { + u8 srev; + const char *v; +}; #define IOMUX_PADNUM_MASK 0x1ff #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) @@ -480,6 +503,8 @@ enum iomux_pins { #define CCMR_FPM (1 << 1) #define CCMR_CKIH (2 << 1) +#define MX31_IIM_BASE_ADDR 0x5001C000 + #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) |