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-rw-r--r--arch/mips/dts/pic32mzda.dtsi56
-rw-r--r--arch/mips/dts/pic32mzda_sk.dts1
-rw-r--r--arch/mips/dts/vocore_vocore2.dts2
-rw-r--r--configs/pic32mzdask_defconfig1
-rw-r--r--configs/vocore2_defconfig2
-rw-r--r--drivers/mmc/pic32_sdhci.c86
-rw-r--r--drivers/pinctrl/pinctrl_pic32.c28
-rw-r--r--include/configs/vocore2.h4
8 files changed, 117 insertions, 63 deletions
diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 4c8b7a9a0b..43cd7cf304 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -26,8 +26,13 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
compatible = "mips,mips14kc";
+ device-type = "cpu";
+ reg = <0>;
};
};
@@ -40,6 +45,7 @@
uart1: serial@1f822000 {
compatible = "microchip,pic32mzda-uart";
reg = <0x1f822000 0x50>;
+ interrupt-parent = <&evic>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clock PB2CLK>;
@@ -48,6 +54,7 @@
uart2: serial@1f822200 {
compatible = "microchip,pic32mzda-uart";
reg = <0x1f822200 0x50>;
+ interrupt-parent = <&evic>;
interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock PB2CLK>;
status = "disabled";
@@ -56,6 +63,7 @@
uart6: serial@1f822a00 {
compatible = "microchip,pic32mzda-uart";
reg = <0x1f822a00 0x50>;
+ interrupt-parent = <&evic>;
interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock PB2CLK>;
status = "disabled";
@@ -69,6 +77,8 @@
};
pinctrl: pinctrl@1f801400 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x100>, /* in */
<0x1f801500 0x200>, /* out */
@@ -76,75 +86,72 @@
reg-names = "ppsin","ppsout","port";
status = "disabled";
- ranges = <0 0x1f860000 0xa00>;
- #address-cells = <1>;
- #size-cells = <1>;
- gpioA: gpio0@0 {
+ gpioA: gpio0@1f860000 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x000 0x48>;
+ reg = <0x1f860000 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioB: gpio1@100 {
+ gpioB: gpio1@1f860100 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x100 0x48>;
+ reg = <0x1f860100 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioC: gpio2@200 {
+ gpioC: gpio2@1f860200 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x200 0x48>;
+ reg = <0x1f860200 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioD: gpio3@300 {
+ gpioD: gpio3@1f860300 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x300 0x48>;
+ reg = <0x1f860300 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioE: gpio4@400 {
+ gpioE: gpio4@1f860400 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x400 0x48>;
+ reg = <0x1f860400 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioF: gpio5@500 {
+ gpioF: gpio5@1f860500 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x500 0x48>;
+ reg = <0x1f860500 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioG: gpio6@600 {
+ gpioG: gpio6@1f860600 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x600 0x48>;
+ reg = <0x1f860600 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioH: gpio7@700 {
+ gpioH: gpio7@1f860700 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x700 0x48>;
+ reg = <0x1f860700 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioJ: gpio8@800 {
+ gpioJ: gpio9@1f860800 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x800 0x48>;
+ reg = <0x1f860800 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpioK: gpio9@900 {
+ gpioK: gpio10@1f860900 {
compatible = "microchip,pic32mzda-gpio";
- reg = <0x900 0x48>;
+ reg = <0x1f860900 0xe0>;
gpio-controller;
#gpio-cells = <2>;
};
@@ -153,6 +160,7 @@
sdhci: sdhci@1f8ec000 {
compatible = "microchip,pic32mzda-sdhci";
reg = <0x1f8ec000 0x100>;
+ interrupt-parent = <&evic>;
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock REF4CLK>, <&clock PB5CLK>;
clock-names = "base_clk", "sys_clk";
@@ -164,6 +172,7 @@
ethernet: ethernet@1f882000 {
compatible = "microchip,pic32mzda-eth";
reg = <0x1f882000 0x1000>;
+ interrupt-parent = <&evic>;
interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock PB5CLK>;
status = "disabled";
@@ -176,6 +185,7 @@
reg = <0x1f8e3000 0x1000>,
<0x1f884000 0x1000>;
reg-names = "mc", "control";
+ interrupt-parent = <&evic>;
interrupts = <132 IRQ_TYPE_EDGE_RISING>,
<133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock PB5CLK>;
diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts
index b3c916a6db..fc86154e0a 100644
--- a/arch/mips/dts/pic32mzda_sk.dts
+++ b/arch/mips/dts/pic32mzda_sk.dts
@@ -40,6 +40,7 @@
};
&sdhci {
+ microchip,use-sdcd;
status = "okay";
};
diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts
index 3502e4b8b7..9adf39652f 100644
--- a/arch/mips/dts/vocore_vocore2.dts
+++ b/arch/mips/dts/vocore_vocore2.dts
@@ -59,7 +59,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <25000000>;
+ spi-max-frequency = <40000000>;
reg = <0>;
};
};
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 7bf61e2d8d..6ff1ee3489 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -27,7 +27,6 @@ CONFIG_CMD_EXT4_WRITE=y
# CONFIG_EFI_PARTITION is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
-# CONFIG_BLK is not set
CONFIG_CLK=y
CONFIG_MMC=y
CONFIG_DM_MMC=y
diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig
index 99a1143e6e..5776aada15 100644
--- a/configs/vocore2_defconfig
+++ b/configs/vocore2_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x04e000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x20000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ARCH_MTMIPS=y
diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c
index 029e0fbc2b..e201bdb8f4 100644
--- a/drivers/mmc/pic32_sdhci.c
+++ b/drivers/mmc/pic32_sdhci.c
@@ -6,65 +6,76 @@
* Andrei Pistirica <andrei.pistirica@microchip.com>
*/
-#include <common.h>
#include <dm.h>
#include <sdhci.h>
-#include <linux/errno.h>
-#include <mach/pic32.h>
+#include <clk.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-static int pic32_sdhci_get_cd(struct sdhci_host *host)
-{
- /* PIC32 SDHCI CD errata:
- * - set CD_TEST and clear CD_TEST_INS bit
- */
- sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
-
- return 0;
-}
-
-static const struct sdhci_ops pic32_sdhci_ops = {
- .get_cd = pic32_sdhci_get_cd,
+struct pic32_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
};
static int pic32_sdhci_probe(struct udevice *dev)
{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
- const void *fdt = gd->fdt_blob;
- u32 f_min_max[2];
- fdt_addr_t addr;
- fdt_size_t size;
+
+ struct clk clk;
+ ulong clk_rate;
int ret;
- addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size);
- if (addr == FDT_ADDR_T_NONE)
+ ret = clk_get_by_name(dev, "base_clk", &clk);
+ if (ret)
+ return ret;
+
+ clk_rate = clk_get_rate(&clk);
+ clk_free(&clk);
+
+ if (IS_ERR_VALUE(clk_rate))
+ return clk_rate;
+
+ host->ioaddr = dev_remap_addr(dev);
+
+ if (!host->ioaddr)
return -EINVAL;
- host->ioaddr = ioremap(addr, size);
host->name = dev->name;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
- host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "bus-width", 4);
- host->ops = &pic32_sdhci_ops;
-
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
- "clock-freq-min-max", f_min_max, 2);
- if (ret) {
- printf("sdhci: clock-freq-min-max not found\n");
+ host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+ host->max_clk = clk_rate;
+
+ host->mmc = &plat->mmc;
+ host->mmc->dev = dev;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
+ if (ret)
return ret;
- }
- host->max_clk = f_min_max[1];
+ host->mmc->priv = host;
+ upriv->mmc = host->mmc;
- ret = add_sdhci(host, 0, f_min_max[0]);
+ ret = sdhci_probe(dev);
if (ret)
return ret;
- host->mmc->dev = dev;
+
+ if (!dev_read_bool(dev, "microchip,use-sdcd")) {
+ // Use workaround 1 for erratum #15 by default
+ u8 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl = (ctrl & ~SDHCI_CTRL_CD_TEST_INS) | SDHCI_CTRL_CD_TEST;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ }
return 0;
}
+static int pic32_sdhci_bind(struct udevice *dev)
+{
+ struct pic32_sdhci_plat *plat = dev_get_platdata(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
static const struct udevice_id pic32_sdhci_ids[] = {
{ .compatible = "microchip,pic32mzda-sdhci" },
{ }
@@ -74,6 +85,9 @@ U_BOOT_DRIVER(pic32_sdhci_drv) = {
.name = "pic32_sdhci",
.id = UCLASS_MMC,
.of_match = pic32_sdhci_ids,
+ .ops = &sdhci_ops,
+ .bind = pic32_sdhci_bind,
.probe = pic32_sdhci_probe,
.priv_auto_alloc_size = sizeof(struct sdhci_host),
+ .platdata_auto_alloc_size = sizeof(struct pic32_sdhci_plat)
};
diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c
index 911af1297b..899c279975 100644
--- a/drivers/pinctrl/pinctrl_pic32.c
+++ b/drivers/pinctrl/pinctrl_pic32.c
@@ -222,6 +222,31 @@ static void pic32_eth_pin_config(struct udevice *dev)
pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
}
+static void pic32_sdhci_pin_config(struct udevice *dev)
+{
+ struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct pic32_pin_config configs[] = {
+ /* SDWP - H2 */
+ PIN_CONFIG(PIC32_PORT_H, 2, PIN_CONFIG_PIC32_DIGITAL),
+ /* SDCD - A0 */
+ PIN_CONFIG(PIC32_PORT_A, 0, PIN_CONFIG_PIC32_DIGITAL),
+ /* SDCMD - D4 */
+ PIN_CONFIG(PIC32_PORT_D, 4, PIN_CONFIG_PIC32_DIGITAL),
+ /* SDCK - A6 */
+ PIN_CONFIG(PIC32_PORT_A, 6, PIN_CONFIG_PIC32_DIGITAL),
+ /* SDDATA0 - G13 */
+ PIN_CONFIG(PIC32_PORT_G, 13, PIN_CONFIG_PIC32_DIGITAL),
+ /* SDDATA1 - G12 */
+ PIN_CONFIG(PIC32_PORT_G, 12, PIN_CONFIG_PIC32_DIGITAL),
+ /* SDDATA2 - G14 */
+ PIN_CONFIG(PIC32_PORT_G, 14, PIN_CONFIG_PIC32_DIGITAL),
+ /* SDDATA3 - A7 */
+ PIN_CONFIG(PIC32_PORT_A, 7, PIN_CONFIG_PIC32_DIGITAL),
+ };
+
+ pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
+}
+
static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
@@ -240,6 +265,9 @@ static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_ETH:
pic32_eth_pin_config(dev);
break;
+ case PERIPH_ID_SDHCI:
+ pic32_sdhci_pin_config(dev);
+ break;
default:
debug("%s: unknown-unhandled case\n", __func__);
break;
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
index 40467b737c..dfdb8fcc04 100644
--- a/include/configs/vocore2.h
+++ b/include/configs/vocore2.h
@@ -25,6 +25,7 @@
#define CONFIG_SPL_BSS_START_ADDR 0x80010000
#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
#define CONFIG_SPL_MAX_SIZE 0x10000
+#define CONFIG_SPL_PAD_TO 0
/* Dummy value */
#define CONFIG_SYS_UBOOT_BASE 0
@@ -34,12 +35,13 @@
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM3 0xb0000e00
+#define CONFIG_CONS_INDEX 3
/* RAM */
/* Memory usage */
#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_CBSIZE 512
generated by cgit (git 2.34.1) at 2024-12-23 00:09:36 +0000