diff options
1080 files changed, 27070 insertions, 6462 deletions
diff --git a/.gitignore b/.gitignore index 29757aa51e..f1b801579c 100644 --- a/.gitignore +++ b/.gitignore @@ -85,3 +85,7 @@ GTAGS *.orig *~ \#*# + +# gcc code coverage files +*.gcda +*.gcno @@ -59,6 +59,13 @@ config CC_OPTIMIZE_FOR_SIZE This option is enabled by default for U-Boot. +config CC_COVERAGE + bool "Enable code coverage analysis" + depends on SANDBOX + help + Enabling this option will pass "--coverage" to gcc to compile + and link code instrumented for coverage analysis. + config DISTRO_DEFAULTS bool "Select defaults suitable for booting general purpose Linux distributions" default y if ARCH_SUNXI || TEGRA @@ -69,22 +76,16 @@ config DISTRO_DEFAULTS imply USE_BOOTCOMMAND select CMD_BOOTZ if ARM && !ARM64 select CMD_BOOTI if ARM64 - select CMD_DHCP if NET && CMD_NET - select CMD_PXE if NET && CMD_NET + select CMD_DHCP if CMD_NET + select CMD_PING if CMD_NET + select CMD_PXE if NET select CMD_EXT2 select CMD_EXT4 select CMD_FAT select CMD_FS_GENERIC imply CMD_MII if NET - select CMD_PING if NET select CMD_PART if PARTITIONS select HUSH_PARSER - select BOOTP_BOOTPATH if NET && CMD_NET - select BOOTP_DNS if NET && CMD_NET - select BOOTP_GATEWAY if NET && CMD_NET - select BOOTP_HOSTNAME if NET && CMD_NET - select BOOTP_PXE if NET && CMD_NET - select BOOTP_SUBNETMASK if NET && CMD_NET select CMDLINE_EDITING select AUTO_COMPLETE select SYS_LONGHELP @@ -131,6 +132,7 @@ config SYS_MALLOC_F config SYS_MALLOC_F_LEN hex "Size of malloc() pool before relocation" depends on SYS_MALLOC_F + default 0x1000 if AM33XX default 0x400 help Before relocation, memory is very limited on many platforms. Still, diff --git a/MAINTAINERS b/MAINTAINERS index fde77b2b61..9f653a0137 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -55,7 +55,9 @@ Maintainers List (try to look for most precise areas first) ----------------------------------- ARC M: Alexey Brodkin <alexey.brodkin@synopsys.com> +M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> S: Maintained +L: uboot-snps-arc@synopsys.com T: git git://git.denx.de/u-boot-arc.git F: arch/arc/ @@ -201,8 +203,8 @@ ARM STM STM32MP M: Patrick Delaunay <patrick.delaunay@st.com> S: Maintained F: arch/arm/mach-stm32mp -F: clk/clk_stm32mp1.c -F: ram/stm32mp1 +F: drivers/clk/clk_stm32mp1.c +F: drivers/ram/stm32mp1/ ARM STM STV0991 M: Vikas Manocha <vikas.manocha@st.com> @@ -264,7 +266,7 @@ F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c F: drivers/usb/host/ehci-zynq.c F: drivers/watchdog/cdns_wdt.c -F: include/zynqmp.h +F: include/zynqpl.h F: tools/zynqimage.c N: zynq @@ -273,7 +275,7 @@ M: Michal Simek <michal.simek@xilinx.com> S: Maintained T: git git://git.denx.de/u-boot-microblaze.git F: arch/arm/mach-zynq/ -F: drivers/clk/clk_zynq.c +F: drivers/clk/clk_zynqmp.c F: drivers/fpga/zynqpl.c F: drivers/gpio/zynq_gpio.c F: drivers/i2c/i2c-cdns.c @@ -288,7 +290,7 @@ F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c F: drivers/usb/host/ehci-zynq.c F: drivers/watchdog/cdns_wdt.c -F: include/zynqmp.h +F: include/zynqmppl.h F: tools/zynqimage.c N: zynqmp @@ -330,7 +332,7 @@ EFI PAYLOAD M: Alexander Graf <agraf@suse.de> S: Maintained T: git git://github.com/agraf/u-boot.git -F: doc/README.efi +F: doc/README.uefi F: doc/README.iscsi F: include/efi* F: include/pe.h @@ -5,7 +5,7 @@ VERSION = 2018 PATCHLEVEL = 05 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 NAME = # *DOCUMENTATION* @@ -725,6 +725,12 @@ else PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc endif PLATFORM_LIBS += $(PLATFORM_LIBGCC) + +ifdef CONFIG_CC_COVERAGE +KBUILD_CFLAGS += --coverage +PLATFORM_LIBGCC += -lgcov +endif + export PLATFORM_LIBS export PLATFORM_LIBGCC @@ -786,8 +792,12 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy) ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img else +ifeq ($(CONFIG_MX7)$(CONFIG_SECURE_BOOT), yy) +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img +else ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img endif +endif ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb ifeq ($(CONFIG_SPL_FRAMEWORK),y) @@ -850,11 +860,11 @@ MKIMAGEOUTPUT ?= /dev/null quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_mkfitimage = MKIMAGE $@ cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -f $(U_BOOT_ITS) -E $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) quiet_cmd_cat = CAT $@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@ @@ -812,14 +812,6 @@ The following options need to be configured: CONFIG_AT91_HW_WDT_TIMEOUT specify the timeout in seconds. default 2 seconds. -- U-Boot Version: - CONFIG_VERSION_VARIABLE - If this variable is defined, an environment variable - named "ver" is created by U-Boot showing the U-Boot - version as printed by the "version" command. - Any change to this variable will be reverted at the - next reset. - - Real-Time Clock: When CONFIG_CMD_DATE is selected, the type of the RTC @@ -2213,12 +2205,6 @@ The following options need to be configured: the environment like the "source" command or the boot command first. - CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - - Define this in order to add variables describing certain - run-time determined information about the hardware to the - environment. These will be named board_name, board_rev. - CONFIG_DELAY_ENVIRONMENT Normally the environment is loaded when the board is diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c index 435fe96ef4..822318ff43 100644 --- a/arch/arc/lib/init_helpers.c +++ b/arch/arc/lib/init_helpers.c @@ -7,8 +7,6 @@ #include <asm/cache.h> #include <common.h> -DECLARE_GLOBAL_DATA_PTR; - int init_cache_f_r(void) { sync_n_cleanup_cache_all(); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 190f883aa8..7212fc5afa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -444,22 +444,6 @@ config TARGET_X600 select SUPPORT_SPL select PL011_SERIAL -config TARGET_IMX31_PHYCORE - bool "Support imx31_phycore_eet" - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - -config TARGET_IMX31_PHYCORE_EET - bool "Support imx31_phycore_eet" - select BOARD_LATE_INIT - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - -config TARGET_MX31ADS - bool "Support mx31ads" - select CPU_ARM1136 - select BOARD_EARLY_INIT_F - config TARGET_MX31PDK bool "Support mx31pdk" select BOARD_LATE_INIT @@ -1335,7 +1319,6 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" -source "board/freescale/mx31ads/Kconfig" source "board/freescale/mx31pdk/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" @@ -1345,7 +1328,6 @@ source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/poplar/Kconfig" -source "board/imx31_phycore/Kconfig" source "board/isee/igep003x/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/silica/pengwyn/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c index a02304f49e..f072f2e474 100644 --- a/arch/arm/cpu/arm926ejs/spear/spr_misc.c +++ b/arch/arm/cpu/arm926ejs/spear/spr_misc.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> +#include <environment.h> #include <i2c.h> #include <net.h> #include <linux/mtd/st_smi.h> diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index a424babde5..29597750f8 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -37,6 +37,9 @@ int cleanup_before_linux(void) * dcache flushing and disabling dcache */ invalidate_dcache_all(); + icache_disable(); + invalidate_icache_all(); + return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 7b59dc9a7c..c4a96d48ba 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -14,6 +14,9 @@ config ARCH_LS1012A select SYS_FSL_ERRATUM_A009008 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 imply PANIC_HANG config ARCH_LS1043A @@ -41,6 +44,11 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply SCSI imply SCSI_AHCI imply CMD_PCI @@ -70,6 +78,11 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply SCSI imply SCSI_AHCI @@ -102,6 +115,11 @@ config ARCH_LS1088A select FSL_TZASC_1 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply SCSI imply PANIC_HANG @@ -144,6 +162,11 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009203 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 imply PANIC_HANG config FSL_LSCH2 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 70a6070935..45cbd91d97 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -644,6 +644,7 @@ void __efi_runtime EFIAPI efi_reset_system( switch (reset_type) { case EFI_RESET_COLD: case EFI_RESET_WARM: + case EFI_RESET_PLATFORM_SPECIFIC: reset_cpu(0); break; case EFI_RESET_SHUTDOWN: @@ -654,9 +655,9 @@ void __efi_runtime EFIAPI efi_reset_system( while (1) { } } -void efi_reset_system_init(void) +efi_status_t efi_reset_system_init(void) { - efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); + return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr)); } #endif diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index c220267536..ff0712bf65 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -146,6 +146,7 @@ void __efi_runtime EFIAPI efi_reset_system( switch (reset_type) { case EFI_RESET_COLD: case EFI_RESET_WARM: + case EFI_RESET_PLATFORM_SPECIFIC: psci_system_reset(); break; case EFI_RESET_SHUTDOWN: diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3f10762b7d..ac7667b1e8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -143,16 +143,25 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ - zynq-zturn-myir.dtb \ + zynq-zturn.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc.dtb \ zynqmp-mini-nand.dtb \ + zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zcu102-rev1.0.dtb \ + zynqmp-zcu104-revA.dtb \ + zynqmp-zcu104-revC.dtb \ + zynqmp-zcu106-revA.dtb \ + zynqmp-zcu111-revA.dtb \ + zynqmp-zc1232-revA.dtb \ + zynqmp-zc1254-revA.dtb \ + zynqmp-zc1275-revA.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ @@ -184,6 +193,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ + socfpga_stratix10_socdk.dtb \ socfpga_cyclone5_vining_fpga.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index 7affab866f..b63f5a53ac 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -881,6 +881,14 @@ status = "disabled"; }; + wdog3: wdog@021e4000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x021e4000 0x4000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG3>; + status = "disabled"; + }; + uart2: serial@021e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 28b8422f31..f8ec649460 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -1026,6 +1026,14 @@ status = "disabled"; }; + wdog3: wdog@021e4000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x021e4000 0x4000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG3>; + status = "disabled"; + }; + uart2: serial@021e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; diff --git a/arch/arm/dts/r8a7790-stout-u-boot.dts b/arch/arm/dts/r8a7790-stout-u-boot.dts index 12092fcf5d..d2b7d371aa 100644 --- a/arch/arm/dts/r8a7790-stout-u-boot.dts +++ b/arch/arm/dts/r8a7790-stout-u-boot.dts @@ -8,3 +8,7 @@ #include "r8a7790-stout.dts" #include "r8a7790-u-boot.dtsi" + +&scifa0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/r8a7791-koelsch-u-boot.dts b/arch/arm/dts/r8a7791-koelsch-u-boot.dts index 9de45bb52d..58e15a4044 100644 --- a/arch/arm/dts/r8a7791-koelsch-u-boot.dts +++ b/arch/arm/dts/r8a7791-koelsch-u-boot.dts @@ -8,3 +8,7 @@ #include "r8a7791-koelsch.dts" #include "r8a7791-u-boot.dtsi" + +&scif0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dts b/arch/arm/dts/r8a7794-silk-u-boot.dts index 435cbc1f65..dcd954e04a 100644 --- a/arch/arm/dts/r8a7794-silk-u-boot.dts +++ b/arch/arm/dts/r8a7794-silk-u-boot.dts @@ -8,3 +8,7 @@ #include "r8a7794-silk.dts" #include "r8a7794-u-boot.dtsi" + +&scif2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index f7dc147317..31df1f62aa 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -1525,6 +1525,14 @@ dma-channels = <2>; }; + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7795", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7795"; reg = <0 0xee100000 0 0x2000>; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 83faabe040..7cb14bb65f 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -1350,6 +1350,14 @@ status = "disabled"; }; + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7796", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7796"; reg = <0 0xee100000 0 0x2000>; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 7eb4e65ea4..3630b52a92 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -748,6 +748,14 @@ status = "disabled"; }; + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77965", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee100000 0 0x2000>; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts index cb76c89b57..c051cddb25 100644 --- a/arch/arm/dts/r8a77970-eagle.dts +++ b/arch/arm/dts/r8a77970-eagle.dts @@ -17,6 +17,7 @@ aliases { serial0 = &scif0; ethernet0 = &avb; + spi0 = &rpc; }; chosen { @@ -59,6 +60,25 @@ }; }; +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi index 78e6f89e30..42c5c72bf2 100644 --- a/arch/arm/dts/r8a77970.dtsi +++ b/arch/arm/dts/r8a77970.dtsi @@ -381,5 +381,13 @@ #address-cells = <1>; #size-cells = <0>; }; + + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77970", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi index d1a03cf811..733b6afc89 100644 --- a/arch/arm/dts/r8a77995.dtsi +++ b/arch/arm/dts/r8a77995.dtsi @@ -400,5 +400,13 @@ #phy-cells = <0>; status = "disabled"; }; + + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77995", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 7557aa01e5..ead0560f47 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -14,6 +14,10 @@ aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; serial0 = &uart0; serial1 = &uart1; timer0 = &timer0; @@ -505,6 +509,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc04000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C0_RESET>; + reset-names = "i2c"; interrupts = <0 158 0x4>; status = "disabled"; }; @@ -515,6 +521,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc05000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C1_RESET>; + reset-names = "i2c"; interrupts = <0 159 0x4>; status = "disabled"; }; @@ -525,6 +533,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc06000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C2_RESET>; + reset-names = "i2c"; interrupts = <0 160 0x4>; status = "disabled"; }; @@ -535,6 +545,8 @@ compatible = "snps,designware-i2c"; reg = <0xffc07000 0x1000>; clocks = <&l4_sp_clk>; + resets = <&rst I2C3_RESET>; + reset-names = "i2c"; interrupts = <0 161 0x4>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts index dc09bed901..5e7fe2aa5f 100644 --- a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -56,6 +56,18 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + + dxl345: adxl345@0 { + compatible = "adi,adxl345"; + reg = <0x53>; + + interrupt-parent = <&portc>; + interrupts = <3 2>; + }; +}; + &mmc0 { status = "okay"; u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi new file mode 100644 index 0000000000..ddf8032b60 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -0,0 +1,381 @@ +/* + * Copyright (C) 2018 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "altr,socfpga-stratix10"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 120 8>, + <0 121 8>, + <0 122 8>, + <0 123 8>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0xfffc1000 0x0 0x1000>, + <0x0 0xfffc2000 0x0 0x2000>, + <0x0 0xfffc4000 0x0 0x2000>, + <0x0 0xfffc6000 0x0 0x2000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + clkmgr@ffd1000 { + compatible = "altr,clk-mgr"; + reg = <0xffd10000 0x1000>; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff800000 0x2000>; + interrupts = <0 90 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff802000 0x2000>; + interrupts = <0 91 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff804000 0x2000>; + interrupts = <0 92 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + gpio0: gpio@ffc03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03200 0x100>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + }; + }; + + gpio1: gpio@ffc03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03300 0x100>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + }; + }; + + i2c0: i2c@ffc02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02800 0x100>; + interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; + status = "disabled"; + }; + + i2c1: i2c@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02900 0x100>; + interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; + status = "disabled"; + }; + + i2c2: i2c@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02a00 0x100>; + interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; + status = "disabled"; + }; + + i2c3: i2c@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02b00 0x100>; + interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; + status = "disabled"; + }; + + i2c4: i2c@ffc02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02c00 0x100>; + interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; + status = "disabled"; + }; + + mmc: dwmmc0@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 96 4>; + fifo-depth = <0x400>; + resets = <&rst SDMMC_RESET>; + reset-names = "reset"; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x100000>; + }; + + rst: rstmgr@ffd11000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd11000 0x1000>; + altr,modrst-offset = <0x20>; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x1000>; + interrupts = <0 99 4>; + resets = <&rst SPIM0_RESET>; + reg-io-width = <4>; + num-chipselect = <4>; + bus-num = <0>; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x1000>; + interrupts = <0 100 4>; + resets = <&rst SPIM1_RESET>; + reg-io-width = <4>; + num-chipselect = <4>; + bus-num = <0>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd12000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd12000 0x1000>; + }; + + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + timer0: timer0@ffc03000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 113 4>; + reg = <0xffc03000 0x100>; + }; + + timer1: timer1@ffc03100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 114 4>; + reg = <0xffc03100 0x100>; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 4>; + reg = <0xffd00000 0x100>; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 4>; + reg = <0xffd00100 0x100>; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 108 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + }; + + uart1: serial1@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 109 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0x40000>; + interrupts = <0 93 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0x40000>; + interrupts = <0 94 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; + status = "disabled"; + }; + + watchdog2: watchdog@ffd00400 { + compatible = "snps,dw-wdt"; + reg = <0xffd00400 0x100>; + interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; + status = "disabled"; + }; + + watchdog3: watchdog@ffd00500 { + compatible = "snps,dw-wdt"; + reg = <0xffd00500 0x100>; + interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts new file mode 100644 index 0000000000..5e5ae62aa8 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2018 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SoCFPGA Stratix 10 SoCDK"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/dts/uniphier-ld11-global.dts b/arch/arm/dts/uniphier-ld11-global.dts index 5ffe7dedf7..11be2aa05e 100644 --- a/arch/arm/dts/uniphier-ld11-global.dts +++ b/arch/arm/dts/uniphier-ld11-global.dts @@ -1,14 +1,13 @@ -/* - * Device Tree Source for UniPhier LD11 Global Board - * - * Copyright (C) 2016-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * Kunihiko Hayashi <hayashi.kunihiko@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD11 Global Board +// +// Copyright (C) 2016-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> +// Kunihiko Hayashi <hayashi.kunihiko@socionext.com> /dts-v1/; +#include <dt-bindings/gpio/uniphier-gpio.h> #include "uniphier-ld11.dtsi" / { @@ -37,6 +36,53 @@ device_type = "memory"; reg = <0 0x80000000 0 0x40000000>; }; + + dvdd_reg: reg-fixed { + compatible = "regulator-fixed"; + regulator-name = "DVDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + amp_vcc_reg: reg-fixed { + compatible = "regulator-fixed"; + regulator-name = "AMP_VCC"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier LD11"; + widgets = "Headphone", "Headphone Jack"; + dais = <&i2s_port2 + &i2s_port3 + &i2s_port4 + &spdif_port0 + &comp_spdif_port0>; + }; + + spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + spdif_tx: endpoint { + remote-endpoint = <&spdif_hiecout1>; + }; + }; + }; + + comp-spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + comp_spdif_tx: endpoint { + remote-endpoint = <&comp_spdif_hiecout1>; + }; + }; + }; }; &serial0 { @@ -47,9 +93,43 @@ status = "okay"; }; +&i2s_hpcmout1 { + dai-format = "i2s"; + remote-endpoint = <&tas_speaker>; +}; + +&spdif_hiecout1 { + remote-endpoint = <&spdif_tx>; +}; + +&comp_spdif_hiecout1 { + remote-endpoint = <&comp_spdif_tx>; +}; + &i2c0 { status = "okay"; + tas5707a@1d { + compatible = "ti,tas5711"; + reg = <0x1d>; + reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>; + pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + AVDD-supply = <&dvdd_reg>; + DVDD-supply = <&dvdd_reg>; + PVDD_A-supply = <&_vcc_reg>; + PVDD_B-supply = <&_vcc_reg>; + PVDD_C-supply = <&_vcc_reg>; + PVDD_D-supply = <&_vcc_reg>; + + port@0 { + tas_speaker: endpoint { + dai-format = "i2s"; + remote-endpoint = <&i2s_hpcmout1>; + }; + }; + }; + eeprom@50 { compatible = "st,24c64", "atmel,24c64", "i2c-eeprom"; reg = <0x50>; @@ -69,6 +149,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; + &nand { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts index 54c5317069..b8f6273484 100644 --- a/arch/arm/dts/uniphier-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ld11-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD11 Reference Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD11 Reference Board +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-ld11.dtsi" @@ -70,3 +68,14 @@ &usb2 { status = "okay"; }; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 8b5b363508..bf3118eca3 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD11 SoC - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD11 SoC +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> @@ -191,6 +189,92 @@ <21 217 3>; }; + audio@56000000 { + compatible = "socionext,uniphier-ld11-aio"; + reg = <0x56000000 0x80000>; + interrupts = <0 144 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aout1>, + <&pinctrl_aoutiec1>; + clock-names = "aio"; + clocks = <&sys_clk 40>; + reset-names = "aio"; + resets = <&sys_rst 40>; + #sound-dai-cells = <1>; + socionext,syscon = <&soc_glue>; + + i2s_port0: port@0 { + i2s_hdmi: endpoint { + }; + }; + + i2s_port1: port@1 { + i2s_pcmin2: endpoint { + }; + }; + + i2s_port2: port@2 { + i2s_line: endpoint { + dai-format = "i2s"; + remote-endpoint = <&evea_line>; + }; + }; + + i2s_port3: port@3 { + i2s_hpcmout1: endpoint { + }; + }; + + i2s_port4: port@4 { + i2s_hp: endpoint { + dai-format = "i2s"; + remote-endpoint = <&evea_hp>; + }; + }; + + spdif_port0: port@5 { + spdif_hiecout1: endpoint { + }; + }; + + src_port0: port@6 { + i2s_epcmout2: endpoint { + }; + }; + + src_port1: port@7 { + i2s_epcmout3: endpoint { + }; + }; + + comp_spdif_port0: port@8 { + comp_spdif_hiecout1: endpoint { + }; + }; + }; + + codec@57900000 { + compatible = "socionext,uniphier-evea"; + reg = <0x57900000 0x1000>; + clock-names = "evea", "exiv"; + clocks = <&sys_clk 41>, <&sys_clk 42>; + reset-names = "evea", "exiv", "adamv"; + resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; + #sound-dai-cells = <1>; + + port@0 { + evea_line: endpoint { + remote-endpoint = <&i2s_line>; + }; + }; + + port@1 { + evea_hp: endpoint { + remote-endpoint = <&i2s_hp>; + }; + }; + }; + adamv@57920000 { compatible = "socionext,uniphier-ld11-adamv", "simple-mfd", "syscon"; @@ -400,7 +484,7 @@ }; }; - soc-glue@5f800000 { + soc_glue: soc-glue@5f800000 { compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -464,6 +548,22 @@ }; }; + eth: ethernet@65000000 { + compatible = "socionext,uniphier-ld11-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; @@ -479,3 +579,12 @@ }; #include "uniphier-pinctrl.dtsi" + +&pinctrl_aoutiec1 { + drive-strength = <4>; /* default: 4mA */ + + ao1arc { + pins = "AO1ARC"; + drive-strength = <8>; /* 8mA */ + }; +}; diff --git a/arch/arm/dts/uniphier-ld20-global.dts b/arch/arm/dts/uniphier-ld20-global.dts index fc2bc9d75d..fe6608ea32 100644 --- a/arch/arm/dts/uniphier-ld20-global.dts +++ b/arch/arm/dts/uniphier-ld20-global.dts @@ -1,14 +1,13 @@ -/* - * Device Tree Source for UniPhier LD20 Global Board - * - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * Kunihiko Hayashi <hayashi.kunihiko@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD20 Global Board +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> +// Kunihiko Hayashi <hayashi.kunihiko@socionext.com> /dts-v1/; +#include <dt-bindings/gpio/uniphier-gpio.h> #include "uniphier-ld20.dtsi" / { @@ -37,6 +36,53 @@ device_type = "memory"; reg = <0 0x80000000 0 0xc0000000>; }; + + dvdd_reg: reg-fixed { + compatible = "regulator-fixed"; + regulator-name = "DVDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + amp_vcc_reg: reg-fixed { + compatible = "regulator-fixed"; + regulator-name = "AMP_VCC"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier LD20"; + widgets = "Headphone", "Headphone Jack"; + dais = <&i2s_port2 + &i2s_port3 + &i2s_port4 + &spdif_port0 + &comp_spdif_port0>; + }; + + spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + spdif_tx: endpoint { + remote-endpoint = <&spdif_hiecout1>; + }; + }; + }; + + comp-spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + comp_spdif_tx: endpoint { + remote-endpoint = <&comp_spdif_hiecout1>; + }; + }; + }; }; &serial0 { @@ -47,8 +93,55 @@ status = "okay"; }; +&i2s_hpcmout1 { + dai-format = "i2s"; + remote-endpoint = <&tas_speaker>; +}; + +&spdif_hiecout1 { + remote-endpoint = <&spdif_tx>; +}; + +&comp_spdif_hiecout1 { + remote-endpoint = <&comp_spdif_tx>; +}; + &i2c0 { status = "okay"; + + tas5707@1b { + compatible = "ti,tas5711"; + reg = <0x1b>; + reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>; + pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + AVDD-supply = <&dvdd_reg>; + DVDD-supply = <&dvdd_reg>; + PVDD_A-supply = <&_vcc_reg>; + PVDD_B-supply = <&_vcc_reg>; + PVDD_C-supply = <&_vcc_reg>; + PVDD_D-supply = <&_vcc_reg>; + + port@0 { + tas_speaker: endpoint { + dai-format = "i2s"; + remote-endpoint = <&i2s_hpcmout1>; + }; + }; + }; +}; + +ð { + status = "okay"; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_ether_rmii>; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; }; &nand { diff --git a/arch/arm/dts/uniphier-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index 693371033c..2c1a92fafb 100644 --- a/arch/arm/dts/uniphier-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD20 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD20 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-ld20.dtsi" @@ -58,3 +56,14 @@ &i2c0 { status = "okay"; }; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@0 { + reg = <0>; + }; +}; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 4d8655e443..b993df8a34 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD20 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD20 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> @@ -291,6 +289,92 @@ <21 217 3>; }; + audio@56000000 { + compatible = "socionext,uniphier-ld20-aio"; + reg = <0x56000000 0x80000>; + interrupts = <0 144 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aout1>, + <&pinctrl_aoutiec1>; + clock-names = "aio"; + clocks = <&sys_clk 40>; + reset-names = "aio"; + resets = <&sys_rst 40>; + #sound-dai-cells = <1>; + socionext,syscon = <&soc_glue>; + + i2s_port0: port@0 { + i2s_hdmi: endpoint { + }; + }; + + i2s_port1: port@1 { + i2s_pcmin2: endpoint { + }; + }; + + i2s_port2: port@2 { + i2s_line: endpoint { + dai-format = "i2s"; + remote-endpoint = <&evea_line>; + }; + }; + + i2s_port3: port@3 { + i2s_hpcmout1: endpoint { + }; + }; + + i2s_port4: port@4 { + i2s_hp: endpoint { + dai-format = "i2s"; + remote-endpoint = <&evea_hp>; + }; + }; + + spdif_port0: port@5 { + spdif_hiecout1: endpoint { + }; + }; + + src_port0: port@6 { + i2s_epcmout2: endpoint { + }; + }; + + src_port1: port@7 { + i2s_epcmout3: endpoint { + }; + }; + + comp_spdif_port0: port@8 { + comp_spdif_hiecout1: endpoint { + }; + }; + }; + + codec@57900000 { + compatible = "socionext,uniphier-evea"; + reg = <0x57900000 0x1000>; + clock-names = "evea", "exiv"; + clocks = <&sys_clk 41>, <&sys_clk 42>; + reset-names = "evea", "exiv", "adamv"; + resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; + #sound-dai-cells = <1>; + + port@0 { + evea_line: endpoint { + remote-endpoint = <&i2s_line>; + }; + }; + + port@1 { + evea_hp: endpoint { + remote-endpoint = <&i2s_hp>; + }; + }; + }; + adamv@57920000 { compatible = "socionext,uniphier-ld20-adamv", "simple-mfd", "syscon"; @@ -460,7 +544,7 @@ cap-sd-highspeed; }; - soc-glue@5f800000 { + soc_glue: soc-glue@5f800000 { compatible = "socionext,uniphier-ld20-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -531,6 +615,24 @@ }; }; + eth: ethernet@65000000 { + compatible = "socionext,uniphier-ld20-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usb: usb@65b00000 { compatible = "socionext,uniphier-ld20-dwc3"; reg = <0x65b00000 0x1000>; @@ -564,3 +666,21 @@ }; #include "uniphier-pinctrl.dtsi" + +&pinctrl_aout1 { + drive-strength = <4>; /* default: 3.5mA */ + + ao1dacck { + pins = "AO1DACCK"; + drive-strength = <5>; /* 5mA */ + }; +}; + +&pinctrl_aoutiec1 { + drive-strength = <4>; /* default: 3.5mA */ + + ao1arc { + pins = "AO1ARC"; + drive-strength = <11>; /* 11mA */ + }; +}; diff --git a/arch/arm/dts/uniphier-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts index 6097878d87..3aaca10f66 100644 --- a/arch/arm/dts/uniphier-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ld4-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD4 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD4 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-ld4.dtsi" diff --git a/arch/arm/dts/uniphier-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index 0393bceffa..5e43a9231e 100644 --- a/arch/arm/dts/uniphier-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD4 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD4 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> diff --git a/arch/arm/dts/uniphier-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts index 1703d8f7a4..3d9080ee7a 100644 --- a/arch/arm/dts/uniphier-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ld6b-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD6b Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD6b Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-ld6b.dtsi" @@ -71,6 +69,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@0 { + reg = <0>; + }; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-ld6b.dtsi b/arch/arm/dts/uniphier-ld6b.dtsi index 9a7b25cc82..4d07a94c6b 100644 --- a/arch/arm/dts/uniphier-ld6b.dtsi +++ b/arch/arm/dts/uniphier-ld6b.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier LD6b SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier LD6b SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /* * LD6b consists of two silicon dies: D-chip and A-chip. diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi index d4f78c2cd4..9dd9d49ad7 100644 --- a/arch/arm/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/dts/uniphier-pinctrl.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier SoCs default pinctrl settings - * - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier SoCs default pinctrl settings +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> &pinctrl { pinctrl_aout: aout { @@ -13,6 +11,46 @@ function = "aout"; }; + pinctrl_ain1: ain1 { + groups = "ain1"; + function = "ain1"; + }; + + pinctrl_ain2: ain2 { + groups = "ain2"; + function = "ain2"; + }; + + pinctrl_ainiec1: ainiec1 { + groups = "ainiec1"; + function = "ainiec1"; + }; + + pinctrl_aout1: aout1 { + groups = "aout1"; + function = "aout1"; + }; + + pinctrl_aout2: aout2 { + groups = "aout2"; + function = "aout2"; + }; + + pinctrl_aout3: aout3 { + groups = "aout3"; + function = "aout3"; + }; + + pinctrl_aoutiec1: aoutiec1 { + groups = "aoutiec1"; + function = "aoutiec1"; + }; + + pinctrl_aoutiec2: aoutiec2 { + groups = "aoutiec2"; + function = "aoutiec2"; + }; + pinctrl_emmc: emmc { groups = "emmc", "emmc_dat8"; function = "emmc"; @@ -38,6 +76,16 @@ function = "ether_rmii"; }; + pinctrl_ether1_rgmii: ether1-rgmii { + groups = "ether1_rgmii"; + function = "ether1_rgmii"; + }; + + pinctrl_ether1_rmii: ether1-rmii { + groups = "ether1_rmii"; + function = "ether1_rmii"; + }; + pinctrl_i2c0: i2c0 { groups = "i2c0"; function = "i2c0"; diff --git a/arch/arm/dts/uniphier-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index 60a8c33767..bff90c256b 100644 --- a/arch/arm/dts/uniphier-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 Ace Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Ace Board +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-pro4.dtsi" @@ -83,6 +81,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; + &usb2 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts index c2466cdfe5..198add3409 100644 --- a/arch/arm/dts/uniphier-pro4-ref.dts +++ b/arch/arm/dts/uniphier-pro4-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-pro4.dtsi" @@ -84,6 +82,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@0 { + reg = <0>; + }; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts index 950f47abf8..7f5b957f98 100644 --- a/arch/arm/dts/uniphier-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 Sanji Board - * - * Copyright (C) 2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 Sanji Board +// +// Copyright (C) 2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-pro4.dtsi" @@ -78,6 +76,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; + &usb2 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index e9d3a3d186..25c4b4f8fc 100644 --- a/arch/arm/dts/uniphier-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro4 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro4 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> @@ -422,6 +420,24 @@ }; }; + eth: ethernet@65000000 { + compatible = "socionext,uniphier-pro4-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usb0: usb@65b00000 { compatible = "socionext,uniphier-pro4-dwc3"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index a4de9b8aac..32debf557e 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Pro5 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Pro5 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> / { compatible = "socionext,uniphier-pro5"; diff --git a/arch/arm/dts/uniphier-pxs2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts index 4397714e49..b13d6277bf 100644 --- a/arch/arm/dts/uniphier-pxs2-gentil.dts +++ b/arch/arm/dts/uniphier-pxs2-gentil.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs2 Gentil Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 Gentil Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-pxs2.dtsi" @@ -34,6 +32,12 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier PXs2"; + dais = <&i2s_port2>; + }; }; &serial2 { @@ -51,14 +55,43 @@ }; }; +&i2s_aux { + dai-format = "i2s"; + remote-endpoint = <&wm_speaker>; +}; + &i2c2 { status = "okay"; + + wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + #sound-dai-cells = <0>; + + port@0 { + wm_speaker: endpoint { + dai-format = "i2s"; + remote-endpoint = <&i2s_aux>; + }; + }; + }; }; &emmc { status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pxs2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts index d29096fc19..23fe42b740 100644 --- a/arch/arm/dts/uniphier-pxs2-vodka.dts +++ b/arch/arm/dts/uniphier-pxs2-vodka.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs2 Vodka Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 Vodka Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-pxs2.dtsi" @@ -32,12 +30,49 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier PXs2"; + dais = <&spdif_port0 + &comp_spdif_port0>; + }; + + spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + spdif_tx: endpoint { + remote-endpoint = <&spdif_hiecout1>; + }; + }; + }; + + comp-spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + comp_spdif_tx: endpoint { + remote-endpoint = <&comp_spdif_hiecout1>; + }; + }; + }; }; &serial2 { status = "okay"; }; +&spdif_hiecout1 { + remote-endpoint = <&spdif_tx>; +}; + +&comp_spdif_hiecout1 { + remote-endpoint = <&comp_spdif_tx>; +}; + &i2c0 { status = "okay"; }; @@ -46,6 +81,17 @@ status = "okay"; }; +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@1 { + reg = <1>; + }; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 7822c9e128..9760f79e7c 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs2 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs2 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> #include <dt-bindings/thermal/thermal.h> @@ -231,6 +229,61 @@ <21 217 3>; }; + audio@56000000 { + compatible = "socionext,uniphier-pxs2-aio"; + reg = <0x56000000 0x80000>; + interrupts = <0 144 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ain1>, + <&pinctrl_ain2>, + <&pinctrl_ainiec1>, + <&pinctrl_aout2>, + <&pinctrl_aout3>, + <&pinctrl_aoutiec1>, + <&pinctrl_aoutiec2>; + clock-names = "aio"; + clocks = <&sys_clk 40>; + reset-names = "aio"; + resets = <&sys_rst 40>; + #sound-dai-cells = <1>; + socionext,syscon = <&soc_glue>; + + i2s_port0: port@0 { + i2s_hdmi: endpoint { + }; + }; + + i2s_port1: port@1 { + i2s_line: endpoint { + }; + }; + + i2s_port2: port@2 { + i2s_aux: endpoint { + }; + }; + + spdif_port0: port@3 { + spdif_hiecout1: endpoint { + }; + }; + + spdif_port1: port@4 { + spdif_iecout1: endpoint { + }; + }; + + comp_spdif_port0: port@5 { + comp_spdif_hiecout1: endpoint { + }; + }; + + comp_spdif_port1: port@6 { + comp_spdif_iecout1: endpoint { + }; + }; + }; + i2c0: i2c@58780000 { compatible = "socionext,uniphier-fi2c"; status = "disabled"; @@ -405,7 +458,7 @@ sd-uhs-sdr50; }; - soc-glue@5f800000 { + soc_glue: soc-glue@5f800000 { compatible = "socionext,uniphier-pxs2-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -485,6 +538,24 @@ }; }; + eth: ethernet@65000000 { + compatible = "socionext,uniphier-pxs2-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs2-dwc3"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-pxs3-ref.dts b/arch/arm/dts/uniphier-pxs3-ref.dts index 0463a8f0ba..3b9931a00d 100644 --- a/arch/arm/dts/uniphier-pxs3-ref.dts +++ b/arch/arm/dts/uniphier-pxs3-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs3 Reference Board - * - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs3 Reference Board +// +// Copyright (C) 2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-pxs3.dtsi" @@ -77,6 +75,28 @@ status = "okay"; }; +ð0 { + status = "okay"; + phy-handle = <ðphy0>; +}; + +&mdio0 { + ethphy0: ethphy@0 { + reg = <0>; + }; +}; + +ð1 { + status = "okay"; + phy-handle = <ðphy1>; +}; + +&mdio1 { + ethphy1: ethphy@0 { + reg = <0>; + }; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index 87ab5e7ff8..d4c458a211 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier PXs3 SoC - * - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier PXs3 SoC +// +// Copyright (C) 2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/uniphier-gpio.h> @@ -361,7 +359,7 @@ cap-sd-highspeed; }; - soc-glue@5f800000 { + soc_glue: soc-glue@5f800000 { compatible = "socionext,uniphier-pxs3-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -425,6 +423,42 @@ }; }; + eth0: ethernet@65000000 { + compatible = "socionext,uniphier-pxs3-ave4"; + status = "disabled"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether_rgmii>; + clocks = <&sys_clk 6>; + resets = <&sys_rst 6>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + eth1: ethernet@65200000 { + compatible = "socionext,uniphier-pxs3-ave4"; + status = "disabled"; + reg = <0x65200000 0x8500>; + interrupts = <0 67 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ether1_rgmii>; + clocks = <&sys_clk 7>; + resets = <&sys_rst 7>; + phy-mode = "rgmii"; + local-mac-address = [00 00 00 00 00 00]; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + usb0: usb@65b00000 { compatible = "socionext,uniphier-pxs3-dwc3"; status = "disabled"; diff --git a/arch/arm/dts/uniphier-ref-daughter.dtsi b/arch/arm/dts/uniphier-ref-daughter.dtsi index 78eccfdd3a..9240a313b9 100644 --- a/arch/arm/dts/uniphier-ref-daughter.dtsi +++ b/arch/arm/dts/uniphier-ref-daughter.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Reference Daughter Board - * - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Reference Daughter Board +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> &i2c0 { eeprom@50 { diff --git a/arch/arm/dts/uniphier-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts index 8fae1ed998..01bf94c6b9 100644 --- a/arch/arm/dts/uniphier-sld8-ref.dts +++ b/arch/arm/dts/uniphier-sld8-ref.dts @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier sLD8 Reference Board - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier sLD8 Reference Board +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> /dts-v1/; #include "uniphier-sld8.dtsi" diff --git a/arch/arm/dts/uniphier-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index fc7585b2ce..67d69778a4 100644 --- a/arch/arm/dts/uniphier-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier sLD8 SoC - * - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier sLD8 SoC +// +// Copyright (C) 2015-2016 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> #include <dt-bindings/gpio/uniphier-gpio.h> diff --git a/arch/arm/dts/uniphier-support-card.dtsi b/arch/arm/dts/uniphier-support-card.dtsi index e4e7e1bb91..bf441c2eff 100644 --- a/arch/arm/dts/uniphier-support-card.dtsi +++ b/arch/arm/dts/uniphier-support-card.dtsi @@ -1,11 +1,9 @@ -/* - * Device Tree Source for UniPhier Support Card (Expansion Board) - * - * Copyright (C) 2015-2017 Socionext Inc. - * Author: Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for UniPhier Support Card (Expansion Board) +// +// Copyright (C) 2015-2017 Socionext Inc. +// Author: Masahiro Yamada <yamada.masahiro@socionext.com> &system_bus { status = "okay"; diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi index 0094a455d2..9459bf0377 100644 --- a/arch/arm/dts/uniphier-v7-u-boot.dtsi +++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi @@ -14,22 +14,6 @@ u-boot,dm-pre-reloc; }; - mioctrl@59810000 { - u-boot,dm-pre-reloc; - - clock { - u-boot,dm-pre-reloc; - }; - }; - - sdctrl@59810000 { - u-boot,dm-pre-reloc; - - clock { - u-boot,dm-pre-reloc; - }; - }; - soc-glue@5f800000 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index 4804da5235..5f8a0d2555 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -1,13 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx CC108 board DTS * - * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2018 Xilinx, Inc. * (C) Copyright 2007-2013 Michal Simek * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd * * Michal SIMEK <monstr@monstr.eu> - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; /include/ "zynq-7000.dtsi" @@ -70,23 +69,23 @@ label = "qspi-fsbl-uboot-bs"; reg = <0x0 0x400000>; /* 4MB */ }; - partition@0x400000 { + partition@400000 { label = "qspi-linux"; reg = <0x400000 0x400000>; /* 4MB */ }; - partition@0x800000 { + partition@800000 { label = "qspi-rootfs"; reg = <0x800000 0x400000>; /* 4MB */ }; - partition@0xc00000 { + partition@c00000 { label = "qspi-devicetree"; reg = <0xc00000 0x100000>; /* 1MB */ }; - partition@0xd00000 { + partition@d00000 { label = "qspi-scratch"; reg = <0xd00000 0x200000>; /* 2MB */ }; - partition@0xf00000 { + partition@f00000 { label = "qspi-uboot-env"; reg = <0xf00000 0x100000>; /* 1MB */ }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index da698a19cc..bb224662bb 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC702 board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" @@ -114,7 +111,7 @@ scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; - i2cswitch@74 { + i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -154,7 +151,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index a88a83c166..f24364b385 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC706 board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" @@ -65,7 +62,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; - i2cswitch@74 { + i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -105,7 +102,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index cc5ba98d6b..a779672f3a 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM010 board DTS * - * Copyright (C) 2013 - 2015 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2013-2018 Xilinx, Inc. */ /dts-v1/; #include "zynq-7000.dtsi" @@ -55,8 +54,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; @@ -75,14 +74,17 @@ num-cs = <4>; is-decoded-cs = <0>; flash@0 { - compatible = "sst25wf080"; + compatible = "sst25wf080", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@test { - label = "spi-flash"; - reg = <0x0 0x100000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "data"; + reg = <0x0 0x100000>; + }; }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 7f08961491..3fe6eb559e 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM013 board DTS * - * Copyright (C) 2013 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2013-2018 Xilinx, Inc. */ /dts-v1/; #include "zynq-7000.dtsi" @@ -42,8 +41,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 699cd2c0fb..19d5b275ae 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM012 board DTS * - * Copyright (C) 2013 - 2015 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2013-2018 Xilinx, Inc. */ /dts-v1/; #include "zynq-7000.dtsi" @@ -38,8 +37,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom0: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; }; @@ -48,8 +47,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom1: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 81a6aa562a..efd0833eab 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM013 board DTS * * Copyright (C) 2013 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" @@ -68,7 +67,7 @@ status = "okay"; num-cs = <4>; is-decoded-cs = <0>; - eeprom: at25@0 { + eeprom: eeprom@0 { at25,byte-len = <8192>; at25,addr-mode = <2>; at25,page-size = <32>; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index a9ff0e6fa8..24eccf1633 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZED board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zturn-myir.dts b/arch/arm/dts/zynq-zturn.dts index a5ecfcc1d7..8aa384b59b 100644 --- a/arch/arm/dts/zynq-zturn-myir.dts +++ b/arch/arm/dts/zynq-zturn.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com> * Copyright (C) 2017 Alexander Graf <agraf@suse.de> @@ -6,31 +7,23 @@ * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ + /dts-v1/; /include/ "zynq-7000.dtsi" / { model = "Zynq Z-Turn MYIR Board"; - compatible = "xlnx,zynq-7000"; + compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; serial0 = &uart1; serial1 = &uart0; - spi0 = &qspi; mmc0 = &sdhci0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; @@ -41,52 +34,23 @@ gpio-leds { compatible = "gpio-leds"; - led_r { - label = "led_r"; - gpios = <&gpio0 0x72 0x1>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led_g { - label = "led_g"; - gpios = <&gpio0 0x73 0x1>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led_b { - label = "led_b"; - gpios = <&gpio0 0x74 0x1>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - usr_led1 { - label = "usr_led1"; + usr-led1 { + label = "usr-led1"; gpios = <&gpio0 0x0 0x1>; default-state = "off"; - linux,default-trigger = "none"; }; - usr_led2 { - label = "usr_led2"; + usr-led2 { + label = "usr-led2"; gpios = <&gpio0 0x9 0x1>; default-state = "off"; - linux,default-trigger = "none"; }; }; - gpio-beep { - compatible = "gpio-beeper"; - label = "pl-beep"; - gpios = <&gpio0 0x75 0x0>; - }; - gpio-keys { compatible = "gpio-keys"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <1>; + #size-cells = <0>; autorepeat; K1 { label = "K1"; @@ -100,7 +64,6 @@ &clkc { ps-clk-frequency = <33333333>; - fclk-enable = <0xf>; }; &qspi { @@ -152,8 +115,8 @@ reg = <0x49>; }; - adxl345@53 { - compatible = "adi,adxl34x", "adxl34x"; + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; reg = <0x53>; interrupt-parent = <&intc>; interrupts = <0x0 0x1e 0x4>; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 52ec5a4566..3844822305 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Digilent ZYBO board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 4449d5b93d..b18d8d19c3 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ / { diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index f6e83e1513..a8664e8187 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ / { @@ -26,6 +25,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; + u-boot,dm-pre-reloc; }; clk250: clk250 { diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts new file mode 100644 index 0000000000..ea1ca561a1 --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1232 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZC1232 RevA"; + compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB FIXME */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts new file mode 100644 index 0000000000..2493883e6f --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1254 + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZC1254 RevA"; + compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zc1275-revA.dts new file mode 100644 index 0000000000..2543a674ca --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1275-revA.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1275 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZC1275 RevA"; + compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 9062ffe919..c794c91de1 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; @@ -40,7 +39,6 @@ }; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -93,8 +91,9 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; - eeprom@55 { - compatible = "at,24c64"; /* 24AA64 */ + + eeprom: eeprom@55 { + compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index bf43bf8748..afa90a8a5b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; @@ -50,7 +49,6 @@ status = "okay"; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -180,15 +178,15 @@ &spi0 { status = "okay"; num-cs = <1>; - spi0_flash0: spi0_flash0@0 { - compatible = "m25p80"; + spi0_flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; + compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; - spi0_flash0@0 { - label = "spi0_flash0"; + partition@0 { + label = "data"; reg = <0x0 0x100000>; }; }; @@ -197,15 +195,15 @@ &spi1 { status = "okay"; num-cs = <1>; - spi1_flash0: spi1_flash0@0 { - compatible = "mtd_dataflash"; + spi1_flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; + compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; - spi1_flash0@0 { - label = "spi1_flash0"; + partition@0 { + label = "data"; reg = <0x0 0x84000>; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts new file mode 100644 index 0000000000..d6a010355b --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP zc1751-xm017-dc3 + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP zc1751-xm017-dc3 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { /* VSC8211 */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +/* just eeprom here */ +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u26: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +/* eeprom24c02 and SE98A temp chip pca9306 */ +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; + +/* MT29F64G08AECDBJ4-6 */ +&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <2>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; + + partition@6 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x1 0x0 0x400000>; + }; + partition@7 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x1 0x400000 0x1400000>; + }; + partition@8 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x1 0x1800000 0x400000>; + }; + partition@9 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x1 0x1C00000 0x1400000>; + }; + partition@10 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x1 0x3000000 0x400000>; + }; + partition@11 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x1 0x3400000 0xFCC00000>; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +&sdhci1 { /* emmc with some settings */ + status = "okay"; +}; + +/* main */ +&uart0 { + status = "okay"; +}; + +/* DB9 */ +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 39c82c592f..fb49b4fcb4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2016, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; @@ -52,7 +51,6 @@ status = "okay"; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index c774b866fb..0632b18ccf 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -1,12 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; @@ -38,7 +37,6 @@ }; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -84,18 +82,33 @@ status = "okay"; }; -/* FIXME: Add device */ &i2c0 { status = "okay"; }; -/* FIXME: Add device */ &i2c1 { status = "okay"; }; &sdhci0 { status = "okay"; + no-1-8-v; +}; + +&ttc0 { + status = "okay"; +}; + +&ttc1 { + status = "okay"; +}; + +&ttc2 { + status = "okay"; +}; + +&ttc3 { + status = "okay"; }; &uart0 { diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts new file mode 100644 index 0000000000..9114f98140 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU100 revC + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * Nathalie Chan King Choy + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU100 RevC"; + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; + + aliases { + gpio0 = &gpio; + i2c0 = &i2c1; + rtc0 = &rtc; + serial0 = &uart1; + serial1 = &uart0; + serial2 = &dcc; + spi0 = &spi0; + spi1 = &spi1; + usb0 = &usb0; + usb1 = &usb1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw4 { + label = "sw4"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + autorepeat; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, + <&xilinx_ams 11>, <&xilinx_ams 12>; + }; + + leds { + compatible = "gpio-leds"; + ds2 { + label = "ds2"; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds3 { + label = "ds3"; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; /* WLAN tx */ + default-state = "off"; + }; + + ds4 { + label = "ds4"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0rx"; /* WLAN rx */ + default-state = "off"; + }; + + ds5 { + label = "ds5"; + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + }; + + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ + label = "vbus_det"; + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + ltc2954: ltc2954 { /* U7 */ + compatible = "lltc,ltc2954", "lltc,ltc2952"; + trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ + /* If there is HW watchdog on mezzanine this signal should be connected there */ + watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ + kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ + }; + + wmmcsdio_fixed: fixedregulator-mmcsdio { + compatible = "regulator-fixed"; + regulator-name = "wmmcsdio_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + sdio_pwrseq: sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + }; +}; + +&dcc { + status = "okay"; +}; + +&gpio { + status = "okay"; + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ + "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + i2c-mux@75 { /* u11 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2csw_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + label = "LS-I2C0"; + }; + i2csw_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + label = "LS-I2C1"; + }; + i2csw_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + label = "HS-I2C2"; + }; + i2csw_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + label = "HS-I2C3"; + }; + i2csw_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + pmic: pmic@5e { /* Custom TI PMIC u33 */ + compatible = "ti,tps65086"; + reg = <0x5e>; + interrupt-parent = <&gpio>; + interrupts = <77 GPIO_ACTIVE_LOW>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + i2csw_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* PS_PMBUS */ + ina226@40 { /* u35 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <10000>; + /* MIO31 is alert which should be routed to PMUFW */ + }; + }; + i2csw_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* + * Not Connected + */ + }; + i2csw_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* + * usb5744 (DNP) - U5 + * 100kHz - this is default freq for us + */ + }; + }; +}; + +&rtc { + status = "okay"; +}; + +/* SD0 only supports 3.3V, no level shifter */ +&sdhci0 { + status = "okay"; + no-1-8-v; + broken-cd; /* CD has to be enabled by default */ + disable-wp; + xlnx,mio_bank = <0>; +}; + +&sdhci1 { + status = "okay"; + bus-width = <0x4>; + xlnx,mio_bank = <0>; + non-removable; + disable-wp; + cap-power-off-card; + mmc-pwrseq = <&sdio_pwrseq>; + vqmmc-supply = <&wmmcsdio_fixed>; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wifi@2 { + compatible = "ti,wl1831"; + reg = <2>; + interrupt-parent = <&gpio>; + interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ + }; +}; + +&serdes { + status = "okay"; +}; + +&spi0 { /* Low Speed connector */ + status = "okay"; + label = "LS-SPI0"; +}; + +&spi1 { /* High Speed connector */ + status = "okay"; + label = "HS-SPI1"; +}; + +&uart0 { + status = "okay"; + bluetooth { + compatible = "ti,wl1831-st"; + enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + +}; + +&uart1 { + status = "okay"; + +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; + maximum-speed = "super-speed"; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + phy-names = "usb3-phy"; + phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; + maximum-speed = "super-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index 323a674e3a..6647e97edb 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ #include "zynqmp-zcu102-revB.dts" @@ -15,23 +14,23 @@ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; -&eeprom { +&eeprom { #address-cells = <1>; #size-cells = <1>; - board_sn: board_sn@0 { + board_sn: board-sn@0 { reg = <0x0 0x14>; }; - eth_mac: eth_mac@20 { + eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; - board_name: board_name@d0 { + board_name: board-name@d0 { reg = <0xd0 0x6>; }; - board_revision: board_revision@e0 { + board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 2be6eb0eb5..b7c638bc9e 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -1,19 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> #include <dt-bindings/phy/phy.h> / { @@ -52,7 +51,7 @@ sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = <108>; /* down */ + linux,code = <KEY_DOWN>; gpio-key,wakeup; autorepeat; }; @@ -70,15 +69,12 @@ &can1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; }; &dcc { status = "okay"; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -115,8 +111,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; @@ -127,8 +121,6 @@ &gpio { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_default>; }; &gpu { @@ -138,19 +130,8 @@ &i2c0 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { - /* - * Enable all GTs to out from U-Boot - * i2c mw 20 6 0 - setup IO to output - * i2c mw 20 2 ef - setup output values on pins 0-7 - * i2c mw 20 3 ff - setup output values on pins 10-17 - */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; @@ -194,7 +175,7 @@ }; }; - tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ + tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; @@ -220,12 +201,12 @@ */ }; - i2cswitch@75 { /* u60 */ + i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; - i2c@0 { /* i2c mw 75 0 1 */ + i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -281,7 +262,7 @@ shunt-resistor = <5000>; }; }; - i2c@1 { /* i2c mw 75 0 1 */ + i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -327,97 +308,85 @@ shunt-resistor = <5000>; }; }; - i2c@2 { /* i2c mw 75 0 1 */ + i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ - compatible = "max15301"; + compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ - compatible = "max15301"; + compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ - compatible = "max15301"; + compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ - compatible = "max15303"; + compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; -/* drivers/hwmon/pmbus/Kconfig:86: be called max20751. -drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o -*/ - max20751@72 { /* u95 FIXME - not detected */ - compatible = "max20751"; + max20751@72 { /* u95 */ + compatible = "maxim,max20751"; reg = <0x72>; }; - max20751@73 { /* u96 FIXME - not detected */ - compatible = "max20751"; + max20751@73 { /* u96 */ + compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; - - /* FIXME PMOD - j160 */ - /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - - /* FIXME PL i2c via PCA9306 - u45 */ - /* FIXME MSP430 - u41 - not detected */ - i2cswitch@74 { /* u34 */ + + /* PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; - i2c@0 { /* i2c mw 74 0 1 */ + i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -430,25 +399,25 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; - i2c@1 { /* i2c mw 74 0 2 */ + i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; - si5341: clock-generator1@36 { /* SI5341 - u69 */ - compatible = "si5341"; + si5341: clock-generator@36 { /* SI5341 - u69 */ + compatible = "silabs,si5341"; reg = <0x36>; }; }; - i2c@2 { /* i2c mw 74 0 4 */ + i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; - si570_1: clock-generator2@5d { /* USER SI570 - u42 */ + si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; @@ -457,11 +426,11 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o clock-frequency = <300000000>; }; }; - i2c@3 { /* i2c mw 74 0 8 */ + i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; - si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ + si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; @@ -470,11 +439,11 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o clock-frequency = <148500000>; }; }; - i2c@4 { /* i2c mw 74 0 10 */ + i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5328: clock-generator4@69 {/* SI5328 - u20 */ + si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* @@ -487,7 +456,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o /* 5 - 7 unconnected */ }; - i2cswitch@75 { + i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; @@ -511,29 +480,24 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o reg = <2>; /* SYSMON */ }; - i2c@3 { /* i2c mw 75 0 8 */ + i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ - dev@19 { /* u-boot detection */ - compatible = "xxx"; + dev@19 { reg = <0x19>; }; - dev@30 { /* u-boot detection */ - compatible = "xxx"; + dev@30 { reg = <0x30>; }; - dev@35 { /* u-boot detection */ - compatible = "xxx"; + dev@35 { reg = <0x35>; }; - dev@36 { /* u-boot detection */ - compatible = "xxx"; + dev@36 { reg = <0x36>; }; - dev@51 { /* u-boot detection - maybe SPD */ - compatible = "xxx"; + dev@51 { reg = <0x51>; }; }; @@ -564,269 +528,6 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o }; }; -&pinctrl0 { - status = "okay"; - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_3_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_3_grp"; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - }; - - pinctrl_i2c0_gpio: i2c0-gpio { - mux { - groups = "gpio0_14_grp", "gpio0_15_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_14_grp", "gpio0_15_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - mux { - groups = "i2c1_4_grp"; - function = "i2c1"; - }; - - conf { - groups = "i2c1_4_grp"; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - mux { - groups = "gpio0_16_grp", "gpio0_17_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_16_grp", "gpio0_17_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - }; - - pinctrl_uart0_default: uart0-default { - mux { - groups = "uart0_4_grp"; - function = "uart0"; - }; - - conf { - groups = "uart0_4_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO18"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO19"; - bias-disable; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_5_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_5_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO21"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO20"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - }; - - pinctrl_gem3_default: gem3-default { - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - - conf { - groups = "ethernet3_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", - "MIO75"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", - "MIO69"; - bias-disable; - low-power-enable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - bias-disable; - }; - }; - - pinctrl_can1_default: can1-default { - mux { - function = "can1"; - groups = "can1_6_grp"; - }; - - conf { - groups = "can1_6_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - conf-rx { - pins = "MIO25"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO24"; - bias-disable; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - - conf { - groups = "sdio1_0_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - bias-disable; - }; - - mux-cd { - groups = "sdio1_0_cd_grp"; - function = "sdio1_cd"; - }; - - conf-cd { - groups = "sdio1_0_cd_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - mux-wp { - groups = "sdio1_0_wp_grp"; - function = "sdio1_wp"; - }; - - conf-wp { - groups = "sdio1_0_wp_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - }; - - pinctrl_gpio_default: gpio-default { - mux-sw { - function = "gpio0"; - groups = "gpio0_22_grp", "gpio0_23_grp"; - }; - - conf-sw { - groups = "gpio0_22_grp", "gpio0_23_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - mux-msp { - function = "gpio0"; - groups = "gpio0_13_grp", "gpio0_38_grp"; - }; - - conf-msp { - groups = "gpio0_13_grp", "gpio0_38_grp"; - slew-rate = <SLEW_RATE_SLOW>; - io-standard = <IO_STANDARD_LVCMOS18>; - }; - - conf-pull-up { - pins = "MIO22", "MIO23"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO13", "MIO38"; - bias-disable; - }; - }; -}; - &pcie { status = "okay"; }; @@ -883,8 +584,6 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o /* SD1 with level shifter */ &sdhci1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ xlnx,mio_bank = <1>; }; @@ -895,21 +594,15 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o &uart0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index c771a946b2..af4d86882a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> - * - * SPDX-License-Identifier: GPL-2.0+ */ #include "zynqmp-zcu102-revA.dts" @@ -27,14 +26,12 @@ /delete-node/ phy@21; }; -/* Different qspi 512Mbit version */ - /* Fix collision with u61 */ &i2c0 { - i2cswitch@75 { + i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts new file mode 100644 index 0000000000..a0e13d8dc5 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU104 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU104 RevA"; + compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* Another connection to this bus via PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ + compatible = "idt,8t49n287"; + reg = <0x6c>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x43>; + }; + irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x4d>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + tca6416_u97: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - IRPS5401_ALERT_B + * 1 - HDMI_8T49N241_INT_ALM + * 2 - MAX6643_OT_B + * 3 - MAX6643_FANFAIL_B + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7 - FMC_LPC_PRSNT_M2C_B + * 4, 10 - 17 - not connected + */ + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + /* 3, 6 not connected */ + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; + disable-wp; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; + maximum-speed = "super-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts new file mode 100644 index 0000000000..6e3cf5a97f --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU104 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU104 RevC"; + compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - IRPS5401_ALERT_B + * 1 - HDMI_8T49N241_INT_ALM + * 2 - MAX6643_OT_B + * 3 - MAX6643_FANFAIL_B + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7 - FMC_LPC_PRSNT_M2C_B + * 4, 10 - 17 - not connected + */ + }; + + /* Another connection to this bus via PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ + compatible = "idt,8t49n287"; + reg = <0x6c>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x43>; + }; + irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x4d>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + /* 3, 6 not connected */ + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; + disable-wp; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; + maximum-speed = "super-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts new file mode 100644 index 0000000000..bbcd26031d --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU106 + * + * (C) Copyright 2016, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU106 RevA"; + compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_DOWN>; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - SFP_SI5328_INT_ALM + * 1 - HDMI_SI5328_INT_ALM + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 10 - FMC_HPC0_PRSNT_M2C_B + * 11 - FMC_HPC1_PRSNT_M2C_B + * 2-4, 7, 12-17 - not connected + */ + }; + + tca6416_u61: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - VCCPSPLL_EN + * 1 - MGTRAVCC_EN + * 2 - MGTRAVTT_EN + * 3 - VCCPSDDRPLL_EN + * 4 - MIO26_PMU_INPUT_LS + * 5 - PL_PMBUS_ALERT + * 6 - PS_PMBUS_ALERT + * 7 - MAXIM_PMBUS_ALERT + * 10 - PL_DDR4_VTERM_EN + * 11 - PL_DDR4_VPP_2V5_EN + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON + * 13 - PS_DIMM_SUSPEND_EN + * 14 - PS_DDR4_VTERM_EN + * 15 - PS_DDR4_VPP_2V5_EN + * 16 - 17 - not connected + */ + }; + + i2c-mux@75 { /* u60 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + ina226@40 { /* u76 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + ina226@41 { /* u77 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u85 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u93 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u88 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u15 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u92 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* PL_PMBUS */ + ina226@40 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u80 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u16 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* MAXIM_PMBUS - 00 */ + max15301@a { /* u46 */ + compatible = "maxim,max15301"; + reg = <0xa>; + }; + max15303@b { /* u4 */ + compatible = "maxim,max15303"; + reg = <0xb>; + }; + max15303@10 { /* u13 */ + compatible = "maxim,max15303"; + reg = <0x10>; + }; + max15301@13 { /* u47 */ + compatible = "maxim,max15301"; + reg = <0x13>; + }; + max15303@14 { /* u7 */ + compatible = "maxim,max15303"; + reg = <0x14>; + }; + max15303@15 { /* u6 */ + compatible = "maxim,max15303"; + reg = <0x15>; + }; + max15303@16 { /* u10 */ + compatible = "maxim,max15303"; + reg = <0x16>; + }; + max15303@17 { /* u9 */ + compatible = "maxim,max15303"; + reg = <0x17>; + }; + max15301@18 { /* u63 */ + compatible = "maxim,max15301"; + reg = <0x18>; + }; + max15303@1a { /* u49 */ + compatible = "maxim,max15303"; + reg = <0x1a>; + }; + max15303@1b { /* u8 */ + compatible = "maxim,max15303"; + reg = <0x1b>; + }; + max15303@1d { /* u18 */ + compatible = "maxim,max15303"; + reg = <0x1d>; + }; + + max20751@72 { /* u95 */ + compatible = "maxim,max20751"; + reg = <0x72>; + }; + max20751@73 { /* u96 */ + compatible = "maxim,max20751"; + reg = <0x73>; + }; + }; + /* Bus 3 is not connected */ + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u69 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u42 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; /* copy from zc702 */ + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; /* FAN controller */ + temp@4c {/* lm96163 - u128 */ + compatible = "national,lm96163"; + reg = <0x4c>; + }; + }; + /* 6 - 7 unconnected */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u135 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* HPC0_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* HPC1_IIC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SEP 3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SEP 2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SEP 1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SEP 0 */ + }; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts new file mode 100644 index 0000000000..4002d78806 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU111 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU111 RevA"; + compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_DOWN>; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u22: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - MAX6643_OT_B + * 1 - MAX6643_FANFAIL_B + * 2 - MIO26_PMU_INPUT_LS + * 4 - SFP_SI5382_INT_ALM + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 10 - FMCP_HSPC_PRSNT_M2C_B + * 11 - CLK_SPI_MUX_SEL0 + * 12 - CLK_SPI_MUX_SEL1 + * 16 - IRPS5401_ALERT_B + * 17 - INA226_PMBUS_ALERT + * 3, 7, 13-15 - not connected + */ + }; + + i2c-mux@75 { /* u23 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + ina226@40 { /* u67 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u59 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u61 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u60 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u64 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u69 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + ina226@47 { /* u66 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@48 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + ina226@49 { /* u63 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u3 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u71 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + ina226@4c { /* u77 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + ina226@4d { /* u73 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + ina226@4e { /* u79 */ + compatible = "ti,ina226"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x43>; + }; + irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x44>; + }; + irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x45>; + }; + /* u68 IR38064 +0 */ + /* u70 IR38060 +1 */ + /* u74 IR38060 +2 */ + /* u75 IR38060 +6 */ + /* J19 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@74 { /* u26 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u88 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u46 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 { /* SI5328 - u48 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + sc18is603@2f { /* sc18is602 - u93 */ + compatible = "nxp,sc18is603"; + reg = <0x2f>; + /* 4 gpios for CS not handled by driver */ + /* + * USB2ANY cable or + * LMK04208 - u90 or + * LMX2594 - u102 or + * LMX2594 - u103 or + * LMX2594 - u104 + */ + }; + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* FMC connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u27 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection FIXME */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 5bdab61164..80ac9a6ac7 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * @@ -5,7 +6,10 @@ * * Michal Simek <michal.simek@xilinx.com> * - * SPDX-License-Identifier: GPL-2.0+ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. */ / { @@ -98,155 +102,6 @@ u-boot,dm-pre-reloc; }; - power-domains { - compatible = "xlnx,zynqmp-genpd"; - - pd_usb0: pd-usb0 { - #power-domain-cells = <0x0>; - pd-id = <0x16>; - }; - - pd_usb1: pd-usb1 { - #power-domain-cells = <0x0>; - pd-id = <0x17>; - }; - - pd_sata: pd-sata { - #power-domain-cells = <0x0>; - pd-id = <0x1c>; - }; - - pd_spi0: pd-spi0 { - #power-domain-cells = <0x0>; - pd-id = <0x23>; - }; - - pd_spi1: pd-spi1 { - #power-domain-cells = <0x0>; - pd-id = <0x24>; - }; - - pd_uart0: pd-uart0 { - #power-domain-cells = <0x0>; - pd-id = <0x21>; - }; - - pd_uart1: pd-uart1 { - #power-domain-cells = <0x0>; - pd-id = <0x22>; - }; - - pd_eth0: pd-eth0 { - #power-domain-cells = <0x0>; - pd-id = <0x1d>; - }; - - pd_eth1: pd-eth1 { - #power-domain-cells = <0x0>; - pd-id = <0x1e>; - }; - - pd_eth2: pd-eth2 { - #power-domain-cells = <0x0>; - pd-id = <0x1f>; - }; - - pd_eth3: pd-eth3 { - #power-domain-cells = <0x0>; - pd-id = <0x20>; - }; - - pd_i2c0: pd-i2c0 { - #power-domain-cells = <0x0>; - pd-id = <0x25>; - }; - - pd_i2c1: pd-i2c1 { - #power-domain-cells = <0x0>; - pd-id = <0x26>; - }; - - pd_dp: pd-dp { - #power-domain-cells = <0x0>; - pd-id = <0x29>; - }; - - pd_gdma: pd-gdma { - #power-domain-cells = <0x0>; - pd-id = <0x2a>; - }; - - pd_adma: pd-adma { - #power-domain-cells = <0x0>; - pd-id = <0x2b>; - }; - - pd_ttc0: pd-ttc0 { - #power-domain-cells = <0x0>; - pd-id = <0x18>; - }; - - pd_ttc1: pd-ttc1 { - #power-domain-cells = <0x0>; - pd-id = <0x19>; - }; - - pd_ttc2: pd-ttc2 { - #power-domain-cells = <0x0>; - pd-id = <0x1a>; - }; - - pd_ttc3: pd-ttc3 { - #power-domain-cells = <0x0>; - pd-id = <0x1b>; - }; - - pd_sd0: pd-sd0 { - #power-domain-cells = <0x0>; - pd-id = <0x27>; - }; - - pd_sd1: pd-sd1 { - #power-domain-cells = <0x0>; - pd-id = <0x28>; - }; - - pd_nand: pd-nand { - #power-domain-cells = <0x0>; - pd-id = <0x2c>; - }; - - pd_qspi: pd-qspi { - #power-domain-cells = <0x0>; - pd-id = <0x2d>; - }; - - pd_gpio: pd-gpio { - #power-domain-cells = <0x0>; - pd-id = <0x2e>; - }; - - pd_can0: pd-can0 { - #power-domain-cells = <0x0>; - pd-id = <0x2f>; - }; - - pd_can1: pd-can1 { - #power-domain-cells = <0x0>; - pd-id = <0x30>; - }; - - pd_pcie: pd-pcie { - #power-domain-cells = <0x0>; - pd-id = <0x3b>; - }; - - pd_gpu: pd-gpu { - #power-domain-cells = <0x0>; - pd-id = <0x3a 0x14 0x15>; - }; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; @@ -390,7 +245,6 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <&pd_can0>; }; can1: can@ff070000 { @@ -402,7 +256,6 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { @@ -435,7 +288,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; - power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { @@ -448,7 +300,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; - power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { @@ -461,7 +312,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; - power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { @@ -474,7 +324,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; - power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { @@ -487,7 +336,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; - power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { @@ -500,7 +348,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; - power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { @@ -513,7 +360,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; - power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { @@ -526,7 +372,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; - power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { @@ -537,7 +382,6 @@ interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; - power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable @@ -547,105 +391,97 @@ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; - power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; - power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; - power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; - power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; - power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; - power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; - power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; - power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { @@ -666,7 +502,6 @@ #size-cells = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; - power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { @@ -680,7 +515,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; - power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { @@ -694,7 +528,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; - power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { @@ -708,7 +541,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; - power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { @@ -722,7 +554,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; - power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { @@ -735,7 +566,6 @@ #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; - power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { @@ -746,7 +576,6 @@ reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { @@ -757,7 +586,6 @@ reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { @@ -781,7 +609,8 @@ <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ - interrupt-names = "misc","dummy","intx", "msi1", "msi0"; + interrupt-names = "misc", "dummy", "intx", + "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, @@ -795,7 +624,6 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; @@ -817,7 +645,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; - power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { @@ -867,7 +694,6 @@ reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; - power-domains = <&pd_sata>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; @@ -885,7 +711,6 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; - power-domains = <&pd_sd0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; @@ -901,7 +726,6 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; - power-domains = <&pd_sd1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; @@ -935,7 +759,6 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { @@ -947,7 +770,6 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { @@ -957,7 +779,6 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { @@ -967,7 +788,6 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { @@ -977,7 +797,6 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { @@ -987,7 +806,6 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { @@ -998,7 +816,6 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; - power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { @@ -1009,7 +826,6 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; - power-domains = <&pd_uart1>; }; usb0: usb0@ff9d0000 { @@ -1019,7 +835,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -1045,7 +860,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -1106,7 +920,6 @@ interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; - power-domains = <&pd_dp>; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; @@ -1129,7 +942,6 @@ xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; - power-domains = <&pd_dp>; }; xlnx_dpdma: dma@fd4c0000 { @@ -1139,7 +951,6 @@ interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; - power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8513406a8e..095eb74195 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -232,7 +232,11 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) +#if defined(CONFIG_MX6UL) +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#else #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) +#endif #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) #define CONFIG_SYS_FSL_SEC_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 3726f02af5..0cdb508d12 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -264,6 +264,8 @@ struct src { u32 ddrc_rcr; }; +#define src_base ((struct src *)SRC_BASE_ADDR) + #define SRC_M4_REG_OFFSET 0xC #define SRC_M4C_NON_SCLR_RST_OFFSET 0 #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index ad3dc9aba5..3daf0e81d8 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -14,6 +14,8 @@ #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D #define KEY_PTR_LEN 32 +#define ZYNQMP_FPGA_BIT_NS 5 + enum { IDCODE, VERSION, diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 96795e1814..aa51c0d786 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -107,6 +107,7 @@ void set_chipselect_size(int const); void init_aips(void); void init_src(void); +void init_snvs(void); void imx_wdog_disable_powerdown(void); int board_mmc_get_env_dev(int devno); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index b5ffffd4e3..3d3085e917 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -41,8 +41,8 @@ obj-$(CONFIG_SPL_FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif -obj-$(CONFIG_$(SPL_)USE_ARCH_MEMSET) += memset.o -obj-$(CONFIG_$(SPL_)USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o +obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o obj-$(CONFIG_SEMIHOSTING) += semihosting.o obj-y += sections.o diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index cfc236f964..91a64bec34 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -448,6 +448,11 @@ void boot_prep_vxworks(bootm_headers_t *images) } void boot_jump_vxworks(bootm_headers_t *images) { +#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI) + armv8_setup_psci(); + smp_kick_all_cpus(); +#endif + /* ARM VxWorks requires device tree physical address to be passed */ ((void (*)(void *))images->ep)(images->ft_addr); } diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 80869adb61..cda4d48460 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -20,6 +20,7 @@ */ #include <common.h> +#include <efi_loader.h> #include <asm/proc-armv/ptrace.h> #include <asm/u-boot-arm.h> #include <efi_loader.h> @@ -51,6 +52,11 @@ void bad_mode (void) reset_cpu (0); } +static void show_efi_loaded_images(struct pt_regs *regs) +{ + efi_print_image_infos((void *)instruction_pointer(regs)); +} + void show_regs (struct pt_regs *regs) { unsigned long __maybe_unused flags; @@ -106,6 +112,7 @@ void do_undefined_instruction (struct pt_regs *pt_regs) printf ("undefined instruction\n"); fixup_pc(pt_regs, -4); show_regs (pt_regs); + show_efi_loaded_images(pt_regs); bad_mode (); } @@ -115,6 +122,7 @@ void do_software_interrupt (struct pt_regs *pt_regs) printf ("software interrupt\n"); fixup_pc(pt_regs, -4); show_regs (pt_regs); + show_efi_loaded_images(pt_regs); bad_mode (); } @@ -124,6 +132,7 @@ void do_prefetch_abort (struct pt_regs *pt_regs) printf ("prefetch abort\n"); fixup_pc(pt_regs, -8); show_regs (pt_regs); + show_efi_loaded_images(pt_regs); bad_mode (); } @@ -133,6 +142,7 @@ void do_data_abort (struct pt_regs *pt_regs) printf ("data abort\n"); fixup_pc(pt_regs, -8); show_regs (pt_regs); + show_efi_loaded_images(pt_regs); bad_mode (); } @@ -142,6 +152,7 @@ void do_not_used (struct pt_regs *pt_regs) printf ("not used\n"); fixup_pc(pt_regs, -8); show_regs (pt_regs); + show_efi_loaded_images(pt_regs); bad_mode (); } @@ -151,6 +162,7 @@ void do_fiq (struct pt_regs *pt_regs) printf ("fast interrupt request\n"); fixup_pc(pt_regs, -8); show_regs (pt_regs); + show_efi_loaded_images(pt_regs); bad_mode (); } @@ -160,5 +172,6 @@ void do_irq (struct pt_regs *pt_regs) printf ("interrupt request\n"); fixup_pc(pt_regs, -8); show_regs (pt_regs); + show_efi_loaded_images(pt_regs); bad_mode (); } diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index b62cb8a51e..aa02d3f9f6 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -63,6 +63,7 @@ void __efi_runtime EFIAPI efi_reset_system( switch (reset_type) { case EFI_RESET_COLD: case EFI_RESET_WARM: + case EFI_RESET_PLATFORM_SPECIFIC: reset_cpu(0); break; case EFI_RESET_SHUTDOWN: @@ -82,9 +83,9 @@ void __efi_runtime EFIAPI efi_reset_system( while (1) { } } -void efi_reset_system_init(void) +efi_status_t efi_reset_system_init(void) { - efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs)); + return efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs)); } #endif diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 461ff778c2..7b9d9619bb 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <environment.h> #include <i2c.h> #include <net.h> #include <asm/arch/hardware.h> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 95a542fa01..306f779392 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -78,9 +78,11 @@ endif quiet_cmd_cpp_cfg = CFGS $@ cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $< -IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%).cfgtmp +# mkimage source config file +IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%) -$(IMX_CONFIG): %.cfgtmp: % FORCE +# How to create a cpp processed config file, they all use the same source +%.cfgout: $(IMX_CONFIG) FORCE $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cpp_cfg) @@ -88,7 +90,7 @@ MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imxim -e $(CONFIG_SYS_TEXT_BASE) u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log -u-boot.imx: u-boot.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) ifeq ($(CONFIG_OF_SEPARATE),y) @@ -96,16 +98,15 @@ MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T i -e $(CONFIG_SYS_TEXT_BASE) u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log -u-boot-dtb.imx: u-boot-dtb.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) endif MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) -T imximage \ -e $(CONFIG_SPL_TEXT_BASE) - SPL: MKIMAGEOUTPUT = SPL.log -SPL: spl/u-boot-spl.bin $(IMX_CONFIG) $(PLUGIN).bin FORCE +SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) MKIMAGEFLAGS_u-boot.uim = -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \ @@ -133,7 +134,7 @@ cmd_u-boot-nand-spl_imx = (printf '\000\000\000\000\106\103\102\040\001' && \ spl/u-boot-nand-spl.imx: SPL FORCE $(call if_changed,u-boot-nand-spl_imx) -targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-spl.imx) +targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx) obj-$(CONFIG_ARM64) += sip.o diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index c730c8f7a9..9ca7badcaf 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -341,6 +341,31 @@ static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc, return 0; } +static int do_authenticate_image_or_failover(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + int ret = CMD_RET_FAILURE; + + if (argc != 4) { + ret = CMD_RET_USAGE; + goto error; + } + + if (!imx_hab_is_enabled()) { + printf("error: secure boot disabled\n"); + goto error; + } + + if (do_authenticate_image(NULL, flag, argc, argv) != CMD_RET_SUCCESS) { + fprintf(stderr, "authentication fail -> %s %s %s %s\n", + argv[0], argv[1], argv[2], argv[3]); + do_hab_failsafe(0, 0, 1, NULL); + }; + ret = CMD_RET_SUCCESS; +error: + return ret; +} + U_BOOT_CMD( hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, "display HAB status", @@ -362,6 +387,16 @@ U_BOOT_CMD( "" ); +U_BOOT_CMD( + hab_auth_img_or_fail, 4, 0, + do_authenticate_image_or_failover, + "authenticate image via HAB on failure drop to USB BootROM mode", + "addr length ivt_offset\n" + "addr - image hex address\n" + "length - image hex length\n" + "ivt_offset - hex offset of IVT in the image" + ); + #endif /* !defined(CONFIG_SPL_BUILD) */ /* Get CSF Header length */ diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d4ce38db8d..aa6f5facbf 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -387,6 +387,16 @@ config TARGET_TBS2910 config TARGET_TITANIUM bool "titanium" +config TARGET_KP_IMX6Q_TPC + bool "K+P KP_IMX6Q_TPC i.MX6 Quad" + select MX6QDL + select BOARD_LATE_INIT + select BOARD_EARLY_INIT_F + select SUPPORT_SPL + select DM + select DM_THERMAL + imply CMD_SPL + config TARGET_TQMA6 bool "TQ Systems TQMa6 board" select BOARD_LATE_INIT @@ -493,6 +503,7 @@ source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" +source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 43b77cfa41..6e5e40dd1a 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -85,6 +85,23 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) writel(val_ctrl, reg_ctrl); } +static void correct_mpwldectr_result(void *reg) +{ + /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */ + const unsigned int limit = 0x148; + u32 val = readl(reg); + u32 old = val; + + if ((val & 0x17f) > limit) + val &= 0xffff << 16; + + if (((val >> 16) & 0x17f) > limit) + val &= 0xffff; + + if (old != val) + writel(val, reg); +} + int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) { struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; @@ -176,6 +193,13 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) errors |= 4; } + correct_mpwldectr_result(&mmdc0->mpwldectrl0); + correct_mpwldectr_result(&mmdc0->mpwldectrl1); + if (sysinfo->dsize == 2) { + correct_mpwldectr_result(&mmdc1->mpwldectrl0); + correct_mpwldectr_result(&mmdc1->mpwldectrl1); + } + /* * User should issue MRS command to exit write leveling mode * through Load Mode Register command diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index ce289c1415..e6bef6acee 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -5,7 +5,7 @@ # # -obj-y := soc.o clock.o clock_slice.o ddr.o +obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o ifdef CONFIG_ARMV7_PSCI obj-y += psci-mx7.o psci.o diff --git a/arch/arm/mach-imx/mx7/snvs.c b/arch/arm/mach-imx/mx7/snvs.c new file mode 100644 index 0000000000..7e649b8513 --- /dev/null +++ b/arch/arm/mach-imx/mx7/snvs.c @@ -0,0 +1,22 @@ +/* + * Copyright 2018 Linaro + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <linux/bitops.h> + +#define SNVS_HPCOMR 0x04 +#define SNVS_HPCOMR_NPSWA_EN BIT(31) + +void init_snvs(void) +{ + u32 val; + + /* Ensure SNVS HPCOMR sets NPSWA_EN to allow unpriv access to SNVS LP */ + val = readl(SNVS_BASE_ADDR + SNVS_HPCOMR); + val |= SNVS_HPCOMR_NPSWA_EN; + writel(val, SNVS_BASE_ADDR + SNVS_HPCOMR); +} diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index d349676b81..3ceeeffd99 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -18,6 +18,7 @@ #include <dm.h> #include <imx_thermal.h> #include <fsl_sec.h> +#include <asm/setup.h> #if defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx7_thermal_plat = { @@ -179,6 +180,8 @@ int arch_cpu_init(void) isolate_resource(); #endif + init_snvs(); + return 0; } @@ -201,6 +204,27 @@ int arch_misc_init(void) #endif #ifdef CONFIG_SERIAL_TAG +/* + * OCOTP_TESTER + * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 + * OCOTP_TESTER describes a unique ID based on silicon wafer + * and die X/Y position + * + * OCOTOP_TESTER offset 0x410 + * 31:0 fuse 0 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID + * + * OCOTP_TESTER1 offset 0x420 + * 31:24 fuse 1 + * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID + * 23:16 fuse 1 + * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID + * 15:11 fuse 1 + * The wafer number of the wafer on which the device was fabricated/SJC + * CHALLENGE/ Unique ID + * 10:0 fuse 1 + * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID + */ void get_board_serial(struct tag_serialnr *serialnr) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index b2521b2101..6fc24630ba 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -101,6 +101,29 @@ u32 spl_boot_device(void) /* Translate iMX7/MX8M boot device to the SPL boot device enumeration */ u32 spl_boot_device(void) { +#if defined(CONFIG_MX7) + unsigned int bmode = readl(&src_base->sbmr2); + + /* + * Check for BMODE if serial downloader is enabled + * BOOT_MODE - see IMX7DRM Table 6-24 + */ + if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */ + return BOOT_DEVICE_BOARD; + + /* + * The above method does not detect that the boot ROM used + * serial downloader in case the boot ROM decided to use the + * serial downloader as a fall back (primary boot source failed). + * + * Infer that the boot ROM used the USB serial downloader by + * checking whether the USB PHY is currently active... This + * assumes that SPL did not (yet) initialize the USB PHY... + */ + if (is_boot_from_usb()) + return BOOT_DEVICE_BOARD; +#endif + enum boot_device boot_device_spl = get_boot_device(); switch (boot_device_spl) { diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 7d1ca274bf..1d3962500d 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <environment.h> #include <asm/setup.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index a96938c01e..a8835f6571 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -47,6 +47,9 @@ config TARGET_KOELSCH bool "Koelsch board" select DM select DM_SERIAL + select SUPPORT_SPL + select USE_TINY_PRINTF + select SPL_TINY_MEMSET config TARGET_LAGER bool "Lager board" @@ -65,18 +68,25 @@ config TARGET_SILK bool "Silk board" select DM select DM_SERIAL + select SUPPORT_SPL + select USE_TINY_PRINTF + select SPL_TINY_MEMSET config TARGET_PORTER bool "Porter board" select DM select DM_SERIAL select SUPPORT_SPL - select SPL_DM if SPL + select USE_TINY_PRINTF + select SPL_TINY_MEMSET config TARGET_STOUT bool "Stout board" select DM select DM_SERIAL + select SUPPORT_SPL + select USE_TINY_PRINTF + select SPL_TINY_MEMSET endchoice diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index ba87d21b73..ce15741c41 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -18,9 +18,6 @@ int arch_cpu_init(void) #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { -#if defined(CONFIG_RCAR_GEN3) - rcar_gen3_memmap_fixup(); -#endif dcache_enable(); } #endif diff --git a/arch/arm/mach-rmobile/include/mach/boot0.h b/arch/arm/mach-rmobile/include/mach/boot0.h new file mode 100644 index 0000000000..61044698bf --- /dev/null +++ b/arch/arm/mach-rmobile/include/mach/boot0.h @@ -0,0 +1,24 @@ +/* + * Specialty padding for the RCar Gen2 SPL JTAG loading + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __BOOT0_H +#define __BOOT0_H + +_start: + ARM_VECTORS + +#ifdef CONFIG_SPL_BUILD + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; + .word 0x0badc0d3; +#endif + +#endif /* __BOOT0_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index ff0ca63f02..94ea366f45 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -41,7 +41,6 @@ u32 rmobile_get_cpu_type(void); u32 rmobile_get_cpu_rev_integer(void); u32 rmobile_get_cpu_rev_fraction(void); -void rcar_gen3_memmap_fixup(void); #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/mach-rmobile/lowlevel_init_ca15.S b/arch/arm/mach-rmobile/lowlevel_init_ca15.S index a5dbbea9e1..806a3bc2f9 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_ca15.S +++ b/arch/arm/mach-rmobile/lowlevel_init_ca15.S @@ -11,6 +11,7 @@ #include <linux/linkage.h> ENTRY(lowlevel_init) +#ifndef CONFIG_SPL_BUILD mrc p15, 0, r4, c0, c0, 5 /* mpidr */ orr r4, r4, r4, lsr #6 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ @@ -83,6 +84,7 @@ _exit_init_l2_a15: bl s_init ldr lr, [sp] +#endif mov pc, lr nop ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c index 801e392425..52cd000a17 100644 --- a/arch/arm/mach-rmobile/memmap-gen3.c +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -9,77 +9,24 @@ #include <common.h> #include <asm/armv8/mmu.h> -static struct mm_region r8a7795_mem_map[] = { +static struct mm_region gen3_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -static struct mm_region r8a7796_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe0000000UL, - .phys = 0xe0000000UL, - .size = 0xe0000000UL, + .size = 0x40000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - /* List terminator */ - 0, - } -}; - -static struct mm_region r8a77970_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe0000000UL, - .phys = 0xe0000000UL, - .size = 0xe0000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -static struct mm_region r8a77995_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0xe0000000UL, + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .virt = 0xe0000000UL, - .phys = 0xe0000000UL, - .size = 0xe0000000UL, + .virt = 0xc0000000UL, + .phys = 0xc0000000UL, + .size = 0x40000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -89,25 +36,4 @@ static struct mm_region r8a77995_mem_map[] = { } }; -struct mm_region *mem_map = r8a7795_mem_map; - -void rcar_gen3_memmap_fixup(void) -{ - u32 cpu_type = rmobile_get_cpu_type(); - - switch (cpu_type) { - case RMOBILE_CPU_TYPE_R8A7795: - mem_map = r8a7795_mem_map; - break; - case RMOBILE_CPU_TYPE_R8A7796: - case RMOBILE_CPU_TYPE_R8A77965: - mem_map = r8a7796_mem_map; - break; - case RMOBILE_CPU_TYPE_R8A77970: - mem_map = r8a77970_mem_map; - break; - case RMOBILE_CPU_TYPE_R8A77995: - mem_map = r8a77995_mem_map; - break; - } -} +struct mm_region *mem_map = gen3_mem_map; diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file mode 100644 index 0000000000..7052804921 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ +#define _SOCFPGA_S10_BASE_HARDWARE_H_ + +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 +#define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_SMMU_ADDRESS 0xfa000000 +#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc02100 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000 +#define GICD_BASE 0xfffc1000 +#define GICC_BASE 0xfffc2000 + +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 87729047f9..1352359438 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -36,6 +36,7 @@ config ZYNQ_DDRC_INIT want to skip ddr init and this option is useful for it. config SYS_BOARD + string "Board name" default "zynq" config SYS_VENDOR diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 1369cd095b..3c27038630 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -94,7 +94,8 @@ int soc_clk_dump(void) clk_free(&clk); - if (rate == (unsigned long)-ENOSYS) + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO)) printf("%10s%20s\n", name, "unknown"); else printf("%10s%20lu\n", name, rate); diff --git a/arch/arm/mach-zynq/include/mach/nand.h b/arch/arm/mach-zynq/include/mach/nand.h deleted file mode 100644 index 61ef45f582..0000000000 --- a/arch/arm/mach-zynq/include/mach/nand.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (C) 2017 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <nand.h> - -void zynq_nand_init(void); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index e1fee11540..3bdaa5fe7b 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <environment.h> #include <linux/libfdt.h> #include <fdt_support.h> #include <asm/processor.h> diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h index 9dc6c8184b..01b5ba4e07 100644 --- a/arch/sandbox/include/asm/clk.h +++ b/arch/sandbox/include/asm/clk.h @@ -64,6 +64,14 @@ int sandbox_clk_query_enable(struct udevice *dev, int id); */ int sandbox_clk_test_get(struct udevice *dev); /** + * sandbox_clk_test_get_bulk - Ask the sandbox clock test device to request its + * clocks with the bulk clk API. + * + * @dev: The sandbox clock test (client) devivce. + * @return: 0 if OK, or a negative error code. + */ +int sandbox_clk_test_get_bulk(struct udevice *dev); +/** * sandbox_clk_test_get_rate - Ask the sandbox clock test device to query a * clock's rate. * @@ -91,6 +99,14 @@ ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate); */ int sandbox_clk_test_enable(struct udevice *dev, int id); /** + * sandbox_clk_test_enable_bulk - Ask the sandbox clock test device to enable + * all clocks in it's clock bulk struct. + * + * @dev: The sandbox clock test (client) devivce. + * @return: 0 if OK, or a negative error code. + */ +int sandbox_clk_test_enable_bulk(struct udevice *dev); +/** * sandbox_clk_test_disable - Ask the sandbox clock test device to disable a * clock. * @@ -100,6 +116,14 @@ int sandbox_clk_test_enable(struct udevice *dev, int id); */ int sandbox_clk_test_disable(struct udevice *dev, int id); /** + * sandbox_clk_test_disable_bulk - Ask the sandbox clock test device to disable + * all clocks in it's clock bulk struct. + * + * @dev: The sandbox clock test (client) devivce. + * @return: 0 if OK, or a negative error code. + */ +int sandbox_clk_test_disable_bulk(struct udevice *dev); +/** * sandbox_clk_test_free - Ask the sandbox clock test device to free its * clocks. * @@ -107,5 +131,13 @@ int sandbox_clk_test_disable(struct udevice *dev, int id); * @return: 0 if OK, or a negative error code. */ int sandbox_clk_test_free(struct udevice *dev); +/** + * sandbox_clk_test_release_bulk - Ask the sandbox clock test device to release + * all clocks in it's clock bulk struct. + * + * @dev: The sandbox clock test (client) devivce. + * @return: 0 if OK, or a negative error code. + */ +int sandbox_clk_test_release_bulk(struct udevice *dev); #endif diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h index 7146aa5ab2..0cd7702b88 100644 --- a/arch/sandbox/include/asm/reset.h +++ b/arch/sandbox/include/asm/reset.h @@ -14,8 +14,12 @@ struct udevice; int sandbox_reset_query(struct udevice *dev, unsigned long id); int sandbox_reset_test_get(struct udevice *dev); +int sandbox_reset_test_get_bulk(struct udevice *dev); int sandbox_reset_test_assert(struct udevice *dev); +int sandbox_reset_test_assert_bulk(struct udevice *dev); int sandbox_reset_test_deassert(struct udevice *dev); +int sandbox_reset_test_deassert_bulk(struct udevice *dev); int sandbox_reset_test_free(struct udevice *dev); +int sandbox_reset_test_release_bulk(struct udevice *dev); #endif diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 472ada5490..69074f4711 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -94,12 +94,16 @@ ifneq ($(CONFIG_EFI_STUB_64BIT),) EFI_LDS := elf_x86_64_efi.lds EFI_CRT0 := crt0_x86_64_efi.o EFI_RELOC := reloc_x86_64_efi.o -EFI_TARGET := --target=efi-app-ia32 else EFI_LDS := elf_ia32_efi.lds EFI_CRT0 := crt0_ia32_efi.o EFI_RELOC := reloc_ia32_efi.o +endif + +ifdef CONFIG_X86_64 EFI_TARGET := --target=efi-app-x86_64 +else +EFI_TARGET := --target=efi-app-ia32 endif endif diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 82407affaf..885fc6f5f2 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -12,12 +12,13 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) { - unsigned num_entries; + unsigned int num_entries; int i; - num_entries = min((unsigned)lib_sysinfo.n_memranges, max_entries); + num_entries = min((unsigned int)lib_sysinfo.n_memranges, max_entries); if (num_entries < lib_sysinfo.n_memranges) { printf("Warning: Limiting e820 map to %d entries.\n", num_entries); diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c index c1c9b89def..ec733cb038 100644 --- a/arch/x86/cpu/qemu/e820.c +++ b/arch/x86/cpu/qemu/e820.c @@ -9,7 +9,8 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) { entries[0].addr = 0; entries[0].size = ISA_START_ADDRESS; diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index eae8d785df..f5f412a1e5 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -99,7 +99,8 @@ static struct sfi_table_simple *sfi_search_mmap(void) i < SFI_GET_NUM_ENTRIES(sb, struct sfi_mem_entry); \ i++, mentry++) \ -static unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries) +static unsigned int sfi_setup_e820(unsigned int max_entries, + struct e820_entry *entries) { struct sfi_table_simple *sb; struct sfi_mem_entry *mentry; @@ -188,7 +189,8 @@ static phys_size_t sfi_get_ram_size(void) return ram; } -unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) { return sfi_setup_e820(max_entries, entries); } diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index 6aba614361..0386cbeca5 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -111,7 +111,7 @@ struct boot_params { struct setup_header hdr; /* setup header */ /* 0x1f1 */ __u8 _pad7[0x290-0x1f1-sizeof(struct setup_header)]; __u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX]; /* 0x290 */ - struct e820entry e820_map[E820MAX]; /* 0x2d0 */ + struct e820_entry e820_map[E820MAX]; /* 0x2d0 */ __u8 _pad8[48]; /* 0xcd0 */ struct edd_info eddbuf[EDDMAXNR]; /* 0xd00 */ __u8 _pad9[276]; /* 0xeec */ diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 351f02107e..9d29f82f97 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -12,7 +12,7 @@ #ifndef __ASSEMBLY__ #include <linux/types.h> -struct e820entry { +struct e820_entry { __u64 addr; /* start of memory segment */ __u64 size; /* size of memory segment */ __u32 type; /* type of memory segment */ @@ -24,6 +24,7 @@ struct e820entry { #endif /* __ASSEMBLY__ */ /* Implementation defined function to install an e820 map */ -unsigned install_e820_map(unsigned max_entries, struct e820entry *); +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *); #endif /* _ASM_X86_E820_H */ diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 263dd8fd17..d1aaa5fc78 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -61,49 +61,53 @@ #define readb(addr) (*(volatile unsigned char *) (addr)) #define readw(addr) (*(volatile unsigned short *) (addr)) #define readl(addr) (*(volatile unsigned int *) (addr)) +#define readq(addr) (*(volatile unsigned long long *) (addr)) #define __raw_readb readb #define __raw_readw readw #define __raw_readl readl +#define __raw_readq readq #define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b)) #define writew(b,addr) (*(volatile unsigned short *) (addr) = (b)) #define writel(b,addr) (*(volatile unsigned int *) (addr) = (b)) +#define writeq(b,addr) (*(volatile unsigned long long *) (addr) = (b)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel +#define __raw_writeq writeq #define memset_io(a,b,c) memset((a),(b),(c)) #define memcpy_fromio(a,b,c) memcpy((a),(b),(c)) #define memcpy_toio(a,b,c) memcpy((a),(b),(c)) -#define write_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) -#define read_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) +#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) +#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) -#define write_le64(a, v) write_arch(q, le64, a, v) -#define write_le32(a, v) write_arch(l, le32, a, v) -#define write_le16(a, v) write_arch(w, le16, a, v) +#define out_le64(a, v) out_arch(q, le64, a, v) +#define out_le32(a, v) out_arch(l, le32, a, v) +#define out_le16(a, v) out_arch(w, le16, a, v) -#define read_le64(a) read_arch(q, le64, a) -#define read_le32(a) read_arch(l, le32, a) -#define read_le16(a) read_arch(w, le16, a) +#define in_le64(a) in_arch(q, le64, a) +#define in_le32(a) in_arch(l, le32, a) +#define in_le16(a) in_arch(w, le16, a) -#define write_be32(a, v) write_arch(l, be32, a, v) -#define write_be16(a, v) write_arch(w, be16, a, v) +#define out_be32(a, v) out_arch(l, be32, a, v) +#define out_be16(a, v) out_arch(w, be16, a, v) -#define read_be32(a) read_arch(l, be32, a) -#define read_be16(a) read_arch(w, be16, a) +#define in_be32(a) in_arch(l, be32, a) +#define in_be16(a) in_arch(w, be16, a) -#define write_8(a, v) __raw_writeb(v, a) -#define read_8(a) __raw_readb(a) +#define out_8(a, v) __raw_writeb(v, a) +#define in_8(a) __raw_readb(a) #define clrbits(type, addr, clear) \ - write_##type((addr), read_##type(addr) & ~(clear)) + out_##type((addr), in_##type(addr) & ~(clear)) #define setbits(type, addr, set) \ - write_##type((addr), read_##type(addr) | (set)) + out_##type((addr), in_##type(addr) | (set)) #define clrsetbits(type, addr, clear, set) \ - write_##type((addr), (read_##type(addr) & ~(clear)) | (set)) + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) #define clrbits_be32(addr, clear) clrbits(be32, addr, clear) #define setbits_be32(addr, set) setbits(be32, addr, set) diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 66d7629a6d..f9092fdc65 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -185,6 +185,7 @@ static void setup_realmode_idt(void) write_idt_stub((void *)0xffe6e, 0x1a); } +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE static u8 vbe_get_mode_info(struct vbe_mode_info *mi) { u16 buffer_seg; @@ -241,6 +242,7 @@ static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) mode_info->video_mode &= 0x3ff; vbe_set_mode(mode_info); } +#endif /* CONFIG_FRAMEBUFFER_SET_VESA_MODE */ void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode, struct vbe_mode_info *mode_info) @@ -273,8 +275,10 @@ void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode, 0x0); debug("done\n"); +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE if (vesa_mode != -1) vbe_set_graphics(vesa_mode, mode_info); +#endif } asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses, diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index b1b4cd9613..5e0edd3214 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -100,7 +100,7 @@ void write_coreboot_table(u32 addr, struct memory_area *cfg_tables) struct cb_record *cbr; struct cb_memory *mem; struct cb_memory_range *map; - struct e820entry e820[32]; + struct e820_entry e820[32]; struct cb_framebuffer *fb; struct vesa_mode_info *vesa; int i, num; diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index 5babfde268..84c8fab189 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; * 0x100000-gd->ram_size Useable RAM * CONFIG_PCIE_ECAM_BASE PCIe ECAM */ -__weak unsigned install_e820_map(unsigned max_entries, - struct e820entry *entries) +__weak unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) { entries[0].addr = 0; entries[0].size = ISA_START_ADDRESS; diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 1a7af576d5..662d4ace21 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -62,9 +62,10 @@ ulong board_get_usable_ram_top(ulong total_size) return fsp_get_usable_lowmem_top(gd->arch.hob_list); } -unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) { - unsigned num_entries = 0; + unsigned int num_entries = 0; const struct hob_header *hdr; struct hob_res_desc *res_desc; diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index d82b8cdfe2..f0a97faa95 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -11,6 +11,7 @@ */ #include <version.h> #include <common.h> +#include <environment.h> #include <errno.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index b03c0a3714..c693aaef63 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <i2c.h> #include <miiphy.h> #include <netdev.h> diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index f639a37d4d..3e070d2b01 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> +#include <environment.h> #include <i2c.h> #include <asm/mach-types.h> #include <asm/arch/cpu.h> diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 52f36644a3..3bd9fa9633 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> +#include <environment.h> #include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> diff --git a/board/amlogic/khadas-vim/khadas-vim.c b/board/amlogic/khadas-vim/khadas-vim.c index 5e198569db..83b1b6ed6f 100644 --- a/board/amlogic/khadas-vim/khadas-vim.c +++ b/board/amlogic/khadas-vim/khadas-vim.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/mem.h> diff --git a/board/amlogic/libretech-cc/libretech-cc.c b/board/amlogic/libretech-cc/libretech-cc.c index 6be6e2ae93..57953404fe 100644 --- a/board/amlogic/libretech-cc/libretech-cc.c +++ b/board/amlogic/libretech-cc/libretech-cc.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/sm.h> diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index 0cb571432f..8645f22e87 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/sm.h> diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c index 5fde53438e..7c0abbcc0a 100644 --- a/board/amlogic/p212/p212.c +++ b/board/amlogic/p212/p212.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/sm.h> diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c index b143e04097..9cd0ec8ea0 100644 --- a/board/armltd/vexpress/vexpress_tc2.c +++ b/board/armltd/vexpress/vexpress_tc2.c @@ -18,7 +18,7 @@ bool armv7_boot_nonsec_default(void) { #ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT - return false + return false; #else /* * The Serial Configuration Controller (SCC) register at address 0x700 diff --git a/board/atmel/common/mac_eeprom.c b/board/atmel/common/mac_eeprom.c index 60ddf00d45..91b86e0c62 100644 --- a/board/atmel/common/mac_eeprom.c +++ b/board/atmel/common/mac_eeprom.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <i2c_eeprom.h> #include <netdev.h> diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 2d01ac25d8..8ae420740d 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <net.h> #include <malloc.h> #include <netdev.h> diff --git a/board/compulab/cl-som-am57x/eth.c b/board/compulab/cl-som-am57x/eth.c index b615fb9e7e..9f9525eeb0 100644 --- a/board/compulab/cl-som-am57x/eth.c +++ b/board/compulab/cl-som-am57x/eth.c @@ -10,6 +10,7 @@ #include <common.h> #include <cpsw.h> +#include <environment.h> #include <miiphy.h> #include <asm/gpio.h> #include <asm/arch/sys_proto.h> diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index f8b1cda5bb..dfa81f5221 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <mmc.h> #include <phy.h> #include <netdev.h> diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 673de03071..c72efc5964 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -12,6 +12,7 @@ #include <ahci.h> #include <dm.h> #include <dwc_ahsata.h> +#include <environment.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <mtd_node.h> diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c index 6f6ba49af5..6eabd38375 100644 --- a/board/compulab/cm_t335/cm_t335.c +++ b/board/compulab/cm_t335/cm_t335.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <errno.h> #include <miiphy.h> #include <cpsw.h> diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index d5cfba4270..e8f604f5db 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -13,6 +13,7 @@ */ #include <common.h> +#include <environment.h> #include <status_led.h> #include <netdev.h> #include <net.h> diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c index 0ff49dcdcc..e4e346077c 100644 --- a/board/compulab/cm_t3517/cm_t3517.c +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <environment.h> #include <status_led.h> #include <net.h> #include <netdev.h> diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index 3e6235a3b7..a1aeafbafd 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <fdt_support.h> #include <usb.h> #include <mmc.h> diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS index 2736aa0282..188906b080 100644 --- a/board/coreboot/coreboot/MAINTAINERS +++ b/board/coreboot/coreboot/MAINTAINERS @@ -3,4 +3,4 @@ M: Simon Glass <sjg@chromium.org> S: Maintained F: board/coreboot/coreboot/ F: include/configs/chromebook_link.h -F: configs/coreboot-x86_defconfig +F: configs/coreboot_defconfig diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 83c9f2940f..37a0d72fe1 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <environment.h> #include <i2c.h> #include <net.h> #include <netdev.h> diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index b00d0e4b6d..1d8b831054 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -19,6 +19,7 @@ #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/sata.h> +#include <environment.h> #include <errno.h> #include <fsl_esdhc.h> #include <fuse.h> diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig deleted file mode 100644 index eeeb6f490f..0000000000 --- a/board/freescale/mx31ads/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_MX31ADS - -config SYS_BOARD - default "mx31ads" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "mx31ads" - -endif diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS deleted file mode 100644 index 5f6ec268c7..0000000000 --- a/board/freescale/mx31ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MX31ADS BOARD -#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> -S: Orphan (since 2013-09) -F: board/freescale/mx31ads/ -F: include/configs/mx31ads.h -F: configs/mx31ads_defconfig diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile deleted file mode 100644 index 5e1440d596..0000000000 --- a/board/freescale/mx31ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mx31ads.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S deleted file mode 100644 index fcb5549d77..0000000000 --- a/board/freescale/mx31ads/lowlevel_init.S +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/imx-regs.h> - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -/* RedBoot: AIPS setup - Only setup MPROTx registers. - * The PACR default values are good.*/ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =0x43F00000 - ldr r1, =0x77777777 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - ldr r0, =0x53F00000 - str r1, [r0, #0x00] - str r1, [r0, #0x04] - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - ldr r0, =0x43F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] - - ldr r0, =0x53F00000 - ldr r1, =0x0 - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - ldr r1, [r0, #0x50] - and r1, r1, #0x00FFFFFF - str r1, [r0, #0x50] -.endm /* init_aips */ - -/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max - ldr r0, =0x43F04000 - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ - ldr r1, =0x00302154 - str r1, [r0, #0x000] /* for S0 */ - str r1, [r0, #0x100] /* for S1 */ - str r1, [r0, #0x200] /* for S2 */ - str r1, [r0, #0x300] /* for S3 */ - str r1, [r0, #0x400] /* for S4 */ - /* SGPCR - always park on last master */ - ldr r1, =0x10 - str r1, [r0, #0x010] /* for S0 */ - str r1, [r0, #0x110] /* for S1 */ - str r1, [r0, #0x210] /* for S2 */ - str r1, [r0, #0x310] /* for S3 */ - str r1, [r0, #0x410] /* for S4 */ - /* MGPCR - restore default values */ - ldr r1, =0x0 - str r1, [r0, #0x800] /* for M0 */ - str r1, [r0, #0x900] /* for M1 */ - str r1, [r0, #0xA00] /* for M2 */ - str r1, [r0, #0xB00] /* for M3 */ - str r1, [r0, #0xC00] /* for M4 */ - str r1, [r0, #0xD00] /* for M5 */ -.endm /* init_max */ - -/* RedBoot: M3IF setup */ -.macro init_m3if - /* Configure M3IF registers */ - ldr r1, =0xB8003000 - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - ldr r0, =0x00000040 - str r0, [r1] /* M3IF control reg */ -.endm /* init_m3if */ - -/* RedBoot: To support 133MHz DDR */ -.macro init_drive_strength - /* - * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits - * in SW_PAD_CTL registers - */ - - /* SDCLK */ - ldr r1, =0x43FAC200 - ldr r0, [r1, #0x6C] - bic r0, r0, #(1 << 12) - str r0, [r1, #0x6C] - - /* CAS */ - ldr r0, [r1, #0x70] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x70] - - /* RAS */ - ldr r0, [r1, #0x74] - bic r0, r0, #(1 << 2) - str r0, [r1, #0x74] - - /* CS2 (CSD0) */ - ldr r0, [r1, #0x7C] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x7C] - - /* DQM3 */ - ldr r0, [r1, #0x84] - bic r0, r0, #(1 << 22) - str r0, [r1, #0x84] - - /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ -pad_loop: - ldr r0, [r1, #0x88] - bic r0, r0, #(1 << 22) - bic r0, r0, #(1 << 12) - bic r0, r0, #(1 << 2) - str r0, [r1, #0x88] - add r1, r1, #4 - subs r2, r2, #0x1 - bne pad_loop -.endm /* init_drive_strength */ - -/* CPLD on CS4 setup */ -.macro init_cs4 - ldr r0, =WEIM_BASE - ldr r1, =0x0000D843 - str r1, [r0, #0x40] - ldr r1, =0x22252521 - str r1, [r0, #0x44] - ldr r1, =0x22220A00 - str r1, [r0, #0x48] -.endm /* init_cs4 */ - -.globl lowlevel_init -lowlevel_init: - - /* Redboot initializes very early AIPS, what for? - * Then it also initializes Multi-Layer AHB Crossbar Switch, - * M3IF */ - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - - init_aips - - init_max - - init_m3if - - init_drive_strength - - init_cs4 - - /* Image Processing Unit: */ - /* Too early to switch display on? */ - REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ - /* Clock Control Module: */ - REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ - - /* PBC CPLD on CS4 */ - mov r1, #CS4_BASE - ldrh r1, [r1, #0x2] - /* Is 27MHz switch set? */ - ands r1, r1, #0x10 - - /* 532-133-66.5 */ - ldr r0, =CCM_BASE - ldr r1, =0xFF871D58 - /* PDR0 */ - str r1, [r0, #0x4] - ldreq r1, MPCTL_PARAM_532 - ldrne r1, MPCTL_PARAM_532_27 - /* MPCTL */ - str r1, [r0, #0x10] - - /* Set UPLL=240MHz, USB=60MHz */ - ldr r1, =0x49FCFE7F - /* PDR1 */ - str r1, [r0, #0x8] - ldreq r1, UPCTL_PARAM_240 - ldrne r1, UPCTL_PARAM_240_27 - /* UPCTL */ - str r1, [r0, #0x14] - /* default CLKO to 1/8 of the ARM core */ - mov r1, #0x000002C0 - add r1, r1, #0x00000006 - /* COSR */ - str r1, [r0, #0x1c] - - /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */ -/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ - - /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ -/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ - /* Default: 1, 4, 12, 1 */ - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) - - /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr - -MPCTL_PARAM_532: - .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) -MPCTL_PARAM_532_27: - .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) -UPCTL_PARAM_240: - .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) -UPCTL_PARAM_240_27: - .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c deleted file mode 100644 index ad89cb021d..0000000000 --- a/board/freescale/mx31ads/mx31ads.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_early_init_f(void) -{ - int i; - - /* CS0: Nor Flash */ - /* - * CS0L and CS0A values are from the RedBoot sources by Freescale - * and are also equal to those used by Sascha Hauer for the Phytec - * i.MX31 board. CS0U is just a slightly optimized hardware default: - * the only non-zero field "Wait State Control" is set to half the - * default value. - */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* SPI2 */ - mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); - mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); - - /* start SPI2 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); - - /* PBC setup */ - /* Enable UART transceivers also reset the Ethernet/external UART */ - readw(CS4_BASE + 4); - - writew(0x8023, CS4_BASE + 4); - - /* RedBoot also has an empty loop with 100000 iterations here - - * clock doesn't run yet */ - for (i = 0; i < 100000; i++) - ; - - /* Clear the reset, toggle the LEDs */ - writew(0xDF, CS4_BASE + 6); - - /* clock still doesn't run */ - for (i = 0; i < 100000; i++) - ; - - /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - readb(CS4_BASE + 8); - readb(CS4_BASE + 7); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ - - return 0; -} - -int checkboard(void) -{ - printf("Board: MX31ADS\n"); - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds deleted file mode 100644 index 71a63f188e..0000000000 --- a/board/freescale/mx31ads/u-boot.lds +++ /dev/null @@ -1,110 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - * (.vectors) - arch/arm/cpu/arm1136/start.o (.text*) - board/freescale/mx31ads/built-in.o (.text*) - arch/arm/lib/built-in.o (.text*) - net/built-in.o (.text*) - drivers/mtd/built-in.o (.text*) - - . = DEFINED(env_offset) ? env_offset : .; - env/embedded.o(.text*) - - *(.text*) - } - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - .hash : { *(.hash*) } - - .end : - { - *(.__end) - } - - _image_binary_end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _image_binary_end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .gnu.hash : { *(.gnu.hash) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 4ddc7e1fa2..332c506dfe 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -22,6 +22,7 @@ #include <asm/setup.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> +#include <environment.h> #include <hwconfig.h> #include <i2c.h> #include <fdt_support.h> diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index c7a29185bf..46321ae666 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -786,23 +786,6 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif -#ifdef CONFIG_VIDEO_IPUV3 - /* We need at least 200ms between power on and backlight on - * as per specifications from CHI MEI */ - mdelay(250); - - /* enable backlight PWM 1 */ - pwm_init(0, 0, 0); - - /* duty cycle 5000000ns, period: 5000000ns */ - pwm_config(0, 5000000, 5000000); - - /* Backlight Power */ - gpio_direction_output(LVDS_BACKLIGHT_GP, 1); - - pwm_enable(0); -#endif - /* board specific pmic init */ pmic_init(); @@ -843,3 +826,31 @@ int checkboard(void) printf("BOARD: %s\n", CONFIG_BOARD_NAME); return 0; } + +static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_VIDEO_IPUV3 + /* We need at least 200ms between power on and backlight on + * as per specifications from CHI MEI */ + mdelay(250); + + /* enable backlight PWM 1 */ + pwm_init(0, 0, 0); + + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(0, 5000000, 5000000); + + /* Backlight Power */ + gpio_direction_output(LVDS_BACKLIGHT_GP, 1); + + pwm_enable(0); +#endif + + return 0; +} + +U_BOOT_CMD( + bx50_backlight_enable, 1, 1, do_backlight_enable, + "enable Bx50 backlight", + "" +); diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index 90dbccc5ed..0010998d66 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -20,6 +20,7 @@ #include <linux/errno.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/mx5_video.h> +#include <environment.h> #include <netdev.h> #include <i2c.h> #include <mmc.h> diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig deleted file mode 100644 index e897ee1c3a..0000000000 --- a/board/imx31_phycore/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET - -config SYS_BOARD - default "imx31_phycore" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "imx31_phycore" - -endif diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS deleted file mode 100644 index 41f6cae81b..0000000000 --- a/board/imx31_phycore/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -IMX31_PHYCORE BOARD -#M: - -S: Maintained -F: board/imx31_phycore/ -F: include/configs/imx31_phycore.h -F: configs/imx31_phycore_defconfig - -IMX31_PHYCORE_EET BOARD -#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> -S: Orphan (since 2013-09) -F: configs/imx31_phycore_eet_defconfig diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile deleted file mode 100644 index e781c13936..0000000000 --- a/board/imx31_phycore/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := imx31_phycore.o -obj-y += lowlevel_init.o diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c deleted file mode 100644 index 653246615f..0000000000 --- a/board/imx31_phycore/imx31_phycore.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <s6e63d6.h> -#include <netdev.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/mach-types.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_init(void) -{ - - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - - return 0; -} - -int board_early_init_f(void) -{ - /* CS0: Nor Flash */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - /* CS1: Network Controller */ - static const struct mxc_weimcs cs1 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) - }; - - /* CS4: SRAM */ - static const struct mxc_weimcs cs4 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - mxc_setup_weimcs(1, &cs1); - mxc_setup_weimcs(4, &cs4); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* setup pins for I2C2 (for EEPROM, RTC) */ - mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); - mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_S6E63D6 - struct s6e63d6 data = { - /* - * See comment in mxc_spi.c::decode_cs() for .cs field format. - * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect - * 2 of the SPI controller #1, since it is unused. - */ - .cs = 2 | (57 << 8), - .bus = 0, - .id = 0, - }; - int ret; - - /* SPI1 */ - mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); - mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); - mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); - mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); - mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); - mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); - - /* start SPI1 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); - - /* GPIO 57 */ - /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ - mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); - - /* SPI1 CS2 is free */ - ret = s6e63d6_init(&data); - if (ret) - return ret; - - /* - * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC - * OLED display connected to a S6E63D6 SPI display controller in the - * 18 bit RGB mode - */ - s6e63d6_index(&data, 2); - s6e63d6_param(&data, 0x0182); - s6e63d6_index(&data, 3); - s6e63d6_param(&data, 0x8130); - s6e63d6_index(&data, 0x10); - s6e63d6_param(&data, 0x0000); - s6e63d6_index(&data, 5); - s6e63d6_param(&data, 0x0001); - s6e63d6_index(&data, 0x22); -#endif - return 0; -} -#endif - -int checkboard (void) -{ - printf("Board: Phytec phyCore i.MX31\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S deleted file mode 100644 index 6ea3878ef9..0000000000 --- a/board/imx31_phycore/lowlevel_init.S +++ /dev/null @@ -1,88 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/imx-regs.h> - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -.globl lowlevel_init -lowlevel_init: - - REG IPU_CONF, IPU_CONF_DI_EN - REG CCM_CCMR, 0x074B0BF5 - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - - REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) - - REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) - - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) - - REG 0x43FAC26C, 0 /* SDCLK */ - REG 0x43FAC270, 0 /* CAS */ - REG 0x43FAC274, 0 /* RAS */ - REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ - REG 0x43FAC284, 0 /* DQM3 */ - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - REG 0x43FAC28C, 0 - REG 0x43FAC290, 0 - REG 0x43FAC294, 0 - REG 0x43FAC298, 0 - REG 0x43FAC29C, 0 - REG 0x43FAC2A0, 0 - REG 0x43FAC2A4, 0 - REG 0x43FAC2A8, 0 - REG 0x43FAC2AC, 0 - REG 0x43FAC2B0, 0 - REG 0x43FAC2B4, 0 - REG 0x43FAC2B8, 0 - REG 0x43FAC2BC, 0 - REG 0x43FAC2C0, 0 - REG 0x43FAC2C4, 0 - REG 0x43FAC2C8, 0 - REG 0x43FAC2CC, 0 - REG 0x43FAC2D0, 0 - REG 0x43FAC2D4, 0 - REG 0x43FAC2D8, 0 - REG 0x43FAC2DC, 0 - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr diff --git a/board/k+p/bootscripts/tpcboot.cmd b/board/k+p/bootscripts/tpcboot.cmd new file mode 100644 index 0000000000..f6d59a1186 --- /dev/null +++ b/board/k+p/bootscripts/tpcboot.cmd @@ -0,0 +1,96 @@ +# +# Copyright (C) 2018 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de +# +# +# This is an example file to generate boot.scr - a boot script for U-Boot +# Generate boot.scr: +# ./tools/mkimage -c none -A arm -T script -d tpcboot.cmd boot.scr +# +# SPDX-License-Identifier: GPL-2.0+ + + +# Input envs (to be set in environment) +# Mandatory: +# kernel_file = "fitImage" +# boardname = "XXXX" // set automatically in u-boot +# boardsoc = "imx6q" // set automatically in u-boot +# +# Optional: +# bootcmd_force = "nfs" "tftp_kernel" +# If not set - eMMC/SD boot + +# Generic setup +setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw" +setenv displayargs "" +setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \ + ${displayargs}" +setenv boot_fitImage " + setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb'; + setenv itbcfg "\"#\${fdt_conf}\""; + print itbcfg; + bootm '${loadaddr}${itbcfg}';" + +#------------------------------------------------------------ +# +# Provide default 'bootcmd' command +#------------------------------------------------------------ +setenv bootcmd " +if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then + echo Found kernel image: ${kernel_file}; + if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \ + ${kernel_file}; then + run mmcargs; + run boot_fitImage; + fi; +fi;" + +#------------------------------------------------------------ +# +# Provide 'boot_tftp_kernel' command +#------------------------------------------------------------ +setenv download_kernel "tftpboot ${loadaddr} ${kernel_file}" + +setenv boot_tftp_kernel " +if run download_kernel; then + run mmcargs; + run boot_fitImage; +fi" + +#------------------------------------------------------------ +# +# Provide 'boot_nfs' command +#------------------------------------------------------------ +setenv rootpath "/srv/tftp/KP/rootfs" +setenv nfsargs "setenv bootargs root=/dev/nfs rw \ + nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" +setenv addip "setenv bootargs ${bootargs} \ + ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:\ + ${hostname}:eth0:on" + +setenv boot_nfs " +if run download_kernel; then + run nfsargs; + run addip; + setenv bootargs ${bootargs} console=${console}; + + run boot_fitImage; +fi" + +#------------------------------------------------------------ +# +# Set correct boot flow +#------------------------------------------------------------ + +setenv bcmd " +if test ! -n ${bootcmd_force}; then + run bootcmd; +fi; +if test ${bootcmd_force} = nfs; then + run boot_nfs; +else if test ${bootcmd_force} = tftp_kernel; then + run boot_tftp_kernel; + fi; +fi" + +run bcmd diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig new file mode 100644 index 0000000000..62e34978ec --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/Kconfig @@ -0,0 +1,12 @@ +if TARGET_KP_IMX6Q_TPC + +config SYS_BOARD + default "kp_imx6q_tpc" + +config SYS_VENDOR + default "k+p" + +config SYS_CONFIG_NAME + default "kp_imx6q_tpc" + +endif diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS new file mode 100644 index 0000000000..6c4c8dd28e --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/MAINTAINERS @@ -0,0 +1,6 @@ +KP_IMX6Q_TPC BOARD +M: Lukasz Majewski <lukma@denx.de> +S: Maintained +F: board/k+p/kp_imx6q_tpc/ +F: include/configs/kp_imx6q_tpc.h +F: configs/kp_imx6q_tpc_defconfig diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile new file mode 100644 index 0000000000..51cbd3e843 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := kp_imx6q_tpc_spl.o +else +obj-y := kp_imx6q_tpc.o +endif diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c new file mode 100644 index 0000000000..9a5b88029f --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c @@ -0,0 +1,302 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <errno.h> +#include <fsl_esdhc.h> +#include <fuse.h> +#include <i2c.h> +#include <miiphy.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) + +#define I2C_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC, + .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | + MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* AR8031 PHY Reset */ + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void eth_phy_reset(void) +{ + /* Reset AR8031 PHY */ + gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + mdelay(10); + gpio_set_value(IMX_GPIO_NR(1, 25), 1); + udelay(100); +} + +static int setup_fec_clock(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* set gpr1[21] to select anatop clock */ + clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21); + + return enable_fec_anatop_clock(0, ENET_50MHZ); +} + +int board_eth_init(bd_t *bis) +{ + SETUP_IOMUX_PADS(enet_pads); + setup_fec_clock(); + eth_phy_reset(); + + return cpu_eth_init(bis); +} + +static int ar8031_phy_fixup(struct phy_device *phydev) +{ + unsigned short val; + + /* To enable AR8031 output a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + ar8031_phy_fixup(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC2_BASE_ADDR }, + { USDHC4_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return !gpio_get_value(USDHC2_CD_GPIO); + case USDHC4_BASE_ADDR: + return 1; /* eMMC/uSDHC4 is always present */ + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 micro SD + * mmc2 eMMC + */ + gpio_direction_input(USDHC2_CD_GPIO); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +static void setup_usb(void) +{ + /* + * Set daisy chain for otg_pin_id on MX6Q. + * For MX6DL, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return USB_INIT_DEVICE; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + gpio_direction_output(IMX_GPIO_NR(3, 31), !!on); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + + return 0; +} + +int board_init(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Enable eim_slow clocks */ + setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + env_set("boardname", "kp-tpc"); + env_set("boardsoc", "imx6q"); + return 0; +} + +int checkboard(void) +{ + puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n"); + return 0; +} diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c new file mode 100644 index 0000000000..3fdfea7546 --- /dev/null +++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c @@ -0,0 +1,338 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/io.h> +#include <errno.h> +#include <fuse.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <mmc.h> +#include <spl.h> + +#define UART_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL \ + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +DECLARE_GLOBAL_DATA_PTR; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +/* onboard microSD */ +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +/* eMMC */ +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +/* SD */ +static void setup_iomux_sd(void) +{ + SETUP_IOMUX_PADS(usdhc2_pads); + SETUP_IOMUX_PADS(usdhc4_pads); +} + +/* UART */ +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +/* USB */ +static iomux_v3_cfg_t const usb_pads[] = { + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +static void setup_iomux_usb(void) +{ + SETUP_IOMUX_PADS(usb_pads); +} + +/* DDR3 */ +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_reset = 0x00000030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00000030, + .dram_sdodt1 = 0x00000030, + + .dram_sdqs0 = 0x00000018, + .dram_sdqs1 = 0x00000018, + .dram_sdqs2 = 0x00000018, + .dram_sdqs3 = 0x00000018, + .dram_sdqs4 = 0x00000018, + .dram_sdqs5 = 0x00000018, + .dram_sdqs6 = 0x00000018, + .dram_sdqs7 = 0x00000018, + + .dram_dqm0 = 0x00000018, + .dram_dqm1 = 0x00000018, + .dram_dqm2 = 0x00000018, + .dram_dqm3 = 0x00000018, + .dram_dqm4 = 0x00000018, + .dram_dqm5 = 0x00000018, + .dram_dqm6 = 0x00000018, + .dram_dqm7 = 0x00000018, +}; + +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000018, + .grp_b1ds = 0x00000018, + .grp_b2ds = 0x00000018, + .grp_b3ds = 0x00000018, + .grp_b4ds = 0x00000018, + .grp_b5ds = 0x00000018, + .grp_b6ds = 0x00000018, + .grp_b7ds = 0x00000018, +}; + +static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x001F001F, + .p1_mpwldectrl1 = 0x001F001F, + .p0_mpdgctrl0 = 0x43270338, + .p0_mpdgctrl1 = 0x03200314, + .p1_mpdgctrl0 = 0x431A032F, + .p1_mpdgctrl1 = 0x03200263, + .p0_mprddlctl = 0x4B434748, + .p1_mprddlctl = 0x4445404C, + .p0_mpwrdlctl = 0x38444542, + .p1_mpwrdlctl = 0x4935493A, +}; + +/* MT41K256M16 (4Gb density) */ +static const struct mx6_ddr3_cfg mt41k256m16 = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +#ifdef CONFIG_MX6_DDRCAL +static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + struct mx6_mmdc_calibration calibration = {0}; + + mmdc_read_calibration(sysinfo, &calibration); + + debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); + debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); + debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); + debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); + debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); + debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); + debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); + debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); + debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); + debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); + debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); + debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); +} + +static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret; + + /* Perform DDR DRAM calibration */ + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR: Write level calibration error [%d]\n", ret); + return; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR: DQS calibration error [%d]\n", ret); + return; + } + + spl_dram_print_cal(sysinfo); +} +#endif /* CONFIG_MX6_DDRCAL */ + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16); + +#ifdef CONFIG_MX6_DDRCAL + spl_dram_perform_cal(&sysinfo); +#endif +} + +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC2_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bd) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bd, &usdhc_cfg[0]); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* setup GP timer */ + timer_init(); + + setup_iomux_sd(); + setup_iomux_uart(); + setup_iomux_usb(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index f0ace03009..91bc9c2651 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -21,6 +21,7 @@ #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/sata.h> #include <asm/mach-imx/video.h> +#include <environment.h> #include <fsl_esdhc.h> #include <i2c.h> #include <input.h> diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index e6c2526ea1..fe1183b0bd 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -16,6 +16,7 @@ */ #include <common.h> #include <dm.h> +#include <environment.h> #include <ns16550.h> #include <netdev.h> #include <twl4030.h> diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 52ad5b64de..c57625b041 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <environment.h> #include <errno.h> #include <spl.h> #include <asm/arch/cpu.h> diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index 47b069e2ad..a1b407d707 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <common.h> #include <dm.h> +#include <environment.h> #include <i2c.h> #include <i2c_eeprom.h> #include <netdev.h> diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index de8e308f6c..30495057d1 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -8,6 +8,7 @@ #include <inttypes.h> #include <config.h> #include <dm.h> +#include <environment.h> #include <efi_loader.h> #include <fdt_support.h> #include <fdt_simplefb.h> diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 0bf8160f1f..f2200ef081 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index 574dcda01b..5dc307370d 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -12,6 +12,7 @@ #include <netdev.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 54e126985b..99d4ba6fd8 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile index 15f111c504..77cf067406 100644 --- a/board/renesas/koelsch/Makefile +++ b/board/renesas/koelsch/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := koelsch.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := koelsch_spl.o +else +obj-y := koelsch.o qos.o +endif diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 8fa648e40a..4a4007b7a3 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -11,6 +11,7 @@ #include <malloc.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -47,13 +48,7 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) - -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP312 (1 << 12) -#define SDHI2_MSTP311 (1 << 11) +#define TMU0_MSTP125 BIT(25) #define SD1CKCR 0xE6150078 #define SD2CKCR 0xE615026C @@ -63,16 +58,6 @@ int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF0 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - /* SDHI */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, - SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); - /* * SD0 clock is set to 97.5MHz by default. * Set SD1 and SD2 to the 97.5MHz as well. @@ -83,133 +68,40 @@ int board_early_init_f(void) return 0; } -/* LSI pin pull-up control */ -#define PUPR5 0xe6060114 -#define PUPR5_ETH 0x3FFC0000 -#define PUPR5_ETH_MAGIC (1 << 27) +#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7791_pinmux_init(); - - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REFCLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ0, NULL); - - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); - gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); - - gpio_direction_output(GPIO_GP_5_22, 0); - mdelay(20); - gpio_set_value(GPIO_GP_5_22, 1); - udelay(1); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); + mdelay(10); + gpio_direction_output(ETHERNET_PHY_RESET, 1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { -#ifdef CONFIG_SH_ETHER - int ret = -ENODEV; - u32 val; - unsigned char enetaddr[6]; - - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); - - return ret; -#else return 0; -#endif } -int board_mmc_init(bd_t *bis) +int dram_init_banksize(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD0_DATA0, NULL); - gpio_request(GPIO_FN_SD0_DATA1, NULL); - gpio_request(GPIO_FN_SD0_DATA2, NULL); - gpio_request(GPIO_FN_SD0_DATA3, NULL); - gpio_request(GPIO_FN_SD0_CLK, NULL); - gpio_request(GPIO_FN_SD0_CMD, NULL); - gpio_request(GPIO_FN_SD0_CD, NULL); - gpio_request(GPIO_FN_SD2_DATA0, NULL); - gpio_request(GPIO_FN_SD2_DATA1, NULL); - gpio_request(GPIO_FN_SD2_DATA2, NULL); - gpio_request(GPIO_FN_SD2_DATA3, NULL); - gpio_request(GPIO_FN_SD2_CLK, NULL); - gpio_request(GPIO_FN_SD2_CMD, NULL); - gpio_request(GPIO_FN_SD2_CD, NULL); - - /* SDHI 0 */ - gpio_request(GPIO_GP_7_17, NULL); - gpio_request(GPIO_GP_2_12, NULL); - gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, - SH_SDHI_QUIRK_16BIT_BUF); - if (ret) - return ret; - - /* SDHI 1 */ - gpio_request(GPIO_GP_7_18, NULL); - gpio_request(GPIO_GP_2_13, NULL); - gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); - if (ret) - return ret; - - /* SDHI 2 */ - gpio_request(GPIO_GP_7_19, NULL); - gpio_request(GPIO_GP_2_26, NULL); - gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); -#endif - return ret; -} - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + fdtdec_setup_memory_banksize(); return 0; } -/* koelsch has KSZ8041NL/RNL */ -#define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 +/* Koelsch has KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 #define PHY_LED_MODE_ACK 0x4000 int board_phy_config(struct phy_device *phydev) { @@ -227,22 +119,38 @@ const struct rmobile_sysinfo sysinfo = { void reset_cpu(ulong addr) { - u8 val; + struct udevice *dev; + const u8 pmic_bus = 6; + const u8 pmic_addr = 0x58; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); + + data |= BIT(1); - i2c_set_bus_num(2); /* PowerIC connected to ch2 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } -static const struct sh_serial_platdata serial_platdata = { - .base = SCIF0_BASE, - .type = PORT_SCIF, - .clk = 14745600, - .clk_mode = EXT_CLK, -}; +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; -U_BOOT_DEVICE(koelsch_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/koelsch/koelsch_spl.c b/board/renesas/koelsch/koelsch_spl.c new file mode 100644 index 0000000000..de6c1c0567 --- /dev/null +++ b/board/renesas/koelsch/koelsch_spl.c @@ -0,0 +1,410 @@ +/* + * board/renesas/koelsch/koelsch_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define QSPI_MSTP917 BIT(17) + +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; + + while (!(readl(dbsc3_1_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x60000000 }, + { 0x0094, 0x60000000 }, + { 0x0098, 0x00800200 }, + { 0x009c, 0x00000000 }, + { 0x0020, 0x00000000 }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x000244c8 }, + { 0x002c, 0x00000000 }, + { 0x0030, 0x00002400 }, + { 0x0034, 0x01520000 }, + { 0x0038, 0x00724003 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x00000000 }, + { 0x0044, 0x00000000 }, + { 0x0048, 0x00000000 }, + { 0x004c, 0x00000000 }, + { 0x0050, 0x00000000 }, + { 0x0054, 0x00000000 }, + { 0x0058, 0x00000000 }, + { 0x005c, 0x00000000 }, + { 0x0160, 0x00000000 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x00ec3fff }, + { 0x000c, 0x3bc001e7 }, + { 0x0010, 0x5bffffff }, + { 0x0014, 0x1ffffffb }, + { 0x0018, 0x01bffff0 }, + { 0x001c, 0xcf7fffff }, + { 0x0074, 0x0381fc00 }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0xffffffdf }, + { 0x0104, 0xc883c3ff }, + { 0x0108, 0x1201f3c9 }, + { 0x010c, 0x00000000 }, + { 0x0110, 0xffffeb04 }, + { 0x0114, 0xc003ffff }, + { 0x0118, 0x0800000f }, + { 0x011c, 0x001800f0 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 + }; + + static const struct reg_config gpio_set[] = { + { 0x2000, 0x04381000 }, + { 0x5000, 0x00000000 }, + { 0x5800, 0x000e0000 }, + + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x00000000 }, + { 0x2000, 0x04381010 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0x00000000 }, + { 0x5000, 0x00400000 }, + { 0x5400, 0x00000000 }, + { 0x5800, 0x000e0380 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x2a103320 }, + { 0x38, 0xff70ff70 }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0280, 0x0000a55a }, + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf004649b }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x0000000b }, + { 0x0044, 0x00000008 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x0000000b }, + { 0x0054, 0x000c000b }, + { 0x0058, 0x00000027 }, + { 0x005c, 0x0000001c }, + { 0x0060, 0x00000006 }, + { 0x0064, 0x00000020 }, + { 0x0068, 0x00000008 }, + { 0x006c, 0x0000000c }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000012 }, + { 0x0078, 0x000000d0 }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x70233005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000300 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20082008 }, + { 0x0380, 0x00020002 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0005c000 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c481 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fdb6c0 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x9d9cbb66 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a868400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300214d8 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000d70 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000018 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x014000aa }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081860 }, + { 0x00e8, 0x00010000 }, + { 0x0014, 0x00000001 }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); + } + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); + } + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + int i; + + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD2CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + + /* Unknown, likely ES1.0-specific delay */ + for (i = 0; i < 100000; i++) + asm volatile("nop"); + + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 562be04760..3566bcc788 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <malloc.h> #include <netdev.h> #include <dm.h> diff --git a/board/renesas/porter/Makefile b/board/renesas/porter/Makefile index b0cfb1b06a..c237ee5ec7 100644 --- a/board/renesas/porter/Makefile +++ b/board/renesas/porter/Makefile @@ -7,4 +7,8 @@ # SPDX-License-Identifier: GPL-2.0 # +ifdef CONFIG_SPL_BUILD +obj-y := porter_spl.o +else obj-y := porter.o qos.o +endif diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index 320841f27b..eb66bc903e 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -11,6 +11,7 @@ #include <malloc.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -137,24 +138,17 @@ void reset_cpu(ulong addr) hang(); } -#ifdef CONFIG_SPL_BUILD -#include <spl.h> -void board_init_f(ulong dummy) +enum env_location env_get_location(enum env_operation op, int prio) { - board_early_init_f(); -} + const u32 load_magic = 0xb33fc0de; -void spl_board_init(void) -{ - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); -} + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; -void board_boot_order(u32 *spl_boot_list) -{ - /* Boot from SPI NOR with YMODEM UART fallback. */ - spl_boot_list[0] = BOOT_DEVICE_SPI; - spl_boot_list[1] = BOOT_DEVICE_UART; - spl_boot_list[2] = BOOT_DEVICE_NONE; + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; } -#endif diff --git a/board/renesas/porter/porter_spl.c b/board/renesas/porter/porter_spl.c new file mode 100644 index 0000000000..55f4cace0c --- /dev/null +++ b/board/renesas/porter/porter_spl.c @@ -0,0 +1,491 @@ +/* + * board/renesas/porter/porter_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define QSPI_MSTP917 BIT(17) + +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; + + while (!(readl(dbsc3_1_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x60000000 }, + { 0x0094, 0x60000000 }, + { 0x0098, 0x00800200 }, + { 0x009c, 0x00000000 }, + { 0x0020, 0x00000000 }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x000244c8 }, + { 0x002c, 0x00000000 }, + { 0x0030, 0x00002400 }, + { 0x0034, 0x01520000 }, + { 0x0038, 0x00724003 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x00000000 }, + { 0x0044, 0x00000000 }, + { 0x0048, 0x00000000 }, + { 0x004c, 0x00000000 }, + { 0x0050, 0x00000000 }, + { 0x0054, 0x00000000 }, + { 0x0058, 0x00000000 }, + { 0x005c, 0x00000000 }, + { 0x0160, 0x00000000 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x00ec3fff }, + { 0x000c, 0x3bc001e7 }, + { 0x0010, 0x5bffffff }, + { 0x0014, 0x1ffffffb }, + { 0x0018, 0x01bffff0 }, + { 0x001c, 0xcf7fffff }, + { 0x0074, 0x0381fc00 }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0xffffffdf }, + { 0x0104, 0xc883c3ff }, + { 0x0108, 0x1201f3c9 }, + { 0x010c, 0x00000000 }, + { 0x0110, 0xffffeb04 }, + { 0x0114, 0xc003ffff }, + { 0x0118, 0x0800000f }, + { 0x011c, 0x00187ff0 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 + }; + + static const struct reg_config gpio_set[] = { + { 0x2000, 0x04381000 }, + { 0x5000, 0x00000000 }, + { 0x5800, 0x000e0000 }, + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x00000000 }, + { 0x2000, 0x04381010 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0x00000000 }, + { 0x5000, 0x00400000 }, + { 0x5400, 0x00000000 }, + { 0x5800, 0x000e0380 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x2a103320 }, + { 0x38, 0xff70ff70 }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0280, 0x0000a55a }, + { 0x4000, 0x0000a55a }, + { 0x4008, 0x00000001 }, + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x80000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config2[] = { + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0001c000 }, + }; + + static const struct reg_config dbsc_config3r0d0[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181885 }, + { 0x0290, 0x00000070 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000080 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000090 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x000000a0 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x000000b0 }, + { 0x02a0, 0x7c000880 }, + { 0x0290, 0x000000c0 }, + { 0x02a0, 0x7c000880 }, + { 0x0290, 0x000000d0 }, + { 0x02a0, 0x7c000880 }, + { 0x0290, 0x000000e0 }, + { 0x02a0, 0x7c000880 }, + }; + static const struct reg_config dbsc_config3r0d1[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181885 }, + { 0x0290, 0x00000070 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000080 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000090 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x000000a0 }, + { 0x02a0, 0x7c000887 }, + }; + + static const struct reg_config dbsc_config3r2[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181224 }, + }; + + static const struct reg_config dbsc_config4[] = { + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf004649b }, + { 0x0290, 0x00000061 }, + { 0x02a0, 0x0000006d }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000073 }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x0000000b }, + { 0x0044, 0x00000008 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x0000000b }, + { 0x0054, 0x000c000b }, + { 0x0058, 0x00000027 }, + { 0x005c, 0x0000001c }, + { 0x0060, 0x00000006 }, + { 0x0064, 0x00000020 }, + { 0x0068, 0x00000008 }, + { 0x006c, 0x0000000c }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000012 }, + { 0x0078, 0x000000d0 }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x70233005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000200 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20042004 }, + { 0x0380, 0x00020002 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c561 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fcdb60 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x9d9cbb66 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a868400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300214d8 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000d70 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000018 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x014a00b9 }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081860 }, + { 0x00e8, 0x00010000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0014, 0x00000001 }, + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf00464db }, + { 0x4008, 0x00000000 }, + { 0x4000, 0x00000000 }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + static const u32 prr_base = 0xff000044; + const u16 prr_rev = readl(prr_base) & 0x7fff; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) { + writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); + writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off); + } + + if (prr_rev == 0x4700) { + for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) { + writel(dbsc_config3r0d0[i].val, + dbsc3_0_base | dbsc_config3r0d0[i].off); + } + for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) { + writel(dbsc_config3r0d1[i].val, + dbsc3_1_base | dbsc_config3r0d1[i].off); + } + } else if (prr_rev != 0x4710) { + for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) { + writel(dbsc_config3r2[i].val, + dbsc3_0_base | dbsc_config3r2[i].off); + writel(dbsc_config3r2[i].val, + dbsc3_1_base | dbsc_config3r2[i].off); + } + } + + for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) { + writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); + writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off); + } + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); + } + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD2CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c index 4a76fb73ee..5da6f39ae3 100644 --- a/board/renesas/sh7752evb/sh7752evb.c +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <environment.h> #include <malloc.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c index ca9e144743..8604d88247 100644 --- a/board/renesas/sh7753evb/sh7753evb.c +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <environment.h> #include <malloc.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c index 3f970fc401..1c598fbedd 100644 --- a/board/renesas/sh7757lcr/sh7757lcr.c +++ b/board/renesas/sh7757lcr/sh7757lcr.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <environment.h> #include <malloc.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile index 8916a8d961..b5c3ad8d93 100644 --- a/board/renesas/silk/Makefile +++ b/board/renesas/silk/Makefile @@ -7,4 +7,8 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := silk.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := silk_spl.o +else +obj-y := silk.o qos.o +endif diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index a8de402d20..bfe9909daf 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -11,6 +11,7 @@ #include <malloc.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -29,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; @@ -43,150 +43,65 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF2_MSTP719 (1 << 19) -#define ETHER_MSTP813 (1 << 13) -#define IIC1_MSTP323 (1 << 23) -#define MMC0_MSTP315 (1 << 15) -#define SDHI1_MSTP312 (1 << 12) +#define TMU0_MSTP125 BIT(25) +#define MMC0_MSTP315 BIT(15) #define SD1CKCR 0xE6150078 -#define SD1_97500KHZ 0x7 +#define SD_97500KHZ 0x7 int board_early_init_f(void) { /* TMU */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF2 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + /* Set SD1 to the 97.5MHz */ + writel(SD_97500KHZ, SD1CKCR); - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - /* IIC1 / sh-i2c ch1 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); - -#ifdef CONFIG_SH_MMCIF - /* MMC */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); -#endif - -#ifdef CONFIG_SH_SDHI - /* SDHI1 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312); - - /* - * Set SD1 to the 97.5MHz - */ - writel(SD1_97500KHZ, SD1CKCR); -#endif return 0; } -/* LSI pin pull-up control */ -#define PUPR3 0xe606010C -#define PUPR3_ETH 0x006FF800 -#define PUPR1 0xe6060104 -#define PUPR1_DREQ0_N (1 << 20) +#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */ + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7794_pinmux_init(); - - /* Ether Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REFCLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_MAGIC, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ8, NULL); - - /* PHY reset */ - mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH); - gpio_request(GPIO_GP_1_24, NULL); - mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N); - - gpio_direction_output(GPIO_GP_1_24, 0); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); mdelay(20); - gpio_set_value(GPIO_GP_1_24, 1); + gpio_direction_output(ETHERNET_PHY_RESET, 1); udelay(1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { -#ifdef CONFIG_SH_ETHER - int ret = -ENODEV; - u32 val; - unsigned char enetaddr[6]; + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); - - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); - - return ret; -#else return 0; -#endif } -int board_mmc_init(bd_t *bis) +int dram_init_banksize(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_MMCIF - /* MMC0 */ - gpio_request(GPIO_GP_4_31, NULL); - gpio_direction_output(GPIO_GP_4_31, 1); - - ret = mmcif_mmc_init(); -#endif - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD1_DATA0, NULL); - gpio_request(GPIO_FN_SD1_DATA1, NULL); - gpio_request(GPIO_FN_SD1_DATA2, NULL); - gpio_request(GPIO_FN_SD1_DATA3, NULL); - gpio_request(GPIO_FN_SD1_CLK, NULL); - gpio_request(GPIO_FN_SD1_CMD, NULL); - gpio_request(GPIO_FN_SD1_CD, NULL); - - /* SDHI 1 */ - gpio_request(GPIO_GP_4_26, NULL); - gpio_request(GPIO_GP_4_29, NULL); - gpio_direction_output(GPIO_GP_4_26, 1); - gpio_direction_output(GPIO_GP_4_29, 1); - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); -#endif - return ret; + fdtdec_setup_memory_banksize(); + + return 0; } -int dram_init(void) +/* porter has KSZ8041RNLI */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); return 0; } @@ -197,22 +112,38 @@ const struct rmobile_sysinfo sysinfo = { void reset_cpu(ulong addr) { - u8 val; + struct udevice *dev; + const u8 pmic_bus = 1; + const u8 pmic_addr = 0x58; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); - i2c_set_bus_num(1); /* PowerIC connected to ch1 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + data |= BIT(1); + + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } -static const struct sh_serial_platdata serial_platdata = { - .base = SCIF2_BASE, - .type = PORT_SCIF, - .clk = 14745600, - .clk_mode = EXT_CLK, -}; +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; -U_BOOT_DEVICE(silk_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/silk/silk_spl.c b/board/renesas/silk/silk_spl.c new file mode 100644 index 0000000000..5309ce9f08 --- /dev/null +++ b/board/renesas/silk/silk_spl.c @@ -0,0 +1,425 @@ +/* + * board/renesas/silk/silk_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF2_MSTP719 BIT(19) +#define QSPI_MSTP917 BIT(17) + +#define SD1CKCR 0xE6150078 +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x00018040 }, + { 0x0094, 0x00000000 }, + { 0x0098, 0x00000000 }, + { 0x0020, 0x94000000 }, + { 0x0024, 0x00000006 }, + { 0x0028, 0x40000000 }, + { 0x002c, 0x00000155 }, + { 0x0030, 0x00000002 }, + { 0x0034, 0x00000000 }, + { 0x0038, 0x00000000 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x60000000 }, + { 0x0044, 0x36dab6db }, + { 0x0048, 0x926da012 }, + { 0x004c, 0x0008c383 }, + { 0x0050, 0x00000000 }, + { 0x0054, 0x00000140 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x00ec3fff }, + { 0x000c, 0x5bffffff }, + { 0x0010, 0x01bfe1ff }, + { 0x0014, 0x5bffffff }, + { 0x0018, 0x0f4b200f }, + { 0x001c, 0x03ffffff }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0x00000000 }, + { 0x0104, 0x4203fdf0 }, + { 0x0108, 0x00000000 }, + { 0x010c, 0x159007ff }, + { 0x0110, 0x80000000 }, + { 0x0114, 0x00de481f }, + { 0x0118, 0x00000000 }, + }; + + static const struct reg_config pfc_with_unlock2[] = { + { 0x0060, 0xffffffff }, + { 0x0064, 0xfffff000 }, + { 0x0068, 0x55555500 }, + { 0x006c, 0xffffff00 }, + { 0x0070, 0x00000000 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) { + writel(~pfc_with_unlock2[i].val, pfc_base); + writel(pfc_with_unlock2[i].val, + pfc_base | pfc_with_unlock2[i].off); + } +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x2000, 0x3000, 0x4000 + }; + + static const struct reg_config gpio_set[] = { + { 0x2000, 0x24000000 }, + { 0x4000, 0xa4000000 }, + { 0x5000, 0x0084c000 }, + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x01000000 }, + { 0x2000, 0x24000000 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0xa4000000 }, + { 0x5000, 0x00044380 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + writel(BIT(23), gpio_base | 0x5020); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + writel(BIT(23), gpio_base | 0x5000); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x2a103320 }, + { 0x38, 0xff70ff70 }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0280, 0x0000a55a }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x80000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config2[] = { + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0005c000 }, + }; + + static const struct reg_config dbsc_config3r2[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181224 }, + }; + + static const struct reg_config dbsc_config4[] = { + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf004649b }, + { 0x0290, 0x00000061 }, + { 0x02a0, 0x0000006d }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000073 }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x00000009 }, + { 0x0044, 0x00000007 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x00000009 }, + { 0x0054, 0x000a0009 }, + { 0x0058, 0x00000021 }, + { 0x005c, 0x00000018 }, + { 0x0060, 0x00000005 }, + { 0x0064, 0x00000020 }, + { 0x0068, 0x00000007 }, + { 0x006c, 0x0000000a }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000010 }, + { 0x0078, 0x000000ae }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x50213005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000200 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20042004 }, + { 0x0380, 0x00020003 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c4e1 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fcb6d0 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x85589955 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a852400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300210b4 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000b50 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000010 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x012c00be }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081450 }, + { 0x00e8, 0x00010000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0014, 0x00000001 }, + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf00464db }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) + writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); + + for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) { + writel(dbsc_config3r2[i].val, + dbsc3_0_base | dbsc_config3r2[i].off); + } + + for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) + writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* Set SD1 to the 97.5MHz */ + writel(SD_97500KHZ, SD1CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/stout/Makefile b/board/renesas/stout/Makefile index cb7c61d020..b8875bb7b9 100644 --- a/board/renesas/stout/Makefile +++ b/board/renesas/stout/Makefile @@ -8,4 +8,8 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := stout.o cpld.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := stout_spl.o +else +obj-y := stout.o cpld.o qos.o +endif diff --git a/board/renesas/stout/cpld.c b/board/renesas/stout/cpld.c index 5640e1d28e..fc1e30ca57 100644 --- a/board/renesas/stout/cpld.c +++ b/board/renesas/stout/cpld.c @@ -13,10 +13,10 @@ #include <asm/gpio.h> #include "cpld.h" -#define SCLK GPIO_GP_3_24 -#define SSTBZ GPIO_GP_3_25 -#define MOSI GPIO_GP_3_26 -#define MISO GPIO_GP_3_27 +#define SCLK (92 + 24) +#define SSTBZ (92 + 25) +#define MOSI (92 + 26) +#define MISO (92 + 27) #define CPLD_ADDR_MODE 0x00 /* RW */ #define CPLD_ADDR_MUX 0x01 /* RW */ @@ -91,10 +91,10 @@ void cpld_init(void) val |= PUPR3_SD3_DAT1; writel(val, PUPR3); - gpio_request(SCLK, NULL); - gpio_request(SSTBZ, NULL); - gpio_request(MOSI, NULL); - gpio_request(MISO, NULL); + gpio_request(SCLK, "SCLK"); + gpio_request(SSTBZ, "SSTBZ"); + gpio_request(MOSI, "MOSI"); + gpio_request(MISO, "MISO"); gpio_direction_output(SCLK, 0); gpio_direction_output(SSTBZ, 1); diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c index d681148273..192ee66a38 100644 --- a/board/renesas/stout/stout.c +++ b/board/renesas/stout/stout.c @@ -14,6 +14,7 @@ #include <netdev.h> #include <dm.h> #include <dm/platform_data/serial_sh.h> +#include <environment.h> #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> @@ -58,14 +59,7 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIFA0_MSTP204 (1 << 4) -#define SDHI0_MSTP314 (1 << 14) -#define SDHI2_MSTP312 (1 << 12) -#define ETHER_MSTP813 (1 << 13) - -#define MSTPSR3 0xE6150048 -#define SMSTPCR3 0xE615013C +#define TMU0_MSTP125 BIT(25) #define SD2CKCR 0xE6150078 #define SD2_97500KHZ 0x7 @@ -74,12 +68,6 @@ int board_early_init_f(void) { /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIFA0 */ - mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - /* SDHI0,2 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); /* * SD0 clock is set to 97.5MHz by default. @@ -90,66 +78,37 @@ int board_early_init_f(void) return 0; } +#define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */ + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7790_pinmux_init(); - cpld_init(); -#ifdef CONFIG_SH_ETHER - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REF_CLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_MAGIC, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ1, NULL); - - gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */ - gpio_direction_output(GPIO_GP_3_31, 0); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); mdelay(20); - gpio_set_value(GPIO_GP_3_31, 1); - udelay(1); -#endif + gpio_direction_output(ETHERNET_PHY_RESET, 1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { - int ret = -ENODEV; + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; -#ifdef CONFIG_SH_ETHER - u32 val; - unsigned char enetaddr[6]; - - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); + return 0; +} - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); -#endif +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); - return ret; + return 0; } /* Stout has KSZ8041NL/RNL */ @@ -166,67 +125,21 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int board_mmc_init(bd_t *bis) -{ - int ret = -ENODEV; - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD0_DAT0, NULL); - gpio_request(GPIO_FN_SD0_DAT1, NULL); - gpio_request(GPIO_FN_SD0_DAT2, NULL); - gpio_request(GPIO_FN_SD0_DAT3, NULL); - gpio_request(GPIO_FN_SD0_CLK, NULL); - gpio_request(GPIO_FN_SD0_CMD, NULL); - gpio_request(GPIO_FN_SD0_CD, NULL); - gpio_request(GPIO_FN_SD2_DAT0, NULL); - gpio_request(GPIO_FN_SD2_DAT1, NULL); - gpio_request(GPIO_FN_SD2_DAT2, NULL); - gpio_request(GPIO_FN_SD2_DAT3, NULL); - gpio_request(GPIO_FN_SD2_CLK, NULL); - gpio_request(GPIO_FN_SD2_CMD, NULL); - gpio_request(GPIO_FN_SD2_CD, NULL); - - /* SDHI0 - needs CPLD mux setup */ - gpio_request(GPIO_GP_3_30, NULL); - gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */ - gpio_request(GPIO_GP_5_24, NULL); - gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, - SH_SDHI_QUIRK_16BIT_BUF); - if (ret) - return ret; - - /* SDHI2 - needs CPLD mux setup */ - gpio_request(GPIO_GP_3_29, NULL); - gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */ - gpio_request(GPIO_GP_5_25, NULL); - gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); -#endif - return ret; -} - - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} - const struct rmobile_sysinfo sysinfo = { CONFIG_ARCH_RMOBILE_BOARD_STRING }; -static const struct sh_serial_platdata serial_platdata = { - .base = SCIFA0_BASE, - .type = PORT_SCIFA, - .clk = CONFIG_MP_CLK_FREQ, -}; +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; -U_BOOT_DEVICE(stout_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/stout/stout_spl.c b/board/renesas/stout/stout_spl.c new file mode 100644 index 0000000000..ed443fdcc2 --- /dev/null +++ b/board/renesas/stout/stout_spl.c @@ -0,0 +1,477 @@ +/* + * board/renesas/stout/stout_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIFA0_MSTP204 BIT(4) +#define QSPI_MSTP917 BIT(17) + +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; + + while (!(readl(dbsc3_1_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x00140300 }, + { 0x0094, 0x09500000 }, + { 0x0098, 0xc0000084 }, + { 0x0020, 0x01a33492 }, + { 0x0024, 0x10000000 }, + { 0x0028, 0x08449252 }, + { 0x002c, 0x2925b322 }, + { 0x0030, 0x0c311249 }, + { 0x0034, 0x10124000 }, + { 0x0038, 0x00001295 }, + { 0x003c, 0x50890000 }, + { 0x0040, 0x0eaa56aa }, + { 0x0044, 0x55550000 }, + { 0x0048, 0x00000005 }, + { 0x004c, 0x54800000 }, + { 0x0050, 0x3736db55 }, + { 0x0054, 0x29148da3 }, + { 0x0058, 0x48c446e1 }, + { 0x005c, 0x2a3a54dc }, + { 0x0160, 0x00000023 }, + { 0x0004, 0xfca0ffff }, + { 0x0008, 0x3fbffbf0 }, + { 0x000c, 0x3ffdffff }, + { 0x0010, 0x00ffffff }, + { 0x0014, 0xfc3ffff3 }, + { 0x0018, 0xe4fdfff7 }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0104, 0xffffbfff }, + { 0x0108, 0xb1ffffe1 }, + { 0x010c, 0xffffffff }, + { 0x0110, 0xffffffff }, + { 0x0114, 0xe047beab }, + { 0x0118, 0x00000203 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x3000, 0x4000, 0x5000 + }; + + static const struct reg_config gpio_set[] = { + { 0x4000, 0x00c00000 }, + { 0x5000, 0x63020000 }, + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x00000000 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0x00c00000 }, + { 0x5000, 0xe3020000 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x02150326 }, + { 0x38, 0x077f077f }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0280, 0x0000a55a }, + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x80000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config2[] = { + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0001c000 }, + }; + + static const struct reg_config dbsc_config3r0d0[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181885 }, + { 0x0290, 0x00000070 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000080 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000090 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x000000a0 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x000000b0 }, + { 0x02a0, 0x7c000880 }, + { 0x0290, 0x000000c0 }, + { 0x02a0, 0x7c000880 }, + { 0x0290, 0x000000d0 }, + { 0x02a0, 0x7c000880 }, + { 0x0290, 0x000000e0 }, + { 0x02a0, 0x7c000880 }, + }; + + static const struct reg_config dbsc_config3r0d1[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181885 }, + { 0x0290, 0x00000070 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000080 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x00000090 }, + { 0x02a0, 0x7c000887 }, + { 0x0290, 0x000000a0 }, + { 0x02a0, 0x7c000887 }, + }; + + static const struct reg_config dbsc_config3r2[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181224 }, + }; + + static const struct reg_config dbsc_config4[] = { + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf004649b }, + { 0x0290, 0x00000061 }, + { 0x02a0, 0x0000006d }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000073 }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x0000000b }, + { 0x0044, 0x00000008 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x0000000b }, + { 0x0054, 0x000c000b }, + { 0x0058, 0x00000027 }, + { 0x005c, 0x0000001c }, + { 0x0060, 0x00000006 }, + { 0x0064, 0x00000020 }, + { 0x0068, 0x00000008 }, + { 0x006c, 0x0000000c }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000012 }, + { 0x0078, 0x000000d0 }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x70233005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000200 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20042004 }, + { 0x0380, 0x00020002 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c4e1 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fcdb60 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x9d9cbb66 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a868400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300214d8 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000d70 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000018 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x014000aa }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081860 }, + { 0x00e8, 0x00010000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0014, 0x00000001 }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000; + static const u32 prr_base = 0xff000044; + const u16 prr_rev = readl(prr_base) & 0x7fff; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) { + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) { + writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); + writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off); + } + + if (prr_rev == 0x4500) { + for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) { + writel(dbsc_config3r0d0[i].val, + dbsc3_0_base | dbsc_config3r0d0[i].off); + } + for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) { + writel(dbsc_config3r0d1[i].val, + dbsc3_1_base | dbsc_config3r0d1[i].off); + } + } else if (prr_rev != 0x4510) { + for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) { + writel(dbsc_config3r2[i].val, + dbsc3_0_base | dbsc_config3r2[i].off); + writel(dbsc_config3r2[i].val, + dbsc3_1_base | dbsc_config3r2[i].off); + } + } + + for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) { + writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); + writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off); + } + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) { + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) { + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) { + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off); + } + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) { + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off); + } + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD2CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index 790a921515..0f2abe2f53 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <i2c_eeprom.h> #include <netdev.h> diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c index cced08b8b8..0cc842116d 100644 --- a/board/samtec/vining_2000/vining_2000.c +++ b/board/samtec/vining_2000/vining_2000.c @@ -18,6 +18,7 @@ #include <asm/mach-imx/mxc_i2c.h> #include <linux/sizes.h> #include <common.h> +#include <environment.h> #include <fsl_esdhc.h> #include <mmc.h> #include <i2c.h> diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c index 229b12f308..14ac7efb8b 100644 --- a/board/samtec/vining_fpga/socfpga.c +++ b/board/samtec/vining_fpga/socfpga.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <environment.h> #include <asm/arch/reset_manager.h> #include <asm/io.h> #include <asm/gpio.h> diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c index 7fa2673c2b..f3e82d4f18 100644 --- a/board/siemens/common/factoryset.c +++ b/board/siemens/common/factoryset.c @@ -9,6 +9,7 @@ #if !defined(CONFIG_SPL_BUILD) #include <common.h> +#include <environment.h> #include <i2c.h> #include <asm/io.h> #include <asm/arch/cpu.h> diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 8bbb03561b..ab54e58861 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -14,6 +14,7 @@ */ #include <common.h> +#include <environment.h> #include <errno.h> #include <spl.h> #include <asm/arch/cpu.h> diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c index 0429e6f0c7..e736afbf93 100644 --- a/board/silica/pengwyn/board.c +++ b/board/silica/pengwyn/board.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <environment.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/ddr_defs.h> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index ee9e4f7c01..727b639943 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -428,7 +428,7 @@ static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { .dram_sdclk_1 = 0x00020030, .dram_cas = 0x00020030, .dram_ras = 0x00020030, - .dram_reset = 0x00020030, + .dram_reset = 0x000c0030, .dram_sdcke0 = 0x00003000, .dram_sdcke1 = 0x00003000, .dram_sdba2 = 0x00000000, @@ -584,7 +584,6 @@ static struct mx6_ddr3_cfg mem_ddr_2g = { .trcd = 1375, .trcmin = 4875, .trasmin = 3500, - .SRT = 1, }; static struct mx6_ddr3_cfg mem_ddr_4g = { diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c index e5bec57f4f..c4dad69110 100644 --- a/board/technologic/ts4800/ts4800.c +++ b/board/technologic/ts4800/ts4800.c @@ -17,6 +17,7 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> #include <asm/mach-imx/mx5_video.h> +#include <environment.h> #include <mmc.h> #include <input.h> #include <fsl_esdhc.h> diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index c6690fa069..1d8b605b69 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <misc.h> #include <spl.h> #include <syscon.h> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7f0fb5d2ba..c33bf58ddc 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -563,8 +563,8 @@ void sdram_init(void) } #endif -#if !defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) static void request_and_set_gpio(int gpio, char *name, int val) { int ret; @@ -621,8 +621,8 @@ int board_init(void) gpmc_init(); #endif -#if !defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +#if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) if (board_is_icev2()) { int rv; u32 reg; diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 0564df2c00..0431cd4606 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <i2c.h> #include <linux/errno.h> #include <spl.h> diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index cdde6a8ca3..4a0f82975a 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -10,6 +10,7 @@ #include <common.h> #include <cpsw.h> +#include <environment.h> #include <errno.h> #include <spl.h> #include <asm/arch/cpu.h> diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index cb40cc5f47..abc961a86e 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <environment.h> #include <spl.h> #include <netdev.h> #include <asm/cache.h> diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 741b3acce2..4bbbd81848 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -18,6 +18,7 @@ */ #include <common.h> #include <dm.h> +#include <environment.h> #include <ns16550.h> #include <twl4030.h> #include <asm/io.h> diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 6e12d279e8..d6d367161c 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <environment.h> #include <g_dnl.h> #include <linux/libfdt.h> diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 1e7c11e670..b7c6c6cb18 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -28,7 +28,6 @@ #include <miiphy.h> #include <netdev.h> #include <phy.h> -#include <input.h> #include <i2c.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index d422d63df5..327f656c44 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -23,6 +23,8 @@ #include <power/pmic.h> #include <power/pfuze3000_pmic.h> #include "../freescale/common/pfuze.h" +#include <asm/setup.h> +#include <asm/bootm.h> DECLARE_GLOBAL_DATA_PTR; @@ -186,6 +188,10 @@ int board_usb_phy_mode(int port) int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; +#ifdef CONFIG_SERIAL_TAG + struct tag_serialnr serialnr; + char serial_string[0x20]; +#endif imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); @@ -197,5 +203,13 @@ int board_late_init(void) */ clrsetbits_le16(&wdog->wcr, 0, 0x10); +#ifdef CONFIG_SERIAL_TAG + /* Set serial# standard environment variable based on OTP settings */ + get_board_serial(&serialnr); + snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x", + serialnr.low, serialnr.high); + env_set("serial#", serial_string); +#endif + return 0; } diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 838ac0f4c4..2f4679e211 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -184,7 +184,8 @@ int dram_init(void) #else int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); zynq_ddrc_init(); diff --git a/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c new file mode 100644 index 0000000000..cb8ec25e6e --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c @@ -0,0 +1,745 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F0E2412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D0419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000802U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x281C0404U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070200U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320E08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0x0000003FU, 0x00000000U); + psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0000807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD402374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40237C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD406374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40637C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD402360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD406360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40506C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD401928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD401900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD405990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD405924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD405928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD405900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000022U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401C14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD401C40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40194C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD405C14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD405C40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40594C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD405950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000001U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD4063E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U); + psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFF9B0000, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U); + psu_mask_write(0xFF9B0014, 0x00000003U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + Xil_Out32(0xFD070180U, 0x00AB002BU); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = + L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) | 0x20 | 0x4 | + ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = + L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) | 0x40 | 0x8 | + ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + unsigned int tmp_regval; + + tmp_regval = Xil_In32(0xFD690040); + tmp_regval &= ~0x00000001; + Xil_Out32(0xFD690040, tmp_regval); + + tmp_regval = Xil_In32(0xFD690030); + tmp_regval &= ~0x00000001; + Xil_Out32(0xFD690030, tmp_regval); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c new file mode 100644 index 0000000000..2c845874d5 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c @@ -0,0 +1,467 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E60EC6CU); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013000U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000300U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010802U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020204U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x003800D4U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x0000003DU); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x64032010U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x38801C20U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0604U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00040200U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000300U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + Xil_Out32(0xFD070180U, 0x00800020U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zc1275-revA b/board/xilinx/zynqmp/zynqmp-zc1275-revA new file mode 120000 index 0000000000..7abf1dc462 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1275-revA @@ -0,0 +1 @@ +zynqmp-zc1254-revA
\ No newline at end of file diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c new file mode 100644 index 0000000000..ab106c6c3d --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c @@ -0,0 +1,912 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFC7FE07FU, 0x54000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03004U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); + psu_mask_write(0xFF180320, 0x33803380U, 0x02801280U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000011U); + psu_mask_write(0xFD402860, 0x00000084U, 0x00000004U); + psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U); + psu_mask_write(0xFD402868, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000018U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000D3U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000DAU); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000096U); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000096U); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000096U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184D1BU); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081906U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F122E7U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c new file mode 100644 index 0000000000..bcf3aedfbc --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c @@ -0,0 +1,900 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U); + psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U); + psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U); + psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U); + psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U); + psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U); + psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U); + psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U); + psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U); + psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U); + psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U); + psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U); + psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U); + psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U); + psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U); + psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U); + psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U); + psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U); + psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U); + psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U); + psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U); + psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD4063E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U); + psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F122E7U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c new file mode 100644 index 0000000000..bcf3aedfbc --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c @@ -0,0 +1,900 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U); + psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U); + psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U); + psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U); + psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U); + psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U); + psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U); + psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U); + psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U); + psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U); + psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U); + psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U); + psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U); + psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U); + psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U); + psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U); + psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U); + psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U); + psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U); + psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U); + psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U); + psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD4063E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U); + psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F122E7U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c new file mode 100644 index 0000000000..bcf3aedfbc --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c @@ -0,0 +1,900 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0058, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0084, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B4, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000A0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000A0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xEC000C00U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0xFC000642U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000F807CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00010000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000000U); + psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0238, 0x00000180U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000084U, 0x00000004U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD480314, 0xFFFFFFFFU, 0x00000004U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000041U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480020, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480030, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480038, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480040, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480044, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480048, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48006C, 0x00000738U, 0x00000138U); + psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000000U); + psu_mask_write(0xFD4801A4, 0x000007FFU, 0x00000172U); + psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000248U); + psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000008U); + psu_mask_write(0xFD4801B0, 0x000007FFU, 0x00000020U); + psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E04U); + psu_mask_write(0xFD480088, 0x0000FFFFU, 0x00000100U); + psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U); + psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000060U); + psu_mask_write(0xFD480184, 0x00000FFFU, 0x00000041U); + psu_mask_write(0xFD480190, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD480194, 0x0000FFE2U, 0x00000000U); + psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U); + psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U); + psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U); + psu_mask_write(0xFD480064, 0x000001FFU, 0x00000105U); + psu_mask_write(0xFD0E0000, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U); + psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U); + psu_mask_write(0xFD4800AC, 0x00000F00U, 0x00000000U); + psu_mask_write(0xFD4800B4, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U); + psu_mask_write(0xFD480094, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U); + mask_poll(0xFD4023E4, 0x00000010U); + mask_poll(0xFD4063E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U); + psu_mask_write(0xFF5E0230, 0x00000004U, 0x00000004U); + psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F122E7U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c new file mode 100644 index 0000000000..8e62a9c040 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c @@ -0,0 +1,926 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U); + psu_mask_write(0xFF18030C, 0x00000003U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x110C2412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28170008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000060U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x000000E0U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0xAF000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x0003F000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000240U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000E807CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000020U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180320, 0x00003380U, 0x00000080U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000800U); + psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000800U); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U); + mask_delay(1); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0000U); + mask_delay(5); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD4010CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD401924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD401928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD405990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD405924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD405928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD409928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000011U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x00000004U); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD3D001C, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000011U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000011U); + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x000C0000U, 0x00000000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + psu_mask_write(0xFD48001C, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480020, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480024, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480028, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD48002C, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD480030, 0x0000FFFFU, 0x000000FFU); + psu_mask_write(0xFD480034, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD480038, 0x0000FFFFU, 0x0000FFFFU); + psu_mask_write(0xFD48003C, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480040, 0x0000FFFFU, 0x0000FFF0U); + psu_mask_write(0xFD480044, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD480048, 0x0000FFFFU, 0x0000FFF1U); + psu_mask_write(0xFD48006C, 0x00000738U, 0x00000100U); + psu_mask_write(0xFD4800C8, 0x0000FFF0U, 0x00000040U); + psu_mask_write(0xFD4801A4, 0x000007FFU, 0x000000CDU); + psu_mask_write(0xFD4801A8, 0x00003FFFU, 0x00000624U); + psu_mask_write(0xFD4801AC, 0x000007FFU, 0x00000018U); + psu_mask_write(0xFD4801B0, 0x000007FFU, 0x000000B5U); + psu_mask_write(0xFD4801B4, 0x0000FFFFU, 0x00007E20U); + psu_mask_write(0xFD480088, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD4800D4, 0x000000FFU, 0x00000060U); + psu_mask_write(0xFD4800A4, 0x000003FFU, 0x00000000U); + psu_mask_write(0xFD480190, 0x00000040U, 0x00000000U); + psu_mask_write(0xFD480194, 0x0000FFE2U, 0x0000FFE2U); + psu_mask_write(0xFD480094, 0x00004200U, 0x00004200U); + psu_mask_write(0xFD480174, 0x0000FFFFU, 0x00009000U); + psu_mask_write(0xFD480200, 0xFFFFFFFFU, 0x10EED011U); + psu_mask_write(0xFD480204, 0xFFFFFFFFU, 0x10EE0007U); + psu_mask_write(0xFD480208, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD480060, 0x0000FFFFU, 0x00008000U); + psu_mask_write(0xFD480064, 0x000001FFU, 0x00000006U); + psu_mask_write(0xFD480010, 0x00001000U, 0x00000000U); + psu_mask_write(0xFD480164, 0x00001FFEU, 0x00000000U); + psu_mask_write(0xFD48013C, 0x00000020U, 0x00000000U); + psu_mask_write(0xFD4800AC, 0x00000100U, 0x00000000U); + psu_mask_write(0xFD4800C0, 0x000007FFU, 0x00000000U); + psu_mask_write(0xFD4800B8, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800BC, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD4800B0, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD4800B4, 0x0000FFF8U, 0x00000000U); + psu_mask_write(0xFD48031C, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD48008C, 0x00003000U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xF7FF0800U); + mask_poll(0xFD4023E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x000E0000U, 0x000E0000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F122E7U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int rdata = 0; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + int count = 0; + + rdata = Xil_In32(0xFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0xFD40289C, rdata); + + do { + if (count == 1100000) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + } while ((rdata & 0x0000000E) != 0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c new file mode 100644 index 0000000000..27e2ab6de9 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c @@ -0,0 +1,993 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0080, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000400U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC3081020U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000102U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x0028B090U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00404310U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00208030U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x0002020AU); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00360000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00001205U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00240012U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0E0B010CU); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00030412U); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x04070F0DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00A05000U); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x05040306U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01020404U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000201U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030303U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x810B0008U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x00E32DCBU); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8206U); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00A00070U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000901U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x00000015U); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F060606U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F03D28U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x85642AD0U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xA0AA0580U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x05102000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A040A1U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06180C08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x2816050AU); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080064U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00602B08U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00231008U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x0000080EU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000024U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000012U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x810091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00030236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x00894C58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00BD0CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00BD0CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00BD0CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00BD0CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00BD0CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x05102000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x05102000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x05102000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x05102000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x05102000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x71000000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x05102000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + psu_mask_write(0xFD090000, 0x0000FFFFU, 0x00000845U); + psu_mask_write(0xFD090004, 0x002DB5ADU, 0x002DB5ADU); + psu_mask_write(0xFD090800, 0xFFFFFFFFU, 0x00000001U); + psu_mask_write(0xFD09000C, 0x0000007FU, 0x00000010U); + psu_mask_write(0xFD090010, 0x0000007FU, 0x00000010U); + psu_mask_write(0xFD380008, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD38001C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD390008, 0x0000000FU, 0x00000003U); + psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000003U); + psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000003U); + psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000003U); + psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000003U); + psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000003U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000080U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x51000006U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B00000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x039E1FFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0001007CU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000FC0U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33803380U, 0x00800080U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD402868, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD40286C, 0x00000081U, 0x00000001U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40E094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40E37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40D06C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40C0F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D0CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000033U); + psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U); + psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFE30C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + Xil_Out32(0xFD090000U, 0x00000845U); + Xil_Out32(0xFD090004U, 0x003FFFFFU); + Xil_Out32(0xFD09000CU, 0x00000010U); + Xil_Out32(0xFD090010U, 0x00000010U); + Xil_Out32(0xFD090800U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + + Xil_Out32(0xFD070010U, 0x80000038U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000331U); + Xil_Out32(0xFD070010U, 0x80000038U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000B36U); + Xil_Out32(0xFD070010U, 0x80000038U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000C21U); + Xil_Out32(0xFD070010U, 0x80000038U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00000E19U); + Xil_Out32(0xFD070010U, 0x80000038U); + regval = Xil_In32(0xFD070018); + while ((regval & 0x1) != 0x0) + regval = Xil_In32(0xFD070018); + + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + regval = Xil_In32(0xFD070018); + Xil_Out32(0xFD070014U, 0x00001616U); + Xil_Out32(0xFD070010U, 0x80000038U); + Xil_Out32(0xFD070010U, 0x80000030U); + Xil_Out32(0xFD0701B0U, 0x00000005U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0014FE01); + + regval = Xil_In32(0xFD080030); + while (regval != 0x8000007E) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x010091C7U); + regval = Xil_In32(0xFD080030); + while (regval != 0x80008FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x810091C7U); + Xil_Out32(0xFD070180U, 0x010B0008U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD070020U, 0x00000001U, 0x00000000U, 0x00000001U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x0000001FU, 0x0000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c new file mode 100644 index 0000000000..aa6496c0b8 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c @@ -0,0 +1,826 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E514C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00013900U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000820CU); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010402U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010302U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000600FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000600FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000600FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000600FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000600FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000600FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000600FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x008005F0U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04121U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28220708U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00080200U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B08U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00340F09U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A2A58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080788, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0807C0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080888, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0808C0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080988, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0809C0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A88, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080AC0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B88, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080BC0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C88, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080CC0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D88, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080DC0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E88, 0xFFFFFFFFU, 0x0000000AU); + psu_mask_write(0xFD080EC0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F88, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080FC0, 0xFFFFFFFFU, 0x00020000U); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U); + psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0xC5ACCE55U); + psu_mask_write(0xFE980004, 0x80000000U, 0x80000000U); + psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00003FBFU, 0x00002417U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + int dpll_divisor; + + dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U; + prog_reg(0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U); + prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); + Xil_Out32(0xFD080004U, 0x00040003U); + while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U) + ; + prog_reg(0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U); + prog_reg(0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U); + prog_reg(0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U); + prog_reg(0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U); + prog_reg(0xFD1A0080, 0x3F00, 0x8, dpll_divisor); + Xil_Out32(0xFD080004U, 0x40040071U); + while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U) + ; + Xil_Out32(0xFD080004U, 0x40040001U); + while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U) + ; + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EF2U); + Xil_Out32(0xFD08001CU, 0x55AA5498U); + Xil_Out32(0xFD08142CU, 0x00041830U); + Xil_Out32(0xFD08146CU, 0x00041830U); + Xil_Out32(0xFD0814ACU, 0x00041830U); + Xil_Out32(0xFD0814ECU, 0x00041830U); + Xil_Out32(0xFD08152CU, 0x00041830U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F12302U); + Xil_Out32(0xFD08001CU, 0x55AA5480U); + Xil_Out32(0xFD08142CU, 0x00041800U); + Xil_Out32(0xFD08146CU, 0x00041800U); + Xil_Out32(0xFD0814ACU, 0x00041800U); + Xil_Out32(0xFD0814ECU, 0x00041800U); + Xil_Out32(0xFD08152CU, 0x00041800U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod; + + Xil_Out32(0xFD40EC4C, 0x00000020); + + Xil_Out32(0xFD410010, 0x00000001); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + + if (maskstatus == 0) { + /* xil_printf("SERDES initialization timed out\n\r"); */ + return maskstatus; + } + + tmp_0_1 = mask_read(0xFD400B0C, 0x3F); + + tmp_0_2 = tmp_0_1 & (0x7); + tmp_0_3 = tmp_0_1 & (0x38); + + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + tmp_0_2_mod = (tmp_0_2 << 1) | (0x1); + tmp_0_2_mod = (tmp_0_2_mod << 4); + + tmp_0_3 = tmp_0_3 >> 3; + Xil_Out32(0xFD40EC4C, tmp_0_3); + + Xil_Out32(0xFD40EC48, tmp_0_2_mod); + return maskstatus; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + unsigned int regvalue; + unsigned int tmp_regval; + + Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000); + Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000); + Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000); + + regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU)); + regvalue &= 0x7; + Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue); + + Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000); + + tmp_regval = Xil_In32(0xFD690040); + tmp_regval &= ~0x00000001; + Xil_Out32(0xFD690040, tmp_regval); + + tmp_regval = Xil_In32(0xFD690030); + tmp_regval &= ~0x00000001; + Xil_Out32(0xFD690030, tmp_regval); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + + status &= init_serdes(); + init_peripheral(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c new file mode 100644 index 0000000000..b7e0300ce2 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c @@ -0,0 +1,878 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010400U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11102412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060DU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002030BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x7007010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07240F08U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F08U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0x7B3F003FU, 0x52240000U); + psu_mask_write(0xFF180208, 0xFFFFE000U, 0x00B02000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33800000U, 0x00800000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U); + psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16)); + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F122E7U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int match_pmos_code[23]; + unsigned int match_nmos_code[23]; + unsigned int match_ical_code[7]; + unsigned int match_rcal_code[7]; + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; + int i = 0; + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + do { + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + if (maskstatus == 0) { + /* xil_printf("#SERDES initialization timed out\n\r");*/ + return maskstatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); + ; + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); + ; + + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + } while (repeat_count++ < 10); + + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return maskstatus; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + status &= init_serdes(); + + status &= psu_afi_config(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revC b/board/xilinx/zynqmp/zynqmp-zcu104-revC new file mode 120000 index 0000000000..529e18f52d --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zcu104-revC @@ -0,0 +1 @@ +zynqmp-zcu104-revA
\ No newline at end of file diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c new file mode 100644 index 0000000000..e6fa477e53 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c @@ -0,0 +1,802 @@ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015900U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x80008E69U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010502U); + psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0088, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A02U); + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010A02U); + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010A02U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0082808BU); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09300301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00200200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x11112412U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041AU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0708060EU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030309U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D06U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002020BU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x6F07010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02019707U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B820BU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E2U); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000808U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10028U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x5E001810U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41980B06U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x06240F09U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28210008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B07U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330F09U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000E0FU); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000830U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000020U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U); + + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000020U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x52240000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B03000U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFF5E0238, 0x00100000U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x0001807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U); + psu_mask_write(0xFF18031C, 0x7F800000U, 0x63800000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000100U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + + return 1; +} + +static unsigned long psu_serdes_init_data(void) +{ + psu_mask_write(0xFD410000, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410004, 0x0000001FU, 0x00000009U); + psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U); + psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU); + psu_mask_write(0xFD402860, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD402864, 0x00000088U, 0x00000008U); + psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40286C, 0x00000082U, 0x00000002U); + psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U); + psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U); + psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD406368, 0x000000FFU, 0x00000058U); + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U); + psu_mask_write(0xFD402370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD402374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40237C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD406370, 0x000000FFU, 0x0000007CU); + psu_mask_write(0xFD406374, 0x000000FFU, 0x00000033U); + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U); + psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U); + psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U); + psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U); + psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U); + psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U); + psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U); + psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU); + psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU); + psu_mask_write(0xFD40CB00, 0x000000F0U, 0x000000F0U); + psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U); + psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU); + psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU); + psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U); + psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU); + psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U); + psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); + psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU); + psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U); + psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U); + psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD401978, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD405978, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD409978, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD40D978, 0x00000080U, 0x00000080U); + psu_mask_write(0xFD410010, 0x00000077U, 0x00000044U); + psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U); + psu_mask_write(0xFD400CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD404CB4, 0x00000037U, 0x00000037U); + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U); + psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU); + psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U); + psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U); + psu_mask_write(0xFD404CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD400CC0, 0x0000001FU, 0x00000000U); + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U); + + return 1; +} + +static unsigned long psu_resetout_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U); + psu_mask_write(0xFE20C200, 0x00003FFFU, 0x00002457U); + psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U); + psu_mask_write(0xFE20C11C, 0x00000400U, 0x00000400U); + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); + mask_poll(0xFD4063E4, 0x00000010U); + mask_poll(0xFD40A3E4, 0x00000010U); + mask_poll(0xFD40E3E4, 0x00000010U); + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U); + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U); + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U); + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U); + + return 1; +} + +static unsigned long psu_resetin_init_data(void) +{ + psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU); + psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U); + psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD080200U, 0x100091C7U); + Xil_Out32(0xFD080018U, 0x00F01EF2U); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + Xil_Out32(0xFD080018U, 0x00F12302U); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static int serdes_fixcal_code(void) +{ + int maskstatus = 1; + unsigned int tmp_0_1, tmp_0_2, tmp_0_3, tmp_0_2_mod; + + Xil_Out32(0xFD40EC4C, 0x00000020); + + Xil_Out32(0xFD410010, 0x00000001); + + maskstatus = mask_poll(0xFD40EF14, 0x2); + + if (maskstatus == 0) { + xil_printf("SERDES initialization timed out\n\r"); + return maskstatus; + } + + tmp_0_1 = mask_read(0xFD400B0C, 0x3F); + + tmp_0_2 = tmp_0_1 & (0x7); + tmp_0_3 = tmp_0_1 & (0x38); + + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + tmp_0_2_mod = (tmp_0_2 << 1) | (0x1); + tmp_0_2_mod = (tmp_0_2_mod << 4); + + tmp_0_3 = tmp_0_3 >> 3; + Xil_Out32(0xFD40EC4C, tmp_0_3); + + Xil_Out32(0xFD40EC48, tmp_0_2_mod); + return maskstatus; +} + +static int serdes_enb_coarse_saturation(void) +{ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +static int init_serdes(void) +{ + int status = 1; + + status &= psu_resetin_init_data(); + + status &= serdes_fixcal_code(); + status &= serdes_enb_coarse_saturation(); + + status &= psu_serdes_init_data(); + status &= psu_resetout_init_data(); + + return status; +} + +static void init_peripheral(void) +{ + unsigned int regvalue; + unsigned int tmp_regval; + + Xil_Out32(((0xFF5E0000U) + 0x00000230U), 0x00000000); + Xil_Out32(((0xFF5E0000U) + 0x00000234U), 0x00000000); + Xil_Out32(((0xFF5E0000U) + 0x00000238U), 0x00000000); + + regvalue = Xil_In32(((0xFF5E0000U) + 0x0000023CU)); + regvalue &= 0x7; + Xil_Out32(((0xFF5E0000U) + 0x0000023CU), regvalue); + + Xil_Out32(((0xFD1A0000U) + 0x00000100U), 0x00000000); + + tmp_regval = Xil_In32(0xFD690040); + tmp_regval &= ~0x00000001; + Xil_Out32(0xFD690040, tmp_regval); + + tmp_regval = Xil_In32(0xFD690030); + tmp_regval &= ~0x00000001; + Xil_Out32(0xFD690030, tmp_regval); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + + status &= init_serdes(); + init_peripheral(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 0d1bd5412b..3c4cf80b23 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -377,7 +377,8 @@ int dram_init(void) #else int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/cmd/Kconfig b/cmd/Kconfig index d440675b6e..bc1d2f31c0 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1021,46 +1021,127 @@ config CMD_SETEXPR endmenu -menu "Network commands" - if NET -config CMD_NET - bool "bootp, tftpboot" +menuconfig CMD_NET + bool "Network commands" + default y + +if CMD_NET + +config CMD_BOOTP + bool "bootp" default y help - Network commands. bootp - boot image via network using BOOTP/TFTP protocol + +config CMD_DHCP + bool "dhcp" + depends on CMD_BOOTP + help + Boot image via network using DHCP/TFTP protocol + +config BOOTP_BOOTPATH + bool "Request & store 'rootpath' from BOOTP/DHCP server" + default y + depends on CMD_BOOTP + help + Even though the config is called BOOTP_BOOTPATH, it stores the + path in the variable 'rootpath'. + +config BOOTP_DNS + bool "Request & store 'dnsip' from BOOTP/DHCP server" + default y + depends on CMD_BOOTP + help + The primary DNS server is stored as 'dnsip'. If two servers are + returned, you must set BOOTP_DNS2 to store that second server IP + also. + +config BOOTP_DNS2 + bool "Store 'dnsip2' from BOOTP/DHCP server" + depends on BOOTP_DNS + help + If a DHCP client requests the DNS server IP from a DHCP server, + it is possible that more than one DNS serverip is offered to the + client. If CONFIG_BOOTP_DNS2 is enabled, the secondary DNS + server IP will be stored in the additional environment + variable "dnsip2". The first DNS serverip is always + stored in the variable "dnsip", when BOOTP_DNS is defined. + +config BOOTP_GATEWAY + bool "Request & store 'gatewayip' from BOOTP/DHCP server" + default y + depends on CMD_BOOTP + +config BOOTP_HOSTNAME + bool "Request & store 'hostname' from BOOTP/DHCP server" + default y + depends on CMD_BOOTP + help + The name may or may not be qualified with the local domain name. + +config BOOTP_SUBNETMASK + bool "Request & store 'netmask' from BOOTP/DHCP server" + default y + depends on CMD_BOOTP + +config BOOTP_PXE + bool "Send PXE client arch to BOOTP/DHCP server" + default y + depends on CMD_BOOTP && CMD_PXE + help + Supported for ARM, ARM64, and x86 for now. + +config BOOTP_PXE_CLIENTARCH + hex + depends on BOOTP_PXE + default 0x16 if ARM64 + default 0x15 if ARM + default 0 if X86 + +config BOOTP_VCI_STRING + string + depends on CMD_BOOTP + default "U-Boot.armv7" if CPU_V7 || CPU_V7M + default "U-Boot.armv8" if ARM64 + default "U-Boot.arm" if ARM + default "U-Boot" + +config CMD_TFTPBOOT + bool "tftpboot" + default y + help tftpboot - boot image via network using TFTP protocol config CMD_TFTPPUT bool "tftp put" + depends on CMD_TFTPBOOT help TFTP put command, for uploading files to a server config CMD_TFTPSRV bool "tftpsrv" + depends on CMD_TFTPBOOT help Act as a TFTP server and boot the first received file +config NET_TFTP_VARS + bool "Control TFTP timeout and count through environment" + depends on CMD_TFTPBOOT + default y + help + If set, allows controlling the TFTP timeout through the + environment variable tftptimeout, and the TFTP maximum + timeout count through the variable tftptimeoutcountmax. + If unset, timeout and maximum are hard-defined as 1 second + and 10 timouts per TFTP transfer. + config CMD_RARP bool "rarpboot" help Boot image via network using RARP/TFTP protocol -config CMD_DHCP - bool "dhcp" - depends on CMD_NET - help - Boot image via network using DHCP/TFTP protocol - -config CMD_PXE - bool "pxe" - depends on CMD_NET - select MENU - help - Boot image via network using PXE protocol - config CMD_NFS bool "nfs" default y @@ -1097,6 +1178,8 @@ config CMD_LINK_LOCAL help Acquire a network IP address using the link-local protocol +endif + config CMD_ETHSW bool "ethsw" help @@ -1105,9 +1188,13 @@ config CMD_ETHSW operations such as enabling / disabling a port and viewing/maintaining the filtering database (FDB) -endif +config CMD_PXE + bool "pxe" + select MENU + help + Boot image via network using PXE protocol -endmenu +endif menu "Misc commands" diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 6546272348..5498a5fccf 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -22,37 +22,65 @@ DECLARE_GLOBAL_DATA_PTR; -static uint8_t efi_obj_list_initalized; +#define OBJ_LIST_NOT_INITIALIZED 1 + +static efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED; static struct efi_device_path *bootefi_image_path; static struct efi_device_path *bootefi_device_path; /* Initialize and populate EFI object list */ -static void efi_init_obj_list(void) +efi_status_t efi_init_obj_list(void) { - efi_obj_list_initalized = 1; + efi_status_t ret = EFI_SUCCESS; + + /* Initialize once only */ + if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED) + return efi_obj_list_initialized; /* Initialize EFI driver uclass */ - efi_driver_init(); + ret = efi_driver_init(); + if (ret != EFI_SUCCESS) + goto out; - efi_console_register(); + ret = efi_console_register(); + if (ret != EFI_SUCCESS) + goto out; #ifdef CONFIG_PARTITIONS - efi_disk_register(); + ret = efi_disk_register(); + if (ret != EFI_SUCCESS) + goto out; #endif #if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO) - efi_gop_register(); + ret = efi_gop_register(); + if (ret != EFI_SUCCESS) + goto out; #endif -#ifdef CONFIG_CMD_NET - efi_net_register(); +#ifdef CONFIG_NET + ret = efi_net_register(); + if (ret != EFI_SUCCESS) + goto out; #endif #ifdef CONFIG_GENERATE_SMBIOS_TABLE - efi_smbios_register(); + ret = efi_smbios_register(); + if (ret != EFI_SUCCESS) + goto out; #endif - efi_watchdog_register(); + ret = efi_watchdog_register(); + if (ret != EFI_SUCCESS) + goto out; /* Initialize EFI runtime services */ - efi_reset_system_init(); - efi_get_time_init(); + ret = efi_reset_system_init(); + if (ret != EFI_SUCCESS) + goto out; + ret = efi_get_time_init(); + if (ret != EFI_SUCCESS) + goto out; + +out: + efi_obj_list_initialized = ret; + return ret; } /* @@ -150,24 +178,85 @@ static efi_status_t efi_run_in_el2(EFIAPI efi_status_t (*entry)( } #endif +/* Carve out DT reserved memory ranges */ +static efi_status_t efi_carve_out_dt_rsv(void *fdt) +{ + int nr_rsv, i; + uint64_t addr, size, pages; + + nr_rsv = fdt_num_mem_rsv(fdt); + + /* Look for an existing entry and add it to the efi mem map. */ + for (i = 0; i < nr_rsv; i++) { + if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0) + continue; + + pages = ALIGN(size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT; + efi_add_memory_map(addr, pages, EFI_RESERVED_MEMORY_TYPE, + false); + } + + return EFI_SUCCESS; +} + +static efi_status_t efi_install_fdt(void *fdt) +{ + bootm_headers_t img = { 0 }; + ulong fdt_pages, fdt_size, fdt_start, fdt_end; + efi_status_t ret; + + if (fdt_check_header(fdt)) { + printf("ERROR: invalid device tree\n"); + return EFI_INVALID_PARAMETER; + } + + /* Prepare fdt for payload */ + fdt = copy_fdt(fdt); + if (!fdt) + return EFI_OUT_OF_RESOURCES; + + if (image_setup_libfdt(&img, fdt, 0, NULL)) { + printf("ERROR: failed to process device tree\n"); + return EFI_LOAD_ERROR; + } + + if (efi_carve_out_dt_rsv(fdt) != EFI_SUCCESS) { + printf("ERROR: failed to carve out memory\n"); + return EFI_LOAD_ERROR; + } + + /* Link to it in the efi tables */ + ret = efi_install_configuration_table(&efi_guid_fdt, fdt); + if (ret != EFI_SUCCESS) + return EFI_OUT_OF_RESOURCES; + + /* And reserve the space in the memory map */ + fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK; + fdt_end = ((ulong)fdt) + fdt_totalsize(fdt); + fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK; + fdt_pages = fdt_size >> EFI_PAGE_SHIFT; + /* Give a bootloader the chance to modify the device tree */ + fdt_pages += 2; + ret = efi_add_memory_map(fdt_start, fdt_pages, + EFI_BOOT_SERVICES_DATA, true); + return ret; +} + /* * Load an EFI payload into a newly allocated piece of memory, register all * EFI objects it would want to access and jump to it. */ -static efi_status_t do_bootefi_exec(void *efi, void *fdt, +static efi_status_t do_bootefi_exec(void *efi, struct efi_device_path *device_path, struct efi_device_path *image_path) { struct efi_loaded_image loaded_image_info = {}; struct efi_object loaded_image_info_obj = {}; struct efi_device_path *memdp = NULL; - ulong ret; + efi_status_t ret; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); - ulong fdt_pages, fdt_size, fdt_start, fdt_end; - const efi_guid_t fdt_guid = EFI_FDT_GUID; - bootm_headers_t img = { 0 }; /* * Special case for efi payload not loaded from disk, such as @@ -183,10 +272,6 @@ static efi_status_t do_bootefi_exec(void *efi, void *fdt, assert(device_path && image_path); } - /* Initialize and populate EFI object list */ - if (!efi_obj_list_initalized) - efi_init_obj_list(); - efi_setup_loaded_image(&loaded_image_info, &loaded_image_info_obj, device_path, image_path); @@ -196,38 +281,12 @@ static efi_status_t do_bootefi_exec(void *efi, void *fdt, */ efi_save_gd(); - if (fdt && !fdt_check_header(fdt)) { - /* Prepare fdt for payload */ - fdt = copy_fdt(fdt); - - if (image_setup_libfdt(&img, fdt, 0, NULL)) { - printf("ERROR: Failed to process device tree\n"); - return -EINVAL; - } - - /* Link to it in the efi tables */ - efi_install_configuration_table(&fdt_guid, fdt); - - /* And reserve the space in the memory map */ - fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK; - fdt_end = ((ulong)fdt) + fdt_totalsize(fdt); - fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK; - fdt_pages = fdt_size >> EFI_PAGE_SHIFT; - /* Give a bootloader the chance to modify the device tree */ - fdt_pages += 2; - efi_add_memory_map(fdt_start, fdt_pages, - EFI_BOOT_SERVICES_DATA, true); - } else { - printf("WARNING: Invalid device tree, expect boot to fail\n"); - efi_install_configuration_table(&fdt_guid, NULL); - } - /* Transfer environment variable bootargs as load options */ set_load_options(&loaded_image_info, "bootargs"); /* Load the EFI payload */ entry = efi_load_pe(efi, &loaded_image_info); if (!entry) { - ret = -ENOENT; + ret = EFI_LOAD_ERROR; goto exit; } @@ -277,16 +336,12 @@ exit: return ret; } -static int do_bootefi_bootmgr_exec(unsigned long fdt_addr) +static int do_bootefi_bootmgr_exec(void) { struct efi_device_path *device_path, *file_path; void *addr; efi_status_t r; - /* Initialize and populate EFI object list */ - if (!efi_obj_list_initalized) - efi_init_obj_list(); - /* * gd lives in a fixed register which may get clobbered while we execute * the payload. So save it here and restore it on every callback entry @@ -298,7 +353,7 @@ static int do_bootefi_bootmgr_exec(unsigned long fdt_addr) return 1; printf("## Starting EFI application at %p ...\n", addr); - r = do_bootefi_exec(addr, (void *)fdt_addr, device_path, file_path); + r = do_bootefi_exec(addr, device_path, file_path); printf("## Application terminated, r = %lu\n", r & ~EFI_ERROR_MASK); @@ -311,12 +366,37 @@ static int do_bootefi_bootmgr_exec(unsigned long fdt_addr) /* Interpreter command to boot an arbitrary EFI image from memory */ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *saddr, *sfdt; - unsigned long addr, fdt_addr = 0; + unsigned long addr; + char *saddr; efi_status_t r; + void *fdt_addr; + + /* Initialize EFI drivers */ + r = efi_init_obj_list(); + if (r != EFI_SUCCESS) { + printf("Error: Cannot set up EFI drivers, r = %lu\n", + r & ~EFI_ERROR_MASK); + return CMD_RET_FAILURE; + } if (argc < 2) return CMD_RET_USAGE; + + if (argc > 2) { + fdt_addr = (void *)simple_strtoul(argv[2], NULL, 16); + if (!fdt_addr && *argv[2] != '0') + return CMD_RET_USAGE; + /* Install device tree */ + r = efi_install_fdt(fdt_addr); + if (r != EFI_SUCCESS) { + printf("ERROR: failed to install device tree\n"); + return CMD_RET_FAILURE; + } + } else { + /* Remove device tree. EFI_NOT_FOUND can be ignored here */ + efi_install_configuration_table(&efi_guid_fdt, NULL); + printf("WARNING: booting without device tree\n"); + } #ifdef CONFIG_CMD_BOOTEFI_HELLO if (!strcmp(argv[1], "hello")) { ulong size = __efi_helloworld_end - __efi_helloworld_begin; @@ -350,8 +430,7 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ efi_save_gd(); /* Initialize and populate EFI object list */ - if (!efi_obj_list_initalized) - efi_init_obj_list(); + efi_init_obj_list(); /* Transfer environment variable efi_selftest as load options */ set_load_options(&loaded_image_info, "efi_selftest"); /* Execute the test */ @@ -363,12 +442,7 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } else #endif if (!strcmp(argv[1], "bootmgr")) { - unsigned long fdt_addr = 0; - - if (argc > 2) - fdt_addr = simple_strtoul(argv[2], NULL, 16); - - return do_bootefi_bootmgr_exec(fdt_addr); + return do_bootefi_bootmgr_exec(); } else { saddr = argv[1]; @@ -377,15 +451,11 @@ static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!addr && *saddr != '0') return CMD_RET_USAGE; - if (argc > 2) { - sfdt = argv[2]; - fdt_addr = simple_strtoul(sfdt, NULL, 16); - } } printf("## Starting EFI application at %08lx ...\n", addr); - r = do_bootefi_exec((void *)addr, (void *)fdt_addr, - bootefi_device_path, bootefi_image_path); + r = do_bootefi_exec((void *)addr, bootefi_device_path, + bootefi_image_path); printf("## Application terminated, r = %lu\n", r & ~EFI_ERROR_MASK); @@ -406,7 +476,7 @@ static char bootefi_help_text[] = " - boot a sample Hello World application stored within U-Boot\n" #endif #ifdef CONFIG_CMD_BOOTEFI_SELFTEST - "bootefi selftest\n" + "bootefi selftest [fdt address]\n" " - boot an EFI selftest application stored within U-Boot\n" " Use environment variable efi_selftest to select a single test.\n" " Use 'setenv efi_selftest list' to enumerate all tests.\n" @@ -424,16 +494,6 @@ U_BOOT_CMD( bootefi_help_text ); -static int parse_partnum(const char *devnr) -{ - const char *str = strchr(devnr, ':'); - if (str) { - str++; - return simple_strtoul(str, NULL, 16); - } - return 0; -} - void efi_set_bootdev(const char *dev, const char *devnr, const char *path) { char filename[32] = { 0 }; /* dp->str is u16[32] long */ @@ -441,16 +501,17 @@ void efi_set_bootdev(const char *dev, const char *devnr, const char *path) if (strcmp(dev, "Net")) { struct blk_desc *desc; + disk_partition_t fs_partition; int part; - desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10)); - if (!desc) + part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition, + 1); + if (part < 0) return; - part = parse_partnum(devnr); bootefi_device_path = efi_dp_from_part(desc, part); } else { -#ifdef CONFIG_CMD_NET +#ifdef CONFIG_NET bootefi_device_path = efi_dp_from_eth(); #endif } @@ -16,7 +16,15 @@ int __weak soc_clk_dump(void) static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - return soc_clk_dump(); + int ret; + + ret = soc_clk_dump(); + if (ret < 0) { + printf("Clock dump error %d\n", ret); + ret = CMD_RET_FAILURE; + } + + return ret; } static cmd_tbl_t cmd_clk_sub[] = { @@ -16,16 +16,56 @@ #include <common.h> #include <command.h> #include <elf.h> +#include <environment.h> #include <net.h> #include <vxworks.h> #ifdef CONFIG_X86 +#include <vbe.h> #include <asm/e820.h> #include <linux/linkage.h> #endif /* - * A very simple elf loader, assumes the image is valid, returns the + * A very simple ELF64 loader, assumes the image is valid, returns the * entry point address. + * + * Note if U-Boot is 32-bit, the loader assumes the to segment's + * physical address and size is within the lower 32-bit address space. + */ +static unsigned long load_elf64_image_phdr(unsigned long addr) +{ + Elf64_Ehdr *ehdr; /* Elf header structure pointer */ + Elf64_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf64_Ehdr *)addr; + phdr = (Elf64_Phdr *)(addr + (ulong)ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *)(ulong)phdr->p_paddr; + void *src = (void *)addr + phdr->p_offset; + + debug("Loading phdr %i to 0x%p (%lu bytes)\n", + i, dst, (ulong)phdr->p_filesz); + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst, phdr->p_filesz); + ++phdr; + } + + return ehdr->e_entry; +} + +/* + * A very simple ELF loader, assumes the image is valid, returns the + * entry point address. + * + * The loader firstly reads the EFI class to see if it's a 64-bit image. + * If yes, call the ELF64 loader. Otherwise continue with the ELF32 loader. */ static unsigned long load_elf_image_phdr(unsigned long addr) { @@ -34,12 +74,16 @@ static unsigned long load_elf_image_phdr(unsigned long addr) int i; ehdr = (Elf32_Ehdr *)addr; + if (ehdr->e_ident[EI_CLASS] == ELFCLASS64) + return load_elf64_image_phdr(addr); + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); /* Load each program header */ for (i = 0; i < ehdr->e_phnum; ++i) { void *dst = (void *)(uintptr_t)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; + debug("Loading phdr %i to 0x%p (%i bytes)\n", i, dst, phdr->p_filesz); if (phdr->p_filesz) @@ -202,14 +246,17 @@ int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long addr; /* Address of image */ - unsigned long bootaddr; /* Address to put the bootline */ + unsigned long bootaddr = 0; /* Address to put the bootline */ char *bootline; /* Text of the bootline */ char *tmp; /* Temporary char pointer */ char build_buf[128]; /* Buffer for building the bootline */ int ptr = 0; #ifdef CONFIG_X86 - struct e820info *info; - struct e820entry *data; + ulong base; + struct e820_info *info; + struct e820_entry *data; + struct efi_gop_info *gop; + struct vesa_mode_info *vesa = &mode_info.vesa; #endif /* @@ -248,6 +295,45 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("## Ethernet MAC address not copied to NV RAM\n"); #endif +#ifdef CONFIG_X86 + /* + * Get VxWorks's physical memory base address from environment, + * if we don't specify it in the environment, use a default one. + */ + base = env_get_hex("vx_phys_mem_base", VXWORKS_PHYS_MEM_BASE); + data = (struct e820_entry *)(base + E820_DATA_OFFSET); + info = (struct e820_info *)(base + E820_INFO_OFFSET); + + memset(info, 0, sizeof(struct e820_info)); + info->sign = E820_SIGNATURE; + info->entries = install_e820_map(E820MAX, data); + info->addr = (info->entries - 1) * sizeof(struct e820_entry) + + E820_DATA_OFFSET; + + /* + * Explicitly clear the bootloader image size otherwise if memory + * at this offset happens to contain some garbage data, the final + * available memory size for the kernel is insane. + */ + *(u32 *)(base + BOOT_IMAGE_SIZE_OFFSET) = 0; + + /* + * Prepare compatible framebuffer information block. + * The VESA mode has to be 32-bit RGBA. + */ + if (vesa->x_resolution && vesa->y_resolution) { + gop = (struct efi_gop_info *)(base + EFI_GOP_INFO_OFFSET); + gop->magic = EFI_GOP_INFO_MAGIC; + gop->info.version = 0; + gop->info.width = vesa->x_resolution; + gop->info.height = vesa->y_resolution; + gop->info.pixel_format = EFI_GOT_RGBA8; + gop->info.pixels_per_scanline = vesa->bytes_per_scanline / 4; + gop->fb_base = vesa->phys_base_ptr; + gop->fb_size = vesa->bytes_per_scanline * vesa->y_resolution; + } +#endif + /* * Use bootaddr to find the location in memory that VxWorks * will look for the bootline string. The default value is @@ -256,104 +342,78 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ tmp = env_get("bootaddr"); if (!tmp) { +#ifdef CONFIG_X86 + bootaddr = base + X86_BOOT_LINE_OFFSET; +#else printf("## VxWorks bootline address not specified\n"); - } else { + return 1; +#endif + } + + if (!bootaddr) bootaddr = simple_strtoul(tmp, NULL, 16); - /* - * Check to see if the bootline is defined in the 'bootargs' - * parameter. If it is not defined, we may be able to - * construct the info. - */ - bootline = env_get("bootargs"); - if (bootline) { - memcpy((void *)bootaddr, bootline, - max(strlen(bootline), (size_t)255)); - flush_cache(bootaddr, max(strlen(bootline), - (size_t)255)); + /* + * Check to see if the bootline is defined in the 'bootargs' parameter. + * If it is not defined, we may be able to construct the info. + */ + bootline = env_get("bootargs"); + if (!bootline) { + tmp = env_get("bootdev"); + if (tmp) { + strcpy(build_buf, tmp); + ptr = strlen(tmp); } else { - tmp = env_get("bootdev"); - if (tmp) { - strcpy(build_buf, tmp); - ptr = strlen(tmp); - } else - printf("## VxWorks boot device not specified\n"); + printf("## VxWorks boot device not specified\n"); + } - tmp = env_get("bootfile"); - if (tmp) - ptr += sprintf(build_buf + ptr, - "host:%s ", tmp); - else - ptr += sprintf(build_buf + ptr, - "host:vxWorks "); + tmp = env_get("bootfile"); + if (tmp) + ptr += sprintf(build_buf + ptr, "host:%s ", tmp); + else + ptr += sprintf(build_buf + ptr, "host:vxWorks "); - /* - * The following parameters are only needed if 'bootdev' - * is an ethernet device, otherwise they are optional. - */ - tmp = env_get("ipaddr"); + /* + * The following parameters are only needed if 'bootdev' + * is an ethernet device, otherwise they are optional. + */ + tmp = env_get("ipaddr"); + if (tmp) { + ptr += sprintf(build_buf + ptr, "e=%s", tmp); + tmp = env_get("netmask"); if (tmp) { - ptr += sprintf(build_buf + ptr, "e=%s", tmp); - tmp = env_get("netmask"); - if (tmp) { - u32 mask = env_get_ip("netmask").s_addr; - ptr += sprintf(build_buf + ptr, - ":%08x ", ntohl(mask)); - } else { - ptr += sprintf(build_buf + ptr, " "); - } + u32 mask = env_get_ip("netmask").s_addr; + ptr += sprintf(build_buf + ptr, + ":%08x ", ntohl(mask)); + } else { + ptr += sprintf(build_buf + ptr, " "); } + } - tmp = env_get("serverip"); - if (tmp) - ptr += sprintf(build_buf + ptr, "h=%s ", tmp); + tmp = env_get("serverip"); + if (tmp) + ptr += sprintf(build_buf + ptr, "h=%s ", tmp); - tmp = env_get("gatewayip"); - if (tmp) - ptr += sprintf(build_buf + ptr, "g=%s ", tmp); + tmp = env_get("gatewayip"); + if (tmp) + ptr += sprintf(build_buf + ptr, "g=%s ", tmp); - tmp = env_get("hostname"); - if (tmp) - ptr += sprintf(build_buf + ptr, "tn=%s ", tmp); + tmp = env_get("hostname"); + if (tmp) + ptr += sprintf(build_buf + ptr, "tn=%s ", tmp); - tmp = env_get("othbootargs"); - if (tmp) { - strcpy(build_buf + ptr, tmp); - ptr += strlen(tmp); - } - - memcpy((void *)bootaddr, build_buf, - max(strlen(build_buf), (size_t)255)); - flush_cache(bootaddr, max(strlen(build_buf), - (size_t)255)); + tmp = env_get("othbootargs"); + if (tmp) { + strcpy(build_buf + ptr, tmp); + ptr += strlen(tmp); } - printf("## Using bootline (@ 0x%lx): %s\n", bootaddr, - (char *)bootaddr); + bootline = build_buf; } -#ifdef CONFIG_X86 - /* - * Since E820 information is critical to the kernel, if we don't - * specify these in the environments, use a default one. - */ - tmp = env_get("e820data"); - if (tmp) - data = (struct e820entry *)simple_strtoul(tmp, NULL, 16); - else - data = (struct e820entry *)VXWORKS_E820_DATA_ADDR; - tmp = env_get("e820info"); - if (tmp) - info = (struct e820info *)simple_strtoul(tmp, NULL, 16); - else - info = (struct e820info *)VXWORKS_E820_INFO_ADDR; - - memset(info, 0, sizeof(struct e820info)); - info->sign = E820_SIGNATURE; - info->entries = install_e820_map(E820MAX, data); - info->addr = (info->entries - 1) * sizeof(struct e820entry) + - VXWORKS_E820_DATA_ADDR; -#endif + memcpy((void *)bootaddr, bootline, max(strlen(bootline), (size_t)255)); + flush_cache(bootaddr, max(strlen(bootline), (size_t)255)); + printf("## Using bootline (@ 0x%lx): %s\n", bootaddr, (char *)bootaddr); /* * If the data at the load address is an elf image, then @@ -368,6 +428,11 @@ int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("## Starting vxWorks at 0x%08lx ...\n", addr); dcache_disable(); +#if defined(CONFIG_ARM64) && defined(CONFIG_ARMV8_PSCI) + armv8_setup_psci(); + smp_kick_all_cpus(); +#endif + #ifdef CONFIG_X86 /* VxWorks on x86 uses stack to pass parameters */ ((asmlinkage void (*)(int))addr)(0); diff --git a/cmd/ethsw.c b/cmd/ethsw.c index b600965e8a..92a60b4515 100644 --- a/cmd/ethsw.c +++ b/cmd/ethsw.c @@ -8,6 +8,7 @@ #include <common.h> #include <command.h> +#include <environment.h> #include <errno.h> #include <env_flags.h> #include <ethsw.h> @@ -14,6 +14,7 @@ static int netboot_common(enum proto_t, cmd_tbl_t *, int, char * const []); +#ifdef CONFIG_CMD_BOOTP static int do_bootp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { return netboot_common(BOOTP, cmdtp, argc, argv); @@ -24,7 +25,9 @@ U_BOOT_CMD( "boot image via network using BOOTP/TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]" ); +#endif +#ifdef CONFIG_CMD_TFTPBOOT int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int ret; @@ -40,6 +43,7 @@ U_BOOT_CMD( "boot image via network using TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]" ); +#endif #ifdef CONFIG_CMD_TFTPPUT static int do_tftpput(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 4cb25b8248..9838678262 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -341,6 +341,36 @@ ulong env_get_hex(const char *varname, ulong default_val) return value; } +void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr) +{ + char *end; + int i; + + for (i = 0; i < 6; ++i) { + enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0; + if (addr) + addr = (*end) ? end + 1 : end; + } +} + +int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr) +{ + eth_parse_enetaddr(env_get(name), enetaddr); + return is_valid_ethaddr(enetaddr); +} + +int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr) +{ + char buf[ARP_HLEN_ASCII + 1]; + + if (eth_env_get_enetaddr(name, (uint8_t *)buf)) + return -EEXIST; + + sprintf(buf, "%pM", enetaddr); + + return env_set(name, buf); +} + #ifndef CONFIG_SPL_BUILD static int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/common/bootm.c b/common/bootm.c index adb12137c7..36162917a1 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -434,6 +434,8 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, ulong blob_end = os.end; ulong image_start = os.image_start; ulong image_len = os.image_len; + ulong flush_start = ALIGN_DOWN(load, ARCH_DMA_MINALIGN); + ulong flush_len = *load_end - load; bool no_overlap; void *load_buf, *image_buf; int err; @@ -447,7 +449,11 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); return err; } - flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN)); + + if (flush_start < load) + flush_len += load - flush_start; + + flush_cache(flush_start, ALIGN(flush_len, ARCH_DMA_MINALIGN)); debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end); bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED); diff --git a/common/log.c b/common/log.c index 680a60f86e..66d5e3ebf8 100644 --- a/common/log.c +++ b/common/log.c @@ -224,6 +224,7 @@ int log_add_filter(const char *drv_name, enum log_category_t cat_list[], { struct log_filter *filt; struct log_device *ldev; + int ret; int i; ldev = log_device_find_by_name(drv_name); @@ -236,8 +237,10 @@ int log_add_filter(const char *drv_name, enum log_category_t cat_list[], if (cat_list) { filt->flags |= LOGFF_HAS_CAT; for (i = 0; ; i++) { - if (i == ARRAY_SIZE(filt->cat_list)) - return -ENOSPC; + if (i == ARRAY_SIZE(filt->cat_list)) { + ret = -ENOSPC; + goto err; + } filt->cat_list[i] = cat_list[i]; if (cat_list[i] == LOGC_END) break; @@ -246,17 +249,19 @@ int log_add_filter(const char *drv_name, enum log_category_t cat_list[], filt->max_level = max_level; if (file_list) { filt->file_list = strdup(file_list); - if (!filt->file_list) - goto nomem; + if (!filt->file_list) { + ret = ENOMEM; + goto err; + } } filt->filter_num = ldev->next_filter_num++; list_add_tail(&filt->sibling_node, &ldev->filter_head); return filt->filter_num; -nomem: +err: free(filt); - return -ENOMEM; + return ret; } int log_remove_filter(const char *drv_name, int filter_num) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index d15f576a81..4d27565566 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -643,6 +643,13 @@ config SPL_SPI_FLASH_SUPPORT lines). This enables the drivers in drivers/mtd/spi as part of an SPL build. This normally requires SPL_SPI_SUPPORT. +config SPL_SPI_LOAD + bool "Support loading from SPI flash" + depends on SPL_SPI_FLASH_SUPPORT + help + Enable support for loading next stage, U-Boot or otherwise, from + SPI NOR in U-Boot SPL. + config SPL_SPI_SUPPORT bool "Support SPI drivers" help @@ -903,6 +910,20 @@ config TPL_NAND_SUPPORT help Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details. +config TPL_RAM_SUPPORT + bool "Support booting from RAM" + help + Enable booting of an image in RAM. The image can be preloaded or + it can be loaded by TPL directly into RAM (e.g. using USB). + +config TPL_RAM_DEVICE + bool "Support booting from preloaded image in RAM" + depends on TPL_RAM_SUPPORT + help + Enable booting of an image already loaded in RAM. The image has to + be already in memory when TPL takes over, e.g. loaded by the boot + ROM. + config TPL_SERIAL_SUPPORT bool "Support serial" help @@ -915,12 +936,27 @@ config TPL_SPI_FLASH_SUPPORT Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT for details. +config TPL_SPI_LOAD + bool "Support loading from SPI flash" + depends on TPL_SPI_FLASH_SUPPORT + help + Enable support for loading next stage, U-Boot or otherwise, from + SPI NOR in U-Boot TPL. + config TPL_SPI_SUPPORT bool "Support SPI drivers" help Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for details. +config TPL_YMODEM_SUPPORT + bool "Support loading using Ymodem" + help + While loading from serial is slow it can be a useful backup when + there is no other option. The Ymodem protocol provides a reliable + means of transmitting U-Boot over a serial line for using in TPL, + with a checksum to ensure correctness. + endif # TPL endif # SPL diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index d9db9f3a40..a15761e309 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -36,7 +36,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image, header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS; -#if defined(CONFIG_SPL_DFU_SUPPORT) +#if CONFIG_IS_ENABLED(DFU_SUPPORT) if (bootdev->boot_device == BOOT_DEVICE_DFU) spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0"); #endif @@ -74,10 +74,10 @@ static int spl_ram_load_image(struct spl_image_info *spl_image, return 0; } -#if defined(CONFIG_SPL_RAM_DEVICE) +#if CONFIG_IS_ENABLED(RAM_DEVICE) SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, spl_ram_load_image); #endif -#if defined(CONFIG_SPL_DFU_SUPPORT) +#if CONFIG_IS_ENABLED(DFU_SUPPORT) SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image); #endif diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index aafaf45b91..4e7b12d1ac 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM_GPIO=y CONFIG_ALTERA_PIO=y CONFIG_MISC=y diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 990cb3ebaf..95d9357d01 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM_GPIO=y CONFIG_ALTERA_PIO=y CONFIG_MISC=y diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 374d4e2b78..feb1173c0b 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -14,7 +14,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_SUN4I_EMAC=y diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 93ab4ec308..9498a6d752 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN4I_EMAC=y CONFIG_AXP152_POWER=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index fb680aa5f3..ed507cdf0b 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUNXI_NO_PMIC=y CONFIG_CONS_INDEX=2 diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 21fbc10832..8e160d7cc4 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DFU_RAM=y CONFIG_AXP_ALDO3_VOLT=3300 diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 396ee0bd2d..9d043e856a 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -17,7 +17,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index b1243ea0dd..f2997c6fe5 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -16,7 +16,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index cc03160923..b7c13a6932 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -12,7 +12,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index c2984cd94f..f7e7cbab0a 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -14,7 +14,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 4c4048dfd2..8dcbdc08f9 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -15,7 +15,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index f353ce9a5e..a06499e2d0 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -16,7 +16,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 3f44104937..847945b649 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -16,7 +16,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SCSI_AHCI=y CONFIG_PHY_ADDR=3 diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index 99ab73c8f5..e56f2c7110 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -15,7 +15,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SCSI_AHCI=y CONFIG_PHY_ADDR=3 diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 273e62ed5f..744e7ef511 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index d438eceaf8..3e47ca2466 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index fe8e6f601a..b0d6047789 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 97b4bd9dc5..ce4806cf5e 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 2b24dabbbd..5faf45c3d7 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 7872cef542..7a9b5fe0e5 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -12,7 +12,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index 8afc8d48ab..2032a4aef8 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-bananapi-m2m" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index faf3b50512..5a8ded0493 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -14,7 +14,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index c6f62302d8..c122944881 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -10,7 +10,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DFU_RAM=y # CONFIG_MMC is not set diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 2a2bf4242a..b103e7e00d 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 8835a0fb57..645a759fc2 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 08bba8660d..c85e47cb11 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -19,7 +19,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index c4ac610003..418da63ba8 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -11,7 +11,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 53d3f9b080..16b1862334 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -14,7 +14,6 @@ CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4" # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP809_POWER=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index 72bf8bfcd8..27223d201e 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -11,7 +11,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_SUN4I_EMAC=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 107c613e23..f0bb4c9d5c 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_SCSI_AHCI=y CONFIG_DFU_RAM=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 5c0f67d889..d76bc6748b 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus" CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_DLDO4_VOLT=3300 diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index d7c2fbcb71..bac5859130 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -19,7 +19,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 84865e5778..47f3fe7e2e 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index d254e993e2..24126fde28 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index a954e6f1e5..72327c90fc 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 54bfe4b1b0..dfef071476 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -11,7 +11,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index 1d5a686852..9ed1f02d52 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -13,7 +13,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_B53_SWITCH=y diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index bf9bccb4a2..6cf0940776 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=14779 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero" # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set # CONFIG_NETDEVICES is not set CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index fdbe2c647d..2df6761455 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -13,7 +13,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 7b4a806e9d..d7e9c26cbf 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -11,7 +11,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_DM_MMC=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 750c80ed17..500f885599 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 280e7e1c19..f24955cd30 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -17,7 +17,4 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index c4d5cc4388..97a4bcd629 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -17,7 +17,4 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 54a53b2941..6f5ad073df 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -13,7 +13,4 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 308f7012c9..5043a8c8aa 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -15,7 +15,4 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 8c4f95310f..6cc67abcca 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -13,7 +13,4 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index 0c8e6a8675..11e6aab841 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -20,9 +20,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index f7835ec935..0907f15df7 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -19,9 +19,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index d9aa67198a..d1571d5c52 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -19,9 +19,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index 75fbac2c50..2f4157f444 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -19,9 +19,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index 4236a4f3fd..45efe2a5d2 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -20,9 +20,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index 0c8e6a8675..11e6aab841 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -20,9 +20,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_CF_SPI=y diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig index 843e54e749..16a7fc6f39 100644 --- a/configs/M54451EVB_defconfig +++ b/configs/M54451EVB_defconfig @@ -21,9 +21,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig index e6dca9c4a4..4bbdfef9fd 100644 --- a/configs/M54451EVB_stmicro_defconfig +++ b/configs/M54451EVB_stmicro_defconfig @@ -20,9 +20,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index 003a2e3e77..b449bbea22 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index 3f01d7d6b6..b33199db78 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index 7e215bc1e6..9d7b5565f2 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index d306a00049..256e1705ed 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index b56c193fa8..e5f8cf571f 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y CONFIG_ISO_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index ee8ba1628a..62768b8656 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index 42e1214d12..c309103b79 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -19,9 +19,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index ac0658d8d5..c4482324c6 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -21,9 +21,6 @@ CONFIG_CMD_DATE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 1ff3545764..3d841b016e 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -21,9 +21,6 @@ CONFIG_CMD_DATE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 563a5f1da1..06c457b2c9 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -27,9 +27,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" # CONFIG_ENV_IS_IN_FLASH is not set CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NAND=y diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index bf7b2a2c70..11dc1893c3 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -27,9 +27,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" # CONFIG_ENV_IS_IN_FLASH is not set CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NAND=y diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index c8a4b00919..930fa40f36 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -21,9 +21,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=e0600000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_FSL_SATA=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 9ae8e80eb6..0294061f1a 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -13,9 +13,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 92ca91d27e..637903b408 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -13,9 +13,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index f33d61fe95..0ebd39b76f 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index a35b3a390a..f611201cb7 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index c1f307cca1..682a9a8337 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index e6e09cbaa6..b607132fb3 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -12,9 +12,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y # CONFIG_PCI is not set diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index b858b8b918..159cc0156f 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -12,9 +12,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 364c6b708d..fa9b632ca5 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 075b99dc96..9258ffd147 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -24,9 +24,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SATA_SIL3114=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index 57105c41cb..aba53d2de5 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -24,9 +24,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SATA_SIL3114=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index 8dcd04e499..9b1ae1e3d8 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -19,9 +19,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 2d04d2d732..59d4fa1955 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -17,9 +17,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index b4d6dac972..d9e2bf5731 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_FSL_SATA=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig index 2885c6b378..a79cd65073 100644 --- a/configs/MPC8541CDS_defconfig +++ b/configs/MPC8541CDS_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig index 7dac9ef71d..7eb5846c6e 100644 --- a/configs/MPC8541CDS_legacy_defconfig +++ b/configs/MPC8541CDS_legacy_defconfig @@ -16,9 +16,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig index 0ed0f1b104..d72f5e2dcc 100644 --- a/configs/MPC8544DS_defconfig +++ b/configs/MPC8544DS_defconfig @@ -19,9 +19,6 @@ CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SCSI_AHCI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index d87543ee8f..474041af83 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index d6744009aa..9c20cfee3f 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 5fb058dcfa..8b219e8aee 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_PCI=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig index f3b62a0c1c..4693e03403 100644 --- a/configs/MPC8555CDS_defconfig +++ b/configs/MPC8555CDS_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig index f46ab2325d..1403136d6e 100644 --- a/configs/MPC8555CDS_legacy_defconfig +++ b/configs/MPC8555CDS_legacy_defconfig @@ -16,9 +16,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig index 767ad2cab0..1e282327cb 100644 --- a/configs/MPC8568MDS_defconfig +++ b/configs/MPC8568MDS_defconfig @@ -17,9 +17,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig index a818d2afc6..cc5743b16b 100644 --- a/configs/MPC8569MDS_ATM_defconfig +++ b/configs/MPC8569MDS_ATM_defconfig @@ -22,9 +22,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig index 27a0f3a66c..cbe0f9f988 100644 --- a/configs/MPC8569MDS_defconfig +++ b/configs/MPC8569MDS_defconfig @@ -21,9 +21,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig index b798136556..acdb28018b 100644 --- a/configs/MPC8610HPCD_defconfig +++ b/configs/MPC8610HPCD_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SCSI_AHCI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig index f831988e3f..f2f9fc7e9b 100644 --- a/configs/MPC8641HPCN_36BIT_defconfig +++ b/configs/MPC8641HPCN_36BIT_defconfig @@ -17,9 +17,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SCSI_AHCI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig index bb3ff52ae1..c6e12a4690 100644 --- a/configs/MPC8641HPCN_defconfig +++ b/configs/MPC8641HPCN_defconfig @@ -17,9 +17,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_DOS_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SCSI_AHCI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 9ac7c489cb..309b384a4e 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -13,6 +13,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index 18b7a7ef20..04b0b63259 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 19fb196902..55c27b8435 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -7,7 +7,6 @@ CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_SUN4I_EMAC=y diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index 013e5117f0..e084454293 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index 2ed578e388..367f2aaf7a 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -11,7 +11,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_SUN4I_EMAC=y diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 3bde011cab..4fa61d311f 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index 08a780cf63..9f48bd91e0 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index 1b802db1bb..6b198be6f6 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -12,7 +12,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index 13e9750772..af89c50ee1 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index eb8f7c3370..329362d336 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -14,7 +14,6 @@ CONFIG_AXP_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus" # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP809_POWER=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index ccc42a9f2d..e32935e132 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 9893651c33..990bb25c41 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set # CONFIG_MMC is not set CONFIG_NAND=y diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index c961e6ac25..88e55495d5 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -15,7 +15,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 33edf695f0..46f27be254 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -17,7 +17,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index ccf0bdc875..9744aef096 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -13,7 +13,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 80fa863523..9e6267200b 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33" CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DFU_RAM=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/Sinovoip_BPI_M2_Plus_defconfig b/configs/Sinovoip_BPI_M2_Plus_defconfig index 71d9e79d34..da5620a770 100644 --- a/configs/Sinovoip_BPI_M2_Plus_defconfig +++ b/configs/Sinovoip_BPI_M2_Plus_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index da0f4663ba..65d81a5284 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index dce310d018..479dd05dfb 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -19,7 +19,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3" CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_AXP_DLDO3_VOLT=2500 diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index d7a6547c95..008af068d4 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -14,6 +14,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cx-a99" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index 4fb0c197c5..2254d40e46 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -22,9 +22,6 @@ CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=TQM834x-0" CONFIG_MTDPARTS_DEFAULT="mtdparts=TQM834x-0:256k(u-boot),256k(env),1m(kernel),2m(initrd),-(user);" -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index efbfe545af..a666e419db 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -23,7 +23,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=2 diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 8b30a00138..9a431ee4cd 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 98a4a53b3d..8065ca2629 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -15,7 +15,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 4d068a345e..88ccfd406e 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 9c2784e89f..c49cbcbc3c 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -22,7 +22,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index 770a39cb8e..87c13b0ea8 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 6edefa4f67..b32df990a0 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 172461a7f4..19ae070895 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 8839538881..71d09714af 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -38,11 +38,13 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),-(UBI)" CONFIG_CMD_UBI=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_OMAP24_I2C_SPEED=1000 CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index e31366d3d5..5688e44c0b 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_TFTP=y CONFIG_DFU_MMC=y @@ -30,7 +31,7 @@ CONFIG_DFU_RAM=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 5ff51e3b02..b9726edc47 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_SPL=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y @@ -34,8 +35,8 @@ CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 1e8a467030..3f8a2a24e2 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -5,7 +5,6 @@ CONFIG_AM33XX=y CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_DISTRO_DEFAULTS=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_SPL_LOAD_FIT=y CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd" CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -23,10 +22,10 @@ CONFIG_CMD_NAND=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y @@ -39,8 +38,8 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 49a04f925e..af12695ed9 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -20,6 +20,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y CONFIG_DFU_NAND=y @@ -29,7 +30,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index 22182f5d9b..068c3f27ad 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -18,13 +18,14 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),4m(kernel),-(rootfs)" CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index c0ebb4d19a..23ad6793c8 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MUSB_NEW_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set @@ -21,13 +22,14 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=m25p80-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=m25p80-flash.0:128k(SPL),512k(u-boot),128k(u-boot-env1),128k(u-boot-env2),3464k(kernel),-(rootfs)" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index b240505a6d..25d01bb53f 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y @@ -37,7 +38,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index 74fe162cff..f473210280 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -10,7 +10,6 @@ CONFIG_ISW_ENTRY_ADDR=0x40300350 CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_DISTRO_DEFAULTS=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -33,6 +32,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),1 # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y @@ -46,8 +46,8 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index 97519ea5bd..1321d52130 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -30,6 +30,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),1 # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y @@ -42,8 +43,8 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index c1cdf96f96..48dc3c970a 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -39,10 +39,11 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),-(UBI)" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_MTD_UBI_FASTMAP=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 3843727c8d..3158c55651 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -33,10 +33,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index fe69ba7459..4dab0a0cd3 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -34,10 +34,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index 3d911064f9..83124b6d4f 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -35,10 +35,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig index 5607789685..1b0d92bb69 100644 --- a/configs/am335x_shc_prompt_defconfig +++ b/configs/am335x_shc_prompt_defconfig @@ -32,10 +32,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 0b4ffdf53a..d4c3bfb856 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -34,10 +34,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig index 0b4ffdf53a..d4c3bfb856 100644 --- a/configs/am335x_shc_sdboot_prompt_defconfig +++ b/configs/am335x_shc_sdboot_prompt_defconfig @@ -34,10 +34,11 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index bf0efb3102..d51812e257 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -38,9 +38,10 @@ CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 0cb79ea663..edb41193be 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -24,6 +24,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -35,7 +36,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index 8e51dc776a..fcb502c605 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)" CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y @@ -41,7 +42,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 3fbf701e60..99daf5d9e0 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -29,6 +29,7 @@ CONFIG_OF_LIST="am4372-generic am437x-sk-evm am437x-idk-evm" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -39,7 +40,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index d6e1e0dc05..339a1c6fc3 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -25,6 +25,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -36,7 +37,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 505890ea41..4e9a614250 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -38,6 +38,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),2 CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -49,7 +50,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 98b0cea131..d290af0e28 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -35,6 +35,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)" CONFIG_OF_CONTROL=y CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DFU_MMC=y @@ -46,7 +47,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 9f2a7f7bc5..6b11b3476c 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 @@ -37,6 +38,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SCSI_AHCI=y @@ -51,10 +53,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index b3e739a348..ca9742f118 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -28,6 +28,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 @@ -40,6 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SCSI_AHCI=y @@ -54,10 +56,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y CONFIG_PMIC_PALMAS=y CONFIG_DM_REGULATOR=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 7718c2935d..3d179d64ef 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_SPL_DM=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 63e940b229..77a4008d7a 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y @@ -48,6 +49,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y diff --git a/configs/apalis_imx6_nospl_com_defconfig b/configs/apalis_imx6_nospl_com_defconfig index d47061ff18..89af27f7dc 100644 --- a/configs/apalis_imx6_nospl_com_defconfig +++ b/configs/apalis_imx6_nospl_com_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg, CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y @@ -37,6 +38,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y diff --git a/configs/apalis_imx6_nospl_it_defconfig b/configs/apalis_imx6_nospl_it_defconfig index 65a868d697..048d4f8271 100644 --- a/configs/apalis_imx6_nospl_it_defconfig +++ b/configs/apalis_imx6_nospl_it_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg, CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y @@ -37,6 +38,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index ddfdc2e4af..918f40c6a5 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_SPL_DM=y diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index 85735287aa..b976096803 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -34,11 +34,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_SPARTAN3=y CONFIG_MXC_GPIO=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index ae2293db3e..fdf751f2d7 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 93f76126a6..c40480cc64 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index f7585d0565..a990db9196 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index bf06d32f55..d6ab479895 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index ad7791ac45..03e0dba2a1 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index 079c6955b0..ca372a3992 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 06390dce6b..a6ea260891 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 06390dce6b..a6ea260891 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 5c3959e24b..4ab4b4e282 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index a26da0064a..72685f3c49 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -27,9 +27,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 4f08450384..dfd6c2e7e4 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -27,9 +27,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index c6cc752728..e2bd1ba395 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index 81b291efab..c825cf5461 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 9a539315bd..55606358ba 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index 5f8824ca42..ba7a83144f 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index 324f3acf57..5f4ccb954b 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 25bd456e65..add4c58fb6 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index c8cb0af1a4..528b112fce 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index b4ddf9cdd0..dbd0c6133e 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 57e48a7adb..a7acecd2cd 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -28,9 +28,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index da9b5efa0c..dd602c28bc 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -28,9 +28,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index a253d448e5..710b102f4d 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -28,9 +28,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index dc9514592e..2089fdf895 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -28,9 +28,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index acd4a89e2c..7d2a05628e 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -28,9 +28,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 069cd2a6ae..b119acfaee 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index b7e050feb1..eb2375476b 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 3ad4729160..a33ad2ee26 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index fa400c898a..4647e1ac55 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index 216ef83d94..24aa2a1457 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index 42ff46ca5c..598f029bed 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 0e2b544b08..2b228d818f 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index d98908e986..69937a621f 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -20,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="\0addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}::off\0addtest=setenv bootargs ${bootargs} loglevel=4 test\0baudrate=115200\0boot_file=setenv bootfile /${project_dir}/kernel/uImage\0boot_retries=0\0bootcmd=run flash_self\0bootdelay=3\0ethact=macb0\0flash_nfs=run nand_kernel;run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0flash_self=run nand_kernel;run setbootargs;upgrade_available;bootm ${kernel_ram};reset\0flash_self_test=run nand_kernel;run setbootargs addtest; upgrade_available;bootm ${kernel_ram};reset\0hostname=systemone\0kernel_Off=0x00200000\0kernel_Off_fallback=0x03800000\0kernel_ram=0x21500000\0kernel_size=0x00400000\0kernel_size_fallback=0x00400000\0loads_echo=1\0nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} ${kernel_size}\0net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0netdev=eth0\0nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs rw nfsroot=${serverip}:${rootpath} at91sam9_wdt.wdt_timeout=16\0partitionset_active=A\0preboot=echo;echo Type 'run flash_self' to use kernel and root filesystem on memory;echo Type 'run flash_nfs' to use kernel from memory and root filesystem over NFS;echo Type 'run net_nfs' to get Kernel over TFTP and mount root filesystem over NFS;echo\0project_dir=systemone\0root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0rootfs=/dev/mtdblock5\0rootfs_fallback=/dev/mtdblock7\0setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops root=${rootfs} rootfstype=jffs2 panic=7 at91sam9_wdt.wdt_timeout=16\0stderr=serial\0stdin=serial\0stdout=serial\0upgrade_available=0\0" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 174b80aeed..25b10888ce 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 9530061568..b9d387b88a 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index afff94ff37..88199c8e78 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index fcdcbd0228..539ed73495 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -12,7 +12,6 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 60cbfd9b2b..47f31c6d9d 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-bananapi-m64" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 5f7a09dffd..436bb64d85 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -42,9 +42,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y @@ -52,5 +49,5 @@ CONFIG_E1000=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_FRAMEBUFFER_VESA_MODE_11B=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index d7eab62c10..89e97db613 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_SPL_DM=y diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index 5a20dc96fd..edc24d62a0 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -42,13 +42,14 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index b9ad03bd2b..4f814e4172 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -42,13 +42,14 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 2079ed92e3..5511f2c78e 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -49,12 +49,9 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NETCONSOLE=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 66cea791ce..e00f409d7b 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -50,13 +50,10 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(MLO),128k(MLO.backup),128k(dtb),128k(u-boot-env),512k(u-boot),4m(kernel),128m(rootfs),-(user)" CONFIG_ENV_IS_IN_NAND=y CONFIG_NETCONSOLE=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y # CONFIG_MMC is not set CONFIG_NAND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 67c254fa06..e31fb94bff 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -26,6 +26,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -55,15 +56,12 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NETCONSOLE=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 4b07bea30a..d18bd939e5 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -50,11 +50,8 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NETCONSOLE=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 6a2b136c1c..cfc3268cc1 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_TSI148=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig index 234b1a5935..7908cfcc34 100644 --- a/configs/calimain_defconfig +++ b/configs/calimain_defconfig @@ -21,7 +21,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DIAG=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_DNS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0x01C23000 # CONFIG_MMC is not set diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index 0c95688711..3628821eaa 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -21,7 +21,6 @@ CONFIG_CMD_USB=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_DM=y CONFIG_SPI_FLASH=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index a868b16a35..29cae602de 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_DM=y CONFIG_DFU_MMC=y diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index 2b49782aa8..e28c683839 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -21,6 +21,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > " CONFIG_FASTBOOT=y @@ -46,6 +47,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DWC_AHSATA=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index a4215044c7..64e38b97db 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -28,9 +28,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index d934182dbb..344a3a08dc 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -34,7 +34,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 75b5d25f02..d8ab84b8e4 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_UART=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_CMD_GPIO=y @@ -31,7 +32,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 8811b41961..5dabae5434 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -17,6 +17,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_CMD_GPIO=y @@ -33,7 +34,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index cd3f910352..dfc022df2e 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -53,9 +53,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index f402f8c98f..deffd86cd8 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -40,9 +40,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index 3e93742e3b..c54c00f484 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -16,6 +16,7 @@ CONFIG_SILENT_CONSOLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_CMD_GPIO=y @@ -32,7 +33,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index cdd1ae5f67..8e6441b188 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -40,9 +40,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 841dce355a..eb85e6be5f 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -36,9 +36,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CROS_EC=y diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig index d826b70112..873f80dab0 100644 --- a/configs/cl-som-am57x_defconfig +++ b/configs/cl-som-am57x_defconfig @@ -3,11 +3,13 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_OMAP54XX=y CONFIG_TARGET_CL_SOM_AM57X=y # CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_VERSION_VARIABLE=y # CONFIG_SPL_EXT_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="U-Boot# " CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y @@ -24,6 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SCSI_AHCI=y CONFIG_CMD_PCA953X=y CONFIG_LED_STATUS=y @@ -42,7 +45,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 68803ae2f9..0861e6207f 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="CL-SOM-iMX7 # " CONFIG_CMD_BOOTZ=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 74936d762a..5926004001 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="CM-FX6 # " # CONFIG_CMD_XIMG is not set CONFIG_CMD_GREPENV=y @@ -45,6 +46,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DWC_AHSATA=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index c8390bd2c2..9b0eed8a69 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -45,7 +45,7 @@ CONFIG_LED_STATUS_BOOT_ENABLE=y CONFIG_LED_STATUS_BOOT=0 CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index f74854776d..917bd6a7e9 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="CM-T43 # " CONFIG_CMD_ASKENV=y CONFIG_CMD_EEPROM=y @@ -41,6 +42,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_MMC_OMAP_HS=y @@ -55,7 +57,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index 24c2a60f09..20cb0fde0b 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SCSI_AHCI=y CONFIG_MMC_OMAP_HS=y CONFIG_SCSI=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 8a15a3eaf1..03ac4a1b81 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -11,8 +11,5 @@ CONFIG_CMD_IMLS=y # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_BAUDRATE=19200 diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 1711c8a37f..c19e782e41 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL" CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y @@ -48,6 +49,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/colibri_imx6_nospl_defconfig b/configs/colibri_imx6_nospl_defconfig index 7b655663e5..aecc179161 100644 --- a/configs/colibri_imx6_nospl_defconfig +++ b/configs/colibri_imx6_nospl_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg CONFIG_BOOTDELAY=1 # CONFIG_CONSOLE_MUX is not set CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y @@ -37,6 +38,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index d4fe57f7b2..b6139c0c38 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -43,6 +43,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index c305e9915f..2a2a82321e 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -23,9 +23,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_MTD_NOR_FLASH=y CONFIG_DM_SERIAL=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 7e04549d21..90777e0201 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -29,7 +29,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=tegra_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=tegra_nand:2m(u-boot)ro,1m(u-boot-env),1m(cfgblock)ro,-(ubi)" CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 73d1bb5091..83cca5c406 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -22,7 +22,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_SPL_DM=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 07c9bd87ea..77ad26e017 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -39,6 +39,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=vf610_nfc:128k(vf-bcb)ro,1408k(u-boot)ro,512k( CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_NAND=y diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index e6007b5dcc..e9c82674a2 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO2_VOLT=1800 diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index e2276a805d..26726ab960 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -46,9 +46,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 73298041b7..6c2771e8d4 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -44,9 +44,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 50363ba1fe..5fe18c6264 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -17,6 +17,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_GO is not set diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot_defconfig index ecedc8b4c5..cc3a6c0a3f 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot_defconfig @@ -33,9 +33,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_TPM_TIS_LPC=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index c15a7966af..d90d4335e3 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -36,9 +36,6 @@ CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 7ee7dfb65f..0310bbb723 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -29,9 +29,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SYS_NS16550=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index d2e5290fad..2ef8d39dfc 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -36,9 +36,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index 3699903667..a216c9888d 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -18,6 +18,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y @@ -33,7 +34,6 @@ CONFIG_CRC32_VERIFY=y CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_DNS=y CONFIG_DM=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 2374e39cbf..90f4f5b16d 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -17,6 +17,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CRC32_VERIFY=y @@ -35,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:512k(u-boot.ais),64k(u-boot-env),7552k( CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_DNS=y CONFIG_DM=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 5ff12ac517..bde8995d73 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -34,7 +34,6 @@ CONFIG_CRC32_VERIFY=y CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_DNS=y CONFIG_DM=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index b0a8c1ada7..16e94d3623 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -22,7 +22,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 6840992c6f..a867db80d7 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -17,14 +17,15 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 8fa4884953..ece22b9cce 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y @@ -24,8 +25,8 @@ CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 8de55472ae..afa666140f 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -25,8 +26,8 @@ CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index cff4981530..ec0c5c89a9 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y @@ -25,8 +26,8 @@ CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig index a814e8dd21..4161262bc9 100644 --- a/configs/dbau1000_defconfig +++ b/configs/dbau1000_defconfig @@ -18,7 +18,4 @@ CONFIG_CMD_IDE=y CONFIG_CMD_DHCP=y CONFIG_MAC_PARTITION=y # CONFIG_ISO_PARTITION is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig index ca8aee6cb0..96305e40f8 100644 --- a/configs/dbau1100_defconfig +++ b/configs/dbau1100_defconfig @@ -18,7 +18,4 @@ CONFIG_CMD_IDE=y CONFIG_CMD_DHCP=y CONFIG_MAC_PARTITION=y # CONFIG_ISO_PARTITION is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig index 3c12f77232..eb83a3dbbb 100644 --- a/configs/dbau1500_defconfig +++ b/configs/dbau1500_defconfig @@ -18,7 +18,4 @@ CONFIG_CMD_IDE=y CONFIG_CMD_DHCP=y CONFIG_MAC_PARTITION=y # CONFIG_ISO_PARTITION is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig index a7864b6171..619874a98f 100644 --- a/configs/dbau1550_defconfig +++ b/configs/dbau1550_defconfig @@ -13,7 +13,4 @@ CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_ISO_PARTITION is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig index 9cbba5503e..b1e448073b 100644 --- a/configs/dbau1550_el_defconfig +++ b/configs/dbau1550_el_defconfig @@ -14,7 +14,4 @@ CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set # CONFIG_ISO_PARTITION is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index fa35748b94..a88cf1cb25 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -36,6 +36,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_NAND=y CONFIG_SPL_NAND_SIMPLE=y CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=31 CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index 700662a981..8827e052ec 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -42,9 +42,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 530ff79a35..de1016eb70 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_UNZIP=y CONFIG_CMD_DFU=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index aa6c04018a..a7cdf0fbf7 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 83eac075de..a5f1cf1e92 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SAVEENV=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="display5 > " CONFIG_CMD_BOOTZ=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index a2c8a561d4..8c07f25c5d 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -21,6 +21,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET_SUPPORT=y CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index af2359758f..8c1a55f325 100644 --- a/configs/dms-ba16-1g_defconfig +++ b/configs/dms-ba16-1g_defconfig @@ -33,6 +33,7 @@ CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_MXC_SPI=y CONFIG_USB=y diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig index 33d44b41c7..578cd691ab 100644 --- a/configs/dms-ba16_defconfig +++ b/configs/dms-ba16_defconfig @@ -32,6 +32,7 @@ CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_MXC_SPI=y CONFIG_USB=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index cb210cf8f0..e17135c8f6 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL=y CONFIG_ARMV7_LPAE=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y @@ -23,6 +24,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 @@ -37,6 +39,7 @@ CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y @@ -60,10 +63,11 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_SPL_PHY=y +CONFIG_PIPE3_PHY=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 3e18023b0e..606f99938c 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL=y CONFIG_ARMV7_LPAE=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -28,6 +29,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 @@ -39,6 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_REGMAP=y @@ -59,10 +62,11 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y CONFIG_DM_ETH=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY_GIGE=y CONFIG_SPL_PHY=y +CONFIG_PIPE3_PHY=y CONFIG_PMIC_PALMAS=y CONFIG_PMIC_LP873X=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 87b0726c75..cb4904261a 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y @@ -53,9 +54,6 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y @@ -65,7 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 697a71b7dc..9d72aea435 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -17,6 +17,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y @@ -24,8 +25,8 @@ CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y @@ -40,6 +41,7 @@ CONFIG_SPL_OF_TRANSLATE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_PCI=y diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 9f5d22ae3a..8f469fbc34 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig index c55a93c0fd..23ca1b7f63 100644 --- a/configs/duovero_defconfig +++ b/configs/duovero_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_NETDEVICES=y CONFIG_SMC911X=y diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig index 5997b33c6e..7332909547 100644 --- a/configs/ea20_defconfig +++ b/configs/ea20_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_BMP=y CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_DNS=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 9da69ef31a..844a2546e0 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_DATE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y CONFIG_LED_STATUS_BIT=8 diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 9e2a53215d..ca9e8a03e7 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -13,9 +13,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_DATE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y CONFIG_LED_STATUS_BIT=8 diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index eea434c45d..44e83a2d4b 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -26,7 +26,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader-nand),1024k(uboot-nand),256k(params-nand),5120k(kernel),-(ubifs)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y CONFIG_SYS_OMAP24_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig index 1a22ef060e..f1abde6a08 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_NET is not set -CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 77f82af27a..c83370b108 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y @@ -53,9 +54,6 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y @@ -65,7 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index 80ca4acfd7..d2432e0096 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -24,8 +24,8 @@ CONFIG_CMD_SAVES=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_RARP=y CONFIG_CMD_DHCP=y +CONFIG_CMD_RARP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CDP=y @@ -43,9 +43,6 @@ CONFIG_CMD_REISER=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index eeea3f7f70..467be641c6 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -12,10 +12,6 @@ CONFIG_PRE_CON_BUF_ADDR=0x1e720000 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_I2C=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_REGMAP=y CONFIG_CLK=y CONFIG_DM_I2C=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 575fd10d43..33775e8cdd 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_SPI=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_REGMAP=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 048c855884..d625fb1c5f 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index fc038aefee..d1f7f777ed 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -30,7 +30,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index b2fe19a4d0..0f254c0972 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig index 88f08d47dc..50462b44c3 100644 --- a/configs/flea3_defconfig +++ b/configs/flea3_defconfig @@ -20,9 +20,6 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)" CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_MXC_GPIO=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 24f3a832da..02cc9677aa 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -19,7 +19,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 233137b882..1751ed92d8 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -35,9 +35,6 @@ CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index f11ba1220d..caff63eb59 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index 95ccbdefea..6c222d6fba 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -24,9 +24,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_PHYLIB=y CONFIG_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index b0eba06238..80bdb20e8a 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -13,7 +13,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2" CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 33b3ba5fce..d716fc3546 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -19,7 +19,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 37f61902d3..844decad2d 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -2,7 +2,7 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_TARGET_HSDK=y CONFIG_SYS_TEXT_BASE=0x81000000 -CONFIG_SYS_CLK_FREQ=1000000000 +CONFIG_SYS_CLK_FREQ=500000000 CONFIG_DEFAULT_DEVICE_TREE="hsdk" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 3d89c4b327..a3c4b0e76c 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index ff5f64ab92..b1d6ed11f1 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 763222cc4c..bfd8f002e1 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 91cc85b596..b370eacc05 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index e7e046c657..29f807ab97 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -19,7 +19,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-d978-rev2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index b68147a6b4..8fca6e81ed 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_I2C_SUPPORT=y CONFIG_CMD_UNZIP=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 481a3c7dd6..b6621113e8 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -30,10 +30,6 @@ CONFIG_CMD_JFFS2=y CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)" CONFIG_CMD_UBI=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_I2C=y CONFIG_SYS_BOOTCOUNT_ADDR=0x9 diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig deleted file mode 100644 index bd5717bb89..0000000000 --- a/configs/imx31_phycore_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_BOOTDELAY=3 -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="uboot> " -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" -CONFIG_ENV_IS_IN_EEPROM=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xa8000000 -CONFIG_SMC911X_32_BIT=y diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig deleted file mode 100644 index 7be4f899a8..0000000000 --- a/configs/imx31_phycore_eet_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE_EET=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_MXC_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_NETDEVICES=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xa8000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_MXC_SPI=y -CONFIG_VIDEO=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index b4e1dbb06a..f0974bfa15 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)" CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 24ca2dce04..100d075960 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 8de41e5e79..9d6e340f08 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index 635b763290..4caf3075cd 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index 32b8568087..1eea0c66a5 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 15889093fc..46fa4ee775 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -16,7 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index 4f9d750bae..b928622813 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index a4062906dd..670e371df9 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index a8a1045c7f..fea531f6b8 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index 126ee3d435..8b6d188478 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index 2ca69595c2..d7ac44189d 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_ARMFLASH=y CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_PCI=y diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig index 13e031119c..e495a8c8b8 100644 --- a/configs/ipam390_defconfig +++ b/configs/ipam390_defconfig @@ -33,6 +33,5 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot), CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y # CONFIG_MMC is not set CONFIG_SYS_NS16550=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 94c7cbe1bf..00bb745be2 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN4I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index c90cb6ab20..fb2e30046c 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_SPL_DM=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index b1be0ff77f..b817a69bdc 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -18,6 +18,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index c71f67ce44..87b887c687 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -18,6 +18,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set @@ -30,6 +31,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index b0c0e08584..86cb5269d3 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -24,6 +24,7 @@ CONFIG_OF_CONTROL=y CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y # CONFIG_BLK is not set CONFIG_DM_MMC=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 38ba413145..feda22b743 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -18,6 +18,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 5f73d95ffa..4ff69feee7 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -18,6 +18,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set # CONFIG_CMD_GPT is not set diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index f4674efb68..0bfb5942aa 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=8 CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index 653dc92ca3..5f378f74a8 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index 0a55ed407a..ae20d245b1 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index dba9eb7b7d..22bc6cd83f 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index 1d92b2dd99..bf92d256a4 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -33,9 +33,6 @@ CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 # CONFIG_MMC is not set diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 1440849250..4e78d37ad4 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);app:-(ubi1);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8 # CONFIG_MMC is not set diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 63654c35cd..5c123a4ad8 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 1d9b982104..e64a6936db 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8 # CONFIG_MMC is not set diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig index 995061781b..2298e2ae38 100644 --- a/configs/kmlion1_defconfig +++ b/configs/kmlion1_defconfig @@ -33,9 +33,6 @@ CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 # CONFIG_MMC is not set diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index 0dd32016a1..4749eadb74 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index cd34d5dd18..c6ad62255d 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig index ed6540fed4..de68d41577 100644 --- a/configs/kmsugp1_defconfig +++ b/configs/kmsugp1_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index eca15363cc..eb4c4b433b 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig index b662077ef9..892f212bfa 100644 --- a/configs/kmsuv31_defconfig +++ b/configs/kmsuv31_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 5e5ffc4c5f..f3ca988c62 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -27,9 +27,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),256k(qe-fw),128k(env),128k(e CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 322e725e24..cf17002d56 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index 4a1b932d5b..b148f80346 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 1246dde599..8875b59a7f 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -1,17 +1,37 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0xE6304000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_R8A7791=y CONFIG_TARGET_KOELSCH=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -19,21 +39,42 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_RENESAS_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y -CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -CONFIG_BAUDRATE=38400 +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SH_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig new file mode 100644 index 0000000000..1df9a61deb --- /dev/null +++ b/configs/kp_imx6q_tpc_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_MX6_DDRCAL=y +CONFIG_TARGET_KP_IMX6Q_TPC=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SPL_RAW_IMAGE_SUPPORT=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="." +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 0dc493c05f..ca53005ecb 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_REGMAP=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 1ce7949d74..86fab8c014 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index 18ddb45d95..931496c8de 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=8 CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 1e2ce4bfb0..6072680e47 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig index 4cada2cc33..78c723ebd1 100644 --- a/configs/ma5d4evk_defconfig +++ b/configs/ma5d4evk_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTARGS="console=ttyS3,115200" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -42,9 +43,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index ec5168fc93..43770c6fec 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -16,13 +16,14 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_TIME=y diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index d9d756dbac..990944c148 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)" CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 2ad871c70b..ff0a935b8e 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor" CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(kernel.nor),8m@0x980000(swupdate-kernel.nor),8m@0x1180000(swupdate-rootfs.nor),128k@0x1980000(kernel-dtb.nor),128k@0x19C0000(swupdate-kernel-dtb.nor)" CONFIG_ENV_IS_IN_FLASH=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index 90012f0f40..e14780927c 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -33,7 +33,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),6m(k_recovery),8m(fs_recovery),-(common_data)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 5a437e2140..1de7821a72 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig index 4aa9602900..e4dfe3e04a 100644 --- a/configs/meesc_dataflash_defconfig +++ b/configs/meesc_dataflash_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig index 9d38247221..a6b2936b47 100644 --- a/configs/meesc_defconfig +++ b/configs/meesc_defconfig @@ -19,9 +19,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig index 6a96b62eb5..89a83fdc8b 100644 --- a/configs/mgcoge3un_defconfig +++ b/configs/mgcoge3un_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 18bec1f2e5..2cbabf67f2 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -30,8 +30,8 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_SAVES=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_JFFS2=y @@ -42,9 +42,6 @@ CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_NETCONSOLE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPL_DM=y CONFIG_XILINX_GPIO=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 35477131a6..37298a34f8 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -45,9 +45,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y @@ -57,5 +54,5 @@ CONFIG_DEBUG_UART_CLOCK=1843200 CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_FRAMEBUFFER_VESA_MODE_11B=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index bc1f223e3f..af5b9cc6a4 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 963cb0d5ca..79d984ba7b 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index f8c7171356..5129b49506 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 3fd5ca6d66..81d121fb84 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUNXI_NO_PMIC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index c5caed5b9e..84ae234fdc 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index bdb567952b..e10b6e76d8 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index 6da1c932c7..81ed01e61d 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -30,7 +30,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_SPARTAN3=y CONFIG_SYS_OMAP24_I2C_SPEED=400000 diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig deleted file mode 100644 index 9a4622577c..0000000000 --- a/configs/mx31ads_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_MX31ADS=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MXC_GPIO=y -# CONFIG_MMC is not set -CONFIG_MTD_NOR_FLASH=y -CONFIG_MXC_SPI=y diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig index ef900ec78d..d101de2caa 100644 --- a/configs/mx35pdk_defconfig +++ b/configs/mx35pdk_defconfig @@ -24,9 +24,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg), CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_MXC_GPIO=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index 351b8cd5d2..3923a36b0d 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -12,9 +12,9 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y -CONFIG_CMD_PXE=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 1b3857753b..6222ac608a 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 77958c8e65..2e4e0ff988 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y CONFIG_FSL_ESDHC=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index a56d685eee..c2d1cd4310 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -51,6 +51,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index c467588009..6ea92bb480 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig index 9c03546209..7b408e2221 100644 --- a/configs/mx6sxsabresd_spl_defconfig +++ b/configs/mx6sxsabresd_spl_defconfig @@ -40,6 +40,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 821c8f9283..fd6962ef5d 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index d1448c552c..86c942ca94 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 1172f41f90..7a85397a74 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 0475c1f7ab..0db69cd56d 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 122fcc5794..0a04911c81 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index e0892c1490..e0ae3c7c60 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index 26483c6c66..ee22364760 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index f27529d7d4..35058186f5 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index b8860c1409..f953b71f03 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air" CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index 87eb243481..66919e5a2b 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo" CONFIG_CONSOLE_MUX=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 5f69799e06..70798a8e9f 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index 496833683d..f39d5949dc 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -28,7 +28,6 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_USB=y # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set CONFIG_OF_EMBED=y # CONFIG_DM_DEVICE_REMOVE is not set diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 3d593fa6ab..7417622152 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_TPM=y CONFIG_CMD_TPM_TEST=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIVE=y CONFIG_SPL_DM=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index bd3a7de1f0..5943c19cf9 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ADC=y CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index 810874de3b..04a5e2cc3a 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_DM_MMC=y diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig index a0c8a36369..08d99624d7 100644 --- a/configs/omap3_pandora_defconfig +++ b/configs/omap3_pandora_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set -# CONFIG_CMD_MII is not set CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 9fb4aec3ca..7e01646a59 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 7d4b7084e5..abff63dd8a 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SCSI_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 8adcf5577d..4bd2fee227 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_BOOTP_DNS=y CONFIG_DM=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index cff15a95cf..a2735bc9a8 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -38,8 +38,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index ddd1acc580..577a32255b 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 770a4c2391..f3fd864a6d 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 575b3051fe..23f4973e5b 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 893780a0f7..dd5f2c78ab 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index c1e9acae36..134db79e72 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index f05e957f58..01c1cd7736 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 8488a6c19d..a6e61a5065 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 1542519869..8e32b0af32 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -14,7 +14,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_SY8106A_POWER=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 759f825cf9..df39caa903 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 0fd297752d..d7211b5823 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -8,7 +8,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index b48f13e7b1..fdb6bb4ed9 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 027be0d8a9..e88db0b52c 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -19,7 +19,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_CMD_EXT4_WRITE=y diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index 4e3438d0c1..7aafee50b7 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/p212_defconfig b/configs/p212_defconfig index b6923f3a67..44221fc8d6 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -20,6 +20,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=8 CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index fc3c4075d6..991e9b99aa 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -14,7 +14,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 071662f505..c07283d865 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig index 5202212129..68f714cba9 100644 --- a/configs/pb1000_defconfig +++ b/configs/pb1000_defconfig @@ -17,7 +17,4 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_ISO_PARTITION is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 079ac8bce5..3f06b6a9d2 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -39,10 +39,11 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index f43c00801e..6a30fc0d43 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -39,10 +39,11 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index 51a73299cf..3ef7a8a43a 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -23,6 +23,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 0a8edb4e7c..ab88d0680f 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -44,9 +44,10 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),512k(SPL.backup1),512k(SPL.backup2),512k(SPL.backup3),1536k(u-boot),512k(u-boot-spl-os),512k(u-boot-env),5m(kernel),-(rootfs)" CONFIG_CMD_DIAG=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index b9ee513a1b..28efd9da5b 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -28,10 +28,12 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_NETDEVICES=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index 27c3d583b3..eacd6b45b8 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -23,6 +23,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 09447b1e68..66decf0653 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 012494162d..ef52dcb2d2 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_USB=y diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig index 19b96ba4c1..21df1a1df5 100644 --- a/configs/picosam9g45_defconfig +++ b/configs/picosam9g45_defconfig @@ -33,9 +33,6 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index 23365a57c3..21ce06f370 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -7,7 +7,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_PHY_REALTEK=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index aea37fec2b..5ca2930f5d 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -19,7 +19,6 @@ CONFIG_CMD_USB=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index cd11aec4f5..c48975f9bf 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -28,9 +28,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0,nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),-(rootfs);nand:-(nand)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 7d9b3d235c..93820921c9 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -28,9 +28,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=physmap-flash.0,nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),-(rootfs);nand:-(nand)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index a78b277000..2a59ff38a8 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -20,9 +20,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_JFFS2=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 2759b72dd0..03931c8f05 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index 175ef2056b..f6ba2370db 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 4354c60f37..8343a4ab4d 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -30,7 +30,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index f90825c204..1a922429af 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -1,7 +1,9 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_RMOBILE=y CONFIG_SYS_TEXT_BASE=0x50000000 -CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -12,12 +14,17 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -39,21 +46,16 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas power-domains" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +CONFIG_RENESAS_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y @@ -65,7 +67,6 @@ CONFIG_DM_PCI=y CONFIG_PCI_RCAR_GEN2=y CONFIG_PINCTRL=y CONFIG_PINCONF=y -CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_PFC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig index 6dc270a035..8a6d996f3d 100644 --- a/configs/portl2_defconfig +++ b/configs/portl2_defconfig @@ -26,9 +26,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_RAM=y # CONFIG_MMC is not set diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index 7e1e6c776e..fd829f57ea 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_MUSB_HOST=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index e0a27b798a..4324a82e76 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 5833a1af31..76a0d971ee 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " @@ -55,9 +56,6 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y @@ -67,7 +65,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 48e2623aca..0ef7e2c473 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=2 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index 80e16e427c..18e0849853 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 275fb19dd2..0b3973dadc 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index 569fb7ebcc..322d01d8a4 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -18,7 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 10bbc76a53..b197eff328 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -54,9 +54,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y @@ -69,5 +66,5 @@ CONFIG_SPL_TIMER=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_FRAMEBUFFER_VESA_MODE_112=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 311fae3360..c5506c6615 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -39,9 +39,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y @@ -49,5 +46,5 @@ CONFIG_NVME=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_FRAMEBUFFER_VESA_MODE_112=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/qemu-x86_efi_payload32_defconfig b/configs/qemu-x86_efi_payload32_defconfig index d2fc5462c8..3e191b8a3a 100644 --- a/configs/qemu-x86_efi_payload32_defconfig +++ b/configs/qemu-x86_efi_payload32_defconfig @@ -34,16 +34,13 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_FRAMEBUFFER_VESA_MODE_112=y CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/qemu-x86_efi_payload64_defconfig b/configs/qemu-x86_efi_payload64_defconfig index 9fd563ed34..43f368ffb9 100644 --- a/configs/qemu-x86_efi_payload64_defconfig +++ b/configs/qemu-x86_efi_payload64_defconfig @@ -34,16 +34,13 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y -CONFIG_FRAMEBUFFER_VESA_MODE_111=y +CONFIG_FRAMEBUFFER_VESA_MODE_112=y CONFIG_CONSOLE_SCROLL_LINES=5 CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig index c85f83697a..ca90fd52d9 100644 --- a/configs/qemu_mips64_defconfig +++ b/configs/qemu_mips64_defconfig @@ -10,15 +10,12 @@ CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_RARP=y CONFIG_CMD_DHCP=y +CONFIG_CMD_RARP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_LZMA=y diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig index b7b92342db..04c4484e86 100644 --- a/configs/qemu_mips64el_defconfig +++ b/configs/qemu_mips64el_defconfig @@ -11,15 +11,12 @@ CONFIG_CMD_IDE=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_RARP=y CONFIG_CMD_DHCP=y +CONFIG_CMD_RARP=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_LZMA=y diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig index 3d61176a92..ece5e647d0 100644 --- a/configs/qemu_mips_defconfig +++ b/configs/qemu_mips_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_LZMA=y diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig index 189453a4b4..52bcbe13c9 100644 --- a/configs/qemu_mipsel_defconfig +++ b/configs/qemu_mipsel_defconfig @@ -15,9 +15,6 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_NS16550=y CONFIG_LZMA=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 2301e0190a..9a66ee90f9 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP152_POWER=y CONFIG_CONS_INDEX=2 diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index 44921d911d..fdfa41c395 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -6,6 +6,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -37,7 +38,10 @@ CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index e85d0a4c31..5b15e74d0c 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -6,6 +6,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -37,7 +38,10 @@ CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig index 6420249181..986c076d51 100644 --- a/configs/r8a77965_salvator-x_defconfig +++ b/configs/r8a77965_salvator-x_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A7796=y CONFIG_TARGET_SALVATOR_X=y CONFIG_DEFAULT_DEVICE_TREE="r8a77965-salvator-x-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -38,7 +39,7 @@ CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index e0cf17a44b..fefc719d1d 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A7796=y CONFIG_TARGET_SALVATOR_X=y CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -38,7 +39,10 @@ CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 5a65982070..3fee38d641 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A7796=y CONFIG_TARGET_ULCB=y CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -38,7 +39,10 @@ CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 3d421d22df..f2861924f6 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A77970=y CONFIG_TARGET_EAGLE=y CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -17,7 +18,8 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -28,16 +30,21 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_BLK=y CONFIG_CLK=y CONFIG_CLK_RENESAS=y CONFIG_DM_GPIO=y CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y -CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y @@ -49,6 +56,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 99a8089851..d3cccec8fc 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -7,6 +7,7 @@ CONFIG_R8A77995=y CONFIG_TARGET_DRAAK=y CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot" CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" @@ -38,7 +39,10 @@ CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y CONFIG_DM_MMC=y -CONFIG_MMC_UNIPHIER=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 30ef7fcd93..533104f4a5 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y @@ -53,9 +54,6 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y @@ -65,7 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index d0d5dffe25..a59599ebbc 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 3570dc9d9b..fcc2ae68c9 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_USB=y CONFIG_OF_EMBED=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 1e3e08e8ec..204af74239 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_USB=y CONFIG_OF_EMBED=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 05586b5933..9e142cae63 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_OF_EMBED=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index d8836f9be4..f46e504497 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_USB=y CONFIG_OF_EMBED=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index d9c78a5e0a..82c90d40e1 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_USB=y CONFIG_OF_EMBED=y CONFIG_ENV_FAT_INTERFACE="mmc" CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 7605b0e285..84ff35cf19 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " @@ -56,9 +57,6 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y @@ -68,7 +66,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 237b590ad7..a54dd5f3a3 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y # CONFIG_NET is not set CONFIG_DFU_MMC=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index 5014216c9b..e14db986dd 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -19,12 +19,12 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDPARTS_DEFAULT="mtdparts=samsung-onenand:128k(s-boot),896k(bootloader),256k(params),2816k(config),8m(csa),7m(kernel),1m(log),12m(modem),60m(qboot),-(UBI)" CONFIG_OF_CONTROL=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_SYS_I2C_S3C24X0=y CONFIG_DM_MMC=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 3cd6e98ad1..1c32d50e89 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -38,9 +38,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 4f427ca1ba..7a52c10181 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -27,9 +27,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index a7681124f6..2739001cf1 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -27,9 +27,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index cd53ac5d1e..9308ca76b1 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -39,9 +39,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 9994f53b83..185ed94eb1 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -36,9 +37,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 186f9f4bdb..1adc6acd0d 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -28,9 +28,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 83bea11571..8a2db44929 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -28,9 +28,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 4d3b83c4f8..d7b809151b 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -28,9 +28,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 1e1d92e739..e626d021ce 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -42,9 +42,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 9ff7651245..2468df914b 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -39,9 +39,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 539404815e..4fceabb849 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -44,9 +44,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index fda2c442b2..308bb54680 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -39,9 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 88a9fa11cb..405ee4433d 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -38,9 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 59edbd0ae4..e8d748f469 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -38,9 +38,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_CLK=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index ce781115d1..5550891c61 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -35,9 +35,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_CLK=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 73aa58395a..1e0c419e16 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -36,9 +37,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 81812a65f8..a9fd08f363 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -40,9 +40,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_FAT=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index dc84cff247..bdb42f129c 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -37,9 +37,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 0c4ffa8e54..df576677e5 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256K(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set @@ -36,9 +37,6 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 866c4401dc..f5cd63a48f 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -13,9 +13,6 @@ CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index 5752fce4af..34ec8490e8 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -13,9 +13,6 @@ CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 4bd06037f9..4f9a69f3a5 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -11,9 +11,6 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig index 6c0ff6b735..3837436702 100644 --- a/configs/sbc8548_PCI_33_PCIE_defconfig +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set # CONFIG_CMD_IRQ is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig index ff4065f790..874d1c064c 100644 --- a/configs/sbc8548_PCI_33_defconfig +++ b/configs/sbc8548_PCI_33_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set # CONFIG_CMD_IRQ is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig index 067201e4b8..8f4e0e070f 100644 --- a/configs/sbc8548_PCI_66_PCIE_defconfig +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set # CONFIG_CMD_IRQ is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig index b7ef6093b9..79f2544edd 100644 --- a/configs/sbc8548_PCI_66_defconfig +++ b/configs/sbc8548_PCI_66_defconfig @@ -18,9 +18,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set # CONFIG_CMD_IRQ is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig index a82ad0c15f..8bdc7d1005 100644 --- a/configs/sbc8548_defconfig +++ b/configs/sbc8548_defconfig @@ -16,9 +16,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y # CONFIG_CMD_HASH is not set # CONFIG_CMD_IRQ is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 2a2acc7bf8..75fe74d7d5 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -19,7 +19,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index db460978aa..ed3946b34b 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -31,6 +31,7 @@ CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index c747384e1b..96f30b3747 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -30,6 +30,7 @@ CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index f5cc2a97d8..b6d5f47bc8 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -33,6 +33,7 @@ CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index bba0ce76e7..309935d08e 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -1,17 +1,37 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0xE6304000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_R8A7794=y CONFIG_TARGET_SILK=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -19,21 +39,43 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_SH_MMCIF=y +CONFIG_RENESAS_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y -CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -CONFIG_BAUDRATE=38400 +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SH_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 4e1ef5fbfa..e0d6cd432e 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -39,9 +39,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:128k(Bootstrap),896k(U-Boot),512k(E CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 4338f3a87b..d70054bfe4 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -25,9 +25,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_CMD_PCA953X=y # CONFIG_MMC is not set CONFIG_USB=y diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index cf2ca31975..9954be567f 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -24,9 +24,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_CMD_PCA953X=y # CONFIG_MMC is not set CONFIG_USB=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index cd414fedd5..0717a84b68 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -13,9 +13,12 @@ CONFIG_BOOTARGS="console=ttyS0,115200" CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_FPGA_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index d8e7ced80f..0d6d80c51b 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -18,10 +18,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -53,6 +57,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 89318a0ab8..d85f3d056a 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -18,10 +18,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -54,6 +58,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index fcd914750d..faafebf2c5 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -17,12 +17,15 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -30,9 +33,9 @@ CONFIG_CMD_PART=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_DHCP=y -CONFIG_CMD_PXE=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -44,12 +47,14 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index b48f179fa5..efb13748b6 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -19,10 +19,13 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -48,6 +52,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 659226ba85..08b0b92615 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -18,10 +18,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -37,6 +40,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -44,6 +48,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 1e6eb86005..a2a8a7491b 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -24,6 +24,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -38,6 +40,7 @@ CONFIG_SPL_DM=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -45,6 +48,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 95311a23f8..6d5c27e8ee 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -18,9 +18,12 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_SF=y @@ -39,6 +42,7 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y @@ -48,5 +52,6 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 4993b2741e..1f8871b6ed 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -19,10 +19,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,12 +44,14 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index a324666b46..49d9db8df7 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -18,10 +18,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -41,6 +44,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -54,6 +58,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 0ce4e55a9b..b69c982a92 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -18,10 +18,13 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -42,6 +45,7 @@ CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -54,6 +58,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index ec9c7e03af..062afe16bc 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -20,10 +20,13 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -43,6 +46,7 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8 CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y @@ -53,6 +57,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_USE_TINY_PRINTF=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 77692491ef..15ac595bae 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -20,11 +20,14 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -70,6 +73,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_RESET=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 96c35dee1c..aad7ef3714 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -30,9 +30,6 @@ CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y # CONFIG_CMD_IRQ is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 55162911b5..a487715afb 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -41,9 +41,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index 503e3903ca..05436a1b43 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -14,7 +14,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 0f5950fed5..46790bbe0e 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PMIC=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_DM_MMC=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index fd7e2dc453..c933fbf214 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -1,17 +1,37 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0xE8080000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_R8A7790=y CONFIG_TARGET_STOUT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -19,21 +39,42 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_RENESAS_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y -CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -CONFIG_BAUDRATE=38400 +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SH_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index e5c5b42ad9..4cb2798ce7 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index c971aa4f5f..d88dd4ebad 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -14,7 +14,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9" CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 2fa97e273f..48fc91f46b 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 1c7c8f93ae..81b95b2903 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -22,6 +22,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index 2162544aa8..3e3de4fbb3 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -15,7 +15,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-tbs-a711" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_FLASH is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index f983f9b33c..77a3da4c06 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -21,7 +21,6 @@ CONFIG_CMD_USB=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_DM=y CONFIG_SPI_FLASH=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 2c237a4588..a14f2c2feb 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_SPL_DM=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index fa96b936d7..4623d00e6c 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -42,9 +42,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index dc756ba2ab..1fda8af1ef 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -41,9 +41,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index aa14da332b..3fc14e85c7 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -40,9 +40,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index 154d493583..044162b3b8 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -28,8 +29,8 @@ CONFIG_CMD_PCI=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 5136dba09b..8891c86459 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set CONFIG_HUSH_PARSER=y @@ -53,9 +54,6 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y @@ -65,7 +63,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OMAP3_SPI=y CONFIG_USB=y diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 891a4173d9..a68f997052 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -19,7 +19,6 @@ CONFIG_SYS_PROMPT="ThunderX_88XX> " # CONFIG_CMD_ENV_EXISTS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set CONFIG_DM=y # CONFIG_MMC is not set CONFIG_DM_SERIAL=y diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index 337f4f34fd..1121ba2322 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -32,10 +32,8 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_MMC_OMAP_HS=y -CONFIG_PHYLIB=y +CONFIG_DRIVER_TI_CPSW=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index cc4350848e..d5c705ae46 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index c2ecf13c0d..1619df303d 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y @@ -25,7 +26,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set -# CONFIG_CMD_MII is not set CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 62a220fb6d..5e55ebdaf8 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y @@ -25,7 +26,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set -# CONFIG_CMD_MII is not set CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index dffc04e14e..39cdb22ba6 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=0 CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="zynq-uboot> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 3ca154b1fa..f270fc9c31 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -22,11 +22,11 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_S3C24X0=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 019dca3602..c929157efe 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -21,11 +21,11 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set CONFIG_CMD_CACHE=y # CONFIG_CMD_MISC is not set CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DFU_MMC=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_S3C24X0=y diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 7dd7b45cf0..38e4a90dfe 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -21,7 +21,6 @@ CONFIG_CMD_USB=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SPL_DM=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 28712f783a..14f256abd4 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index db71c67f0b..a1183952e7 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 602e1dd6a8..d3b9ca25b6 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 # CONFIG_MMC is not set diff --git a/configs/twister_defconfig b/configs/twister_defconfig index b5d4838242..dffd8254fb 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -31,7 +31,6 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),6m(kernel),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_DNS=y CONFIG_SYS_OMAP24_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index 658f5771b6..2d8cedf8ea 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index ec0f152ff8..fb02fc5a55 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index ac3f3e2e58..2ff2c8babb 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -24,9 +24,6 @@ CONFIG_CMD_PING=y CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig index d1a3ffde01..12312261c4 100644 --- a/configs/vct_platinum_defconfig +++ b/configs/vct_platinum_defconfig @@ -15,10 +15,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y CONFIG_SMC911X=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig index 52e1f49bb0..b1ac814058 100644 --- a/configs/vct_platinum_onenand_defconfig +++ b/configs/vct_platinum_onenand_defconfig @@ -22,10 +22,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(r CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_NETDEVICES=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x00000000 diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig index 174a840f39..974d47b4d0 100644 --- a/configs/vct_platinumavc_defconfig +++ b/configs/vct_platinumavc_defconfig @@ -10,7 +10,6 @@ CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig index c33dc0d4f9..8e219ecdc4 100644 --- a/configs/vct_platinumavc_onenand_defconfig +++ b/configs/vct_platinumavc_onenand_defconfig @@ -12,7 +12,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_ONENAND=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set CONFIG_CMD_JFFS2=y CONFIG_MTDIDS_DEFAULT="onenand0=onenand" CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(rootfs)" diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig index f975d17c9f..987cd793b8 100644 --- a/configs/vct_premium_defconfig +++ b/configs/vct_premium_defconfig @@ -15,10 +15,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y CONFIG_SMC911X=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig index 222b7544ec..523ea486dc 100644 --- a/configs/vct_premium_onenand_defconfig +++ b/configs/vct_premium_onenand_defconfig @@ -22,10 +22,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=onenand:128k(u-boot),128k(env),20m(kernel),-(r CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_IS_IN_ONENAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_NETDEVICES=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x00000000 diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index 78aab9fc25..822d5ef196 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 9d6d7631ee..550038c8fe 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -22,7 +22,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_DM=y CONFIG_DFU_MMC=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index e642734bf0..70e28f7db7 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -17,7 +17,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index e8dad4468b..a47e0ba2d6 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -26,9 +26,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index dc2f85da93..1d28b2f1db 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PCI=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index a22d55fcb1..df5cd19376 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -14,9 +14,6 @@ CONFIG_CMD_TSI148=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_DATE=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_NETDEVICES=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 7644d739bd..bf1de5a56e 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index e6707a03c0..03335298eb 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_FSL_ESDHC=y diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig index 7018516780..02083520b6 100644 --- a/configs/wb45n_defconfig +++ b/configs/wb45n_defconfig @@ -23,8 +23,5 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y CONFIG_LZMA=y CONFIG_OF_LIBFDT=y diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig index ce3677bc28..306e4c16bf 100644 --- a/configs/wb50n_defconfig +++ b/configs/wb50n_defconfig @@ -23,9 +23,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig index 4c2d28050a..62cad079c2 100644 --- a/configs/woodburn_defconfig +++ b/configs/woodburn_defconfig @@ -25,9 +25,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64 CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_MXC_GPIO=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig index 7726472c9a..21d92d99c2 100644 --- a/configs/woodburn_sd_defconfig +++ b/configs/woodburn_sd_defconfig @@ -36,9 +36,6 @@ CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_DNS=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_SUBNETMASK=y CONFIG_MXC_GPIO=y CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 150fb077dc..677672d0b6 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_DM=y CONFIG_DM_GPIO=y # CONFIG_MMC is not set CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_LPC32XX_SSP=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 1da4d8d5e6..77f2b037e7 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -44,6 +44,7 @@ CONFIG_FPGA_SPARTAN3=y CONFIG_SYS_I2C_DW=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y +CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_NETDEVICES=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig new file mode 100644 index 0000000000..f4e680d1be --- /dev/null +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1232 revA" +# CONFIG_SPL_FAT_SUPPORT is not set +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA" +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM=y +# CONFIG_BLK is not set +CONFIG_CLK_ZYNQMP=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig new file mode 100644 index 0000000000..77b4ada4e2 --- /dev/null +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1254 revA" +# CONFIG_SPL_FAT_SUPPORT is not set +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA" +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM=y +# CONFIG_BLK is not set +CONFIG_CLK_ZYNQMP=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig new file mode 100644 index 0000000000..17c1be879d --- /dev/null +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +# CONFIG_SPL_LIBDISK_SUPPORT is not set +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1275 revA" +# CONFIG_SPL_FAT_SUPPORT is not set +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA" +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +# CONFIG_CMD_NET is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM=y +# CONFIG_BLK is not set +CONFIG_CLK_ZYNQMP=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index c5bfa2b126..0272eea311 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -19,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y @@ -40,7 +41,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y @@ -70,6 +70,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index f86dce403a..2758bfb4da 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -20,6 +20,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y @@ -40,7 +41,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y @@ -66,6 +66,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig new file mode 100644 index 0000000000..a92361e146 --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm017_dc3" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm017 dc3" +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_NAND=y +CONFIG_NAND_ARASAN=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff010000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 6e947cf568..9a6a1e5733 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y @@ -29,7 +30,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y @@ -58,6 +58,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 1c934858c6..8d6b353a5f 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -17,6 +17,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y @@ -30,10 +31,10 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK_ZYNQMP=y @@ -46,6 +47,12 @@ CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig new file mode 100644 index 0000000000..4024017bf8 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu100" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU100 RevC" +CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000 +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff010000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_ZYNQ_SPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index e13c7c56f3..68da9dc75b 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -19,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y @@ -41,7 +42,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y @@ -76,6 +76,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 5b2cd495ee..2adba612d6 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -19,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y @@ -41,7 +42,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y @@ -76,6 +76,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index e6530fbfe7..2310fa8494 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -19,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_FASTBOOT=y CONFIG_FASTBOOT_FLASH=y @@ -41,7 +42,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FAT=y @@ -76,6 +76,7 @@ CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ZYNQ_GEM=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig new file mode 100644 index 0000000000..817f789133 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revA" +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig new file mode 100644 index 0000000000..4be3d8358a --- /dev/null +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu104" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU104 revC" +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revC" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig new file mode 100644 index 0000000000..8c9a60d3bf --- /dev/null +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu106" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU106 revA" +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C0=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_FUNCTION_THOR=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig new file mode 100644 index 0000000000..cb4542cae7 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu111" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU111" +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_ATF=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +CONFIG_SATA_CEVA=y +CONFIG_CLK_ZYNQMP=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_CMD_PCA953X=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C0=y +CONFIG_ZYNQ_I2C1=y +CONFIG_MISC=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_ZYNQ_GEM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig index b006deab2e..deaab12a6f 100644 --- a/configs/xpedite520x_defconfig +++ b/configs/xpedite520x_defconfig @@ -25,8 +25,6 @@ CONFIG_CMD_DATE=y # CONFIG_CMD_HASH is not set CONFIG_CMD_JFFS2=y # CONFIG_CMD_IRQ is not set -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y CONFIG_CMD_PCA953X=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index c84ae3cbf3..c1fec76487 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -29,6 +30,7 @@ CONFIG_CMD_SF=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index 958f8f5cf2..415664fef4 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -28,6 +29,7 @@ CONFIG_CMD_SF=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig index cdf624e528..b3eb1ca534 100644 --- a/configs/zmx25_defconfig +++ b/configs/zmx25_defconfig @@ -20,9 +20,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_BOOTP_BOOTPATH=y -CONFIG_BOOTP_GATEWAY=y -CONFIG_BOOTP_HOSTNAME=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_USB=y diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig index d328fe6cfe..170cfbd978 100644 --- a/configs/zynq_cc108_defconfig +++ b/configs/zynq_cc108_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index d93cdbfba5..2a3d8b200d 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=-1 # CONFIG_USE_BOOTCOMMAND is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 25331cac86..967c037123 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -12,6 +12,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig index 9013239a8f..5b13edb506 100644 --- a/configs/zynq_z_turn_defconfig +++ b/configs/zynq_z_turn_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL=y CONFIG_SPL_STACK_R_ADDR=0x200000 -CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir" +CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn" CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -13,6 +13,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 72c109b2e3..2c9210fdea 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_EEPROM=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 825a7263d2..dd1b1afab2 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_EEPROM=y diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index 683dfe8d19..214d7eb52b 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y @@ -28,7 +29,6 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index 9613b8af25..8db7b99d78 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_NAND_LOCK_UNLOCK=y # CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BLK=y diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig index 884186a460..036b73fd7b 100644 --- a/configs/zynq_zc770_xm011_x16_defconfig +++ b/configs/zynq_zc770_xm011_x16_defconfig @@ -27,14 +27,13 @@ CONFIG_CMD_NAND_LOCK_UNLOCK=y # CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BLK=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQPL=y CONFIG_DM_GPIO=y # CONFIG_MMC is not set -CONFIG_DM_MMC=y CONFIG_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_DEBUG_UART_ZYNQ=y diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 0b3db398f9..b3956eeda6 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index d7d9d80ce6..76f881a916 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_FLASH is not set CONFIG_CMD_FPGA_LOADBP=y @@ -25,7 +26,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 9f76e5ed8f..769c531ce6 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -13,6 +13,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_DFU=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 15922d2fa1..fbe22c5e10 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_EEPROM=y diff --git a/disk/Kconfig b/disk/Kconfig index f3050cfde1..8af2a95430 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -53,7 +53,6 @@ config ISO_PARTITION config SPL_ISO_PARTITION bool "Enable ISO partition table for SPL" depends on SPL && PARTITIONS - default y if ISO_PARTITION config AMIGA_PARTITION bool "Enable AMIGA partition table" diff --git a/doc/README.efi b/doc/README.efi deleted file mode 100644 index 956f5bfa0c..0000000000 --- a/doc/README.efi +++ /dev/null @@ -1,86 +0,0 @@ -# -# Copyright (C) 2015 Google, Inc -# -# SPDX-License-Identifier: GPL-2.0+ -# - -EFI on U-Boot -============= -This document provides information about the implementation of the UEFI API [1] -in U-Boot. - - -=========== Table of Contents =========== - -Motivation -How do I get it? -Status -Future work - - -Motivation ----------- - -With this API support in place, you can run any UEFI payload (such as the Linux -kernel, grub2 or gummiboot) on U-Boot. This dramatically simplifies boot loader -configuration, as U-Boot based systems now look and feel (almost) the same way -as TianoCore based systems. - -How do I get it? ----------------- - -EFI support for 32bit ARM and AArch64 is already included in U-Boot. All you -need to do is enable - - CONFIG_CMD_BOOTEFI=y - CONFIG_EFI_LOADER=y - -in your .config file and you will automatically get a bootefi command to run -an efi application as well as snippet in the default distro boot script that -scans for removable media efi binaries as fallback. - -Status ------- - -I am successfully able to run grub2 and Linux EFI binaries with this code on -ARMv7 as well as AArch64 systems. - -When enabled, the resulting U-Boot binary only grows by ~10KB, so it's very -light weight. - -All storage devices are directly accessible from the uEFI payload - -Removable media booting (search for /efi/boot/boota{a64,arm}.efi) is supported. - -Simple use cases like "Plug this SD card into my ARM device and it just -boots into grub which boots into Linux", work very well. - - -Running HelloWord.efi ---------------------- - -You can run a simple 'hello world' EFI program in U-Boot. -Enable the option CONFIG_CMD_BOOTEFI_HELLO. - -Then you can boot into U-Boot and type: - - > bootefi hello - -The 'hello world EFI' program will then run, print a message and exit. - - -Future work ------------ - -Of course, there are still a few things one could do on top: - - - Improve disk media detection (don't scan, use what information we -have) - - Add EFI variable support using NVRAM - - Add GFX support - - Make EFI Shell work - - Network device support - - Support for payload exit - - Payload Watchdog support - -[1] http://uefi.org/ diff --git a/doc/README.log b/doc/README.log index dc9e2deec5..2ee1b753bc 100644 --- a/doc/README.log +++ b/doc/README.log @@ -162,7 +162,8 @@ Code size --------- Code size impact depends largely on what is enabled. The following numbers are -for snow, which is a Thumb-2 board: +generated by 'buildman -S' for snow, which is a Thumb-2 board (all units in +bytes): This series: adds bss +20.0 data +4.0 rodata +4.0 text +44.0 CONFIG_LOG: bss -52.0 data +92.0 rodata -635.0 text +1048.0 diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab index 75390a505e..a40ebf3e84 100644 --- a/doc/README.mxc_hab +++ b/doc/README.mxc_hab @@ -33,12 +33,12 @@ Image Ver: 2 (i.MX53/6 compatible) Data Size: 327680 Bytes = 320.00 kB = 0.31 MB Load Address: 177ff420 Entry Point: 17800000 -HAB Blocks: 177ff400 00000000 0004dc00 - ^^^^^^^^ ^^^^^^^^ ^^^^^^^^ - | | | - | | -------- (1) - | | - | ------------------- (2) +HAB Blocks: 0x177ff400 0x00000000 0x0004dc00 + ^^^^^^^^^^ ^^^^^^^^^^ ^^^^^^^^^^ + | | | + | | ----- (1) + | | + | ---------------- (2) | --------------------------- (3) @@ -78,7 +78,7 @@ Example Output of the SPL (imximage) creation: Data Size: 61440 Bytes = 60.00 kB = 0.06 MB Load Address: 00907420 Entry Point: 00908000 - HAB Blocks: 00907400 00000000 0000cc00 + HAB Blocks: 0x00907400 0x00000000 0x0000cc00 Example Output of the u-boot-ivt.img (firmware_ivt) creation: Image Name: U-Boot 2016.11-rc1-31589-g2a4411 diff --git a/doc/README.uefi b/doc/README.uefi new file mode 100644 index 0000000000..bb89b7ac2f --- /dev/null +++ b/doc/README.uefi @@ -0,0 +1,334 @@ +<!-- + Copyright (c) 2018 Heinrich Schuchardt + + SPDX-License-Identifier: GPL-2.0+ +--> + +# UEFI on U-Boot + +The Unified Extensible Firmware Interface Specification (UEFI) [1] has become +the default for booting on AArch64 and x86 systems. It provides a stable API for +the interaction of drivers and applications with the firmware. The API comprises +access to block storage, network, and console to name a few. The Linux kernel +and boot loaders like GRUB or the FreeBSD loader can be executed. + +## Building for UEFI + +The UEFI standard supports only little endian systems. The UEFI support can be +activated for ARM and x86 by specifying + + CONFIG_CMD_BOOTEFI=y + CONFIG_EFI_LOADER=y + +in the .config file. + +Support for attaching virtual block devices, e.g. iSCSI drives connected by the +loaded UEFI application [3], requires + + CONFIG_BLK=y + CONFIG_PARTITIONS=y + +### Executing a UEFI binary + +The bootefi command is used to start UEFI applications or to install UEFI +drivers. It takes two parameters + + bootefi <image address> [fdt address] + +* image address - the memory address of the UEFI binary +* fdt address - the memory address of the flattened device tree + +Below you find the output of an example session starting GRUB. + + => load mmc 0:2 ${fdt_addr_r} boot/dtb + 29830 bytes read in 14 ms (2 MiB/s) + => load mmc 0:1 ${kernel_addr_r} efi/debian/grubaa64.efi + reading efi/debian/grubaa64.efi + 120832 bytes read in 7 ms (16.5 MiB/s) + => bootefi ${kernel_addr_r} ${fdt_addr_r} + +The environment variable 'bootargs' is passed as load options in the UEFI system +table. The Linux kernel EFI stub uses the load options as command line +arguments. + +### Executing the boot manager + +The UEFI specfication foresees to define boot entries and boot sequence via UEFI +variables. Booting according to these variables is possible via + + bootefi bootmgr [fdt address] + +As of U-Boot v2018.03 UEFI variables are not persisted and cannot be set at +runtime. + +### Executing the built in hello world application + +A hello world UEFI application can be built with + + CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y + +It can be embedded into the U-Boot binary with + + CONFIG_CMD_BOOTEFI_HELLO=y + +The bootefi command is used to start the embedded hello world application. + + bootefi hello [fdt address] + +Below you find the output of an example session. + + => bootefi hello ${fdtcontroladdr} + ## Starting EFI application at 01000000 ... + WARNING: using memory device/image path, this may confuse some payloads! + Hello, world! + Running on UEFI 2.7 + Have SMBIOS table + Have device tree + Load options: root=/dev/sdb3 init=/sbin/init rootwait ro + ## Application terminated, r = 0 + +The environment variable fdtcontroladdr points to U-Boot's internal device tree +(if available). + +### Executing the built-in selftest + +An UEFI selftest suite can be embedded in U-Boot by building with + + CONFIG_CMD_BOOTEFI_SELFTEST=y + +For testing the UEFI implementation the bootefi command can be used to start the +selftest. + + bootefi selftest [fdt address] + +The environment variable 'efi_selftest' can be used to select a single test. If +it is not provided all tests are executed except those marked as 'on request'. +If the environment variable is set to 'list' a list of all tests is shown. + +Below you can find the output of an example session. + + => setenv efi_selftest simple network protocol + => bootefi selftest + Testing EFI API implementation + Selected test: 'simple network protocol' + Setting up 'simple network protocol' + Setting up 'simple network protocol' succeeded + Executing 'simple network protocol' + DHCP Discover + DHCP reply received from 192.168.76.2 (52:55:c0:a8:4c:02) + as broadcast message. + Executing 'simple network protocol' succeeded + Tearing down 'simple network protocol' + Tearing down 'simple network protocol' succeeded + Boot services terminated + Summary: 0 failures + Preparing for reset. Press any key. + +## The UEFI life cycle + +After the U-Boot platform has been initialized the UEFI API provides two kinds +of services + +* boot services and +* runtime services. + +The API can be extended by loading UEFI drivers which come in two variants + +* boot drivers and +* runtime drivers. + +UEFI drivers are installed with U-Boot's bootefi command. With the same command +UEFI applications can be executed. + +Loaded images of UEFI drivers stay in memory after returning to U-Boot while +loaded images of applications are removed from memory. + +An UEFI application (e.g. an operating system) that wants to take full control +of the system calls ExitBootServices. After a UEFI application calls +ExitBootServices + +* boot services are not available anymore +* timer events are stopped +* the memory used by U-Boot except for runtime services is released +* the memory used by boot time drivers is released + +So this is a point of no return. Afterwards the UEFI application can only return +to U-Boot by rebooting. + +## The UEFI object model + +UEFI offers a flexible and expandable object model. The objects in the UEFI API +are devices, drivers, and loaded images. These objects are referenced by +handles. + +The interfaces implemented by the objects are referred to as protocols. These +are identified by GUIDs. They can be installed and uninstalled by calling the +appropriate boot services. + +Handles are created by the InstallProtocolInterface or the +InstallMultipleProtocolinterfaces service if NULL is passed as handle. + +Handles are deleted when the last protocol has been removed with the +UninstallProtocolInterface or the UninstallMultipleProtocolInterfaces service. + +Devices offer the EFI_DEVICE_PATH_PROTOCOL. A device path is the concatenation +of device nodes. By their device paths all devices of a system are arranged in a +tree. + +Drivers offer the EFI_DRIVER_BINDING_PROTOCOL. This protocol is used to connect +a driver to devices (which are referenced as controllers in this context). + +Loaded images offer the EFI_LOADED_IMAGE_PROTOCOL. This protocol provides meta +information about the image and a pointer to the unload callback function. + +## The UEFI events + +In the UEFI terminology an event is a data object referencing a notification +function which is queued for calling when the event is signaled. The following +types of events exist: + +* periodic and single shot timer events +* exit boot services events, triggered by calling the ExitBootServices() service +* virtual address change events +* memory map change events +* read to boot events +* reset system events +* system table events +* events that are only triggered programmatically + +Events can be created with the CreateEvent service and deleted with CloseEvent +service. + +Events can be assigned to an event group. If any of the events in a group is +signaled, all other events in the group are also set to the signaled state. + +## The UEFI driver model + +A driver is specific for a single protocol installed on a device. To install a +driver on a device the ConnectController service is called. In this context +controller refers to the device for which the driver is installed. + +The relevant drivers are identified using the EFI_DRIVER_BINDING_PROTOCOL. This +protocol has has three functions: + +* supported - determines if the driver is compatible with the device +* start - installs the driver by opening the relevant protocol with + attribute EFI_OPEN_PROTOCOL_BY_DRIVER +* stop - uninstalls the driver + +The driver may create child controllers (child devices). E.g. a driver for block +IO devices will create the device handles for the partitions. The child +controllers will open the supported protocol with the attribute +EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER. + +A driver can be detached from a device using the DisconnectController service. + +## U-Boot devices mapped as UEFI devices + +Some of the U-Boot devices are mapped as UEFI devices + +* block IO devices +* console +* graphical output +* network adapter + +As of U-Boot 2018.03 the logic for doing this is hard coded. + +The development target is to integrate the setup of these UEFI devices with the +U-Boot driver model. So when a U-Boot device is discovered a handle should be +created and the device path protocol and the relevant IO protocol should be +installed. The UEFI driver then would be attached by calling ConnectController. +When a U-Boot device is removed DisconnectController should be called. + +## UEFI devices mapped as U-Boot devices + +UEFI drivers binaries and applications may create new (virtual) devices, install +a protocol and call the ConnectController service. Now the matching UEFI driver +is determined by iterating over the implementations of the +EFI_DRIVER_BINDING_PROTOCOL. + +It is the task of the UEFI driver to create a corresponding U-Boot device and to +proxy calls for this U-Boot device to the controller. + +In U-Boot 2018.03 this has only been implemented for block IO devices. + +### UEFI uclass + +An UEFI uclass driver (lib/efi_driver/efi_uclass.c) has been created that +takes care of initializing the UEFI drivers and providing the +EFI_DRIVER_BINDING_PROTOCOL implementation for the UEFI drivers. + +A linker created list is used to keep track of the UEFI drivers. To create an +entry in the list the UEFI driver uses the U_BOOT_DRIVER macro specifying +UCLASS_EFI as the ID of its uclass, e.g. + + /* Identify as UEFI driver */ + U_BOOT_DRIVER(efi_block) = { + .name = "EFI block driver", + .id = UCLASS_EFI, + .ops = &driver_ops, + }; + +The available operations are defined via the structure struct efi_driver_ops. + + struct efi_driver_ops { + const efi_guid_t *protocol; + const efi_guid_t *child_protocol; + int (*bind)(efi_handle_t handle, void *interface); + }; + +When the supported() function of the EFI_DRIVER_BINDING_PROTOCOL is called the +uclass checks if the protocol GUID matches the protocol GUID of the UEFI driver. +In the start() function the bind() function of the UEFI driver is called after +checking the GUID. +The stop() function of the EFI_DRIVER_BINDING_PROTOCOL disconnects the child +controllers created by the UEFI driver and the UEFI driver. (In U-Boot v2013.03 +this is not yet completely implemented.) + +### UEFI block IO driver + +The UEFI block IO driver supports devices exposing the EFI_BLOCK_IO_PROTOCOL. + +When connected it creates a new U-Boot block IO device with interface type +IF_TYPE_EFI, adds child controllers mapping the partitions, and installs the +EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the +software iPXE to boot from iSCSI network drives [3]. + +This driver is only available if U-Boot is configured with + + CONFIG_BLK=y + CONFIG_PARTITIONS=y + +## TODOs as of U-Boot 2018.03 + +* unimplemented or incompletely implemented boot services + * Exit - call unload function, unload applications only + * ReinstallProtocolInterface + * UnloadImage + +* unimplemented events + * EVT_RUNTIME + * EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE + * event groups + +* data model + * manage events in a linked list + * manage configuration tables in a linked list + +* UEFI drivers + * support DisconnectController for UEFI block devices. + +* support for CONFIG_EFI_LOADER in the sandbox (CONFIG_SANDBOX=y) + +* UEFI variables + * persistence + * runtime support + +* support bootefi booting ARMv7 in non-secure mode (CONFIG_ARMV7_NONSEC=y) + +## Links + +* [1](http://uefi.org/specifications) + http://uefi.org/specifications - UEFI specifications +* [2](./driver-model/README.txt) doc/driver-model/README.txt - Driver model +* [3](./README.iscsi) doc/README.iscsi - iSCSI booting with U-Boot and iPXE diff --git a/doc/README.vxworks b/doc/README.vxworks index 3433e4f3ae..3239c5bb11 100644 --- a/doc/README.vxworks +++ b/doc/README.vxworks @@ -17,9 +17,7 @@ For booting old kernels (6.9.x) on PowerPC and ARM, and all kernel versions on other architectures, 'bootvx' shall be used. For booting VxWorks 7 kernels on PowerPC and ARM, 'bootm' shall be used. -64-bit x86 kernel cannot be loaded as of today. - -VxWork 7 on PowerPC and ARM +VxWorks 7 on PowerPC and ARM --------------------------- From VxWorks 7, VxWorks starts adopting device tree as its hardware decription mechansim (for PowerPC and ARM), thus requiring boot interface changes. @@ -30,11 +28,11 @@ the ePAPR standard, which is shown below (see ePAPR for more details): void (*kernel_entry)(fdt_addr, 0, 0, EPAPR_MAGIC, boot_IMA, 0, 0) -For ARM, the calling convention is show below: +For ARM, the calling convention is shown below: void (*kernel_entry)(void *fdt_addr) -When booting new VxWorks kernel (uImage format), the parameters passed to bootm +When booting a VxWorks 7 kernel (uImage format), the parameters passed to bootm is like below: bootm <kernel image address> - <device tree address> @@ -46,7 +44,7 @@ board-specific address before loading VxWorks. U-Boot supplies its address via "bootaddr" environment variable. To check where the bootline should be for a specific board, go to the VxWorks BSP for that board, and look for a parameter called BOOT_LINE_ADRS. Assign its value to "bootaddr". A typical -value for "bootaddr" is 0x101200. +value for "bootaddr" on an x86 board is 0x101200. If a "bootargs" variable is defined, its content will be copied to the memory location pointed by "bootaddr" as the kernel bootline. If "bootargs" is not @@ -67,19 +65,34 @@ look like VxWorks hangs somewhere as nothing outputs on the serial console. x86-specific information ------------------------ -Before loading an x86 kernel, two additional environment variables need to be -provided. They are "e820data" and "e820info", which represent the address of -E820 table and E820 information (defined by VxWorks) in system memory. - -Check VxWorks kernel configuration to look for BIOS_E820_DATA_START and -BIOS_E820_INFO_START, and assign their values to "e820data" and "e820info" -accordingly. If neither of these two are supplied, U-Boot assumes a default -location at 0x4000 for "e820data" and 0x4a00 for "e820info". Typical values -for "e820data" and "e820info" are 0x104000 and 0x104a00. But there is one -exception on Intel Galileo, where "e820data" and "e820info" should be left -unset, which assume the default location for VxWorks. - -Note since currently U-Boot does not support ACPI yet, VxWorks kernel must +Before loading an x86 kernel, one additional environment variable need to be +provided. This is "vx_phys_mem_base", which represent the physical memory +base address of VxWorks. + +Check VxWorks kernel configuration to look for LOCAL_MEM_LOCAL_ADRS. For +VxWorks 7, this is normally a virtual address and you need find out its +corresponding physical address and assign its value to "vx_phys_mem_base". + +For boards on which ACPI is not supported by U-Boot yet, VxWorks kernel must be configured to use MP table and virtual wire interrupt mode. This requires INCLUDE_MPTABLE_BOOT_OP and INCLUDE_VIRTUAL_WIRE_MODE to be included in a VxWorks kernel configuration. + +Both 32-bit x86 and 64-bit x64 kernels can be loaded. + +There are two types of graphics console drivers in VxWorks. One is the 80x25 +VGA text mode driver. The other one is the EFI console bitmapped graphics mode +driver. To make these drivers function, U-Boot needs to load and run the VGA +BIOS of the graphics card first. + + - If the kernel is configured with 80x25 VGA text mode driver, + CONFIG_FRAMEBUFFER_SET_VESA_MODE must be unset in U-Boot. + - If the kernel is configured with bitmapped graphics mode driver, + CONFIG_FRAMEBUFFER_SET_VESA_MODE need remain set but care must be taken + at which VESA mode is to be set. The supported pixel format is 32-bit + RGBA, hence the available VESA mode can only be one of the following: + * FRAMEBUFFER_VESA_MODE_10F + * FRAMEBUFFER_VESA_MODE_112 + * FRAMEBUFFER_VESA_MODE_115 + * FRAMEBUFFER_VESA_MODE_118 + * FRAMEBUFFER_VESA_MODE_11B diff --git a/doc/README.x86 b/doc/README.x86 index 772e8d2a86..b1663a4111 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -46,7 +46,7 @@ Build Instructions for U-Boot as coreboot payload Building U-Boot as a coreboot payload is just like building U-Boot for targets on other architectures, like below: -$ make coreboot-x86_defconfig +$ make coreboot_defconfig $ make all Note this default configuration will build a U-Boot payload for the QEMU board. diff --git a/doc/device-tree-bindings/i2c/i2c.txt b/doc/device-tree-bindings/i2c/i2c.txt index ea918dd61d..de818d4713 100644 --- a/doc/device-tree-bindings/i2c/i2c.txt +++ b/doc/device-tree-bindings/i2c/i2c.txt @@ -12,6 +12,11 @@ property which allows the chip offset length to be selected. Optional properties: - u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the default value of 1 is used. +- gpios = <sda ...>, <scl ...>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c_xfer>; + pinctrl-1 = <&i2c_gpio>; + Pin description for I2C bus software deblocking. Example @@ -26,3 +31,11 @@ i2c4: i2c@12ca0000 { ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; }; }; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_xfer>; + pinctrl-1 = <&i2c1_gpio>; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>, /* SDA */ + <&gpio1 27 GPIO_ACTIVE_LOW>; /* SCL */ +}; diff --git a/doc/git-mailrc b/doc/git-mailrc index 5a365cddd9..e55a1cb1d9 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -15,6 +15,7 @@ alias abiessmann Andreas Bießmann <andreas@biessmann.org> alias abrodkin Alexey Brodkin <alexey.brodkin@synopsys.com> alias afleming Andy Fleming <afleming@gmail.com> alias ag Anatolij Gustschin <agust@denx.de> +alias agraf Alexander Graf <agraf@suse.de> alias alisonwang Alison Wang <alison.wang@freescale.com> alias angelo_ts Angelo Dureghello <angelo@sysam.it> alias bmeng Bin Meng <bmeng.cn@gmail.com> @@ -31,7 +32,7 @@ alias jhersh Joe Hershberger <joe.hershberger@ni.com> alias jwrdegoede Hans de Goede <hdegoede@redhat.com> alias kimphill Kim Phillips <kim.phillips@freescale.com> alias luka Luka Perkov <luka.perkov@sartura.hr> -alias lukma Lukasz Majewski <l.majewski@denx.de> +alias lukma Lukasz Majewski <lukma@denx.de> alias macpaul Macpaul Lin <macpaul@andestech.com> alias marex Marek Vasut <marex@denx.de> alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com> @@ -120,6 +121,7 @@ alias x86 uboot, sjg, bmeng alias dm uboot, sjg alias cfi uboot, stroese alias dfu uboot, lukma +alias efi uboot, agraf alias eth uboot, jhersh alias kerneldoc uboot, marex alias fdt uboot, sjg diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c index 029b7784f6..6c7371e3ed 100644 --- a/drivers/ata/dwc_ahci.c +++ b/drivers/ata/dwc_ahci.c @@ -25,17 +25,18 @@ struct dwc_ahci_priv { void *wrapper_base; }; +static int dwc_ahci_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + + return ahci_bind_scsi(dev, &scsi_dev); +} + static int dwc_ahci_ofdata_to_platdata(struct udevice *dev) { struct dwc_ahci_priv *priv = dev_get_priv(dev); - struct scsi_platdata *plat = dev_get_uclass_platdata(dev); fdt_addr_t addr; - plat->max_id = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), - "max-id", CONFIG_SYS_SCSI_MAX_SCSI_ID); - plat->max_lun = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), - "max-lun", CONFIG_SYS_SCSI_MAX_LUN); - priv->base = map_physmem(devfdt_get_addr(dev), sizeof(void *), MAP_NOCACHE); @@ -81,11 +82,7 @@ static int dwc_ahci_probe(struct udevice *dev) writel(val, priv->wrapper_base + TI_SATA_SYSCONFIG); } - ret = ahci_init_dm(dev, priv->base); - if (ret) - return ret; - - return ahci_start_ports_dm(dev); + return ahci_probe_scsi(dev, (ulong)priv->base); } static const struct udevice_id dwc_ahci_ids[] = { @@ -95,11 +92,11 @@ static const struct udevice_id dwc_ahci_ids[] = { U_BOOT_DRIVER(dwc_ahci) = { .name = "dwc_ahci", - .id = UCLASS_SCSI, + .id = UCLASS_AHCI, .of_match = dwc_ahci_ids, + .bind = dwc_ahci_bind, .ofdata_to_platdata = dwc_ahci_ofdata_to_platdata, .ops = &scsi_ops, .probe = dwc_ahci_probe, .priv_auto_alloc_size = sizeof(struct dwc_ahci_priv), - .flags = DM_FLAG_ALLOC_PRIV_DMA, }; diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 2d5b5dc562..4a16fc7e1c 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -65,6 +65,7 @@ static u32 saveBaseAddress20; /* Addres im memory of VBE region */ const int vbe_offset = 0x2000; +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE static const void *bios_ptr(const void *buf, BE_VGAInfo *vga_info, u32 x86_dword_ptr) { @@ -215,6 +216,7 @@ static int atibios_set_vesa_mode(RMREGS *regs, int vesa_mode, return 0; } +#endif /* CONFIG_FRAMEBUFFER_SET_VESA_MODE */ /**************************************************************************** PARAMETERS: @@ -263,11 +265,13 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info, /*Cleanup and exit*/ BE_getVGA(vga_info); +#ifdef CONFIG_FRAMEBUFFER_SET_VESA_MODE /* Useful for debugging */ if (0) atibios_debug_mode(vga_info, ®s, vesa_mode, mode_info); if (vesa_mode != -1) atibios_set_vesa_mode(®s, vesa_mode, mode_info); +#endif } /**************************************************************************** diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ad763795d9..53f418bfdd 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -104,6 +104,39 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) return clk_get_by_indexed_prop(dev, "clocks", index, clk); } +int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) +{ + int i, ret, err, count; + + bulk->count = 0; + + count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); + if (count < 1) + return count; + + bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL); + if (!bulk->clks) + return -ENOMEM; + + for (i = 0; i < count; i++) { + ret = clk_get_by_index(dev, i, &bulk->clks[i]); + if (ret < 0) + goto bulk_get_err; + + ++bulk->count; + } + + return 0; + +bulk_get_err: + err = clk_release_all(bulk->clks, bulk->count); + if (err) + debug("%s: could release all clocks for %p\n", + __func__, dev); + + return ret; +} + static int clk_set_default_parents(struct udevice *dev) { struct clk clk, parent_clk; @@ -336,6 +369,19 @@ int clk_enable(struct clk *clk) return ops->enable(clk); } +int clk_enable_bulk(struct clk_bulk *bulk) +{ + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = clk_enable(&bulk->clks[i]); + if (ret < 0 && ret != -ENOSYS) + return ret; + } + + return 0; +} + int clk_disable(struct clk *clk) { const struct clk_ops *ops = clk_dev_ops(clk->dev); @@ -348,6 +394,19 @@ int clk_disable(struct clk *clk) return ops->disable(clk); } +int clk_disable_bulk(struct clk_bulk *bulk) +{ + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = clk_disable(&bulk->clks[i]); + if (ret < 0 && ret != -ENOSYS) + return ret; + } + + return 0; +} + UCLASS_DRIVER(clk) = { .id = UCLASS_CLK, .name = "clk", diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c index 999100de9d..d0898815b3 100644 --- a/drivers/clk/clk_sandbox_test.c +++ b/drivers/clk/clk_sandbox_test.c @@ -11,6 +11,7 @@ struct sandbox_clk_test { struct clk clks[SANDBOX_CLK_TEST_ID_COUNT]; + struct clk_bulk bulk; }; static const char * const sandbox_clk_test_names[] = { @@ -34,6 +35,13 @@ int sandbox_clk_test_get(struct udevice *dev) return 0; } +int sandbox_clk_test_get_bulk(struct udevice *dev) +{ + struct sandbox_clk_test *sbct = dev_get_priv(dev); + + return clk_get_bulk(dev, &sbct->bulk); +} + ulong sandbox_clk_test_get_rate(struct udevice *dev, int id) { struct sandbox_clk_test *sbct = dev_get_priv(dev); @@ -64,6 +72,13 @@ int sandbox_clk_test_enable(struct udevice *dev, int id) return clk_enable(&sbct->clks[id]); } +int sandbox_clk_test_enable_bulk(struct udevice *dev) +{ + struct sandbox_clk_test *sbct = dev_get_priv(dev); + + return clk_enable_bulk(&sbct->bulk); +} + int sandbox_clk_test_disable(struct udevice *dev, int id) { struct sandbox_clk_test *sbct = dev_get_priv(dev); @@ -74,6 +89,13 @@ int sandbox_clk_test_disable(struct udevice *dev, int id) return clk_disable(&sbct->clks[id]); } +int sandbox_clk_test_disable_bulk(struct udevice *dev) +{ + struct sandbox_clk_test *sbct = dev_get_priv(dev); + + return clk_disable_bulk(&sbct->bulk); +} + int sandbox_clk_test_free(struct udevice *dev) { struct sandbox_clk_test *sbct = dev_get_priv(dev); @@ -88,6 +110,13 @@ int sandbox_clk_test_free(struct udevice *dev) return 0; } +int sandbox_clk_test_release_bulk(struct udevice *dev) +{ + struct sandbox_clk_test *sbct = dev_get_priv(dev); + + return clk_release_bulk(&sbct->bulk); +} + static const struct udevice_id sandbox_clk_test_ids[] = { { .compatible = "sandbox,clk-test" }, { } diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 4ef8662af5..d0d6c898bc 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -702,6 +702,7 @@ static struct clk_ops zynqmp_clk_ops = { }; static const struct udevice_id zynqmp_clk_ids[] = { + { .compatible = "xlnx,zynqmp-clk" }, { .compatible = "xlnx,zynqmp-clkc" }, { } }; diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c index 33ab9ad7cc..360c02c5fd 100644 --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c @@ -40,7 +40,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7790_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7790_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), @@ -90,7 +90,7 @@ static const struct cpg_core_clk r8a7790_core_clks[] __initconst = { DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c), }; -static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7790_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7790_CLK_MP), DEF_MOD("vcp1", 100, R8A7790_CLK_ZS), DEF_MOD("vcp0", 101, R8A7790_CLK_ZS), @@ -209,10 +209,6 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = { DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; -static const unsigned int r8a7790_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -235,7 +231,7 @@ static const unsigned int r8a7790_crit_mod_clks[] __initconst = { #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 }, { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 }, }; diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index 260bb892d6..4ba18b18be 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -39,7 +39,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7792_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -78,7 +78,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1), }; -static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7792_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7792_CLK_MP), DEF_MOD("jpu", 106, R8A7792_CLK_M2), DEF_MOD("tmu1", 111, R8A7792_CLK_P), @@ -152,10 +152,6 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), }; -static const unsigned int r8a7792_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -179,7 +175,7 @@ static const unsigned int r8a7792_crit_mod_clks[] __initconst = { #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { { 1, 208, 106, 200 }, { 1, 208, 88, 200 }, { 1, 156, 80, 150 }, diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c index 90bac3deed..e8f57c3d01 100644 --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c @@ -40,7 +40,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7794_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), @@ -85,7 +85,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240), }; -static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7794_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7794_CLK_MP), DEF_MOD("vcp0", 101, R8A7794_CLK_ZS), DEF_MOD("vpc0", 103, R8A7794_CLK_ZS), @@ -188,10 +188,6 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { DEF_MOD("scifa5", 1108, R8A7794_CLK_MP), }; -static const unsigned int r8a7794_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -210,7 +206,7 @@ static const unsigned int r8a7794_crit_mod_clks[] __initconst = { */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = { { 1, 208, 88, 200 }, { 1, 156, 66, 150 }, { 2, 240, 102, 230 }, diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig index 3666d8414c..a26ca8c1cd 100644 --- a/drivers/clk/uniphier/Kconfig +++ b/drivers/clk/uniphier/Kconfig @@ -2,7 +2,6 @@ config CLK_UNIPHIER def_bool y depends on ARCH_UNIPHIER select CLK - select SPL_CLK if SPL help Support for clock controllers on UniPhier SoCs. Say Y if you want to control clocks provided by System Control diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index c852c78659..0230a18608 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -21,7 +21,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) UNIPHIER_LD4_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ + UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ + UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ @@ -34,6 +37,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ @@ -45,6 +49,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ + UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */ diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 57a4e6c88e..43e8b2520e 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -11,6 +11,7 @@ #include <zynqmppl.h> #include <linux/sizes.h> #include <asm/arch/sys_proto.h> +#include <memalign.h> #define DUMMY_WORD 0xffffffff @@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { + ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); u32 swap; ulong bin_buf; int ret; @@ -205,25 +207,37 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL; bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap); + bsizeptr = (u32 *)&bsize; debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); - - if (bsize % 4) - bsize = bsize / 4 + 1; - else - bsize = bsize / 4; + flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t)); buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, - bstype, ret_payload); + bstype |= BIT(ZYNQMP_FPGA_BIT_NS); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + (u32)(uintptr_t)bsizeptr, bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n"); return ret; } +static int zynqmp_pcap_info(xilinx_desc *desc) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, + 0, ret_payload); + if (!ret) + printf("PCAP status\t0x%x\n", ret_payload[1]); + + return ret; +} + struct xilinx_fpga_op zynqmp_op = { .load = zynqmp_load, + .info = zynqmp_pcap_info, }; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 2ff716c252..db9bd12992 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -17,6 +17,7 @@ #include <asm/arch/sys_proto.h> #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 +#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 @@ -205,9 +206,24 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Setting PCFG_PROG_B signal to high */ control = readl(&devcfg_base->ctrl); writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Setting PCFG_PROG_B signal to low */ writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + /* + * Delay is required if AES efuse is selected as + * key source. + */ + if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) + mdelay(5); + /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 3299ef0fea..7fb201d8e6 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -149,13 +149,176 @@ config SYS_I2C_MESON both 7-bit and 10-bit addresses. config SYS_I2C_MXC - bool "NXP i.MX I2C driver" - depends on MX6 + bool "NXP MXC I2C driver" help - Add support for the NXP i.MX I2C driver. This supports upto for bus + Add support for the NXP I2C driver. This supports upto for bus channels and operating on standard mode upto 100 kbits/s and fast mode upto 400 kbits/s. +if SYS_I2C_MXC +config SYS_I2C_MXC_I2C1 + bool "NXP MXC I2C1" + help + Add support for NXP MXC I2C Controller 1. + Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C2 + bool "NXP MXC I2C2" + help + Add support for NXP MXC I2C Controller 2. + Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C3 + bool "NXP MXC I2C3" + help + Add support for NXP MXC I2C Controller 3. + Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C4 + bool "NXP MXC I2C4" + help + Add support for NXP MXC I2C Controller 4. + Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A + +config SYS_I2C_MXC_I2C5 + bool "NXP MXC I2C5" + help + Add support for NXP MXC I2C Controller 5. + Required for SoCs which have I2C MXC controller 5 eg LX2160A + +config SYS_I2C_MXC_I2C6 + bool "NXP MXC I2C6" + help + Add support for NXP MXC I2C Controller 6. + Required for SoCs which have I2C MXC controller 6 eg LX2160A + +config SYS_I2C_MXC_I2C7 + bool "NXP MXC I2C7" + help + Add support for NXP MXC I2C Controller 7. + Required for SoCs which have I2C MXC controller 7 eg LX2160A + +config SYS_I2C_MXC_I2C8 + bool "NXP MXC I2C8" + help + Add support for NXP MXC I2C Controller 8. + Required for SoCs which have I2C MXC controller 8 eg LX2160A +endif + +if SYS_I2C_MXC_I2C1 +config SYS_MXC_I2C1_SPEED + int "I2C Channel 1 speed" + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 100000 + help + MXC I2C Channel 1 speed + +config SYS_MXC_I2C1_SLAVE + int "I2C1 Slave" + default 0 + help + MXC I2C1 Slave +endif + +if SYS_I2C_MXC_I2C2 +config SYS_MXC_I2C2_SPEED + int "I2C Channel 2 speed" + default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU + default 100000 + help + MXC I2C Channel 2 speed + +config SYS_MXC_I2C2_SLAVE + int "I2C2 Slave" + default 0 + help + MXC I2C2 Slave +endif + +if SYS_I2C_MXC_I2C3 +config SYS_MXC_I2C3_SPEED + int "I2C Channel 3 speed" + default 100000 + help + MXC I2C Channel 3 speed + +config SYS_MXC_I2C3_SLAVE + int "I2C3 Slave" + default 0 + help + MXC I2C3 Slave +endif + +if SYS_I2C_MXC_I2C4 +config SYS_MXC_I2C4_SPEED + int "I2C Channel 4 speed" + default 100000 + help + MXC I2C Channel 4 speed + +config SYS_MXC_I2C4_SLAVE + int "I2C4 Slave" + default 0 + help + MXC I2C4 Slave +endif + +if SYS_I2C_MXC_I2C5 +config SYS_MXC_I2C5_SPEED + int "I2C Channel 5 speed" + default 100000 + help + MXC I2C Channel 5 speed + +config SYS_MXC_I2C5_SLAVE + int "I2C5 Slave" + default 0 + help + MXC I2C5 Slave +endif + +if SYS_I2C_MXC_I2C6 +config SYS_MXC_I2C6_SPEED + int "I2C Channel 6 speed" + default 100000 + help + MXC I2C Channel 6 speed + +config SYS_MXC_I2C6_SLAVE + int "I2C6 Slave" + default 0 + help + MXC I2C6 Slave +endif + +if SYS_I2C_MXC_I2C7 +config SYS_MXC_I2C7_SPEED + int "I2C Channel 7 speed" + default 100000 + help + MXC I2C Channel 7 speed + +config SYS_MXC_I2C7_SLAVE + int "I2C7 Slave" + default 0 + help + MXC I2C7 Slave +endif + +if SYS_I2C_MXC_I2C8 +config SYS_MXC_I2C8_SPEED + int "I2C Channel 8 speed" + default 100000 + help + MXC I2C Channel 8 speed + +config SYS_MXC_I2C8_SLAVE + int "I2C8 Slave" + default 0 + help + MXC I2C8 Slave +endif + config SYS_I2C_OMAP24XX bool "TI OMAP2+ I2C driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 8cfed2194c..419d021a31 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -9,6 +9,7 @@ #include <dm.h> #include <i2c.h> #include <pci.h> +#include <reset.h> #include <asm/io.h> #include "designware_i2c.h" @@ -34,6 +35,7 @@ static struct dw_scl_sda_cfg byt_config = { struct dw_i2c { struct i2c_regs *regs; struct dw_scl_sda_cfg *scl_sda_cfg; + struct reset_ctl reset_ctl; }; #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED @@ -534,6 +536,7 @@ static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, static int designware_i2c_probe(struct udevice *bus) { struct dw_i2c *priv = dev_get_priv(bus); + int ret; if (device_is_on_pci_bus(bus)) { #ifdef CONFIG_DM_PCI @@ -549,6 +552,13 @@ static int designware_i2c_probe(struct udevice *bus) priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus); } + ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl); + if (ret) + pr_info("reset_get_by_name() failed: %d\n", ret); + + if (&priv->reset_ctl) + reset_deassert(&priv->reset_ctl); + __dw_i2c_init(priv->regs, 0, 0); return 0; diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index cb0f5ea233..450a91ded6 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -12,6 +12,7 @@ #include <i2c.h> /* Functional interface */ #include <asm/io.h> #include <asm/fsl_i2c.h> /* HW definitions */ +#include <clk.h> #include <dm.h> #include <mapmem.h> @@ -573,11 +574,9 @@ static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed) static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) { struct fsl_i2c_dev *dev = dev_get_priv(bus); - fdt_addr_t addr; + struct clk clock; - addr = dev_read_u32_default(bus, "reg", -1); - - dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, sizeof(struct fsl_i2c_base)); + dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct fsl_i2c_base)); if (!dev->base) return -ENOMEM; @@ -587,7 +586,11 @@ static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) 0x7f); dev->speed = dev_read_u32_default(bus, "clock-frequency", 400000); - dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk; + if (!clk_get_by_index(bus, 0, &clock)) + dev->i2c_clk = clk_get_rate(&clock); + else + dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : + gd->arch.i2c1_clk; return 0; } diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 920811a075..4ac6ef84f5 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -11,9 +11,19 @@ #include <malloc.h> #include <dm/device-internal.h> #include <dm/lists.h> +#include <dm/pinctrl.h> +#ifdef CONFIG_DM_GPIO +#include <asm/gpio.h> +#endif #define I2C_MAX_OFFSET_LEN 4 +enum { + PIN_SDA = 0, + PIN_SCL, + PIN_COUNT, +}; + /* Useful debugging function */ void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs) { @@ -445,20 +455,110 @@ int i2c_get_chip_offset_len(struct udevice *dev) return chip->offset_len; } +#ifdef CONFIG_DM_GPIO +static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit) +{ + if (bit) + dm_gpio_set_dir_flags(pin, GPIOD_IS_IN); + else + dm_gpio_set_dir_flags(pin, GPIOD_IS_OUT | + GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); +} + +static int i2c_gpio_get_pin(struct gpio_desc *pin) +{ + return dm_gpio_get_value(pin); +} + +static int i2c_deblock_gpio_loop(struct gpio_desc *sda_pin, + struct gpio_desc *scl_pin) +{ + int counter = 9; + int ret = 0; + + i2c_gpio_set_pin(sda_pin, 1); + i2c_gpio_set_pin(scl_pin, 1); + udelay(5); + + /* Toggle SCL until slave release SDA */ + while (counter-- >= 0) { + i2c_gpio_set_pin(scl_pin, 1); + udelay(5); + i2c_gpio_set_pin(scl_pin, 0); + udelay(5); + if (i2c_gpio_get_pin(sda_pin)) + break; + } + + /* Then, send I2C stop */ + i2c_gpio_set_pin(sda_pin, 0); + udelay(5); + + i2c_gpio_set_pin(scl_pin, 1); + udelay(5); + + i2c_gpio_set_pin(sda_pin, 1); + udelay(5); + + if (!i2c_gpio_get_pin(sda_pin) || !i2c_gpio_get_pin(scl_pin)) + ret = -EREMOTEIO; + + return ret; +} + +static int i2c_deblock_gpio(struct udevice *bus) +{ + struct gpio_desc gpios[PIN_COUNT]; + int ret, ret0; + + ret = gpio_request_list_by_name(bus, "gpios", gpios, + ARRAY_SIZE(gpios), GPIOD_IS_IN); + if (ret != ARRAY_SIZE(gpios)) { + debug("%s: I2C Node '%s' has no 'gpios' property %s\n", + __func__, dev_read_name(bus), bus->name); + if (ret >= 0) { + gpio_free_list(bus, gpios, ret); + ret = -ENOENT; + } + goto out; + } + + ret = pinctrl_select_state(bus, "gpio"); + if (ret) { + debug("%s: I2C Node '%s' has no 'gpio' pinctrl state. %s\n", + __func__, dev_read_name(bus), bus->name); + goto out_no_pinctrl; + } + + ret0 = i2c_deblock_gpio_loop(&gpios[PIN_SDA], &gpios[PIN_SCL]); + + ret = pinctrl_select_state(bus, "default"); + if (ret) { + debug("%s: I2C Node '%s' has no 'default' pinctrl state. %s\n", + __func__, dev_read_name(bus), bus->name); + } + + ret = !ret ? ret0 : ret; + +out_no_pinctrl: + gpio_free_list(bus, gpios, ARRAY_SIZE(gpios)); +out: + return ret; +} +#else +static int i2c_deblock_gpio(struct udevice *bus) +{ + return -ENOSYS; +} +#endif // CONFIG_DM_GPIO + int i2c_deblock(struct udevice *bus) { struct dm_i2c_ops *ops = i2c_get_ops(bus); - /* - * We could implement a software deblocking here if we could get - * access to the GPIOs used by I2C, and switch them to GPIO mode - * and then back to I2C. This is somewhat beyond our powers in - * driver model at present, so for now just fail. - * - * See https://patchwork.ozlabs.org/patch/399040/ - */ if (!ops->deblock) - return -ENOSYS; + return i2c_deblock_gpio(bus); return ops->deblock(bus); } diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 9298521220..82abb439f0 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -99,7 +99,8 @@ static int wait_for_int(bool read) #endif #ifdef CONFIG_DM_I2C - fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val); + fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, + FPGAMAP_SIZE_16); #else I2C_GET_REG(interrupt_status, &val); #endif @@ -110,7 +111,8 @@ static int wait_for_int(bool read) if (ctr++ > 5000) return 1; #ifdef CONFIG_DM_I2C - fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val); + fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, + FPGAMAP_SIZE_16); #else I2C_GET_REG(interrupt_status, &val); #endif @@ -128,6 +130,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, #endif { u16 val; + u16 data; #ifdef CONFIG_DM_I2C struct ihs_i2c_priv *priv = dev_get_priv(dev); struct udevice *fpga; @@ -136,13 +139,14 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, #endif /* Clear interrupt status */ + data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV; #ifdef CONFIG_DM_I2C - fpgamap_write16(fpga, priv->addr + REG_INTERRUPT_STATUS, - I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); - fpgamap_read16(fpga, priv->addr + REG_INTERRUPT_STATUS, &val); + fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data, + FPGAMAP_SIZE_16); + fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, + FPGAMAP_SIZE_16); #else - I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV - | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV); + I2C_SET_REG(interrupt_status, data); I2C_GET_REG(interrupt_status, &val); #endif @@ -153,26 +157,24 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, if (len > 1) val |= buffer[1] << 8; #ifdef CONFIG_DM_I2C - fpgamap_write16(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, val); + fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val, + FPGAMAP_SIZE_16); #else I2C_SET_REG(write_mailbox_ext, val); #endif } + data = I2CMB_NATIVE + | (read ? 0 : I2CMB_WRITE) + | (chip << 1) + | ((len > 1) ? I2CMB_2BYTE : 0) + | (is_last ? 0 : I2CMB_HOLD_BUS); + #ifdef CONFIG_DM_I2C - fpgamap_write16(fpga, priv->addr + REG_WRITE_MAILBOX, - I2CMB_NATIVE - | (read ? I2CMB_READ : I2CMB_WRITE) - | (chip << 1) - | ((len > 1) ? I2CMB_2BYTE : I2CMB_1BYTE) - | (!is_last ? I2CMB_HOLD_BUS : I2CMB_DONT_HOLD_BUS)); + fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data, + FPGAMAP_SIZE_16); #else - I2C_SET_REG(write_mailbox, - I2CMB_NATIVE - | (read ? 0 : I2CMB_WRITE) - | (chip << 1) - | ((len > 1) ? I2CMB_2BYTE : 0) - | (is_last ? 0 : I2CMB_HOLD_BUS)); + I2C_SET_REG(write_mailbox, data); #endif #ifdef CONFIG_DM_I2C @@ -185,7 +187,8 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, /* If we want to read, get the bytes from the mailbox */ if (read) { #ifdef CONFIG_DM_I2C - fpgamap_read16(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val); + fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val, + FPGAMAP_SIZE_16); #else I2C_GET_REG(read_mailbox_ext, &val); #endif diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 79228c2757..a17c1eceae 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -589,6 +589,22 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, #define I2C4_BASE_ADDR 0 #endif +#if !defined(I2C5_BASE_ADDR) +#define I2C5_BASE_ADDR 0 +#endif + +#if !defined(I2C6_BASE_ADDR) +#define I2C6_BASE_ADDR 0 +#endif + +#if !defined(I2C7_BASE_ADDR) +#define I2C7_BASE_ADDR 0 +#endif + +#if !defined(I2C8_BASE_ADDR) +#define I2C8_BASE_ADDR 0 +#endif + static struct mxc_i2c_bus mxc_i2c_buses[] = { #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \ defined(CONFIG_FSL_LAYERSCAPE) @@ -596,11 +612,19 @@ static struct mxc_i2c_bus mxc_i2c_buses[] = { { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, + { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG }, + { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG }, + { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG }, + { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG }, #else { 0, I2C1_BASE_ADDR, 0 }, { 1, I2C2_BASE_ADDR, 0 }, { 2, I2C3_BASE_ADDR, 0 }, { 3, I2C4_BASE_ADDR, 0 }, + { 4, I2C5_BASE_ADDR, 0 }, + { 5, I2C6_BASE_ADDR, 0 }, + { 6, I2C7_BASE_ADDR, 0 }, + { 7, I2C8_BASE_ADDR, 0 }, #endif }; @@ -738,6 +762,38 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, CONFIG_SYS_MXC_I2C4_SLAVE, 3) #endif +#ifdef CONFIG_SYS_I2C_MXC_I2C5 +U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C5_SPEED, + CONFIG_SYS_MXC_I2C5_SLAVE, 4) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C6 +U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C6_SPEED, + CONFIG_SYS_MXC_I2C6_SLAVE, 5) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C7 +U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C7_SPEED, + CONFIG_SYS_MXC_I2C7_SLAVE, 6) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C8 +U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe, + mxc_i2c_read, mxc_i2c_write, + mxc_i2c_set_bus_speed, + CONFIG_SYS_MXC_I2C8_SPEED, + CONFIG_SYS_MXC_I2C8_SLAVE, 7) +#endif + #else static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index ff4a8f5b97..4fa8dd83bb 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -266,14 +266,29 @@ config SH_SDHI help Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform +config SH_MMCIF + bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support" + depends on ARCH_RMOBILE || SH + help + Support for the on-chip MMCIF host controller on SuperH/Renesas ARM SoCs platform + config MMC_UNIPHIER - bool "UniPhier/RCar SD/MMC Host Controller support" - depends on ARCH_UNIPHIER || ARCH_RMOBILE + bool "UniPhier SD/MMC Host Controller support" + depends on ARCH_UNIPHIER + depends on BLK && DM_MMC + depends on OF_CONTROL + help + This selects support for the Matsushita SD/MMC Host Controller on + SocioNext UniPhier SoCs. + +config RENESAS_SDHI + bool "Renesas R-Car SD/MMC Host Controller support" + depends on ARCH_RMOBILE depends on BLK && DM_MMC depends on OF_CONTROL help This selects support for the Matsushita SD/MMC Host Controller on - SocioNext UniPhier and Renesas RCar SoCs. + Renesas R-Car SoCs. config MMC_BCM2835 bool "BCM2835 family custom SD/MMC Host Controller support" diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 958341017c..cf46c332f1 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -62,5 +62,6 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o -obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o +obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o +obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index a2cd5d3a44..454593eec4 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -35,6 +35,9 @@ static void meson_mmc_config_clock(struct mmc *mmc) uint32_t meson_mmc_clk = 0; unsigned int clk, clk_src, clk_div; + if (!mmc->clock) + return; + /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ if (mmc->clock > 16000000) { clk = SD_EMMC_CLKSRC_DIV2; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c930893300..f72b80c704 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1334,7 +1334,7 @@ static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode) return 0; } -int sd_select_bus_width(struct mmc *mmc, int w) +static int sd_select_bus_width(struct mmc *mmc, int w) { int err; struct mmc_cmd cmd; diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 69aa87babe..0ed0d38c90 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -68,7 +68,7 @@ static char *MVSDH_NAME = "mv_sdh"; int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) { struct sdhci_host *host = NULL; - host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + host = calloc(1, sizeof(*host)); if (!host) { printf("sdh_host malloc fail!\n"); return -ENOMEM; diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c new file mode 100644 index 0000000000..8e49b2f73c --- /dev/null +++ b/drivers/mmc/renesas-sdhi.c @@ -0,0 +1,391 @@ +/* + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <fdtdec.h> +#include <mmc.h> +#include <dm.h> +#include <linux/compat.h> +#include <linux/dma-direction.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <power/regulator.h> +#include <asm/unaligned.h> + +#include "tmio-common.h" + +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) + +/* SCC registers */ +#define RENESAS_SDHI_SCC_DTCNTL 0x800 +#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0) +#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 +#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff +#define RENESAS_SDHI_SCC_TAPSET 0x804 +#define RENESAS_SDHI_SCC_DT2FF 0x808 +#define RENESAS_SDHI_SCC_CKSEL 0x80c +#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0) +#define RENESAS_SDHI_SCC_RVSCNTL 0x810 +#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0) +#define RENESAS_SDHI_SCC_RVSREQ 0x814 +#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2) +#define RENESAS_SDHI_SCC_SMPCMP 0x818 +#define RENESAS_SDHI_SCC_TMPPORT2 0x81c + +#define RENESAS_SDHI_MAX_TAP 3 + +static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv) +{ + u32 reg; + + /* Initialize SCC */ + tmio_sd_writel(priv, 0, TMIO_SD_INFO1); + + reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + reg &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); + + /* Set sampling clock selection range */ + tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT, + RENESAS_SDHI_SCC_DTCNTL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL); + reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); + reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); + + tmio_sd_writel(priv, 0x300 /* scc_tappos */, + RENESAS_SDHI_SCC_DT2FF); + + reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + reg |= TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); + + /* Read TAPNUM */ + return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >> + RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & + RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK; +} + +static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv) +{ + u32 reg; + + /* Reset SCC */ + reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + reg &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); + reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); + + reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + reg |= TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); +} + +static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv, + unsigned long tap) +{ + /* Set sampling clock position */ + tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET); +} + +static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv) +{ + /* Get comparison of sampling data */ + return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP); +} + +static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, + unsigned int tap_num, unsigned int taps, + unsigned int smpcmp) +{ + unsigned long tap_cnt; /* counter of tuning success */ + unsigned long tap_set; /* tap position */ + unsigned long tap_start;/* start position of tuning success */ + unsigned long tap_end; /* end position of tuning success */ + unsigned long ntap; /* temporary counter of tuning success */ + unsigned long match_cnt;/* counter of matching data */ + unsigned long i; + bool select = false; + u32 reg; + + /* Clear SCC_RVSREQ */ + tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + + /* Merge the results */ + for (i = 0; i < tap_num * 2; i++) { + if (!(taps & BIT(i))) { + taps &= ~BIT(i % tap_num); + taps &= ~BIT((i % tap_num) + tap_num); + } + if (!(smpcmp & BIT(i))) { + smpcmp &= ~BIT(i % tap_num); + smpcmp &= ~BIT((i % tap_num) + tap_num); + } + } + + /* + * Find the longest consecutive run of successful probes. If that + * is more than RENESAS_SDHI_MAX_TAP probes long then use the + * center index as the tap. + */ + tap_cnt = 0; + ntap = 0; + tap_start = 0; + tap_end = 0; + for (i = 0; i < tap_num * 2; i++) { + if (taps & BIT(i)) + ntap++; + else { + if (ntap > tap_cnt) { + tap_start = i - ntap; + tap_end = i - 1; + tap_cnt = ntap; + } + ntap = 0; + } + } + + if (ntap > tap_cnt) { + tap_start = i - ntap; + tap_end = i - 1; + tap_cnt = ntap; + } + + /* + * If all of the TAP is OK, the sampling clock position is selected by + * identifying the change point of data. + */ + if (tap_cnt == tap_num * 2) { + match_cnt = 0; + ntap = 0; + tap_start = 0; + tap_end = 0; + for (i = 0; i < tap_num * 2; i++) { + if (smpcmp & BIT(i)) + ntap++; + else { + if (ntap > match_cnt) { + tap_start = i - ntap; + tap_end = i - 1; + match_cnt = ntap; + } + ntap = 0; + } + } + if (ntap > match_cnt) { + tap_start = i - ntap; + tap_end = i - 1; + match_cnt = ntap; + } + if (match_cnt) + select = true; + } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP) + select = true; + + if (select) + tap_set = ((tap_start + tap_end) / 2) % tap_num; + else + return -EIO; + + /* Set SCC */ + tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET); + + /* Enable auto re-tuning */ + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); + + return 0; +} + +int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; + unsigned int tap_num; + unsigned int taps = 0, smpcmp = 0; + int i, ret = 0; + u32 caps; + + /* Only supported on Renesas RCar */ + if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS)) + return -EINVAL; + + /* clock tuning is not needed for upto 52MHz */ + if (!((mmc->selected_mode == MMC_HS_200) || + (mmc->selected_mode == UHS_SDR104) || + (mmc->selected_mode == UHS_SDR50))) + return 0; + + tap_num = renesas_sdhi_init_tuning(priv); + if (!tap_num) + /* Tuning is not supported */ + goto out; + + if (tap_num * 2 >= sizeof(taps) * 8) { + dev_err(dev, + "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); + goto out; + } + + /* Issue CMD19 twice for each tap */ + for (i = 0; i < 2 * tap_num; i++) { + renesas_sdhi_prepare_tuning(priv, i % tap_num); + + /* Force PIO for the tuning */ + caps = priv->caps; + priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL; + + ret = mmc_send_tuning(mmc, opcode, NULL); + + priv->caps = caps; + + if (ret == 0) + taps |= BIT(i); + + ret = renesas_sdhi_compare_scc_data(priv); + if (ret == 0) + smpcmp |= BIT(i); + + mdelay(1); + } + + ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp); + +out: + if (ret < 0) { + dev_warn(dev, "Tuning procedure failed\n"); + renesas_sdhi_reset_tuning(priv); + } + + return ret; +} +#endif + +static int renesas_sdhi_set_ios(struct udevice *dev) +{ + int ret = tmio_sd_set_ios(dev); + + mdelay(10); + +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) + struct tmio_sd_priv *priv = dev_get_priv(dev); + + renesas_sdhi_reset_tuning(priv); +#endif + + return ret; +} + +static const struct dm_mmc_ops renesas_sdhi_ops = { + .send_cmd = tmio_sd_send_cmd, + .set_ios = renesas_sdhi_set_ios, + .get_cd = tmio_sd_get_cd, +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) + .execute_tuning = renesas_sdhi_execute_tuning, +#endif +}; + +#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2 +#define RENESAS_GEN3_QUIRKS \ + TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS + +static const struct udevice_id renesas_sdhi_match[] = { + { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS }, + { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS }, + { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS }, + { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS }, + { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS }, + { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS }, + { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS }, + { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS }, + { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS }, + { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS }, + { /* sentinel */ } +}; + +static int renesas_sdhi_probe(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + u32 quirks = dev_get_driver_data(dev); + struct fdt_resource reg_res; + struct clk clk; + DECLARE_GLOBAL_DATA_PTR; + int ret; + + if (quirks == RENESAS_GEN2_QUIRKS) { + ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), + "reg", 0, ®_res); + if (ret < 0) { + dev_err(dev, "\"reg\" resource not found, ret=%i\n", + ret); + return ret; + } + + if (fdt_resource_size(®_res) == 0x100) + quirks |= TMIO_SD_CAP_16BIT; + } + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get host clock\n"); + return ret; + } + + /* set to max rate */ + priv->mclk = clk_set_rate(&clk, ULONG_MAX); + if (IS_ERR_VALUE(priv->mclk)) { + dev_err(dev, "failed to set rate for host clock\n"); + clk_free(&clk); + return priv->mclk; + } + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) { + dev_err(dev, "failed to enable host clock\n"); + return ret; + } + + ret = tmio_sd_probe(dev, quirks); +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) + if (!ret) + renesas_sdhi_reset_tuning(dev_get_priv(dev)); +#endif + return ret; +} + +U_BOOT_DRIVER(renesas_sdhi) = { + .name = "renesas-sdhi", + .id = UCLASS_MMC, + .of_match = renesas_sdhi_match, + .bind = tmio_sd_bind, + .probe = renesas_sdhi_probe, + .priv_auto_alloc_size = sizeof(struct tmio_sd_priv), + .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat), + .ops = &renesas_sdhi_ops, +}; diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 1ff59f06d5..26fe125cea 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -11,9 +11,13 @@ #include <watchdog.h> #include <command.h> #include <mmc.h> +#include <clk.h> +#include <dm.h> #include <malloc.h> #include <linux/errno.h> -#include <asm/io.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <linux/sizes.h> #include "sh_mmcif.h" #define DRIVER_NAME "sh_mmcif" @@ -510,10 +514,9 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, return ret; } -static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) +static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host, + struct mmc_cmd *cmd, struct mmc_data *data) { - struct sh_mmcif_host *host = mmc->priv; int ret; WATCHDOG_RESET(); @@ -539,10 +542,8 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, return ret; } -static int sh_mmcif_set_ios(struct mmc *mmc) +static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc) { - struct sh_mmcif_host *host = mmc->priv; - if (mmc->clock) sh_mmcif_clock_control(host, mmc->clock); @@ -558,19 +559,45 @@ static int sh_mmcif_set_ios(struct mmc *mmc) return 0; } -static int sh_mmcif_init(struct mmc *mmc) +static int sh_mmcif_initialize_common(struct sh_mmcif_host *host) { - struct sh_mmcif_host *host = mmc->priv; - sh_mmcif_sync_reset(host); sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); return 0; } +#ifndef CONFIG_DM_MMC +static void *mmc_priv(struct mmc *mmc) +{ + return (void *)mmc->priv; +} + +static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_send_cmd_common(host, cmd, data); +} + +static int sh_mmcif_set_ios(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_set_ios_common(host, mmc); +} + +static int sh_mmcif_initialize(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_initialize_common(host); +} + static const struct mmc_ops sh_mmcif_ops = { - .send_cmd = sh_mmcif_request, - .set_ios = sh_mmcif_set_ios, - .init = sh_mmcif_init, + .send_cmd = sh_mmcif_send_cmd, + .set_ios = sh_mmcif_set_ios, + .init = sh_mmcif_initialize, }; static struct mmc_config sh_mmcif_cfg = { @@ -606,3 +633,115 @@ int mmcif_mmc_init(void) return 0; } + +#else +struct sh_mmcif_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_mmcif_host *host = dev_get_priv(dev); + + return sh_mmcif_send_cmd_common(host, cmd, data); +} + +int sh_mmcif_dm_set_ios(struct udevice *dev) +{ + struct sh_mmcif_host *host = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return sh_mmcif_set_ios_common(host, mmc); +} + +static const struct dm_mmc_ops sh_mmcif_dm_ops = { + .send_cmd = sh_mmcif_dm_send_cmd, + .set_ios = sh_mmcif_dm_set_ios, +}; + +static int sh_mmcif_dm_bind(struct udevice *dev) +{ + struct sh_mmcif_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +static int sh_mmcif_dm_probe(struct udevice *dev) +{ + struct sh_mmcif_plat *plat = dev_get_platdata(dev); + struct sh_mmcif_host *host = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct clk sh_mmcif_clk; + fdt_addr_t base; + int ret; + + base = devfdt_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K); + if (!host->regs) + return -ENOMEM; + + ret = clk_get_by_index(dev, 0, &sh_mmcif_clk); + if (ret) { + debug("failed to get clock, ret=%d\n", ret); + return ret; + } + + ret = clk_enable(&sh_mmcif_clk); + if (ret) { + debug("failed to enable clock, ret=%d\n", ret); + return ret; + } + + host->clk = clk_get_rate(&sh_mmcif_clk); + + plat->cfg.name = dev->name; + plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + + switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", + 1)) { + case 8: + plat->cfg.host_caps |= MMC_MODE_8BIT; + break; + case 4: + plat->cfg.host_caps |= MMC_MODE_4BIT; + break; + case 1: + break; + default: + dev_err(dev, "Invalid \"bus-width\" value\n"); + return -EINVAL; + } + + sh_mmcif_initialize_common(host); + + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk); + plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk); + plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + upriv->mmc = &plat->mmc; + + return 0; +} + +static const struct udevice_id sh_mmcif_sd_match[] = { + { .compatible = "renesas,sh-mmcif" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sh_mmcif_mmc) = { + .name = "sh-mmcif", + .id = UCLASS_MMC, + .of_match = sh_mmcif_sd_match, + .bind = sh_mmcif_dm_bind, + .probe = sh_mmcif_dm_probe, + .priv_auto_alloc_size = sizeof(struct sh_mmcif_host), + .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat), + .ops = &sh_mmcif_dm_ops, +}; +#endif diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c new file mode 100644 index 0000000000..4ea6612142 --- /dev/null +++ b/drivers/mmc/tmio-common.c @@ -0,0 +1,765 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <fdtdec.h> +#include <mmc.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <linux/compat.h> +#include <linux/dma-direction.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <power/regulator.h> +#include <asm/unaligned.h> + +#include "tmio-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg) +{ + return readq(priv->regbase + (reg << 1)); +} + +static void tmio_sd_writeq(struct tmio_sd_priv *priv, + u64 val, unsigned int reg) +{ + writeq(val, priv->regbase + (reg << 1)); +} + +static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg) +{ + return readw(priv->regbase + (reg >> 1)); +} + +static void tmio_sd_writew(struct tmio_sd_priv *priv, + u16 val, unsigned int reg) +{ + writew(val, priv->regbase + (reg >> 1)); +} + +u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg) +{ + u32 val; + + if (priv->caps & TMIO_SD_CAP_64BIT) + return readl(priv->regbase + (reg << 1)); + else if (priv->caps & TMIO_SD_CAP_16BIT) { + val = readw(priv->regbase + (reg >> 1)) & 0xffff; + if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) || + (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) { + val |= readw(priv->regbase + (reg >> 1) + 2) << 16; + } + return val; + } else + return readl(priv->regbase + reg); +} + +void tmio_sd_writel(struct tmio_sd_priv *priv, + u32 val, unsigned int reg) +{ + if (priv->caps & TMIO_SD_CAP_64BIT) + writel(val, priv->regbase + (reg << 1)); + else if (priv->caps & TMIO_SD_CAP_16BIT) { + writew(val & 0xffff, priv->regbase + (reg >> 1)); + if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK || + reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK || + reg == TMIO_SD_ARG) + writew(val >> 16, priv->regbase + (reg >> 1) + 2); + } else + writel(val, priv->regbase + reg); +} + +static dma_addr_t __dma_map_single(void *ptr, size_t size, + enum dma_data_direction dir) +{ + unsigned long addr = (unsigned long)ptr; + + if (dir == DMA_FROM_DEVICE) + invalidate_dcache_range(addr, addr + size); + else + flush_dcache_range(addr, addr + size); + + return addr; +} + +static void __dma_unmap_single(dma_addr_t addr, size_t size, + enum dma_data_direction dir) +{ + if (dir != DMA_TO_DEVICE) + invalidate_dcache_range(addr, addr + size); +} + +static int tmio_sd_check_error(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2); + + if (info2 & TMIO_SD_INFO2_ERR_RTO) { + /* + * TIMEOUT must be returned for unsupported command. Do not + * display error log since this might be a part of sequence to + * distinguish between SD and MMC. + */ + return -ETIMEDOUT; + } + + if (info2 & TMIO_SD_INFO2_ERR_TO) { + dev_err(dev, "timeout error\n"); + return -ETIMEDOUT; + } + + if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC | + TMIO_SD_INFO2_ERR_IDX)) { + dev_err(dev, "communication out of sync\n"); + return -EILSEQ; + } + + if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR | + TMIO_SD_INFO2_ERR_ILW)) { + dev_err(dev, "illegal access\n"); + return -EIO; + } + + return 0; +} + +static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg, + u32 flag) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + long wait = 1000000; + int ret; + + while (!(tmio_sd_readl(priv, reg) & flag)) { + if (wait-- < 0) { + dev_err(dev, "timeout\n"); + return -ETIMEDOUT; + } + + ret = tmio_sd_check_error(dev); + if (ret) + return ret; + + udelay(1); + } + + return 0; +} + +#define tmio_pio_read_fifo(__width, __suffix) \ +static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \ + char *pbuf, uint blksz) \ +{ \ + u##__width *buf = (u##__width *)pbuf; \ + int i; \ + \ + if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ + for (i = 0; i < blksz / ((__width) / 8); i++) { \ + *buf++ = tmio_sd_read##__suffix(priv, \ + TMIO_SD_BUF); \ + } \ + } else { \ + for (i = 0; i < blksz / ((__width) / 8); i++) { \ + u##__width data; \ + data = tmio_sd_read##__suffix(priv, \ + TMIO_SD_BUF); \ + put_unaligned(data, buf++); \ + } \ + } \ +} + +tmio_pio_read_fifo(64, q) +tmio_pio_read_fifo(32, l) +tmio_pio_read_fifo(16, w) + +static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf, + uint blocksize) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + int ret; + + /* wait until the buffer is filled with data */ + ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, + TMIO_SD_INFO2_BRE); + if (ret) + return ret; + + /* + * Clear the status flag _before_ read the buffer out because + * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered. + */ + tmio_sd_writel(priv, 0, TMIO_SD_INFO2); + + if (priv->caps & TMIO_SD_CAP_64BIT) + tmio_pio_read_fifo_64(priv, pbuf, blocksize); + else if (priv->caps & TMIO_SD_CAP_16BIT) + tmio_pio_read_fifo_16(priv, pbuf, blocksize); + else + tmio_pio_read_fifo_32(priv, pbuf, blocksize); + + return 0; +} + +#define tmio_pio_write_fifo(__width, __suffix) \ +static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \ + const char *pbuf, uint blksz)\ +{ \ + const u##__width *buf = (const u##__width *)pbuf; \ + int i; \ + \ + if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ + for (i = 0; i < blksz / ((__width) / 8); i++) { \ + tmio_sd_write##__suffix(priv, *buf++, \ + TMIO_SD_BUF); \ + } \ + } else { \ + for (i = 0; i < blksz / ((__width) / 8); i++) { \ + u##__width data = get_unaligned(buf++); \ + tmio_sd_write##__suffix(priv, data, \ + TMIO_SD_BUF); \ + } \ + } \ +} + +tmio_pio_write_fifo(64, q) +tmio_pio_write_fifo(32, l) +tmio_pio_write_fifo(16, w) + +static int tmio_sd_pio_write_one_block(struct udevice *dev, + const char *pbuf, uint blocksize) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + int ret; + + /* wait until the buffer becomes empty */ + ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, + TMIO_SD_INFO2_BWE); + if (ret) + return ret; + + tmio_sd_writel(priv, 0, TMIO_SD_INFO2); + + if (priv->caps & TMIO_SD_CAP_64BIT) + tmio_pio_write_fifo_64(priv, pbuf, blocksize); + else if (priv->caps & TMIO_SD_CAP_16BIT) + tmio_pio_write_fifo_16(priv, pbuf, blocksize); + else + tmio_pio_write_fifo_32(priv, pbuf, blocksize); + + return 0; +} + +static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) +{ + const char *src = data->src; + char *dest = data->dest; + int i, ret; + + for (i = 0; i < data->blocks; i++) { + if (data->flags & MMC_DATA_READ) + ret = tmio_sd_pio_read_one_block(dev, dest, + data->blocksize); + else + ret = tmio_sd_pio_write_one_block(dev, src, + data->blocksize); + if (ret) + return ret; + + if (data->flags & MMC_DATA_READ) + dest += data->blocksize; + else + src += data->blocksize; + } + + return 0; +} + +static void tmio_sd_dma_start(struct tmio_sd_priv *priv, + dma_addr_t dma_addr) +{ + u32 tmp; + + tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1); + tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2); + + /* enable DMA */ + tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); + tmp |= TMIO_SD_EXTMODE_DMA_EN; + tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); + + tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L); + + /* suppress the warning "right shift count >= width of type" */ + dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); + + tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H); + + tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL); +} + +static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, + unsigned int blocks) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + long wait = 1000000 + 10 * blocks; + + while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) { + if (wait-- < 0) { + dev_err(dev, "timeout during DMA\n"); + return -ETIMEDOUT; + } + + udelay(10); + } + + if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) { + dev_err(dev, "error during DMA\n"); + return -EIO; + } + + return 0; +} + +static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + size_t len = data->blocks * data->blocksize; + void *buf; + enum dma_data_direction dir; + dma_addr_t dma_addr; + u32 poll_flag, tmp; + int ret; + + tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); + + if (data->flags & MMC_DATA_READ) { + buf = data->dest; + dir = DMA_FROM_DEVICE; + /* + * The DMA READ completion flag position differs on Socionext + * and Renesas SoCs. It is bit 20 on Socionext SoCs and using + * bit 17 is a hardware bug and forbidden. It is bit 17 on + * Renesas SoCs and bit 20 does not work on them. + */ + poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ? + TMIO_SD_DMA_INFO1_END_RD : + TMIO_SD_DMA_INFO1_END_RD2; + tmp |= TMIO_SD_DMA_MODE_DIR_RD; + } else { + buf = (void *)data->src; + dir = DMA_TO_DEVICE; + poll_flag = TMIO_SD_DMA_INFO1_END_WR; + tmp &= ~TMIO_SD_DMA_MODE_DIR_RD; + } + + tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); + + dma_addr = __dma_map_single(buf, len, dir); + + tmio_sd_dma_start(priv, dma_addr); + + ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); + + __dma_unmap_single(dma_addr, len, dir); + + return ret; +} + +/* check if the address is DMA'able */ +static bool tmio_sd_addr_is_dmaable(unsigned long addr) +{ + if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN)) + return false; + +#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ + defined(CONFIG_SPL_BUILD) + /* + * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways + * of L2, which is unreachable from the DMA engine. + */ + if (addr < CONFIG_SPL_STACK) + return false; +#endif + + return true; +} + +int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + int ret; + u32 tmp; + + if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) { + dev_err(dev, "command busy\n"); + return -EBUSY; + } + + /* clear all status flags */ + tmio_sd_writel(priv, 0, TMIO_SD_INFO1); + tmio_sd_writel(priv, 0, TMIO_SD_INFO2); + + /* disable DMA once */ + tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); + tmp &= ~TMIO_SD_EXTMODE_DMA_EN; + tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); + + tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG); + + tmp = cmd->cmdidx; + + if (data) { + tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE); + tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT); + + /* Do not send CMD12 automatically */ + tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA; + + if (data->blocks > 1) + tmp |= TMIO_SD_CMD_MULTI; + + if (data->flags & MMC_DATA_READ) + tmp |= TMIO_SD_CMD_RD; + } + + /* + * Do not use the response type auto-detection on this hardware. + * CMD8, for example, has different response types on SD and eMMC, + * while this controller always assumes the response type for SD. + * Set the response type manually. + */ + switch (cmd->resp_type) { + case MMC_RSP_NONE: + tmp |= TMIO_SD_CMD_RSP_NONE; + break; + case MMC_RSP_R1: + tmp |= TMIO_SD_CMD_RSP_R1; + break; + case MMC_RSP_R1b: + tmp |= TMIO_SD_CMD_RSP_R1B; + break; + case MMC_RSP_R2: + tmp |= TMIO_SD_CMD_RSP_R2; + break; + case MMC_RSP_R3: + tmp |= TMIO_SD_CMD_RSP_R3; + break; + default: + dev_err(dev, "unknown response type\n"); + return -EINVAL; + } + + dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", + cmd->cmdidx, tmp, cmd->cmdarg); + tmio_sd_writel(priv, tmp, TMIO_SD_CMD); + + ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1, + TMIO_SD_INFO1_RSP); + if (ret) + return ret; + + if (cmd->resp_type & MMC_RSP_136) { + u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76); + u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54); + u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32); + u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10); + + cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | + ((rsp_103_72 & 0xff000000) >> 24); + cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | + ((rsp_71_40 & 0xff000000) >> 24); + cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | + ((rsp_39_8 & 0xff000000) >> 24); + cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; + } else { + /* bit 39-8 */ + cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10); + } + + if (data) { + /* use DMA if the HW supports it and the buffer is aligned */ + if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL && + tmio_sd_addr_is_dmaable((long)data->src)) + ret = tmio_sd_dma_xfer(dev, data); + else + ret = tmio_sd_pio_xfer(dev, data); + + ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1, + TMIO_SD_INFO1_CMP); + if (ret) + return ret; + } + + tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN); + + return ret; +} + +static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv, + struct mmc *mmc) +{ + u32 val, tmp; + + switch (mmc->bus_width) { + case 0: + case 1: + val = TMIO_SD_OPTION_WIDTH_1; + break; + case 4: + val = TMIO_SD_OPTION_WIDTH_4; + break; + case 8: + val = TMIO_SD_OPTION_WIDTH_8; + break; + default: + return -EINVAL; + } + + tmp = tmio_sd_readl(priv, TMIO_SD_OPTION); + tmp &= ~TMIO_SD_OPTION_WIDTH_MASK; + tmp |= val; + tmio_sd_writel(priv, tmp, TMIO_SD_OPTION); + + return 0; +} + +static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv, + struct mmc *mmc) +{ + u32 tmp; + + tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE); + if (mmc->ddr_mode) + tmp |= TMIO_SD_IF_MODE_DDR; + else + tmp &= ~TMIO_SD_IF_MODE_DDR; + tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE); +} + +static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, + struct mmc *mmc) +{ + unsigned int divisor; + u32 val, tmp; + + if (!mmc->clock) + return; + + divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); + + if (divisor <= 1) + val = (priv->caps & TMIO_SD_CAP_RCAR) ? + TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; + else if (divisor <= 2) + val = TMIO_SD_CLKCTL_DIV2; + else if (divisor <= 4) + val = TMIO_SD_CLKCTL_DIV4; + else if (divisor <= 8) + val = TMIO_SD_CLKCTL_DIV8; + else if (divisor <= 16) + val = TMIO_SD_CLKCTL_DIV16; + else if (divisor <= 32) + val = TMIO_SD_CLKCTL_DIV32; + else if (divisor <= 64) + val = TMIO_SD_CLKCTL_DIV64; + else if (divisor <= 128) + val = TMIO_SD_CLKCTL_DIV128; + else if (divisor <= 256) + val = TMIO_SD_CLKCTL_DIV256; + else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) + val = TMIO_SD_CLKCTL_DIV512; + else + val = TMIO_SD_CLKCTL_DIV1024; + + tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); + if (tmp & TMIO_SD_CLKCTL_SCLKEN && + (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val) + return; + + /* stop the clock before changing its rate to avoid a glitch signal */ + tmp &= ~TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + + tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; + tmp |= val | TMIO_SD_CLKCTL_OFFEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + + tmp |= TMIO_SD_CLKCTL_SCLKEN; + tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); + + udelay(1000); +} + +static void tmio_sd_set_pins(struct udevice *dev) +{ + __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev); + +#ifdef CONFIG_DM_REGULATOR + struct tmio_sd_priv *priv = dev_get_priv(dev); + + if (priv->vqmmc_dev) { + if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + regulator_set_value(priv->vqmmc_dev, 1800000); + else + regulator_set_value(priv->vqmmc_dev, 3300000); + regulator_set_enable(priv->vqmmc_dev, true); + } +#endif + +#ifdef CONFIG_PINCTRL + switch (mmc->selected_mode) { + case MMC_LEGACY: + case SD_LEGACY: + case MMC_HS: + case SD_HS: + case MMC_HS_52: + case MMC_DDR_52: + pinctrl_select_state(dev, "default"); + break; + case UHS_SDR12: + case UHS_SDR25: + case UHS_SDR50: + case UHS_DDR50: + case UHS_SDR104: + case MMC_HS_200: + pinctrl_select_state(dev, "state_uhs"); + break; + default: + break; + } +#endif +} + +int tmio_sd_set_ios(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + int ret; + + dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", + mmc->clock, mmc->ddr_mode, mmc->bus_width); + + ret = tmio_sd_set_bus_width(priv, mmc); + if (ret) + return ret; + tmio_sd_set_ddr_mode(priv, mmc); + tmio_sd_set_clk_rate(priv, mmc); + tmio_sd_set_pins(dev); + + return 0; +} + +int tmio_sd_get_cd(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + + if (priv->caps & TMIO_SD_CAP_NONREMOVABLE) + return 1; + + return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) & + TMIO_SD_INFO1_CD); +} + +static void tmio_sd_host_init(struct tmio_sd_priv *priv) +{ + u32 tmp; + + /* soft reset of the host */ + tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST); + tmp &= ~TMIO_SD_SOFT_RST_RSTX; + tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); + tmp |= TMIO_SD_SOFT_RST_RSTX; + tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); + + /* FIXME: implement eMMC hw_reset */ + + tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP); + + /* + * Connected to 32bit AXI. + * This register dropped backward compatibility at version 0x10. + * Write an appropriate value depending on the IP version. + */ + if (priv->version >= 0x10) + tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE); + else + tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE); + + if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) { + tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); + tmp |= TMIO_SD_DMA_MODE_ADDR_INC; + tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); + } +} + +int tmio_sd_bind(struct udevice *dev) +{ + struct tmio_sd_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +int tmio_sd_probe(struct udevice *dev, u32 quirks) +{ + struct tmio_sd_plat *plat = dev_get_platdata(dev); + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + fdt_addr_t base; + int ret; + + base = devfdt_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regbase = devm_ioremap(dev, base, SZ_2K); + if (!priv->regbase) + return -ENOMEM; + +#ifdef CONFIG_DM_REGULATOR + device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev); +#endif + + ret = mmc_of_parse(dev, &plat->cfg); + if (ret < 0) { + dev_err(dev, "failed to parse host caps\n"); + return ret; + } + + plat->cfg.name = dev->name; + plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + + if (quirks) + priv->caps = quirks; + + priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) & + TMIO_SD_VERSION_IP; + dev_dbg(dev, "version %x\n", priv->version); + if (priv->version >= 0x10) { + priv->caps |= TMIO_SD_CAP_DMA_INTERNAL; + priv->caps |= TMIO_SD_CAP_DIV1024; + } + + if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", + NULL)) + priv->caps |= TMIO_SD_CAP_NONREMOVABLE; + + tmio_sd_host_init(priv); + + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + plat->cfg.f_min = priv->mclk / + (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); + plat->cfg.f_max = priv->mclk; + plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ + + upriv->mmc = &plat->mmc; + + return 0; +} diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h new file mode 100644 index 0000000000..ef9404409d --- /dev/null +++ b/drivers/mmc/tmio-common.h @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TMIO_COMMON_H__ +#define __TMIO_COMMON_H__ + +#define TMIO_SD_CMD 0x000 /* command */ +#define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ +#define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */ +#define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */ +#define TMIO_SD_CMD_DATA BIT(11) /* data transfer */ +#define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ +#define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ +#define TMIO_SD_CMD_RSP_NONE (3 << 8)/* response: none */ +#define TMIO_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ +#define TMIO_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ +#define TMIO_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ +#define TMIO_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ +#define TMIO_SD_ARG 0x008 /* command argument */ +#define TMIO_SD_STOP 0x010 /* stop action control */ +#define TMIO_SD_STOP_SEC BIT(8) /* use sector count */ +#define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */ +#define TMIO_SD_SECCNT 0x014 /* sector counter */ +#define TMIO_SD_RSP10 0x018 /* response[39:8] */ +#define TMIO_SD_RSP32 0x020 /* response[71:40] */ +#define TMIO_SD_RSP54 0x028 /* response[103:72] */ +#define TMIO_SD_RSP76 0x030 /* response[127:104] */ +#define TMIO_SD_INFO1 0x038 /* IRQ status 1 */ +#define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */ +#define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */ +#define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */ +#define TMIO_SD_INFO1_CMP BIT(2) /* data complete */ +#define TMIO_SD_INFO1_RSP BIT(0) /* response complete */ +#define TMIO_SD_INFO2 0x03c /* IRQ status 2 */ +#define TMIO_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ +#define TMIO_SD_INFO2_CBSY BIT(14) /* command busy */ +#define TMIO_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */ +#define TMIO_SD_INFO2_BWE BIT(9) /* write buffer ready */ +#define TMIO_SD_INFO2_BRE BIT(8) /* read buffer ready */ +#define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ +#define TMIO_SD_INFO2_ERR_RTO BIT(6) /* response time out */ +#define TMIO_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ +#define TMIO_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ +#define TMIO_SD_INFO2_ERR_TO BIT(3) /* time out error */ +#define TMIO_SD_INFO2_ERR_END BIT(2) /* END bit error */ +#define TMIO_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ +#define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ +#define TMIO_SD_INFO1_MASK 0x040 +#define TMIO_SD_INFO2_MASK 0x044 +#define TMIO_SD_CLKCTL 0x048 /* clock divisor */ +#define TMIO_SD_CLKCTL_DIV_MASK 0x104ff +#define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ +#define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ +#define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ +#define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ +#define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ +#define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ +#define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ +#define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ +#define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ +#define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ +#define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ +#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ +#define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ +#define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ +#define TMIO_SD_SIZE 0x04c /* block size */ +#define TMIO_SD_OPTION 0x050 +#define TMIO_SD_OPTION_WIDTH_MASK (5 << 13) +#define TMIO_SD_OPTION_WIDTH_1 (4 << 13) +#define TMIO_SD_OPTION_WIDTH_4 (0 << 13) +#define TMIO_SD_OPTION_WIDTH_8 (1 << 13) +#define TMIO_SD_BUF 0x060 /* read/write buffer */ +#define TMIO_SD_EXTMODE 0x1b0 +#define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ +#define TMIO_SD_SOFT_RST 0x1c0 +#define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ +#define TMIO_SD_VERSION 0x1c4 /* version register */ +#define TMIO_SD_VERSION_IP 0xff /* IP version */ +#define TMIO_SD_HOST_MODE 0x1c8 +#define TMIO_SD_IF_MODE 0x1cc +#define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */ +#define TMIO_SD_VOLT 0x1e4 /* voltage switch */ +#define TMIO_SD_VOLT_MASK (3 << 0) +#define TMIO_SD_VOLT_OFF (0 << 0) +#define TMIO_SD_VOLT_330 (1 << 0)/* 3.3V signal */ +#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */ +#define TMIO_SD_DMA_MODE 0x410 +#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ +#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ +#define TMIO_SD_DMA_CTL 0x414 +#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ +#define TMIO_SD_DMA_RST 0x418 +#define TMIO_SD_DMA_RST_RD BIT(9) +#define TMIO_SD_DMA_RST_WR BIT(8) +#define TMIO_SD_DMA_INFO1 0x420 +#define TMIO_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */ +#define TMIO_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */ +#define TMIO_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ +#define TMIO_SD_DMA_INFO1_MASK 0x424 +#define TMIO_SD_DMA_INFO2 0x428 +#define TMIO_SD_DMA_INFO2_ERR_RD BIT(17) +#define TMIO_SD_DMA_INFO2_ERR_WR BIT(16) +#define TMIO_SD_DMA_INFO2_MASK 0x42c +#define TMIO_SD_DMA_ADDR_L 0x440 +#define TMIO_SD_DMA_ADDR_H 0x444 + +/* alignment required by the DMA engine of this controller */ +#define TMIO_SD_DMA_MINALIGN 0x10 + +struct tmio_sd_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct tmio_sd_priv { + void __iomem *regbase; + unsigned long mclk; + unsigned int version; + u32 caps; +#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ +#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ +#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ +#define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ +#define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */ +#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */ +#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */ +#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */ +#define TMIO_SD_CAP_RCAR \ + (TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3) +#ifdef CONFIG_DM_REGULATOR + struct udevice *vqmmc_dev; +#endif +}; + +int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data); +int tmio_sd_set_ios(struct udevice *dev); +int tmio_sd_get_cd(struct udevice *dev); + +int tmio_sd_bind(struct udevice *dev); +int tmio_sd_probe(struct udevice *dev, u32 quirks); + +u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg); +void tmio_sd_writel(struct tmio_sd_priv *priv, + u32 val, unsigned int reg); + +#endif /* __TMIO_COMMON_H__ */ diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 525b1702b9..61f8da4e41 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -17,766 +17,25 @@ #include <power/regulator.h> #include <asm/unaligned.h> -DECLARE_GLOBAL_DATA_PTR; - -#define UNIPHIER_SD_CMD 0x000 /* command */ -#define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ -#define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */ -#define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */ -#define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */ -#define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ -#define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ -#define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */ -#define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ -#define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ -#define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ -#define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ -#define UNIPHIER_SD_ARG 0x008 /* command argument */ -#define UNIPHIER_SD_STOP 0x010 /* stop action control */ -#define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */ -#define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */ -#define UNIPHIER_SD_SECCNT 0x014 /* sector counter */ -#define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */ -#define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */ -#define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */ -#define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */ -#define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */ -#define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */ -#define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */ -#define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */ -#define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */ -#define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */ -#define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */ -#define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ -#define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */ -#define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */ -#define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */ -#define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ -#define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */ -#define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ -#define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ -#define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */ -#define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */ -#define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ -#define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ -#define UNIPHIER_SD_INFO1_MASK 0x040 -#define UNIPHIER_SD_INFO2_MASK 0x044 -#define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */ -#define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff -#define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ -#define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ -#define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ -#define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ -#define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ -#define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ -#define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ -#define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ -#define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ -#define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ -#define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ -#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ -#define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ -#define UNIPHIER_SD_SIZE 0x04c /* block size */ -#define UNIPHIER_SD_OPTION 0x050 -#define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13) -#define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13) -#define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13) -#define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13) -#define UNIPHIER_SD_BUF 0x060 /* read/write buffer */ -#define UNIPHIER_SD_EXTMODE 0x1b0 -#define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ -#define UNIPHIER_SD_SOFT_RST 0x1c0 -#define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ -#define UNIPHIER_SD_VERSION 0x1c4 /* version register */ -#define UNIPHIER_SD_VERSION_IP 0xff /* IP version */ -#define UNIPHIER_SD_HOST_MODE 0x1c8 -#define UNIPHIER_SD_IF_MODE 0x1cc -#define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */ -#define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */ -#define UNIPHIER_SD_VOLT_MASK (3 << 0) -#define UNIPHIER_SD_VOLT_OFF (0 << 0) -#define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */ -#define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */ -#define UNIPHIER_SD_DMA_MODE 0x410 -#define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ -#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ -#define UNIPHIER_SD_DMA_CTL 0x414 -#define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ -#define UNIPHIER_SD_DMA_RST 0x418 -#define UNIPHIER_SD_DMA_RST_RD BIT(9) -#define UNIPHIER_SD_DMA_RST_WR BIT(8) -#define UNIPHIER_SD_DMA_INFO1 0x420 -#define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/ -#define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */ -#define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ -#define UNIPHIER_SD_DMA_INFO1_MASK 0x424 -#define UNIPHIER_SD_DMA_INFO2 0x428 -#define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17) -#define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16) -#define UNIPHIER_SD_DMA_INFO2_MASK 0x42c -#define UNIPHIER_SD_DMA_ADDR_L 0x440 -#define UNIPHIER_SD_DMA_ADDR_H 0x444 - -/* alignment required by the DMA engine of this controller */ -#define UNIPHIER_SD_DMA_MINALIGN 0x10 - -struct uniphier_sd_plat { - struct mmc_config cfg; - struct mmc mmc; -}; - -struct uniphier_sd_priv { - void __iomem *regbase; - unsigned long mclk; - unsigned int version; - u32 caps; -#define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ -#define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ -#define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ -#define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ -}; - -static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg) -{ - if (priv->caps & UNIPHIER_SD_CAP_64BIT) - return readq(priv->regbase + (reg << 1)); - else - return readq(priv->regbase + reg); -} - -static void uniphier_sd_writeq(struct uniphier_sd_priv *priv, - u64 val, unsigned int reg) -{ - if (priv->caps & UNIPHIER_SD_CAP_64BIT) - writeq(val, priv->regbase + (reg << 1)); - else - writeq(val, priv->regbase + reg); -} - -static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg) -{ - if (priv->caps & UNIPHIER_SD_CAP_64BIT) - return readl(priv->regbase + (reg << 1)); - else - return readl(priv->regbase + reg); -} - -static void uniphier_sd_writel(struct uniphier_sd_priv *priv, - u32 val, unsigned int reg) -{ - if (priv->caps & UNIPHIER_SD_CAP_64BIT) - writel(val, priv->regbase + (reg << 1)); - else - writel(val, priv->regbase + reg); -} - -static dma_addr_t __dma_map_single(void *ptr, size_t size, - enum dma_data_direction dir) -{ - unsigned long addr = (unsigned long)ptr; - - if (dir == DMA_FROM_DEVICE) - invalidate_dcache_range(addr, addr + size); - else - flush_dcache_range(addr, addr + size); - - return addr; -} - -static void __dma_unmap_single(dma_addr_t addr, size_t size, - enum dma_data_direction dir) -{ - if (dir != DMA_TO_DEVICE) - invalidate_dcache_range(addr, addr + size); -} - -static int uniphier_sd_check_error(struct udevice *dev) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2); - - if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { - /* - * TIMEOUT must be returned for unsupported command. Do not - * display error log since this might be a part of sequence to - * distinguish between SD and MMC. - */ - return -ETIMEDOUT; - } - - if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { - dev_err(dev, "timeout error\n"); - return -ETIMEDOUT; - } - - if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC | - UNIPHIER_SD_INFO2_ERR_IDX)) { - dev_err(dev, "communication out of sync\n"); - return -EILSEQ; - } - - if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR | - UNIPHIER_SD_INFO2_ERR_ILW)) { - dev_err(dev, "illegal access\n"); - return -EIO; - } - - return 0; -} - -static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg, - u32 flag) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - long wait = 1000000; - int ret; - - while (!(uniphier_sd_readl(priv, reg) & flag)) { - if (wait-- < 0) { - dev_err(dev, "timeout\n"); - return -ETIMEDOUT; - } - - ret = uniphier_sd_check_error(dev); - if (ret) - return ret; - - udelay(1); - } - - return 0; -} - -static int uniphier_sd_pio_read_one_block(struct udevice *dev, char *pbuf, - uint blocksize) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - int i, ret; - - /* wait until the buffer is filled with data */ - ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, - UNIPHIER_SD_INFO2_BRE); - if (ret) - return ret; - - /* - * Clear the status flag _before_ read the buffer out because - * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. - */ - uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); - - if (priv->caps & UNIPHIER_SD_CAP_64BIT) { - u64 *buf = (u64 *)pbuf; - if (likely(IS_ALIGNED((uintptr_t)buf, 8))) { - for (i = 0; i < blocksize / 8; i++) { - *buf++ = uniphier_sd_readq(priv, - UNIPHIER_SD_BUF); - } - } else { - for (i = 0; i < blocksize / 8; i++) { - u64 data; - data = uniphier_sd_readq(priv, - UNIPHIER_SD_BUF); - put_unaligned(data, buf++); - } - } - } else { - u32 *buf = (u32 *)pbuf; - if (likely(IS_ALIGNED((uintptr_t)buf, 4))) { - for (i = 0; i < blocksize / 4; i++) { - *buf++ = uniphier_sd_readl(priv, - UNIPHIER_SD_BUF); - } - } else { - for (i = 0; i < blocksize / 4; i++) { - u32 data; - data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF); - put_unaligned(data, buf++); - } - } - } - - return 0; -} - -static int uniphier_sd_pio_write_one_block(struct udevice *dev, - const char *pbuf, uint blocksize) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - int i, ret; - - /* wait until the buffer becomes empty */ - ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, - UNIPHIER_SD_INFO2_BWE); - if (ret) - return ret; - - uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); - - if (priv->caps & UNIPHIER_SD_CAP_64BIT) { - const u64 *buf = (const u64 *)pbuf; - if (likely(IS_ALIGNED((uintptr_t)buf, 8))) { - for (i = 0; i < blocksize / 8; i++) { - uniphier_sd_writeq(priv, *buf++, - UNIPHIER_SD_BUF); - } - } else { - for (i = 0; i < blocksize / 8; i++) { - u64 data = get_unaligned(buf++); - uniphier_sd_writeq(priv, data, - UNIPHIER_SD_BUF); - } - } - } else { - const u32 *buf = (const u32 *)pbuf; - if (likely(IS_ALIGNED((uintptr_t)buf, 4))) { - for (i = 0; i < blocksize / 4; i++) { - uniphier_sd_writel(priv, *buf++, - UNIPHIER_SD_BUF); - } - } else { - for (i = 0; i < blocksize / 4; i++) { - u32 data = get_unaligned(buf++); - uniphier_sd_writel(priv, data, - UNIPHIER_SD_BUF); - } - } - } - - return 0; -} - -static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) -{ - const char *src = data->src; - char *dest = data->dest; - int i, ret; - - for (i = 0; i < data->blocks; i++) { - if (data->flags & MMC_DATA_READ) - ret = uniphier_sd_pio_read_one_block(dev, dest, - data->blocksize); - else - ret = uniphier_sd_pio_write_one_block(dev, src, - data->blocksize); - if (ret) - return ret; - - if (data->flags & MMC_DATA_READ) - dest += data->blocksize; - else - src += data->blocksize; - } - - return 0; -} - -static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, - dma_addr_t dma_addr) -{ - u32 tmp; - - uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1); - uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2); - - /* enable DMA */ - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); - tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); - - uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L); - - /* suppress the warning "right shift count >= width of type" */ - dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); - - uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H); - - uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL); -} - -static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, - unsigned int blocks) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - long wait = 1000000 + 10 * blocks; - - while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) { - if (wait-- < 0) { - dev_err(dev, "timeout during DMA\n"); - return -ETIMEDOUT; - } - - udelay(10); - } - - if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) { - dev_err(dev, "error during DMA\n"); - return -EIO; - } - - return 0; -} - -static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - size_t len = data->blocks * data->blocksize; - void *buf; - enum dma_data_direction dir; - dma_addr_t dma_addr; - u32 poll_flag, tmp; - int ret; - - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); - - if (data->flags & MMC_DATA_READ) { - buf = data->dest; - dir = DMA_FROM_DEVICE; - poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2; - tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD; - } else { - buf = (void *)data->src; - dir = DMA_TO_DEVICE; - poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR; - tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; - } - - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); - - dma_addr = __dma_map_single(buf, len, dir); - - uniphier_sd_dma_start(priv, dma_addr); - - ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); - - __dma_unmap_single(dma_addr, len, dir); - - return ret; -} - -/* check if the address is DMA'able */ -static bool uniphier_sd_addr_is_dmaable(unsigned long addr) -{ - if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN)) - return false; - -#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ - defined(CONFIG_SPL_BUILD) - /* - * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways - * of L2, which is unreachable from the DMA engine. - */ - if (addr < CONFIG_SPL_STACK) - return false; -#endif - - return true; -} - -static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - int ret; - u32 tmp; - - if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { - dev_err(dev, "command busy\n"); - return -EBUSY; - } - - /* clear all status flags */ - uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1); - uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); - - /* disable DMA once */ - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); - tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); - - uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG); - - tmp = cmd->cmdidx; - - if (data) { - uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE); - uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT); - - /* Do not send CMD12 automatically */ - tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; - - if (data->blocks > 1) - tmp |= UNIPHIER_SD_CMD_MULTI; - - if (data->flags & MMC_DATA_READ) - tmp |= UNIPHIER_SD_CMD_RD; - } - - /* - * Do not use the response type auto-detection on this hardware. - * CMD8, for example, has different response types on SD and eMMC, - * while this controller always assumes the response type for SD. - * Set the response type manually. - */ - switch (cmd->resp_type) { - case MMC_RSP_NONE: - tmp |= UNIPHIER_SD_CMD_RSP_NONE; - break; - case MMC_RSP_R1: - tmp |= UNIPHIER_SD_CMD_RSP_R1; - break; - case MMC_RSP_R1b: - tmp |= UNIPHIER_SD_CMD_RSP_R1B; - break; - case MMC_RSP_R2: - tmp |= UNIPHIER_SD_CMD_RSP_R2; - break; - case MMC_RSP_R3: - tmp |= UNIPHIER_SD_CMD_RSP_R3; - break; - default: - dev_err(dev, "unknown response type\n"); - return -EINVAL; - } - - dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", - cmd->cmdidx, tmp, cmd->cmdarg); - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD); - - ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, - UNIPHIER_SD_INFO1_RSP); - if (ret) - return ret; - - if (cmd->resp_type & MMC_RSP_136) { - u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76); - u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54); - u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32); - u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); - - cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | - ((rsp_103_72 & 0xff000000) >> 24); - cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | - ((rsp_71_40 & 0xff000000) >> 24); - cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | - ((rsp_39_8 & 0xff000000) >> 24); - cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; - } else { - /* bit 39-8 */ - cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); - } - - if (data) { - /* use DMA if the HW supports it and the buffer is aligned */ - if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL && - uniphier_sd_addr_is_dmaable((long)data->src)) - ret = uniphier_sd_dma_xfer(dev, data); - else - ret = uniphier_sd_pio_xfer(dev, data); - - ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, - UNIPHIER_SD_INFO1_CMP); - if (ret) - return ret; - } - - return ret; -} - -static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, - struct mmc *mmc) -{ - u32 val, tmp; - - switch (mmc->bus_width) { - case 1: - val = UNIPHIER_SD_OPTION_WIDTH_1; - break; - case 4: - val = UNIPHIER_SD_OPTION_WIDTH_4; - break; - case 8: - val = UNIPHIER_SD_OPTION_WIDTH_8; - break; - default: - return -EINVAL; - } - - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION); - tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; - tmp |= val; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION); - - return 0; -} - -static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, - struct mmc *mmc) -{ - u32 tmp; - - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE); - if (mmc->ddr_mode) - tmp |= UNIPHIER_SD_IF_MODE_DDR; - else - tmp &= ~UNIPHIER_SD_IF_MODE_DDR; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE); -} - -static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, - struct mmc *mmc) -{ - unsigned int divisor; - u32 val, tmp; - - if (!mmc->clock) - return; - - divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); - - if (divisor <= 1) - val = UNIPHIER_SD_CLKCTL_DIV1; - else if (divisor <= 2) - val = UNIPHIER_SD_CLKCTL_DIV2; - else if (divisor <= 4) - val = UNIPHIER_SD_CLKCTL_DIV4; - else if (divisor <= 8) - val = UNIPHIER_SD_CLKCTL_DIV8; - else if (divisor <= 16) - val = UNIPHIER_SD_CLKCTL_DIV16; - else if (divisor <= 32) - val = UNIPHIER_SD_CLKCTL_DIV32; - else if (divisor <= 64) - val = UNIPHIER_SD_CLKCTL_DIV64; - else if (divisor <= 128) - val = UNIPHIER_SD_CLKCTL_DIV128; - else if (divisor <= 256) - val = UNIPHIER_SD_CLKCTL_DIV256; - else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024)) - val = UNIPHIER_SD_CLKCTL_DIV512; - else - val = UNIPHIER_SD_CLKCTL_DIV1024; - - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL); - if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN && - (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val) - return; - - /* stop the clock before changing its rate to avoid a glitch signal */ - tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); - - tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; - tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); - - tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); - - udelay(1000); -} - -static int uniphier_sd_set_ios(struct udevice *dev) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - struct mmc *mmc = mmc_get_mmc_dev(dev); - int ret; - - dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", - mmc->clock, mmc->ddr_mode, mmc->bus_width); - - ret = uniphier_sd_set_bus_width(priv, mmc); - if (ret) - return ret; - uniphier_sd_set_ddr_mode(priv, mmc); - uniphier_sd_set_clk_rate(priv, mmc); - - return 0; -} - -static int uniphier_sd_get_cd(struct udevice *dev) -{ - struct uniphier_sd_priv *priv = dev_get_priv(dev); - - if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) - return 1; - - return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) & - UNIPHIER_SD_INFO1_CD); -} +#include "tmio-common.h" static const struct dm_mmc_ops uniphier_sd_ops = { - .send_cmd = uniphier_sd_send_cmd, - .set_ios = uniphier_sd_set_ios, - .get_cd = uniphier_sd_get_cd, + .send_cmd = tmio_sd_send_cmd, + .set_ios = tmio_sd_set_ios, + .get_cd = tmio_sd_get_cd, }; -static void uniphier_sd_host_init(struct uniphier_sd_priv *priv) -{ - u32 tmp; - - /* soft reset of the host */ - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST); - tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); - tmp |= UNIPHIER_SD_SOFT_RST_RSTX; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); - - /* FIXME: implement eMMC hw_reset */ - - uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP); - - /* - * Connected to 32bit AXI. - * This register dropped backward compatibility at version 0x10. - * Write an appropriate value depending on the IP version. - */ - uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000, - UNIPHIER_SD_HOST_MODE); - - if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { - tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); - tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; - uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); - } -} - -static int uniphier_sd_bind(struct udevice *dev) -{ - struct uniphier_sd_plat *plat = dev_get_platdata(dev); - - return mmc_bind(dev, &plat->mmc, &plat->cfg); -} +static const struct udevice_id uniphier_sd_match[] = { + { .compatible = "socionext,uniphier-sdhc", .data = 0 }, + { /* sentinel */ } +}; static int uniphier_sd_probe(struct udevice *dev) { - struct uniphier_sd_plat *plat = dev_get_platdata(dev); - struct uniphier_sd_priv *priv = dev_get_priv(dev); - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - const u32 quirks = dev_get_driver_data(dev); - fdt_addr_t base; + struct tmio_sd_priv *priv = dev_get_priv(dev); +#ifndef CONFIG_SPL_BUILD struct clk clk; int ret; -#ifdef CONFIG_DM_REGULATOR - struct udevice *vqmmc_dev; -#endif - - base = devfdt_get_addr(dev); - if (base == FDT_ADDR_T_NONE) - return -EINVAL; - - priv->regbase = devm_ioremap(dev, base, SZ_2K); - if (!priv->regbase) - return -ENOMEM; - -#ifdef CONFIG_DM_REGULATOR - ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); - if (!ret) { - /* Set the regulator to 3.3V until we support 1.8V modes */ - regulator_set_value(vqmmc_dev, 3300000); - regulator_set_enable(vqmmc_dev, true); - } -#endif ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) { @@ -798,76 +57,20 @@ static int uniphier_sd_probe(struct udevice *dev) dev_err(dev, "failed to enable host clock\n"); return ret; } +#else + priv->mclk = 100000000; +#endif - plat->cfg.name = dev->name; - plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; - - switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", - 1)) { - case 8: - plat->cfg.host_caps |= MMC_MODE_8BIT; - break; - case 4: - plat->cfg.host_caps |= MMC_MODE_4BIT; - break; - case 1: - break; - default: - dev_err(dev, "Invalid \"bus-width\" value\n"); - return -EINVAL; - } - - if (quirks) { - priv->caps = quirks; - } else { - priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) & - UNIPHIER_SD_VERSION_IP; - dev_dbg(dev, "version %x\n", priv->version); - if (priv->version >= 0x10) { - priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL; - priv->caps |= UNIPHIER_SD_CAP_DIV1024; - } - } - - if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", - NULL)) - priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; - - uniphier_sd_host_init(priv); - - plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; - plat->cfg.f_min = priv->mclk / - (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512); - plat->cfg.f_max = priv->mclk; - plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */ - - upriv->mmc = &plat->mmc; - - return 0; + return tmio_sd_probe(dev, 0); } -static const struct udevice_id uniphier_sd_match[] = { - { .compatible = "renesas,sdhi-r8a7790", .data = 0 }, - { .compatible = "renesas,sdhi-r8a7791", .data = 0 }, - { .compatible = "renesas,sdhi-r8a7792", .data = 0 }, - { .compatible = "renesas,sdhi-r8a7793", .data = 0 }, - { .compatible = "renesas,sdhi-r8a7794", .data = 0 }, - { .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT }, - { .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT }, - { .compatible = "renesas,sdhi-r8a77965", .data = UNIPHIER_SD_CAP_64BIT }, - { .compatible = "renesas,sdhi-r8a77970", .data = UNIPHIER_SD_CAP_64BIT }, - { .compatible = "renesas,sdhi-r8a77995", .data = UNIPHIER_SD_CAP_64BIT }, - { .compatible = "socionext,uniphier-sdhc", .data = 0 }, - { /* sentinel */ } -}; - U_BOOT_DRIVER(uniphier_mmc) = { .name = "uniphier-mmc", .id = UCLASS_MMC, .of_match = uniphier_sd_match, - .bind = uniphier_sd_bind, + .bind = tmio_sd_bind, .probe = uniphier_sd_probe, - .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv), - .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat), + .priv_auto_alloc_size = sizeof(struct tmio_sd_priv), + .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat), .ops = &uniphier_sd_ops, }; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 19579801d2..707359dca1 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -40,6 +40,13 @@ config FLASH_PIC32 This enables access to Microchip PIC32 internal non-CFI flash chips through PIC32 Non-Volatile-Memory Controller. +config RENESAS_RPC_HF + bool "Renesas RCar Gen3 RPC Hyperflash driver" + depends on RCAR_GEN3 && MTD + help + This enables access to Hyperflash memory through the Renesas + RCar Gen3 RPC controller. + endmenu source "drivers/mtd/nand/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 20c0d0af44..e46cbd8837 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o obj-$(CONFIG_ST_SMI) += st_smi.o obj-$(CONFIG_STM32_FLASH) += stm32_flash.o +obj-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index da44e6184e..e5509fe353 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -2461,27 +2461,28 @@ unsigned long flash_init(void) #ifdef CONFIG_CFI_FLASH /* for driver model */ static int cfi_flash_probe(struct udevice *dev) { - void *blob = (void *)gd->fdt_blob; - int node = dev_of_offset(dev); const fdt32_t *cell; - phys_addr_t addr; - int parent, addrc, sizec; + int addrc, sizec; int len, idx; - parent = fdt_parent_offset(blob, node); - fdt_support_default_count_cells(blob, parent, &addrc, &sizec); - /* decode regs, there may be multiple reg tuples. */ - cell = fdt_getprop(blob, node, "reg", &len); + addrc = dev_read_addr_cells(dev); + sizec = dev_read_size_cells(dev); + + /* decode regs; there may be multiple reg tuples. */ + cell = dev_read_prop(dev, "reg", &len); if (!cell) return -ENOENT; idx = 0; len /= sizeof(fdt32_t); while (idx < len) { - addr = fdt_translate_address((void *)blob, - node, cell + idx); + phys_addr_t addr; + + addr = dev_translate_address(dev, cell + idx); + flash_info[cfi_flash_num_flash_banks].dev = dev; flash_info[cfi_flash_num_flash_banks].base = addr; cfi_flash_num_flash_banks++; + idx += addrc + sizec; } gd->bd->bi_flashstart = flash_info[0].base; diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c index 9c82c7db33..3be66efb73 100644 --- a/drivers/mtd/nand/arasan_nfc.c +++ b/drivers/mtd/nand/arasan_nfc.c @@ -86,7 +86,7 @@ struct arasan_nand_command_format { #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28 -#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF +#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF @@ -796,7 +796,7 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, writel(reg_val, &arasan_nand_base->cmd_reg); page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & - ARASAN_NAND_MEM_ADDR1_PAGE_MASK; + ARASAN_NAND_MEM_ADDR1_COL_MASK; column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK; writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT), &arasan_nand_base->memadr_reg1); diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c index 6494196049..2d4e8b4736 100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@ -1006,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd) return 0; } -int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) { struct zynq_nand_info *xnand; struct mtd_info *mtd; @@ -1025,7 +1025,7 @@ int zynq_nand_init(struct nand_chip *nand_chip, int devnum) } xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR; - mtd = get_nand_dev_by_index(0); + mtd = nand_to_mtd(nand_chip); nand_chip->priv = xnand; mtd->priv = nand_chip; @@ -1192,14 +1192,12 @@ fail: return err; } -#ifdef CONFIG_SYS_NAND_SELF_INIT static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -void __weak board_nand_init(void) +void board_nand_init(void) { struct nand_chip *nand = &nand_chip[0]; if (zynq_nand_init(nand, 0)) puts("ZYNQ NAND init failed\n"); } -#endif diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c new file mode 100644 index 0000000000..1ba6e354a0 --- /dev/null +++ b/drivers/mtd/renesas_rpc_hf.c @@ -0,0 +1,398 @@ +/* + * Renesas RCar Gen3 RPC Hyperflash driver + * + * Copyright (C) 2016 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc. + * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/of_access.h> +#include <errno.h> +#include <fdt_support.h> +#include <flash.h> +#include <mtd.h> +#include <wait_bit.h> +#include <mtd/cfi_flash.h> + +#define RPC_CMNCR 0x0000 /* R/W */ +#define RPC_CMNCR_MD BIT(31) +#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) +#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) +#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) +#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) +#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \ + RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3)) +#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8) +#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) +#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) +#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \ + RPC_CMNCR_IO3FV(3)) +#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0) + +#define RPC_SSLDR 0x0004 /* R/W */ +#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16) +#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8) +#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0) + +#define RPC_DRCR 0x000C /* R/W */ +#define RPC_DRCR_SSLN BIT(24) +#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) +#define RPC_DRCR_RCF BIT(9) +#define RPC_DRCR_RBE BIT(8) +#define RPC_DRCR_SSLE BIT(0) + +#define RPC_DRCMR 0x0010 /* R/W */ +#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16) +#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0) + +#define RPC_DREAR 0x0014 /* R/W */ +#define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16) +#define RPC_DREAR_EAC(v) (((v) & 0x7) << 0) + +#define RPC_DROPR 0x0018 /* R/W */ +#define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24) +#define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16) +#define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8) +#define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0) + +#define RPC_DRENR 0x001C /* R/W */ +#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) +#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28) +#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24) +#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20) +#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16) +#define RPC_DRENR_DME BIT(15) +#define RPC_DRENR_CDE BIT(14) +#define RPC_DRENR_OCDE BIT(12) +#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8) +#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4) + +#define RPC_SMCR 0x0020 /* R/W */ +#define RPC_SMCR_SSLKP BIT(8) +#define RPC_SMCR_SPIRE BIT(2) +#define RPC_SMCR_SPIWE BIT(1) +#define RPC_SMCR_SPIE BIT(0) + +#define RPC_SMCMR 0x0024 /* R/W */ +#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16) +#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0) + +#define RPC_SMADR 0x0028 /* R/W */ +#define RPC_SMOPR 0x002C /* R/W */ +#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0) +#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8) +#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16) +#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24) + +#define RPC_SMENR 0x0030 /* R/W */ +#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30) +#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28) +#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24) +#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20) +#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16) +#define RPC_SMENR_DME BIT(15) +#define RPC_SMENR_CDE BIT(14) +#define RPC_SMENR_OCDE BIT(12) +#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8) +#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4) +#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0) + +#define RPC_SMRDR0 0x0038 /* R */ +#define RPC_SMRDR1 0x003C /* R */ +#define RPC_SMWDR0 0x0040 /* R/W */ +#define RPC_SMWDR1 0x0044 /* R/W */ +#define RPC_CMNSR 0x0048 /* R */ +#define RPC_CMNSR_SSLF BIT(1) +#define RPC_CMNSR_TEND BIT(0) + +#define RPC_DRDMCR 0x0058 /* R/W */ +#define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0) + +#define RPC_DRDRENR 0x005C /* R/W */ +#define RPC_DRDRENR_HYPE (0x5 << 12) +#define RPC_DRDRENR_ADDRE BIT(8) +#define RPC_DRDRENR_OPDRE BIT(4) +#define RPC_DRDRENR_DRDRE BIT(0) + +#define RPC_SMDMCR 0x0060 /* R/W */ +#define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0) + +#define RPC_SMDRENR 0x0064 /* R/W */ +#define RPC_SMDRENR_HYPE (0x5 << 12) +#define RPC_SMDRENR_ADDRE BIT(8) +#define RPC_SMDRENR_OPDRE BIT(4) +#define RPC_SMDRENR_SPIDRE BIT(0) + +#define RPC_PHYCNT 0x007C /* R/W */ +#define RPC_PHYCNT_CAL BIT(31) +#define PRC_PHYCNT_OCTA_AA BIT(22) +#define PRC_PHYCNT_OCTA_SA BIT(23) +#define PRC_PHYCNT_EXDS BIT(21) +#define RPC_PHYCNT_OCT BIT(20) +#define RPC_PHYCNT_WBUF2 BIT(4) +#define RPC_PHYCNT_WBUF BIT(2) +#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) + +#define RPC_PHYINT 0x0088 /* R/W */ +#define RPC_PHYINT_RSTEN BIT(18) +#define RPC_PHYINT_WPEN BIT(17) +#define RPC_PHYINT_INTEN BIT(16) +#define RPC_PHYINT_RST BIT(2) +#define RPC_PHYINT_WP BIT(1) +#define RPC_PHYINT_INT BIT(0) + +#define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */ +#define RPC_WBUF_SIZE 0x100 + +static phys_addr_t rpc_base; + +enum rpc_hf_size { + RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8), + RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC), + RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF), +}; + +static int rpc_hf_wait_tend(void) +{ + void __iomem *reg = (void __iomem *)rpc_base + RPC_CMNSR; + return wait_for_bit_le32(reg, RPC_CMNSR_TEND, true, 1000, 0); +} + +static int rpc_hf_mode(bool man) +{ + int ret; + + ret = rpc_hf_wait_tend(); + if (ret) + return ret; + + clrsetbits_le32(rpc_base + RPC_PHYCNT, + RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 | + RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3), + RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)); + + clrsetbits_le32(rpc_base + RPC_CMNCR, + RPC_CMNCR_MD | RPC_CMNCR_BSZ(3), + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | + (man ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1)); + + if (man) + return 0; + + writel(RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE, + rpc_base + RPC_DRCR); + + writel(RPC_DRCMR_CMD(0xA0), rpc_base + RPC_DRCMR); + writel(RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | RPC_DRENR_ADB(2) | + RPC_DRENR_SPIDB(2) | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE(4), rpc_base + RPC_DRENR); + writel(RPC_DRDMCR_DMCYC(0xE), rpc_base + RPC_DRDMCR); + writel(RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE, + rpc_base + RPC_DRDRENR); + + /* Dummy read */ + readl(rpc_base + RPC_DRCR); + + return 0; +} + +static int rpc_hf_xfer(void *addr, u64 wdata, u64 *rdata, + enum rpc_hf_size size, bool write) +{ + int ret; + u32 val; + + ret = rpc_hf_mode(1); + if (ret) + return ret; + + /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */ + writel(write ? 0 : RPC_SMCMR_CMD(0x80), rpc_base + RPC_SMCMR); + writel((uintptr_t)addr >> 1, rpc_base + RPC_SMADR); + writel(0x0, rpc_base + RPC_SMOPR); + + writel(RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE, + rpc_base + RPC_SMDRENR); + + val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) | + RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) | + RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size; + + if (write) { + writel(val, rpc_base + RPC_SMENR); + + if (size == RPC_HF_SIZE_64BIT) + writeq(cpu_to_be64(wdata), rpc_base + RPC_SMWDR0); + else + writel(cpu_to_be32(wdata), rpc_base + RPC_SMWDR0); + + writel(RPC_SMCR_SPIWE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR); + } else { + val |= RPC_SMENR_DME; + + writel(RPC_SMDMCR_DMCYC(0xE), rpc_base + RPC_SMDMCR); + + writel(val, rpc_base + RPC_SMENR); + + writel(RPC_SMCR_SPIRE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR); + + ret = rpc_hf_wait_tend(); + if (ret) + return ret; + + if (size == RPC_HF_SIZE_64BIT) + *rdata = be64_to_cpu(readq(rpc_base + RPC_SMRDR0)); + else + *rdata = be32_to_cpu(readl(rpc_base + RPC_SMRDR0)); + } + + return rpc_hf_mode(0); +} + +static void rpc_hf_write_cmd(void *addr, u64 wdata, enum rpc_hf_size size) +{ + int ret; + + ret = rpc_hf_xfer(addr, wdata, NULL, size, 1); + if (ret) + printf("RPC: Write failed, ret=%i\n", ret); +} + +static u64 rpc_hf_read_reg(void *addr, enum rpc_hf_size size) +{ + u64 rdata = 0; + int ret; + + ret = rpc_hf_xfer(addr, 0, &rdata, size, 0); + if (ret) + printf("RPC: Read failed, ret=%i\n", ret); + + return rdata; +} + +void flash_write8(u8 value, void *addr) +{ + rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT); +} + +void flash_write16(u16 value, void *addr) +{ + rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT); +} + +void flash_write32(u32 value, void *addr) +{ + rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_32BIT); +} + +void flash_write64(u64 value, void *addr) +{ + rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_64BIT); +} + +u8 flash_read8(void *addr) +{ + return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT); +} + +u16 flash_read16(void *addr) +{ + return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT); +} + +u32 flash_read32(void *addr) +{ + return rpc_hf_read_reg(addr, RPC_HF_SIZE_32BIT); +} + +u64 flash_read64(void *addr) +{ + return rpc_hf_read_reg(addr, RPC_HF_SIZE_64BIT); +} + +static int rpc_hf_bind(struct udevice *parent) +{ + const void *fdt = gd->fdt_blob; + ofnode node; + int ret, off; + + /* + * Check if there are any SPI NOR child nodes, if so, do NOT bind + * as this controller will be operated by the QSPI driver instead. + */ + dev_for_each_subnode(node, parent) { + off = ofnode_to_offset(node); + + ret = fdt_node_check_compatible(fdt, off, "spi-flash"); + if (!ret) + return -ENODEV; + + ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor"); + if (!ret) + return -ENODEV; + } + + return 0; +} + +static int rpc_hf_probe(struct udevice *dev) +{ + void *blob = (void *)gd->fdt_blob; + const fdt32_t *cell; + int node = dev_of_offset(dev); + int parent, addrc, sizec, len, ret; + struct clk clk; + phys_addr_t flash_base; + + parent = fdt_parent_offset(blob, node); + fdt_support_default_count_cells(blob, parent, &addrc, &sizec); + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) + return -ENOENT; + + if (addrc != 2 || sizec != 2) + return -EINVAL; + + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "Failed to get RPC clock\n"); + return ret; + } + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) { + dev_err(dev, "Failed to enable RPC clock\n"); + return ret; + } + + rpc_base = fdt_translate_address(blob, node, cell); + flash_base = fdt_translate_address(blob, node, cell + addrc + sizec); + + flash_info[0].dev = dev; + flash_info[0].base = flash_base; + cfi_flash_num_flash_banks = 1; + gd->bd->bi_flashstart = flash_base; + + return 0; +} + +static const struct udevice_id rpc_hf_ids[] = { + { .compatible = "renesas,rpc" }, + {} +}; + +U_BOOT_DRIVER(rpc_hf) = { + .name = "rpc_hf", + .id = UCLASS_MTD, + .of_match = rpc_hf_ids, + .bind = rpc_hf_bind, + .probe = rpc_hf_probe, +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f2cfcb0606..3a374d8871 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -11,6 +11,13 @@ config DM_ETH This is currently implemented in net/eth.c Look in include/net.h for details. +config DRIVER_TI_CPSW + bool "TI Common Platform Ethernet Switch" + select PHYLIB + help + This driver supports the TI three port switch gigabit ethernet + subsystem found in the TI SoCs. + menuconfig NETDEVICES bool "Network device support" depends on NET @@ -148,9 +155,20 @@ config ETHOC help This MAC is present in OpenRISC and Xtensa XTFPGA boards. +config FEC_MXC_SHARE_MDIO + bool "Share the MDIO bus for FEC controller" + depends on FEC_MXC + +config FEC_MXC_MDIO_BASE + hex "MDIO base address for the FEC controller" + depends on FEC_MXC_SHARE_MDIO + help + This specifies the MDIO registers base address. It is used when + two FEC controllers share MDIO bus. + config FEC_MXC bool "FEC Ethernet controller" - depends on MX5 || MX6 + depends on MX5 || MX6 || MX7 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/cpsw-common.c b/drivers/net/cpsw-common.c index 0dc83ab820..7bd312a6c0 100644 --- a/drivers/net/cpsw-common.c +++ b/drivers/net/cpsw-common.c @@ -8,6 +8,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <fdt_support.h> #include <asm/io.h> #include <cpsw.h> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ff7ad91116..0076d6323e 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -10,6 +10,7 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <malloc.h> #include <memalign.h> #include <miiphy.h> @@ -806,7 +807,16 @@ static int fec_recv(struct eth_device *dev) uint16_t bd_status; ulong addr, size, end; int i; + +#ifdef CONFIG_DM_ETH + *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE); + if (*packetp == 0) { + printf("%s: error allocating packetp\n", __func__); + return -ENOMEM; + } +#else ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); +#endif /* Check if any critical events have happened */ ievent = readl(&fec->eth->ievent); @@ -882,8 +892,13 @@ static int fec_recv(struct eth_device *dev) #ifdef CONFIG_FEC_MXC_SWAP_PACKET swap_packet((uint32_t *)addr, frame_length); #endif + +#ifdef CONFIG_DM_ETH + memcpy(*packetp, (char *)addr, frame_length); +#else memcpy(buff, (char *)addr, frame_length); net_process_received_packet(buff, frame_length); +#endif len = frame_length; } else { if (bd_status & FEC_RBD_ERR) @@ -997,18 +1012,9 @@ static void fec_free_descs(struct fec_priv *fec) free(fec->tbd_base); } -#ifdef CONFIG_DM_ETH -struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id) -#else -struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) -#endif +struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) { -#ifdef CONFIG_DM_ETH - struct fec_priv *priv = dev_get_priv(dev); - struct ethernet_regs *eth = priv->eth; -#else - struct ethernet_regs *eth = (struct ethernet_regs *)(ulong)base_addr; -#endif + struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; struct mii_dev *bus; int ret; @@ -1140,12 +1146,12 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) #endif int ret; -#ifdef CONFIG_MX28 +#ifdef CONFIG_FEC_MXC_MDIO_BASE /* * The i.MX28 has two ethernet interfaces, but they are not equal. * Only the first one can access the MDIO bus. */ - base_mii = MXS_ENET0_BASE; + base_mii = CONFIG_FEC_MXC_MDIO_BASE; #else base_mii = addr; #endif @@ -1201,10 +1207,19 @@ static int fecmxc_read_rom_hwaddr(struct udevice *dev) return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); } +static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + if (packet) + free(packet); + + return 0; +} + static const struct eth_ops fecmxc_ops = { .start = fecmxc_init, .send = fecmxc_send, .recv = fecmxc_recv, + .free_pkt = fecmxc_free_pkt, .stop = fecmxc_halt, .write_hwaddr = fecmxc_set_hwaddr, .read_rom_hwaddr = fecmxc_read_rom_hwaddr, @@ -1236,7 +1251,6 @@ static int fecmxc_probe(struct udevice *dev) struct eth_pdata *pdata = dev_get_platdata(dev); struct fec_priv *priv = dev_get_priv(dev); struct mii_dev *bus = NULL; - int dev_id = -1; uint32_t start; int ret; @@ -1257,9 +1271,13 @@ static int fecmxc_probe(struct udevice *dev) } fec_reg_setup(priv); - priv->dev_id = (dev_id == -1) ? 0 : dev_id; - bus = fec_get_miibus(dev, dev_id); + priv->dev_id = dev->seq; +#ifdef CONFIG_FEC_MXC_MDIO_BASE + bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq); +#else + bus = fec_get_miibus((ulong)priv->eth, dev->seq); +#endif if (!bus) { ret = -ENOMEM; goto err_mii; @@ -1274,12 +1292,11 @@ static int fecmxc_probe(struct udevice *dev) return 0; -err_timeout: - free(priv->phydev); err_phy: mdio_unregister(bus); free(bus); err_mii: +err_timeout: fec_free_descs(priv); return ret; } @@ -1325,6 +1342,9 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx6q-fec" }, + { .compatible = "fsl,imx6sl-fec" }, + { .compatible = "fsl,imx6sx-fec" }, + { .compatible = "fsl,imx6ul-fec" }, { } }; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 2d89cea4a3..00d905c299 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <malloc.h> #include <command.h> #include <config.h> diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index ebcbed941a..505a2d1bee 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <environment.h> #include <malloc.h> #include <command.h> diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 83e3153768..f2e9acfd1f 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -890,6 +890,15 @@ static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, mvneta_set_ucast_addr(pp, addr[5], queue); } +static int mvneta_write_hwaddr(struct udevice *dev) +{ + mvneta_mac_addr_set(dev_get_priv(dev), + ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr, + rxq_def); + + return 0; +} + /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, u32 phys_addr, u32 cookie) @@ -1753,6 +1762,7 @@ static const struct eth_ops mvneta_ops = { .send = mvneta_send, .recv = mvneta_recv, .stop = mvneta_stop, + .write_hwaddr = mvneta_write_hwaddr, }; static int mvneta_ofdata_to_platdata(struct udevice *dev) diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index fb088e06a4..421aa20ea6 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -74,6 +74,7 @@ Add SNMP #include <common.h> #include <command.h> +#include <environment.h> #include <net.h> #include <malloc.h> #include <linux/compiler.h> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 179e0418bc..f5821dfed9 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -13,12 +13,20 @@ menuconfig PHYLIB if PHYLIB +config PHY_ADDR_ENABLE + bool "Limit phy address" + default y if ARCH_SUNXI + help + Select this if you want to control which phy address is used + +if PHY_ADDR_ENABLE config PHY_ADDR int "PHY address" default 1 if ARCH_SUNXI default 0 help The address of PHY on MII bus. Usually in range of 0 to 31. +endif config B53_SWITCH bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support." diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c index 3f80f0495e..7142a99ce5 100644 --- a/drivers/net/phy/xilinx_phy.c +++ b/drivers/net/phy/xilinx_phy.c @@ -105,7 +105,7 @@ static int xilinxphy_of_init(struct phy_device *phydev) debug("%s\n", __func__); phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev), - "phy-type", -1); + "xlnx,phy-type", -1); if (phytype == XAE_PHY_TYPE_1000BASE_X) phydev->flags |= XAE_PHY_TYPE_1000BASE_X; diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 6f48e93ab5..cb3970e051 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -11,6 +11,7 @@ #include <config.h> #include <common.h> +#include <environment.h> #include <malloc.h> #include <net.h> #include <netdev.h> @@ -905,7 +906,10 @@ int sh_ether_ofdata_to_platdata(struct udevice *dev) } static const struct udevice_id sh_ether_ids[] = { + { .compatible = "renesas,ether-r8a7790" }, { .compatible = "renesas,ether-r8a7791" }, + { .compatible = "renesas,ether-r8a7793" }, + { .compatible = "renesas,ether-r8a7794" }, { } }; diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 70a2e95a8e..80ed06ac66 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -78,9 +78,10 @@ static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); struct axidma_reg { u32 control; /* DMACR */ u32 status; /* DMASR */ - u32 current; /* CURDESC */ - u32 reserved; - u32 tail; /* TAILDESC */ + u32 current; /* CURDESC low 32 bit */ + u32 current_hi; /* CURDESC high 32 bit */ + u32 tail; /* TAILDESC low 32 bit */ + u32 tail_hi; /* TAILDESC high 32 bit */ }; /* Private driver structures */ @@ -168,6 +169,22 @@ static inline int mdio_wait(struct axi_regs *regs) return 0; } +/** + * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write. + * @bd: pointer to BD descriptor structure + * @desc: Address offset of DMA descriptors + * + * This function writes the value into the corresponding Axi DMA register. + */ +static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc) +{ +#if defined(CONFIG_PHYS_64BIT) + writeq(bd, desc); +#else + writel((u32)bd, desc); +#endif +} + static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum, u16 *val) { @@ -465,7 +482,7 @@ static int axiemac_start(struct udevice *dev) writel(temp, &priv->dmarx->control); /* Start DMA RX channel. Now it's ready to receive data.*/ - writel((u32)&rx_bd, &priv->dmarx->current); + axienet_dma_write(&rx_bd, &priv->dmarx->current); /* Setup the BD. */ memset(&rx_bd, 0, sizeof(rx_bd)); @@ -485,7 +502,7 @@ static int axiemac_start(struct udevice *dev) writel(temp, &priv->dmarx->control); /* Rx BD is ready - start */ - writel((u32)&rx_bd, &priv->dmarx->tail); + axienet_dma_write(&rx_bd, &priv->dmarx->tail); /* Enable TX */ writel(XAE_TC_TX_MASK, ®s->tc); @@ -527,7 +544,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) { u32 temp; - writel((u32)&tx_bd, &priv->dmatx->current); + axienet_dma_write(&tx_bd, &priv->dmatx->current); /* Start the hardware */ temp = readl(&priv->dmatx->control); temp |= XAXIDMA_CR_RUNSTOP_MASK; @@ -535,7 +552,7 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) } /* Start transfer */ - writel((u32)&tx_bd, &priv->dmatx->tail); + axienet_dma_write(&tx_bd, &priv->dmatx->tail); /* Wait for transmission to complete */ debug("axiemac: Waiting for tx to be done\n"); @@ -626,7 +643,7 @@ static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length) flush_cache((u32)&rxframe, sizeof(rxframe)); /* Rx BD is ready - start again */ - writel((u32)&rx_bd, &priv->dmarx->tail); + axienet_dma_write(&rx_bd, &priv->dmarx->tail); debug("axiemac: RX completed, framelength = %d\n", length); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 1390c36c61..dd36a8c22a 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -182,6 +182,7 @@ struct zynq_gem_priv { int phy_of_handle; struct mii_dev *bus; struct clk clk; + u32 max_speed; bool int_pcs; }; @@ -341,6 +342,12 @@ static int zynq_phy_init(struct udevice *dev) priv->phydev->supported &= supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; + if (priv->max_speed) { + ret = phy_set_supported(priv->phydev, priv->max_speed); + if (ret) + return ret; + } + priv->phydev->advertising = priv->phydev->supported; if (priv->phy_of_handle > 0) @@ -704,6 +711,8 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) } priv->interface = pdata->phy_interface; + priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle, + "max-speed", SPEED_1000); priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node, "is-internal-pcspma"); diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 46fe5e6247..7f461943f8 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -355,8 +355,6 @@ int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void)) struct video_priv *uc_priv = dev_get_uclass_priv(dev); int ret; - printf("Video: "); - /* If we are running from EFI or coreboot, this can't work */ if (!ll_boot_init()) { printf("Not available (previous bootloader prevents it)\n"); @@ -377,7 +375,7 @@ int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void)) return ret; } - printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, + printf("Video: %dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, mode_info.vesa.bits_per_pixel); return 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4e9d09910c..119edec204 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -110,4 +110,12 @@ config STI_USB_PHY used by USB2 and USB3 Host controllers available on STiH407 SoC families. +config MESON_GXL_USB_PHY + bool "Amlogic Meson GXL USB PHYs" + depends on PHY && ARCH_MESON && MESON_GXL + imply REGMAP + help + This is the generic phy driver for the Amlogic Meson GXL + USB2 and USB3 PHYS. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 68087ae3b1..72c14921b0 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o +obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c new file mode 100644 index 0000000000..15c9c89fd9 --- /dev/null +++ b/drivers/phy/meson-gxl-usb2.c @@ -0,0 +1,238 @@ +/* + * Meson GXL and GXM USB2 PHY driver + * + * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstron@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <power/regulator.h> +#include <clk.h> + +#include <linux/bitops.h> +#include <linux/compat.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* bits [31:27] are read-only */ +#define U2P_R0 0x0 + #define U2P_R0_BYPASS_SEL BIT(0) + #define U2P_R0_BYPASS_DM_EN BIT(1) + #define U2P_R0_BYPASS_DP_EN BIT(2) + #define U2P_R0_TXBITSTUFF_ENH BIT(3) + #define U2P_R0_TXBITSTUFF_EN BIT(4) + #define U2P_R0_DM_PULLDOWN BIT(5) + #define U2P_R0_DP_PULLDOWN BIT(6) + #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7) + #define U2P_R0_DP_VBUS_VLD_EXT BIT(8) + #define U2P_R0_ADP_PRB_EN BIT(9) + #define U2P_R0_ADP_DISCHARGE BIT(10) + #define U2P_R0_ADP_CHARGE BIT(11) + #define U2P_R0_DRV_VBUS BIT(12) + #define U2P_R0_ID_PULLUP BIT(13) + #define U2P_R0_LOOPBACK_EN_B BIT(14) + #define U2P_R0_OTG_DISABLE BIT(15) + #define U2P_R0_COMMON_ONN BIT(16) + #define U2P_R0_FSEL_MASK GENMASK(19, 17) + #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20) + #define U2P_R0_POWER_ON_RESET BIT(22) + #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23) + #define U2P_R0_ID_SET_ID_DQ BIT(25) + #define U2P_R0_ATE_RESET BIT(26) + #define U2P_R0_FSV_MINUS BIT(27) + #define U2P_R0_FSV_PLUS BIT(28) + #define U2P_R0_BYPASS_DM_DATA BIT(29) + #define U2P_R0_BYPASS_DP_DATA BIT(30) + +#define U2P_R1 0x4 + #define U2P_R1_BURN_IN_TEST BIT(0) + #define U2P_R1_ACA_ENABLE BIT(1) + #define U2P_R1_DCD_ENABLE BIT(2) + #define U2P_R1_VDAT_SRC_EN_B BIT(3) + #define U2P_R1_VDAT_DET_EN_B BIT(4) + #define U2P_R1_CHARGES_SEL BIT(5) + #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6) + #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7) + #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9) + #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11) + #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13) + #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17) + #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21) + #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23) + #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26) + #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29) + +/* bits [31:14] are read-only */ +#define U2P_R2 0x8 + #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0) + #define U2P_R2_TESTADDR_MASK GENMASK(11, 8) + #define U2P_R2_TESTDATA_OUT_SEL BIT(12) + #define U2P_R2_TESTCLK BIT(13) + #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14) + #define U2P_R2_ACA_PIN_RANGE_C BIT(18) + #define U2P_R2_ACA_PIN_RANGE_B BIT(19) + #define U2P_R2_ACA_PIN_RANGE_A BIT(20) + #define U2P_R2_ACA_PIN_GND BIT(21) + #define U2P_R2_ACA_PIN_FLOAT BIT(22) + #define U2P_R2_CHARGE_DETECT BIT(23) + #define U2P_R2_DEVICE_SESSION_VALID BIT(24) + #define U2P_R2_ADP_PROBE BIT(25) + #define U2P_R2_ADP_SENSE BIT(26) + #define U2P_R2_SESSION_END BIT(27) + #define U2P_R2_VBUS_VALID BIT(28) + #define U2P_R2_B_VALID BIT(29) + #define U2P_R2_A_VALID BIT(30) + #define U2P_R2_ID_DIG BIT(31) + +#define U2P_R3 0xc + +#define RESET_COMPLETE_TIME 500 + +struct phy_meson_gxl_usb2_priv { + struct regmap *regmap; +#if CONFIG_IS_ENABLED(DM_REGULATOR) + struct udevice *phy_supply; +#endif +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +}; + +static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv) +{ + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + + /* reset the PHY and wait until settings are stabilized */ + val |= U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + udelay(RESET_COMPLETE_TIME); + + val &= ~U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + udelay(RESET_COMPLETE_TIME); +} + +static void +phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv) +{ + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + val |= U2P_R0_DM_PULLDOWN; + val |= U2P_R0_DP_PULLDOWN; + val &= ~U2P_R0_ID_PULLUP; + regmap_write(priv->regmap, U2P_R0, val); + + phy_meson_gxl_usb2_reset(priv); +} + +static int phy_meson_gxl_usb2_power_on(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + /* power on the PHY by taking it out of reset mode */ + val &= ~U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + + phy_meson_gxl_usb2_set_host_mode(priv); + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (priv->phy_supply) { + int ret = regulator_set_enable(priv->phy_supply, true); + if (ret) + return ret; + } +#endif + + return 0; +} + +static int phy_meson_gxl_usb2_power_off(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, U2P_R0, &val); + /* power off the PHY by putting it into reset mode */ + val |= U2P_R0_POWER_ON_RESET; + regmap_write(priv->regmap, U2P_R0, val); + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (priv->phy_supply) { + int ret = regulator_set_enable(priv->phy_supply, false); + if (ret) { + pr_err("Error disabling PHY supply\n"); + return ret; + } + } +#endif + + return 0; +} + +struct phy_ops meson_gxl_usb2_phy_ops = { + .power_on = phy_meson_gxl_usb2_power_on, + .power_off = phy_meson_gxl_usb2_power_off, +}; + +int meson_gxl_usb2_phy_probe(struct udevice *dev) +{ + struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem(dev, &priv->regmap); + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + pr_err("failed to enable PHY clock\n"); + clk_free(&priv->clk); + return ret; + } +#endif + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); + if (ret && ret != -ENOENT) { + pr_err("Failed to get PHY regulator\n"); + return ret; + } +#endif + + return 0; +} + +static const struct udevice_id meson_gxl_usb2_phy_ids[] = { + { .compatible = "amlogic,meson-gxl-usb2-phy" }, + { } +}; + +U_BOOT_DRIVER(meson_gxl_usb2_phy) = { + .name = "meson_gxl_usb2_phy", + .id = UCLASS_PHY, + .of_match = meson_gxl_usb2_phy_ids, + .probe = meson_gxl_usb2_phy_probe, + .ops = &meson_gxl_usb2_phy_ops, + .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv), +}; diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c new file mode 100644 index 0000000000..a385fbdf12 --- /dev/null +++ b/drivers/phy/meson-gxl-usb3.c @@ -0,0 +1,201 @@ +/* + * Meson GXL USB3 PHY driver + * + * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com> + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstron@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <clk.h> + +#include <linux/bitops.h> +#include <linux/compat.h> +#include <linux/bitfield.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define USB_R0 0x00 + #define USB_R0_P30_FSEL_MASK GENMASK(5, 0) + #define USB_R0_P30_PHY_RESET BIT(6) + #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7) + #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8) + #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9) + #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14) + #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17) + #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18) + #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19) + #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29) + #define USB_R0_U2D_ACT BIT(31) + +#define USB_R1 0x04 + #define USB_R1_U3H_BIGENDIAN_GS BIT(0) + #define USB_R1_U3H_PME_ENABLE BIT(1) + #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2) + #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7) + #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12) + #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16) + #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17) + #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18) + #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19) + #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25) + +#define USB_R2 0x08 + #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0) + #define USB_R2_P30_CR_READ BIT(16) + #define USB_R2_P30_CR_WRITE BIT(17) + #define USB_R2_P30_CR_CAP_ADDR BIT(18) + #define USB_R2_P30_CR_CAP_DATA BIT(19) + #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20) + #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26) + +#define USB_R3 0x0c + #define USB_R3_P30_SSC_ENABLE BIT(0) + #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1) + #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4) + #define USB_R3_P30_REF_SSP_EN BIT(13) + #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16) + #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19) + #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24) + +#define USB_R4 0x10 + #define USB_R4_P21_PORT_RESET_0 BIT(0) + #define USB_R4_P21_SLEEP_M0 BIT(1) + #define USB_R4_MEM_PD_MASK GENMASK(3, 2) + #define USB_R4_P21_ONLY BIT(4) + +#define USB_R5 0x14 + #define USB_R5_ID_DIG_SYNC BIT(0) + #define USB_R5_ID_DIG_REG BIT(1) + #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2) + #define USB_R5_ID_DIG_EN_0 BIT(4) + #define USB_R5_ID_DIG_EN_1 BIT(5) + #define USB_R5_ID_DIG_CURR BIT(6) + #define USB_R5_ID_DIG_IRQ BIT(7) + #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8) + #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16) + +/* read-only register */ +#define USB_R6 0x18 + #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0) + #define USB_R6_P30_CR_ACK BIT(16) + +struct phy_meson_gxl_usb3_priv { + struct regmap *regmap; +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; +#endif +}; + +static int +phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv) +{ + uint val; + + regmap_read(priv->regmap, USB_R0, &val); + val &= ~USB_R0_U2D_ACT; + regmap_write(priv->regmap, USB_R0, val); + + regmap_read(priv->regmap, USB_R4, &val); + val &= ~USB_R4_P21_SLEEP_M0; + regmap_write(priv->regmap, USB_R4, val); + + return 0; +} + +static int phy_meson_gxl_usb3_power_on(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, USB_R5, &val); + val |= USB_R5_ID_DIG_EN_0; + val |= USB_R5_ID_DIG_EN_1; + val &= ~USB_R5_ID_DIG_TH_MASK; + val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff); + regmap_write(priv->regmap, USB_R5, val); + + return phy_meson_gxl_usb3_set_host_mode(priv); +} + +static int phy_meson_gxl_usb3_power_off(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, USB_R5, &val); + val &= ~USB_R5_ID_DIG_EN_0; + val &= ~USB_R5_ID_DIG_EN_1; + regmap_write(priv->regmap, USB_R5, val); + + return 0; +} + +static int phy_meson_gxl_usb3_init(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + uint val; + + regmap_read(priv->regmap, USB_R1, &val); + val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK; + val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20); + regmap_write(priv->regmap, USB_R1, val); + + return 0; +} + +struct phy_ops meson_gxl_usb3_phy_ops = { + .init = phy_meson_gxl_usb3_init, + .power_on = phy_meson_gxl_usb3_power_on, + .power_off = phy_meson_gxl_usb3_power_off, +}; + +int meson_gxl_usb3_phy_probe(struct udevice *dev) +{ + struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem(dev, &priv->regmap); + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret < 0) + return ret; + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + pr_err("failed to enable PHY clock\n"); + clk_free(&priv->clk); + return ret; + } +#endif + + return 0; +} + +static const struct udevice_id meson_gxl_usb3_phy_ids[] = { + { .compatible = "amlogic,meson-gxl-usb3-phy" }, + { } +}; + +U_BOOT_DRIVER(meson_gxl_usb3_phy) = { + .name = "meson_gxl_usb3_phy", + .id = UCLASS_PHY, + .of_match = meson_gxl_usb3_phy_ids, + .probe = meson_gxl_usb3_phy_probe, + .ops = &meson_gxl_usb3_phy_ops, + .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv), +}; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71a786bab5..33c39b7fb6 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -83,4 +83,19 @@ config RESET_ROCKCHIP though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_MESON + bool "Reset controller driver for Amlogic Meson SoCs" + depends on DM_RESET && ARCH_MESON + imply REGMAP + default y + help + Support for reset controller on Amlogic Meson SoC. + +config RESET_SOCFPGA + bool "Reset controller driver for SoCFPGA" + depends on DM_RESET && ARCH_SOCFPGA + default y + help + Support for reset controller on SoCFPGA platform. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 7d7e080c78..ad08be4c8c 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -13,3 +13,5 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o +obj-$(CONFIG_RESET_MESON) += reset-meson.o +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c new file mode 100644 index 0000000000..5324f86f5f --- /dev/null +++ b/drivers/reset/reset-meson.c @@ -0,0 +1,90 @@ +/* + * Amlogic Meson Reset Controller driver + * + * Copyright (c) 2018 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <reset-uclass.h> +#include <regmap.h> + +#define REG_COUNT 8 +#define BITS_PER_REG 32 +#define LEVEL_OFFSET 0x7c + +struct meson_reset_priv { + struct regmap *regmap; +}; + +static int meson_reset_request(struct reset_ctl *reset_ctl) +{ + if (reset_ctl->id > (REG_COUNT * BITS_PER_REG)) + return -EINVAL; + + return 0; +} + +static int meson_reset_free(struct reset_ctl *reset_ctl) +{ + return 0; +} + +static int meson_reset_level(struct reset_ctl *reset_ctl, bool assert) +{ + struct meson_reset_priv *priv = dev_get_priv(reset_ctl->dev); + uint bank = reset_ctl->id / BITS_PER_REG; + uint offset = reset_ctl->id % BITS_PER_REG; + uint reg_offset = LEVEL_OFFSET + (bank << 2); + uint val; + + regmap_read(priv->regmap, reg_offset, &val); + if (assert) + val &= ~BIT(offset); + else + val |= BIT(offset); + regmap_write(priv->regmap, reg_offset, val); + + return 0; +} + +static int meson_reset_assert(struct reset_ctl *reset_ctl) +{ + return meson_reset_level(reset_ctl, true); +} + +static int meson_reset_deassert(struct reset_ctl *reset_ctl) +{ + return meson_reset_level(reset_ctl, false); +} + +struct reset_ops meson_reset_ops = { + .request = meson_reset_request, + .free = meson_reset_free, + .rst_assert = meson_reset_assert, + .rst_deassert = meson_reset_deassert, +}; + +static const struct udevice_id meson_reset_ids[] = { + { .compatible = "amlogic,meson-gxbb-reset" }, + { } +}; + +static int meson_reset_probe(struct udevice *dev) +{ + struct meson_reset_priv *priv = dev_get_priv(dev); + + return regmap_init_mem(dev, &priv->regmap); +} + +U_BOOT_DRIVER(meson_reset) = { + .name = "meson_reset", + .id = UCLASS_RESET, + .of_match = meson_reset_ids, + .probe = meson_reset_probe, + .ops = &meson_reset_ops, + .priv_auto_alloc_size = sizeof(struct meson_reset_priv), +}; diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c new file mode 100644 index 0000000000..466455d073 --- /dev/null +++ b/drivers/reset/reset-socfpga.c @@ -0,0 +1,105 @@ +/* + * Socfpga Reset Controller Driver + * + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * based on + * Allwinner SoCs Reset Controller driver + * + * Copyright 2013 Maxime Ripard + * + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/of_access.h> +#include <reset-uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define BANK_INCREMENT 4 +#define NR_BANKS 8 + +struct socfpga_reset_data { + void __iomem *membase; +}; + +static int socfpga_reset_assert(struct reset_ctl *reset_ctl) +{ + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); + int id = reset_ctl->id; + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + + setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + return 0; +} + +static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); + int id = reset_ctl->id; + int reg_width = sizeof(u32); + int bank = id / (reg_width * BITS_PER_BYTE); + int offset = id % (reg_width * BITS_PER_BYTE); + + clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); + return 0; +} + +static int socfpga_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int socfpga_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static const struct reset_ops socfpga_reset_ops = { + .request = socfpga_reset_request, + .free = socfpga_reset_free, + .rst_assert = socfpga_reset_assert, + .rst_deassert = socfpga_reset_deassert, +}; + +static int socfpga_reset_probe(struct udevice *dev) +{ + struct socfpga_reset_data *data = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + u32 modrst_offset; + + data->membase = devfdt_get_addr_ptr(dev); + + modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10); + data->membase += modrst_offset; + + return 0; +} + +static const struct udevice_id socfpga_reset_match[] = { + { .compatible = "altr,rst-mgr" }, + { /* sentinel */ }, +}; + +U_BOOT_DRIVER(socfpga_reset) = { + .name = "socfpga-reset", + .id = UCLASS_RESET, + .of_match = socfpga_reset_match, + .probe = socfpga_reset_probe, + .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), + .ops = &socfpga_reset_ops, +}; diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 307a29705f..fa4f6538ed 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -81,6 +81,40 @@ int reset_get_by_index(struct udevice *dev, int index, return 0; } +int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) +{ + int i, ret, err, count; + + bulk->count = 0; + + count = dev_count_phandle_with_args(dev, "resets", "#reset-cells"); + if (count < 1) + return count; + + bulk->resets = devm_kcalloc(dev, count, sizeof(struct reset_ctl), + GFP_KERNEL); + if (!bulk->resets) + return -ENOMEM; + + for (i = 0; i < count; i++) { + ret = reset_get_by_index(dev, i, &bulk->resets[i]); + if (ret < 0) + goto bulk_get_err; + + ++bulk->count; + } + + return 0; + +bulk_get_err: + err = reset_release_all(bulk->resets, bulk->count); + if (err) + debug("%s: could release all resets for %p\n", + __func__, dev); + + return ret; +} + int reset_get_by_name(struct udevice *dev, const char *name, struct reset_ctl *reset_ctl) { @@ -126,6 +160,19 @@ int reset_assert(struct reset_ctl *reset_ctl) return ops->rst_assert(reset_ctl); } +int reset_assert_bulk(struct reset_ctl_bulk *bulk) +{ + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = reset_assert(&bulk->resets[i]); + if (ret < 0) + return ret; + } + + return 0; +} + int reset_deassert(struct reset_ctl *reset_ctl) { struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); @@ -135,6 +182,19 @@ int reset_deassert(struct reset_ctl *reset_ctl) return ops->rst_deassert(reset_ctl); } +int reset_deassert_bulk(struct reset_ctl_bulk *bulk) +{ + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = reset_deassert(&bulk->resets[i]); + if (ret < 0) + return ret; + } + + return 0; +} + int reset_release_all(struct reset_ctl *reset_ctl, int count) { int i, ret; diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index a40cea55ae..e7a7da7fa9 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -43,6 +43,7 @@ struct uniphier_reset_data { /* System reset data */ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ + UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */ UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ @@ -52,6 +53,7 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ + UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */ UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ @@ -68,6 +70,7 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(6, 0x200c, 6), /* ETHER */ UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */ UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ @@ -80,6 +83,8 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(6, 0x200c, 9), /* ETHER0 */ + UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */ UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */ UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */ diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c index e37d6c91ef..f0ceaa0483 100644 --- a/drivers/reset/sandbox-reset-test.c +++ b/drivers/reset/sandbox-reset-test.c @@ -12,6 +12,7 @@ struct sandbox_reset_test { struct reset_ctl ctl; + struct reset_ctl_bulk bulk; }; int sandbox_reset_test_get(struct udevice *dev) @@ -21,6 +22,13 @@ int sandbox_reset_test_get(struct udevice *dev) return reset_get_by_name(dev, "test", &sbrt->ctl); } +int sandbox_reset_test_get_bulk(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_get_bulk(dev, &sbrt->bulk); +} + int sandbox_reset_test_assert(struct udevice *dev) { struct sandbox_reset_test *sbrt = dev_get_priv(dev); @@ -28,6 +36,13 @@ int sandbox_reset_test_assert(struct udevice *dev) return reset_assert(&sbrt->ctl); } +int sandbox_reset_test_assert_bulk(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_assert_bulk(&sbrt->bulk); +} + int sandbox_reset_test_deassert(struct udevice *dev) { struct sandbox_reset_test *sbrt = dev_get_priv(dev); @@ -35,6 +50,13 @@ int sandbox_reset_test_deassert(struct udevice *dev) return reset_deassert(&sbrt->ctl); } +int sandbox_reset_test_deassert_bulk(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_deassert_bulk(&sbrt->bulk); +} + int sandbox_reset_test_free(struct udevice *dev) { struct sandbox_reset_test *sbrt = dev_get_priv(dev); @@ -42,6 +64,13 @@ int sandbox_reset_test_free(struct udevice *dev) return reset_free(&sbrt->ctl); } +int sandbox_reset_test_release_bulk(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_release_bulk(&sbrt->bulk); +} + static const struct udevice_id sandbox_reset_test_ids[] = { { .compatible = "sandbox,reset-ctl-test" }, { } diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c index 4258af521b..c310749dc8 100644 --- a/drivers/reset/sandbox-reset.c +++ b/drivers/reset/sandbox-reset.c @@ -10,7 +10,7 @@ #include <asm/io.h> #include <asm/reset.h> -#define SANDBOX_RESET_SIGNALS 3 +#define SANDBOX_RESET_SIGNALS 101 struct sandbox_reset_signal { bool asserted; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index cac9a8b312..16609edf4b 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -5,11 +5,27 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD + +ifeq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)DM_SERIAL),yy) +obj-y += serial-uclass.o +else +obj-y += serial.o +endif + +else + ifdef CONFIG_DM_SERIAL -obj-$(CONFIG_$(SPL_TPL_)DM_SERIAL) += serial-uclass.o -obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o +obj-y += serial-uclass.o else obj-y += serial.o +endif + +endif + +ifdef CONFIG_DM_SERIAL +obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o +else obj-$(CONFIG_PL010_SERIAL) += serial_pl01x.o obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o @@ -44,7 +60,6 @@ obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o -obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o obj-$(CONFIG_BCM283X_PL011_SERIAL) += serial_bcm283x_pl011.o obj-$(CONFIG_MSM_SERIAL) += serial_msm.o diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c index 363affb8c5..6412ca6496 100644 --- a/drivers/serial/serial_meson.c +++ b/drivers/serial/serial_meson.c @@ -125,6 +125,7 @@ static const struct dm_serial_ops meson_serial_ops = { static const struct udevice_id meson_serial_ids[] = { { .compatible = "amlogic,meson-uart" }, + { .compatible = "amlogic,meson-gx-uart" }, { } }; diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index a17698f90e..5f4ace7848 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -270,6 +270,8 @@ U_BOOT_DRIVER(serial_sh) = { # define SCIF_BASE SCIF6_BASE #elif defined(CONFIG_CONS_SCIF7) # define SCIF_BASE SCIF7_BASE +#elif defined(CONFIG_CONS_SCIFA0) +# define SCIF_BASE SCIFA0_BASE #else # error "Default SCIF doesn't set....." #endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d3e407ec11..ec92b84ed2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -114,6 +114,14 @@ config PIC32_SPI to access the SPI NOR flash, MMC-over-SPI on platforms based on Microchip PIC32 family devices. +config RENESAS_RPC_SPI + bool "Renesas RPC SPI driver" + depends on RCAR_GEN3 + help + Enable the Renesas RPC SPI driver, used to access SPI NOR flash + on Renesas RCar Gen3 SoCs. This uses driver model and requires a + device tree binding to operate. + config ROCKCHIP_SPI bool "Rockchip SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b6000fd9a..176bfa05cf 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o obj-$(CONFIG_PIC32_SPI) += pic32_spi.o +obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c new file mode 100644 index 0000000000..e54f24c5d8 --- /dev/null +++ b/drivers/spi/renesas_rpc_spi.c @@ -0,0 +1,465 @@ +/* + * Renesas RCar Gen3 RPC QSPI driver + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/of_access.h> +#include <dt-structs.h> +#include <errno.h> +#include <linux/errno.h> +#include <spi.h> +#include <wait_bit.h> + +#define RPC_CMNCR 0x0000 /* R/W */ +#define RPC_CMNCR_MD BIT(31) +#define RPC_CMNCR_SFDE BIT(24) +#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) +#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) +#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) +#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) +#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \ + RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3)) +#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) +#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) +#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8) +#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \ + RPC_CMNCR_IO3FV(3)) +#define RPC_CMNCR_CPHAT BIT(6) +#define RPC_CMNCR_CPHAR BIT(5) +#define RPC_CMNCR_SSLP BIT(4) +#define RPC_CMNCR_CPOL BIT(3) +#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0) + +#define RPC_SSLDR 0x0004 /* R/W */ +#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16) +#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8) +#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0) + +#define RPC_DRCR 0x000C /* R/W */ +#define RPC_DRCR_SSLN BIT(24) +#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) +#define RPC_DRCR_RCF BIT(9) +#define RPC_DRCR_RBE BIT(8) +#define RPC_DRCR_SSLE BIT(0) + +#define RPC_DRCMR 0x0010 /* R/W */ +#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16) +#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0) + +#define RPC_DREAR 0x0014 /* R/W */ +#define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16) +#define RPC_DREAR_EAC(v) (((v) & 0x7) << 0) + +#define RPC_DROPR 0x0018 /* R/W */ +#define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24) +#define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16) +#define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8) +#define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0) + +#define RPC_DRENR 0x001C /* R/W */ +#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) +#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28) +#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24) +#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20) +#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16) +#define RPC_DRENR_DME BIT(15) +#define RPC_DRENR_CDE BIT(14) +#define RPC_DRENR_OCDE BIT(12) +#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8) +#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4) + +#define RPC_SMCR 0x0020 /* R/W */ +#define RPC_SMCR_SSLKP BIT(8) +#define RPC_SMCR_SPIRE BIT(2) +#define RPC_SMCR_SPIWE BIT(1) +#define RPC_SMCR_SPIE BIT(0) + +#define RPC_SMCMR 0x0024 /* R/W */ +#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16) +#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0) + +#define RPC_SMADR 0x0028 /* R/W */ +#define RPC_SMOPR 0x002C /* R/W */ +#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0) +#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8) +#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16) +#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24) + +#define RPC_SMENR 0x0030 /* R/W */ +#define RPC_SMENR_CDB(o) (((o) & 0x3) << 30) +#define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28) +#define RPC_SMENR_ADB(o) (((o) & 0x3) << 24) +#define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20) +#define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16) +#define RPC_SMENR_DME BIT(15) +#define RPC_SMENR_CDE BIT(14) +#define RPC_SMENR_OCDE BIT(12) +#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8) +#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4) +#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0) + +#define RPC_SMRDR0 0x0038 /* R */ +#define RPC_SMRDR1 0x003C /* R */ +#define RPC_SMWDR0 0x0040 /* R/W */ +#define RPC_SMWDR1 0x0044 /* R/W */ +#define RPC_CMNSR 0x0048 /* R */ +#define RPC_CMNSR_SSLF BIT(1) +#define RPC_CMNSR_TEND BIT(0) + +#define RPC_DRDMCR 0x0058 /* R/W */ +#define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0) + +#define RPC_DRDRENR 0x005C /* R/W */ +#define RPC_DRDRENR_HYPE (0x5 << 12) +#define RPC_DRDRENR_ADDRE BIT(8) +#define RPC_DRDRENR_OPDRE BIT(4) +#define RPC_DRDRENR_DRDRE BIT(0) + +#define RPC_SMDMCR 0x0060 /* R/W */ +#define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0) + +#define RPC_SMDRENR 0x0064 /* R/W */ +#define RPC_SMDRENR_HYPE (0x5 << 12) +#define RPC_SMDRENR_ADDRE BIT(8) +#define RPC_SMDRENR_OPDRE BIT(4) +#define RPC_SMDRENR_SPIDRE BIT(0) + +#define RPC_PHYCNT 0x007C /* R/W */ +#define RPC_PHYCNT_CAL BIT(31) +#define PRC_PHYCNT_OCTA_AA BIT(22) +#define PRC_PHYCNT_OCTA_SA BIT(23) +#define PRC_PHYCNT_EXDS BIT(21) +#define RPC_PHYCNT_OCT BIT(20) +#define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) +#define RPC_PHYCNT_WBUF2 BIT(4) +#define RPC_PHYCNT_WBUF BIT(2) +#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) + +#define RPC_PHYINT 0x0088 /* R/W */ +#define RPC_PHYINT_RSTEN BIT(18) +#define RPC_PHYINT_WPEN BIT(17) +#define RPC_PHYINT_INTEN BIT(16) +#define RPC_PHYINT_RST BIT(2) +#define RPC_PHYINT_WP BIT(1) +#define RPC_PHYINT_INT BIT(0) + +#define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */ +#define RPC_WBUF_SIZE 0x100 + +DECLARE_GLOBAL_DATA_PTR; + +struct rpc_spi_platdata { + fdt_addr_t regs; + fdt_addr_t extr; + s32 freq; /* Default clock freq, -1 for none */ +}; + +struct rpc_spi_priv { + fdt_addr_t regs; + fdt_addr_t extr; + struct clk clk; + + u8 cmdcopy[8]; + u32 cmdlen; + bool cmdstarted; +}; + +static int rpc_spi_wait_sslf(struct udevice *dev) +{ + struct rpc_spi_priv *priv = dev_get_priv(dev->parent); + + return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF, + false, 1000, false); +} + +static int rpc_spi_wait_tend(struct udevice *dev) +{ + struct rpc_spi_priv *priv = dev_get_priv(dev->parent); + + return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND, + true, 1000, false); +} + +static void rpc_spi_flush_read_cache(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct rpc_spi_priv *priv = dev_get_priv(bus); + + /* Flush read cache */ + writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) | + RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE, + priv->regs + RPC_DRCR); + readl(priv->regs + RPC_DRCR); + +} + +static int rpc_spi_claim_bus(struct udevice *dev, bool manual) +{ + struct udevice *bus = dev->parent; + struct rpc_spi_priv *priv = dev_get_priv(bus); + + /* + * NOTE: The 0x260 are undocumented bits, but they must be set. + * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the + * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the + * RPC_PHYCNT_STRTIM shall be 6. + */ + writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260, + priv->regs + RPC_PHYCNT); + writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE | + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0), + priv->regs + RPC_CMNCR); + + writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) | + RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR); + + rpc_spi_flush_read_cache(dev); + + return 0; +} + +static int rpc_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct rpc_spi_priv *priv = dev_get_priv(bus); + + /* NOTE: The 0x260 are undocumented bits, but they must be set. */ + writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT); + + rpc_spi_flush_read_cache(dev); + + return 0; +} + +static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct rpc_spi_priv *priv = dev_get_priv(bus); + u32 wlen = dout ? (bitlen / 8) : 0; + u32 rlen = din ? (bitlen / 8) : 0; + u32 wloop = DIV_ROUND_UP(wlen, 4); + u32 smenr, smcr, offset; + int ret = 0; + + if (!priv->cmdstarted) { + if (!wlen || rlen) + BUG(); + + memcpy(priv->cmdcopy, dout, wlen); + priv->cmdlen = wlen; + + /* Command transfer start */ + priv->cmdstarted = true; + if (!(flags & SPI_XFER_END)) + return 0; + } + + offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) | + (priv->cmdcopy[3] << 0); + + smenr = 0; + + if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) { + if (wlen && flags == SPI_XFER_END) + smenr = RPC_SMENR_SPIDE(0xf); + + rpc_spi_claim_bus(dev, true); + + writel(0, priv->regs + RPC_SMCR); + + if (priv->cmdlen >= 1) { /* Command(1) */ + writel(RPC_SMCMR_CMD(priv->cmdcopy[0]), + priv->regs + RPC_SMCMR); + smenr |= RPC_SMENR_CDE; + } else { + writel(0, priv->regs + RPC_SMCMR); + } + + if (priv->cmdlen >= 4) { /* Address(3) */ + writel(offset, priv->regs + RPC_SMADR); + smenr |= RPC_SMENR_ADE(7); + } else { + writel(0, priv->regs + RPC_SMADR); + } + + if (priv->cmdlen >= 5) { /* Dummy(n) */ + writel(8 * (priv->cmdlen - 4) - 1, + priv->regs + RPC_SMDMCR); + smenr |= RPC_SMENR_DME; + } else { + writel(0, priv->regs + RPC_SMDMCR); + } + + writel(0, priv->regs + RPC_SMOPR); + + writel(0, priv->regs + RPC_SMDRENR); + + if (wlen && flags == SPI_XFER_END) { + u32 *datout = (u32 *)dout; + + while (wloop--) { + smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE; + if (wloop >= 1) + smcr |= RPC_SMCR_SSLKP; + writel(smenr, priv->regs + RPC_SMENR); + writel(*datout, priv->regs + RPC_SMWDR0); + writel(smcr, priv->regs + RPC_SMCR); + ret = rpc_spi_wait_tend(dev); + if (ret) + goto err; + datout++; + smenr = RPC_SMENR_SPIDE(0xf); + } + + ret = rpc_spi_wait_sslf(dev); + + } else { + writel(smenr, priv->regs + RPC_SMENR); + writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR); + ret = rpc_spi_wait_tend(dev); + } + } else { /* Read data only, using DRx ext access */ + rpc_spi_claim_bus(dev, false); + + if (priv->cmdlen >= 1) { /* Command(1) */ + writel(RPC_DRCMR_CMD(priv->cmdcopy[0]), + priv->regs + RPC_DRCMR); + smenr |= RPC_DRENR_CDE; + } else { + writel(0, priv->regs + RPC_DRCMR); + } + + if (priv->cmdlen >= 4) /* Address(3) */ + smenr |= RPC_DRENR_ADE(7); + + if (priv->cmdlen >= 5) { /* Dummy(n) */ + writel(8 * (priv->cmdlen - 4) - 1, + priv->regs + RPC_DRDMCR); + smenr |= RPC_DRENR_DME; + } else { + writel(0, priv->regs + RPC_DRDMCR); + } + + writel(0, priv->regs + RPC_DROPR); + + writel(smenr, priv->regs + RPC_DRENR); + + if (rlen) + memcpy_fromio(din, (void *)(priv->extr + offset), rlen); + else + readl(priv->extr); /* Dummy read */ + } + +err: + priv->cmdstarted = false; + + rpc_spi_release_bus(dev); + + return ret; +} + +static int rpc_spi_set_speed(struct udevice *bus, uint speed) +{ + /* This is a SPI NOR controller, do nothing. */ + return 0; +} + +static int rpc_spi_set_mode(struct udevice *bus, uint mode) +{ + /* This is a SPI NOR controller, do nothing. */ + return 0; +} + +static int rpc_spi_bind(struct udevice *parent) +{ + const void *fdt = gd->fdt_blob; + ofnode node; + int ret, off; + + /* + * Check if there are any SPI NOR child nodes, if so, bind as + * this controller will be operated in SPI mode. + */ + dev_for_each_subnode(node, parent) { + off = ofnode_to_offset(node); + + ret = fdt_node_check_compatible(fdt, off, "spi-flash"); + if (!ret) + return 0; + + ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor"); + if (!ret) + return 0; + } + + return -ENODEV; +} + +static int rpc_spi_probe(struct udevice *dev) +{ + struct rpc_spi_platdata *plat = dev_get_platdata(dev); + struct rpc_spi_priv *priv = dev_get_priv(dev); + + priv->regs = plat->regs; + priv->extr = plat->extr; + + clk_enable(&priv->clk); + + return 0; +} + +static int rpc_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct rpc_spi_platdata *plat = dev_get_platdata(bus); + struct rpc_spi_priv *priv = dev_get_priv(bus); + int ret; + + plat->regs = dev_read_addr_index(bus, 0); + plat->extr = dev_read_addr_index(bus, 1); + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) { + printf("%s: Could not get clock for %s: %d\n", + __func__, bus->name, ret); + return ret; + } + + plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000); + + return 0; +} + +static const struct dm_spi_ops rpc_spi_ops = { + .xfer = rpc_spi_xfer, + .set_speed = rpc_spi_set_speed, + .set_mode = rpc_spi_set_mode, +}; + +static const struct udevice_id rpc_spi_ids[] = { + { .compatible = "renesas,rpc-r8a7795" }, + { .compatible = "renesas,rpc-r8a7796" }, + { .compatible = "renesas,rpc-r8a77965" }, + { .compatible = "renesas,rpc-r8a77970" }, + { .compatible = "renesas,rpc-r8a77995" }, + { } +}; + +U_BOOT_DRIVER(rpc_spi) = { + .name = "rpc_spi", + .id = UCLASS_SPI, + .of_match = rpc_spi_ids, + .ops = &rpc_spi_ops, + .ofdata_to_platdata = rpc_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct rpc_spi_platdata), + .priv_auto_alloc_size = sizeof(struct rpc_spi_priv), + .bind = rpc_spi_bind, + .probe = rpc_spi_probe, +}; diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index 75999c812d..5075be3cd1 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -11,6 +11,7 @@ #include <console.h> #include <malloc.h> #include <spi.h> +#include <wait_bit.h> #include <asm/arch/rmobile.h> #include <asm/io.h> @@ -35,33 +36,35 @@ SPCMD_BRDV0 #define SPBFCR_TXRST BIT(7) #define SPBFCR_RXRST BIT(6) +#define SPBFCR_TXTRG 0x30 +#define SPBFCR_RXTRG 0x07 /* SH QSPI register set */ struct sh_qspi_regs { - unsigned char spcr; - unsigned char sslp; - unsigned char sppcr; - unsigned char spsr; - unsigned long spdr; - unsigned char spscr; - unsigned char spssr; - unsigned char spbr; - unsigned char spdcr; - unsigned char spckd; - unsigned char sslnd; - unsigned char spnd; - unsigned char dummy0; - unsigned short spcmd0; - unsigned short spcmd1; - unsigned short spcmd2; - unsigned short spcmd3; - unsigned char spbfcr; - unsigned char dummy1; - unsigned short spbdcr; - unsigned long spbmul0; - unsigned long spbmul1; - unsigned long spbmul2; - unsigned long spbmul3; + u8 spcr; + u8 sslp; + u8 sppcr; + u8 spsr; + u32 spdr; + u8 spscr; + u8 spssr; + u8 spbr; + u8 spdcr; + u8 spckd; + u8 sslnd; + u8 spnd; + u8 dummy0; + u16 spcmd0; + u16 spcmd1; + u16 spcmd2; + u16 spcmd3; + u8 spbfcr; + u8 dummy1; + u16 spbdcr; + u32 spbmul0; + u32 spbmul1; + u32 spbmul2; + u32 spbmul3; }; struct sh_qspi_slave { @@ -200,11 +203,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct sh_qspi_slave *ss = to_sh_qspi(slave); - unsigned long nbyte; - int ret = 0; - unsigned char dtdata = 0, drdata; - unsigned char *tdata = &dtdata, *rdata = &drdata; - unsigned long *spbmul0 = &ss->regs->spbmul0; + u32 nbyte, chunk; + int i, ret = 0; + u8 dtdata = 0, drdata; + u8 *tdata = &dtdata, *rdata = &drdata; + u32 *spbmul0 = &ss->regs->spbmul0; if (dout == NULL && din == NULL) { if (flags & SPI_XFER_END) @@ -230,46 +233,44 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, writel(nbyte, spbmul0); if (dout != NULL) - tdata = (unsigned char *)dout; + tdata = (u8 *)dout; if (din != NULL) rdata = din; while (nbyte > 0) { - while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) { - if (ctrlc()) { - puts("abort\n"); - return 1; - } - udelay(10); + /* + * Check if there is 32 Byte chunk and if there is, transfer + * it in one burst, otherwise transfer on byte-by-byte basis. + */ + chunk = (nbyte >= 32) ? 32 : 1; + + clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG, + chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0); + + ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF, + true, 1000, true); + if (ret) + return ret; + + for (i = 0; i < chunk; i++) { + writeb(*tdata, &ss->regs->spdr); + if (dout != NULL) + tdata++; } - writeb(*tdata, (unsigned char *)(&ss->regs->spdr)); + ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF, + true, 1000, true); + if (ret) + return ret; - while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) { - if (ctrlc()) { - puts("abort\n"); - return 1; - } - udelay(1); + for (i = 0; i < chunk; i++) { + *rdata = readb(&ss->regs->spdr); + if (din != NULL) + rdata++; } - while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) { - if (ctrlc()) { - puts("abort\n"); - return 1; - } - udelay(10); - } - - *rdata = readb((unsigned char *)(&ss->regs->spdr)); - - if (dout != NULL) - tdata++; - if (din != NULL) - rdata++; - - nbyte--; + nbyte -= chunk; } if (flags & SPI_XFER_END) diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index 3abce7f678..22c602a4d2 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -15,8 +15,6 @@ #include <sysreset.h> #include <syscon.h> -DECLARE_GLOBAL_DATA_PTR; - struct syscon_reboot_priv { struct regmap *regmap; unsigned int offset; @@ -55,10 +53,8 @@ int syscon_reboot_probe(struct udevice *dev) return -ENODEV; } - priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), - "offset", 0); - priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), - "mask", 0); + priv->offset = dev_read_u32_default(dev, "offset", 0); + priv->mask = dev_read_u32_default(dev, "mask", 0); return 0; } diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 6825e6b543..26b4d12a09 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -158,6 +158,7 @@ endif # USB_GADGET_DOWNLOAD config USB_ETHER bool "USB Ethernet Gadget" + depends on NET default y if ARCH_SUNXI && USB_MUSB_GADGET help Creates an Ethernet network device through a USB peripheral diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index a80486e91f..386505d42d 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -10,6 +10,7 @@ #include <common.h> #include <console.h> +#include <environment.h> #include <linux/errno.h> #include <linux/netdevice.h> #include <linux/usb/ch9.h> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index a7249b7511..3455e8113b 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -21,6 +21,14 @@ config USB_XHCI_DWC3 Say Y or if your system has a Dual Role SuperSpeed USB controller based on the DesignWare USB3 IP Core. +config USB_XHCI_DWC3_OF_SIMPLE + bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" + depends on DM_USB + default y if DRA7XX + help + Support USB2/3 functionality in simple SoC integrations with + USB controller based on the DesignWare USB3 IP Core. + config USB_XHCI_MVEBU bool "MVEBU USB 3.0 support" default y diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 98194893b9..abe4f9087f 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c new file mode 100644 index 0000000000..440dd1027d --- /dev/null +++ b/drivers/usb/host/dwc3-of-simple.c @@ -0,0 +1,110 @@ +/* + * dwc3-of-simple.c - OF glue layer for simple integrations + * + * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi <balbi@ti.com> + * + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstron@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <reset.h> +#include <clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct dwc3_of_simple { + struct clk_bulk clks; + struct reset_ctl_bulk resets; +}; + +static int dwc3_of_simple_reset_init(struct udevice *dev, + struct dwc3_of_simple *simple) +{ + int ret; + + ret = reset_get_bulk(dev, &simple->resets); + if (ret == -ENOTSUPP) + return 0; + else if (ret) + return ret; + + ret = reset_deassert_bulk(&simple->resets); + if (ret) { + reset_release_bulk(&simple->resets); + return ret; + } + + return 0; +} + +static int dwc3_of_simple_clk_init(struct udevice *dev, + struct dwc3_of_simple *simple) +{ + int ret; + + ret = clk_get_bulk(dev, &simple->clks); + if (ret == -ENOSYS) + return 0; + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_enable_bulk(&simple->clks); + if (ret) { + clk_release_bulk(&simple->clks); + return ret; + } +#endif + + return 0; +} + +static int dwc3_of_simple_probe(struct udevice *dev) +{ + struct dwc3_of_simple *simple = dev_get_platdata(dev); + int ret; + + ret = dwc3_of_simple_clk_init(dev, simple); + if (ret) + return ret; + + ret = dwc3_of_simple_reset_init(dev, simple); + if (ret) + return ret; + + return 0; +} + +static int dwc3_of_simple_remove(struct udevice *dev) +{ + struct dwc3_of_simple *simple = dev_get_platdata(dev); + + reset_release_bulk(&simple->resets); + + clk_release_bulk(&simple->clks); + + return dm_scan_fdt_dev(dev); +} + +static const struct udevice_id dwc3_of_simple_ids[] = { + { .compatible = "amlogic,meson-gxl-dwc3" }, + { .compatible = "ti,dwc3" }, + { } +}; + +U_BOOT_DRIVER(dwc3_of_simple) = { + .name = "dwc3-of-simple", + .id = UCLASS_SIMPLE_BUS, + .of_match = dwc3_of_simple_ids, + .probe = dwc3_of_simple_probe, + .remove = dwc3_of_simple_remove, + .platdata_auto_alloc_size = sizeof(struct dwc3_of_simple), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 1022dd5512..c1007350b7 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c @@ -22,8 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; struct xhci_dwc3_platdata { - struct phy usb_phy; - struct phy usb3_phy; + struct phy *usb_phys; + int num_phys; }; void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) @@ -113,45 +113,82 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) } #ifdef CONFIG_DM_USB -static int xhci_dwc3_setup_phy(struct udevice *dev, int index, struct phy *phy) +static int xhci_dwc3_setup_phy(struct udevice *dev, int count) { - int ret = 0; + struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); + int i, ret; + + if (!count) + return 0; - ret = generic_phy_get_by_index(dev, index, phy); - if (ret) { - if (ret != -ENOENT) { - pr_err("Failed to get USB PHY for %s\n", dev->name); + plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy), + GFP_KERNEL); + if (!plat->usb_phys) + return -ENOMEM; + + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, dev->name); return ret; } - } else { - ret = generic_phy_init(phy); + + ++plat->num_phys; + } + + for (i = 0; i < plat->num_phys; i++) { + ret = generic_phy_init(&plat->usb_phys[i]); if (ret) { - pr_err("Can't init USB PHY for %s\n", dev->name); - return ret; + pr_err("Can't init USB PHY%d for %s\n", + i, dev->name); + goto phys_init_err; } - ret = generic_phy_power_on(phy); + } + + for (i = 0; i < plat->num_phys; i++) { + ret = generic_phy_power_on(&plat->usb_phys[i]); if (ret) { - pr_err("Can't power on USB PHY for %s\n", dev->name); - generic_phy_exit(phy); - return ret; + pr_err("Can't power USB PHY%d for %s\n", + i, dev->name); + goto phys_poweron_err; } } return 0; + + +phys_poweron_err: + for (; i >= 0; i--) + generic_phy_power_off(&plat->usb_phys[i]); + + for (i = 0; i < plat->num_phys; i++) + generic_phy_exit(&plat->usb_phys[i]); + + return ret; + +phys_init_err: + for (; i >= 0; i--) + generic_phy_exit(&plat->usb_phys[i]); + + return ret; } -static int xhci_dwc3_shutdown_phy(struct phy *phy) +static int xhci_dwc3_shutdown_phy(struct udevice *dev) { - int ret = 0; + struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); + int i, ret; - if (generic_phy_valid(phy)) { - ret = generic_phy_power_off(phy); - if (ret) - return ret; + for (i = 0; i < plat->num_phys; i++) { + if (!generic_phy_valid(&plat->usb_phys[i])) + continue; - ret = generic_phy_exit(phy); - if (ret) - return ret; + ret = generic_phy_power_off(&plat->usb_phys[i]); + ret |= generic_phy_exit(&plat->usb_phys[i]); + if (ret) { + pr_err("Can't shutdown USB PHY%d for %s\n", + i, dev->name); + } } return 0; @@ -159,7 +196,6 @@ static int xhci_dwc3_shutdown_phy(struct phy *phy) static int xhci_dwc3_probe(struct udevice *dev) { - struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); struct xhci_hcor *hcor; struct xhci_hccr *hccr; struct dwc3 *dwc3_reg; @@ -170,18 +206,10 @@ static int xhci_dwc3_probe(struct udevice *dev) hcor = (struct xhci_hcor *)((uintptr_t)hccr + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); - ret = xhci_dwc3_setup_phy(dev, 0, &plat->usb_phy); - if (ret) { - pr_err("Failed to setup USB PHY for %s\n", dev->name); + ret = xhci_dwc3_setup_phy(dev, dev_count_phandle_with_args( + dev, "phys", "#phy-cells")); + if (ret) return ret; - } - - ret = xhci_dwc3_setup_phy(dev, 1, &plat->usb3_phy); - if (ret) { - pr_err("Failed to setup USB3 PHY for %s\n", dev->name); - xhci_dwc3_shutdown_phy(&plat->usb_phy); - return ret; - } dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET); @@ -199,16 +227,7 @@ static int xhci_dwc3_probe(struct udevice *dev) static int xhci_dwc3_remove(struct udevice *dev) { - struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); - int ret; - - ret = xhci_dwc3_shutdown_phy(&plat->usb_phy); - if (ret) - pr_err("Can't shutdown USB PHY for %s\n", dev->name); - - ret = xhci_dwc3_shutdown_phy(&plat->usb3_phy); - if (ret) - pr_err("Can't shutdown USB3 PHY for %s\n", dev->name); + xhci_dwc3_shutdown_phy(dev); return xhci_deregister(dev); } diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 45a105db06..4c4d2861fe 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -174,7 +174,7 @@ config FRAMEBUFFER_SET_VESA_MODE choice prompt "framebuffer graphics resolution" - default FRAMEBUFFER_VESA_MODE_117 + default FRAMEBUFFER_VESA_MODE_118 depends on FRAMEBUFFER_SET_VESA_MODE help This option sets the resolution used for the U-Boot framebuffer (and diff --git a/drivers/video/Makefile b/drivers/video/Makefile index dfafe08fc5..ab897e145c 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_S6E8AX0) += s6e8ax0.o -obj-$(CONFIG_S6E63D6) += s6e63d6.o obj-$(CONFIG_LD9040) += ld9040.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c deleted file mode 100644 index f077260d76..0000000000 --- a/drivers/video/s6e63d6.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <spi.h> -#include <s6e63d6.h> - -/* - * Each transfer is performed as: - * 1. chip-select active - * 2. send 8-bit start code - * 3. send 16-bit data - * 4. chip-select inactive - */ -static int send_word(struct s6e63d6 *data, u8 rs, u16 word) -{ - /* - * The start byte looks like (binary): - * 01110<ID><RS><R/W> - * RS is 0 for index or 1 for data, and R/W is 0 for write. - */ - u32 buf8 = 0x70 | data->id | (rs & 2); - u32 buf16 = cpu_to_le16(word); - u32 buf_in; - int err; - - err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN); - if (err) - return err; - - return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END); -} - -/* Index and param differ in Register Select bit */ -int s6e63d6_index(struct s6e63d6 *data, u8 idx) -{ - return send_word(data, 0, idx); -} - -int s6e63d6_param(struct s6e63d6 *data, u16 param) -{ - return send_word(data, 2, param); -} - -int s6e63d6_init(struct s6e63d6 *data) -{ - if (data->id != 0 && data->id != 4) { - printf("s6e63d6: invalid ID %u\n", data->id); - return 1; - } - - data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3); - if (!data->slave) - return 1; - - return 0; -} diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 71733cf8ba..c43f7e8096 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -25,7 +25,6 @@ struct cdns_regs { struct cdns_wdt_priv { bool rst; u32 timeout; - void __iomem *reg; struct cdns_regs *regs; }; @@ -224,12 +223,8 @@ static int cdns_wdt_stop(struct udevice *dev) */ static int cdns_wdt_probe(struct udevice *dev) { - struct cdns_wdt_priv *priv = dev_get_priv(dev); - debug("%s: Probing wdt%u\n", __func__, dev->seq); - priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs)); - cdns_wdt_stop(dev); return 0; diff --git a/env/Kconfig b/env/Kconfig index 680441c74c..f403906b6f 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -497,4 +497,11 @@ config DEFAULT_ENV_FILE containing key=value pairs, blank lines and lines beginning with # are ignored. +config ENV_VARS_UBOOT_RUNTIME_CONFIG + bool "Add run-time information to the environment" + help + Enable this in order to add variables describing certain + run-time determined information about the hardware to the + environment. These will be named board_name, board_rev. + endmenu diff --git a/env/common.c b/env/common.c index f21ff70096..8f602de9d2 100644 --- a/env/common.c +++ b/env/common.c @@ -227,6 +227,7 @@ void env_relocate(void) { #if defined(CONFIG_NEEDS_MANUAL_RELOC) env_reloc(); + env_fix_drivers(); env_htab.change_ok += gd->reloc_off; #endif if (gd->env_valid == ENV_INVALID) { @@ -10,6 +10,27 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_NEEDS_MANUAL_RELOC) +void env_fix_drivers(void) +{ + struct env_driver *drv; + const int n_ents = ll_entry_count(struct env_driver, env_driver); + struct env_driver *entry; + + drv = ll_entry_start(struct env_driver, env_driver); + for (entry = drv; entry != drv + n_ents; entry++) { + if (entry->name) + entry->name += gd->reloc_off; + if (entry->load) + entry->load += gd->reloc_off; + if (entry->save) + entry->save += gd->reloc_off; + if (entry->init) + entry->init += gd->reloc_off; + } +} +#endif + static struct env_driver *_env_driver_lookup(enum env_location loc) { struct env_driver *drv; diff --git a/env/ext4.c b/env/ext4.c index 6c69a0a57f..a2d32b9c8d 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -87,8 +87,10 @@ static int env_ext4_load(void) int err; loff_t off; +#ifdef CONFIG_MMC if (!strcmp(CONFIG_ENV_EXT4_INTERFACE, "mmc")) mmc_initialize(NULL); +#endif part = blk_get_device_part_str(CONFIG_ENV_EXT4_INTERFACE, CONFIG_ENV_EXT4_DEVICE_AND_PART, @@ -89,8 +89,10 @@ static int env_fat_load(void) int dev, part; int err; +#ifdef CONFIG_MMC if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc")) mmc_initialize(NULL); +#endif part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE, CONFIG_ENV_FAT_DEVICE_AND_PART, diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index b4ce706a8e..cbc4cb2bc8 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -611,7 +611,7 @@ static inline ino_t parent_ino(struct dentry *dentry) /* misc.h */ #define mutex_lock_nested(...) #define mutex_unlock_nested(...) -#define mutex_is_locked(...) 0 +#define mutex_is_locked(...) 1 #endif /* Version of this UBIFS implementation */ diff --git a/include/clk.h b/include/clk.h index a7d95d32c9..b3a9fcecb0 100644 --- a/include/clk.h +++ b/include/clk.h @@ -60,6 +60,23 @@ struct clk { unsigned long id; }; +/** + * struct clk_bulk - A handle to (allowing control of) a bulk of clocks. + * + * Clients provide storage for the clock bulk. The content of the structure is + * managed solely by the clock API. A clock bulk struct is + * initialized by "get"ing the clock bulk struct. + * The clock bulk struct is passed to all other bulk clock APIs to apply + * the API to all the clock in the bulk struct. + * + * @clks: An array of clock handles. + * @count: The number of clock handles in the clks array. + */ +struct clk_bulk { + struct clk *clks; + unsigned int count; +}; + #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) struct phandle_1_arg; int clk_get_by_index_platdata(struct udevice *dev, int index, @@ -83,6 +100,21 @@ int clk_get_by_index_platdata(struct udevice *dev, int index, int clk_get_by_index(struct udevice *dev, int index, struct clk *clk); /** + * clock_get_bulk - Get/request all clocks of a device. + * + * This looks up and requests all clocks of the client device; each device is + * assumed to have n clocks associated with it somehow, and this function finds + * and requests all of them in a separate structure. The mapping of client + * device clock indices to provider clocks may be via device-tree properties, + * board-provided mapping tables, or some other mechanism. + * + * @dev: The client device. + * @bulk A pointer to a clock bulk struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk); + +/** * clock_get_by_name - Get/request a clock by name. * * This looks up and requests a clock. The name is relative to the client @@ -120,6 +152,11 @@ static inline int clk_get_by_index(struct udevice *dev, int index, return -ENOSYS; } +static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) +{ + return -ENOSYS; +} + static inline int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) { @@ -130,7 +167,6 @@ static inline int clk_release_all(struct clk *clk, int count) { return -ENOSYS; } - #endif #if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \ @@ -151,6 +187,22 @@ static inline int clk_set_defaults(struct udevice *dev) #endif /** + * clk_release_bulk() - Disable (turn off)/Free an array of previously + * requested clocks in a clock bulk struct. + * + * For each clock contained in the clock bulk struct, this function will check + * if clock has been previously requested and then will disable and free it. + * + * @clk: A clock bulk struct that was previously successfully + * requested by clk_get_bulk(). + * @return zero on success, or -ve error code. + */ +static inline int clk_release_bulk(struct clk_bulk *bulk) +{ + return clk_release_all(bulk->clks, bulk->count); +} + +/** * clk_request - Request a clock by provider-specific ID. * * This requests a clock using a provider-specific ID. Generally, this function @@ -215,6 +267,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent); int clk_enable(struct clk *clk); /** + * clk_enable_bulk() - Enable (turn on) all clocks in a clock bulk struct. + * + * @bulk: A clock bulk struct that was previously successfully requested + * by clk_get_bulk(). + * @return zero on success, or -ve error code. + */ +int clk_enable_bulk(struct clk_bulk *bulk); + +/** * clk_disable() - Disable (turn off) a clock. * * @clk: A clock struct that was previously successfully requested by @@ -223,6 +284,15 @@ int clk_enable(struct clk *clk); */ int clk_disable(struct clk *clk); +/** + * clk_disable_bulk() - Disable (turn off) all clocks in a clock bulk struct. + * + * @bulk: A clock bulk struct that was previously successfully requested + * by clk_get_bulk(). + * @return zero on success, or -ve error code. + */ +int clk_disable_bulk(struct clk_bulk *bulk); + int soc_clk_dump(void); #endif diff --git a/include/configs/alt.h b/include/configs/alt.h index f5e41db156..d6236870b9 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -73,7 +73,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* MMCIF */ -#define CONFIG_SH_MMCIF #define CONFIG_SH_MMCIF_ADDR 0xee200000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 8d45b6fade..ff87adcd49 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -56,8 +56,6 @@ #define NANDARGS "" #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "setenv mmcdev " #instance"; "\ @@ -74,14 +72,26 @@ #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ #devtypel #instance " " +#if CONFIG_IS_ENABLED(CMD_PXE) +# define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_PXE(func) +#endif + +#if CONFIG_IS_ENABLED(CMD_DHCP) +# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DHCP(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(LEGACY_MMC, legacy_mmc, 0) \ func(MMC, mmc, 1) \ func(LEGACY_MMC, legacy_mmc, 1) \ func(NAND, nand, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + BOOT_TARGET_PXE(func) \ + BOOT_TARGET_DHCP(func) #include <config_distro_bootcmd.h> @@ -270,7 +280,6 @@ */ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index fe3f838598..a429dd9910 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -22,8 +22,6 @@ #define CONFIG_ENV_SIZE (96 << 10) /* 96 KiB */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 60b162e534..e29de0e15c 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -64,8 +64,6 @@ # define CONFIG_RESET_TO_RETRY #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ @@ -250,7 +248,6 @@ #undef CONFIG_TIMER #endif -#define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS2 diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 739a99860b..9687f3765a 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -26,8 +26,6 @@ /* Always 128 KiB env size */ #define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 663f861706..d2c1810bfd 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -62,8 +62,6 @@ /* Always 64 KiB env size */ #define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -221,7 +219,6 @@ #define CONFIG_NET_RETRY_COUNT 10 #endif -#define CONFIG_DRIVER_TI_CPSW #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ #define CONFIG_SYS_RX_ETH_BUFFER 64 diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c079a3ace0..d1f73f76a4 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -78,7 +78,6 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ #define CONFIG_MII /* Required in net/eth.c */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ @@ -112,7 +111,6 @@ /* SPI SPL */ #define CONFIG_TI_EDMA3 -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 /* SPI */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 7a75f6d6ad..eb8ffda67e 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -38,10 +38,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -/* Make the HW version stuff available in U-Boot env */ -#define CONFIG_VERSION_VARIABLE /* ver environment variable */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 0758902fe6..90dbc0eac4 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -170,7 +170,6 @@ #elif CONFIG_SYS_USE_NANDFLASH #elif CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 #elif CONFIG_NAND_BOOT diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 95e327aa65..0af0127cd4 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -143,7 +143,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #elif CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 #elif CONFIG_NAND_BOOT diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 943a6f819d..03559bd4f5 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -69,8 +69,6 @@ #define NANDARGS "" #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -231,11 +229,6 @@ /* SPL */ #ifndef CONFIG_NOR_BOOT -/* USB gadget RNDIS */ - -/* General network SPL, both CPSW and USB gadget RNDIS */ -#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/ - #ifdef CONFIG_NAND #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ @@ -273,14 +266,6 @@ #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_OTG -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) -/* disable host part of MUSB in SPL */ -/* disable EFI partitions and partition UUID support */ -/* - * Disable CPSW SPL support so we fit within the 101KiB limit. - */ -#endif - /* Network. */ #define CONFIG_PHY_SMSC #define CONFIG_MII diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index e7f65d6d03..fb896fee27 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -56,8 +56,6 @@ #define NANDARGS "" #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ @@ -452,7 +450,6 @@ DEFAULT_LINUX_BOOT_ENV \ */ #if defined(CONFIG_SPI_BOOT) /* SPL related */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 02e989ad7a..457f55b8a8 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -216,7 +216,6 @@ MMCARGS #define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 24000000 -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 4aa0cb698d..37d6aa5f4c 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ /* Network defines */ -#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_PHY_NATSEMI diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index afc0bae167..a0a9ec8af3 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -19,7 +19,6 @@ #ifdef CONFIG_SPL #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#define CONFIG_SPL_SPI_LOAD #include "imx6_spl.h" #endif @@ -99,7 +98,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index 596e0605e3..9c70cf0b37 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -36,8 +36,6 @@ /* Offsets: 0K - SPL1, 64K - SPL2, 128K - SPL3, 192K - SPL4, 256K - U-Boot */ #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) #define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_LOAD /* SD/MMC RAW/FS boot */ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" @@ -45,7 +43,6 @@ /* Environment */ #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_ENV_SECT_SIZE (64 * 1024) #define CONFIG_ENV_OFFSET (768 * 1024) @@ -81,7 +78,6 @@ /* USB Networking options */ /* CPSW Ethernet */ -#define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 7d6f39f4da..36cf5769e9 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -184,7 +184,6 @@ /* SPL */ #include "imx7_spl.h" #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index c5bd2ed336..059c302173 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -98,7 +98,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 4f36930a94..35328b1646 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -63,7 +63,6 @@ #define CONFIG_ENV_OFFSET (768 * 1024) #ifndef CONFIG_SPL_BUILD -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -228,7 +227,6 @@ /* SPL */ #include "imx6_spl.h" #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#define CONFIG_SPL_SPI_LOAD /* Display */ #define CONFIG_VIDEO_IPUV3 diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index da78519c8e..a118f0ee36 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -45,7 +45,6 @@ 50, 51, 52, 53, 54, 55, 56, 57, } /* CPSW Ethernet support */ -#define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_SEND_HOSTNAME @@ -84,7 +83,6 @@ #undef CONFIG_SYS_MONITOR_LEN #define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -133,7 +131,6 @@ #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SPL_SPI_LOAD /* EEPROM */ #define CONFIG_ENV_EEPROM_IS_ON_I2C diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index d257e5c339..0c372c5e00 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -36,10 +36,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -/* Make the HW version stuff available in U-Boot env */ -#define CONFIG_VERSION_VARIABLE /* ver environment variable */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 6f97c1e065..daa085966b 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -17,8 +17,6 @@ /*#define CONFIG_DBG_MONITOR*/ #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 2588731215..f5f648d7aa 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -24,7 +24,6 @@ * Environment settings */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 2d8b627f83..4d55c0119a 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -37,7 +37,6 @@ /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 1db18a4065..b6d15f684f 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -117,7 +117,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index dcae282e28..a914564c63 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -136,7 +136,6 @@ #endif #ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #endif @@ -292,7 +291,6 @@ #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_STACK 0x8001ff00 #define CONFIG_SPL_TEXT_BASE 0x80000000 #define CONFIG_SPL_MAX_FOOTPRINT 32768 @@ -300,9 +298,6 @@ #endif /* Load U-Boot Image From MMC */ -#ifdef CONFIG_SPL_MMC_LOAD -#undef CONFIG_SPL_SPI_LOAD -#endif /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 066b7def0e..a0eab2dcae 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -80,7 +80,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 915432ae26..cc54efec99 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -84,7 +84,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index bcc919d86d..8ea039efc2 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -98,7 +98,6 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index f886591159..f69d997c11 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -91,7 +91,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 02bf6981e9..9fce261d2e 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -25,7 +25,6 @@ /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" /* Miscellaneous configurable options */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 9fa96fed08..cda03d9f9b 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -49,7 +49,6 @@ #include "imx6_spl.h" #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SPL_SPI_LOAD #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e82de2a637..917a05d701 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -97,7 +97,6 @@ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_PHY_TI @@ -131,7 +130,6 @@ /* SPI SPL */ #define CONFIG_TI_EDMA3 -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/ds414.h b/include/configs/ds414.h index e137c0fd2a..1ac6ccad25 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -100,7 +100,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 /* DS414 bus width is 32bits */ diff --git a/include/configs/duovero.h b/include/configs/duovero.h index 96644b1fa6..1fecac2bc8 100644 --- a/include/configs/duovero.h +++ b/include/configs/duovero.h @@ -34,6 +34,4 @@ /* ENV related config options */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #endif /* __CONFIG_DUOVERO_H */ diff --git a/include/configs/eagle.h b/include/configs/eagle.h index 2ef0c7a777..d2edd56130 100644 --- a/include/configs/eagle.h +++ b/include/configs/eagle.h @@ -19,6 +19,12 @@ #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI +/* Environment compatibility */ +#undef CONFIG_ENV_SIZE_REDUND +#undef CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_OFFSET 0x700000 + /* Board Clock */ /* XTAL_CLK : 33.33MHz */ #define CONFIG_SYS_CLK_FREQ 33333333u diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 2dac12f607..9c145200a2 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -22,7 +22,6 @@ #ifdef CONFIG_SPL #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#define CONFIG_SPL_SPI_LOAD #include "imx6_spl.h" #endif @@ -56,7 +55,6 @@ #define CONFIG_BOARD_NAME EL6Q -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "board="__stringify(CONFIG_BOARD_NAME)"\0" \ "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 0a6f179612..44c92f9d48 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -124,6 +124,7 @@ "swappartitions=" \ "setexpr partnum 3 - ${partnum}\0" \ "failbootcmd=" \ + "bx50_backlight_enable; " \ "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ "echo $msg; " \ "setenv stdout vga; " \ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h deleted file mode 100644 index e651410b53..0000000000 --- a/include/configs/imx31_phycore.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff <r-woodruff2@ti.com> - * Kshitij Gupta <kshitij@ti.com> - * - * Configuration settings for the phyCORE-i.MX31 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -/* High Level Configuration Options */ -#define CONFIG_MX31 /* This is a mx31 */ -#define CONFIG_MX31_CLK32 32000 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/*********************************************************** - * Command definition - ***********************************************************/ - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.23.168 -#define CONFIG_SERVERIP 192.168.23.2 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ - "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootargs_flash=setenv bootargs $(bootargs) " \ - "root=/dev/mtdblock2 rootfstype=jffs2\0" \ - "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \ - "tftpboot 0x80000000 $(uimage);bootm\0" \ - "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \ - "bootm 0x80000000\0" \ - "unlock=yes\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "prg_uboot=tftpboot 0x80000000 $(uboot);" \ - "protect off 0xa0000000 +0x20000;" \ - "erase 0xa0000000 +0x20000;" \ - "cp.b 0x80000000 0xa0000000 $(filesize)\0" \ - "prg_kernel=tftpboot 0x80000000 $(uimage);" \ - "erase 0xa0040000 +0x180000;" \ - "cp.b 0x80000000 0xa0040000 $(filesize)\0" \ - "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \ - "erase 0xa01c0000 0xa1ffffff;" \ - "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \ - "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \ - "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \ - "sync:1241513985,vmode:0\0" - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0xa0000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */ -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */ - -/* - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ - -/* - * Timeout for Flash Erase and Flash Write - * timeout values are in ticks - */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) - -/* - * JFFS2 partitions - */ -#define CONFIG_JFFS2_DEV "nor0" - -/* EET platform additions */ -#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET -#define CONFIG_HARD_SPI - -#define CONFIG_S6E63D6 - -#define CONFIG_VIDEO_MX3 -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 1bc7f2ac42..bfc9b33e8c 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -28,8 +28,6 @@ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index f00ca1c233..b14f6c5422 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -16,8 +16,6 @@ /* Platform type */ #define CONFIG_SOC_K2G -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* U-Boot general configuration */ #define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ DEFAULT_MMC_TI_ARGS \ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 4d093ded35..6b2af7a858 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -14,15 +14,9 @@ #include "rcar-gen2-common.h" -/* STACK */ -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC -#endif - -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ @@ -41,45 +35,29 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_SYS_TMU_CLK_DIV 4 - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_SPEED2 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF*/ -#define CONFIG_SMSTP2_ENA 0x00002000 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 -/* SCIF0 */ -#define CONFIG_SMSTP7_ENA 0x00200000 +#define CONFIG_SYS_TMU_CLK_DIV 4 -/* SD */ -#define CONFIG_SH_SDHI_FREQ 97500000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __KOELSCH_H */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h new file mode 100644 index 0000000000..fae2faec2f --- /dev/null +++ b/include/configs/kp_imx6q_tpc.h @@ -0,0 +1,141 @@ +/* + * K+P iMX6Q KP_IMX6Q_TPC board configuration + * + * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_ +#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_ + +#include <asm/arch/imx-regs.h> + +#include "mx6_common.h" + +/* SPL */ +#include "imx6_spl.h" /* common IMX6 SPL configuration */ + +/* Miscellaneous configurable options */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_BOUNCE_BUFFER + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) + +/* FEC ethernet */ +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_ARP_TIMEOUT 200UL + +/* Fuses */ +#ifdef CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP +#endif + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */ + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ +#endif + +/* Watchdog */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_IMX_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x10008000\0" \ + "fdt_addr_r=0x13000000\0" \ + "ramdisk_addr_r=0x18000000\0" \ + "scriptaddr=0x14000000\0" \ + "kernel_file=fitImage\0"\ + "rdinit=/sbin/init\0" \ + "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ + "fit_config=mx6q_tpc70_conf\0" \ + "upd_image=st.4k\0" \ + "updargs=setenv bootargs console=${console} ${smp}"\ + "rdinit=${rdinit} ${debug} ${displayargs}\0" \ + "loadusb=usb start; " \ + "fatload usb 0 ${loadaddr} ${upd_image}\0" \ + "usbupd=echo Booting update from usb ...; " \ + "setenv bootargs; " \ + "run updargs; " \ + "run loadusb; " \ + "bootm ${loadaddr}#${fit_config}\0" \ + BOOTENV + +#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> +#endif + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment */ +#define CONFIG_ENV_SIZE (SZ_8K) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 45a76f8010..97f7b2c7e7 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -72,7 +72,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* MMC */ -#define CONFIG_SH_MMCIF #define CONFIG_SH_MMCIF_ADDR 0xEE220000 #define CONFIG_SH_MMCIF_CLK 97500000 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 91e6da03b1..35ecb3ce56 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -75,9 +75,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 790db150ce..5ab29a14db 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -147,11 +147,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 /* PCIe */ #ifndef SPL_NO_PCIE diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 7d67f10d40..b9424e666d 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -125,11 +125,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 211059a601..814760ebe9 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -67,11 +67,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4e6a26cc72..258a6f1a04 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -77,11 +77,6 @@ /* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h index 6b34edfbf1..c2fdc4daf6 100644 --- a/include/configs/ls2080a_emu.h +++ b/include/configs/ls2080a_emu.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 - #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index aff319bd72..d4da91fcfe 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -12,9 +12,6 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 133333333 -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 - #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h index a00af1a1fb..1781db8cb5 100644 --- a/include/configs/ma5d4evk.h +++ b/include/configs/ma5d4evk.h @@ -205,7 +205,6 @@ #define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #define CONFIG_SYS_USE_MMC diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 93597db236..0f97b4c1e0 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -76,7 +76,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 8eb248ac89..0aa797aa60 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -94,7 +94,6 @@ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200 quiet\0" \ "fdtfile=imx6q-mccmon6.dtb\0" \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index bc58ca5c62..79d4c9b2ce 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -65,6 +65,7 @@ /* FEC Ethernet on SoC */ #ifdef CONFIG_CMD_NET #define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE #define CONFIG_MX28_FEC_MAC_IN_OCOTP #endif diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h deleted file mode 100644 index 651b998a4a..0000000000 --- a/include/configs/mx31ads.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> - * - * Configuration settings for the MX31ADS Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - - /* High Level Configuration Options */ -#define CONFIG_MX31 1 /* This is a mx31 */ - -#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_HARD_SPI 1 -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot_addr=0xa0000000\0" \ - "uboot=mx31ads/u-boot.bin\0" \ - "kernel=mx31ads/uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ - "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_nfs; " \ - "tftpboot ${loadaddr} ${kernel}; bootm\0" \ - "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ - "protect off ${uboot_addr} 0xa003ffff; " \ - "erase ${uboot_addr} 0xa003ffff; " \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ - "setenv filesize; saveenv\0" - -#define CONFIG_CS8900 -#define CONFIG_CS8900_BASE 0xb4020300 -#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ - -/* - * The MX31ADS board seems to have a hardware "peculiarity" confirmed under - * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A - * controller inverted. The controller is capable of detecting and correcting - * this, but it needs 4 network packets for that. Which means, at startup, you - * will not receive answers to the first 4 packest, unless there have been some - * broadcasts on the network, or your board is on a hub. Reducing the ARP - * timeout from default 5 seconds to 200ms we speed up the initial TFTP - * transfer, should the user wish one, significantly. - */ -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ - -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ -#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ - -/* - * JFFS2 partitions - */ -#define CONFIG_JFFS2_DEV "nor0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index bd28515e3a..e2ce79671d 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -197,8 +197,8 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* FLASH and environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_ENV_SIZE (10 * 1024) #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 0e1d18cad8..9fbd162d8f 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -71,7 +71,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 #define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "fdtfile=undefined\0" \ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index d976e77aef..6f970a41ef 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -57,8 +57,6 @@ #define EMMC_ENV "" #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1eaaf013f7..713ebf6ac1 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -43,7 +43,6 @@ #define UPDATE_M4_ENV "" #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ "script=boot.scr\0" \ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 1c1671e30f..733538f2ee 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -18,8 +18,6 @@ /* SPL options */ #include "imx6_spl.h" -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 21429134ba..cf9f8abedf 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -22,8 +22,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 000b305cce..3544ffc516 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -57,6 +57,9 @@ /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#endif #endif #endif diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 2c8ee7a7fe..8faa7a33fc 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -185,7 +185,6 @@ * TODO: Add Odroid X support */ #define CONFIG_MISC_COMMON -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_BOARD_TYPES #define CONFIG_MISC_INIT_R diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 9067ba6893..53edd23bdb 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -88,7 +88,6 @@ #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, boardname, fdtfile */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_ODROID_REV_AIN 9 #define CONFIG_REVISION_TAG #define CONFIG_BOARD_TYPES diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 75203b291c..8cded9996e 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -30,7 +30,6 @@ /* ENV related config options */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_ENV_OVERWRITE #endif /* __CONFIG_PANDA_H */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 77b89bc7a0..d67a619a8c 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -129,7 +129,6 @@ #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 #endif diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index b2cbf91ddf..62b48bc258 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -68,7 +68,6 @@ #ifdef CONFIG_SPL #include "imx6_spl.h" #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#define CONFIG_SPL_SPI_LOAD #endif #define CONFIG_FEC_MXC diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 411403e8fd..a59e88171f 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -25,7 +25,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_PCM051 /* set to negative value for no autoboot */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80007fc0\0" \ "fdtaddr=0x80000000\0" \ @@ -117,7 +116,6 @@ /* CPU */ #ifdef CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #endif diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 9481e5b5c5..3b8239052e 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -9,7 +9,6 @@ #define __PCM058_CONFIG_H #ifdef CONFIG_SPL -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 74bfde7222..863b6e7eb4 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -22,8 +22,6 @@ /* set env size */ #define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ @@ -167,16 +165,9 @@ #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST -#if defined(CONFIG_SPL_BUILD) -/* disable host part of MUSB in SPL */ -/* Disable CPSW SPL support so we fit within the 101KiB limit. */ -#endif - /* Network */ #define CONFIG_PHY_RESET 1 #define CONFIG_PHY_NATSEMI #define CONFIG_PHY_REALTEK -/* CPSW support */ - #endif /* ! __CONFIG_PENGWYN_H */ diff --git a/include/configs/pepper.h b/include/configs/pepper.h index f0ffc518c3..44dcfba673 100644 --- a/include/configs/pepper.h +++ b/include/configs/pepper.h @@ -20,7 +20,6 @@ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "bootdir=/boot\0" \ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index e3c1191817..072cd3454a 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -9,7 +9,6 @@ #define __PCM058_CONFIG_H #ifdef CONFIG_SPL -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) #include "imx6_spl.h" #endif diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index ee48363590..a81548cb00 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -50,8 +50,8 @@ "finduuid=part uuid mmc 0:2 uuid\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run finduuid; " \ "run mmcargs; " \ diff --git a/include/configs/porter.h b/include/configs/porter.h index eb28d1afcc..b1a4c2576e 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -54,10 +54,13 @@ "initrd_high=0xffffffff\0" /* SPL support */ -#define CONFIG_SPL_TEXT_BASE 0xe6304000 +#define CONFIG_SPL_TEXT_BASE 0xe6300000 #define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x40000 -#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_MAX_SIZE 0x4000 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __PORTER_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index bbaab80e23..da82e4442a 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -51,6 +51,7 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* ENV setting */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index f0e550d8aa..bdba19eeae 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -13,9 +13,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#if defined(CONFIG_SPL_SPI_SUPPORT) -#define CONFIG_SPL_SPI_LOAD -#endif #define COUNTER_FREQUENCY 24000000 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 17cdecd1c3..325e52a019 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -86,7 +86,6 @@ #define CONFIG_INITRD_TAG /* Environment */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define ENV_DEVICE_SETTINGS \ "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 1b40c29a55..40f037e06d 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -103,7 +103,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_UPDATEB \ "updatek=" \ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 841deddbe8..410d20bd89 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -71,8 +71,6 @@ #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 24fa027034..71dbc10430 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -82,7 +82,6 @@ #endif #ifdef CONFIG_QSPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #endif diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index f06556f0d4..7f27f7a5ee 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -61,7 +61,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #elif CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 843aaa6394..51db135940 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -15,8 +15,6 @@ #include "at91-sama5_common.h" -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* * This needs to be defined for the OHCI code to work but it is defined as * ATMEL_ID_UHPHS in the CPU specific header files. @@ -104,7 +102,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #elif CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #elif CONFIG_NAND_BOOT diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 007a4f653f..fb1e74019d 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -63,7 +63,6 @@ #elif CONFIG_SYS_USE_NANDFLASH #elif CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #elif CONFIG_NAND_BOOT diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index dec3b526c0..2ac47fdb24 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -60,7 +60,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #elif CONFIG_SPI_BOOT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 #elif CONFIG_NAND_BOOT diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index e192de0623..ff1208f196 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -60,7 +60,6 @@ #define CONFIG_SH_SPI_BASE 0xfe002000 /* MMCIF */ -#define CONFIG_SH_MMCIF 1 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index c17bc310bb..9a1d2e3368 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -60,7 +60,6 @@ #define CONFIG_SH_SPI_BASE 0xfe002000 /* MMCIF */ -#define CONFIG_SH_MMCIF 1 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 6ca13aa5f8..94b4119c58 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -64,7 +64,6 @@ #define CONFIG_SH_SPI_BASE 0xfe002000 /* MMCIF */ -#define CONFIG_SH_MMCIF 1 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index b23e20a563..13c3dc8b23 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -103,7 +103,6 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SPL_NAND_BASE @@ -192,7 +191,6 @@ # define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ #endif /* SPI support */ -#define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS2 diff --git a/include/configs/silk.h b/include/configs/silk.h index 5d85c0df93..5f351b5c4b 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -16,12 +16,8 @@ #include "rcar-gen2-common.h" -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC -#endif -#define STACK_AREA_SIZE 0xC000 +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) @@ -49,46 +45,22 @@ /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK -#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) -#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) - -#define CONFIG_SYS_TMU_CLK_DIV 4 - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_SPEED2 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* MMCIF */ -#define CONFIG_SH_MMCIF -#define CONFIG_SH_MMCIF_ADDR 0xee200000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 97500000 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF */ -#define CONFIG_SMSTP2_ENA 0x00002000 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 -/* SCIF2 */ -#define CONFIG_SMSTP7_ENA 0x00080000 +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF2 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __SILK_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6385357b22..025c7de2d1 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -137,6 +137,7 @@ /* * I2C support */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS @@ -157,6 +158,7 @@ unsigned int cm_get_l4_sp_clk_hz(void); #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) #endif +#endif /* CONFIG_DM_I2C */ /* * QSPI support @@ -269,7 +271,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif @@ -293,7 +294,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define BOOT_TARGET_DEVICES_DHCP(func) #endif -#ifdef CONFIG_CMD_PXE +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) #else #define BOOT_TARGET_DEVICES_PXE(func) diff --git a/include/configs/stout.h b/include/configs/stout.h index b81103e8a7..228cb552cb 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -17,14 +17,9 @@ #include "rcar-gen2-common.h" -/* STACK */ -#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC -#endif -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ @@ -43,47 +38,31 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_RCAR -#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 -#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK -#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) -#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) -#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) -#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) #define CONFIG_SYS_TMU_CLK_DIV 4 -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF, SCIFA0 */ -#define CONFIG_SMSTP2_ENA 0x00002010 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 97500000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIFA0 +#define CONFIG_SH_SCIF_CLK_FREQ 52000000 +#endif #endif /* __STOUT_H */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index f138bd2238..2fa0ded439 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -123,7 +123,6 @@ #if defined(CONFIG_SPL_BUILD) /* SPL related */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SF_DEFAULT_BUS 0 diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 3c2691f952..c487642e89 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -118,7 +118,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 2f9056cad8..a81f3b8201 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -28,7 +28,6 @@ /* commands to include */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ @@ -155,7 +154,6 @@ #endif /* Ethernet */ -#define CONFIG_DRIVER_TI_CPSW #define CONFIG_MII #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 9832e09aac..83e26dbb6e 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -35,7 +35,6 @@ #define CONFIG_MII /* Required in net/eth.c */ #endif -#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ /* * SPL related defines. The Public RAM memory map the ROM defines the * area between 0x402F0400 and 0x4030B800 as a download area and diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2592014694..e87acca650 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -48,7 +48,6 @@ CONFIG_SYS_SPL_MALLOC_SIZE + \ SPL_MALLOC_F_SIZE + \ KEYSTONE_SPL_STACK_SIZE - 4) -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO /* SRAM scratch space entries */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 539164177b..d6ea17bec4 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -58,7 +58,6 @@ #include <environment/ti/boot.h> #include <environment/ti/mmc.h> -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ diff --git a/include/configs/trats.h b/include/configs/trats.h index e6649fffa2..e892b59311 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -57,8 +57,6 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" diff --git a/include/configs/trats2.h b/include/configs/trats2.h index c3eb7c95fe..aecac077e4 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -52,8 +52,6 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 27ce047f7d..1df806b60a 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -97,7 +97,6 @@ #ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI /* SPL related SPI defines */ -# define CONFIG_SPL_SPI_LOAD # define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 # define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS #endif diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 989014a177..dd86deeb12 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -46,8 +46,6 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 35a6eca9f6..7e6b98041e 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ /* Linux only */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 1b4140de06..c39f13bf6b 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -33,7 +33,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ +#define CONFIG_SYS_MONITOR_LEN 0x00090000 /* 576KB */ #define CONFIG_SYS_FLASH_BASE 0 /* @@ -186,6 +186,7 @@ "setexpr tmp_addr $nor_base + 0x70000 && " \ "tftpboot $tmp_addr $third_image\0" \ "emmcupdate=mmcsetn &&" \ + "mmc dev $mmc_first_dev &&" \ "mmc partconf $mmc_first_dev 0 1 1 &&" \ "tftpboot $second_image && " \ "mmc write $loadaddr 0 100 && " \ @@ -219,7 +220,7 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -#define CONFIG_SPL_STACK (0x00100000) +#define CONFIG_SPL_STACK (0x00200000) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 diff --git a/include/configs/veyron.h b/include/configs/veyron.h index 3a5fc065d8..49522559d4 100644 --- a/include/configs/veyron.h +++ b/include/configs/veyron.h @@ -14,7 +14,6 @@ #include <configs/rk3288_common.h> -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_KEYBOARD diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index f054c9933f..45d1c35faa 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -92,7 +92,6 @@ #define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_ENV_OFFSET (8 * SZ_64K) #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index bc2d269070..7b502840cb 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -78,7 +78,6 @@ #define CONFIG_IMX_VIDEO_SKIP #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "splashpos=m,m\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index fe96988be7..0c3b605de3 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -24,6 +24,9 @@ #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +/* Switch on SERIAL_TAG */ +#define CONFIG_SERIAL_TAG + #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h index df27523e78..028e3ff937 100644 --- a/include/configs/wb50n.h +++ b/include/configs/wb50n.h @@ -23,7 +23,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_IMAGE_FORMAT_LEGACY /* general purpose I/O */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8cdc72206c..5827911c4e 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -172,12 +172,24 @@ # define BOOT_TARGET_DEVICES_USB(func) #endif +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DEVICES_DHCP(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) #include <config_distro_bootcmd.h> @@ -209,7 +221,6 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) -# define CONFIG_SPL_SPI_LOAD # define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 # define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 # define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 diff --git a/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h b/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h new file mode 100644 index 0000000000..cdc0062c3b --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm017_dc3.h @@ -0,0 +1,20 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM017 DC3 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H +#define __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H + +#define CONFIG_ZYNQ_SDHCI1 + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM017_DC3_H */ diff --git a/include/configs/xilinx_zynqmp_zcu100.h b/include/configs/xilinx_zynqmp_zcu100.h new file mode 100644 index 0000000000..bfb85d6b75 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu100.h @@ -0,0 +1,36 @@ +/* + * Configuration for Xilinx ZynqMP zcu100 + * + * (C) Copyright 2015 - 2016 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU100_H +#define __CONFIG_ZYNQMP_ZCU100_H + +/* FIXME Will go away soon */ +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 9 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {0, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZCU100_H */ diff --git a/include/configs/xilinx_zynqmp_zcu104.h b/include/configs/xilinx_zynqmp_zcu104.h new file mode 100644 index 0000000000..f8cdade763 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu104.h @@ -0,0 +1,36 @@ +/* + * Configuration for Xilinx ZynqMP zcu104 + * + * (C) Copyright 2017 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU104_H +#define __CONFIG_ZYNQMP_ZCU104_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 9 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ + {0, {{I2C_MUX_PCA9548, 0x74, 7} } }, \ + } + +#define CONFIG_PCA953X + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZCU104_H */ diff --git a/include/configs/xilinx_zynqmp_zcu106.h b/include/configs/xilinx_zynqmp_zcu106.h new file mode 100644 index 0000000000..0f0d8c6d42 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu106.h @@ -0,0 +1,47 @@ +/* + * Configuration for Xilinx ZynqMP zcu106 + * + * (C) Copyright 2016 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU106_H +#define __CONFIG_ZYNQMP_ZCU106_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 18 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_PCA953X + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ZYNQ_EEPROM_BUS 5 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZCU106_H */ diff --git a/include/configs/xilinx_zynqmp_zcu111.h b/include/configs/xilinx_zynqmp_zcu111.h new file mode 100644 index 0000000000..c488c2133c --- /dev/null +++ b/include/configs/xilinx_zynqmp_zcu111.h @@ -0,0 +1,50 @@ +/* + * Configuration for Xilinx ZynqMP zcu111 + * + * (C) Copyright 2017 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZCU111_H +#define __CONFIG_ZYNQMP_ZCU111_H + +#define CONFIG_ZYNQ_SDHCI1 +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 21 +#define CONFIG_SYS_I2C_BUSES { \ + {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \ + {0, {{I2C_MUX_PCA9544, 0x75, 3} } }, \ + {1, {I2C_NULL_HOP} }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x74, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \ + {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \ + } + +#define CONFIG_PCA953X + +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR} + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_ZYNQ_EEPROM_BUS 5 +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZCU111_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 554fb66634..baad8db62f 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -127,7 +127,9 @@ #endif /* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE (128 << 10) +#ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE (128 << 10) +#endif /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -135,7 +137,9 @@ /* Environment */ #ifndef CONFIG_ENV_IS_NOWHERE # define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# define CONFIG_ENV_OFFSET 0xE0000 +# ifndef CONFIG_ENV_OFFSET +# define CONFIG_ENV_OFFSET 0xE0000 +# endif #endif /* enable preboot to be loaded before CONFIG_BOOTDELAY */ @@ -162,7 +166,7 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif -#if defined(CONFIG_CMD_PXE) +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) #else #define BOOT_TARGET_DEVICES_PXE(func) @@ -298,7 +302,6 @@ /* qspi mode is working fine */ #ifdef CONFIG_ZYNQ_QSPI -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 #define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h deleted file mode 100644 index e1b81fe5ef..0000000000 --- a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * MIO pin configuration defines for Xilinx ZynqMP - * - * Copyright (C) 2017 Xilinx, Inc. - * Author: Chirag Parekh <chirag.parekh@xilinx.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H -#define _DT_BINDINGS_PINCTRL_ZYNQMP_H - -/* Bit value for IO standards */ -#define IO_STANDARD_LVCMOS33 0 -#define IO_STANDARD_LVCMOS18 1 - -/* Bit values for Slew Rates */ -#define SLEW_RATE_FAST 0 -#define SLEW_RATE_SLOW 1 - -/* Bit values for Pin inputs */ -#define PIN_INPUT_TYPE_CMOS 0 -#define PIN_INPUT_TYPE_SCHMITT 1 - -#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h new file mode 100644 index 0000000000..e3cae08e0e --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2016-2018 Intel Corporation. All rights reserved + * Copyright (C) 2016 Altera Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define CPU2_RESET 2 +#define CPU3_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +/* 38 is empty */ +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +/* 46 is empty */ +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 64 +#define WATCHDOG1_RESET 65 +#define WATCHDOG2_RESET 66 +#define WATCHDOG3_RESET 67 +#define L4SYSTIMER0_RESET 68 +#define L4SYSTIMER1_RESET 69 +#define SPTIMER0_RESET 70 +#define SPTIMER1_RESET 71 +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is empty */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is empty */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 + +/* BRGMODRST */ +#define SOC2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2SOC_RESET 98 +#define F2SSDRAM0_RESET 99 +#define F2SSDRAM1_RESET 100 +#define F2SSDRAM2_RESET 101 +#define DDRSCH_RESET 102 + +/* COLDMODRST */ +#define CPUPO0_RESET 160 +#define CPUPO1_RESET 161 +#define CPUPO2_RESET 162 +#define CPUPO3_RESET 163 +/* 164-167 is empty */ +#define L2_RESET 168 + +/* DBGMODRST */ +#define DBG_RESET 224 +#define CSDAP_RESET 225 + +/* TAPMODRST */ +#define TAP_RESET 256 + +#endif diff --git a/include/efi_api.h b/include/efi_api.h index 3ba650e57e..64c27e494b 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -107,7 +107,7 @@ struct efi_boot_services { efi_status_t (EFIAPI *load_image)(bool boot_policiy, efi_handle_t parent_image, struct efi_device_path *file_path, void *source_buffer, - unsigned long source_size, efi_handle_t *image); + efi_uintn_t source_size, efi_handle_t *image); efi_status_t (EFIAPI *start_image)(efi_handle_t handle, unsigned long *exitdata_size, s16 **exitdata); @@ -180,7 +180,8 @@ struct efi_boot_services { enum efi_reset_type { EFI_RESET_COLD = 0, EFI_RESET_WARM = 1, - EFI_RESET_SHUTDOWN = 2 + EFI_RESET_SHUTDOWN = 2, + EFI_RESET_PLATFORM_SPECIFIC = 3, }; /* EFI Runtime Services table */ @@ -243,6 +244,27 @@ struct efi_runtime_services { u64 maximum_variable_size); }; +/* EFI event group GUID definitions */ +#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \ + EFI_GUID(0x27abf055, 0xb1b8, 0x4c26, 0x80, 0x48, \ + 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf) + +#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \ + EFI_GUID(0x13fa7698, 0xc831, 0x49c7, 0x87, 0xea, \ + 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96) + +#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \ + EFI_GUID(0x78bee926, 0x692f, 0x48fd, 0x9e, 0xdb, \ + 0x01, 0x42, 0x2e, 0xf0, 0xd7, 0xab) + +#define EFI_EVENT_GROUP_READY_TO_BOOT \ + EFI_GUID(0x7ce88fb3, 0x4bd7, 0x4679, 0x87, 0xa8, \ + 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b) + +#define EFI_EVENT_GROUP_RESET_SYSTEM \ + EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \ + 0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b) + /* EFI Configuration Table and GUID definitions */ #define NULL_GUID \ EFI_GUID(0x00000000, 0x0000, 0x0000, 0x00, 0x00, \ @@ -296,8 +318,8 @@ struct efi_loaded_image { u32 revision; void *parent_handle; struct efi_system_table *system_table; - void *device_handle; - void *file_path; + efi_handle_t device_handle; + struct efi_device_path *file_path; void *reserved; u32 load_options_size; void *load_options; @@ -309,6 +331,8 @@ struct efi_loaded_image { /* Below are efi loader private fields */ #ifdef CONFIG_EFI_LOADER + void *reloc_base; + aligned_u64 reloc_size; efi_status_t exit_status; struct jmp_buf_data exit_jmp; #endif @@ -319,6 +343,7 @@ struct efi_loaded_image { 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b ) #define DEVICE_PATH_TYPE_END 0x7f +# define DEVICE_PATH_SUB_TYPE_INSTANCE_END 0x01 # define DEVICE_PATH_SUB_TYPE_END 0xff struct efi_device_path { @@ -571,24 +596,6 @@ struct efi_simple_input_interface { struct efi_event *wait_for_key; }; -#define CONSOLE_CONTROL_GUID \ - EFI_GUID(0xf42f7782, 0x12e, 0x4c12, \ - 0x99, 0x56, 0x49, 0xf9, 0x43, 0x4, 0xf7, 0x21) -#define EFI_CONSOLE_MODE_TEXT 0 -#define EFI_CONSOLE_MODE_GFX 1 - -struct efi_console_control_protocol -{ - efi_status_t (EFIAPI *get_mode)( - struct efi_console_control_protocol *this, int *mode, - char *uga_exists, char *std_in_locked); - efi_status_t (EFIAPI *set_mode)( - struct efi_console_control_protocol *this, int mode); - efi_status_t (EFIAPI *lock_std_in)( - struct efi_console_control_protocol *this, - uint16_t *password); -}; - #define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \ EFI_GUID(0x8b843e20, 0x8132, 0x4852, \ 0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c) @@ -605,6 +612,35 @@ struct efi_device_path_to_text_protocol bool allow_shortcuts); }; +#define EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID \ + EFI_GUID(0x0379be4e, 0xd706, 0x437d, \ + 0xb0, 0x37, 0xed, 0xb8, 0x2f, 0xb7, 0x72, 0xa4) + +struct efi_device_path_utilities_protocol { + efi_uintn_t (EFIAPI *get_device_path_size)( + const struct efi_device_path *device_path); + struct efi_device_path *(EFIAPI *duplicate_device_path)( + const struct efi_device_path *device_path); + struct efi_device_path *(EFIAPI *append_device_path)( + const struct efi_device_path *src1, + const struct efi_device_path *src2); + struct efi_device_path *(EFIAPI *append_device_node)( + const struct efi_device_path *device_path, + const struct efi_device_path *device_node); + struct efi_device_path *(EFIAPI *append_device_path_instance)( + const struct efi_device_path *device_path, + const struct efi_device_path *device_path_instance); + struct efi_device_path *(EFIAPI *get_next_device_path_instance)( + struct efi_device_path **device_path_instance, + efi_uintn_t *device_path_instance_size); + bool (EFIAPI *is_device_path_multi_instance)( + const struct efi_device_path *device_path); + struct efi_device_path *(EFIAPI *create_device_node)( + uint8_t node_type, + uint8_t node_sub_type, + uint16_t node_length); +}; + #define EFI_GOP_GUID \ EFI_GUID(0x9042a9de, 0x23dc, 0x4a38, \ 0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a) @@ -633,6 +669,13 @@ struct efi_gop_mode unsigned long fb_size; }; +struct efi_gop_pixel { + u8 blue; + u8 green; + u8 red; + u8 reserved; +}; + #define EFI_BLT_VIDEO_FILL 0 #define EFI_BLT_VIDEO_TO_BLT_BUFFER 1 #define EFI_BLT_BUFFER_TO_VIDEO 2 @@ -644,7 +687,8 @@ struct efi_gop efi_uintn_t *size_of_info, struct efi_gop_mode_info **info); efi_status_t (EFIAPI *set_mode)(struct efi_gop *this, u32 mode_number); - efi_status_t (EFIAPI *blt)(struct efi_gop *this, void *buffer, + efi_status_t (EFIAPI *blt)(struct efi_gop *this, + struct efi_gop_pixel *buffer, u32 operation, efi_uintn_t sx, efi_uintn_t sy, efi_uintn_t dx, efi_uintn_t dy, efi_uintn_t width, @@ -662,7 +706,7 @@ struct efi_mac_address { struct efi_ip_address { u8 ip_addr[16]; -}; +} __attribute__((aligned(4))); enum efi_simple_network_state { EFI_NETWORK_STOPPED, @@ -756,7 +800,28 @@ struct efi_pxe_packet { struct efi_pxe_mode { - u8 unused[52]; + u8 started; + u8 ipv6_available; + u8 ipv6_supported; + u8 using_ipv6; + u8 bis_supported; + u8 bis_detected; + u8 auto_arp; + u8 send_guid; + u8 dhcp_discover_valid; + u8 dhcp_ack_received; + u8 proxy_offer_received; + u8 pxe_discover_valid; + u8 pxe_reply_received; + u8 pxe_bis_reply_received; + u8 icmp_error_received; + u8 tftp_error_received; + u8 make_callbacks; + u8 ttl; + u8 tos; + u8 pad; + struct efi_ip_address station_ip; + struct efi_ip_address subnet_mask; struct efi_pxe_packet dhcp_discover; struct efi_pxe_packet dhcp_ack; struct efi_pxe_packet proxy_offer; @@ -794,17 +859,19 @@ struct efi_file_handle { efi_status_t (EFIAPI *close)(struct efi_file_handle *file); efi_status_t (EFIAPI *delete)(struct efi_file_handle *file); efi_status_t (EFIAPI *read)(struct efi_file_handle *file, - u64 *buffer_size, void *buffer); + efi_uintn_t *buffer_size, void *buffer); efi_status_t (EFIAPI *write)(struct efi_file_handle *file, - u64 *buffer_size, void *buffer); + efi_uintn_t *buffer_size, void *buffer); efi_status_t (EFIAPI *getpos)(struct efi_file_handle *file, - u64 *pos); + efi_uintn_t *pos); efi_status_t (EFIAPI *setpos)(struct efi_file_handle *file, - u64 pos); + efi_uintn_t pos); efi_status_t (EFIAPI *getinfo)(struct efi_file_handle *file, - efi_guid_t *info_type, u64 *buffer_size, void *buffer); + const efi_guid_t *info_type, efi_uintn_t *buffer_size, + void *buffer); efi_status_t (EFIAPI *setinfo)(struct efi_file_handle *file, - efi_guid_t *info_type, u64 buffer_size, void *buffer); + const efi_guid_t *info_type, efi_uintn_t buffer_size, + void *buffer); efi_status_t (EFIAPI *flush)(struct efi_file_handle *file); }; @@ -823,6 +890,10 @@ struct efi_simple_file_system_protocol { EFI_GUID(0x9576e92, 0x6d3f, 0x11d2, \ 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b) +#define EFI_FILE_SYSTEM_INFO_GUID \ + EFI_GUID(0x09576e93, 0x6d3f, 0x11d2, \ + 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) + #define EFI_FILE_MODE_READ 0x0000000000000001 #define EFI_FILE_MODE_WRITE 0x0000000000000002 #define EFI_FILE_MODE_CREATE 0x8000000000000000 @@ -846,6 +917,15 @@ struct efi_file_info { s16 file_name[0]; }; +struct efi_file_system_info { + u64 size; + u8 read_only; + u64 volume_size; + u64 free_space; + u32 block_size; + u16 volume_label[0]; +}; + #define EFI_DRIVER_BINDING_PROTOCOL_GUID \ EFI_GUID(0x18a031ab, 0xb443, 0x4d1a,\ 0xa5, 0xc0, 0x0c, 0x09, 0x26, 0x1e, 0x9f, 0x71) diff --git a/include/efi_loader.h b/include/efi_loader.h index 07730c3f39..8d21ba74b1 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -83,6 +83,9 @@ extern struct efi_simple_text_output_protocol efi_con_out; extern struct efi_simple_input_interface efi_con_in; extern struct efi_console_control_protocol efi_console_control; extern const struct efi_device_path_to_text_protocol efi_device_path_to_text; +/* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */ +extern const struct efi_device_path_utilities_protocol + efi_device_path_utilities; uint16_t *efi_dp_str(struct efi_device_path *dp); @@ -93,10 +96,25 @@ extern const efi_guid_t efi_guid_console_control; extern const efi_guid_t efi_guid_device_path; /* GUID of the EFI_DRIVER_BINDING_PROTOCOL */ extern const efi_guid_t efi_guid_driver_binding_protocol; +/* event group ExitBootServices() invoked */ +extern const efi_guid_t efi_guid_event_group_exit_boot_services; +/* event group SetVirtualAddressMap() invoked */ +extern const efi_guid_t efi_guid_event_group_virtual_address_change; +/* event group memory map changed */ +extern const efi_guid_t efi_guid_event_group_memory_map_change; +/* event group boot manager about to boot */ +extern const efi_guid_t efi_guid_event_group_ready_to_boot; +/* event group ResetSystem() invoked (before ExitBootServices) */ +extern const efi_guid_t efi_guid_event_group_reset_system; +/* GUID of the device tree table */ +extern const efi_guid_t efi_guid_fdt; extern const efi_guid_t efi_guid_loaded_image; extern const efi_guid_t efi_guid_device_path_to_text_protocol; extern const efi_guid_t efi_simple_file_system_protocol_guid; extern const efi_guid_t efi_file_info_guid; +/* GUID for file system information */ +extern const efi_guid_t efi_file_system_info_guid; +extern const efi_guid_t efi_guid_device_path_utilities_protocol; extern unsigned int __efi_runtime_start, __efi_runtime_stop; extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop; @@ -144,21 +162,25 @@ struct efi_object { /** * struct efi_event * + * @link: Link to list of all events * @type: Type of event, see efi_create_event * @notify_tpl: Task priority level of notifications - * @trigger_time: Period of the timer - * @trigger_next: Next time to trigger the timer * @nofify_function: Function to call when the event is triggered * @notify_context: Data to be passed to the notify function + * @group: Event group + * @trigger_time: Period of the timer + * @trigger_next: Next time to trigger the timer * @trigger_type: Type of timer, see efi_set_timer - * @queued: The notification function is queued - * @signaled: The event occurred. The event is in the signaled state. + * @is_queued: The notification function is queued + * @is_signaled: The event occurred. The event is in the signaled state. */ struct efi_event { + struct list_head link; uint32_t type; efi_uintn_t notify_tpl; void (EFIAPI *notify_function)(struct efi_event *event, void *context); void *notify_context; + const efi_guid_t *group; u64 trigger_next; u64 trigger_time; enum efi_timer_delay trigger_type; @@ -166,9 +188,10 @@ struct efi_event { bool is_signaled; }; - /* This list contains all UEFI objects we know of */ extern struct list_head efi_obj_list; +/* List of all events */ +extern struct list_head efi_events; /* Called by bootefi to make console interface available */ int efi_console_register(void); @@ -179,13 +202,13 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc, const char *if_typename, int diskid, const char *pdevname); /* Called by bootefi to make GOP (graphical) interface available */ -int efi_gop_register(void); +efi_status_t efi_gop_register(void); /* Called by bootefi to make the network interface available */ -int efi_net_register(void); +efi_status_t efi_net_register(void); /* Called by bootefi to make the watchdog available */ -int efi_watchdog_register(void); +efi_status_t efi_watchdog_register(void); /* Called by bootefi to make SMBIOS tables available */ -void efi_smbios_register(void); +efi_status_t efi_smbios_register(void); struct efi_simple_file_system_protocol * efi_fs_from_path(struct efi_device_path *fp); @@ -235,7 +258,8 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), - void *notify_context, struct efi_event **event); + void *notify_context, efi_guid_t *group, + struct efi_event **event); /* Call this to set a timer */ efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, uint64_t trigger_time); @@ -284,6 +308,10 @@ efi_status_t efi_setup_loaded_image( struct efi_device_path *file_path); efi_status_t efi_load_image_from_path(struct efi_device_path *file_path, void **buffer); +/* Print information about a loaded image */ +efi_status_t efi_print_image_info(struct efi_loaded_image *image, void *pc); +/* Print information about all loaded images */ +void efi_print_image_infos(void *pc); #ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER extern void *efi_bounce_buffer; @@ -296,13 +324,28 @@ int efi_dp_match(const struct efi_device_path *a, const struct efi_device_path *b); struct efi_object *efi_dp_find_obj(struct efi_device_path *dp, struct efi_device_path **rem); -unsigned efi_dp_size(const struct efi_device_path *dp); +/* get size of the first device path instance excluding end node */ +efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp); +/* size of multi-instance device path excluding end node */ +efi_uintn_t efi_dp_size(const struct efi_device_path *dp); struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp); struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1, const struct efi_device_path *dp2); struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, const struct efi_device_path *node); - +/* Create a device path node of given type, sub-type, length */ +struct efi_device_path *efi_dp_create_device_node(const u8 type, + const u8 sub_type, + const u16 length); +/* Append device path instance */ +struct efi_device_path *efi_dp_append_instance( + const struct efi_device_path *dp, + const struct efi_device_path *dpi); +/* Get next device path instance */ +struct efi_device_path *efi_dp_get_next_instance(struct efi_device_path **dp, + efi_uintn_t *size); +/* Check if a device path contains muliple instances */ +bool efi_dp_is_multi_instance(const struct efi_device_path *dp); struct efi_device_path *efi_dp_from_dev(struct udevice *dev); struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part); @@ -330,6 +373,7 @@ static inline void ascii2unicode(u16 *unicode, const char *ascii) { while (*ascii) *(unicode++) = *(ascii++); + *unicode = 0; } static inline int guidcmp(const efi_guid_t *g1, const efi_guid_t *g2) @@ -346,7 +390,7 @@ static inline int guidcmp(const efi_guid_t *g1, const efi_guid_t *g2) /* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region * to make it available at runtime */ -void efi_add_runtime_mmio(void *mmio_ptr, u64 len); +efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len); /* Boards may provide the functions below to implement RTS functionality */ @@ -354,12 +398,14 @@ void __efi_runtime EFIAPI efi_reset_system( enum efi_reset_type reset_type, efi_status_t reset_status, unsigned long data_size, void *reset_data); -void efi_reset_system_init(void); + +/* Architecture specific initialization of the EFI subsystem */ +efi_status_t efi_reset_system_init(void); efi_status_t __efi_runtime EFIAPI efi_get_time( struct efi_time *time, struct efi_time_cap *capabilities); -void efi_get_time_init(void); +efi_status_t efi_get_time_init(void); #ifdef CONFIG_CMD_BOOTEFI_SELFTEST /* @@ -388,13 +434,17 @@ void *efi_bootmgr_load(struct efi_device_path **device_path, /* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */ #define __efi_runtime_data #define __efi_runtime -static inline void efi_add_runtime_mmio(void *mmio_ptr, u64 len) { } +static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len) +{ + return EFI_SUCCESS; +} /* No loader configured, stub out EFI_ENTRY */ static inline void efi_restore_gd(void) { } static inline void efi_set_bootdev(const char *dev, const char *devnr, const char *path) { } static inline void efi_net_set_dhcp_ack(void *pkt, int len) { } +static inline void efi_print_image_infos(void *pc) { } #endif /* CONFIG_EFI_LOADER && !CONFIG_SPL_BUILD */ diff --git a/include/efi_selftest.h b/include/efi_selftest.h index 08dd8e43ad..c23bc24bed 100644 --- a/include/efi_selftest.h +++ b/include/efi_selftest.h @@ -114,6 +114,7 @@ u16 efi_st_get_key(void); * @setup: set up the unit test * @teardown: tear down the unit test * @execute: execute the unit test + * @setup_ok: setup was successful (set at runtime) * @on_request: test is only executed on request */ struct efi_unit_test { @@ -123,6 +124,7 @@ struct efi_unit_test { const struct efi_system_table *systable); int (*execute)(void); int (*teardown)(void); + int setup_ok; bool on_request; }; diff --git a/include/elf.h b/include/elf.h index fe2128f378..248ba59cd6 100644 --- a/include/elf.h +++ b/include/elf.h @@ -5,10 +5,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -/* - * This is the ELF ABI header file - * formerly known as "elf_abi.h". - */ +/* This is the ELF ABI header file formerly known as "elf_abi.h" */ #ifndef _ELF_H #define _ELF_H @@ -16,20 +13,16 @@ #ifndef __ASSEMBLER__ #include "compiler.h" -/* - * This version doesn't work for 64-bit ABIs - Erik. - */ +/* This version doesn't work for 64-bit ABIs - Erik */ -/* - * These typedefs need to be handled better. - */ +/* These typedefs need to be handled better */ typedef uint32_t Elf32_Addr; /* Unsigned program address */ typedef uint32_t Elf32_Off; /* Unsigned file offset */ typedef int32_t Elf32_Sword; /* Signed large integer */ typedef uint32_t Elf32_Word; /* Unsigned large integer */ typedef uint16_t Elf32_Half; /* Unsigned medium integer */ -/* 64-bit ELF base types. */ +/* 64-bit ELF base types */ typedef uint64_t Elf64_Addr; typedef uint16_t Elf64_Half; typedef int16_t Elf64_SHalf; @@ -96,7 +89,7 @@ typedef int64_t Elf64_Sxword; (ehdr).e_ident[EI_MAG3] == ELFMAG3) /* ELF Header */ -typedef struct elfhdr{ +typedef struct { unsigned char e_ident[EI_NIDENT]; /* ELF Identification */ Elf32_Half e_type; /* object file type */ Elf32_Half e_machine; /* machine */ @@ -114,6 +107,24 @@ typedef struct elfhdr{ header string table" entry offset */ } Elf32_Ehdr; +typedef struct { + unsigned char e_ident[EI_NIDENT]; /* ELF Identification */ + Elf64_Half e_type; /* object file type */ + Elf64_Half e_machine; /* machine */ + Elf64_Word e_version; /* object file version */ + Elf64_Addr e_entry; /* virtual entry point */ + Elf64_Off e_phoff; /* program header table offset */ + Elf64_Off e_shoff; /* section header table offset */ + Elf64_Word e_flags; /* processor-specific flags */ + Elf64_Half e_ehsize; /* ELF header size */ + Elf64_Half e_phentsize; /* program header entry size */ + Elf64_Half e_phnum; /* number of program header entries */ + Elf64_Half e_shentsize; /* section header entry size */ + Elf64_Half e_shnum; /* number of section header entries */ + Elf64_Half e_shstrndx; /* section header table's "section + header string table" entry offset */ +} Elf64_Ehdr; + /* e_type */ #define ET_NONE 0 /* No file type */ #define ET_REL 1 /* relocatable file */ @@ -122,9 +133,9 @@ typedef struct elfhdr{ #define ET_CORE 4 /* core file */ #define ET_NUM 5 /* number of types */ #define ET_LOOS 0xfe00 /* reserved range for operating */ -#define ET_HIOS 0xfeff /* system specific e_type */ +#define ET_HIOS 0xfeff /* system specific e_type */ #define ET_LOPROC 0xff00 /* reserved range for processor */ -#define ET_HIPROC 0xffff /* specific e_type */ +#define ET_HIPROC 0xffff /* specific e_type */ /* e_machine */ #define EM_NONE 0 /* No Machine */ @@ -231,13 +242,27 @@ typedef struct { Elf32_Word sh_entsize; /* section entry size */ } Elf32_Shdr; +typedef struct { + Elf64_Word sh_name; /* name - index into section header + string table section */ + Elf64_Word sh_type; /* type */ + Elf64_Xword sh_flags; /* flags */ + Elf64_Addr sh_addr; /* address */ + Elf64_Off sh_offset; /* file offset */ + Elf64_Xword sh_size; /* section size */ + Elf64_Word sh_link; /* section header table index link */ + Elf64_Word sh_info; /* extra information */ + Elf64_Xword sh_addralign; /* address alignment */ + Elf64_Xword sh_entsize; /* section entry size */ +} Elf64_Shdr; + /* Special Section Indexes */ #define SHN_UNDEF 0 /* undefined */ #define SHN_LORESERVE 0xff00 /* lower bounds of reserved indexes */ #define SHN_LOPROC 0xff00 /* reserved range for processor */ -#define SHN_HIPROC 0xff1f /* specific section indexes */ +#define SHN_HIPROC 0xff1f /* specific section indexes */ #define SHN_LOOS 0xff20 /* reserved range for operating */ -#define SHN_HIOS 0xff3f /* specific semantics */ +#define SHN_HIOS 0xff3f /* specific semantics */ #define SHN_ABS 0xfff1 /* absolute value */ #define SHN_COMMON 0xfff2 /* common symbol */ #define SHN_XINDEX 0xffff /* Index is an extra table */ @@ -265,46 +290,46 @@ typedef struct { #define SHT_LOOS 0x60000000 /* Start OS-specific */ #define SHT_HIOS 0x6fffffff /* End OS-specific */ #define SHT_LOPROC 0x70000000 /* reserved range for processor */ -#define SHT_HIPROC 0x7fffffff /* specific section header types */ +#define SHT_HIPROC 0x7fffffff /* specific section header types */ #define SHT_LOUSER 0x80000000 /* reserved range for application */ -#define SHT_HIUSER 0xffffffff /* specific indexes */ +#define SHT_HIUSER 0xffffffff /* specific indexes */ /* Section names */ -#define ELF_BSS ".bss" /* uninitialized data */ +#define ELF_BSS ".bss" /* uninitialized data */ #define ELF_COMMENT ".comment" /* version control information */ -#define ELF_DATA ".data" /* initialized data */ -#define ELF_DATA1 ".data1" /* initialized data */ -#define ELF_DEBUG ".debug" /* debug */ -#define ELF_DYNAMIC ".dynamic" /* dynamic linking information */ -#define ELF_DYNSTR ".dynstr" /* dynamic string table */ -#define ELF_DYNSYM ".dynsym" /* dynamic symbol table */ -#define ELF_FINI ".fini" /* termination code */ +#define ELF_DATA ".data" /* initialized data */ +#define ELF_DATA1 ".data1" /* initialized data */ +#define ELF_DEBUG ".debug" /* debug */ +#define ELF_DYNAMIC ".dynamic" /* dynamic linking information */ +#define ELF_DYNSTR ".dynstr" /* dynamic string table */ +#define ELF_DYNSYM ".dynsym" /* dynamic symbol table */ +#define ELF_FINI ".fini" /* termination code */ #define ELF_FINI_ARRAY ".fini_array" /* Array of destructors */ -#define ELF_GOT ".got" /* global offset table */ -#define ELF_HASH ".hash" /* symbol hash table */ -#define ELF_INIT ".init" /* initialization code */ +#define ELF_GOT ".got" /* global offset table */ +#define ELF_HASH ".hash" /* symbol hash table */ +#define ELF_INIT ".init" /* initialization code */ #define ELF_INIT_ARRAY ".init_array" /* Array of constuctors */ #define ELF_INTERP ".interp" /* Pathname of program interpreter */ #define ELF_LINE ".line" /* Symbolic line numnber information */ #define ELF_NOTE ".note" /* Contains note section */ #define ELF_PLT ".plt" /* Procedure linkage table */ #define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */ -#define ELF_REL_DATA ".rel.data" /* relocation data */ -#define ELF_REL_FINI ".rel.fini" /* relocation termination code */ -#define ELF_REL_INIT ".rel.init" /* relocation initialization code */ -#define ELF_REL_DYN ".rel.dyn" /* relocaltion dynamic link info */ -#define ELF_REL_RODATA ".rel.rodata" /* relocation read-only data */ -#define ELF_REL_TEXT ".rel.text" /* relocation code */ -#define ELF_RODATA ".rodata" /* read-only data */ -#define ELF_RODATA1 ".rodata1" /* read-only data */ -#define ELF_SHSTRTAB ".shstrtab" /* section header string table */ -#define ELF_STRTAB ".strtab" /* string table */ -#define ELF_SYMTAB ".symtab" /* symbol table */ +#define ELF_REL_DATA ".rel.data" /* relocation data */ +#define ELF_REL_FINI ".rel.fini" /* relocation termination code */ +#define ELF_REL_INIT ".rel.init" /* relocation initialization code */ +#define ELF_REL_DYN ".rel.dyn" /* relocaltion dynamic link info */ +#define ELF_REL_RODATA ".rel.rodata" /* relocation read-only data */ +#define ELF_REL_TEXT ".rel.text" /* relocation code */ +#define ELF_RODATA ".rodata" /* read-only data */ +#define ELF_RODATA1 ".rodata1" /* read-only data */ +#define ELF_SHSTRTAB ".shstrtab" /* section header string table */ +#define ELF_STRTAB ".strtab" /* string table */ +#define ELF_SYMTAB ".symtab" /* symbol table */ #define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */ #define ELF_TBSS ".tbss" /* thread local uninit data */ #define ELF_TDATA ".tdata" /* thread local init data */ #define ELF_TDATA1 ".tdata1" /* thread local init data */ -#define ELF_TEXT ".text" /* code */ +#define ELF_TEXT ".text" /* code */ /* Section Attribute Flags - sh_flags */ #define SHF_WRITE 0x1 /* Writable */ @@ -319,7 +344,7 @@ typedef struct { #define SHF_TLS 0x400 /* Thread local storage */ #define SHF_MASKOS 0x0ff00000 /* OS specific */ #define SHF_MASKPROC 0xf0000000 /* reserved bits for processor */ - /* specific section attributes */ + /* specific section attributes */ /* Section Group Flags */ #define GRP_COMDAT 0x1 /* COMDAT group */ @@ -327,7 +352,7 @@ typedef struct { #define GRP_MASKPROC 0xf0000000 /* Mask processor specific flags */ /* Symbol Table Entry */ -typedef struct elf32_sym { +typedef struct { Elf32_Word st_name; /* name - index into string table */ Elf32_Addr st_value; /* symbol value */ Elf32_Word st_size; /* symbol size */ @@ -351,9 +376,9 @@ typedef struct elf32_sym { #define STB_WEAK 2 /* like global - lower precedence */ #define STB_NUM 3 /* number of symbol bindings */ #define STB_LOOS 10 /* reserved range for operating */ -#define STB_HIOS 12 /* system specific symbol bindings */ +#define STB_HIOS 12 /* system specific symbol bindings */ #define STB_LOPROC 13 /* reserved range for processor */ -#define STB_HIPROC 15 /* specific symbol bindings */ +#define STB_HIPROC 15 /* specific symbol bindings */ /* Symbol type - ELF32_ST_TYPE - st_info */ #define STT_NOTYPE 0 /* not specified */ @@ -364,9 +389,9 @@ typedef struct elf32_sym { #define STT_NUM 5 /* number of symbol types */ #define STT_TLS 6 /* Thread local storage symbol */ #define STT_LOOS 10 /* reserved range for operating */ -#define STT_HIOS 12 /* system specific symbol types */ +#define STT_HIOS 12 /* system specific symbol types */ #define STT_LOPROC 13 /* reserved range for processor */ -#define STT_HIPROC 15 /* specific symbol types */ +#define STT_HIPROC 15 /* specific symbol types */ /* Symbol visibility - ELF32_ST_VISIBILITY - st_other */ #define STV_DEFAULT 0 /* Normal visibility rules */ @@ -374,17 +399,14 @@ typedef struct elf32_sym { #define STV_HIDDEN 2 /* Symbol unavailable in other mods */ #define STV_PROTECTED 3 /* Not preemptible, not exported */ - /* Relocation entry with implicit addend */ -typedef struct -{ +typedef struct { Elf32_Addr r_offset; /* offset of relocation */ Elf32_Word r_info; /* symbol table index and type */ } Elf32_Rel; /* Relocation entry with explicit addend */ -typedef struct -{ +typedef struct { Elf32_Addr r_offset; /* offset of relocation */ Elf32_Word r_info; /* symbol table index and type */ Elf32_Sword r_addend; @@ -396,9 +418,9 @@ typedef struct { } Elf64_Rel; typedef struct { - Elf64_Addr r_offset; /* Location at which to apply the action */ - Elf64_Xword r_info; /* index and type of relocation */ - Elf64_Sxword r_addend; /* Constant addend used to compute value */ + Elf64_Addr r_offset; /* Location at which to apply the action */ + Elf64_Xword r_info; /* index and type of relocation */ + Elf64_Sxword r_addend; /* Constant addend used to compute value */ } Elf64_Rela; /* Extract relocation info - r_info */ @@ -411,13 +433,24 @@ typedef struct { Elf32_Word p_type; /* segment type */ Elf32_Off p_offset; /* segment offset */ Elf32_Addr p_vaddr; /* virtual address of segment */ - Elf32_Addr p_paddr; /* physical address - ignored? */ - Elf32_Word p_filesz; /* number of bytes in file for seg. */ - Elf32_Word p_memsz; /* number of bytes in mem. for seg. */ + Elf32_Addr p_paddr; /* physical address of segment */ + Elf32_Word p_filesz; /* number of bytes in file for seg */ + Elf32_Word p_memsz; /* number of bytes in mem. for seg */ Elf32_Word p_flags; /* flags */ Elf32_Word p_align; /* memory alignment */ } Elf32_Phdr; +typedef struct { + Elf64_Word p_type; /* segment type */ + Elf64_Word p_flags; /* flags */ + Elf64_Off p_offset; /* segment offset */ + Elf64_Addr p_vaddr; /* virtual address of segment */ + Elf64_Addr p_paddr; /* physical address of segment */ + Elf64_Xword p_filesz; /* number of bytes in file for seg */ + Elf64_Xword p_memsz; /* number of bytes in mem. for seg */ + Elf64_Xword p_align; /* memory alignment */ +} Elf64_Phdr; + /* Segment types - p_type */ #define PT_NULL 0 /* unused */ #define PT_LOAD 1 /* loadable segment */ @@ -429,9 +462,9 @@ typedef struct { #define PT_TLS 7 /* Thread local storage template */ #define PT_NUM 8 /* Number of segment types */ #define PT_LOOS 0x60000000 /* reserved range for operating */ -#define PT_HIOS 0x6fffffff /* system specific segment types */ +#define PT_HIOS 0x6fffffff /* system specific segment types */ #define PT_LOPROC 0x70000000 /* reserved range for processor */ -#define PT_HIPROC 0x7fffffff /* specific segment types */ +#define PT_HIPROC 0x7fffffff /* specific segment types */ /* Segment flags - p_flags */ #define PF_X 0x1 /* Executable */ @@ -439,13 +472,11 @@ typedef struct { #define PF_R 0x4 /* Readable */ #define PF_MASKOS 0x0ff00000 /* OS specific segment flags */ #define PF_MASKPROC 0xf0000000 /* reserved bits for processor */ - /* specific segment flags */ + /* specific segment flags */ /* Dynamic structure */ -typedef struct -{ +typedef struct { Elf32_Sword d_tag; /* controls meaning of d_val */ - union - { + union { Elf32_Word d_val; /* Multiple meanings - see d_tag */ Elf32_Addr d_ptr; /* program virtual address */ } d_un; @@ -477,12 +508,12 @@ typedef struct { #define DT_RELAENT 9 /* size of relocation entry */ #define DT_STRSZ 10 /* size of string table */ #define DT_SYMENT 11 /* size of symbol table entry */ -#define DT_INIT 12 /* address of initialization func. */ +#define DT_INIT 12 /* address of initialization func */ #define DT_FINI 13 /* address of termination function */ #define DT_SONAME 14 /* string table offset of shared obj */ #define DT_RPATH 15 /* string table offset of library search path */ -#define DT_SYMBOLIC 16 /* start sym search in shared obj. */ +#define DT_SYMBOLIC 16 /* start sym search in shared obj */ #define DT_REL 17 /* address of rel. tbl. w addends */ #define DT_RELSZ 18 /* size of DT_REL relocation table */ #define DT_RELENT 19 /* size of DT_REL relocation entry */ @@ -500,11 +531,11 @@ typedef struct { #define DT_ENCODING 32 /* Start of encoded range */ #define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ #define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ -#define DT_NUM 34 /* Number used. */ +#define DT_NUM 34 /* Number used */ #define DT_LOOS 0x60000000 /* reserved range for OS */ -#define DT_HIOS 0x6fffffff /* specific dynamic array tags */ +#define DT_HIOS 0x6fffffff /* specific dynamic array tags */ #define DT_LOPROC 0x70000000 /* reserved range for processor */ -#define DT_HIPROC 0x7fffffff /* specific dynamic array tags */ +#define DT_HIPROC 0x7fffffff /* specific dynamic array tags */ /* Dynamic Tag Flags - d_un.d_val */ #define DF_ORIGIN 0x01 /* Object may use DF_ORIGIN */ @@ -525,93 +556,97 @@ unsigned long elf_hash(const unsigned char *name); * but we'll put them in for simplicity. */ -/* Values for Elf32/64_Ehdr.e_flags. */ -#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ +/* Values for Elf32/64_Ehdr.e_flags */ +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ /* Cygnus local bits below */ -#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ -#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag */ /* PowerPC relocations defined by the ABIs */ -#define R_PPC_NONE 0 -#define R_PPC_ADDR32 1 /* 32bit absolute address */ -#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -#define R_PPC_ADDR16 3 /* 16bit absolute address */ -#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -#define R_PPC_ADDR14_BRTAKEN 8 -#define R_PPC_ADDR14_BRNTAKEN 9 -#define R_PPC_REL24 10 /* PC relative 26 bit */ -#define R_PPC_REL14 11 /* PC relative 16 bit */ -#define R_PPC_REL14_BRTAKEN 12 -#define R_PPC_REL14_BRNTAKEN 13 -#define R_PPC_GOT16 14 -#define R_PPC_GOT16_LO 15 -#define R_PPC_GOT16_HI 16 -#define R_PPC_GOT16_HA 17 -#define R_PPC_PLTREL24 18 -#define R_PPC_COPY 19 -#define R_PPC_GLOB_DAT 20 -#define R_PPC_JMP_SLOT 21 -#define R_PPC_RELATIVE 22 -#define R_PPC_LOCAL24PC 23 -#define R_PPC_UADDR32 24 -#define R_PPC_UADDR16 25 -#define R_PPC_REL32 26 -#define R_PPC_PLT32 27 -#define R_PPC_PLTREL32 28 -#define R_PPC_PLT16_LO 29 -#define R_PPC_PLT16_HI 30 -#define R_PPC_PLT16_HA 31 -#define R_PPC_SDAREL16 32 -#define R_PPC_SECTOFF 33 -#define R_PPC_SECTOFF_LO 34 -#define R_PPC_SECTOFF_HI 35 -#define R_PPC_SECTOFF_HA 36 -/* Keep this the last entry. */ -#define R_PPC_NUM 37 - -/* The remaining relocs are from the Embedded ELF ABI, and are not - in the SVR4 ELF ABI. */ -#define R_PPC_EMB_NADDR32 101 -#define R_PPC_EMB_NADDR16 102 -#define R_PPC_EMB_NADDR16_LO 103 -#define R_PPC_EMB_NADDR16_HI 104 -#define R_PPC_EMB_NADDR16_HA 105 -#define R_PPC_EMB_SDAI16 106 -#define R_PPC_EMB_SDA2I16 107 -#define R_PPC_EMB_SDA2REL 108 -#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ -#define R_PPC_EMB_MRKREF 110 -#define R_PPC_EMB_RELSEC16 111 -#define R_PPC_EMB_RELST_LO 112 -#define R_PPC_EMB_RELST_HI 113 -#define R_PPC_EMB_RELST_HA 114 -#define R_PPC_EMB_BIT_FLD 115 -#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ - -/* Diab tool relocations. */ -#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ -#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ -#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ -#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ -#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ -#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ - -/* This is a phony reloc to handle any old fashioned TOC16 references - that may still be in object files. */ -#define R_PPC_TOC16 255 +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 /* 32bit absolute address */ +#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored */ +#define R_PPC_ADDR16 3 /* 16bit absolute address */ +#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ +#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ +#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ +#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 /* PC relative 26 bit */ +#define R_PPC_REL14 11 /* PC relative 16 bit */ +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 +/* Keep this the last entry */ +#define R_PPC_NUM 37 + +/* + * The remaining relocs are from the Embedded ELF ABI, and are not + * in the SVR4 ELF ABI. + */ +#define R_PPC_EMB_NADDR32 101 +#define R_PPC_EMB_NADDR16 102 +#define R_PPC_EMB_NADDR16_LO 103 +#define R_PPC_EMB_NADDR16_HI 104 +#define R_PPC_EMB_NADDR16_HA 105 +#define R_PPC_EMB_SDAI16 106 +#define R_PPC_EMB_SDA2I16 107 +#define R_PPC_EMB_SDA2REL 108 +#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ +#define R_PPC_EMB_MRKREF 110 +#define R_PPC_EMB_RELSEC16 111 +#define R_PPC_EMB_RELST_LO 112 +#define R_PPC_EMB_RELST_HI 113 +#define R_PPC_EMB_RELST_HA 114 +#define R_PPC_EMB_BIT_FLD 115 +#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ + +/* Diab tool relocations */ +#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ +#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ +#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ +#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ +#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ +#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ + +/* + * This is a phony reloc to handle any old fashioned TOC16 references + * that may still be in object files. + */ +#define R_PPC_TOC16 255 /* ARM relocs */ #define R_ARM_NONE 0 /* No reloc */ #define R_ARM_RELATIVE 23 /* Adjust by program base */ /* AArch64 relocs */ -#define R_AARCH64_NONE 0 /* No relocation. */ -#define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */ +#define R_AARCH64_NONE 0 /* No relocation */ +#define R_AARCH64_RELATIVE 1027 /* Adjust by program base */ /* RISC-V relocations */ #define R_RISCV_32 1 diff --git a/include/environment.h b/include/environment.h index 7986a24277..2bd0ad12a6 100644 --- a/include/environment.h +++ b/include/environment.h @@ -314,6 +314,15 @@ int env_load(void); */ int env_save(void); +/** + * env_fix_drivers() - Updates envdriver as per relocation + */ +void env_fix_drivers(void); + +void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr); +int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr); +int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr); + #endif /* DO_DEPS_ONLY */ #endif /* _ENVIRONMENT_H_ */ diff --git a/include/imximage.h b/include/imximage.h index de1ea8ff14..553b852367 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -56,6 +56,7 @@ #define DCD_CHECK_BITS_SET_PARAM 0x14 #define DCD_CHECK_BITS_CLR_PARAM 0x04 +#ifndef __ASSEMBLY__ enum imximage_cmd { CMD_INVALID, CMD_IMAGE_VERSION, @@ -197,4 +198,5 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr, typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len, uint32_t entry_point, uint32_t flash_offset); +#endif /* __ASSEMBLY__ */ #endif /* _IMXIMAGE_H_ */ diff --git a/include/log.h b/include/log.h index 20dc5289c7..3cf08de6d0 100644 --- a/include/log.h +++ b/include/log.h @@ -46,7 +46,7 @@ enum log_category_t { LOGC_CORE, LOGC_DM, /* Core driver-model */ LOGC_DT, /* Device-tree */ - LOGL_EFI, /* EFI implementation */ + LOGC_EFI, /* EFI implementation */ LOGC_COUNT, LOGC_END, diff --git a/include/net.h b/include/net.h index 3101096e9a..3469811aa0 100644 --- a/include/net.h +++ b/include/net.h @@ -238,9 +238,6 @@ void eth_try_another(int first_restart); /* Change the device */ void eth_set_current(void); /* set nterface to ethcur var */ int eth_get_dev_index(void); /* get the device index */ -void eth_parse_enetaddr(const char *addr, uchar *enetaddr); -int eth_env_get_enetaddr(const char *name, uchar *enetaddr); -int eth_env_set_enetaddr(const char *name, const uchar *enetaddr); /** * eth_env_set_enetaddr_by_index() - set the MAC address environment variable diff --git a/include/netdev.h b/include/netdev.h index 86d28ade14..68c6d49cbf 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -117,11 +117,7 @@ static inline int pci_eth_init(bd_t *bis) return num; } -#ifdef CONFIG_DM_ETH -struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id); -#else -struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id); -#endif +struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id); #ifdef CONFIG_PHYLIB struct phy_device; diff --git a/include/pe.h b/include/pe.h index c3a19cef76..e7845bb7d2 100644 --- a/include/pe.h +++ b/include/pe.h @@ -38,11 +38,15 @@ typedef struct _IMAGE_DOS_HEADER { #define IMAGE_DOS_SIGNATURE 0x5A4D /* MZ */ #define IMAGE_NT_SIGNATURE 0x00004550 /* PE00 */ +#define IMAGE_FILE_MACHINE_I386 0x014c #define IMAGE_FILE_MACHINE_ARM 0x01c0 #define IMAGE_FILE_MACHINE_THUMB 0x01c2 #define IMAGE_FILE_MACHINE_ARMNT 0x01c4 #define IMAGE_FILE_MACHINE_AMD64 0x8664 #define IMAGE_FILE_MACHINE_ARM64 0xaa64 +#define IMAGE_FILE_MACHINE_RISCV32 0x5032 +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 + #define IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b #define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b #define IMAGE_SUBSYSTEM_EFI_APPLICATION 10 diff --git a/include/reset.h b/include/reset.h index 7185ade7ac..ae247ceb4f 100644 --- a/include/reset.h +++ b/include/reset.h @@ -60,6 +60,24 @@ struct reset_ctl { unsigned long id; }; +/** + * struct reset_ctl_bulk - A handle to (allowing control of) a bulk of reset + * signals. + * + * Clients provide storage for the reset control bulk. The content of the + * structure is managed solely by the reset API. A reset control bulk struct is + * initialized by "get"ing the reset control bulk struct. + * The reset control bulk struct is passed to all other bulk reset APIs to apply + * the API to all the reset signals in the bulk struct. + * + * @resets: An array of reset signal handles handles. + * @count: The number of reset signal handles in the reset array. + */ +struct reset_ctl_bulk { + struct reset_ctl *resets; + unsigned int count; +}; + #ifdef CONFIG_DM_RESET /** * reset_get_by_index - Get/request a reset signal by integer index. @@ -81,6 +99,22 @@ int reset_get_by_index(struct udevice *dev, int index, struct reset_ctl *reset_ctl); /** + * reset_get_bulk - Get/request all reset signals of a device. + * + * This looks up and requests all reset signals of the client device; each + * device is assumed to have n reset signals associated with it somehow, + * and this function finds and requests all of them in a separate structure. + * The mapping of client device reset signals indices to provider reset signals + * may be via device-tree properties, board-provided mapping tables, or some + * other mechanism. + * + * @dev: The client device. + * @bulk A pointer to a reset control bulk struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk); + +/** * reset_get_by_name - Get/request a reset signal by name. * * This looks up and requests a reset signal. The name is relative to the @@ -132,6 +166,21 @@ int reset_free(struct reset_ctl *reset_ctl); int reset_assert(struct reset_ctl *reset_ctl); /** + * reset_assert_bulk - Assert all reset signals in a reset control bulk struct. + * + * This function will assert the specified reset signals in a reset control + * bulk struct, thus resetting the affected HW module(s). Depending on the + * reset controller hardware, the reset signals will either stay asserted + * until reset_deassert_bulk() is called, or the hardware may autonomously + * clear the reset signals itself. + * + * @bulk: A reset control bulk struct that was previously successfully + * requested by reset_get_bulk(). + * @return 0 if OK, or a negative error code. + */ +int reset_assert_bulk(struct reset_ctl_bulk *bulk); + +/** * reset_deassert - Deassert a reset signal. * * This function will deassert the specified reset signal, thus releasing the @@ -145,6 +194,20 @@ int reset_assert(struct reset_ctl *reset_ctl); int reset_deassert(struct reset_ctl *reset_ctl); /** + * reset_deassert_bulk - Deassert all reset signals in a reset control bulk + * struct. + * + * This function will deassert the specified reset signals in a reset control + * bulk struct, thus releasing the affected HW modules() from reset, and + * allowing them to continue normal operation. + * + * @bulk: A reset control bulk struct that was previously successfully + * requested by reset_get_bulk(). + * @return 0 if OK, or a negative error code. + */ +int reset_deassert_bulk(struct reset_ctl_bulk *bulk); + +/** * reset_release_all - Assert/Free an array of previously requested resets. * * For each reset contained in the reset array, this function will check if @@ -156,6 +219,23 @@ int reset_deassert(struct reset_ctl *reset_ctl); * @return 0 if OK, or a negative error code. */ int reset_release_all(struct reset_ctl *reset_ctl, int count); + +/** + * reset_release_bulk - Assert/Free an array of previously requested reset + * signals in a reset control bulk struct. + * + * For each reset contained in the reset control bulk struct, this function + * will check if reset has been previously requested and then will assert + * and free it. + * + * @bulk: A reset control bulk struct that was previously successfully + * requested by reset_get_bulk(). + * @return 0 if OK, or a negative error code. + */ +static inline int reset_release_bulk(struct reset_ctl_bulk *bulk) +{ + return reset_release_all(bulk->resets, bulk->count); +} #else static inline int reset_get_by_index(struct udevice *dev, int index, struct reset_ctl *reset_ctl) @@ -163,6 +243,12 @@ static inline int reset_get_by_index(struct udevice *dev, int index, return -ENOTSUPP; } +static inline int reset_get_bulk(struct udevice *dev, + struct reset_ctl_bulk *bulk) +{ + return -ENOTSUPP; +} + static inline int reset_get_by_name(struct udevice *dev, const char *name, struct reset_ctl *reset_ctl) { @@ -179,16 +265,30 @@ static inline int reset_assert(struct reset_ctl *reset_ctl) return 0; } +static inline int reset_assert_bulk(struct reset_ctl_bulk *bulk) +{ + return 0; +} + static inline int reset_deassert(struct reset_ctl *reset_ctl) { return 0; } +static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk) +{ + return 0; +} + static inline int reset_release_all(struct reset_ctl *reset_ctl, int count) { return 0; } +static inline int reset_release_bulk(struct reset_ctl_bulk *bulk) +{ + return 0; +} #endif #endif diff --git a/include/s6e63d6.h b/include/s6e63d6.h deleted file mode 100644 index aa583eed1b..0000000000 --- a/include/s6e63d6.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _S6E63D6_H_ -#define _S6E63D6_H_ - -struct s6e63d6 { - unsigned int bus; - unsigned int cs; - unsigned int id; - struct spi_slave *slave; -}; - -extern int s6e63d6_init(struct s6e63d6 *data); -extern int s6e63d6_index(struct s6e63d6 *data, u8 idx); -extern int s6e63d6_param(struct s6e63d6 *data, u16 param); - -#endif diff --git a/include/vxworks.h b/include/vxworks.h index f69b0084ff..39f0a444a2 100644 --- a/include/vxworks.h +++ b/include/vxworks.h @@ -8,10 +8,21 @@ #ifndef _VXWORKS_H_ #define _VXWORKS_H_ +#include <efi_api.h> + +/* + * Physical address of memory base for VxWorks x86 + * This is LOCAL_MEM_LOCAL_ADRS in the VxWorks kernel configuration. + */ +#define VXWORKS_PHYS_MEM_BASE 0x100000 + +/* x86 bootline offset relative to LOCAL_MEM_LOCAL_ADRS in VxWorks */ +#define X86_BOOT_LINE_OFFSET 0x1200 + /* * VxWorks x86 E820 related stuff * - * VxWorks on x86 gets E820 information from pre-defined address @ + * VxWorks on x86 gets E820 information from pre-defined offset @ * 0x4a00 and 0x4000. At 0x4a00 it's an information table defined * by VxWorks and the actual E820 table entries starts from 0x4000. * As defined by the BIOS E820 spec, the maximum number of E820 table @@ -20,13 +31,13 @@ * information that is retrieved from the BIOS E820 call and saved * later for sanity test during the kernel boot-up. */ -#define VXWORKS_E820_DATA_ADDR 0x4000 -#define VXWORKS_E820_INFO_ADDR 0x4a00 +#define E820_DATA_OFFSET 0x4000 +#define E820_INFO_OFFSET 0x4a00 /* E820 info signatiure "SMAP" - System MAP */ #define E820_SIGNATURE 0x534d4150 -struct e820info { +struct e820_info { u32 sign; /* "SMAP" signature */ u32 x0; /* don't care, used by VxWorks */ u32 x1; /* don't care, used by VxWorks */ @@ -37,6 +48,39 @@ struct e820info { u32 error; /* must be zero */ }; +/* + * VxWorks bootloader stores its size at a pre-defined offset @ 0x5004. + * Later when VxWorks kernel boots up and system memory information is + * retrieved from the E820 table, the bootloader size will be subtracted + * from the total system memory size to calculate the size of available + * memory for the OS. + */ +#define BOOT_IMAGE_SIZE_OFFSET 0x5004 + +/* + * When booting from EFI BIOS, VxWorks bootloader stores the EFI GOP + * framebuffer info at a pre-defined offset @ 0x6100. When VxWorks kernel + * boots up, its EFI console driver tries to find such a block and if + * the signature matches, the framebuffer information will be used to + * initialize the driver. + * + * However it is not necessary to prepare an EFI environment for VxWorks's + * EFI console driver to function (eg: EFI loader in U-Boot). If U-Boot has + * already initialized the graphics card and set it to a VESA mode that is + * compatible with EFI GOP, we can simply prepare such a block for VxWorks. + */ +#define EFI_GOP_INFO_OFFSET 0x6100 + +/* EFI GOP info signatiure */ +#define EFI_GOP_INFO_MAGIC 0xfeedface + +struct efi_gop_info { + u32 magic; /* signature */ + struct efi_gop_mode_info info; /* EFI GOP mode info structure */ + phys_addr_t fb_base; /* framebuffer base address */ + u32 fb_size; /* framebuffer size */ +}; + int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); void boot_prep_vxworks(bootm_headers_t *images); void boot_jump_vxworks(bootm_headers_t *images); diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 4c8c2f88f0..8b3ce8ef77 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -12,6 +12,7 @@ #define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 +#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017 #define ZYNQMP_FPGA_OP_INIT (1 << 0) #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 83d75c4fdc..d38780b604 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -1,6 +1,8 @@ config EFI_LOADER bool "Support running EFI Applications in U-Boot" depends on (ARM || X86) && OF_LIBFDT + # We do not support bootefi booting ARMv7 in non-secure mode + depends on !ARMV7_NONSEC # We need EFI_STUB_64BIT to be set on x86_64 with EFI_STUB depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 2a87d9ed77..55c97c0476 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -17,9 +17,10 @@ endif obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o obj-y += efi_memory.o efi_device_path_to_text.o efi_device_path.o -obj-y += efi_file.o efi_variable.o efi_bootmgr.o efi_watchdog.o +obj-y += efi_device_path_utilities.o efi_file.o efi_variable.o efi_bootmgr.o +obj-y += efi_watchdog.o obj-$(CONFIG_LCD) += efi_gop.o obj-$(CONFIG_DM_VIDEO) += efi_gop.o obj-$(CONFIG_PARTITIONS) += efi_disk.o -obj-$(CONFIG_CMD_NET) += efi_net.o +obj-$(CONFIG_NET) += efi_net.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += efi_smbios.o diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 66e26fd63a..1cfdabf6eb 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -26,6 +26,9 @@ static efi_uintn_t efi_tpl = TPL_APPLICATION; /* This list contains all the EFI objects our payload has access to */ LIST_HEAD(efi_obj_list); +/* List of all events */ +LIST_HEAD(efi_events); + /* * If we're running on nasty systems (32bit ARM booting into non-EFI Linux) * we need to do trickery with caches. Since we don't want to break the EFI @@ -56,10 +59,28 @@ static volatile void *efi_gd, *app_gd; static int entry_count; static int nesting_level; +/* GUID of the device tree table */ +const efi_guid_t efi_guid_fdt = EFI_FDT_GUID; /* GUID of the EFI_DRIVER_BINDING_PROTOCOL */ const efi_guid_t efi_guid_driver_binding_protocol = EFI_DRIVER_BINDING_PROTOCOL_GUID; +/* event group ExitBootServices() invoked */ +const efi_guid_t efi_guid_event_group_exit_boot_services = + EFI_EVENT_GROUP_EXIT_BOOT_SERVICES; +/* event group SetVirtualAddressMap() invoked */ +const efi_guid_t efi_guid_event_group_virtual_address_change = + EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE; +/* event group memory map changed */ +const efi_guid_t efi_guid_event_group_memory_map_change = + EFI_EVENT_GROUP_MEMORY_MAP_CHANGE; +/* event group boot manager about to boot */ +const efi_guid_t efi_guid_event_group_ready_to_boot = + EFI_EVENT_GROUP_READY_TO_BOOT; +/* event group ResetSystem() invoked (before ExitBootServices) */ +const efi_guid_t efi_guid_event_group_reset_system = + EFI_EVENT_GROUP_RESET_SYSTEM; + static efi_status_t EFIAPI efi_disconnect_controller( efi_handle_t controller_handle, efi_handle_t driver_image_handle, @@ -121,6 +142,7 @@ static const char *indent_string(int level) { const char *indent = " "; const int max = strlen(indent); + level = min(max, level * 2); return &indent[max - level]; } @@ -154,7 +176,7 @@ const char *__efi_nesting_dec(void) * @event event to signal * @check_tpl check the TPL level */ -void efi_signal_event(struct efi_event *event, bool check_tpl) +static void efi_queue_event(struct efi_event *event, bool check_tpl) { if (event->notify_function) { event->is_queued = true; @@ -168,6 +190,50 @@ void efi_signal_event(struct efi_event *event, bool check_tpl) } /* + * Signal an EFI event. + * + * This function signals an event. If the event belongs to an event group + * all events of the group are signaled. If they are of type EVT_NOTIFY_SIGNAL + * their notification function is queued. + * + * For the SignalEvent service see efi_signal_event_ext. + * + * @event event to signal + * @check_tpl check the TPL level + */ +void efi_signal_event(struct efi_event *event, bool check_tpl) +{ + if (event->group) { + struct efi_event *evt; + + /* + * The signaled state has to set before executing any + * notification function + */ + list_for_each_entry(evt, &efi_events, link) { + if (!evt->group || guidcmp(evt->group, event->group)) + continue; + if (evt->is_signaled) + continue; + evt->is_signaled = true; + if (evt->type & EVT_NOTIFY_SIGNAL && + evt->notify_function) + evt->is_queued = true; + } + list_for_each_entry(evt, &efi_events, link) { + if (!evt->group || guidcmp(evt->group, event->group)) + continue; + if (evt->is_queued) + efi_queue_event(evt, check_tpl); + } + } else if (!event->is_signaled) { + event->is_signaled = true; + if (event->type & EVT_NOTIFY_SIGNAL) + efi_queue_event(event, check_tpl); + } +} + +/* * Raise the task priority level. * * This function implements the RaiseTpl service. @@ -212,6 +278,11 @@ static void EFIAPI efi_restore_tpl(efi_uintn_t old_tpl) if (efi_tpl > TPL_HIGH_LEVEL) efi_tpl = TPL_HIGH_LEVEL; + /* + * Lowering the TPL may have made queued events eligible for execution. + */ + efi_timer_check(); + EFI_EXIT(EFI_SUCCESS); } @@ -255,7 +326,7 @@ static efi_status_t EFIAPI efi_free_pages_ext(uint64_t memory, { efi_status_t r; - EFI_ENTRY("%"PRIx64", 0x%zx", memory, pages); + EFI_ENTRY("%" PRIx64 ", 0x%zx", memory, pages); r = efi_free_pages(memory, pages); return EFI_EXIT(r); } @@ -470,10 +541,23 @@ void efi_delete_handle(struct efi_object *obj) } /* - * Our event capabilities are very limited. Only a small limited - * number of events is allowed to coexist. + * Check if a pointer is a valid event. + * + * @event pointer to check + * @return status code */ -static struct efi_event efi_events[16]; +static efi_status_t efi_is_event(const struct efi_event *event) +{ + const struct efi_event *evt; + + if (!event) + return EFI_INVALID_PARAMETER; + list_for_each_entry(evt, &efi_events, link) { + if (evt == event) + return EFI_SUCCESS; + } + return EFI_INVALID_PARAMETER; +} /* * Create an event. @@ -494,9 +578,10 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), - void *notify_context, struct efi_event **event) + void *notify_context, efi_guid_t *group, + struct efi_event **event) { - int i; + struct efi_event *evt; if (event == NULL) return EFI_INVALID_PARAMETER; @@ -504,25 +589,25 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, if ((type & EVT_NOTIFY_SIGNAL) && (type & EVT_NOTIFY_WAIT)) return EFI_INVALID_PARAMETER; - if ((type & (EVT_NOTIFY_SIGNAL|EVT_NOTIFY_WAIT)) && + if ((type & (EVT_NOTIFY_SIGNAL | EVT_NOTIFY_WAIT)) && notify_function == NULL) return EFI_INVALID_PARAMETER; - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) { - if (efi_events[i].type) - continue; - efi_events[i].type = type; - efi_events[i].notify_tpl = notify_tpl; - efi_events[i].notify_function = notify_function; - efi_events[i].notify_context = notify_context; - /* Disable timers on bootup */ - efi_events[i].trigger_next = -1ULL; - efi_events[i].is_queued = false; - efi_events[i].is_signaled = false; - *event = &efi_events[i]; - return EFI_SUCCESS; - } - return EFI_OUT_OF_RESOURCES; + evt = calloc(1, sizeof(struct efi_event)); + if (!evt) + return EFI_OUT_OF_RESOURCES; + evt->type = type; + evt->notify_tpl = notify_tpl; + evt->notify_function = notify_function; + evt->notify_context = notify_context; + evt->group = group; + /* Disable timers on bootup */ + evt->trigger_next = -1ULL; + evt->is_queued = false; + evt->is_signaled = false; + list_add_tail(&evt->link, &efi_events); + *event = evt; + return EFI_SUCCESS; } /* @@ -551,10 +636,8 @@ efi_status_t EFIAPI efi_create_event_ex(uint32_t type, efi_uintn_t notify_tpl, { EFI_ENTRY("%d, 0x%zx, %p, %p, %pUl", type, notify_tpl, notify_function, notify_context, event_group); - if (event_group) - return EFI_EXIT(EFI_UNSUPPORTED); return EFI_EXIT(efi_create_event(type, notify_tpl, notify_function, - notify_context, event)); + notify_context, event_group, event)); } /* @@ -581,10 +664,9 @@ static efi_status_t EFIAPI efi_create_event_ext( EFI_ENTRY("%d, 0x%zx, %p, %p", type, notify_tpl, notify_function, notify_context); return EFI_EXIT(efi_create_event(type, notify_tpl, notify_function, - notify_context, event)); + notify_context, NULL, event)); } - /* * Check if a timer event has occurred or a queued notification function should * be called. @@ -594,30 +676,26 @@ static efi_status_t EFIAPI efi_create_event_ext( */ void efi_timer_check(void) { - int i; + struct efi_event *evt; u64 now = timer_get_us(); - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) { - if (!efi_events[i].type) - continue; - if (efi_events[i].is_queued) - efi_signal_event(&efi_events[i], true); - if (!(efi_events[i].type & EVT_TIMER) || - now < efi_events[i].trigger_next) + list_for_each_entry(evt, &efi_events, link) { + if (evt->is_queued) + efi_queue_event(evt, true); + if (!(evt->type & EVT_TIMER) || now < evt->trigger_next) continue; - switch (efi_events[i].trigger_type) { + switch (evt->trigger_type) { case EFI_TIMER_RELATIVE: - efi_events[i].trigger_type = EFI_TIMER_STOP; + evt->trigger_type = EFI_TIMER_STOP; break; case EFI_TIMER_PERIODIC: - efi_events[i].trigger_next += - efi_events[i].trigger_time; + evt->trigger_next += evt->trigger_time; break; default: continue; } - efi_events[i].is_signaled = true; - efi_signal_event(&efi_events[i], true); + evt->is_signaled = false; + efi_signal_event(evt, true); } WATCHDOG_RESET(); } @@ -636,7 +714,9 @@ void efi_timer_check(void) efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, uint64_t trigger_time) { - int i; + /* Check that the event is valid */ + if (efi_is_event(event) != EFI_SUCCESS || !(event->type & EVT_TIMER)) + return EFI_INVALID_PARAMETER; /* * The parameter defines a multiple of 100ns. @@ -644,30 +724,21 @@ efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, */ do_div(trigger_time, 10); - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) { - if (event != &efi_events[i]) - continue; - - if (!(event->type & EVT_TIMER)) - break; - switch (type) { - case EFI_TIMER_STOP: - event->trigger_next = -1ULL; - break; - case EFI_TIMER_PERIODIC: - case EFI_TIMER_RELATIVE: - event->trigger_next = - timer_get_us() + trigger_time; - break; - default: - return EFI_INVALID_PARAMETER; - } - event->trigger_type = type; - event->trigger_time = trigger_time; - event->is_signaled = false; - return EFI_SUCCESS; + switch (type) { + case EFI_TIMER_STOP: + event->trigger_next = -1ULL; + break; + case EFI_TIMER_PERIODIC: + case EFI_TIMER_RELATIVE: + event->trigger_next = timer_get_us() + trigger_time; + break; + default: + return EFI_INVALID_PARAMETER; } - return EFI_INVALID_PARAMETER; + event->trigger_type = type; + event->trigger_time = trigger_time; + event->is_signaled = false; + return EFI_SUCCESS; } /* @@ -686,7 +757,7 @@ static efi_status_t EFIAPI efi_set_timer_ext(struct efi_event *event, enum efi_timer_delay type, uint64_t trigger_time) { - EFI_ENTRY("%p, %d, %"PRIx64, event, type, trigger_time); + EFI_ENTRY("%p, %d, %" PRIx64, event, type, trigger_time); return EFI_EXIT(efi_set_timer(event, type, trigger_time)); } @@ -706,7 +777,7 @@ static efi_status_t EFIAPI efi_wait_for_event(efi_uintn_t num_events, struct efi_event **event, efi_uintn_t *index) { - int i, j; + int i; EFI_ENTRY("%zd, %p, %p", num_events, event, index); @@ -717,16 +788,12 @@ static efi_status_t EFIAPI efi_wait_for_event(efi_uintn_t num_events, if (efi_tpl != TPL_APPLICATION) return EFI_EXIT(EFI_UNSUPPORTED); for (i = 0; i < num_events; ++i) { - for (j = 0; j < ARRAY_SIZE(efi_events); ++j) { - if (event[i] == &efi_events[j]) - goto known_event; - } - return EFI_EXIT(EFI_INVALID_PARAMETER); -known_event: + if (efi_is_event(event[i]) != EFI_SUCCESS) + return EFI_EXIT(EFI_INVALID_PARAMETER); if (!event[i]->type || event[i]->type & EVT_NOTIFY_SIGNAL) return EFI_EXIT(EFI_INVALID_PARAMETER); if (!event[i]->is_signaled) - efi_signal_event(event[i], true); + efi_queue_event(event[i], true); } /* Wait for signal */ @@ -766,19 +833,10 @@ out: */ static efi_status_t EFIAPI efi_signal_event_ext(struct efi_event *event) { - int i; - EFI_ENTRY("%p", event); - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) { - if (event != &efi_events[i]) - continue; - if (event->is_signaled) - break; - event->is_signaled = true; - if (event->type & EVT_NOTIFY_SIGNAL) - efi_signal_event(event, true); - break; - } + if (efi_is_event(event) != EFI_SUCCESS) + return EFI_EXIT(EFI_INVALID_PARAMETER); + efi_signal_event(event, true); return EFI_EXIT(EFI_SUCCESS); } @@ -794,19 +852,12 @@ static efi_status_t EFIAPI efi_signal_event_ext(struct efi_event *event) */ static efi_status_t EFIAPI efi_close_event(struct efi_event *event) { - int i; - EFI_ENTRY("%p", event); - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) { - if (event == &efi_events[i]) { - event->type = 0; - event->trigger_next = -1ULL; - event->is_queued = false; - event->is_signaled = false; - return EFI_EXIT(EFI_SUCCESS); - } - } - return EFI_EXIT(EFI_INVALID_PARAMETER); + if (efi_is_event(event) != EFI_SUCCESS) + return EFI_EXIT(EFI_INVALID_PARAMETER); + list_del(&event->link); + free(event); + return EFI_EXIT(EFI_SUCCESS); } /* @@ -816,29 +867,26 @@ static efi_status_t EFIAPI efi_close_event(struct efi_event *event) * See the Unified Extensible Firmware Interface (UEFI) specification * for details. * - * If an event is not signaled yet the notification function is queued. + * If an event is not signaled yet, the notification function is queued. + * The signaled state is cleared. * * @event event to check * @return status code */ static efi_status_t EFIAPI efi_check_event(struct efi_event *event) { - int i; - EFI_ENTRY("%p", event); efi_timer_check(); - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) { - if (event != &efi_events[i]) - continue; - if (!event->type || event->type & EVT_NOTIFY_SIGNAL) - break; - if (!event->is_signaled) - efi_signal_event(event, true); - if (event->is_signaled) - return EFI_EXIT(EFI_SUCCESS); - return EFI_EXIT(EFI_NOT_READY); + if (efi_is_event(event) != EFI_SUCCESS || + event->type & EVT_NOTIFY_SIGNAL) + return EFI_EXIT(EFI_INVALID_PARAMETER); + if (!event->is_signaled) + efi_queue_event(event, true); + if (event->is_signaled) { + event->is_signaled = false; + return EFI_EXIT(EFI_SUCCESS); } - return EFI_EXIT(EFI_INVALID_PARAMETER); + return EFI_EXIT(EFI_NOT_READY); } /* @@ -1259,7 +1307,7 @@ static efi_status_t efi_locate_handle( /* Count how much space we need */ list_for_each_entry(efiobj, &efi_obj_list, link) { if (!efi_search(search_type, protocol, search_key, efiobj)) - size += sizeof(void*); + size += sizeof(void *); } if (*buffer_size < size) { @@ -1310,7 +1358,7 @@ static efi_status_t EFIAPI efi_locate_handle_ext( static void efi_remove_configuration_table(int i) { struct efi_configuration_table *this = &efi_conf_table[i]; - struct efi_configuration_table *next = &efi_conf_table[i+1]; + struct efi_configuration_table *next = &efi_conf_table[i + 1]; struct efi_configuration_table *end = &efi_conf_table[systab.nr_tables]; memmove(this, next, (ulong)end - (ulong)next); @@ -1327,10 +1375,15 @@ static void efi_remove_configuration_table(int i) * @table table to be installed * @return status code */ -efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table) +efi_status_t efi_install_configuration_table(const efi_guid_t *guid, + void *table) { + struct efi_event *evt; int i; + if (!guid) + return EFI_INVALID_PARAMETER; + /* Check for guid override */ for (i = 0; i < systab.nr_tables; i++) { if (!guidcmp(guid, &efi_conf_table[i].guid)) { @@ -1338,7 +1391,7 @@ efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table efi_conf_table[i].table = table; else efi_remove_configuration_table(i); - return EFI_SUCCESS; + goto out; } } @@ -1354,6 +1407,15 @@ efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table efi_conf_table[i].table = table; systab.nr_tables = i + 1; +out: + /* Notify that the configuration table was changed */ + list_for_each_entry(evt, &efi_events, link) { + if (evt->group && !guidcmp(evt->group, guid)) { + efi_signal_event(evt, false); + break; + } + } + return EFI_SUCCESS; } @@ -1420,14 +1482,15 @@ efi_status_t efi_setup_loaded_image( if (ret != EFI_SUCCESS) goto failure; - ret = efi_add_protocol(obj->handle, &efi_guid_console_control, - (void *)&efi_console_control); + ret = efi_add_protocol(obj->handle, + &efi_guid_device_path_to_text_protocol, + (void *)&efi_device_path_to_text); if (ret != EFI_SUCCESS) goto failure; ret = efi_add_protocol(obj->handle, - &efi_guid_device_path_to_text_protocol, - (void *)&efi_device_path_to_text); + &efi_guid_device_path_utilities_protocol, + (void *)&efi_device_path_utilities); if (ret != EFI_SUCCESS) goto failure; @@ -1450,7 +1513,7 @@ efi_status_t efi_load_image_from_path(struct efi_device_path *file_path, struct efi_file_info *info = NULL; struct efi_file_handle *f; static efi_status_t ret; - uint64_t bs; + efi_uintn_t bs; f = efi_file_from_path(file_path); if (!f) @@ -1471,7 +1534,8 @@ efi_status_t efi_load_image_from_path(struct efi_device_path *file_path, if (ret) goto error; - EFI_CALL(ret = f->read(f, &info->file_size, *buffer)); + bs = info->file_size; + EFI_CALL(ret = f->read(f, &bs, *buffer)); error: free(info); @@ -1505,18 +1569,37 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, efi_handle_t parent_image, struct efi_device_path *file_path, void *source_buffer, - unsigned long source_size, + efi_uintn_t source_size, efi_handle_t *image_handle) { struct efi_loaded_image *info; struct efi_object *obj; efi_status_t ret; - EFI_ENTRY("%d, %p, %pD, %p, %ld, %p", boot_policy, parent_image, + EFI_ENTRY("%d, %p, %pD, %p, %zd, %p", boot_policy, parent_image, file_path, source_buffer, source_size, image_handle); + if (!image_handle || !parent_image) { + ret = EFI_INVALID_PARAMETER; + goto error; + } + + if (!source_buffer && !file_path) { + ret = EFI_NOT_FOUND; + goto error; + } + info = calloc(1, sizeof(*info)); + if (!info) { + ret = EFI_OUT_OF_RESOURCES; + goto error; + } obj = calloc(1, sizeof(*obj)); + if (!obj) { + free(info); + ret = EFI_OUT_OF_RESOURCES; + goto error; + } if (!source_buffer) { struct efi_device_path *dp, *fp; @@ -1552,6 +1635,7 @@ static efi_status_t EFIAPI efi_load_image(bool boot_policy, failure: free(info); efi_delete_handle(obj); +error: return EFI_EXIT(ret); } @@ -1635,8 +1719,9 @@ static efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, * @return status code */ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, - efi_status_t exit_status, unsigned long exit_data_size, - int16_t *exit_data) + efi_status_t exit_status, + unsigned long exit_data_size, + int16_t *exit_data) { /* * We require that the handle points to the original loaded @@ -1649,7 +1734,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, * TODO: We should call the unload procedure of the loaded * image protocol. */ - struct efi_loaded_image *loaded_image_info = (void*)image_handle; + struct efi_loaded_image *loaded_image_info = (void *)image_handle; EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status, exit_data_size, exit_data); @@ -1724,7 +1809,7 @@ static void efi_exit_caches(void) static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle, unsigned long map_key) { - int i; + struct efi_event *evt; EFI_ENTRY("%p, %ld", image_handle, map_key); @@ -1735,12 +1820,19 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle, if (!systab.boottime) return EFI_EXIT(EFI_SUCCESS); + /* Add related events to the event group */ + list_for_each_entry(evt, &efi_events, link) { + if (evt->type == EVT_SIGNAL_EXIT_BOOT_SERVICES) + evt->group = &efi_guid_event_group_exit_boot_services; + } /* Notify that ExitBootServices is invoked. */ - for (i = 0; i < ARRAY_SIZE(efi_events); ++i) { - if (efi_events[i].type != EVT_SIGNAL_EXIT_BOOT_SERVICES) - continue; - efi_events[i].is_signaled = true; - efi_signal_event(&efi_events[i], false); + list_for_each_entry(evt, &efi_events, link) { + if (evt->group && + !guidcmp(evt->group, + &efi_guid_event_group_exit_boot_services)) { + efi_signal_event(evt, false); + break; + } } /* TODO Should persist EFI variables here */ @@ -1786,7 +1878,8 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle, */ static efi_status_t EFIAPI efi_get_next_monotonic_count(uint64_t *count) { - static uint64_t mono = 0; + static uint64_t mono; + EFI_ENTRY("%p", count); *count = mono++; return EFI_EXIT(EFI_SUCCESS); @@ -1827,7 +1920,7 @@ static efi_status_t EFIAPI efi_set_watchdog_timer(unsigned long timeout, unsigned long data_size, uint16_t *watchdog_data) { - EFI_ENTRY("%ld, 0x%"PRIx64", %ld, %p", timeout, watchdog_code, + EFI_ENTRY("%ld, 0x%" PRIx64 ", %ld, %p", timeout, watchdog_code, data_size, watchdog_data); return EFI_EXIT(efi_set_watchdog(timeout)); } @@ -1892,8 +1985,8 @@ out: * @entry_count number of entries available in the buffer * @return status code */ -static efi_status_t EFIAPI efi_open_protocol_information(efi_handle_t handle, - const efi_guid_t *protocol, +static efi_status_t EFIAPI efi_open_protocol_information( + efi_handle_t handle, const efi_guid_t *protocol, struct efi_open_protocol_info_entry **entry_buffer, efi_uintn_t *entry_count) { @@ -2126,7 +2219,7 @@ static efi_status_t EFIAPI efi_locate_device_path( } /* Find end of device path */ - len = efi_dp_size(*device_path); + len = efi_dp_instance_size(*device_path); /* Get all handles implementing the protocol */ ret = EFI_CALL(efi_locate_handle_buffer(BY_PROTOCOL, protocol, NULL, @@ -2141,7 +2234,7 @@ static efi_status_t EFIAPI efi_locate_device_path( if (ret != EFI_SUCCESS) continue; dp = (struct efi_device_path *)handler->protocol_interface; - len_dp = efi_dp_size(dp); + len_dp = efi_dp_instance_size(dp); /* * This handle can only be a better fit * if its device path length is longer than the best fit and @@ -2878,15 +2971,16 @@ static const struct efi_boot_services efi_boot_services = { .protocols_per_handle = efi_protocols_per_handle, .locate_handle_buffer = efi_locate_handle_buffer, .locate_protocol = efi_locate_protocol, - .install_multiple_protocol_interfaces = efi_install_multiple_protocol_interfaces, - .uninstall_multiple_protocol_interfaces = efi_uninstall_multiple_protocol_interfaces, + .install_multiple_protocol_interfaces = + efi_install_multiple_protocol_interfaces, + .uninstall_multiple_protocol_interfaces = + efi_uninstall_multiple_protocol_interfaces, .calculate_crc32 = efi_calculate_crc32, .copy_mem = efi_copy_mem, .set_mem = efi_set_mem, .create_event_ex = efi_create_event_ex, }; - static uint16_t __efi_runtime_data firmware_vendor[] = L"Das U-Boot"; struct efi_system_table __efi_runtime_data systab = { @@ -2896,11 +2990,11 @@ struct efi_system_table __efi_runtime_data systab = { .headersize = sizeof(struct efi_table_hdr), }, .fw_vendor = (long)firmware_vendor, - .con_in = (void*)&efi_con_in, - .con_out = (void*)&efi_con_out, - .std_err = (void*)&efi_con_out, - .runtime = (void*)&efi_runtime_services, - .boottime = (void*)&efi_boot_services, + .con_in = (void *)&efi_con_in, + .con_out = (void *)&efi_con_out, + .std_err = (void *)&efi_con_out, + .runtime = (void *)&efi_runtime_services, + .boottime = (void *)&efi_boot_services, .nr_tables = 0, - .tables = (void*)efi_conf_table, + .tables = (void *)efi_conf_table, }; diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 28d63635ec..5d1a9a8081 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -45,7 +45,6 @@ static struct cout_mode efi_cout_modes[] = { }, }; -const efi_guid_t efi_guid_console_control = CONSOLE_CONTROL_GUID; const efi_guid_t efi_guid_text_output_protocol = EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID; const efi_guid_t efi_guid_text_input_protocol = @@ -54,43 +53,6 @@ const efi_guid_t efi_guid_text_input_protocol = #define cESC '\x1b' #define ESC "\x1b" -static efi_status_t EFIAPI efi_cin_get_mode( - struct efi_console_control_protocol *this, - int *mode, char *uga_exists, char *std_in_locked) -{ - EFI_ENTRY("%p, %p, %p, %p", this, mode, uga_exists, std_in_locked); - - if (mode) - *mode = EFI_CONSOLE_MODE_TEXT; - if (uga_exists) - *uga_exists = 0; - if (std_in_locked) - *std_in_locked = 0; - - return EFI_EXIT(EFI_SUCCESS); -} - -static efi_status_t EFIAPI efi_cin_set_mode( - struct efi_console_control_protocol *this, int mode) -{ - EFI_ENTRY("%p, %d", this, mode); - return EFI_EXIT(EFI_UNSUPPORTED); -} - -static efi_status_t EFIAPI efi_cin_lock_std_in( - struct efi_console_control_protocol *this, - uint16_t *password) -{ - EFI_ENTRY("%p, %p", this, password); - return EFI_EXIT(EFI_UNSUPPORTED); -} - -struct efi_console_control_protocol efi_console_control = { - .get_mode = efi_cin_get_mode, - .set_mode = efi_cin_set_mode, - .lock_std_in = efi_cin_lock_std_in, -}; - /* Default to mode 0 */ static struct simple_text_output_mode efi_con_mode = { .max_mode = 1, @@ -399,6 +361,48 @@ static efi_status_t EFIAPI efi_cin_reset( return EFI_EXIT(EFI_UNSUPPORTED); } +/* + * Analyze modifiers (shift, alt, ctrl) for function keys. + * This gets called when we have already parsed CSI. + * + * @modifiers: bitmask (shift, alt, ctrl) + * @return: the unmodified code + */ +static char skip_modifiers(int *modifiers) +{ + char c, mod = 0, ret = 0; + + c = getc(); + + if (c != ';') { + ret = c; + if (c == '~') + goto out; + c = getc(); + } + for (;;) { + switch (c) { + case '0'...'9': + mod *= 10; + mod += c - '0'; + /* fall through */ + case ';': + c = getc(); + break; + default: + goto out; + } + } +out: + if (mod) + --mod; + if (modifiers) + *modifiers = mod; + if (!ret) + ret = c; + return ret; +} + static efi_status_t EFIAPI efi_cin_read_key_stroke( struct efi_simple_input_interface *this, struct efi_input_key *key) @@ -421,14 +425,21 @@ static efi_status_t EFIAPI efi_cin_read_key_stroke( ch = getc(); if (ch == cESC) { - /* Escape Sequence */ + /* + * Xterm Control Sequences + * https://www.xfree86.org/4.8.0/ctlseqs.html + */ ch = getc(); switch (ch) { case cESC: /* ESC */ pressed_key.scan_code = 23; break; case 'O': /* F1 - F4 */ - pressed_key.scan_code = getc() - 'P' + 11; + ch = getc(); + /* skip modifiers */ + if (ch <= '9') + ch = getc(); + pressed_key.scan_code = ch - 'P' + 11; break; case 'a'...'z': ch = ch - 'a'; @@ -445,17 +456,51 @@ static efi_status_t EFIAPI efi_cin_read_key_stroke( case 'H': /* Home */ pressed_key.scan_code = 5; break; - case '1': /* F5 - F8 */ - pressed_key.scan_code = getc() - '0' + 11; - getc(); + case '1': + ch = skip_modifiers(NULL); + switch (ch) { + case '1'...'5': /* F1 - F5 */ + pressed_key.scan_code = ch - '1' + 11; + break; + case '7'...'9': /* F6 - F8 */ + pressed_key.scan_code = ch - '7' + 16; + break; + case 'A'...'D': /* up, down right, left */ + pressed_key.scan_code = ch - 'A' + 1; + break; + case 'F': + pressed_key.scan_code = 6; /* End */ + break; + case 'H': + pressed_key.scan_code = 5; /* Home */ + break; + } break; - case '2': /* F9 - F12 */ - pressed_key.scan_code = getc() - '0' + 19; - getc(); + case '2': + ch = skip_modifiers(NULL); + switch (ch) { + case '0'...'1': /* F9 - F10 */ + pressed_key.scan_code = ch - '0' + 19; + break; + case '3'...'4': /* F11 - F12 */ + pressed_key.scan_code = ch - '3' + 21; + break; + case '~': /* INS */ + pressed_key.scan_code = 7; + break; + } break; case '3': /* DEL */ pressed_key.scan_code = 8; - getc(); + skip_modifiers(NULL); + break; + case '5': /* PG UP */ + pressed_key.scan_code = 9; + skip_modifiers(NULL); + break; + case '6': /* PG DOWN */ + pressed_key.scan_code = 10; + skip_modifiers(NULL); break; } break; @@ -464,7 +509,8 @@ static efi_status_t EFIAPI efi_cin_read_key_stroke( /* Backspace */ ch = 0x08; } - pressed_key.unicode_char = ch; + if (!pressed_key.scan_code) + pressed_key.unicode_char = ch; *key = pressed_key; return EFI_EXIT(EFI_SUCCESS); @@ -506,18 +552,10 @@ static void EFIAPI efi_console_timer_notify(struct efi_event *event, int efi_console_register(void) { efi_status_t r; - struct efi_object *efi_console_control_obj; struct efi_object *efi_console_output_obj; struct efi_object *efi_console_input_obj; /* Create handles */ - r = efi_create_handle((efi_handle_t *)&efi_console_control_obj); - if (r != EFI_SUCCESS) - goto out_of_memory; - r = efi_add_protocol(efi_console_control_obj->handle, - &efi_guid_console_control, &efi_console_control); - if (r != EFI_SUCCESS) - goto out_of_memory; r = efi_create_handle((efi_handle_t *)&efi_console_output_obj); if (r != EFI_SUCCESS) goto out_of_memory; @@ -534,14 +572,14 @@ int efi_console_register(void) goto out_of_memory; /* Create console events */ - r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK, - efi_key_notify, NULL, &efi_con_in.wait_for_key); + r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK, efi_key_notify, + NULL, NULL, &efi_con_in.wait_for_key); if (r != EFI_SUCCESS) { printf("ERROR: Failed to register WaitForKey event\n"); return r; } r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, - efi_console_timer_notify, NULL, + efi_console_timer_notify, NULL, NULL, &console_timer_event); if (r != EFI_SUCCESS) { printf("ERROR: Failed to register console event\n"); diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index 3c735e60d3..634dacf41b 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -66,6 +66,7 @@ static void *dp_alloc(size_t sz) return NULL; } + memset(buf, 0, sz); return buf; } @@ -148,7 +149,7 @@ static struct efi_object *find_obj(struct efi_device_path *dp, bool short_path, struct efi_device_path **rem) { struct efi_object *efiobj; - unsigned int dp_size = efi_dp_size(dp); + efi_uintn_t dp_size = efi_dp_instance_size(dp); list_for_each_entry(efiobj, &efi_obj_list, link) { struct efi_handler *handler; @@ -169,11 +170,12 @@ static struct efi_object *find_obj(struct efi_device_path *dp, bool short_path, * the caller. */ *rem = ((void *)dp) + - efi_dp_size(obj_dp); + efi_dp_instance_size(obj_dp); return efiobj; } else { /* Only return on exact matches */ - if (efi_dp_size(obj_dp) == dp_size) + if (efi_dp_instance_size(obj_dp) == + dp_size) return efiobj; } } @@ -228,11 +230,13 @@ const struct efi_device_path *efi_dp_last_node(const struct efi_device_path *dp) return ret; } -/* return size not including End node: */ -unsigned efi_dp_size(const struct efi_device_path *dp) +/* get size of the first device path instance excluding end node */ +efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp) { - unsigned sz = 0; + efi_uintn_t sz = 0; + if (!dp || dp->type == DEVICE_PATH_TYPE_END) + return 0; while (dp) { sz += dp->length; dp = efi_dp_next(dp); @@ -241,10 +245,25 @@ unsigned efi_dp_size(const struct efi_device_path *dp) return sz; } +/* get size of multi-instance device path excluding end node */ +efi_uintn_t efi_dp_size(const struct efi_device_path *dp) +{ + const struct efi_device_path *p = dp; + + if (!p) + return 0; + while (p->type != DEVICE_PATH_TYPE_END || + p->sub_type != DEVICE_PATH_SUB_TYPE_END) + p = (void *)p + p->length; + + return (void *)p - (void *)dp; +} + +/* copy multi-instance device path */ struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp) { struct efi_device_path *ndp; - unsigned sz = efi_dp_size(dp) + sizeof(END); + size_t sz = efi_dp_size(dp) + sizeof(END); if (!dp) return NULL; @@ -262,7 +281,10 @@ struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1, { struct efi_device_path *ret; - if (!dp1) { + if (!dp1 && !dp2) { + /* return an end node */ + ret = efi_dp_dup(&END); + } else if (!dp1) { ret = efi_dp_dup(dp2); } else if (!dp2) { ret = efi_dp_dup(dp1); @@ -274,8 +296,8 @@ struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1, if (!p) return NULL; memcpy(p, dp1, sz1); - memcpy(p + sz1, dp2, sz2); - memcpy(p + sz1 + sz2, &END, sizeof(END)); + /* the end node of the second device path has to be retained */ + memcpy(p + sz1, dp2, sz2 + sizeof(END)); ret = p; } @@ -292,7 +314,7 @@ struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, } else if (!node) { ret = efi_dp_dup(dp); } else if (!dp) { - unsigned sz = node->length; + size_t sz = node->length; void *p = dp_alloc(sz + sizeof(END)); if (!p) return NULL; @@ -301,7 +323,7 @@ struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, ret = p; } else { /* both dp and node are non-null */ - unsigned sz = efi_dp_size(dp); + size_t sz = efi_dp_size(dp); void *p = dp_alloc(sz + node->length + sizeof(END)); if (!p) return NULL; @@ -314,6 +336,85 @@ struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, return ret; } +struct efi_device_path *efi_dp_create_device_node(const u8 type, + const u8 sub_type, + const u16 length) +{ + struct efi_device_path *ret; + + ret = dp_alloc(length); + if (!ret) + return ret; + ret->type = type; + ret->sub_type = sub_type; + ret->length = length; + return ret; +} + +struct efi_device_path *efi_dp_append_instance( + const struct efi_device_path *dp, + const struct efi_device_path *dpi) +{ + size_t sz, szi; + struct efi_device_path *p, *ret; + + if (!dpi) + return NULL; + if (!dp) + return efi_dp_dup(dpi); + sz = efi_dp_size(dp); + szi = efi_dp_instance_size(dpi); + p = dp_alloc(sz + szi + 2 * sizeof(END)); + if (!p) + return NULL; + ret = p; + memcpy(p, dp, sz + sizeof(END)); + p = (void *)p + sz; + p->sub_type = DEVICE_PATH_SUB_TYPE_INSTANCE_END; + p = (void *)p + sizeof(END); + memcpy(p, dpi, szi); + p = (void *)p + szi; + memcpy(p, &END, sizeof(END)); + return ret; +} + +struct efi_device_path *efi_dp_get_next_instance(struct efi_device_path **dp, + efi_uintn_t *size) +{ + size_t sz; + struct efi_device_path *p; + + if (size) + *size = 0; + if (!dp || !*dp) + return NULL; + p = *dp; + sz = efi_dp_instance_size(*dp); + p = dp_alloc(sz + sizeof(END)); + if (!p) + return NULL; + memcpy(p, *dp, sz + sizeof(END)); + *dp = (void *)*dp + sz; + if ((*dp)->sub_type == DEVICE_PATH_SUB_TYPE_INSTANCE_END) + *dp = (void *)*dp + sizeof(END); + else + *dp = NULL; + if (size) + *size = sz + sizeof(END); + return p; +} + +bool efi_dp_is_multi_instance(const struct efi_device_path *dp) +{ + const struct efi_device_path *p = dp; + + if (!p) + return false; + while (p->type != DEVICE_PATH_TYPE_END) + p = (void *)p + p->length; + return p->sub_type == DEVICE_PATH_SUB_TYPE_INSTANCE_END; +} + #ifdef CONFIG_DM /* size of device-path not including END node for device and all parents * up to the root device. @@ -746,10 +847,12 @@ struct efi_device_path *efi_dp_from_file(struct blk_desc *desc, int part, return start; } -#ifdef CONFIG_CMD_NET +#ifdef CONFIG_NET struct efi_device_path *efi_dp_from_eth(void) { +#ifndef CONFIG_DM_ETH struct efi_device_path_mac_addr *ndp; +#endif void *buf, *start; unsigned dpsize = 0; @@ -759,8 +862,8 @@ struct efi_device_path *efi_dp_from_eth(void) dpsize += dp_size(eth_get_dev()); #else dpsize += sizeof(ROOT); -#endif dpsize += sizeof(*ndp); +#endif start = buf = dp_alloc(dpsize + sizeof(END)); if (!buf) @@ -771,14 +874,15 @@ struct efi_device_path *efi_dp_from_eth(void) #else memcpy(buf, &ROOT, sizeof(ROOT)); buf += sizeof(ROOT); -#endif ndp = buf; ndp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; ndp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR; ndp->dp.length = sizeof(*ndp); + ndp->if_type = 1; /* Ethernet */ memcpy(ndp->mac.addr, eth_get_ethaddr(), ARP_HLEN); buf = &ndp[1]; +#endif *((struct efi_device_path *)buf) = END; diff --git a/lib/efi_loader/efi_device_path_utilities.c b/lib/efi_loader/efi_device_path_utilities.c new file mode 100644 index 0000000000..0ada2111db --- /dev/null +++ b/lib/efi_loader/efi_device_path_utilities.c @@ -0,0 +1,200 @@ +/* + * EFI device path interface + * + * Copyright (c) 2017 Leif Lindholm + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <efi_loader.h> + +const efi_guid_t efi_guid_device_path_utilities_protocol = + EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID; + +/* + * Get size of a device path. + * + * This function implements the GetDevicePathSize service of the device path + * utilities protocol. The device path length includes the end of path tag + * which may be an instance end. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @device_path device path + * @return size in bytes + */ +static efi_uintn_t EFIAPI get_device_path_size( + const struct efi_device_path *device_path) +{ + efi_uintn_t sz = 0; + + EFI_ENTRY("%pD", device_path); + /* size includes the END node: */ + if (device_path) + sz = efi_dp_size(device_path) + sizeof(struct efi_device_path); + return EFI_EXIT(sz); +} + +/* + * Duplicate a device path. + * + * This function implements the DuplicateDevicePath service of the device path + * utilities protocol. + * + * The UEFI spec does not indicate what happens to the end tag. We follow the + * EDK2 logic: In case the device path ends with an end of instance tag, the + * copy will also end with an end of instance tag. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @device_path device path + * @return copy of the device path + */ +static struct efi_device_path * EFIAPI duplicate_device_path( + const struct efi_device_path *device_path) +{ + EFI_ENTRY("%pD", device_path); + return EFI_EXIT(efi_dp_dup(device_path)); +} + +/* + * Append device path. + * + * This function implements the AppendDevicePath service of the device path + * utilities protocol. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @src1 1st device path + * @src2 2nd device path + * @return concatenated device path + */ +static struct efi_device_path * EFIAPI append_device_path( + const struct efi_device_path *src1, + const struct efi_device_path *src2) +{ + EFI_ENTRY("%pD, %pD", src1, src2); + return EFI_EXIT(efi_dp_append(src1, src2)); +} + +/* + * Append device path node. + * + * This function implements the AppendDeviceNode service of the device path + * utilities protocol. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @device_path device path + * @device_node device node + * @return concatenated device path + */ +static struct efi_device_path * EFIAPI append_device_node( + const struct efi_device_path *device_path, + const struct efi_device_path *device_node) +{ + EFI_ENTRY("%pD, %p", device_path, device_node); + return EFI_EXIT(efi_dp_append_node(device_path, device_node)); +} + +/* + * Append device path instance. + * + * This function implements the AppendDevicePathInstance service of the device + * path utilities protocol. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @device_path 1st device path + * @device_path_instance 2nd device path + * @return concatenated device path + */ +static struct efi_device_path * EFIAPI append_device_path_instance( + const struct efi_device_path *device_path, + const struct efi_device_path *device_path_instance) +{ + EFI_ENTRY("%pD, %pD", device_path, device_path_instance); + return EFI_EXIT(efi_dp_append_instance(device_path, + device_path_instance)); +} + +/* + * Get next device path instance. + * + * This function implements the GetNextDevicePathInstance service of the device + * path utilities protocol. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @device_path_instance next device path instance + * @device_path_instance_size size of the device path instance + * @return concatenated device path + */ +static struct efi_device_path * EFIAPI get_next_device_path_instance( + struct efi_device_path **device_path_instance, + efi_uintn_t *device_path_instance_size) +{ + EFI_ENTRY("%pD, %p", device_path_instance, device_path_instance_size); + return EFI_EXIT(efi_dp_get_next_instance(device_path_instance, + device_path_instance_size)); +} + +/* + * Check if a device path contains more than one instance. + * + * This function implements the AppendDeviceNode service of the device path + * utilities protocol. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @device_path device path + * @device_node device node + * @return concatenated device path + */ +static bool EFIAPI is_device_path_multi_instance( + const struct efi_device_path *device_path) +{ + EFI_ENTRY("%pD", device_path); + return EFI_EXIT(efi_dp_is_multi_instance(device_path)); +} + +/* + * Create device node. + * + * This function implements the CreateDeviceNode service of the device path + * utilities protocol. + * + * See the Unified Extensible Firmware Interface (UEFI) specification + * for details. + * + * @node_type node type + * @node_sub_type node sub type + * @node_length node length + * @return device path node + */ +static struct efi_device_path * EFIAPI create_device_node( + uint8_t node_type, uint8_t node_sub_type, uint16_t node_length) +{ + EFI_ENTRY("%u, %u, %u", node_type, node_sub_type, node_length); + return EFI_EXIT(efi_dp_create_device_node(node_type, node_sub_type, + node_length)); +} + +const struct efi_device_path_utilities_protocol efi_device_path_utilities = { + .get_device_path_size = get_device_path_size, + .duplicate_device_path = duplicate_device_path, + .append_device_path = append_device_path, + .append_device_node = append_device_node, + .append_device_path_instance = append_device_path_instance, + .get_next_device_path_instance = get_next_device_path_instance, + .is_device_path_multi_instance = is_device_path_multi_instance, + .create_device_node = create_device_node, +}; diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 52a4e7438e..cec8347f55 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -12,6 +12,9 @@ #include <malloc.h> #include <fs.h> +/* GUID for file system information */ +const efi_guid_t efi_file_system_info_guid = EFI_FILE_SYSTEM_INFO_GUID; + struct file_system { struct efi_simple_file_system_protocol base; struct efi_device_path *dp; @@ -314,29 +317,41 @@ static efi_status_t dir_read(struct file_handle *fh, u64 *buffer_size, } static efi_status_t EFIAPI efi_file_read(struct efi_file_handle *file, - u64 *buffer_size, void *buffer) + efi_uintn_t *buffer_size, void *buffer) { struct file_handle *fh = to_fh(file); efi_status_t ret = EFI_SUCCESS; + u64 bs; EFI_ENTRY("%p, %p, %p", file, buffer_size, buffer); + if (!buffer_size || !buffer) { + ret = EFI_INVALID_PARAMETER; + goto error; + } + if (set_blk_dev(fh)) { ret = EFI_DEVICE_ERROR; goto error; } + bs = *buffer_size; if (fh->isdir) - ret = dir_read(fh, buffer_size, buffer); + ret = dir_read(fh, &bs, buffer); else - ret = file_read(fh, buffer_size, buffer); + ret = file_read(fh, &bs, buffer); + if (bs <= SIZE_MAX) + *buffer_size = bs; + else + *buffer_size = SIZE_MAX; error: return EFI_EXIT(ret); } static efi_status_t EFIAPI efi_file_write(struct efi_file_handle *file, - u64 *buffer_size, void *buffer) + efi_uintn_t *buffer_size, + void *buffer) { struct file_handle *fh = to_fh(file); efi_status_t ret = EFI_SUCCESS; @@ -363,21 +378,27 @@ error: } static efi_status_t EFIAPI efi_file_getpos(struct efi_file_handle *file, - u64 *pos) + efi_uintn_t *pos) { struct file_handle *fh = to_fh(file); + EFI_ENTRY("%p, %p", file, pos); - *pos = fh->offset; - return EFI_EXIT(EFI_SUCCESS); + + if (fh->offset <= SIZE_MAX) { + *pos = fh->offset; + return EFI_EXIT(EFI_SUCCESS); + } else { + return EFI_EXIT(EFI_DEVICE_ERROR); + } } static efi_status_t EFIAPI efi_file_setpos(struct efi_file_handle *file, - u64 pos) + efi_uintn_t pos) { struct file_handle *fh = to_fh(file); efi_status_t ret = EFI_SUCCESS; - EFI_ENTRY("%p, %llu", file, pos); + EFI_ENTRY("%p, %zu", file, pos); if (fh->isdir) { if (pos != 0) { @@ -411,7 +432,9 @@ error: } static efi_status_t EFIAPI efi_file_getinfo(struct efi_file_handle *file, - efi_guid_t *info_type, u64 *buffer_size, void *buffer) + const efi_guid_t *info_type, + efi_uintn_t *buffer_size, + void *buffer) { struct file_handle *fh = to_fh(file); efi_status_t ret = EFI_SUCCESS; @@ -452,6 +475,41 @@ static efi_status_t EFIAPI efi_file_getinfo(struct efi_file_handle *file, info->attribute |= EFI_FILE_DIRECTORY; ascii2unicode((u16 *)info->file_name, filename); + } else if (!guidcmp(info_type, &efi_file_system_info_guid)) { + struct efi_file_system_info *info = buffer; + disk_partition_t part; + efi_uintn_t required_size; + int r; + + if (fh->fs->part >= 1) + r = part_get_info(fh->fs->desc, fh->fs->part, &part); + else + r = part_get_info_whole_disk(fh->fs->desc, &part); + if (r < 0) { + ret = EFI_DEVICE_ERROR; + goto error; + } + required_size = sizeof(info) + 2 * + (strlen((const char *)part.name) + 1); + if (*buffer_size < required_size) { + *buffer_size = required_size; + ret = EFI_BUFFER_TOO_SMALL; + goto error; + } + + memset(info, 0, required_size); + + info->size = required_size; + info->read_only = true; + info->volume_size = part.size * part.blksz; + info->free_space = 0; + info->block_size = part.blksz; + /* + * TODO: The volume label is not available in U-Boot. + * Use the partition name as substitute. + */ + ascii2unicode((u16 *)info->volume_label, + (const char *)part.name); } else { ret = EFI_UNSUPPORTED; } @@ -461,9 +519,12 @@ error: } static efi_status_t EFIAPI efi_file_setinfo(struct efi_file_handle *file, - efi_guid_t *info_type, u64 buffer_size, void *buffer) + const efi_guid_t *info_type, + efi_uintn_t buffer_size, + void *buffer) { - EFI_ENTRY("%p, %p, %llu, %p", file, info_type, buffer_size, buffer); + EFI_ENTRY("%p, %p, %zu, %p", file, info_type, buffer_size, buffer); + return EFI_EXIT(EFI_UNSUPPORTED); } diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index 3caddd5f84..363ccbb789 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -56,27 +56,166 @@ static efi_status_t EFIAPI gop_set_mode(struct efi_gop *this, u32 mode_number) return EFI_EXIT(EFI_SUCCESS); } -efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer, - u32 operation, efi_uintn_t sx, - efi_uintn_t sy, efi_uintn_t dx, - efi_uintn_t dy, efi_uintn_t width, - efi_uintn_t height, efi_uintn_t delta) +static __always_inline struct efi_gop_pixel efi_vid16_to_blt_col(u16 vid) +{ + struct efi_gop_pixel blt = { + .reserved = 0, + }; + + blt.blue = (vid & 0x1f) << 3; + vid >>= 5; + blt.green = (vid & 0x3f) << 2; + vid >>= 6; + blt.red = (vid & 0x1f) << 3; + return blt; +} + +static __always_inline u16 efi_blt_col_to_vid16(struct efi_gop_pixel *blt) +{ + return (u16)(blt->red >> 3) << 11 | + (u16)(blt->green >> 2) << 5 | + (u16)(blt->blue >> 3); +} + +static __always_inline efi_status_t gop_blt_int(struct efi_gop *this, + struct efi_gop_pixel *bufferp, + u32 operation, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, + efi_uintn_t width, + efi_uintn_t height, + efi_uintn_t delta, + efi_uintn_t vid_bpp) { struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops); - int i, j, line_len16, line_len32; - void *fb; + efi_uintn_t i, j, linelen, slineoff = 0, dlineoff, swidth, dwidth; + u32 *fb32 = gopobj->fb; + u16 *fb16 = gopobj->fb; + struct efi_gop_pixel *buffer = __builtin_assume_aligned(bufferp, 4); + + if (delta) { + /* Check for 4 byte alignment */ + if (delta & 3) + return EFI_INVALID_PARAMETER; + linelen = delta >> 2; + } else { + linelen = width; + } - EFI_ENTRY("%p, %p, %u, %zu, %zu, %zu, %zu, %zu, %zu, %zu", this, - buffer, operation, sx, sy, dx, dy, width, height, delta); + /* Check source rectangle */ + switch (operation) { + case EFI_BLT_VIDEO_FILL: + break; + case EFI_BLT_BUFFER_TO_VIDEO: + if (sx + width > linelen) + return EFI_INVALID_PARAMETER; + break; + case EFI_BLT_VIDEO_TO_BLT_BUFFER: + case EFI_BLT_VIDEO_TO_VIDEO: + if (sx + width > gopobj->info.width || + sy + height > gopobj->info.height) + return EFI_INVALID_PARAMETER; + break; + default: + return EFI_INVALID_PARAMETER; + } - if (operation != EFI_BLT_BUFFER_TO_VIDEO) - return EFI_EXIT(EFI_INVALID_PARAMETER); + /* Check destination rectangle */ + switch (operation) { + case EFI_BLT_VIDEO_FILL: + case EFI_BLT_BUFFER_TO_VIDEO: + case EFI_BLT_VIDEO_TO_VIDEO: + if (dx + width > gopobj->info.width || + dy + height > gopobj->info.height) + return EFI_INVALID_PARAMETER; + break; + case EFI_BLT_VIDEO_TO_BLT_BUFFER: + if (dx + width > linelen) + return EFI_INVALID_PARAMETER; + break; + } - fb = gopobj->fb; - line_len16 = gopobj->info.width * sizeof(u16); - line_len32 = gopobj->info.width * sizeof(u32); + /* Calculate line width */ + switch (operation) { + case EFI_BLT_BUFFER_TO_VIDEO: + swidth = linelen; + break; + case EFI_BLT_VIDEO_TO_BLT_BUFFER: + case EFI_BLT_VIDEO_TO_VIDEO: + swidth = gopobj->info.width; + if (!vid_bpp) + return EFI_UNSUPPORTED; + break; + case EFI_BLT_VIDEO_FILL: + swidth = 0; + break; + } + + switch (operation) { + case EFI_BLT_BUFFER_TO_VIDEO: + case EFI_BLT_VIDEO_FILL: + case EFI_BLT_VIDEO_TO_VIDEO: + dwidth = gopobj->info.width; + if (!vid_bpp) + return EFI_UNSUPPORTED; + break; + case EFI_BLT_VIDEO_TO_BLT_BUFFER: + dwidth = linelen; + break; + } - /* Copy the contents line by line */ + slineoff = swidth * sy; + dlineoff = dwidth * dy; + for (i = 0; i < height; i++) { + for (j = 0; j < width; j++) { + struct efi_gop_pixel pix; + + /* Read source pixel */ + switch (operation) { + case EFI_BLT_VIDEO_FILL: + pix = *buffer; + break; + case EFI_BLT_BUFFER_TO_VIDEO: + pix = buffer[slineoff + j + sx]; + break; + case EFI_BLT_VIDEO_TO_BLT_BUFFER: + case EFI_BLT_VIDEO_TO_VIDEO: + if (vid_bpp == 32) + pix = *(struct efi_gop_pixel *)&fb32[ + slineoff + j + sx]; + else + pix = efi_vid16_to_blt_col(fb16[ + slineoff + j + sx]); + break; + } + + /* Write destination pixel */ + switch (operation) { + case EFI_BLT_VIDEO_TO_BLT_BUFFER: + buffer[dlineoff + j + dx] = pix; + break; + case EFI_BLT_BUFFER_TO_VIDEO: + case EFI_BLT_VIDEO_FILL: + case EFI_BLT_VIDEO_TO_VIDEO: + if (vid_bpp == 32) + fb32[dlineoff + j + dx] = *(u32 *)&pix; + else + fb16[dlineoff + j + dx] = + efi_blt_col_to_vid16(&pix); + break; + } + } + slineoff += swidth; + dlineoff += dwidth; + } + + return EFI_SUCCESS; +} + +static efi_uintn_t gop_get_bpp(struct efi_gop *this) +{ + struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops); + efi_uintn_t vid_bpp = 0; switch (gopobj->bpix) { #ifdef CONFIG_DM_VIDEO @@ -84,38 +223,151 @@ efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer, #else case LCD_COLOR32: #endif - for (i = 0; i < height; i++) { - u32 *dest = fb + ((i + dy) * line_len32) + - (dx * sizeof(u32)); - u32 *src = buffer + ((i + sy) * line_len32) + - (sx * sizeof(u32)); - - /* Same color format, just memcpy */ - memcpy(dest, src, width * sizeof(u32)); - } + vid_bpp = 32; break; #ifdef CONFIG_DM_VIDEO case VIDEO_BPP16: #else case LCD_COLOR16: #endif - for (i = 0; i < height; i++) { - u16 *dest = fb + ((i + dy) * line_len16) + - (dx * sizeof(u16)); - u32 *src = buffer + ((i + sy) * line_len32) + - (sx * sizeof(u32)); - - /* Convert from rgb888 to rgb565 */ - for (j = 0; j < width; j++) { - u32 rgb888 = src[j]; - dest[j] = ((((rgb888 >> (16 + 3)) & 0x1f) << 11) | - (((rgb888 >> (8 + 2)) & 0x3f) << 5) | - (((rgb888 >> (0 + 3)) & 0x1f) << 0)); - } - } + vid_bpp = 16; break; } + return vid_bpp; +} + +/* + * Gcc can't optimize our BLT function well, but we need to make sure that + * our 2-dimensional loop gets executed very quickly, otherwise the system + * will feel slow. + * + * By manually putting all obvious branch targets into functions which call + * our generic blt function with constants, the compiler can successfully + * optimize for speed. + */ +static efi_status_t gop_blt_video_fill(struct efi_gop *this, + struct efi_gop_pixel *buffer, + u32 foo, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta, + efi_uintn_t vid_bpp) +{ + return gop_blt_int(this, buffer, EFI_BLT_VIDEO_FILL, sx, sy, dx, + dy, width, height, delta, vid_bpp); +} + +static efi_status_t gop_blt_buf_to_vid16(struct efi_gop *this, + struct efi_gop_pixel *buffer, + u32 foo, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta) +{ + return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx, + dy, width, height, delta, 16); +} + +static efi_status_t gop_blt_buf_to_vid32(struct efi_gop *this, + struct efi_gop_pixel *buffer, + u32 foo, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta) +{ + return gop_blt_int(this, buffer, EFI_BLT_BUFFER_TO_VIDEO, sx, sy, dx, + dy, width, height, delta, 32); +} + +static efi_status_t gop_blt_vid_to_vid(struct efi_gop *this, + struct efi_gop_pixel *buffer, + u32 foo, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta, + efi_uintn_t vid_bpp) +{ + return gop_blt_int(this, buffer, EFI_BLT_VIDEO_TO_VIDEO, sx, sy, dx, + dy, width, height, delta, vid_bpp); +} + +static efi_status_t gop_blt_vid_to_buf(struct efi_gop *this, + struct efi_gop_pixel *buffer, + u32 foo, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta, + efi_uintn_t vid_bpp) +{ + return gop_blt_int(this, buffer, EFI_BLT_VIDEO_TO_BLT_BUFFER, sx, sy, + dx, dy, width, height, delta, vid_bpp); +} + +/* + * Copy rectangle. + * + * This function implements the Blt service of the EFI_GRAPHICS_OUTPUT_PROTOCOL. + * See the Unified Extensible Firmware Interface (UEFI) specification for + * details. + * + * @this: EFI_GRAPHICS_OUTPUT_PROTOCOL + * @buffer: pixel buffer + * @sx: source x-coordinate + * @sy: source y-coordinate + * @dx: destination x-coordinate + * @dy: destination y-coordinate + * @width: width of rectangle + * @height: height of rectangle + * @delta: length in bytes of a line in the pixel buffer (optional) + * @return: status code + */ +efi_status_t EFIAPI gop_blt(struct efi_gop *this, struct efi_gop_pixel *buffer, + u32 operation, efi_uintn_t sx, + efi_uintn_t sy, efi_uintn_t dx, + efi_uintn_t dy, efi_uintn_t width, + efi_uintn_t height, efi_uintn_t delta) +{ + efi_status_t ret = EFI_INVALID_PARAMETER; + efi_uintn_t vid_bpp; + + EFI_ENTRY("%p, %p, %u, %zu, %zu, %zu, %zu, %zu, %zu, %zu", this, + buffer, operation, sx, sy, dx, dy, width, height, delta); + + vid_bpp = gop_get_bpp(this); + + /* Allow for compiler optimization */ + switch (operation) { + case EFI_BLT_VIDEO_FILL: + ret = gop_blt_video_fill(this, buffer, operation, sx, sy, dx, + dy, width, height, delta, vid_bpp); + break; + case EFI_BLT_BUFFER_TO_VIDEO: + /* This needs to be super-fast, so duplicate for 16/32bpp */ + if (vid_bpp == 32) + ret = gop_blt_buf_to_vid32(this, buffer, operation, sx, + sy, dx, dy, width, height, + delta); + else + ret = gop_blt_buf_to_vid16(this, buffer, operation, sx, + sy, dx, dy, width, height, + delta); + break; + case EFI_BLT_VIDEO_TO_VIDEO: + ret = gop_blt_vid_to_vid(this, buffer, operation, sx, sy, dx, + dy, width, height, delta, vid_bpp); + break; + case EFI_BLT_VIDEO_TO_BLT_BUFFER: + ret = gop_blt_vid_to_buf(this, buffer, operation, sx, sy, dx, + dy, width, height, delta, vid_bpp); + break; + default: + ret = EFI_UNSUPPORTED; + } + + if (ret != EFI_SUCCESS) + return EFI_EXIT(ret); + #ifdef CONFIG_DM_VIDEO video_sync_all(); #else @@ -125,8 +377,13 @@ efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer, return EFI_EXIT(EFI_SUCCESS); } -/* This gets called from do_bootefi_exec(). */ -int efi_gop_register(void) +/* + * Install graphical output protocol. + * + * If no supported video device exists this is not considered as an + * error. + */ +efi_status_t efi_gop_register(void) { struct efi_gop_obj *gopobj; u32 bpix, col, row; @@ -136,12 +393,15 @@ int efi_gop_register(void) #ifdef CONFIG_DM_VIDEO struct udevice *vdev; + struct video_priv *priv; /* We only support a single video output device for now */ - if (uclass_first_device(UCLASS_VIDEO, &vdev) || !vdev) - return -1; + if (uclass_first_device(UCLASS_VIDEO, &vdev) || !vdev) { + debug("WARNING: No video device\n"); + return EFI_SUCCESS; + } - struct video_priv *priv = dev_get_uclass_priv(vdev); + priv = dev_get_uclass_priv(vdev); bpix = priv->bpix; col = video_get_xsize(vdev); row = video_get_ysize(vdev); @@ -170,13 +430,14 @@ int efi_gop_register(void) break; default: /* So far, we only work in 16 or 32 bit mode */ - return -1; + debug("WARNING: Unsupported video mode\n"); + return EFI_SUCCESS; } gopobj = calloc(1, sizeof(*gopobj)); if (!gopobj) { printf("ERROR: Out of memory\n"); - return 1; + return EFI_OUT_OF_RESOURCES; } /* Hook up to the device list */ @@ -186,8 +447,8 @@ int efi_gop_register(void) ret = efi_add_protocol(gopobj->parent.handle, &efi_gop_guid, &gopobj->ops); if (ret != EFI_SUCCESS) { - printf("ERROR: Out of memory\n"); - return 1; + printf("ERROR: Failure adding gop protocol\n"); + return ret; } gopobj->ops.query_mode = gop_query_mode; gopobj->ops.set_mode = gop_set_mode; @@ -199,10 +460,11 @@ int efi_gop_register(void) gopobj->mode.info_size = sizeof(gopobj->info); #ifdef CONFIG_DM_VIDEO - if (bpix == VIDEO_BPP32) { + if (bpix == VIDEO_BPP32) #else - if (bpix == LCD_COLOR32) { + if (bpix == LCD_COLOR32) #endif + { /* With 32bit color space we can directly expose the fb */ gopobj->mode.fb_base = fb_base; gopobj->mode.fb_size = fb_size; @@ -217,5 +479,5 @@ int efi_gop_register(void) gopobj->bpix = bpix; gopobj->fb = fb; - return 0; + return EFI_SUCCESS; } diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index cac64ba9fe..d5fbba3138 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -22,6 +22,76 @@ const efi_guid_t efi_simple_file_system_protocol_guid = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID; +static int machines[] = { +#if defined(CONFIG_ARM64) + IMAGE_FILE_MACHINE_ARM64, +#elif defined(CONFIG_ARM) + IMAGE_FILE_MACHINE_ARM, + IMAGE_FILE_MACHINE_THUMB, + IMAGE_FILE_MACHINE_ARMNT, +#endif + +#if defined(CONFIG_X86_64) + IMAGE_FILE_MACHINE_AMD64, +#elif defined(CONFIG_X86) + IMAGE_FILE_MACHINE_I386, +#endif + +#if defined(CONFIG_CPU_RISCV_32) + IMAGE_FILE_MACHINE_RISCV32, +#endif + +#if defined(CONFIG_CPU_RISCV_64) + IMAGE_FILE_MACHINE_RISCV64, +#endif + 0 }; + +/* + * Print information about a loaded image. + * + * If the program counter is located within the image the offset to the base + * address is shown. + * + * @image: loaded image + * @pc: program counter (use NULL to suppress offset output) + * @return: status code + */ +efi_status_t efi_print_image_info(struct efi_loaded_image *image, void *pc) +{ + if (!image) + return EFI_INVALID_PARAMETER; + printf("UEFI image"); + printf(" [0x%p:0x%p]", + image->reloc_base, image->reloc_base + image->reloc_size - 1); + if (pc && pc >= image->reloc_base && + pc < image->reloc_base + image->reloc_size) + printf(" pc=0x%zx", pc - image->reloc_base); + if (image->file_path) + printf(" '%pD'", image->file_path); + printf("\n"); + return EFI_SUCCESS; +} + +/* + * Print information about all loaded images. + * + * @pc: program counter (use NULL to suppress offset output) + */ +void efi_print_image_infos(void *pc) +{ + struct efi_object *efiobj; + struct efi_handler *handler; + + list_for_each_entry(efiobj, &efi_obj_list, link) { + list_for_each_entry(handler, &efiobj->protocols, link) { + if (!guidcmp(handler->guid, &efi_guid_loaded_image)) { + efi_print_image_info( + handler->protocol_interface, pc); + } + } + } +} + static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel, unsigned long rel_size, void *efi_reloc) { @@ -126,14 +196,7 @@ void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info) void *entry; uint64_t image_size; unsigned long virt_size = 0; - bool can_run_nt64 = true; - bool can_run_nt32 = true; - -#if defined(CONFIG_ARM64) - can_run_nt32 = false; -#elif defined(CONFIG_ARM) - can_run_nt64 = false; -#endif + int supported = 0; dos = efi; if (dos->e_magic != IMAGE_DOS_SIGNATURE) { @@ -147,6 +210,18 @@ void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info) return NULL; } + for (i = 0; machines[i]; i++) + if (machines[i] == nt->FileHeader.Machine) { + supported = 1; + break; + } + + if (!supported) { + printf("%s: Machine type 0x%04x is not supported\n", + __func__, nt->FileHeader.Machine); + return NULL; + } + /* Calculate upper virtual address boundary */ num_sections = nt->FileHeader.NumberOfSections; sections = (void *)&nt->OptionalHeader + @@ -159,8 +234,7 @@ void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info) } /* Read 32/64bit specific header bits */ - if (can_run_nt64 && - (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC)) { + if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC) { IMAGE_NT_HEADERS64 *nt64 = (void *)nt; IMAGE_OPTIONAL_HEADER64 *opt = &nt64->OptionalHeader; image_size = opt->SizeOfImage; @@ -175,8 +249,8 @@ void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info) entry = efi_reloc + opt->AddressOfEntryPoint; rel_size = opt->DataDirectory[rel_idx].Size; rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress; - } else if (can_run_nt32 && - (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC)) { + virt_size = ALIGN(virt_size, opt->SectionAlignment); + } else if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC) { IMAGE_OPTIONAL_HEADER32 *opt = &nt->OptionalHeader; image_size = opt->SizeOfImage; efi_set_code_and_data_type(loaded_image_info, opt->Subsystem); @@ -190,6 +264,7 @@ void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info) entry = efi_reloc + opt->AddressOfEntryPoint; rel_size = opt->DataDirectory[rel_idx].Size; rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress; + virt_size = ALIGN(virt_size, opt->SectionAlignment); } else { printf("%s: Invalid optional header magic %x\n", __func__, nt->OptionalHeader.Magic); @@ -221,6 +296,8 @@ void *efi_load_pe(void *efi, struct efi_loaded_image *loaded_image_info) /* Populate the loaded image interface bits */ loaded_image_info->image_base = efi; loaded_image_info->image_size = image_size; + loaded_image_info->reloc_base = efi_reloc; + loaded_image_info->reloc_size = virt_size; return entry; } diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index ff0edf30ff..95f9ff0a14 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -8,12 +8,11 @@ #include <common.h> #include <efi_loader.h> +#include <inttypes.h> #include <malloc.h> +#include <watchdog.h> #include <asm/global_data.h> -#include <linux/libfdt_env.h> #include <linux/list_sort.h> -#include <inttypes.h> -#include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; @@ -292,7 +291,7 @@ efi_status_t efi_allocate_pages(int type, int memory_type, uint64_t addr; switch (type) { - case 0: + case EFI_ALLOCATE_ANY_PAGES: /* Any page */ addr = efi_find_free_memory(len, gd->start_addr_sp); if (!addr) { @@ -300,7 +299,7 @@ efi_status_t efi_allocate_pages(int type, int memory_type, break; } break; - case 1: + case EFI_ALLOCATE_MAX_ADDRESS: /* Max address */ addr = efi_find_free_memory(len, *memory); if (!addr) { @@ -308,7 +307,7 @@ efi_status_t efi_allocate_pages(int type, int memory_type, break; } break; - case 2: + case EFI_ALLOCATE_ADDRESS: /* Exact address, reserve it. The addr is already in *memory. */ addr = *memory; break; diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c index 8c5d5b492c..9afe76cdb3 100644 --- a/lib/efi_loader/efi_net.c +++ b/lib/efi_loader/efi_net.c @@ -54,14 +54,46 @@ static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this) return EFI_EXIT(EFI_SUCCESS); } +/* + * Initialize network adapter and allocate transmit and receive buffers. + * + * This function implements the Initialize service of the + * EFI_SIMPLE_NETWORK_PROTOCOL. See the Unified Extensible Firmware Interface + * (UEFI) specification for details. + * + * @this: pointer to the protocol instance + * @extra_rx: extra receive buffer to be allocated + * @extra_tx: extra transmit buffer to be allocated + * @return: status code + */ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this, ulong extra_rx, ulong extra_tx) { + int ret; + efi_status_t r = EFI_SUCCESS; + EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx); - eth_init(); + if (!this) { + r = EFI_INVALID_PARAMETER; + goto error; + } - return EFI_EXIT(EFI_SUCCESS); + /* Setup packet buffers */ + net_init(); + /* Disable hardware and put it into the reset state */ + eth_halt(); + /* Set current device according to environment variables */ + eth_set_current(); + /* Get hardware ready for send and receive operations */ + ret = eth_init(); + if (ret < 0) { + eth_halt(); + r = EFI_DEVICE_ERROR; + } + +error: + return EFI_EXIT(r); } static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this, @@ -280,20 +312,22 @@ static void EFIAPI efi_network_timer_notify(struct efi_event *event, } /* This gets called from do_bootefi_exec(). */ -int efi_net_register(void) +efi_status_t efi_net_register(void) { struct efi_net_obj *netobj; efi_status_t r; if (!eth_get_dev()) { /* No eth device active, don't expose any */ - return 0; + return EFI_SUCCESS; } /* We only expose the "active" eth device, so one is enough */ netobj = calloc(1, sizeof(*netobj)); - if (!netobj) - goto out_of_memory; + if (!netobj) { + printf("ERROR: Out of memory\n"); + return EFI_OUT_OF_RESOURCES; + } /* Hook net up to the device list */ efi_add_handle(&netobj->parent); @@ -302,15 +336,15 @@ int efi_net_register(void) r = efi_add_protocol(netobj->parent.handle, &efi_net_guid, &netobj->net); if (r != EFI_SUCCESS) - goto out_of_memory; + goto failure_to_add_protocol; r = efi_add_protocol(netobj->parent.handle, &efi_guid_device_path, efi_dp_from_eth()); if (r != EFI_SUCCESS) - goto out_of_memory; + goto failure_to_add_protocol; r = efi_add_protocol(netobj->parent.handle, &efi_pxe_guid, &netobj->pxe); if (r != EFI_SUCCESS) - goto out_of_memory; + goto failure_to_add_protocol; netobj->net.revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION; netobj->net.start = efi_net_start; netobj->net.stop = efi_net_stop; @@ -339,7 +373,7 @@ int efi_net_register(void) * Create WaitForPacket event. */ r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK, - efi_network_timer_notify, NULL, + efi_network_timer_notify, NULL, NULL, &wait_for_packet); if (r != EFI_SUCCESS) { printf("ERROR: Failed to register network event\n"); @@ -351,9 +385,11 @@ int efi_net_register(void) * * The notification function is used to check if a new network packet * has been received. + * + * iPXE is running at TPL_CALLBACK most of the time. Use a higher TPL. */ - r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, - efi_network_timer_notify, NULL, + r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_NOTIFY, + efi_network_timer_notify, NULL, NULL, &network_timer_event); if (r != EFI_SUCCESS) { printf("ERROR: Failed to register network event\n"); @@ -366,8 +402,8 @@ int efi_net_register(void) return r; } - return 0; -out_of_memory: - printf("ERROR: Out of memory\n"); - return 1; + return EFI_SUCCESS; +failure_to_add_protocol: + printf("ERROR: Failure to add protocol\n"); + return r; } diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index ccb4fc6141..8558124c0a 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -74,12 +74,24 @@ static void EFIAPI efi_reset_system_boottime( efi_status_t reset_status, unsigned long data_size, void *reset_data) { + struct efi_event *evt; + EFI_ENTRY("%d %lx %lx %p", reset_type, reset_status, data_size, reset_data); + /* Notify reset */ + list_for_each_entry(evt, &efi_events, link) { + if (evt->group && + !guidcmp(evt->group, + &efi_guid_event_group_reset_system)) { + efi_signal_event(evt, false); + break; + } + } switch (reset_type) { case EFI_RESET_COLD: case EFI_RESET_WARM: + case EFI_RESET_PLATFORM_SPECIFIC: do_reset(NULL, 0, 0, NULL); break; case EFI_RESET_SHUTDOWN: @@ -134,8 +146,9 @@ void __weak __efi_runtime EFIAPI efi_reset_system( while (1) { } } -void __weak efi_reset_system_init(void) +efi_status_t __weak efi_reset_system_init(void) { + return EFI_SUCCESS; } efi_status_t __weak __efi_runtime EFIAPI efi_get_time( @@ -146,8 +159,9 @@ efi_status_t __weak __efi_runtime EFIAPI efi_get_time( return EFI_DEVICE_ERROR; } -void __weak efi_get_time_init(void) +efi_status_t __weak efi_get_time_init(void) { + return EFI_SUCCESS; } struct efi_runtime_detach_list_struct { @@ -332,18 +346,26 @@ static efi_status_t EFIAPI efi_set_virtual_address_map( return EFI_EXIT(EFI_INVALID_PARAMETER); } -void efi_add_runtime_mmio(void *mmio_ptr, u64 len) +efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len) { struct efi_runtime_mmio_list *newmmio; - u64 pages = (len + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; - efi_add_memory_map(*(uintptr_t *)mmio_ptr, pages, EFI_MMAP_IO, false); + uint64_t addr = *(uintptr_t *)mmio_ptr; + uint64_t retaddr; + + retaddr = efi_add_memory_map(addr, pages, EFI_MMAP_IO, false); + if (retaddr != addr) + return EFI_OUT_OF_RESOURCES; newmmio = calloc(1, sizeof(*newmmio)); + if (!newmmio) + return EFI_OUT_OF_RESOURCES; newmmio->ptr = mmio_ptr; newmmio->paddr = *(uintptr_t *)mmio_ptr; newmmio->len = len; list_add_tail(&newmmio->link, &efi_runtime_mmio); + + return EFI_SUCCESS; } /* diff --git a/lib/efi_loader/efi_smbios.c b/lib/efi_loader/efi_smbios.c index ac412e7362..62e9697902 100644 --- a/lib/efi_loader/efi_smbios.c +++ b/lib/efi_loader/efi_smbios.c @@ -13,20 +13,27 @@ static const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID; -void efi_smbios_register(void) +/* + * Install the SMBIOS table as a configuration table. + * + * @return status code + */ +efi_status_t efi_smbios_register(void) { /* Map within the low 32 bits, to allow for 32bit SMBIOS tables */ - uint64_t dmi = 0xffffffff; - /* Reserve 4kb for SMBIOS */ - uint64_t pages = 1; - int memtype = EFI_RUNTIME_SERVICES_DATA; + u64 dmi = U32_MAX; + efi_status_t ret; - if (efi_allocate_pages(1, memtype, pages, &dmi) != EFI_SUCCESS) - return; + /* Reserve 4kiB page for SMBIOS */ + ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS, + EFI_RUNTIME_SERVICES_DATA, 1, &dmi); + if (ret != EFI_SUCCESS) + return ret; /* Generate SMBIOS tables */ write_smbios_table(dmi); /* And expose them to our EFI payload */ - efi_install_configuration_table(&smbios_guid, (void*)(uintptr_t)dmi); + return efi_install_configuration_table(&smbios_guid, + (void *)(uintptr_t)dmi); } diff --git a/lib/efi_loader/efi_watchdog.c b/lib/efi_loader/efi_watchdog.c index 35a45dedf8..d12e51da0a 100644 --- a/lib/efi_loader/efi_watchdog.c +++ b/lib/efi_loader/efi_watchdog.c @@ -59,7 +59,7 @@ efi_status_t efi_set_watchdog(unsigned long timeout) * * This function is called by efi_init_obj_list() */ -int efi_watchdog_register(void) +efi_status_t efi_watchdog_register(void) { efi_status_t r; @@ -67,7 +67,7 @@ int efi_watchdog_register(void) * Create a timer event. */ r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, - efi_watchdog_timer_notify, NULL, + efi_watchdog_timer_notify, NULL, NULL, &watchdog_timer_event); if (r != EFI_SUCCESS) { printf("ERROR: Failed to register watchdog event\n"); @@ -85,5 +85,5 @@ int efi_watchdog_register(void) printf("ERROR: Failed to set watchdog timer\n"); return r; } - return 0; + return EFI_SUCCESS; } diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c index 1ec0179226..6c539ba204 100644 --- a/lib/efi_loader/helloworld.c +++ b/lib/efi_loader/helloworld.c @@ -46,9 +46,27 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle, struct efi_loaded_image *loaded_image; efi_status_t ret; efi_uintn_t i; + u16 rev[] = L"0.0.0"; con_out->output_string(con_out, L"Hello, world!\n"); + /* Print the revision number */ + rev[0] = (systable->hdr.revision >> 16) + '0'; + rev[4] = systable->hdr.revision & 0xffff; + for (; rev[4] >= 10;) { + rev[4] -= 10; + ++rev[2]; + } + /* Third digit is only to be shown if non-zero */ + if (rev[4]) + rev[4] += '0'; + else + rev[3] = 0; + + con_out->output_string(con_out, L"Running on UEFI "); + con_out->output_string(con_out, rev); + con_out->output_string(con_out, L"\n"); + /* Get the loaded image protocol */ ret = boottime->handle_protocol(handle, &loaded_image_guid, (void **)&loaded_image); diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile index c4bdbdf6c0..0e4980c8a0 100644 --- a/lib/efi_selftest/Makefile +++ b/lib/efi_selftest/Makefile @@ -14,14 +14,19 @@ CFLAGS_REMOVE_efi_selftest_miniapp_return.o := $(CFLAGS_NON_EFI) -Os obj-$(CONFIG_CMD_BOOTEFI_SELFTEST) += \ efi_selftest.o \ +efi_selftest_bitblt.o \ efi_selftest_controllers.o \ efi_selftest_console.o \ efi_selftest_devicepath.o \ +efi_selftest_devicepath_util.o \ efi_selftest_events.o \ +efi_selftest_event_groups.o \ efi_selftest_exitbootservices.o \ +efi_selftest_fdt.o \ efi_selftest_gop.o \ efi_selftest_manageprotocols.o \ efi_selftest_snp.o \ +efi_selftest_textinput.o \ efi_selftest_textoutput.o \ efi_selftest_tpl.o \ efi_selftest_util.o \ diff --git a/lib/efi_selftest/efi_selftest.c b/lib/efi_selftest/efi_selftest.c index fc5ef254a1..fd4fee726f 100644 --- a/lib/efi_selftest/efi_selftest.c +++ b/lib/efi_selftest/efi_selftest.c @@ -77,20 +77,20 @@ void efi_st_exit_boot_services(void) */ static int setup(struct efi_unit_test *test, unsigned int *failures) { - int ret; - - if (!test->setup) + if (!test->setup) { + test->setup_ok = EFI_ST_SUCCESS; return EFI_ST_SUCCESS; + } efi_st_printc(EFI_LIGHTBLUE, "\nSetting up '%s'\n", test->name); - ret = test->setup(handle, systable); - if (ret != EFI_ST_SUCCESS) { + test->setup_ok = test->setup(handle, systable); + if (test->setup_ok != EFI_ST_SUCCESS) { efi_st_error("Setting up '%s' failed\n", test->name); ++*failures; } else { efi_st_printc(EFI_LIGHTGREEN, "Setting up '%s' succeeded\n", test->name); } - return ret; + return test->setup_ok; } /* @@ -200,7 +200,7 @@ void efi_st_do_tests(const u16 *testname, unsigned int phase, continue; if (steps & EFI_ST_SETUP) setup(test, failures); - if (steps & EFI_ST_EXECUTE) + if (steps & EFI_ST_EXECUTE && test->setup_ok == EFI_ST_SUCCESS) execute(test, failures); if (steps & EFI_ST_TEARDOWN) teardown(test, failures); diff --git a/lib/efi_selftest/efi_selftest_bitblt.c b/lib/efi_selftest/efi_selftest_bitblt.c new file mode 100644 index 0000000000..0fb76cc727 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_bitblt.c @@ -0,0 +1,311 @@ +/* + * efi_selftest_bitblt + * + * Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Test the block image transfer in the graphical output protocol. + * An animated submarine is shown. + */ + +#include <efi_selftest.h> + +#define WIDTH 200 +#define HEIGHT 120 +#define DEPTH 60 + +static const struct efi_gop_pixel BLACK = { 0, 0, 0, 0}; +static const struct efi_gop_pixel RED = { 0, 0, 255, 0}; +static const struct efi_gop_pixel ORANGE = { 0, 128, 255, 0}; +static const struct efi_gop_pixel YELLOW = { 0, 255, 255, 0}; +static const struct efi_gop_pixel GREEN = { 0, 255, 0, 0}; +static const struct efi_gop_pixel DARK_BLUE = {128, 0, 0, 0}; +static const struct efi_gop_pixel LIGHT_BLUE = {255, 192, 192, 0}; + +static struct efi_boot_services *boottime; +static efi_guid_t efi_gop_guid = EFI_GOP_GUID; +static struct efi_gop *gop; +static struct efi_gop_pixel *bitmap; +static struct efi_event *event; +static efi_uintn_t xpos; + +static void ellipse(efi_uintn_t x, efi_uintn_t y, + efi_uintn_t x0, efi_uintn_t y0, + efi_uintn_t x1, efi_uintn_t y1, + const struct efi_gop_pixel col, struct efi_gop_pixel *pix) +{ + efi_uintn_t xm = x0 + x1; + efi_uintn_t ym = y0 + y1; + efi_uintn_t dx = x1 - x0 + 1; + efi_uintn_t dy = y1 - y0 + 1; + + if (dy * dy * (2 * x - xm) * (2 * x - xm) + + dx * dx * (2 * y - ym) * (2 * y - ym) <= dx * dx * dy * dy) + *pix = col; +} + +static void rectangle(efi_uintn_t x, efi_uintn_t y, + efi_uintn_t x0, efi_uintn_t y0, + efi_uintn_t x1, efi_uintn_t y1, + const struct efi_gop_pixel col, struct efi_gop_pixel *pix) +{ + if (x >= x0 && y >= y0 && x <= x1 && y <= y1) + *pix = col; +} + +/* + * Notification function, copies image to video. + * The position is incremented in each call. + * + * @event notified event + * @context pointer to the notification count + */ +static void EFIAPI notify(struct efi_event *event, void *context) +{ + efi_uintn_t *pos = context; + efi_uintn_t dx, sx, width; + + if (!pos) + return; + + /* Increment position */ + *pos += 5; + if (*pos >= WIDTH + gop->mode->info->width) + *pos = 0; + + width = WIDTH; + dx = *pos - WIDTH; + sx = 0; + if (*pos >= gop->mode->info->width) { + width = WIDTH + gop->mode->info->width - *pos; + } else if (*pos < WIDTH) { + dx = 0; + sx = WIDTH - *pos; + width = *pos; + } + + /* Copy image to video */ + gop->blt(gop, bitmap, EFI_BLT_BUFFER_TO_VIDEO, sx, 0, dx, DEPTH, + width, HEIGHT, WIDTH * sizeof(struct efi_gop_pixel)); +} + +/* + * Setup unit test. + * + * @handle: handle of the loaded image + * @systable: system table + * @return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t handle, + const struct efi_system_table *systable) +{ + efi_status_t ret; + struct efi_gop_pixel pix; + efi_uintn_t x, y; + + boottime = systable->boottime; + + /* Create event */ + ret = boottime->create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, notify, (void *)&xpos, + &event); + if (ret != EFI_SUCCESS) { + efi_st_error("could not create event\n"); + return EFI_ST_FAILURE; + } + + /* Get graphical output protocol */ + ret = boottime->locate_protocol(&efi_gop_guid, NULL, (void **)&gop); + if (ret != EFI_SUCCESS) { + gop = NULL; + efi_st_printf("Graphical output protocol is not available.\n"); + return EFI_ST_SUCCESS; + } + + /* Prepare image of submarine */ + ret = boottime->allocate_pool(EFI_LOADER_DATA, + sizeof(struct efi_gop_pixel) * + WIDTH * HEIGHT, (void **)&bitmap); + if (ret != EFI_SUCCESS) { + efi_st_error("Out of memory\n"); + return EFI_ST_FAILURE; + } + for (y = 0; y < HEIGHT; ++y) { + for (x = 0; x < WIDTH; ++x) { + pix = DARK_BLUE; + + /* Propeller */ + ellipse(x, y, 35, 55, 43, 75, BLACK, &pix); + ellipse(x, y, 36, 56, 42, 74, LIGHT_BLUE, &pix); + + ellipse(x, y, 35, 75, 43, 95, BLACK, &pix); + ellipse(x, y, 36, 76, 42, 94, LIGHT_BLUE, &pix); + + /* Shaft */ + rectangle(x, y, 35, 73, 100, 77, BLACK, &pix); + + /* Periscope */ + ellipse(x, y, 120, 10, 160, 50, BLACK, &pix); + ellipse(x, y, 121, 11, 159, 59, YELLOW, &pix); + ellipse(x, y, 130, 20, 150, 40, BLACK, &pix); + ellipse(x, y, 131, 21, 149, 49, DARK_BLUE, &pix); + rectangle(x, y, 135, 10, 160, 50, DARK_BLUE, &pix); + ellipse(x, y, 132, 10, 138, 20, BLACK, &pix); + ellipse(x, y, 133, 11, 139, 19, RED, &pix); + + /* Rudder */ + ellipse(x, y, 45, 40, 75, 70, BLACK, &pix); + ellipse(x, y, 46, 41, 74, 69, ORANGE, &pix); + ellipse(x, y, 45, 80, 75, 109, BLACK, &pix); + ellipse(x, y, 46, 81, 74, 108, RED, &pix); + + /* Bridge */ + ellipse(x, y, 100, 30, 120, 50, BLACK, &pix); + ellipse(x, y, 101, 31, 119, 49, GREEN, &pix); + ellipse(x, y, 140, 30, 160, 50, BLACK, &pix); + ellipse(x, y, 141, 31, 159, 49, GREEN, &pix); + rectangle(x, y, 110, 30, 150, 50, BLACK, &pix); + rectangle(x, y, 110, 31, 150, 50, GREEN, &pix); + + /* Hull */ + ellipse(x, y, 50, 40, 199, 109, BLACK, &pix); + ellipse(x, y, 51, 41, 198, 108, LIGHT_BLUE, &pix); + + /* Port holes */ + ellipse(x, y, 79, 57, 109, 82, BLACK, &pix); + ellipse(x, y, 80, 58, 108, 81, LIGHT_BLUE, &pix); + ellipse(x, y, 83, 61, 105, 78, BLACK, &pix); + ellipse(x, y, 84, 62, 104, 77, YELLOW, &pix); + /* + * This port hole is created by copying + * ellipse(x, y, 119, 57, 149, 82, BLACK, &pix); + * ellipse(x, y, 120, 58, 148, 81, LIGHT_BLUE, &pix); + * ellipse(x, y, 123, 61, 145, 78, BLACK, &pix); + * ellipse(x, y, 124, 62, 144, 77, YELLOW, &pix); + */ + ellipse(x, y, 159, 57, 189, 82, BLACK, &pix); + ellipse(x, y, 160, 58, 188, 81, LIGHT_BLUE, &pix); + ellipse(x, y, 163, 61, 185, 78, BLACK, &pix); + ellipse(x, y, 164, 62, 184, 77, YELLOW, &pix); + + bitmap[WIDTH * y + x] = pix; + } + } + + return EFI_ST_SUCCESS; +} + +/* + * Tear down unit test. + * + * @return: EFI_ST_SUCCESS for success + */ +static int teardown(void) +{ + efi_status_t ret; + + if (bitmap) { + ret = boottime->free_pool(bitmap); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + } + if (event) { + ret = boottime->close_event(event); + event = NULL; + if (ret != EFI_SUCCESS) { + efi_st_error("could not close event\n"); + return EFI_ST_FAILURE; + } + } + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * @return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + u32 max_mode; + efi_status_t ret; + struct efi_gop_mode_info *info; + + if (!gop) + return EFI_ST_SUCCESS; + + if (!gop->mode) { + efi_st_error("EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE missing\n"); + return EFI_ST_FAILURE; + } + info = gop->mode->info; + max_mode = gop->mode->max_mode; + if (!max_mode) { + efi_st_error("No graphical mode available\n"); + return EFI_ST_FAILURE; + } + + /* Fill background */ + ret = gop->blt(gop, bitmap, EFI_BLT_VIDEO_FILL, 0, 0, 0, 0, + info->width, info->height, 0); + if (ret != EFI_SUCCESS) { + efi_st_error("EFI_BLT_VIDEO_FILL failed\n"); + return EFI_ST_FAILURE; + } + + /* Copy image to video */ + ret = gop->blt(gop, bitmap, EFI_BLT_BUFFER_TO_VIDEO, 0, 0, 0, DEPTH, + WIDTH, HEIGHT, 0); + if (ret != EFI_SUCCESS) { + efi_st_error("EFI_BLT_BUFFER_TO_VIDEO failed\n"); + return EFI_ST_FAILURE; + } + + /* Copy left port hole */ + ret = gop->blt(gop, bitmap, EFI_BLT_VIDEO_TO_VIDEO, + 79, 57 + DEPTH, 119, 57 + DEPTH, + 31, 26, 0); + if (ret != EFI_SUCCESS) { + efi_st_error("EFI_BLT_VIDEO_TO_VIDEO failed\n"); + return EFI_ST_FAILURE; + } + + /* Copy port holes back to buffer */ + ret = gop->blt(gop, bitmap, EFI_BLT_VIDEO_TO_BLT_BUFFER, + 94, 57 + DEPTH, 94, 57, + 90, 26, WIDTH * sizeof(struct efi_gop_pixel)); + if (ret != EFI_SUCCESS) { + efi_st_error("EFI_BLT_VIDEO_TO_BLT_BUFFER failed\n"); + return EFI_ST_FAILURE; + } + + /* Set 250ms timer */ + xpos = WIDTH; + ret = boottime->set_timer(event, EFI_TIMER_PERIODIC, 250000); + if (ret != EFI_SUCCESS) { + efi_st_error("Could not set timer\n"); + return EFI_ST_FAILURE; + } + + con_out->set_cursor_position(con_out, 0, 0); + con_out->set_attribute(con_out, EFI_WHITE | EFI_BACKGROUND_BLUE); + efi_st_printf("The submarine should have three yellow port holes.\n"); + efi_st_printf("Press any key to continue"); + efi_st_get_key(); + con_out->set_attribute(con_out, EFI_LIGHTGRAY); + efi_st_printf("\n"); + + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(bitblt) = { + .name = "block image transfer", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, + .teardown = teardown, + .on_request = true, +}; diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c index 9e4b93d9a6..a8979ed56b 100644 --- a/lib/efi_selftest/efi_selftest_block_device.c +++ b/lib/efi_selftest/efi_selftest_block_device.c @@ -29,6 +29,7 @@ static const efi_guid_t block_io_protocol_guid = BLOCK_IO_GUID; static const efi_guid_t guid_device_path = DEVICE_PATH_GUID; static const efi_guid_t guid_simple_file_system_protocol = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; +static const efi_guid_t guid_file_system_info = EFI_FILE_SYSTEM_INFO_GUID; static efi_guid_t guid_vendor = EFI_GUID(0xdbca4c98, 0x6cb0, 0x694d, 0x08, 0x72, 0x81, 0x9c, 0x65, 0x0c, 0xb7, 0xb8); @@ -302,7 +303,11 @@ static int execute(void) struct efi_device_path *dp_partition; struct efi_simple_file_system_protocol *file_system; struct efi_file_handle *root, *file; - u64 buf_size; + struct { + struct efi_file_system_info info; + u16 label[12]; + } system_info; + efi_uintn_t buf_size; char buf[16] __aligned(ARCH_DMA_MINALIGN); ret = boottime->connect_controller(disk_handle, NULL, NULL, 1); @@ -356,6 +361,23 @@ static int execute(void) efi_st_error("Failed to open volume\n"); return EFI_ST_FAILURE; } + buf_size = sizeof(system_info); + ret = root->getinfo(root, &guid_file_system_info, &buf_size, + &system_info); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to get file system info\n"); + return EFI_ST_FAILURE; + } + if (system_info.info.block_size != 512) { + efi_st_error("Wrong block size %u, expected 512\n", + system_info.info.block_size); + return EFI_ST_FAILURE; + } + if (efi_st_strcmp_16_8(system_info.info.volume_label, "U-BOOT TEST")) { + efi_st_todo( + "Wrong volume label '%ps', expected 'U-BOOT TEST'\n", + system_info.info.volume_label); + } ret = root->open(root, &file, (s16 *)L"hello.txt", EFI_FILE_MODE_READ, 0); if (ret != EFI_SUCCESS) { diff --git a/lib/efi_selftest/efi_selftest_devicepath.c b/lib/efi_selftest/efi_selftest_devicepath.c index 92940c7ab6..da68102eb2 100644 --- a/lib/efi_selftest/efi_selftest_devicepath.c +++ b/lib/efi_selftest/efi_selftest_devicepath.c @@ -52,7 +52,7 @@ struct efi_device_path_to_text_protocol *device_path_to_text; * Setup unit test. * * Create three handles. Install a new protocol on two of them and - * provice device paths. + * provide device paths. * * handle1 * guid interface diff --git a/lib/efi_selftest/efi_selftest_devicepath_util.c b/lib/efi_selftest/efi_selftest_devicepath_util.c new file mode 100644 index 0000000000..2b5384f21b --- /dev/null +++ b/lib/efi_selftest/efi_selftest_devicepath_util.c @@ -0,0 +1,286 @@ +/* + * efi_selftest_devicepath_util + * + * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This unit test checks the device path utilities protocol. + */ + +#include <efi_selftest.h> + +static struct efi_boot_services *boottime; + +static efi_guid_t guid_device_path_utilities_protocol = + EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID; + +struct efi_device_path_utilities_protocol *dpu; + +/* + * Setup unit test. + * + * Locate the device path utilities protocol. + * + * @handle: handle of the loaded image + * @systable: system table + */ +static int setup(const efi_handle_t img_handle, + const struct efi_system_table *systable) +{ + int ret; + + boottime = systable->boottime; + + ret = boottime->locate_protocol(&guid_device_path_utilities_protocol, + NULL, (void **)&dpu); + if (ret != EFI_SUCCESS) { + dpu = NULL; + efi_st_error( + "Device path to text protocol is not available.\n"); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +/* + * Create a device path consisting of a single media device node followed by an + * end node. + * + * @length: length of the media device node + * @dp: device path + * @return: status code + */ +static int create_single_node_device_path(unsigned int length, + struct efi_device_path **dp) +{ + struct efi_device_path *node; + efi_uintn_t len; + int ret; + + node = dpu->create_device_node(DEVICE_PATH_TYPE_MEDIA_DEVICE, + DEVICE_PATH_SUB_TYPE_FILE_PATH, length); + if (!node) { + efi_st_error("CreateDeviceNode failed\n"); + return EFI_ST_FAILURE; + } + *dp = dpu->append_device_node(NULL, node); + if (!*dp) { + efi_st_error("AppendDeviceNode failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(node); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + len = dpu->get_device_path_size(*dp); + if (len != length + 4) { + efi_st_error("Wrong device path length %u, expected %u\n", + (unsigned int)len, length); + return EFI_ST_FAILURE; + } + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * In the test device paths are created, copied, and concatenated. The device + * path length is used as a measure of success. + */ +static int execute(void) +{ + struct efi_device_path *dp1; + struct efi_device_path *dp2; + struct efi_device_path *dp3; + + efi_uintn_t len; + int ret; + + /* IsDevicePathMultiInstance(NULL) */ + if (dpu->is_device_path_multi_instance(NULL)) { + efi_st_error("IsDevicePathMultiInstance(NULL) returned true\n"); + return EFI_ST_FAILURE; + } + /* GetDevicePathSize(NULL) */ + len = dpu->get_device_path_size(NULL); + if (len) { + efi_st_error("Wrong device path length %u, expected 0\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + /* DuplicateDevicePath(NULL) */ + dp1 = dpu->duplicate_device_path(NULL); + if (dp1) { + efi_st_error("DuplicateDevicePath(NULL) failed\n"); + return EFI_ST_FAILURE; + } + /* AppendDevicePath(NULL, NULL) */ + dp1 = dpu->append_device_path(NULL, NULL); + if (!dp1) { + efi_st_error("AppendDevicePath(NULL, NULL) failed\n"); + return EFI_ST_FAILURE; + } + len = dpu->get_device_path_size(dp1); + if (len != 4) { + efi_st_error("Wrong device path length %u, expected 4\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp1); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + /* CreateDeviceNode */ + ret = create_single_node_device_path(21, &dp1); + if (ret != EFI_ST_SUCCESS) + return ret; + ret = create_single_node_device_path(17, &dp2); + if (ret != EFI_ST_SUCCESS) + return ret; + /* AppendDevicePath */ + dp3 = dpu->append_device_path(dp1, dp2); + if (!dp3) { + efi_st_error("AppendDevicePath failed\n"); + return EFI_ST_FAILURE; + } + if (dp3 == dp1 || dp3 == dp2) { + efi_st_error("AppendDevicePath reused buffer\n"); + return EFI_ST_FAILURE; + } + len = dpu->get_device_path_size(dp3); + /* 21 + 17 + 4 */ + if (len != 42) { + efi_st_error("Wrong device path length %u, expected 42\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp2); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + /* AppendDeviceNode */ + dp2 = dpu->append_device_node(dp1, dp3); + if (!dp2) { + efi_st_error("AppendDevicePath failed\n"); + return EFI_ST_FAILURE; + } + len = dpu->get_device_path_size(dp2); + /* 21 + 21 + 4 */ + if (len != 46) { + printf("%s(%d) %s\n", __FILE__, __LINE__, __func__); + efi_st_error("Wrong device path length %u, expected 46\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp1); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + /* IsDevicePathMultiInstance */ + if (dpu->is_device_path_multi_instance(dp2)) { + printf("%s(%d) %s\n", __FILE__, __LINE__, __func__); + efi_st_error("IsDevicePathMultiInstance returned true\n"); + return EFI_ST_FAILURE; + } + /* AppendDevicePathInstance */ + dp1 = dpu->append_device_path_instance(dp2, dp3); + if (!dp1) { + efi_st_error("AppendDevicePathInstance failed\n"); + return EFI_ST_FAILURE; + } + len = dpu->get_device_path_size(dp1); + /* 46 + 42 */ + if (len != 88) { + efi_st_error("Wrong device path length %u, expected 88\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + /* IsDevicePathMultiInstance */ + if (!dpu->is_device_path_multi_instance(dp1)) { + efi_st_error("IsDevicePathMultiInstance returned false\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp2); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp3); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + /* GetNextDevicePathInstance */ + dp3 = dp1; + dp2 = dpu->get_next_device_path_instance(&dp1, &len); + if (!dp2) { + efi_st_error("GetNextDevicePathInstance failed\n"); + return EFI_ST_FAILURE; + } + if (!dp1) { + efi_st_error("GetNextDevicePathInstance no 2nd instance\n"); + return EFI_ST_FAILURE; + } + if (len != 46) { + efi_st_error("Wrong device path length %u, expected 46\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + len = dpu->get_device_path_size(dp1); + if (len != 42) { + efi_st_error("Wrong device path length %u, expected 42\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp2); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + dp2 = dpu->get_next_device_path_instance(&dp1, &len); + if (!dp2) { + efi_st_error("GetNextDevicePathInstance failed\n"); + return EFI_ST_FAILURE; + } + if (len != 42) { + efi_st_error("Wrong device path length %u, expected 46\n", + (unsigned int)len); + return EFI_ST_FAILURE; + } + if (dp1) { + efi_st_error("GetNextDevicePathInstance did not signal end\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp2); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + + /* Clean up */ + ret = boottime->free_pool(dp2); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(dp3); + if (ret != EFI_ST_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(dputil) = { + .name = "device path utilities protocol", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, +}; diff --git a/lib/efi_selftest/efi_selftest_disk_image.h b/lib/efi_selftest/efi_selftest_disk_image.h index 4775dace70..9c741ce136 100644 --- a/lib/efi_selftest/efi_selftest_disk_image.h +++ b/lib/efi_selftest/efi_selftest_disk_image.h @@ -3,21 +3,21 @@ * * Generated with tools/file2include * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #define EFI_ST_DISK_IMG { 0x00010000, { \ - {0x000001b8, "\x94\x37\x69\xfc\x00\x00\x00\x00"}, /* .7i..... */ \ - {0x000001c0, "\x02\x00\x83\x02\x02\x00\x01\x00"}, /* ........ */ \ + {0x000001b8, "\x21\x5d\x53\xd1\x00\x00\x00\x00"}, /* !]S..... */ \ + {0x000001c0, "\x02\x00\x01\x02\x02\x00\x01\x00"}, /* ........ */ \ {0x000001c8, "\x00\x00\x7f\x00\x00\x00\x00\x00"}, /* ........ */ \ {0x000001f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \ {0x00000200, "\xeb\x3c\x90\x6d\x6b\x66\x73\x2e"}, /* .<.mkfs. */ \ {0x00000208, "\x66\x61\x74\x00\x02\x04\x01\x00"}, /* fat..... */ \ {0x00000210, "\x02\x00\x02\x7f\x00\xf8\x01\x00"}, /* ........ */ \ {0x00000218, "\x20\x00\x40\x00\x00\x00\x00\x00"}, /* .@..... */ \ - {0x00000220, "\x00\x00\x00\x00\x80\x00\x29\x86"}, /* ......). */ \ - {0x00000228, "\xe8\x82\x80\x4e\x4f\x20\x4e\x41"}, /* ...NO NA */ \ - {0x00000230, "\x4d\x45\x20\x20\x20\x20\x46\x41"}, /* ME FA */ \ + {0x00000220, "\x00\x00\x00\x00\x80\x00\x29\xc4"}, /* ......). */ \ + {0x00000228, "\xc4\x88\x11\x55\x2d\x42\x4f\x4f"}, /* ...U-BOO */ \ + {0x00000230, "\x54\x20\x54\x45\x53\x54\x46\x41"}, /* T TESTFA */ \ {0x00000238, "\x54\x31\x32\x20\x20\x20\x0e\x1f"}, /* T12 .. */ \ {0x00000240, "\xbe\x5b\x7c\xac\x22\xc0\x74\x0b"}, /* .[|.".t. */ \ {0x00000248, "\x56\xb4\x0e\xbb\x07\x00\xcd\x10"}, /* V....... */ \ @@ -36,34 +36,20 @@ {0x000002b0, "\x72\x79\x20\x61\x67\x61\x69\x6e"}, /* ry again */ \ {0x000002b8, "\x20\x2e\x2e\x2e\x20\x0d\x0a\x00"}, /* ... ... */ \ {0x000003f8, "\x00\x00\x00\x00\x00\x00\x55\xaa"}, /* ......U. */ \ - {0x00000400, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \ - {0x00000408, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \ - {0x00000600, "\xf8\xff\xff\x00\x00\x00\x00\xf0"}, /* ........ */ \ - {0x00000608, "\xff\x00\x00\x00\x00\x00\x00\x00"}, /* ........ */ \ - {0x00000800, "\xe5\x70\x00\x00\x00\xff\xff\xff"}, /* .p...... */ \ - {0x00000808, "\xff\xff\xff\x0f\x00\x0e\xff\xff"}, /* ........ */ \ - {0x00000810, "\xff\xff\xff\xff\xff\xff\xff\xff"}, /* ........ */ \ - {0x00000818, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \ - {0x00000820, "\xe5\x2e\x00\x68\x00\x65\x00\x6c"}, /* ...h.e.l */ \ - {0x00000828, "\x00\x6c\x00\x0f\x00\x0e\x6f\x00"}, /* .l....o. */ \ - {0x00000830, "\x2e\x00\x74\x00\x78\x00\x74\x00"}, /* ..t.x.t. */ \ - {0x00000838, "\x2e\x00\x00\x00\x73\x00\x77\x00"}, /* ....s.w. */ \ - {0x00000840, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \ - {0x00000848, "\x53\x57\x50\x20\x00\x64\xd0\x8a"}, /* SWP .d.. */ \ - {0x00000850, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \ - {0x00000858, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \ - {0x00000860, "\x41\x68\x00\x65\x00\x6c\x00\x6c"}, /* Ah.e.l.l */ \ - {0x00000868, "\x00\x6f\x00\x0f\x00\xf1\x2e\x00"}, /* .o...... */ \ - {0x00000870, "\x74\x00\x78\x00\x74\x00\x00\x00"}, /* t.x.t... */ \ - {0x00000878, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \ - {0x00000880, "\x48\x45\x4c\x4c\x4f\x20\x20\x20"}, /* HELLO */ \ - {0x00000888, "\x54\x58\x54\x20\x00\x64\xd4\x8a"}, /* TXT .d.. */ \ - {0x00000890, "\x92\x4b\x92\x4b\x00\x00\xd4\x8a"}, /* .K.K.... */ \ - {0x00000898, "\x92\x4b\x05\x00\x0d\x00\x00\x00"}, /* .K...... */ \ - {0x000008a0, "\xe5\x45\x4c\x4c\x4f\x54\x7e\x31"}, /* .ELLOT~1 */ \ - {0x000008a8, "\x53\x57\x58\x20\x00\x64\xd0\x8a"}, /* SWX .d.. */ \ - {0x000008b0, "\x92\x4b\x92\x4b\x00\x00\xd0\x8a"}, /* .K.K.... */ \ - {0x000008b8, "\x92\x4b\x00\x00\x00\x00\x00\x00"}, /* .K...... */ \ - {0x00006000, "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"}, /* Hello wo */ \ - {0x00006008, "\x72\x6c\x64\x21\x0a\x00\x00\x00"}, /* rld!.... */ \ + {0x00000400, "\xf8\xff\xff\x00\xf0\xff\x00\x00"}, /* ........ */ \ + {0x00000600, "\xf8\xff\xff\x00\xf0\xff\x00\x00"}, /* ........ */ \ + {0x00000800, "\x55\x2d\x42\x4f\x4f\x54\x20\x54"}, /* U-BOOT T */ \ + {0x00000808, "\x45\x53\x54\x08\x00\x00\xaa\x56"}, /* EST....V */ \ + {0x00000810, "\x84\x4c\x84\x4c\x00\x00\xaa\x56"}, /* .L.L...V */ \ + {0x00000818, "\x84\x4c\x00\x00\x00\x00\x00\x00"}, /* .L...... */ \ + {0x00000820, "\x41\x68\x00\x65\x00\x6c\x00\x6c"}, /* Ah.e.l.l */ \ + {0x00000828, "\x00\x6f\x00\x0f\x00\xf1\x2e\x00"}, /* .o...... */ \ + {0x00000830, "\x74\x00\x78\x00\x74\x00\x00\x00"}, /* t.x.t... */ \ + {0x00000838, "\xff\xff\x00\x00\xff\xff\xff\xff"}, /* ........ */ \ + {0x00000840, "\x48\x45\x4c\x4c\x4f\x20\x20\x20"}, /* HELLO */ \ + {0x00000848, "\x54\x58\x54\x20\x00\x64\xd7\x46"}, /* TXT .d.F */ \ + {0x00000850, "\x84\x4c\x84\x4c\x00\x00\xd7\x46"}, /* .L.L...F */ \ + {0x00000858, "\x84\x4c\x03\x00\x0d\x00\x00\x00"}, /* .L...... */ \ + {0x00005000, "\x48\x65\x6c\x6c\x6f\x20\x77\x6f"}, /* Hello wo */ \ + {0x00005008, "\x72\x6c\x64\x21\x0a\x00\x00\x00"}, /* rld!.... */ \ {0, NULL} } } diff --git a/lib/efi_selftest/efi_selftest_event_groups.c b/lib/efi_selftest/efi_selftest_event_groups.c new file mode 100644 index 0000000000..79e4ea1ce2 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_event_groups.c @@ -0,0 +1,140 @@ +/* + * efi_selftest_event_groups + * + * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This test checks the notification of group events and the + * following services: + * CreateEventEx, CloseEvent, SignalEvent, CheckEvent. + */ + +#include <efi_selftest.h> + +#define GROUP_SIZE 16 + +static struct efi_boot_services *boottime; +static efi_guid_t event_group = + EFI_GUID(0x2335905b, 0xc3b9, 0x4221, 0xa3, 0x71, + 0x0e, 0x5b, 0x45, 0xc0, 0x56, 0x91); + +/* + * Notification function, increments the notfication count if parameter + * context is provided. + * + * @event notified event + * @context pointer to the notification count + */ +static void EFIAPI notify(struct efi_event *event, void *context) +{ + unsigned int *count = context; + + if (count) + ++*count; +} + +/* + * Setup unit test. + * + * @handle: handle of the loaded image + * @systable: system table + * @return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t handle, + const struct efi_system_table *systable) +{ + boottime = systable->boottime; + + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * Create multiple events in an event group. Signal each event once and check + * that all events are notified once in each round. + * + * @return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + unsigned int counter[GROUP_SIZE] = {0}; + struct efi_event *events[GROUP_SIZE]; + size_t i, j; + efi_status_t ret; + + for (i = 0; i < GROUP_SIZE; ++i) { + ret = boottime->create_event_ex(0, TPL_NOTIFY, + notify, (void *)&counter[i], + &event_group, &events[i]); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to create event\n"); + return EFI_ST_FAILURE; + } + } + + for (i = 0; i < GROUP_SIZE; ++i) { + ret = boottime->signal_event(events[i]); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to signal event\n"); + return EFI_ST_FAILURE; + } + for (j = 0; j < GROUP_SIZE; ++j) { + if (counter[j] != i) { + efi_st_printf("i %u, j %u, count %u\n", + (unsigned int)i, (unsigned int)j, + (unsigned int)counter[j]); + efi_st_error( + "Notification function was called\n"); + return EFI_ST_FAILURE; + } + /* Clear signaled state */ + ret = boottime->check_event(events[j]); + if (ret != EFI_SUCCESS) { + efi_st_error("Event was not signaled\n"); + return EFI_ST_FAILURE; + } + if (counter[j] != i) { + efi_st_printf("i %u, j %u, count %u\n", + (unsigned int)i, (unsigned int)j, + (unsigned int)counter[j]); + efi_st_error( + "Notification function was called\n"); + return EFI_ST_FAILURE; + } + /* Call notification function */ + ret = boottime->check_event(events[j]); + if (ret != EFI_NOT_READY) { + efi_st_error( + "Signaled state not cleared\n"); + return EFI_ST_FAILURE; + } + if (counter[j] != i + 1) { + efi_st_printf("i %u, j %u, count %u\n", + (unsigned int)i, (unsigned int)j, + (unsigned int)counter[j]); + efi_st_error( + "Nofification function not called\n"); + return EFI_ST_FAILURE; + } + } + } + + for (i = 0; i < GROUP_SIZE; ++i) { + ret = boottime->close_event(events[i]); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to close event\n"); + return EFI_ST_FAILURE; + } + } + + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(eventgoups) = { + .name = "event groups", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, +}; diff --git a/lib/efi_selftest/efi_selftest_fdt.c b/lib/efi_selftest/efi_selftest_fdt.c new file mode 100644 index 0000000000..e5a8d6a6ae --- /dev/null +++ b/lib/efi_selftest/efi_selftest_fdt.c @@ -0,0 +1,188 @@ +/* + * efi_selftest_pos + * + * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Test the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL. + * + * The following services are tested: + * OutputString, TestString, SetAttribute. + */ + +#include <efi_selftest.h> +#include <linux/libfdt.h> + +static struct efi_boot_services *boottime; +static const char *fdt; + +/* This should be sufficent for */ +#define BUFFERSIZE 0x100000 + +static efi_guid_t fdt_guid = EFI_FDT_GUID; + +/* + * Convert FDT value to host endianness. + * + * @val FDT value + * @return converted value + */ +static uint32_t f2h(fdt32_t val) +{ + char *buf = (char *)&val; + char i; + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + /* Swap the bytes */ + i = buf[0]; buf[0] = buf[3]; buf[3] = i; + i = buf[1]; buf[1] = buf[2]; buf[2] = i; +#endif + return *(uint32_t *)buf; +} + +/* + * Return the value of a property of the FDT root node. + * + * @name name of the property + * @return value of the property + */ +static char *get_property(const u16 *property) +{ + struct fdt_header *header = (struct fdt_header *)fdt; + const fdt32_t *pos; + const char *strings; + + if (!header) + return NULL; + + if (f2h(header->magic) != FDT_MAGIC) { + printf("Wrong magic\n"); + return NULL; + } + + pos = (fdt32_t *)(fdt + f2h(header->off_dt_struct)); + strings = fdt + f2h(header->off_dt_strings); + + for (;;) { + switch (f2h(pos[0])) { + case FDT_BEGIN_NODE: { + char *c = (char *)&pos[1]; + size_t i; + + for (i = 0; c[i]; ++i) + ; + pos = &pos[2 + (i >> 2)]; + break; + } + case FDT_PROP: { + struct fdt_property *prop = (struct fdt_property *)pos; + const char *label = &strings[f2h(prop->nameoff)]; + efi_status_t ret; + + /* Check if this is the property to be returned */ + if (!efi_st_strcmp_16_8(property, label)) { + char *str; + efi_uintn_t len = f2h(prop->len); + + if (!len) + return NULL; + /* + * The string might not be 0 terminated. + * It is safer to make a copy. + */ + ret = boottime->allocate_pool( + EFI_LOADER_DATA, len + 1, + (void **)&str); + if (ret != EFI_SUCCESS) { + efi_st_printf("AllocatePool failed\n"); + return NULL; + } + boottime->copy_mem(str, &pos[3], len); + str[len] = 0; + + return str; + } + + pos = &pos[3 + ((f2h(prop->len) + 3) >> 2)]; + break; + } + case FDT_NOP: + pos = &pos[1]; + break; + default: + return NULL; + } + } +} + +/* + * Setup unit test. + * + * @handle: handle of the loaded image + * @systable: system table + * @return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t img_handle, + const struct efi_system_table *systable) +{ + efi_uintn_t i; + + boottime = systable->boottime; + + /* Find configuration tables */ + for (i = 0; i < systable->nr_tables; ++i) { + if (!efi_st_memcmp(&systable->tables[i].guid, &fdt_guid, + sizeof(efi_guid_t))) + fdt = systable->tables[i].table; + } + if (!fdt) { + efi_st_error("Missing device tree\n"); + return EFI_ST_FAILURE; + } + + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * @return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + char *str; + efi_status_t ret; + + str = get_property(L"compatible"); + if (str) { + efi_st_printf("compatible: %s\n", str); + ret = boottime->free_pool(str); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + } else { + efi_st_printf("Missing property 'compatible'\n"); + return EFI_ST_FAILURE; + } + str = get_property(L"serial-number"); + if (str) { + efi_st_printf("serial-number: %s\n", str); + ret = boottime->free_pool(str); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } + } + + return EFI_ST_SUCCESS; +} + +EFI_UNIT_TEST(fdt) = { + .name = "device tree", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, + .on_request = true, +}; diff --git a/lib/efi_selftest/efi_selftest_textinput.c b/lib/efi_selftest/efi_selftest_textinput.c new file mode 100644 index 0000000000..c890ff88b7 --- /dev/null +++ b/lib/efi_selftest/efi_selftest_textinput.c @@ -0,0 +1,182 @@ +/* + * efi_selftest_textinput + * + * Copyright (c) 2018 Heinrich Schuchardt <xypron.glpk@gmx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Provides a unit test for the EFI_SIMPLE_TEXT_INPUT_PROTOCOL. + * The unicode character and the scan code are printed for text + * input. To run the test: + * + * setenv efi_selftest text input + * bootefi selftest + */ + +#include <efi_selftest.h> + +struct translate { + u16 code; + u16 *text; +}; + +static struct efi_boot_services *boottime; + +static struct translate control_characters[] = { + {0, L"Null"}, + {8, L"BS"}, + {9, L"TAB"}, + {10, L"LF"}, + {13, L"CR"}, + {0, NULL}, +}; + +static u16 ch[] = L"' '"; +static u16 unknown[] = L"unknown"; + +static struct translate scan_codes[] = { + {0x00, L"Null"}, + {0x01, L"Up"}, + {0x02, L"Down"}, + {0x03, L"Right"}, + {0x04, L"Left"}, + {0x05, L"Home"}, + {0x06, L"End"}, + {0x07, L"Insert"}, + {0x08, L"Delete"}, + {0x09, L"Page Up"}, + {0x0a, L"Page Down"}, + {0x0b, L"FN 1"}, + {0x0c, L"FN 2"}, + {0x0d, L"FN 3"}, + {0x0e, L"FN 4"}, + {0x0f, L"FN 5"}, + {0x10, L"FN 6"}, + {0x11, L"FN 7"}, + {0x12, L"FN 8"}, + {0x13, L"FN 9"}, + {0x14, L"FN 10"}, + {0x15, L"FN 11"}, + {0x16, L"FN 12"}, + {0x17, L"Escape"}, + {0x68, L"FN 13"}, + {0x69, L"FN 14"}, + {0x6a, L"FN 15"}, + {0x6b, L"FN 16"}, + {0x6c, L"FN 17"}, + {0x6d, L"FN 18"}, + {0x6e, L"FN 19"}, + {0x6f, L"FN 20"}, + {0x70, L"FN 21"}, + {0x71, L"FN 22"}, + {0x72, L"FN 23"}, + {0x73, L"FN 24"}, + {0x7f, L"Mute"}, + {0x80, L"Volume Up"}, + {0x81, L"Volume Down"}, + {0x100, L"Brightness Up"}, + {0x101, L"Brightness Down"}, + {0x102, L"Suspend"}, + {0x103, L"Hibernate"}, + {0x104, L"Toggle Display"}, + {0x105, L"Recovery"}, + {0x106, L"Reject"}, + {0x0, NULL}, +}; + +/* + * Translate a unicode character to a string. + * + * @code unicode character + * @return string + */ +static u16 *translate_char(u16 code) +{ + struct translate *tr; + + if (code >= ' ') { + ch[1] = code; + return ch; + } + for (tr = control_characters; tr->text; ++tr) { + if (tr->code == code) + return tr->text; + } + return unknown; +} + +/* + * Translate a scan code to a human readable string. + * + * @code unicode character + * @return string + */ +static u16 *translate_code(u16 code) +{ + struct translate *tr; + + for (tr = scan_codes; tr->text; ++tr) { + if (tr->code == code) + return tr->text; + } + return unknown; +} + +/* + * Setup unit test. + * + * @handle: handle of the loaded image + * @systable: system table + * @return: EFI_ST_SUCCESS for success + */ +static int setup(const efi_handle_t handle, + const struct efi_system_table *systable) +{ + boottime = systable->boottime; + + return EFI_ST_SUCCESS; +} + +/* + * Execute unit test. + * + * @return: EFI_ST_SUCCESS for success + */ +static int execute(void) +{ + struct efi_input_key input_key = {0}; + efi_status_t ret; + + efi_st_printf("Waiting for your input\n"); + efi_st_printf("To terminate type 'x'\n"); + + for (;;) { + /* Wait for next key */ + do { + ret = con_in->read_key_stroke(con_in, &input_key); + } while (ret == EFI_NOT_READY); + + /* Allow 5 minutes until time out */ + boottime->set_watchdog_timer(300, 0, 0, NULL); + + efi_st_printf("Unicode char %u (%ps), scan code %u (%ps)\n", + (unsigned int)input_key.unicode_char, + translate_char(input_key.unicode_char), + (unsigned int)input_key.scan_code, + translate_code(input_key.scan_code)); + + switch (input_key.unicode_char) { + case 'x': + case 'X': + return EFI_ST_SUCCESS; + } + } +} + +EFI_UNIT_TEST(textinput) = { + .name = "text input", + .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT, + .setup = setup, + .execute = execute, + .on_request = true, +}; diff --git a/net/Kconfig b/net/Kconfig index 143c4416cd..f2363e5256 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -22,55 +22,4 @@ config NETCONSOLE Support the 'nc' input/output device for networked console. See README.NetConsole for details. -config NET_TFTP_VARS - bool "Control TFTP timeout and count through environment" - depends on CMD_NET - default y - help - If set, allows controlling the TFTP timeout through the - environment variable tftptimeout, and the TFTP maximum - timeout count through the variable tftptimeoutcountmax. - If unset, timeout and maximum are hard-defined as 1 second - and 10 timouts per TFTP transfer. - -config BOOTP_BOOTPATH - bool "Enable BOOTP BOOTPATH" - depends on CMD_NET - -config BOOTP_DNS - bool "Enable bootp DNS" - depends on CMD_NET - -config BOOTP_GATEWAY - bool "Enable BOOTP gateway" - depends on CMD_NET - -config BOOTP_HOSTNAME - bool "Enable BOOTP hostname" - depends on CMD_NET - -config BOOTP_PXE - bool "Enable BOOTP PXE" - depends on CMD_NET - -config BOOTP_SUBNETMASK - bool "Enable BOOTP subnetmask" - depends on CMD_NET - depends on CMD_NET - -config BOOTP_PXE_CLIENTARCH - hex - depends on CMD_NET - default 0x16 if ARM64 - default 0x15 if ARM - default 0 if X86 - -config BOOTP_VCI_STRING - string - depends on CMD_NET - default "U-Boot.armv7" if CPU_V7 || CPU_V7M - default "U-Boot.armv8" if ARM64 - default "U-Boot.arm" if ARM - default "U-Boot" - endif # if NET diff --git a/net/Makefile b/net/Makefile index ae54eee5af..ce6e5adfa5 100644 --- a/net/Makefile +++ b/net/Makefile @@ -8,23 +8,23 @@ #ccflags-y += -DDEBUG obj-y += checksum.o -obj-$(CONFIG_CMD_NET) += arp.o -obj-$(CONFIG_CMD_NET) += bootp.o +obj-$(CONFIG_NET) += arp.o +obj-$(CONFIG_CMD_BOOTP) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o obj-$(CONFIG_CMD_DNS) += dns.o ifdef CONFIG_DM_ETH -obj-$(CONFIG_CMD_NET) += eth-uclass.o +obj-$(CONFIG_NET) += eth-uclass.o else -obj-$(CONFIG_CMD_NET) += eth_legacy.o +obj-$(CONFIG_NET) += eth_legacy.o endif -obj-$(CONFIG_CMD_NET) += eth_common.o +obj-$(CONFIG_NET) += eth_common.o obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o -obj-$(CONFIG_CMD_NET) += net.o +obj-$(CONFIG_NET) += net.o obj-$(CONFIG_CMD_NFS) += nfs.o obj-$(CONFIG_CMD_PING) += ping.o obj-$(CONFIG_CMD_RARP) += rarp.o obj-$(CONFIG_CMD_SNTP) += sntp.o -obj-$(CONFIG_CMD_NET) += tftp.o +obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o # Disable this warning as it is triggered by: # sprintf(buf, index ? "foo%d" : "foo", index) diff --git a/net/eth_common.c b/net/eth_common.c index 66d0d22966..0af91a9642 100644 --- a/net/eth_common.c +++ b/net/eth_common.c @@ -8,40 +8,11 @@ #include <common.h> #include <dm.h> +#include <environment.h> #include <miiphy.h> #include <net.h> #include "eth_internal.h" -void eth_parse_enetaddr(const char *addr, uchar *enetaddr) -{ - char *end; - int i; - - for (i = 0; i < 6; ++i) { - enetaddr[i] = addr ? simple_strtoul(addr, &end, 16) : 0; - if (addr) - addr = (*end) ? end + 1 : end; - } -} - -int eth_env_get_enetaddr(const char *name, uchar *enetaddr) -{ - eth_parse_enetaddr(env_get(name), enetaddr); - return is_valid_ethaddr(enetaddr); -} - -int eth_env_set_enetaddr(const char *name, const uchar *enetaddr) -{ - char buf[ARP_HLEN_ASCII + 1]; - - if (eth_env_get_enetaddr(name, (uchar *)buf)) - return -EEXIST; - - sprintf(buf, "%pM", enetaddr); - - return env_set(name, buf); -} - int eth_env_get_enetaddr_by_index(const char *base_name, int index, uchar *enetaddr) { diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8f21653136..c6b3f69064 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -521,7 +521,7 @@ cmd_xzmisc = (cat $(filter-out FORCE,$^) | \ MKIMAGEOUTPUT ?= /dev/null quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) # fdtgrep # --------------------------------------------------------------------------- diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 2993ade41e..7f2908d799 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -144,7 +144,7 @@ MKIMAGEOUTPUT ?= /dev/null quiet_cmd_mkimage = MKIMAGE $@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >$(MKIMAGEOUTPUT)) + >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) MKIMAGEFLAGS_MLO = -T omapimage -a $(CONFIG_SPL_TEXT_BASE) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index e450826c36..373094e59e 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -145,7 +145,8 @@ sub list_types { close($script); my @types = (); - for ($text =~ /\b(?:(?:CHK|WARN|ERROR)\s*\(\s*"([^"]+)")/g) { + # Also catch when type or level is passed through a variable + for ($text =~ /(?:(?:\bCHK|\bWARN|\bERROR|&\{\$msg_level})\s*\(|\$msg_type\s*=)\s*"([^"]+)"/g) { push (@types, $_); } @types = sort(uniq(@types)); @@ -392,7 +393,7 @@ our $Binary = qr{(?i)0b[01]+$Int_type?}; our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?}; our $Int = qr{[0-9]+$Int_type?}; our $Octal = qr{0[0-7]+$Int_type?}; -our $String = qr{(?:\bL)?"[X\t]*"}; +our $String = qr{"[X\t]*"}; our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; @@ -453,6 +454,7 @@ our $zero_initializer = qr{(?:(?:0[xX])?0+$Int_type?|NULL|false)\b}; our $logFunctions = qr{(?x: printk(?:_ratelimited|_once|_deferred_once|_deferred|)| (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| + TP_printk| WARN(?:_RATELIMIT|_ONCE|)| panic| MODULE_[A-Z_]+| @@ -564,6 +566,7 @@ foreach my $entry (@mode_permission_funcs) { $mode_perms_search .= '|' if ($mode_perms_search ne ""); $mode_perms_search .= $entry->[0]; } +$mode_perms_search = "(?:${mode_perms_search})"; our $mode_perms_world_writable = qr{ S_IWUGO | @@ -598,6 +601,37 @@ foreach my $entry (keys %mode_permission_string_types) { $mode_perms_string_search .= '|' if ($mode_perms_string_search ne ""); $mode_perms_string_search .= $entry; } +our $single_mode_perms_string_search = "(?:${mode_perms_string_search})"; +our $multi_mode_perms_string_search = qr{ + ${single_mode_perms_string_search} + (?:\s*\|\s*${single_mode_perms_string_search})* +}x; + +sub perms_to_octal { + my ($string) = @_; + + return trim($string) if ($string =~ /^\s*0[0-7]{3,3}\s*$/); + + my $val = ""; + my $oval = ""; + my $to = 0; + my $curpos = 0; + my $lastpos = 0; + while ($string =~ /\b(($single_mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) { + $curpos = pos($string); + my $match = $2; + my $omatch = $1; + last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos)); + $lastpos = $curpos; + $to |= $mode_permission_string_types{$match}; + $val .= '\s*\|\s*' if ($val ne ""); + $val .= $match; + $oval .= $omatch; + } + $oval =~ s/^\s*\|\s*//; + $oval =~ s/\s*\|\s*$//; + return sprintf("%04o", $to); +} our $allowed_asm_includes = qr{(?x: irq| @@ -757,7 +791,8 @@ our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant|$String)}; our $declaration_macros = qr{(?x: (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(| (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(| - (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\( + (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\(| + (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\( )}; sub deparenthesize { @@ -1041,7 +1076,7 @@ sub parse_email { } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { $address = $1; $comment = $2 if defined $2; - $formatted_email =~ s/$address.*$//; + $formatted_email =~ s/\Q$address\E.*$//; $name = $formatted_email; $name = trim($name); $name =~ s/^\"|\"$//g; @@ -1183,7 +1218,7 @@ sub sanitise_line { for ($off = 1; $off < length($line); $off++) { $c = substr($line, $off, 1); - # Comments we are wacking completly including the begin + # Comments we are whacking completely including the begin # and end, all to $;. if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { $sanitise_quote = '*/'; @@ -1263,6 +1298,7 @@ sub sanitise_line { sub get_quoted_string { my ($line, $rawline) = @_; + return "" if (!defined($line) || !defined($rawline)); return "" if ($line !~ m/($String)/g); return substr($rawline, $-[0], $+[0] - $-[0]); } @@ -1610,6 +1646,28 @@ sub raw_line { return $line; } +sub get_stat_real { + my ($linenr, $lc) = @_; + + my $stat_real = raw_line($linenr, 0); + for (my $count = $linenr + 1; $count <= $lc; $count++) { + $stat_real = $stat_real . "\n" . raw_line($count, 0); + } + + return $stat_real; +} + +sub get_stat_here { + my ($linenr, $cnt, $here) = @_; + + my $herectx = $here . "\n"; + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + return $herectx; +} + sub cat_vet { my ($vet) = @_; my ($res, $coded); @@ -2223,6 +2281,8 @@ sub process { my $camelcase_file_seeded = 0; + my $checklicenseline = 1; + sanitise_line_reset(); my $line; foreach my $rawline (@rawlines) { @@ -2414,6 +2474,7 @@ sub process { } else { $check = $check_orig; } + $checklicenseline = 1; next; } @@ -2715,10 +2776,10 @@ sub process { my $typo_fix = $spelling_fix{lc($typo)}; $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/); $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/); - my $msg_type = \&WARN; - $msg_type = \&CHK if ($file); - if (&{$msg_type}("TYPO_SPELLING", - "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) && + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + if (&{$msg_level}("TYPO_SPELLING", + "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) && $fix) { $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/; } @@ -2753,17 +2814,20 @@ sub process { $rawline =~ /\b59\s+Temple\s+Pl/i || $rawline =~ /\b51\s+Franklin\s+St/i) { my $herevet = "$here\n" . cat_vet($rawline) . "\n"; - my $msg_type = \&ERROR; - $msg_type = \&CHK if ($file); - &{$msg_type}("FSF_MAILING_ADDRESS", - "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet) + my $msg_level = \&ERROR; + $msg_level = \&CHK if ($file); + &{$msg_level}("FSF_MAILING_ADDRESS", + "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet) } # check for Kconfig help text having a real description # Only applies when adding the entry originally, after that we do not have # sufficient context to determine whether it is indeed long enough. if ($realfile =~ /Kconfig/ && - $line =~ /^\+\s*config\s+/) { + # 'choice' is usually the last thing on the line (though + # Kconfig supports named choices), so use a word boundary + # (\b) rather than a whitespace character (\s) + $line =~ /^\+\s*(?:config|menuconfig|choice)\b/) { my $length = 0; my $cnt = $realcnt; my $ln = $linenr + 1; @@ -2778,9 +2842,13 @@ sub process { next if ($f =~ /^-/); last if (!$file && $f =~ /^\@\@/); - if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate)\s*\"/) { + if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate|prompt)\s*["']/) { $is_start = 1; - } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) { + } elsif ($lines[$ln - 1] =~ /^\+\s*(?:help|---help---)\s*$/) { + if ($lines[$ln - 1] =~ "---help---") { + WARN("CONFIG_DESCRIPTION", + "prefer 'help' over '---help---' for new help texts\n" . $herecurr); + } $length = -1; } @@ -2788,7 +2856,13 @@ sub process { $f =~ s/#.*//; $f =~ s/^\s+//; next if ($f =~ /^$/); - if ($f =~ /^\s*config\s/) { + + # This only checks context lines in the patch + # and so hopefully shouldn't trigger false + # positives, even though some of these are + # common words in help texts + if ($f =~ /^\s*(?:config|menuconfig|choice|endchoice| + if|endif|menu|endmenu|source)\b/x) { $is_end = 1; last; } @@ -2864,6 +2938,30 @@ sub process { } } +# check for using SPDX license tag at beginning of files + if ($realline == $checklicenseline) { + if ($rawline =~ /^[ \+]\s*\#\!\s*\//) { + $checklicenseline = 2; + } elsif ($rawline =~ /^\+/) { + my $comment = ""; + if ($realfile =~ /\.(h|s|S)$/) { + $comment = '/*'; + } elsif ($realfile =~ /\.(c|dts|dtsi)$/) { + $comment = '//'; + } elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc)$/) { + $comment = '#'; + } elsif ($realfile =~ /\.rst$/) { + $comment = '..'; + } + + if ($comment !~ /^$/ && + $rawline !~ /^\+\Q$comment\E SPDX-License-Identifier: /) { + WARN("SPDX_LICENSE_TAG", + "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr); + } + } + } + # check we are in a valid source file if not then ignore this hunk next if ($realfile !~ /\.(h|c|s|S|sh|dtsi|dts)$/); @@ -2873,9 +2971,10 @@ sub process { # logging functions like pr_info that end in a string # lines with a single string # #defines that are a single string +# lines with an RFC3986 like URL # # There are 3 different line length message types: -# LONG_LINE_COMMENT a comment starts before but extends beyond $max_linelength +# LONG_LINE_COMMENT a comment starts before but extends beyond $max_line_length # LONG_LINE_STRING a string starts before but extends beyond $max_line_length # LONG_LINE all other lines longer than $max_line_length # @@ -2899,8 +2998,13 @@ sub process { $line =~ /^\+\s*#\s*define\s+\w+\s+$String$/) { $msg_type = ""; - # EFI_GUID is another special case - } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/) { + # More special cases + } elsif ($line =~ /^\+.*\bEFI_GUID\s*\(/ || + $line =~ /^\+\s*(?:\w+)?\s*DEFINE_PER_CPU/) { + $msg_type = ""; + + # URL ($rawline is used in case the URL is in a comment) + } elsif ($rawline =~ /^\+.*\b[a-z][\w\.\+\-]*:\/\/\S+/i) { $msg_type = ""; # Otherwise set the alternate message types @@ -2929,20 +3033,6 @@ sub process { "adding a line without newline at end of file\n" . $herecurr); } -# Blackfin: use hi/lo macros - if ($realfile =~ m@arch/blackfin/.*\.S$@) { - if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("LO_MACRO", - "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); - } - if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("HI_MACRO", - "use the HI() macro, not (... >> 16)\n" . $herevet); - } - } - # check we are in a valid source file C or perl if not then ignore this hunk next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/); @@ -2980,7 +3070,7 @@ sub process { # check indentation starts on a tab stop if ($^V && $^V ge 5.10.0 && - $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$))/) { + $sline =~ /^\+\t+( +)(?:$c90_Keywords\b|\{\s*$|\}\s*(?:else\b|while\b|\s*$)|$Declare\s*$Ident\s*[;=])/) { my $indent = length($1); if ($indent % 8) { if (WARN("TABSTOP", @@ -3102,6 +3192,7 @@ sub process { $line =~ /^\+[a-z_]*init/ || $line =~ /^\+\s*(?:static\s+)?[A-Z_]*ATTR/ || $line =~ /^\+\s*DECLARE/ || + $line =~ /^\+\s*builtin_[\w_]*driver/ || $line =~ /^\+\s*__setup/)) { if (CHK("LINE_SPACING", "Please use a blank line after function/struct/union/enum declarations\n" . $hereprev) && @@ -3181,6 +3272,12 @@ sub process { # check we are in a valid C source file if not then ignore this hunk next if ($realfile !~ /\.(h|c)$/); +# check for unusual line ending [ or ( + if ($line =~ /^\+.*([\[\(])\s*$/) { + CHK("OPEN_ENDED_LINE", + "Lines should not end with a '$1'\n" . $herecurr); + } + # check if this appears to be the start function declaration, save the name if ($sline =~ /^\+\{\s*$/ && $prevline =~ /^\+(?:(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*)?($Ident)\(/) { @@ -3222,18 +3319,6 @@ sub process { "CVS style keyword markers, these will _not_ be updated\n". $herecurr); } -# Blackfin: don't use __builtin_bfin_[cs]sync - if ($line =~ /__builtin_bfin_csync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("CSYNC", - "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); - } - if ($line =~ /__builtin_bfin_ssync/) { - my $herevet = "$here\n" . cat_vet($line) . "\n"; - ERROR("SSYNC", - "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); - } - # check for old HOTPLUG __dev<foo> section markings if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { WARN("HOTPLUG_SECTION", @@ -3810,10 +3895,10 @@ sub process { # avoid BUG() or BUG_ON() if ($line =~ /\b(?:BUG|BUG_ON)\b/) { - my $msg_type = \&WARN; - $msg_type = \&CHK if ($file); - &{$msg_type}("AVOID_BUG", - "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr); + my $msg_level = \&WARN; + $msg_level = \&CHK if ($file); + &{$msg_level}("AVOID_BUG", + "Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\n" . $herecurr); } # avoid LINUX_VERSION_CODE @@ -3828,28 +3913,10 @@ sub process { "Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\n" . $herecurr); } -# printk should use KERN_* levels. Note that follow on printk's on the -# same line do not need a level, so we use the current block context -# to try and find and validate the current printk. In summary the current -# printk includes all preceding printk's which have no newline on the end. -# we assume the first bad printk is the one to report. - if ($line =~ /\bprintk\((?!KERN_)\s*"/) { - my $ok = 0; - for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { - #print "CHECK<$lines[$ln - 1]\n"; - # we have a preceding printk if it ends - # with "\n" ignore it, else it is to blame - if ($lines[$ln - 1] =~ m{\bprintk\(}) { - if ($rawlines[$ln - 1] !~ m{\\n"}) { - $ok = 1; - } - last; - } - } - if ($ok == 0) { - WARN("PRINTK_WITHOUT_KERN_LEVEL", - "printk() should include KERN_ facility level\n" . $herecurr); - } +# printk should use KERN_* levels + if ($line =~ /\bprintk\s*\(\s*(?!KERN_[A-Z]+\b)/) { + WARN("PRINTK_WITHOUT_KERN_LEVEL", + "printk() should include KERN_<LEVEL> facility level\n" . $herecurr); } if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { @@ -3890,10 +3957,12 @@ sub process { # function brace can't be on same line, except for #defines of do while, # or if closed on same line - if (($line=~/$Type\s*$Ident\(.*\).*\s*{/) and - !($line=~/\#\s*define.*do\s\{/) and !($line=~/}/)) { + if ($^V && $^V ge 5.10.0 && + $sline =~ /$Type\s*$Ident\s*$balanced_parens\s*\{/ && + $sline !~ /\#\s*define\b.*do\s*\{/ && + $sline !~ /}/) { if (ERROR("OPEN_BRACE", - "open brace '{' following function declarations go on the next line\n" . $herecurr) && + "open brace '{' following function definitions go on the next line\n" . $herecurr) && $fix) { fix_delete_line($fixlinenr, $rawline); my $fixed_line = $rawline; @@ -4339,11 +4408,11 @@ sub process { # messages are ERROR, but ?: are CHK if ($ok == 0) { - my $msg_type = \&ERROR; - $msg_type = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/); + my $msg_level = \&ERROR; + $msg_level = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/); - if (&{$msg_type}("SPACING", - "spaces required around that '$op' $at\n" . $hereptr)) { + if (&{$msg_level}("SPACING", + "spaces required around that '$op' $at\n" . $hereptr)) { $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; if (defined $fix_elements[$n + 2]) { $fix_elements[$n + 2] =~ s/^\s+//; @@ -4496,6 +4565,32 @@ sub process { } } +# check for unnecessary parentheses around comparisons in if uses +# when !drivers/staging or command-line uses --strict + if (($realfile !~ m@^(?:drivers/staging/)@ || $check_orig) && + $^V && $^V ge 5.10.0 && defined($stat) && + $stat =~ /(^.\s*if\s*($balanced_parens))/) { + my $if_stat = $1; + my $test = substr($2, 1, -1); + my $herectx; + while ($test =~ /(?:^|[^\w\&\!\~])+\s*\(\s*([\&\!\~]?\s*$Lval\s*(?:$Compare\s*$FuncArg)?)\s*\)/g) { + my $match = $1; + # avoid parentheses around potential macro args + next if ($match =~ /^\s*\w+\s*$/); + if (!defined($herectx)) { + $herectx = $here . "\n"; + my $cnt = statement_rawlines($if_stat); + for (my $n = 0; $n < $cnt; $n++) { + my $rl = raw_line($linenr, $n); + $herectx .= $rl . "\n"; + last if $rl =~ /^[ \+].*\{/; + } + } + CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around '$match'\n" . $herectx); + } + } + #goto labels aren't indented, allow a single space however if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { @@ -4884,12 +4979,8 @@ sub process { #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; $ctx =~ s/\n*$//; - my $herectx = $here . "\n"; my $stmt_cnt = statement_rawlines($ctx); - - for (my $n = 0; $n < $stmt_cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } + my $herectx = get_stat_here($linenr, $stmt_cnt, $here); if ($dstat ne '' && $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), @@ -4961,12 +5052,9 @@ sub process { # check for macros with flow control, but without ## concatenation # ## concatenation is commonly a macro that defines a function so ignore those if ($has_flow_statement && !$has_arg_concat) { - my $herectx = $here . "\n"; my $cnt = statement_rawlines($ctx); + my $herectx = get_stat_here($linenr, $cnt, $here); - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } WARN("MACRO_WITH_FLOW_CONTROL", "Macros with flow control statements should be avoided\n" . "$herectx"); } @@ -5006,11 +5094,7 @@ sub process { $ctx =~ s/\n*$//; my $cnt = statement_rawlines($ctx); - my $herectx = $here . "\n"; - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } + my $herectx = get_stat_here($linenr, $cnt, $here); if (($stmts =~ tr/;/;/) == 1 && $stmts !~ /^\s*(if|while|for|switch)\b/) { @@ -5024,11 +5108,7 @@ sub process { } elsif ($dstat =~ /^\+\s*#\s*define\s+$Ident.*;\s*$/) { $ctx =~ s/\n*$//; my $cnt = statement_rawlines($ctx); - my $herectx = $here . "\n"; - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } + my $herectx = get_stat_here($linenr, $cnt, $here); WARN("TRAILING_SEMICOLON", "macros should not use a trailing semicolon\n" . "$herectx"); @@ -5151,12 +5231,8 @@ sub process { } } if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { - my $herectx = $here . "\n"; my $cnt = statement_rawlines($block); - - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } + my $herectx = get_stat_here($linenr, $cnt, $here); WARN("BRACES", "braces {} are not necessary for single statement blocks\n" . $herectx); @@ -5254,14 +5330,13 @@ sub process { } # concatenated string without spaces between elements - if ($line =~ /$String[A-Z_]/ || - ($line =~ /([A-Za-z0-9_]+)$String/ && $1 !~ /^L$/)) { + if ($line =~ /$String[A-Z_]/ || $line =~ /[A-Za-z0-9_]$String/) { CHK("CONCATENATED_STRING", "Concatenated strings should use spaces between elements\n" . $herecurr); } # uncoalesced string fragments - if ($line =~ /$String\s*L?"/) { + if ($line =~ /$String\s*"/) { WARN("STRING_FRAGMENTS", "Consecutive strings are generally better as a single string\n" . $herecurr); } @@ -5292,7 +5367,7 @@ sub process { } # check for line continuations in quoted strings with odd counts of " - if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { + if ($rawline =~ /\\$/ && $sline =~ tr/"/"/ % 2) { WARN("LINE_CONTINUATIONS", "Avoid line continuations in quoted strings\n" . $herecurr); } @@ -5571,6 +5646,12 @@ sub process { } } +# check for smp_read_barrier_depends and read_barrier_depends + if (!$file && $line =~ /\b(smp_|)read_barrier_depends\s*\(/) { + WARN("READ_BARRIER_DEPENDS", + "$1read_barrier_depends should only be used in READ_ONCE or DEC Alpha code\n" . $herecurr); + } + # check of hardware specific defines if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { CHK("ARCH_DEFINES", @@ -5734,29 +5815,50 @@ sub process { } } - # check for vsprintf extension %p<foo> misuses +# check for vsprintf extension %p<foo> misuses if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+(?![^\{]*\{\s*).*\b(\w+)\s*\(.*$String\s*,/s && $1 !~ /^_*volatile_*$/) { - my $bad_extension = ""; + my $specifier; + my $extension; + my $bad_specifier = ""; + my $stat_real; + my $lc = $stat =~ tr@\n@@; $lc = $lc + $linenr; for (my $count = $linenr; $count <= $lc; $count++) { my $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0)); $fmt =~ s/%%//g; - if ($fmt =~ /(\%[\*\d\.]*p(?![\WFfSsBKRraEhMmIiUDdgVCbGNO]).)/) { - $bad_extension = $1; - last; + + while ($fmt =~ /(\%[\*\d\.]*p(\w))/g) { + $specifier = $1; + $extension = $2; + if ($extension !~ /[SsBKRraEhMmIiUDdgVCbGNOx]/) { + $bad_specifier = $specifier; + last; + } + if ($extension eq "x" && !defined($stat_real)) { + if (!defined($stat_real)) { + $stat_real = get_stat_real($linenr, $lc); + } + WARN("VSPRINTF_SPECIFIER_PX", + "Using vsprintf specifier '\%px' potentially exposes the kernel memory layout, if you don't really need the address please consider using '\%p'.\n" . "$here\n$stat_real\n"); + } } - } - if ($bad_extension ne "") { - my $stat_real = raw_line($linenr, 0); - for (my $count = $linenr + 1; $count <= $lc; $count++) { - $stat_real = $stat_real . "\n" . raw_line($count, 0); + if ($bad_specifier ne "") { + my $stat_real = get_stat_real($linenr, $lc); + my $ext_type = "Invalid"; + my $use = ""; + if ($bad_specifier =~ /p[Ff]/) { + $ext_type = "Deprecated"; + $use = " - use %pS instead"; + $use =~ s/pS/ps/ if ($bad_specifier =~ /pf/); + } + + WARN("VSPRINTF_POINTER_EXTENSION", + "$ext_type vsprintf pointer extension '$bad_specifier'$use\n" . "$here\n$stat_real\n"); } - WARN("VSPRINTF_POINTER_EXTENSION", - "Invalid vsprintf pointer extension '$bad_extension'\n" . "$here\n$stat_real\n"); } } @@ -5869,10 +5971,7 @@ sub process { $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) { my $lc = $stat =~ tr@\n@@; $lc = $lc + $linenr; - my $stat_real = raw_line($linenr, 0); - for (my $count = $linenr + 1; $count <= $lc; $count++) { - $stat_real = $stat_real . "\n" . raw_line($count, 0); - } + my $stat_real = get_stat_real($linenr, $lc); WARN("NAKED_SSCANF", "unchecked sscanf return value\n" . "$here\n$stat_real\n"); } @@ -5883,10 +5982,7 @@ sub process { $line =~ /\bsscanf\b/) { my $lc = $stat =~ tr@\n@@; $lc = $lc + $linenr; - my $stat_real = raw_line($linenr, 0); - for (my $count = $linenr + 1; $count <= $lc; $count++) { - $stat_real = $stat_real . "\n" . raw_line($count, 0); - } + my $stat_real = get_stat_real($linenr, $lc); if ($stat_real =~ /\bsscanf\b\s*\(\s*$FuncArg\s*,\s*("[^"]+")/) { my $format = $6; my $count = $format =~ tr@%@%@; @@ -5940,7 +6036,7 @@ sub process { # check for function declarations that have arguments without identifier names if (defined $stat && - $stat =~ /^.\s*(?:extern\s+)?$Type\s*$Ident\s*\(\s*([^{]+)\s*\)\s*;/s && + $stat =~ /^.\s*(?:extern\s+)?$Type\s*(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*\(\s*([^{]+)\s*\)\s*;/s && $1 ne "void") { my $args = trim($1); while ($args =~ m/\s*($Type\s*(?:$Ident|\(\s*\*\s*$Ident?\s*\)\s*$balanced_parens)?)/g) { @@ -6016,12 +6112,9 @@ sub process { } if ($r1 !~ /^sizeof\b/ && $r2 =~ /^sizeof\s*\S/ && !($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) { - my $ctx = ''; - my $herectx = $here . "\n"; my $cnt = statement_rawlines($stat); - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } + my $herectx = get_stat_here($linenr, $cnt, $here); + if (WARN("ALLOC_WITH_MULTIPLY", "Prefer $newfunc over $oldfunc with multiply\n" . $herectx) && $cnt == 1 && @@ -6092,7 +6185,7 @@ sub process { next if ($fline =~ /^.[\s$;]*$/); $has_statement = 1; $count++; - $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|return\b|goto\b|continue\b)/); + $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|exit\s*\(\b|return\b|goto\b|continue\b)/); } if (!$has_break && $has_statement) { WARN("MISSING_BREAK", @@ -6104,12 +6197,9 @@ sub process { if ($^V && $^V ge 5.10.0 && defined $stat && $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { - my $ctx = ''; - my $herectx = $here . "\n"; my $cnt = statement_rawlines($stat); - for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n"; - } + my $herectx = get_stat_here($linenr, $cnt, $here); + WARN("DEFAULT_NO_BREAK", "switch default: should use break\n" . $herectx); } @@ -6225,28 +6315,6 @@ sub process { } } -# whine about ACCESS_ONCE - if ($^V && $^V ge 5.10.0 && - $line =~ /\bACCESS_ONCE\s*$balanced_parens\s*(=(?!=))?\s*($FuncArg)?/) { - my $par = $1; - my $eq = $2; - my $fun = $3; - $par =~ s/^\(\s*(.*)\s*\)$/$1/; - if (defined($eq)) { - if (WARN("PREFER_WRITE_ONCE", - "Prefer WRITE_ONCE(<FOO>, <BAR>) over ACCESS_ONCE(<FOO>) = <BAR>\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)\s*$eq\s*\Q$fun\E/WRITE_ONCE($par, $fun)/; - } - } else { - if (WARN("PREFER_READ_ONCE", - "Prefer READ_ONCE(<FOO>) over ACCESS_ONCE(<FOO>)\n" . $herecurr) && - $fix) { - $fixed[$fixlinenr] =~ s/\bACCESS_ONCE\s*\(\s*\Q$par\E\s*\)/READ_ONCE($par)/; - } - } - } - # check for mutex_trylock_recursive usage if ($line =~ /mutex_trylock_recursive/) { ERROR("LOCKING", @@ -6270,8 +6338,69 @@ sub process { "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); } +# check for DEVICE_ATTR uses that could be DEVICE_ATTR_<FOO> +# and whether or not function naming is typical and if +# DEVICE_ATTR permissions uses are unusual too + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /\bDEVICE_ATTR\s*\(\s*(\w+)\s*,\s*\(?\s*(\s*(?:${multi_mode_perms_string_search}|0[0-7]{3,3})\s*)\s*\)?\s*,\s*(\w+)\s*,\s*(\w+)\s*\)/) { + my $var = $1; + my $perms = $2; + my $show = $3; + my $store = $4; + my $octal_perms = perms_to_octal($perms); + if ($show =~ /^${var}_show$/ && + $store =~ /^${var}_store$/ && + $octal_perms eq "0644") { + if (WARN("DEVICE_ATTR_RW", + "Use DEVICE_ATTR_RW\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*$store\s*\)/DEVICE_ATTR_RW(${var})/; + } + } elsif ($show =~ /^${var}_show$/ && + $store =~ /^NULL$/ && + $octal_perms eq "0444") { + if (WARN("DEVICE_ATTR_RO", + "Use DEVICE_ATTR_RO\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*$show\s*,\s*NULL\s*\)/DEVICE_ATTR_RO(${var})/; + } + } elsif ($show =~ /^NULL$/ && + $store =~ /^${var}_store$/ && + $octal_perms eq "0200") { + if (WARN("DEVICE_ATTR_WO", + "Use DEVICE_ATTR_WO\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bDEVICE_ATTR\s*\(\s*$var\s*,\s*\Q$perms\E\s*,\s*NULL\s*,\s*$store\s*\)/DEVICE_ATTR_WO(${var})/; + } + } elsif ($octal_perms eq "0644" || + $octal_perms eq "0444" || + $octal_perms eq "0200") { + my $newshow = "$show"; + $newshow = "${var}_show" if ($show ne "NULL" && $show ne "${var}_show"); + my $newstore = $store; + $newstore = "${var}_store" if ($store ne "NULL" && $store ne "${var}_store"); + my $rename = ""; + if ($show ne $newshow) { + $rename .= " '$show' to '$newshow'"; + } + if ($store ne $newstore) { + $rename .= " '$store' to '$newstore'"; + } + WARN("DEVICE_ATTR_FUNCTIONS", + "Consider renaming function(s)$rename\n" . $herecurr); + } else { + WARN("DEVICE_ATTR_PERMS", + "DEVICE_ATTR unusual permissions '$perms' used\n" . $herecurr); + } + } + # Mode permission misuses where it seems decimal should be octal # This uses a shortcut match to avoid unnecessary uses of a slow foreach loop +# o Ignore module_param*(...) uses with a decimal 0 permission as that has a +# specific definition of not visible in sysfs. +# o Ignore proc_create*(...) uses with a decimal 0 permission as that means +# use the default permissions if ($^V && $^V ge 5.10.0 && defined $stat && $line =~ /$mode_perms_search/) { @@ -6281,10 +6410,7 @@ sub process { my $lc = $stat =~ tr@\n@@; $lc = $lc + $linenr; - my $stat_real = raw_line($linenr, 0); - for (my $count = $linenr + 1; $count <= $lc; $count++) { - $stat_real = $stat_real . "\n" . raw_line($count, 0); - } + my $stat_real = get_stat_real($linenr, $lc); my $skip_args = ""; if ($arg_pos > 1) { @@ -6295,8 +6421,9 @@ sub process { if ($stat =~ /$test/) { my $val = $1; $val = $6 if ($skip_args ne ""); - if (($val =~ /^$Int$/ && $val !~ /^$Octal$/) || - ($val =~ /^$Octal$/ && length($val) ne 4)) { + if (!($func =~ /^(?:module_param|proc_create)/ && $val eq "0") && + (($val =~ /^$Int$/ && $val !~ /^$Octal$/) || + ($val =~ /^$Octal$/ && length($val) ne 4))) { ERROR("NON_OCTAL_PERMISSIONS", "Use 4 digit octal (0777) not decimal permissions\n" . "$here\n" . $stat_real); } @@ -6309,30 +6436,13 @@ sub process { } # check for uses of S_<PERMS> that could be octal for readability - if ($line =~ /\b$mode_perms_string_search\b/) { - my $val = ""; - my $oval = ""; - my $to = 0; - my $curpos = 0; - my $lastpos = 0; - while ($line =~ /\b(($mode_perms_string_search)\b(?:\s*\|\s*)?\s*)/g) { - $curpos = pos($line); - my $match = $2; - my $omatch = $1; - last if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos)); - $lastpos = $curpos; - $to |= $mode_permission_string_types{$match}; - $val .= '\s*\|\s*' if ($val ne ""); - $val .= $match; - $oval .= $omatch; - } - $oval =~ s/^\s*\|\s*//; - $oval =~ s/\s*\|\s*$//; - my $octal = sprintf("%04o", $to); + while ($line =~ m{\b($multi_mode_perms_string_search)\b}g) { + my $oval = $1; + my $octal = perms_to_octal($oval); if (WARN("SYMBOLIC_PERMS", "Symbolic permissions '$oval' are not preferred. Consider using octal permissions '$octal'.\n" . $herecurr) && $fix) { - $fixed[$fixlinenr] =~ s/$val/$octal/; + $fixed[$fixlinenr] =~ s/\Q$oval\E/$octal/; } } @@ -6373,7 +6483,7 @@ sub process { exit(0); } - if (!$is_patch && $file !~ /cover-letter\.patch$/) { + if (!$is_patch && $filename !~ /cover-letter\.patch$/) { ERROR("NOT_UNIFIED_DIFF", "Does not appear to be a unified-diff format patch\n"); } diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 23a1dc9abd..9eba487ec4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -154,7 +154,6 @@ CONFIG_BOOTP_BOOTFILE CONFIG_BOOTP_BOOTFILESIZE CONFIG_BOOTP_DEFAULT CONFIG_BOOTP_DHCP_REQUEST_DELAY -CONFIG_BOOTP_DNS2 CONFIG_BOOTP_ID_CACHE_SIZE CONFIG_BOOTP_MAY_FAIL CONFIG_BOOTP_NISDOMAIN @@ -305,8 +304,6 @@ CONFIG_CPU_TYPE_R CONFIG_CPU_VR41XX CONFIG_CQSPI_REF_CLK CONFIG_CRC32 -CONFIG_CS8900 -CONFIG_CS8900_BASE CONFIG_CS8900_BUS16 CONFIG_CS8900_BUS32 CONFIG_CSF_SIZE @@ -409,7 +406,6 @@ CONFIG_DRIVER_NE2000_BASE CONFIG_DRIVER_NE2000_CCR CONFIG_DRIVER_NE2000_VAL CONFIG_DRIVER_SMC911X_BASE -CONFIG_DRIVER_TI_CPSW CONFIG_DRIVER_TI_EMAC CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE CONFIG_DRIVER_TI_EMAC_USE_RMII @@ -494,7 +490,6 @@ CONFIG_ENABLE_36BIT_PHYS CONFIG_ENABLE_MMU CONFIG_ENABLE_MUST_CHECK CONFIG_ENABLE_WARN_DEPRECATED -CONFIG_ENC_SILENTLINK CONFIG_ENV_ACCESS_IGNORE_FORCE CONFIG_ENV_ADDR CONFIG_ENV_ADDR_FLEX @@ -536,7 +531,6 @@ CONFIG_ENV_TOTAL_SIZE CONFIG_ENV_UBIFS_OPTION CONFIG_ENV_UBI_MTD CONFIG_ENV_UBI_VOLUME_REDUND -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG CONFIG_ENV_VERSION CONFIG_EP9302 CONFIG_EP9307 @@ -1738,7 +1732,6 @@ CONFIG_S5P CONFIG_S5PC100 CONFIG_S5PC110 CONFIG_S5P_PA_SYSRAM -CONFIG_S6E63D6 CONFIG_S6E8AX0 CONFIG_SABRELITE CONFIG_SAMA5D3_LCD_BASE @@ -1827,7 +1820,6 @@ CONFIG_SH_I2C_8BIT CONFIG_SH_I2C_CLOCK CONFIG_SH_I2C_DATA_HIGH CONFIG_SH_I2C_DATA_LOW -CONFIG_SH_MMCIF CONFIG_SH_MMCIF_ADDR CONFIG_SH_MMCIF_CLK CONFIG_SH_QSPI_BASE @@ -1961,7 +1953,6 @@ CONFIG_SPL_MAX_FOOTPRINT CONFIG_SPL_MAX_PEB_SIZE CONFIG_SPL_MAX_SIZE CONFIG_SPL_MMC_BOOT -CONFIG_SPL_MMC_LOAD CONFIG_SPL_MPC83XX_WAIT_FOR_NAND CONFIG_SPL_MXS_PSWITCH_WAIT CONFIG_SPL_NAND_BASE @@ -1990,7 +1981,6 @@ CONFIG_SPL_SKIP_RELOCATE CONFIG_SPL_SPAACT_ADDR CONFIG_SPL_SPI_BOOT CONFIG_SPL_SPI_FLASH_MINIMAL -CONFIG_SPL_SPI_LOAD CONFIG_SPL_STACK CONFIG_SPL_STACK_ADDR CONFIG_SPL_STACK_SIZE @@ -2038,7 +2028,6 @@ CONFIG_STANDALONE_LOAD_ADDR CONFIG_STATIC_BOARD_REV CONFIG_STD_DEVICES_SETTINGS CONFIG_STM32_FLASH -CONFIG_STM32_HZ CONFIG_STRIDER CONFIG_STRIDER_CON CONFIG_STRIDER_CON_DP @@ -3182,10 +3171,6 @@ CONFIG_SYS_I2C_MAC2_DATA_ADDR CONFIG_SYS_I2C_MAC_OFFSET CONFIG_SYS_I2C_MAX1237_ADDR CONFIG_SYS_I2C_MAX_HOPS -CONFIG_SYS_I2C_MXC_I2C1 -CONFIG_SYS_I2C_MXC_I2C2 -CONFIG_SYS_I2C_MXC_I2C3 -CONFIG_SYS_I2C_MXC_I2C4 CONFIG_SYS_I2C_NCT72_ADDR CONFIG_SYS_I2C_NOPROBES CONFIG_SYS_I2C_OFFSET @@ -3618,14 +3603,6 @@ CONFIG_SYS_MX6_CLK32 CONFIG_SYS_MX6_HCLK CONFIG_SYS_MX7_CLK32 CONFIG_SYS_MX7_HCLK -CONFIG_SYS_MXC_I2C1_SLAVE -CONFIG_SYS_MXC_I2C1_SPEED -CONFIG_SYS_MXC_I2C2_SLAVE -CONFIG_SYS_MXC_I2C2_SPEED -CONFIG_SYS_MXC_I2C3_SLAVE -CONFIG_SYS_MXC_I2C3_SPEED -CONFIG_SYS_MXC_I2C4_SLAVE -CONFIG_SYS_MXC_I2C4_SPEED CONFIG_SYS_MXS_VDD5V_ONLY CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST CONFIG_SYS_NAND_4_ADDR_CYCLE @@ -3642,8 +3619,6 @@ CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_BASE2 CONFIG_SYS_NAND_BASE_LIST CONFIG_SYS_NAND_BASE_PHYS -CONFIG_SYS_NAND_BCR -CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_BOOT CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_NAND_BUSWIDTH_16 @@ -3682,12 +3657,10 @@ CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES CONFIG_SYS_NAND_NO_SUBPAGE CONFIG_SYS_NAND_NO_SUBPAGE_WRITE CONFIG_SYS_NAND_ONFI_DETECTION -CONFIG_SYS_NAND_OOBSIZE CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_NAND_PAGE_2K CONFIG_SYS_NAND_PAGE_4K CONFIG_SYS_NAND_PAGE_COUNT -CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_QUIET CONFIG_SYS_NAND_READY_PIN CONFIG_SYS_NAND_REGS_BASE @@ -3702,7 +3675,6 @@ CONFIG_SYS_NAND_U_BOOT_RELOC_SP CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_WINDOW_SIZE -CONFIG_SYS_NDFC_EBC0_CFG CONFIG_SYS_NETA_INTERFACE_TYPE CONFIG_SYS_NONCACHED_MEMORY CONFIG_SYS_NOR0_CSPR @@ -4774,7 +4746,6 @@ CONFIG_VIDEO_LCD_I2C_BUS CONFIG_VIDEO_LOGO CONFIG_VIDEO_MB862xx CONFIG_VIDEO_MB862xx_ACCEL -CONFIG_VIDEO_MX3 CONFIG_VIDEO_MXS CONFIG_VIDEO_MXS_MODE_SYSTEM CONFIG_VIDEO_OMAP3 @@ -4792,7 +4763,6 @@ CONFIG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE CONFIG_VSC9953 CONFIG_VSC_CROSSBAR -CONFIG_WATCHDOG CONFIG_WATCHDOG_BASEADDR CONFIG_WATCHDOG_IRQ CONFIG_WATCHDOG_NOWAYOUT diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl index 07800e62d1..e3b41616c9 100755 --- a/scripts/get_maintainer.pl +++ b/scripts/get_maintainer.pl @@ -57,6 +57,7 @@ my $sections = 0; my $file_emails = 0; my $from_filename = 0; my $pattern_depth = 0; +my $self_test = undef; my $version = 0; my $help = 0; my $find_maintainer_files = 1; @@ -136,6 +137,7 @@ my %VCS_cmds_git = ( "subject_pattern" => "^GitSubject: (.*)", "stat_pattern" => "^(\\d+)\\t(\\d+)\\t\$file\$", "file_exists_cmd" => "git ls-files \$file", + "list_files_cmd" => "git ls-files \$file", ); my %VCS_cmds_hg = ( @@ -165,6 +167,7 @@ my %VCS_cmds_hg = ( "subject_pattern" => "^HgSubject: (.*)", "stat_pattern" => "^(\\d+)\t(\\d+)\t\$file\$", "file_exists_cmd" => "hg files \$file", + "list_files_cmd" => "hg manifest -R \$file", ); my $conf = which_conf(".get_maintainer.conf"); @@ -214,6 +217,14 @@ if (-f $ignore_file) { close($ignore); } +if ($#ARGV > 0) { + foreach (@ARGV) { + if ($_ =~ /^-{1,2}self-test(?:=|$)/) { + die "$P: using --self-test does not allow any other option or argument\n"; + } + } +} + if (!GetOptions( 'email!' => \$email, 'git!' => \$email_git, @@ -250,6 +261,7 @@ if (!GetOptions( 'fe|file-emails!' => \$file_emails, 'f|file' => \$from_filename, 'find-maintainer-files' => \$find_maintainer_files, + 'self-test:s' => \$self_test, 'v|version' => \$version, 'h|help|usage' => \$help, )) { @@ -266,6 +278,12 @@ if ($version != 0) { exit 0; } +if (defined $self_test) { + read_all_maintainer_files(); + self_test(); + exit 0; +} + if (-t STDIN && !@ARGV) { # We're talking to a terminal, but have no command line arguments. die "$P: missing patchfile or -f file - use --help if necessary\n"; @@ -309,14 +327,17 @@ if (!top_of_kernel_tree($lk_path)) { my @typevalue = (); my %keyword_hash; my @mfiles = (); +my @self_test_info = (); sub read_maintainer_file { my ($file) = @_; open (my $maint, '<', "$file") or die "$P: Can't open MAINTAINERS file '$file': $!\n"; + my $i = 1; while (<$maint>) { my $line = $_; + chomp $line; if ($line =~ m/^([A-Z]):\s*(.*)/) { my $type = $1; @@ -336,9 +357,12 @@ sub read_maintainer_file { } push(@typevalue, "$type:$value"); } elsif (!(/^\s*$/ || /^\s*\#/)) { - $line =~ s/\n$//g; push(@typevalue, $line); } + if (defined $self_test) { + push(@self_test_info, {file=>$file, linenr=>$i, line=>$line}); + } + $i++; } close($maint); } @@ -355,26 +379,30 @@ sub find_ignore_git { return grep { $_ !~ /^\.git$/; } @_; } -if (-d "${lk_path}MAINTAINERS") { - opendir(DIR, "${lk_path}MAINTAINERS") or die $!; - my @files = readdir(DIR); - closedir(DIR); - foreach my $file (@files) { - push(@mfiles, "${lk_path}MAINTAINERS/$file") if ($file !~ /^\./); +read_all_maintainer_files(); + +sub read_all_maintainer_files { + if (-d "${lk_path}MAINTAINERS") { + opendir(DIR, "${lk_path}MAINTAINERS") or die $!; + my @files = readdir(DIR); + closedir(DIR); + foreach my $file (@files) { + push(@mfiles, "${lk_path}MAINTAINERS/$file") if ($file !~ /^\./); + } } -} -if ($find_maintainer_files) { - find( { wanted => \&find_is_maintainer_file, - preprocess => \&find_ignore_git, - no_chdir => 1, - }, "${lk_path}"); -} else { - push(@mfiles, "${lk_path}MAINTAINERS") if -f "${lk_path}MAINTAINERS"; -} + if ($find_maintainer_files) { + find( { wanted => \&find_is_maintainer_file, + preprocess => \&find_ignore_git, + no_chdir => 1, + }, "${lk_path}"); + } else { + push(@mfiles, "${lk_path}MAINTAINERS") if -f "${lk_path}MAINTAINERS"; + } -foreach my $file (@mfiles) { - read_maintainer_file("$file"); + foreach my $file (@mfiles) { + read_maintainer_file("$file"); + } } # @@ -584,6 +612,135 @@ if ($web) { exit($exit); +sub self_test { + my @lsfiles = (); + my @good_links = (); + my @bad_links = (); + my @section_headers = (); + my $index = 0; + + @lsfiles = vcs_list_files($lk_path); + + for my $x (@self_test_info) { + $index++; + + ## Section header duplication and missing section content + if (($self_test eq "" || $self_test =~ /\bsections\b/) && + $x->{line} =~ /^\S[^:]/ && + defined $self_test_info[$index] && + $self_test_info[$index]->{line} =~ /^([A-Z]):\s*\S/) { + my $has_S = 0; + my $has_F = 0; + my $has_ML = 0; + my $status = ""; + if (grep(m@^\Q$x->{line}\E@, @section_headers)) { + print("$x->{file}:$x->{linenr}: warning: duplicate section header\t$x->{line}\n"); + } else { + push(@section_headers, $x->{line}); + } + my $nextline = $index; + while (defined $self_test_info[$nextline] && + $self_test_info[$nextline]->{line} =~ /^([A-Z]):\s*(\S.*)/) { + my $type = $1; + my $value = $2; + if ($type eq "S") { + $has_S = 1; + $status = $value; + } elsif ($type eq "F" || $type eq "N") { + $has_F = 1; + } elsif ($type eq "M" || $type eq "R" || $type eq "L") { + $has_ML = 1; + } + $nextline++; + } + if (!$has_ML && $status !~ /orphan|obsolete/i) { + print("$x->{file}:$x->{linenr}: warning: section without email address\t$x->{line}\n"); + } + if (!$has_S) { + print("$x->{file}:$x->{linenr}: warning: section without status \t$x->{line}\n"); + } + if (!$has_F) { + print("$x->{file}:$x->{linenr}: warning: section without file pattern\t$x->{line}\n"); + } + } + + next if ($x->{line} !~ /^([A-Z]):\s*(.*)/); + + my $type = $1; + my $value = $2; + + ## Filename pattern matching + if (($type eq "F" || $type eq "X") && + ($self_test eq "" || $self_test =~ /\bpatterns\b/)) { + $value =~ s@\.@\\\.@g; ##Convert . to \. + $value =~ s/\*/\.\*/g; ##Convert * to .* + $value =~ s/\?/\./g; ##Convert ? to . + ##if pattern is a directory and it lacks a trailing slash, add one + if ((-d $value)) { + $value =~ s@([^/])$@$1/@; + } + if (!grep(m@^$value@, @lsfiles)) { + print("$x->{file}:$x->{linenr}: warning: no file matches\t$x->{line}\n"); + } + + ## Link reachability + } elsif (($type eq "W" || $type eq "Q" || $type eq "B") && + $value =~ /^https?:/ && + ($self_test eq "" || $self_test =~ /\blinks\b/)) { + next if (grep(m@^\Q$value\E$@, @good_links)); + my $isbad = 0; + if (grep(m@^\Q$value\E$@, @bad_links)) { + $isbad = 1; + } else { + my $output = `wget --spider -q --no-check-certificate --timeout 10 --tries 1 $value`; + if ($? == 0) { + push(@good_links, $value); + } else { + push(@bad_links, $value); + $isbad = 1; + } + } + if ($isbad) { + print("$x->{file}:$x->{linenr}: warning: possible bad link\t$x->{line}\n"); + } + + ## SCM reachability + } elsif ($type eq "T" && + ($self_test eq "" || $self_test =~ /\bscm\b/)) { + next if (grep(m@^\Q$value\E$@, @good_links)); + my $isbad = 0; + if (grep(m@^\Q$value\E$@, @bad_links)) { + $isbad = 1; + } elsif ($value !~ /^(?:git|quilt|hg)\s+\S/) { + print("$x->{file}:$x->{linenr}: warning: malformed entry\t$x->{line}\n"); + } elsif ($value =~ /^git\s+(\S+)(\s+([^\(]+\S+))?/) { + my $url = $1; + my $branch = ""; + $branch = $3 if $3; + my $output = `git ls-remote --exit-code -h "$url" $branch > /dev/null 2>&1`; + if ($? == 0) { + push(@good_links, $value); + } else { + push(@bad_links, $value); + $isbad = 1; + } + } elsif ($value =~ /^(?:quilt|hg)\s+(https?:\S+)/) { + my $url = $1; + my $output = `wget --spider -q --no-check-certificate --timeout 10 --tries 1 $url`; + if ($? == 0) { + push(@good_links, $value); + } else { + push(@bad_links, $value); + $isbad = 1; + } + } + if ($isbad) { + print("$x->{file}:$x->{linenr}: warning: possible bad link\t$x->{line}\n"); + } + } + } +} + sub ignore_email_address { my ($address) = @_; @@ -861,6 +1018,7 @@ Other options: --sections => print all of the subsystem sections with pattern matches --letters => print all matching 'letter' types from all matching sections --mailmap => use .mailmap file (default: $email_use_mailmap) + --self-test => show potential issues with MAINTAINERS file content --version => show version --help => show this help information @@ -2192,6 +2350,23 @@ sub vcs_file_exists { return $exists; } +sub vcs_list_files { + my ($file) = @_; + + my @lsfiles = (); + + my $vcs_used = vcs_exists(); + return 0 if (!$vcs_used); + + my $cmd = $VCS_cmds{"list_files_cmd"}; + $cmd =~ s/(\$\w+)/$1/eeg; # interpolate $cmd + @lsfiles = &{$VCS_cmds{"execute_cmd"}}($cmd); + + return () if ($? != 0); + + return @lsfiles; +} + sub uniq { my (@parms) = @_; diff --git a/test/dm/clk.c b/test/dm/clk.c index 712a1e674a..d3649103ee 100644 --- a/test/dm/clk.c +++ b/test/dm/clk.c @@ -101,3 +101,40 @@ static int dm_test_clk(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_clk, DM_TESTF_SCAN_FDT); + +static int dm_test_clk_bulk(struct unit_test_state *uts) +{ + struct udevice *dev_clk, *dev_test; + + ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox", + &dev_clk)); + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", + &dev_test)); + ut_assertok(sandbox_clk_test_get_bulk(dev_test)); + + ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI)); + ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C)); + + /* Fixed clock does not support enable, thus should not fail */ + ut_assertok(sandbox_clk_test_enable_bulk(dev_test)); + ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI)); + ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C)); + + /* Fixed clock does not support disable, thus should not fail */ + ut_assertok(sandbox_clk_test_disable_bulk(dev_test)); + ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI)); + ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C)); + + /* Fixed clock does not support enable, thus should not fail */ + ut_assertok(sandbox_clk_test_enable_bulk(dev_test)); + ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI)); + ut_asserteq(1, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C)); + + /* Fixed clock does not support disable, thus should not fail */ + ut_assertok(sandbox_clk_test_release_bulk(dev_test)); + ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI)); + ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_I2C)); + + return 0; +} +DM_TEST(dm_test_clk_bulk, DM_TESTF_SCAN_FDT); diff --git a/test/dm/reset.c b/test/dm/reset.c index 0ae8031540..8dc0023c08 100644 --- a/test/dm/reset.c +++ b/test/dm/reset.c @@ -13,6 +13,9 @@ /* This must match the specifier for mbox-names="test" in the DT node */ #define TEST_RESET_ID 2 +/* This is the other reset phandle specifier handled by bulk */ +#define OTHER_RESET_ID 2 + static int dm_test_reset(struct unit_test_state *uts) { struct udevice *dev_reset; @@ -37,3 +40,33 @@ static int dm_test_reset(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT); + +static int dm_test_reset_bulk(struct unit_test_state *uts) +{ + struct udevice *dev_reset; + struct udevice *dev_test; + + ut_assertok(uclass_get_device_by_name(UCLASS_RESET, "reset-ctl", + &dev_reset)); + ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID)); + + ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test", + &dev_test)); + ut_assertok(sandbox_reset_test_get_bulk(dev_test)); + + ut_assertok(sandbox_reset_test_assert_bulk(dev_test)); + ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID)); + + ut_assertok(sandbox_reset_test_deassert_bulk(dev_test)); + ut_asserteq(0, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + ut_asserteq(0, sandbox_reset_query(dev_reset, OTHER_RESET_ID)); + + ut_assertok(sandbox_reset_test_release_bulk(dev_test)); + ut_asserteq(1, sandbox_reset_query(dev_reset, TEST_RESET_ID)); + ut_asserteq(1, sandbox_reset_query(dev_reset, OTHER_RESET_ID)); + + return 0; +} +DM_TEST(dm_test_reset_bulk, DM_TESTF_SCAN_FDT); diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py index 66b799bed6..b1ef6bd581 100644 --- a/test/py/tests/test_efi_selftest.py +++ b/test/py/tests/test_efi_selftest.py @@ -25,6 +25,20 @@ def test_efi_selftest(u_boot_console): u_boot_console.restart_uboot(); @pytest.mark.buildconfigspec('cmd_bootefi_selftest') +@pytest.mark.buildconfigspec('of_control') +def test_efi_selftest_device_tree(u_boot_console): + u_boot_console.run_command(cmd='setenv efi_selftest list') + output = u_boot_console.run_command('bootefi selftest') + assert '\'device tree\'' in output + u_boot_console.run_command(cmd='setenv efi_selftest device tree') + u_boot_console.run_command(cmd='setenv -f serial# Testing DT') + u_boot_console.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False) + m = u_boot_console.p.expect(['serial-number: Testing DT', 'U-Boot']) + if m != 0: + raise Exception('Reset failed in \'device tree\' test') + u_boot_console.restart_uboot(); + +@pytest.mark.buildconfigspec('cmd_bootefi_selftest') def test_efi_selftest_watchdog_reboot(u_boot_console): u_boot_console.run_command(cmd='setenv efi_selftest list') output = u_boot_console.run_command('bootefi selftest') diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index d93a915fd1..fb4afa5ee9 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -239,7 +239,7 @@ int main(int argc, char *argv[]) argv += optind; if (env_opts.lockname) { - lockname = malloc(sizeof(env_opts.lockname) + + lockname = malloc(strlen(env_opts.lockname) + sizeof(CMD_PRINTENV) + 10); if (!lockname) { fprintf(stderr, "Unable allocate memory"); diff --git a/tools/imximage.c b/tools/imximage.c index ed9d935903..6dabb13520 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -516,7 +516,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr) offs = (char *)&hdr_v2->data.dcd_table - (char *)hdr_v2; - printf("HAB Blocks: %08x %08x %08x\n", + printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n", (uint32_t)fhdr_v2->self, 0, hdr_v2->boot_data.size - imximage_ivt_offset - imximage_csf_size); diff --git a/tools/mkimage.c b/tools/mkimage.c index 28ff35e670..4e561820e7 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -588,9 +588,8 @@ int main(int argc, char **argv) if (tparams->print_header) tparams->print_header (ptr); else { - fprintf (stderr, "%s: Can't print header for %s: %s\n", - params.cmdname, tparams->name, strerror(errno)); - exit (EXIT_FAILURE); + fprintf (stderr, "%s: Can't print header for %s\n", + params.cmdname, tparams->name); } (void) munmap((void *)ptr, sbuf.st_size); |