diff options
124 files changed, 2857 insertions, 686 deletions
diff --git a/.checkpatch.conf b/.checkpatch.conf index d1d32fac9d..95f19635d3 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -25,3 +25,6 @@ # Ignore "WARNING: Prefer ether_addr_copy() over memcpy() if the Ethernet # addresses are __aligned(2)". --ignore PREFER_ETHER_ADDR_COPY + +# A bit shorter of a description is OK with us. +--min-conf-desc-length=2 diff --git a/.travis.yml b/.travis.yml index 5e251314db..2a98c4bb11 100644 --- a/.travis.yml +++ b/.travis.yml @@ -46,6 +46,8 @@ install: - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - mkdir ~/grub2-arm - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di ) + - mkdir ~/grub2-arm64 + - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di ) env: global: @@ -114,6 +116,7 @@ script: - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD}; cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/; cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi; + cp ~/grub2-arm64/usr/lib/grub2/arm64-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi; if [[ "${TEST_PY_BD}" != "" ]]; then ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID} -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}" @@ -336,6 +339,11 @@ matrix: QEMU_TARGET="arm-softmmu" BUILDMAN="^qemu_arm$" - env: + - TEST_PY_BD="qemu_arm64" + TEST_PY_TEST_SPEC="not sleep" + QEMU_TARGET="aarch64-softmmu" + BUILDMAN="^qemu_arm64$" + - env: - TEST_PY_BD="qemu_mips" TEST_PY_TEST_SPEC="not sleep" QEMU_TARGET="mips-softmmu" diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts index a7b276c01e..67dfb93ca8 100644 --- a/arch/arc/dts/hsdk.dts +++ b/arch/arc/dts/hsdk.dts @@ -24,6 +24,12 @@ }; }; + cgu_clk: cgu-clk@f0000000 { + compatible = "snps,hsdk-cgu-clock"; + reg = <0xf0000000 0x10>, <0xf00014B8 0x4>; + #clock-cells = <1>; + }; + uart0: serial0@f0005000 { compatible = "snps,dw-apb-uart"; reg = <0xf0005000 0x1000>; diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index ba1f7bac77..67f416305d 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -63,8 +63,15 @@ #define ARC_AUX_SLC_INVALIDATE 0x905 #define ARC_AUX_SLC_IVDL 0x910 #define ARC_AUX_SLC_FLDL 0x912 +#define ARC_AUX_SLC_RGN_START 0x914 +#define ARC_AUX_SLC_RGN_START1 0x915 +#define ARC_AUX_SLC_RGN_END 0x916 +#define ARC_AUX_SLC_RGN_END1 0x917 #define ARC_BCR_CLUSTER 0xcf +/* MMU Management regs */ +#define ARC_AUX_MMU_BCR 0x06f + /* IO coherency related auxiliary registers */ #define ARC_AUX_IO_COH_ENABLE 0x500 #define ARC_AUX_IO_COH_PARTIAL 0x501 diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 1073e1570f..04f1d9d59b 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -13,19 +13,24 @@ #include <asm/cache.h> /* Bit values in IC_CTRL */ -#define IC_CTRL_CACHE_DISABLE (1 << 0) +#define IC_CTRL_CACHE_DISABLE BIT(0) /* Bit values in DC_CTRL */ -#define DC_CTRL_CACHE_DISABLE (1 << 0) -#define DC_CTRL_INV_MODE_FLUSH (1 << 6) -#define DC_CTRL_FLUSH_STATUS (1 << 8) +#define DC_CTRL_CACHE_DISABLE BIT(0) +#define DC_CTRL_INV_MODE_FLUSH BIT(6) +#define DC_CTRL_FLUSH_STATUS BIT(8) #define CACHE_VER_NUM_MASK 0xF -#define SLC_CTRL_SB (1 << 2) #define OP_INV 0x1 #define OP_FLUSH 0x2 #define OP_INV_IC 0x3 +/* Bit val in SLC_CONTROL */ +#define SLC_CTRL_DIS 0x001 +#define SLC_CTRL_IM 0x040 +#define SLC_CTRL_BUSY 0x100 +#define SLC_CTRL_RGN_OP_INV 0x200 + /* * By default that variable will fall into .bss section. * But .bss section is not relocated and so it will be initilized before @@ -41,88 +46,118 @@ bool icache_exists __section(".data") = false; int slc_line_sz __section(".data"); bool slc_exists __section(".data") = false; bool ioc_exists __section(".data") = false; +bool pae_exists __section(".data") = false; + +/* To force enable IOC set ioc_enable to 'true' */ +bool ioc_enable __section(".data") = false; -static unsigned int __before_slc_op(const int op) +void read_decode_mmu_bcr(void) { - unsigned int reg = reg; + /* TODO: should we compare mmu version from BCR and from CONFIG? */ +#if (CONFIG_ARC_MMU_VER >= 4) + u32 tmp; - if (op == OP_INV) { - /* - * IM is set by default and implies Flush-n-inv - * Clear it here for vanilla inv - */ - reg = read_aux_reg(ARC_AUX_SLC_CTRL); - write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH); - } + tmp = read_aux_reg(ARC_AUX_MMU_BCR); - return reg; -} + struct bcr_mmu_4 { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1, + n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3; +#else + /* DTLB ITLB JES JE JA */ + unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2, + pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8; +#endif /* CONFIG_CPU_BIG_ENDIAN */ + } *mmu4; -static void __after_slc_op(const int op, unsigned int reg) -{ - if (op & OP_FLUSH) { /* flush / flush-n-inv both wait */ - /* - * Make sure "busy" bit reports correct status, - * see STAR 9001165532 - */ - read_aux_reg(ARC_AUX_SLC_CTRL); - while (read_aux_reg(ARC_AUX_SLC_CTRL) & - DC_CTRL_FLUSH_STATUS) - ; - } + mmu4 = (struct bcr_mmu_4 *)&tmp; - /* Switch back to default Invalidate mode */ - if (op == OP_INV) - write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH); + pae_exists = !!mmu4->pae; +#endif /* (CONFIG_ARC_MMU_VER >= 4) */ } -static inline void __slc_line_loop(unsigned long paddr, unsigned long sz, - const int op) +static void __slc_entire_op(const int op) { - unsigned int aux_cmd; - int num_lines; + unsigned int ctrl; -#define SLC_LINE_MASK (~(slc_line_sz - 1)) + ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); - aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL; + if (!(op & OP_FLUSH)) /* i.e. OP_INV */ + ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ + else + ctrl |= SLC_CTRL_IM; - sz += paddr & ~SLC_LINE_MASK; - paddr &= SLC_LINE_MASK; + write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); - num_lines = DIV_ROUND_UP(sz, slc_line_sz); + if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ + write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1); + else + write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1); - while (num_lines-- > 0) { - write_aux_reg(aux_cmd, paddr); - paddr += slc_line_sz; - } + /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ + read_aux_reg(ARC_AUX_SLC_CTRL); + + /* Important to wait for flush to complete */ + while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); } -static inline void __slc_entire_op(const int cacheop) +static void slc_upper_region_init(void) { - int aux; - unsigned int ctrl_reg = __before_slc_op(cacheop); + /* + * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0 + * as we don't use PAE40. + */ + write_aux_reg(ARC_AUX_SLC_RGN_END1, 0); + write_aux_reg(ARC_AUX_SLC_RGN_START1, 0); +} - if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */ - aux = ARC_AUX_SLC_INVALIDATE; +static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) +{ + unsigned int ctrl; + unsigned long end; + + /* + * The Region Flush operation is specified by CTRL.RGN_OP[11..9] + * - b'000 (default) is Flush, + * - b'001 is Invalidate if CTRL.IM == 0 + * - b'001 is Flush-n-Invalidate if CTRL.IM == 1 + */ + ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); + + /* Don't rely on default value of IM bit */ + if (!(op & OP_FLUSH)) /* i.e. OP_INV */ + ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */ else - aux = ARC_AUX_SLC_FLUSH; + ctrl |= SLC_CTRL_IM; - write_aux_reg(aux, 0x1); + if (op & OP_INV) + ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */ + else + ctrl &= ~SLC_CTRL_RGN_OP_INV; - __after_slc_op(cacheop, ctrl_reg); -} + write_aux_reg(ARC_AUX_SLC_CTRL, ctrl); -static inline void __slc_line_op(unsigned long paddr, unsigned long sz, - const int cacheop) -{ - unsigned int ctrl_reg = __before_slc_op(cacheop); - __slc_line_loop(paddr, sz, cacheop); - __after_slc_op(cacheop, ctrl_reg); + /* + * Lower bits are ignored, no need to clip + * END needs to be setup before START (latter triggers the operation) + * END can't be same as START, so add (l2_line_sz - 1) to sz + */ + end = paddr + sz + slc_line_sz - 1; + + /* + * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) + * are always == 0 as we don't use PAE40, so we only setup lower ones + * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START) + */ + write_aux_reg(ARC_AUX_SLC_RGN_END, end); + write_aux_reg(ARC_AUX_SLC_RGN_START, paddr); + + /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */ + read_aux_reg(ARC_AUX_SLC_CTRL); + + while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); } -#else -#define __slc_entire_op(cacheop) -#define __slc_line_op(paddr, sz, cacheop) -#endif +#endif /* CONFIG_ISA_ARCV2 */ #ifdef CONFIG_ISA_ARCV2 static void read_decode_cache_bcr_arcv2(void) @@ -168,7 +203,7 @@ static void read_decode_cache_bcr_arcv2(void) } cbcr; cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); - if (cbcr.fields.c) + if (cbcr.fields.c && ioc_enable) ioc_exists = true; } #endif @@ -197,7 +232,7 @@ void read_decode_cache_bcr(void) } dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); - if (dbcr.fields.ver){ + if (dbcr.fields.ver) { dcache_exists = true; l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) @@ -232,8 +267,7 @@ void cache_init(void) * so setting 0x11 implies 512M, 0x12 implies 1G... */ write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, - order_base_2(ap_size/1024) - 2); - + order_base_2(ap_size / 1024) - 2); /* IOC Aperture start must be aligned to the size of the aperture */ if (ap_base % ap_size != 0) @@ -242,9 +276,18 @@ void cache_init(void) write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); - } -#endif + + read_decode_mmu_bcr(); + + /* + * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist + * only if PAE exists in current HW. So we had to check pae_exist + * before using them. + */ + if (slc_exists && pae_exists) + slc_upper_region_init(); +#endif /* CONFIG_ISA_ARCV2 */ } int icache_status(void) @@ -272,7 +315,6 @@ void icache_disable(void) IC_CTRL_CACHE_DISABLE); } -#ifndef CONFIG_SYS_DCACHE_OFF void invalidate_icache_all(void) { /* Any write to IC_IVIC register triggers invalidation of entire I$ */ @@ -287,12 +329,12 @@ void invalidate_icache_all(void) __builtin_arc_nop(); read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ } -} -#else -void invalidate_icache_all(void) -{ -} + +#ifdef CONFIG_ISA_ARCV2 + if (slc_exists) + __slc_entire_op(OP_INV); #endif +} int dcache_status(void) { @@ -382,8 +424,7 @@ static unsigned int __before_dc_op(const int op) static void __after_dc_op(const int op, unsigned int reg) { if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ - while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) - ; + while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); /* Switch back to default Invalidate mode */ if (op == OP_INV) @@ -409,6 +450,7 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long sz, const int cacheop) { unsigned int ctrl_reg = __before_dc_op(cacheop); + __cache_line_loop(paddr, sz, cacheop); __after_dc_op(cacheop, ctrl_reg); } @@ -419,6 +461,9 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long sz, void invalidate_dcache_range(unsigned long start, unsigned long end) { + if (start >= end) + return; + #ifdef CONFIG_ISA_ARCV2 if (!ioc_exists) #endif @@ -426,12 +471,15 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) #ifdef CONFIG_ISA_ARCV2 if (slc_exists && !ioc_exists) - __slc_line_op(start, end - start, OP_INV); + __slc_rgn_op(start, end - start, OP_INV); #endif } void flush_dcache_range(unsigned long start, unsigned long end) { + if (start >= end) + return; + #ifdef CONFIG_ISA_ARCV2 if (!ioc_exists) #endif @@ -439,7 +487,7 @@ void flush_dcache_range(unsigned long start, unsigned long end) #ifdef CONFIG_ISA_ARCV2 if (slc_exists && !ioc_exists) - __slc_line_op(start, end - start, OP_FLUSH); + __slc_rgn_op(start, end - start, OP_FLUSH); #endif } diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 95d64f9d43..0d72fe71d4 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -44,6 +44,14 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_IC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_IC_IVIC] + ; As per ARC HS databook (see chapter 5.3.3.2) + ; it is required to add 3 NOPs after each write to IC_IVIC. + nop + nop + nop + 1: ; Disable/enable D-cache according to configuration lr r5, [ARC_BCR_DC_BUILD] @@ -57,6 +65,10 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_DC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_DC_IVDC] + + 1: #ifdef CONFIG_ISA_ARCV2 ; Disable System-Level Cache (SLC) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9dc542625e..f6d57f5505 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -675,8 +675,6 @@ config ARCH_MX5 config ARCH_QEMU bool "QEMU Virtual Platform" - select CPU_V7 - select ARCH_SUPPORT_PSCI select DM select DM_SERIAL select OF_CONTROL diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 26b2a528e6..9540ba4313 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -187,6 +187,7 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am57xx-beagle-x15-revc.dtb \ + am574x-idk.dtb \ am572x-idk.dtb \ am571x-idk.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb @@ -445,6 +446,11 @@ dtb-$(CONFIG_TARGET_OMAP3_EVM) += \ omap3-evm-37xx.dtb \ omap3-evm.dtb +dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \ + omap3-beagle-xm-ab.dtb \ + omap3-beagle-xm.dtb \ + omap3-beagle.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ at91-sama5d2_ptc_ek.dtb diff --git a/arch/arm/dts/am572x-idk-common.dtsi b/arch/arm/dts/am572x-idk-common.dtsi new file mode 100644 index 0000000000..c6d858b310 --- /dev/null +++ b/arch/arm/dts/am572x-idk-common.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "am57xx-idk-common.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + status-leds { + compatible = "gpio-leds"; + cpu0-led { + label = "status0:red:cpu0"; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + usr0-led { + label = "status0:green:usr"; + gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat-led { + label = "status0:blue:heartbeat"; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + cpu1-led { + label = "status1:red:cpu1"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu1"; + }; + + usr1-led { + label = "status1:green:usr"; + gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + mmc0-led { + label = "status1:blue:mmc0"; + gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&extcon_usb2 { + id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; +}; + +&sn65hvs882 { + load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +&pcie1_rc { + status = "okay"; + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts index a578fe97ba..9212931f25 100644 --- a/arch/arm/dts/am572x-idk.dts +++ b/arch/arm/dts/am572x-idk.dts @@ -9,8 +9,7 @@ /dts-v1/; #include "dra74x.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> +#include "am572x-idk-common.dtsi" #include "am57xx-idk-common.dtsi" #include "dra74x-mmc-iodelay.dtsi" @@ -18,54 +17,6 @@ model = "TI AM5728 IDK"; compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - status-leds { - compatible = "gpio-leds"; - cpu0-led { - label = "status0:red:cpu0"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - usr0-led { - label = "status0:green:usr"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - heartbeat-led { - label = "status0:blue:heartbeat"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - cpu1-led { - label = "status1:red:cpu1"; - gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu1"; - }; - - usr1-led { - label = "status1:green:usr"; - gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - mmc0-led { - label = "status1:blue:mmc0"; - gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - }; }; &mmc1 { @@ -85,45 +36,3 @@ pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&extcon_usb2 { - id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; -}; - -&sn65hvs882 { - load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; -}; - -&pcie1_rc { - status = "okay"; - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&pcie1_ep { - gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; diff --git a/arch/arm/dts/am574x-idk.dts b/arch/arm/dts/am574x-idk.dts new file mode 100644 index 0000000000..41e12a382d --- /dev/null +++ b/arch/arm/dts/am574x-idk.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + */ + + +/dts-v1/; + +#include "dra76x.dtsi" +#include "am572x-idk-common.dtsi" + +/ { + model = "TI AM5748 IDK"; + compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7"; +}; + +&qspi { + spi-max-frequency = <96000000>; + m25p80@0 { + spi-max-frequency = <96000000>; + }; +}; diff --git a/arch/arm/dts/am57xx-commercial-grade.dtsi b/arch/arm/dts/am57xx-commercial-grade.dtsi index c183654464..3eed6e09c8 100644 --- a/arch/arm/dts/am57xx-commercial-grade.dtsi +++ b/arch/arm/dts/am57xx-commercial-grade.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 &cpu_alert0 { temperature = <80000>; /* milliCelsius */ }; diff --git a/arch/arm/dts/am57xx-industrial-grade.dtsi b/arch/arm/dts/am57xx-industrial-grade.dtsi index 70c8c4ba19..422f953fc8 100644 --- a/arch/arm/dts/am57xx-industrial-grade.dtsi +++ b/arch/arm/dts/am57xx-industrial-grade.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 &cpu_alert0 { temperature = <90000>; /* milliCelsius */ }; diff --git a/arch/arm/dts/omap3-beagle-u-boot.dtsi b/arch/arm/dts/omap3-beagle-u-boot.dtsi new file mode 100644 index 0000000000..5325f0ffa4 --- /dev/null +++ b/arch/arm/dts/omap3-beagle-u-boot.dtsi @@ -0,0 +1,29 @@ +/* + * U-Boot additions + * + * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + chosen { + stdout-path = &uart3; + }; +}; + +&mmc1 { + cd-inverted; +}; + +&uart1 { + reg-shift = <2>; +}; + +&uart2 { + reg-shift = <2>; +}; + +&uart3 { + reg-shift = <2>; +}; diff --git a/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi b/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi new file mode 100644 index 0000000000..5325f0ffa4 --- /dev/null +++ b/arch/arm/dts/omap3-beagle-xm-ab-u-boot.dtsi @@ -0,0 +1,29 @@ +/* + * U-Boot additions + * + * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + chosen { + stdout-path = &uart3; + }; +}; + +&mmc1 { + cd-inverted; +}; + +&uart1 { + reg-shift = <2>; +}; + +&uart2 { + reg-shift = <2>; +}; + +&uart3 { + reg-shift = <2>; +}; diff --git a/arch/arm/dts/omap3-beagle-xm-ab.dts b/arch/arm/dts/omap3-beagle-xm-ab.dts new file mode 100644 index 0000000000..7ac3bcf59d --- /dev/null +++ b/arch/arm/dts/omap3-beagle-xm-ab.dts @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-beagle-xm.dts" + +/ { + /* HS USB Port 2 Power enable was inverted with the xM C */ + hsusb2_power: hsusb2_power_reg { + enable-active-high; + }; +}; diff --git a/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi b/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi new file mode 100644 index 0000000000..5325f0ffa4 --- /dev/null +++ b/arch/arm/dts/omap3-beagle-xm-u-boot.dtsi @@ -0,0 +1,29 @@ +/* + * U-Boot additions + * + * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + chosen { + stdout-path = &uart3; + }; +}; + +&mmc1 { + cd-inverted; +}; + +&uart1 { + reg-shift = <2>; +}; + +&uart2 { + reg-shift = <2>; +}; + +&uart3 { + reg-shift = <2>; +}; diff --git a/arch/arm/dts/omap3-beagle-xm.dts b/arch/arm/dts/omap3-beagle-xm.dts new file mode 100644 index 0000000000..0349fcc9dc --- /dev/null +++ b/arch/arm/dts/omap3-beagle-xm.dts @@ -0,0 +1,409 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap36xx.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard xM"; + compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + aliases { + display0 = &dvi0; + display1 = &tv0; + ethernet = ðernet; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pmu_stat { + label = "beagleboard::pmu_stat"; + pwms = <&twl_pwmled 1 7812500>; + max-brightness = <127>; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + linux,code = <0x114>; + wakeup-source; + }; + + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>; + + /* XXX pinctrl from twl */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + etb@5401b000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x5401b000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&etm_out>; + }; + }; + }; + + etm@54010000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x54010000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; +}; + +&omap3_pmx_wkup { + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ + >; + }; + + dss_dpi_pins2: pinmux_dss_dpi_pins1 { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + >; + }; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + dss_dpi_pins1: pinmux_dss_dpi_pins2 { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + + twl_power: power { + compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off"; + ti,use_poweroff; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + hub@2 { + compatible = "usb424,9514"; + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; +}; + +&vaux2 { + regulator-name = "usb_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mcbsp2 { + status = "okay"; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins1 + &dss_dpi_pins2 + >; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; diff --git a/arch/arm/dts/omap3-beagle.dts b/arch/arm/dts/omap3-beagle.dts new file mode 100644 index 0000000000..3ca8991a6c --- /dev/null +++ b/arch/arm/dts/omap3-beagle.dts @@ -0,0 +1,436 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap34xx.dtsi" + +/ { + model = "TI OMAP3 BeagleBoard"; + compatible = "ti,omap3-beagle", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + aliases { + display0 = &dvi0; + display1 = &tv0; + }; + + leds { + compatible = "gpio-leds"; + pmu_stat { + label = "beagleboard::pmu_stat"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ + }; + + heartbeat { + label = "beagleboard::usr0"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ + linux,default-trigger = "heartbeat"; + }; + + mmc { + label = "beagleboard::usr1"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ + linux,default-trigger = "mmc0"; + }; + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_HIGH>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */ + vcc-supply = <&hsusb2_power>; + #phy-cells = <0>; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + ti,mcbsp = <&mcbsp2>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user { + label = "user"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + linux,code = <0x114>; + wakeup-source; + }; + + }; + + tfp410: encoder0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ + + pinctrl-names = "default"; + pinctrl-0 = <&tfp410_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + tv0: connector1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; + + etb@540000000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x5401b000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&etm_out>; + }; + }; + }; + + etm@54010000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x54010000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; +}; + +&omap3_pmx_wkup { + gpio1_pins: pinmux_gpio1_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a14, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ + >; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + tfp410_pins: pinmux_tfp410_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c3 { + clock-frequency = <100000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc1>; + vqmmc-supply = <&vsim>; + bus-width = <8>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio1_pins>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&vaux2 { + regulator-name = "vdd_ehci"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mcbsp2 { + status = "okay"; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + +&venc { + status = "ok"; + + vdda-supply = <&vdac>; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; + +&gpmc { + status = "ok"; + ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ + + /* Chip select 0 */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* NAND I/O window, 4 bytes */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-ecc-opt = "ham1"; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <16>; + #address-cells = <1>; + #size-cells = <1>; + + gpmc,device-width = <2>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + partition@1c0000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x680000 0xf980000>; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 724e252946..5a2ea8faef 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -21,8 +21,8 @@ /* * OMAP HSMMC register definitions */ -#define OMAP_HSMMC1_BASE 0x48060100 -#define OMAP_HSMMC2_BASE 0x481D8100 +#define OMAP_HSMMC1_BASE 0x48060000 +#define OMAP_HSMMC2_BASE 0x481D8000 #if defined(CONFIG_TI814X) #undef MMC_CLOCK_REFERENCE diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h index 9c8ccb6c83..d06779956f 100644 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -31,8 +31,8 @@ * OMAP HSMMC register definitions */ -#define OMAP_HSMMC1_BASE 0x4809C100 -#define OMAP_HSMMC2_BASE 0x480B4100 -#define OMAP_HSMMC3_BASE 0x480AD100 +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 +#define OMAP_HSMMC3_BASE 0x480AD000 #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h index 9c8ccb6c83..d06779956f 100644 --- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h @@ -31,8 +31,8 @@ * OMAP HSMMC register definitions */ -#define OMAP_HSMMC1_BASE 0x4809C100 -#define OMAP_HSMMC2_BASE 0x480B4100 -#define OMAP_HSMMC3_BASE 0x480AD100 +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 +#define OMAP_HSMMC3_BASE 0x480AD000 #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index 55f49c7848..dc2eb608e2 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -351,4 +351,7 @@ #define NMIN_DSP 0x460 #define RSTOUTN 0x464 +#define MCAN_SEL_ALT_MASK 0x6000 +#define MCAN_SEL 0x2000 + #endif /* _MUX_DRA7XX_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 81feac704a..f8e7f06442 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -66,6 +66,9 @@ #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F #define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F +#define DRA762_ABZ_PACKAGE 0x2 +#define DRA762_ACD_PACKAGE 0x3 + /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index ab0e7fae9c..a6b3557b50 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -62,6 +62,7 @@ u32 omap_sdram_size(void); u32 cortex_rev(void); void save_omap_boot_params(void); void init_omap_revision(void); +void init_package_revision(void); void do_io_settings(void); void sri2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 9a46340deb..dc398efd32 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -17,7 +17,9 @@ #include <asm/io.h> /* Base address */ +#ifndef EMIF1_BASE #define EMIF1_BASE 0x4c000000 +#endif #define EMIF2_BASE 0x4d000000 #define EMIF_4D 0x4 @@ -604,6 +606,34 @@ #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 +/* EMIF ECC CTRL reg */ +#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT 31 +#define EMIF_ECC_CTRL_REG_ECC_EN_MASK (1 << 31) +#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT 30 +#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK (1 << 30) +#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT 29 +#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK (1 << 29) +#define EMIF_ECC_REG_RMW_EN_SHIFT 28 +#define EMIF_ECC_REG_RMW_EN_MASK (1 << 28) +#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT 1 +#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK (1 << 1) +#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT 0 +#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK (1 << 0) + +/* EMIF ECC ADDRESS RANGE */ +#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT 16 +#define EMIF_ECC_REG_ECC_END_ADDR_MASK (0xffff << 16) +#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT 0 +#define EMIF_ECC_REG_ECC_START_ADDR_MASK (0xffff << 0) + +/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */ +#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT 5 +#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK (1 << 5) +#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT 4 +#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK (1 << 4) +#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT 3 +#define EMIF_INT_WR_ECC_ERR_SYS_MASK (1 << 3) + /* Reg mapping structure */ struct emif_reg_struct { u32 emif_mod_id_rev; @@ -664,12 +694,27 @@ struct emif_reg_struct { u32 emif_prio_class_serv_map; u32 emif_connect_id_serv_1_map; u32 emif_connect_id_serv_2_map; - u32 padding8[5]; + u32 padding8; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; + u32 padding8_1; u32 emif_rd_wr_exec_thresh; u32 emif_cos_config; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE) + u32 padding9[2]; + u32 emif_1b_ecc_err_cnt; + u32 emif_1b_ecc_err_thrush; + u32 emif_1b_ecc_err_dist_1; + u32 emif_1b_ecc_err_addr_log; + u32 emif_2b_ecc_err_addr_log; + u32 emif_ddr_phy_status[28]; + u32 padding10[19]; +#else u32 padding9[6]; u32 emif_ddr_phy_status[28]; u32 padding10[20]; +#endif u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; @@ -1190,6 +1235,9 @@ struct emif_regs { u32 emif_connect_id_serv_1_map; u32 emif_connect_id_serv_2_map; u32 emif_cos_config; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; }; struct lpddr2_mr_regs { diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 481e9389c4..5710136e88 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -597,6 +597,7 @@ extern struct prcm_regs const dra7xx_prcm; extern struct dplls const **dplls_data; extern struct dplls dra7xx_dplls; extern struct dplls dra72x_dplls; +extern struct dplls dra76x_dplls; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; @@ -743,6 +744,18 @@ static inline u8 is_dra76x(void) extern u32 *const omap_si_rev; return (*omap_si_rev & 0xFFF00000) == DRA76X; } + +static inline u8 is_dra76x_abz(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xF) == 2; +} + +static inline u8 is_dra76x_acd(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xF) == 3; +} #endif /* @@ -778,6 +791,8 @@ static inline u8 is_dra76x(void) #define DRA722_ES2_0 0x07220200 #define DRA722_ES2_1 0x07220210 +#define DRA762_ABZ_ES1_0 0x07620102 +#define DRA762_ACD_ES1_0 0x07620103 /* * silicon device type * Moving to common from cpu.h, since it is shared by various omap devices diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index fd33408622..bf9de9b211 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -28,6 +28,12 @@ #include <mmc.h> struct hsmmc { +#ifndef CONFIG_OMAP34XX + unsigned int hl_rev; + unsigned int hl_hwinfo; + unsigned int hl_sysconfig; + unsigned char res0[0xf4]; +#endif unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned int sysstatus; /* 0x14 */ @@ -49,6 +55,9 @@ struct hsmmc { unsigned int ie; /* 0x134 */ unsigned char res4[0x8]; unsigned int capa; /* 0x140 */ + unsigned char res5[0x10]; + unsigned int admaes; /* 0x154 */ + unsigned int admasal; /* 0x158 */ }; struct omap_hsmmc_plat { @@ -61,6 +70,7 @@ struct omap_hsmmc_plat { /* * OMAP HS MMC Bit definitions */ +#define MADMA_EN (0x1 << 0) #define MMC_SOFTRESET (0x1 << 1) #define RESETDONE (0x1 << 0) #define NOOPENDRAIN (0x0 << 0) @@ -77,12 +87,12 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) +#define DE_ENABLE (0x1 << 0) #define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) +#define ACEN_ENABLE (0x1 << 2) #define DDIR_OFFSET (4) #define DDIR_MASK (0x1 << 4) #define DDIR_WRITE (0x0 << 4) @@ -116,13 +126,13 @@ struct omap_hsmmc_plat { #define SDBP_PWRON (0x1 << 8) #define SDVS_1V8 (0x5 << 9) #define SDVS_3V0 (0x6 << 9) +#define DMA_SELECT (0x2 << 3) #define ICE_MASK (0x1 << 0) #define ICE_STOP (0x0 << 0) #define ICS_MASK (0x1 << 1) #define ICS_NOTREADY (0x0 << 1) #define ICE_OSCILLATE (0x1 << 0) #define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) #define CEN_ENABLE (0x1 << 2) #define CLKD_OFFSET (6) #define CLKD_MASK (0x3FF << 6) @@ -145,6 +155,7 @@ struct omap_hsmmc_plat { #define IE_DTO (0x01 << 20) #define IE_DCRC (0x01 << 21) #define IE_DEB (0x01 << 22) +#define IE_ADMAE (0x01 << 25) #define IE_CERR (0x01 << 28) #define IE_BADA (0x01 << 29) diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h index 6a7a321c1b..3f41d34a7a 100644 --- a/arch/arm/include/asm/ti-common/ti-edma3.h +++ b/arch/arm/include/asm/ti-common/ti-edma3.h @@ -119,5 +119,7 @@ void edma3_set_transfer_params(u32 base, int slot, int acnt, enum edma3_sync_dimension sync_mode); void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len); +void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len); #endif diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index cababdba52..d24596eccb 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -7,16 +7,19 @@ choice config TARGET_K2HK_EVM bool "TI Keystone 2 Kepler/Hawking EVM" select SPL_BOARD_INIT if SPL + select CMD_DDR3 imply DM_I2C config TARGET_K2E_EVM bool "TI Keystone 2 Edison EVM" select SPL_BOARD_INIT if SPL + select CMD_DDR3 imply DM_I2C config TARGET_K2L_EVM bool "TI Keystone 2 Lamar EVM" select SPL_BOARD_INIT if SPL + select CMD_DDR3 imply DM_I2C config TARGET_K2G_EVM @@ -24,6 +27,7 @@ config TARGET_K2G_EVM select BOARD_LATE_INIT select SPL_BOARD_INIT if SPL select TI_I2C_BOARD_DETECT + select CMD_DDR3 imply DM_I2C endchoice diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index 8253a3bcc1..3e076e12ec 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -13,7 +13,6 @@ ifndef CONFIG_SPL_BUILD obj-y += cmd_clock.o obj-y += cmd_mon.o obj-y += cmd_poweroff.o -obj-y += cmd_ddr3.o endif obj-y += msmc.o obj-y += ddr3.o diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 1969a10ab3..5d08418eb9 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -78,6 +78,7 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 #define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 #define KS2_DDR3A_DDRPHYC 0x02329000 +#define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE #define KS2_DDR3_MIDR_OFFSET 0x00 #define KS2_DDR3_STATUS_OFFSET 0x04 @@ -326,6 +327,9 @@ typedef volatile unsigned int *dv_reg_p; #define CPU_66AK2Lx 0xb9a7 #define CPU_66AK2Gx 0xbb06 +/* Variant definitions */ +#define CPU_66AK2G1x 0x08 + /* DEVSPEED register */ #define DEVSPEED_DEVSPEED_SHIFT 16 #define DEVSPEED_DEVSPEED_MASK (0xfff << 16) diff --git a/arch/arm/mach-keystone/include/mach/mmc_host_def.h b/arch/arm/mach-keystone/include/mach/mmc_host_def.h index a5050ac0f1..b8eed7d29b 100644 --- a/arch/arm/mach-keystone/include/mach/mmc_host_def.h +++ b/arch/arm/mach-keystone/include/mach/mmc_host_def.h @@ -16,7 +16,7 @@ * OMAP HSMMC register definitions */ -#define OMAP_HSMMC1_BASE 0x23000100 -#define OMAP_HSMMC2_BASE 0x23100100 +#define OMAP_HSMMC1_BASE 0x23000000 +#define OMAP_HSMMC2_BASE 0x23100000 #endif /* K2G_MMC_HOST_DEF_H */ diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 6e5a1e1af1..f9c03f1dd1 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -229,7 +229,19 @@ int print_cpuinfo(void) puts("66AK2Ex SR"); break; case CPU_66AK2Gx: - puts("66AK2Gx SR"); + puts("66AK2Gx"); +#ifdef CONFIG_SOC_K2G + { + int speed = get_max_arm_speed(speeds); + if (speed == SPD1000) + puts("-100 "); + else if (speed == SPD600) + puts("-60 "); + else + puts("-xx "); + } +#endif + puts("SR"); break; default: puts("Unknown\n"); @@ -241,7 +253,8 @@ int print_cpuinfo(void) puts("1.1\n"); else if (rev == 0) puts("1.0\n"); - + else if (rev == 8) + puts("1.0\n"); return 0; } #endif diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index 9ab4d250d2..dc61131c1e 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -116,22 +116,22 @@ const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = { const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = { {505, 15, 2, -1, -1, -1, -1}, /*19.2*/ {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */ - {303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ - {303, 12, 2, -1, 4, -1, -1} /* 26 MHz */ + {303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */ + {303, 12, 2, -1, -1, -1, -1} /* 26 MHz */ }; const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = { {125, 5, 1, -1, -1, -1, -1}, /*19.2*/ {50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */ - {16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */ - {200, 12, 1, -1, 4, -1, -1} /* 26 MHz */ + {16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */ + {200, 12, 1, -1, -1, -1, -1} /* 26 MHz */ }; const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = { {665, 47, 1, -1, -1, -1, -1}, /*19.2*/ {133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */ - {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ - {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ + {266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */ + {133, 12, 1, -1, -1, -1, -1} /* 26 MHz */ }; __weak const struct dpll_params *get_dpll_mpu_params(void) diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index def7fe0f0a..e3ef37b077 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -17,6 +17,7 @@ #include <asm/omap_sec_common.h> #include <asm/utils.h> #include <linux/compiler.h> +#include <asm/ti-common/ti-edma3.h> static int emif1_enabled = -1, emif2_enabled = -1; @@ -255,7 +256,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; u32 reg, i, phy; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6]; phy = readl(&emif->emif_ddr_phy_ctrl_1); /* Update PHY_REG_RDDQS_RATIO */ @@ -269,7 +270,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11]; if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++); @@ -279,7 +280,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16]; if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++); @@ -332,6 +333,71 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) update_hwleveling_output(base, regs); } +static void dra7_reset_ddr_data(u32 base, u32 size) +{ +#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) + enable_edma3_clocks(); + + edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size); + + disable_edma3_clocks(); +#else + memset((void *)base, 0, size); +#endif +} + +static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 rgn, size; + + /* ECC available only on dra76x EMIF1 */ + if ((base != EMIF1_BASE) || !is_dra76x()) + return; + + if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) { + writel(regs->emif_ecc_address_range_1, + &emif->emif_ecc_address_range_1); + writel(regs->emif_ecc_address_range_2, + &emif->emif_ecc_address_range_2); + writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); + + /* Set region1 memory with 0 */ + rgn = ((regs->emif_ecc_address_range_1 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + size = (regs->emif_ecc_address_range_1 & + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + + if (regs->emif_ecc_ctrl_reg & + EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) + dra7_reset_ddr_data(rgn, size); + + /* Set region2 memory with 0 */ + rgn = ((regs->emif_ecc_address_range_2 & + EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + size = (regs->emif_ecc_address_range_2 & + EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000; + + if (regs->emif_ecc_ctrl_reg & + EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) + dra7_reset_ddr_data(rgn, size); + +#ifdef CONFIG_DRA7XX + /* Clear the status flags and other history */ + writel(readl(&emif->emif_1b_ecc_err_cnt), + &emif->emif_1b_ecc_err_cnt); + writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); + writel(0x1, &emif->emif_2b_ecc_err_addr_log); + writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | + EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | + EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, + &emif->emif_irqstatus_sys); +#endif + } +} + static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -368,8 +434,29 @@ static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); - if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) + if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) { + /* + * Perform Dummy ECC setup just to allow hardware + * leveling of ECC memories + */ + if (is_dra76x() && (base == EMIF1_BASE) && + (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) { + writel(0, &emif->emif_ecc_address_range_1); + writel(0, &emif->emif_ecc_address_range_2); + writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK | + EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK, + &emif->emif_ecc_ctrl_reg); + } + dra7_ddr3_leveling(base, regs); + + /* Disable ECC */ + if (is_dra76x()) + writel(0, &emif->emif_ecc_ctrl_reg); + } + + /* Enable ECC as necessary */ + dra7_enable_ecc(base, regs); } static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 56890a0c54..4f491e60f2 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -66,7 +66,7 @@ static void omap_rev_string(void) u32 major_rev = (omap_rev & 0x00000F00) >> 8; u32 minor_rev = (omap_rev & 0x000000F0) >> 4; - const char *sec_s; + const char *sec_s, *package = NULL; switch (get_device_type()) { case TST_DEVICE: @@ -85,11 +85,29 @@ static void omap_rev_string(void) sec_s = "?"; } +#if defined(CONFIG_DRA7XX) + if (is_dra76x()) { + switch (omap_rev & 0xF) { + case DRA762_ABZ_PACKAGE: + package = "ABZ"; + break; + case DRA762_ACD_PACKAGE: + default: + package = "ACD"; + break; + } + } +#endif + if (soc_variant) printf("OMAP"); else printf("DRA"); - printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev); + printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev); + if (package) + printf(" %s package\n", package); + else + puts("\n"); } #ifdef CONFIG_SPL_BUILD @@ -128,6 +146,16 @@ void s_init(void) } /** + * init_package_revision() - Initialize package revision + * + * Function to get the pacakage information. This is expected to be + * overridden in the SoC family file where desired. + */ +void __weak init_package_revision(void) +{ +} + +/** * early_system_init - Does Early system initialization. * * Does early system init of watchdog, muxing, andclocks @@ -146,6 +174,7 @@ void early_system_init(void) { init_omap_revision(); hw_data_init(); + init_package_revision(); #ifdef CONFIG_SPL_BUILD if (warm_reset()) diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 8c1730a6be..deb9873cc5 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -39,6 +39,7 @@ config TARGET_AM57XX_EVM select BOARD_LATE_INIT select DRA7XX select TI_I2C_BOARD_DETECT + select CMD_DDR3 imply SCSI imply SPL_THERMAL imply DM_THERMAL diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 3bdb114bb6..bb05e1920b 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -746,6 +746,8 @@ void __weak hw_data_init(void) *ctrl = &omap5_ctrl; break; + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra76x_dplls; @@ -792,6 +794,8 @@ void get_ioregs(const struct ctrl_ioregs **regs) case DRA752_ES1_1: case DRA752_ES2_0: case DRA762_ES1_0: + case DRA762_ACD_ES1_0: + case DRA762_ABZ_ES1_0: *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 14a35dd284..57f2a8664c 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -389,6 +389,27 @@ void init_omap_revision(void) init_cpu_configuration(); } +void init_package_revision(void) +{ + unsigned int die_id[4] = { 0 }; + u8 package; + + omap_die_id(die_id); + package = (die_id[2] >> 16) & 0x3; + + if (is_dra76x()) { + switch (package) { + case DRA762_ABZ_PACKAGE: + *omap_si_rev = DRA762_ABZ_ES1_0; + break; + case DRA762_ACD_PACKAGE: + default: + *omap_si_rev = DRA762_ACD_ES1_0; + break; + } + } +} + void omap_die_id(unsigned int *die_id) { die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c index 8fb962e39d..c0e0e0888c 100644 --- a/arch/arm/mach-omap2/omap5/sdram.c +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -481,6 +481,8 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; case DRA762_ES1_0: + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA722_ES2_0: case DRA722_ES2_1: *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; @@ -711,6 +713,8 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) *iterations = sizeof(omap5_bug_00339_regs)/ sizeof(omap5_bug_00339_regs[0]); break; + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 2630e7d316..896cb7036f 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -130,7 +130,7 @@ int secure_boot_verify_image(void **image, size_t *size) *size = sig_addr - cert_addr; /* Subtract out the signature size */ /* Subtract header if present */ if (strncmp((char *)sig_addr, "CERT_ISW_", 9) == 0) - *size = ((u32 *)*image)[HEADER_SIZE_OFFSET]; + *size -= ((u32 *)*image)[HEADER_SIZE_OFFSET]; cert_size = *size; /* Check if image load address is 32-bit aligned */ @@ -168,16 +168,16 @@ auth_exit: } /* - * Output notification of successful authentication as well the name of - * the signing certificate used to re-assure the user that the secure - * code is being processed as expected. However suppress any such log - * output in case of building for SPL and booting via YMODEM. This is - * done to avoid disturbing the YMODEM serial protocol transactions. + * Output notification of successful authentication to re-assure the + * user that the secure code is being processed as expected. However + * suppress any such log output in case of building for SPL and booting + * via YMODEM. This is done to avoid disturbing the YMODEM serial + * protocol transactions. */ if (!(IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) - printf("Authentication passed: %s\n", (char *)sig_addr); + printf("Authentication passed\n"); return result; } diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig index 3500b56cb0..133163aecf 100644 --- a/arch/arm/mach-qemu/Kconfig +++ b/arch/arm/mach-qemu/Kconfig @@ -10,3 +10,14 @@ config SYS_CONFIG_NAME default "qemu-arm" endif + +config TARGET_QEMU_ARM_32BIT + bool "Support qemu_arm" + depends on ARCH_QEMU + select CPU_V7 + select ARCH_SUPPORT_PSCI + +config TARGET_QEMU_ARM_64BIT + bool "Support qemu_arm64" + depends on ARCH_QEMU + select ARM64 diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index b618b60795..5f7a2b5669 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -2,9 +2,31 @@ if STM32 config STM32F4 bool "stm32f4 family" + select CLK + select DM_GPIO + select DM_RESET + select MISC + select PINCTRL + select PINCTRL_STM32 + select RAM + select STM32_SDRAM + select STM32_RCC + select STM32_RESET + select STM32_SERIAL config STM32F7 bool "stm32f7 family" + select CLK + select DM_GPIO + select DM_RESET + select MISC + select PINCTRL + select PINCTRL_STM32 + select RAM + select STM32_SDRAM + select STM32_RCC + select STM32_RESET + select STM32_SERIAL select SUPPORT_SPL select SPL select SPL_CLK @@ -38,7 +60,7 @@ config STM32H7 select STM32_SDRAM select STM32_RCC select STM32_RESET - select STM32X7_SERIAL + select STM32_SERIAL select SYSCON source "arch/arm/mach-stm32/stm32f4/Kconfig" diff --git a/board/emulation/qemu-arm/MAINTAINERS b/board/emulation/qemu-arm/MAINTAINERS index a803061ff4..e757ffc64f 100644 --- a/board/emulation/qemu-arm/MAINTAINERS +++ b/board/emulation/qemu-arm/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/emulation/qemu-arm/ F: include/configs/qemu-arm.h F: configs/qemu_arm_defconfig +F: configs/qemu_arm64_defconfig diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index e29ba4630f..1bc7edcfb7 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -6,6 +6,41 @@ #include <common.h> #include <fdtdec.h> +#ifdef CONFIG_ARM64 +#include <asm/armv8/mmu.h> + +static struct mm_region qemu_arm64_mem_map[] = { + { + /* Flash */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Peripherals */ + .virt = 0x08000000UL, + .phys = 0x08000000UL, + .size = 0x38000000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0xc0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = qemu_arm64_mem_map; +#endif + int board_init(void) { return 0; diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README index 89e033e1c5..b7ceb5993e 100644 --- a/board/freescale/m52277evb/README +++ b/board/freescale/m52277evb/README @@ -67,7 +67,6 @@ Changed files: 1.2 Configuration settings for M52277EVB Development Board CONFIG_MCF5227x -- define for all MCF5227x CPUs CONFIG_M52277 -- define for all Freescale MCF52277 CPUs -CONFIG_M52277EVB -- define for M52277EVB board CONFIG_MCFUART -- define to use common CF Uart driver CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 diff --git a/board/freescale/m5253evbe/README b/board/freescale/m5253evbe/README index 2ed5c768d5..f4eae67fc0 100644 --- a/board/freescale/m5253evbe/README +++ b/board/freescale/m5253evbe/README @@ -27,7 +27,6 @@ Created 06/05/2007 3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h CONFIG_MCF52x2 Processor family CONFIG_MCF5253 MCF5253 specific - CONFIG_M5253EVBE Amadeus Plus board specific CONFIG_SYS_CLK Define Amadeus Plus CPU Clock CONFIG_SYS_MBAR MBAR base address CONFIG_SYS_MBAR2 MBAR2 base address diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README index 48bbd50356..3012b83737 100644 --- a/board/freescale/mpc8349itx/README +++ b/board/freescale/mpc8349itx/README @@ -91,7 +91,6 @@ Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards CONFIG_MPC83xx MPC83xx family CONFIG_MPC8349 MPC8349 specific CONFIG_MPC8349ITX MPC8349E-mITX - CONFIG_MPC8349ITXGP MPC8349E-mITX-GP 5. Compilation diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index f79aefd400..11287846e0 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -43,6 +43,7 @@ #define board_is_am572x_evm_reva3() \ (board_ti_is("AM572PM_") && \ !strncmp("A.30", board_ti_get_rev(), 3)) +#define board_is_am574x_idk() board_ti_is("AM574IDK") #define board_is_am572x_idk() board_ti_is("AM572IDK") #define board_is_am571x_idk() board_ti_is("AM571IDK") @@ -88,10 +89,18 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = { .is_ma_present = 0x1 }; +static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = { + .dmm_lisa_map_2 = 0xc0600200, + .dmm_lisa_map_3 = 0x80600100, + .is_ma_present = 0x1 +}; + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { if (board_is_am571x_idk()) *dmm_lisa_regs = &am571x_idk_lisa_regs; + else if (board_is_am574x_idk()) + *dmm_lisa_regs = &am574x_idk_lisa_regs; else *dmm_lisa_regs = &beagle_x15_lisa_regs; } @@ -230,8 +239,8 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .ref_ctrl = 0x0000514d, .ref_ctrl_final = 0x0000144a, .sdram_tim1 = 0xd333887c, - .sdram_tim2 = 0x40b37fe3, - .sdram_tim3 = 0x409f8ada, + .sdram_tim2 = 0x30b37fe3, + .sdram_tim3 = 0x409f8ad8, .read_idle_ctrl = 0x00050000, .zq_config = 0x5007190b, .temp_alert_config = 0x00000000, @@ -248,17 +257,50 @@ static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = { .emif_rd_wr_exec_thresh = 0x00000305 }; +static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = { + .sdram_config_init = 0x61863332, + .sdram_config = 0x61863332, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x0000514d, + .ref_ctrl_final = 0x0000144a, + .sdram_tim1 = 0xd333887c, + .sdram_tim2 = 0x30b37fe3, + .sdram_tim3 = 0x409f8ad8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400f, + .emif_ddr_phy_ctlr_1 = 0x0e24400f, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305, + .emif_ecc_ctrl_reg = 0xD0000001, + .emif_ecc_address_range_1 = 0x3FFF0000, + .emif_ecc_address_range_2 = 0x00000000 +}; + void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { switch (emif_nr) { case 1: if (board_is_am571x_idk()) *regs = &am571x_emif1_ddr3_666mhz_emif_regs; + else if (board_is_am574x_idk()) + *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs; else *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; break; case 2: - *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; + if (board_is_am574x_idk()) + *regs = &am571x_emif1_ddr3_666mhz_emif_regs; + else + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; break; } } @@ -481,6 +523,8 @@ void do_board_detect(void) bname = "BeagleBoard X15"; else if (board_is_am572x_evm()) bname = "AM572x EVM"; + else if (board_is_am574x_idk()) + bname = "AM574x IDK"; else if (board_is_am572x_idk()) bname = "AM572x IDK"; else if (board_is_am571x_idk()) @@ -513,6 +557,8 @@ static void setup_board_eeprom_env(void) name = "am57xx_evm_reva3"; else name = "am57xx_evm"; + } else if (board_is_am574x_idk()) { + name = "am574x_idk"; } else if (board_is_am572x_idk()) { name = "am572x_idk"; } else if (board_is_am571x_idk()) { @@ -530,7 +576,7 @@ invalid_eeprom: void vcores_init(void) { - if (board_is_am572x_idk()) + if (board_is_am572x_idk() || board_is_am574x_idk()) *omap_vcores = &am572x_idk_volts; else if (board_is_am571x_idk()) *omap_vcores = &am571x_idk_volts; @@ -543,6 +589,8 @@ void hw_data_init(void) *prcm = &dra7xx_prcm; if (is_dra72x()) *dplls_data = &dra72x_dplls; + else if (is_dra76x()) + *dplls_data = &dra76x_dplls; else *dplls_data = &dra7xx_dplls; *ctrl = &dra7xx_ctrl; @@ -688,6 +736,11 @@ void recalibrate_iodelay(void) pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk); iod = iodelay_cfg_array_am572x_idk; iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk); + } else if (board_is_am574x_idk()) { + pconf = core_padconf_array_essential_am574x_idk; + pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk); + iod = iodelay_cfg_array_am574x_idk; + iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk); } else if (board_is_am571x_idk()) { pconf = core_padconf_array_essential_am571x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk); @@ -990,7 +1043,8 @@ int board_eth_init(bd_t *bis) writel(ctrl_val, (*ctrl)->control_core_control_io1); /* The phy address for the AM57xx IDK are different than x15 */ - if (board_is_am572x_idk() || board_is_am571x_idk()) { + if (board_is_am572x_idk() || board_is_am571x_idk() || + board_is_am574x_idk()) { cpsw_data.slave_data[0].phy_addr = 0; cpsw_data.slave_data[1].phy_addr = 1; } @@ -1074,6 +1128,8 @@ int board_fit_config_name_match(const char *name) return 0; } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) { return 0; + } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) { + return 0; } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) { return 0; } diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index b4a71bd7c8..a48f681840 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -298,6 +298,226 @@ const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = { {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ }; +const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = { + {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */ + {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */ + {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */ + {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */ + {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */ + {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */ + {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */ + {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */ + {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */ + {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */ + {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */ + {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */ + {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */ + {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ + {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */ + {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */ + {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */ + {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */ + {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */ + {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */ + {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */ + {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */ + {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */ + {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */ + {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */ + {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */ + {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */ + {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */ + {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */ + {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */ + {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */ + {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */ + {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */ + {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */ + {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */ + {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */ + {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */ + {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */ + {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */ + {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */ + {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */ + {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */ + {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */ + {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ + {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ + {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */ + {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */ + {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ + {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_AXR4, (M14 | PIN_INPUT)}, /* mcasp2_axr4.gpio1_4 */ + {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */ + {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */ + {MCASP2_AXR7, (M14 | PIN_INPUT)}, /* mcasp2_axr7.gpio1_5 */ + {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ + {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */ + {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */ + {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ + {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */ + {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ + {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ + {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ + {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */ + {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */ + {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */ + {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */ + {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */ + {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */ + {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */ + {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */ + {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */ + {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ + {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ + {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ + {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ + {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ + {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ + {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */ + {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */ + {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */ + {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */ + {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */ + {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ + {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ + {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ + {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */ + {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */ + {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */ + {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */ + {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */ + {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */ + {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */ + {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */ + {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */ +}; + const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */ {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */ @@ -980,6 +1200,85 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = { {0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */ }; +const struct iodelay_cfg_entry iodelay_cfg_array_am574x_idk[] = { + {0x0114, 2199, 621}, /* CFG_GPMC_A0_IN */ + {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 2133, 859}, /* CFG_GPMC_A11_IN */ + {0x0138, 2258, 562}, /* CFG_GPMC_A12_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */ + {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */ + {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */ + {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x0198, 1989, 612}, /* CFG_GPMC_A1_IN */ + {0x0204, 2218, 912}, /* CFG_GPMC_A2_IN */ + {0x0210, 2168, 963}, /* CFG_GPMC_A3_IN */ + {0x021C, 2196, 813}, /* CFG_GPMC_A4_IN */ + {0x0228, 2082, 782}, /* CFG_GPMC_A5_IN */ + {0x0234, 2098, 407}, /* CFG_GPMC_A6_IN */ + {0x0240, 2343, 585}, /* CFG_GPMC_A7_IN */ + {0x024C, 2030, 685}, /* CFG_GPMC_A8_IN */ + {0x0258, 2116, 832}, /* CFG_GPMC_A9_IN */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ + {0x0590, 1000, 3900}, /* CFG_MCASP5_ACLKX_OUT */ + {0x05AC, 1000, 3800}, /* CFG_MCASP5_FSX_IN */ + {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */ + {0x0B30, 0, 200}, /* CFG_VIN2A_D5_OUT */ + {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */ + {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */ + {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */ + {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */ + {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */ + {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */ + {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */ + {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */ + {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */ + {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */ + {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */ + {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */ + {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */ + {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */ + {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */ + {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */ + {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */ + {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */ + {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */ + {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */ + {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */ + {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */ + {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */ + {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */ + {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */ + {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */ + {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */ + {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */ +}; + const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = { {0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */ {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */ diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index bdf84b0be8..d8402f2675 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -103,6 +103,17 @@ int board_init(void) return 0; } +#if defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + /* * Routine: get_board_revision * Description: Detect if we are running on a Beagle revision Ax/Bx, diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 6bcfa48231..6ecf971a92 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -285,6 +285,8 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: if (emif_nr == 1) *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76; @@ -347,6 +349,8 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) ram_size = board_ti_get_emif_size(); switch (omap_revision()) { + case DRA762_ABZ_ES1_0: + case DRA762_ACD_ES1_0: case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: @@ -655,8 +659,10 @@ int board_late_init(void) name = "dra71x"; else name = "dra72x"; - } else if (is_dra76x()) { - name = "dra76x"; + } else if (is_dra76x_abz()) { + name = "dra76x_abz"; + } else if (is_dra76x_acd()) { + name = "dra76x_acd"; } else { name = "dra7xx"; } @@ -793,6 +799,7 @@ void recalibrate_iodelay(void) iodelay = dra742_es1_1_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); break; + case DRA762_ACD_ES1_0: case DRA762_ES1_0: pads = dra76x_core_padconf_array; npads = ARRAY_SIZE(dra76x_core_padconf_array); @@ -801,6 +808,7 @@ void recalibrate_iodelay(void) break; default: case DRA752_ES2_0: + case DRA762_ABZ_ES1_0: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; @@ -823,6 +831,11 @@ void recalibrate_iodelay(void) do_set_mux32((*ctrl)->control_padconf_core_base, delta_pads, delta_npads); + if (is_dra76x()) + /* Set mux for MCAN instead of DCAN1 */ + clrsetbits_le32((*ctrl)->control_core_control_spare_rw, + MCAN_SEL_ALT_MASK, MCAN_SEL); + /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); err: @@ -1125,9 +1138,10 @@ int board_fit_config_name_match(const char *name) } else if (!strcmp(name, "dra72-evm")) { return 0; } - } else if (is_dra76x() && !strcmp(name, "dra76-evm")) { + } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) { return 0; - } else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) { + } else if (!is_dra72x() && !is_dra76x_acd() && + !strcmp(name, "dra7-evm")) { return 0; } diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 3c3a19a0e1..b5dcaa584a 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -882,7 +882,7 @@ const struct pad_conf_entry dra76x_core_padconf_array[] = { {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */ {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */ - {WAKEUP2, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq2 */ + {WAKEUP2, (M14 | PIN_INPUT)}, /* N/A.gpio1_2 */ {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */ }; diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h index b3ad1881fa..48d60a1c74 100644 --- a/board/ti/ks2_evm/board.h +++ b/board/ti/ks2_evm/board.h @@ -20,6 +20,10 @@ static inline int board_is_k2g_gp(void) { return board_ti_is("66AK2GGP"); } +static inline int board_is_k2g_g1(void) +{ + return board_ti_is("66AK2GG1"); +} static inline int board_is_k2g_ice(void) { return board_ti_is("66AK2GIC"); diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 01328f1955..88df419b10 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -55,7 +55,7 @@ unsigned int get_external_clk(u32 clk) return clk_freq; } -static int arm_speeds[DEVSPEED_NUMSPDS] = { +int speeds[DEVSPEED_NUMSPDS] = { SPD400, SPD600, SPD800, @@ -159,13 +159,20 @@ static struct pll_init_data nss_pll_config[MAX_SYSCLK] = { [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2}, }; -static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = { +static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = { [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16}, [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16}, [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16}, [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16}, }; +static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = { + [SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14}, + [SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14}, + [SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14}, + [SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14}, +}; + struct pll_init_data *get_pll_init_data(int pll) { int speed; @@ -178,7 +185,7 @@ struct pll_init_data *get_pll_init_data(int pll) data = &main_pll_config[sysclk_index][speed]; break; case TETRIS_PLL: - speed = get_max_arm_speed(arm_speeds); + speed = get_max_arm_speed(speeds); data = &tetris_pll_config[sysclk_index][speed]; break; case NSS_PLL: @@ -188,7 +195,15 @@ struct pll_init_data *get_pll_init_data(int pll) data = &uart_pll_config[sysclk_index]; break; case DDR3_PLL: - data = &ddr3_pll_config[sysclk_index]; + if (cpu_revision() & CPU_66AK2G1x) { + speed = get_max_arm_speed(speeds); + if (speed == SPD1000) + data = &ddr3_pll_config_1066[sysclk_index]; + else + data = &ddr3_pll_config_800[sysclk_index]; + } else { + data = &ddr3_pll_config_800[sysclk_index]; + } break; default: data = NULL; @@ -209,7 +224,7 @@ int board_mmc_init(bd_t *bis) return -1; } - if (board_is_k2g_gp()) + if (board_is_k2g_gp() || board_is_k2g_g1()) omap_mmc_init(0, 0, 0, -1, -1); omap_mmc_init(1, 0, 0, -1, -1); @@ -224,7 +239,8 @@ int board_fit_config_name_match(const char *name) if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read) return 0; - else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP")) + else if (!strcmp(name, "keystone-k2g-evm") && + (board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1"))) return 0; else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC")) return 0; @@ -283,7 +299,7 @@ int embedded_dtb_select(void) k2g_reset_mux_config(); - if (board_is_k2g_gp()) { + if (board_is_k2g_gp() || board_is_k2g_g1()) { /* deassert FLASH_HOLD */ clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, BIT(9)); @@ -312,6 +328,8 @@ int board_late_init(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG if (board_is_k2g_gp()) env_set("board_name", "66AK2GGP\0"); + else if (board_is_k2g_g1()) + env_set("board_name", "66AK2GG1\0"); else if (board_is_k2g_ice()) env_set("board_name", "66AK2GIC\0"); #endif diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c index 44db335580..3398246e28 100644 --- a/board/ti/ks2_evm/ddr3_k2g.c +++ b/board/ti/ks2_evm/ddr3_k2g.c @@ -10,10 +10,11 @@ #include <common.h> #include "ddr3_cfg.h" #include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> #include "board.h" /* K2G GP EVM DDR3 Configuration */ -struct ddr3_phy_config ddr3phy_800_2g = { +static struct ddr3_phy_config ddr3phy_800_2g = { .pllcr = 0x000DC000ul, .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), @@ -53,7 +54,47 @@ struct ddr3_phy_config ddr3phy_800_2g = { .pir_v2 = 0x00000F81ul, }; -struct ddr3_emif_config ddr3_800_2g = { +static struct ddr3_phy_config ddr3phy_1066_2g = { + .pllcr = 0x000DC000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, + .ptr3 = 0x0904111Dul, + .ptr4 = 0x0859A072ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x6D147744ul, + .dtpr1 = 0x32845A80ul, + .dtpr2 = 0x50023600ul, + .mr0 = 0x00001830ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000000ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F05159ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .datx8_2_mask = 0, + .datx8_2_val = 0, + .datx8_3_mask = 0, + .datx8_3_val = 0, + .datx8_4_mask = 0, + .datx8_4_val = ((1 << 0)), + .datx8_5_mask = DXEN_MASK, + .datx8_5_val = 0, + .datx8_6_mask = DXEN_MASK, + .datx8_6_val = 0, + .datx8_7_mask = DXEN_MASK, + .datx8_7_val = 0, + .datx8_8_mask = DXEN_MASK, + .datx8_8_val = 0, + .pir_v2 = 0x00000F81ul, +}; + +static struct ddr3_emif_config ddr3_800_2g = { .sdcfg = 0x62005662ul, .sdtim1 = 0x0A385033ul, .sdtim2 = 0x00001CA5ul, @@ -63,8 +104,18 @@ struct ddr3_emif_config ddr3_800_2g = { .sdrfc = 0x00000C34ul, }; +static struct ddr3_emif_config ddr3_1066_2g = { + .sdcfg = 0x62005662ul, + .sdtim1 = 0x0E4C6843ul, + .sdtim2 = 0x00001CC6ul, + .sdtim3 = 0x323DFF32ul, + .sdtim4 = 0x533F08AFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001044ul, +}; + /* K2G ICE evm DDR3 Configuration */ -struct ddr3_phy_config ddr3phy_800_512mb = { +static struct ddr3_phy_config ddr3phy_800_512mb = { .pllcr = 0x000DC000ul, .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), .pgcr1_val = ((1 << 2) | (2 << 7) | (1 << 23)), @@ -104,7 +155,7 @@ struct ddr3_phy_config ddr3phy_800_512mb = { .pir_v2 = 0x00000F81ul, }; -struct ddr3_emif_config ddr3_800_512mb = { +static struct ddr3_emif_config ddr3_800_512mb = { .sdcfg = 0x62006662ul, .sdtim1 = 0x0A385033ul, .sdtim2 = 0x00001CA5ul, @@ -118,8 +169,10 @@ u32 ddr3_init(void) { /* Reset DDR3 PHY after PLL enabled */ ddr3_reset_ddrphy(); - - if (board_is_k2g_gp()) { + if (board_is_k2g_g1()) { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1066_2g); + } else if (board_is_k2g_gp()) { ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g); } else if (board_is_k2g_ice()) { diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index 630103d0ff..9e3fa11003 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -345,7 +345,7 @@ void k2g_mux_config(void) { if (!board_ti_was_eeprom_read()) { configure_pin_mux(k2g_generic_pin_cfg); - } else if (board_is_k2g_gp()) { + } else if (board_is_k2g_gp() || board_is_k2g_g1()) { configure_pin_mux(k2g_evm_pin_cfg); } else if (board_is_k2g_ice()) { configure_pin_mux(k2g_ice_evm_pin_cfg); diff --git a/cmd/Kconfig b/cmd/Kconfig index 83dc778e46..faa8bc62b5 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1184,6 +1184,8 @@ config CMD_UUID endmenu +source "cmd/ti/Kconfig" + config CMD_BOOTSTAGE bool "Enable the 'bootstage' command" depends on BOOTSTAGE diff --git a/cmd/Makefile b/cmd/Makefile index ce65cef8ce..5ab47cbbf1 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -159,6 +159,7 @@ endif # !CONFIG_SPL_BUILD obj-y += nvedit.o obj-$(CONFIG_ARCH_MVEBU) += mvebu/ +obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/ filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";") diff --git a/cmd/pmic.c b/cmd/pmic.c index 970767cdfa..7bf23fb2a9 100644 --- a/cmd/pmic.c +++ b/cmd/pmic.c @@ -201,7 +201,7 @@ static int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, } U_BOOT_CMD(pmic, CONFIG_SYS_MAXARGS, 1, do_pmic, - " operations", + "PMIC sub-system", "list - list pmic devices\n" "pmic dev [name] - show or [set] operating PMIC device\n" "pmic dump - dump registers\n" diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig new file mode 100644 index 0000000000..efeff0d482 --- /dev/null +++ b/cmd/ti/Kconfig @@ -0,0 +1,10 @@ +menu "TI specific command line interface" + +config CMD_DDR3 + bool "command for verifying DDR features" + help + Support for testing ddr3 on TI platforms. This command + supports memory verification, memory comapre and ecc + verification if supported. + +endmenu diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile new file mode 100644 index 0000000000..7dba66f4e7 --- /dev/null +++ b/cmd/ti/Makefile @@ -0,0 +1,10 @@ +# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj- += dummy.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_CMD_DDR3) += ddr3.o +endif diff --git a/arch/arm/mach-keystone/cmd_ddr3.c b/cmd/ti/ddr3.c index d3eab0711c..664bb5ff55 100644 --- a/arch/arm/mach-keystone/cmd_ddr3.c +++ b/cmd/ti/ddr3.c @@ -1,19 +1,21 @@ /* - * Keystone2: DDR3 test commands + * EMIF: DDR3 test commands * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> + * Copyright (C) 2012-2017 Texas Instruments Incorporated, <www.ti.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <asm/arch/hardware.h> -#include <asm/arch/ddr3.h> +#include <asm/cache.h> +#include <asm/emif.h> #include <common.h> #include <command.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_ARCH_KEYSTONE +#include <asm/arch/ddr3.h> #define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE #define STACKSIZE (512 << 10) /* 512 KiB */ @@ -22,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \ STACKSIZE) >> 17) - 2) +#endif #define DDR_TEST_BURST_SIZE 1024 @@ -154,57 +157,143 @@ static int ddr_memory_compare(u32 address1, u32 address2, u32 size) return 0; } -static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err) +static void ddr_check_ecc_status(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt); + u32 int_status = readl(&emif->emif_irqstatus_raw_sys); + int ecc_test = 0; + char *env; + + env = env_get("ecc_test"); + if (env) + ecc_test = simple_strtol(env, NULL, 0); + + puts("ECC test Status:\n"); + if (int_status & EMIF_INT_WR_ECC_ERR_SYS_MASK) + puts("\tECC test: DDR ECC write error interrupted\n"); + + if (int_status & EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK) + if (!ecc_test) + panic("\tECC test: DDR ECC 2-bit error interrupted"); + + if (int_status & EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK) + puts("\tECC test: DDR ECC 1-bit error interrupted\n"); + + if (err_1b) + printf("\tECC test: 1-bit ECC err count: 0x%x\n", err_1b); +} + +static int ddr_memory_ecc_err(u32 addr, u32 ecc_err) { - u32 value1, value2, value3; + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + u32 val1, val2, val3; + + debug("Disabling D-Cache before ECC test\n"); + dcache_disable(); + invalidate_dcache_all(); - puts("Disabling DDR ECC ...\n"); - ddr3_disable_ecc(base); + puts("Testing DDR ECC:\n"); + puts("\tECC test: Disabling DDR ECC ...\n"); + writel(0, &emif->emif_ecc_ctrl_reg); - value1 = __raw_readl(address); - value2 = value1 ^ ecc_err; - __raw_writel(value2, address); + val1 = readl(addr); + val2 = val1 ^ ecc_err; + writel(val2, addr); - value3 = __raw_readl(address); - printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n", - address, value1, value2, ecc_err, value3); + val3 = readl(addr); + printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n", + addr, val1, val2, ecc_err, val3); - __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16), - base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + puts("\tECC test: Enabling DDR ECC ...\n"); +#ifdef CONFIG_ARCH_KEYSTONE + ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16); + writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + ddr3_enable_ecc(EMIF1_BASE, 1); +#else + writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg); +#endif - puts("Enabling DDR ECC ...\n"); - ddr3_enable_ecc(base, 1); + val1 = readl(addr); + printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1); - value1 = __raw_readl(address); - printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1); + ddr_check_ecc_status(); + + debug("Enabling D-cache back after ECC test\n"); + enable_caches(); - ddr3_check_ecc_int(base); return 0; } +static int is_addr_valid(u32 addr) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 start_addr, end_addr, range, ecc_ctrl; + +#ifdef CONFIG_ARCH_KEYSTONE + ecc_ctrl = EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK; + range = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16); +#else + ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + range = readl(&emif->emif_ecc_address_range_1); +#endif + + /* Check in ecc address range 1 */ + if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { + start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + + 0xFFFF; + if ((addr >= start_addr) && (addr <= end_addr)) + /* addr within ecc address range 1 */ + return 1; + } + + /* Check in ecc address range 2 */ + if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) { + range = readl(&emif->emif_ecc_address_range_2); + start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) + + CONFIG_SYS_SDRAM_BASE; + end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + + 0xFFFF; + if ((addr >= start_addr) && (addr <= end_addr)) + /* addr within ecc address range 2 */ + return 1; + } + + return 0; +} + +static int is_ecc_enabled(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg); + + return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) && + (ecc_ctrl & EMIF_ECC_REG_RMW_EN_MASK); +} + static int do_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { u32 start_addr, end_addr, size, ecc_err; if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) { - if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) { - puts("ECC RMW isn't supported for this SOC\n"); - return 1; + if (!is_ecc_enabled()) { + puts("ECC not enabled. Please Enable ECC any try again\n"); + return CMD_RET_FAILURE; } start_addr = simple_strtoul(argv[2], NULL, 16); ecc_err = simple_strtoul(argv[3], NULL, 16); - if ((start_addr < CONFIG_SYS_SDRAM_BASE) || - (start_addr > (CONFIG_SYS_SDRAM_BASE + - CONFIG_MAX_RAM_BANK_SIZE - 1))) { - puts("Invalid address!\n"); - return cmd_usage(cmdtp); + if (!is_addr_valid(start_addr)) { + puts("Invalid address. Please enter ECC supported address!\n"); + return CMD_RET_FAILURE; } - ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE, - start_addr, ecc_err); + ddr_memory_ecc_err(start_addr, ecc_err); return 0; } @@ -217,10 +306,10 @@ static int do_ddr_test(cmd_tbl_t *cmdtp, if ((start_addr < CONFIG_SYS_SDRAM_BASE) || (start_addr > (CONFIG_SYS_SDRAM_BASE + - CONFIG_MAX_RAM_BANK_SIZE - 1)) || + get_effective_memsize() - 1)) || (end_addr < CONFIG_SYS_SDRAM_BASE) || (end_addr > (CONFIG_SYS_SDRAM_BASE + - CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) { + get_effective_memsize() - 1)) || (start_addr >= end_addr)) { puts("Invalid start or end address!\n"); return cmd_usage(cmdtp); } diff --git a/common/board_r.c b/common/board_r.c index 2a9df6b716..2baa47f3a0 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -624,9 +624,7 @@ int initr_mem(void) ulong pram = 0; char memsz[32]; -# ifdef CONFIG_PRAM pram = env_get_ulong("pram", 10, CONFIG_PRAM); -# endif sprintf(memsz, "%ldk", (long int) ((gd->ram_size / 1024) - pram)); env_set("mem", memsz); diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 319141de1b..97dc8e7a80 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -3,7 +3,7 @@ CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000" +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" CONFIG_BOOTDELAY=6 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitxgp:eth0:off console=ttyS0,115200" diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 04484e0ae2..b3b3cf7168 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_SPL=y CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk" +CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SPL_DM=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 6c33cc9030..edfead087d 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -38,7 +38,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk" +CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_SPL_DM=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index a04cfee5f0..11cb7e03a6 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -39,3 +39,4 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_PANIC_HANG=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index ad7207909b..95c8784888 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -2,9 +2,11 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TARGET_OMAP3_BEAGLE=y +CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle" CONFIG_DISTRO_DEFAULTS=y # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y CONFIG_SPL_MTD_SUPPORT=y @@ -26,7 +28,9 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)" +CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y +# CONFIG_BLK is not set CONFIG_LED_STATUS=y CONFIG_LED_STATUS0=y CONFIG_LED_STATUS_BIT=1 @@ -59,4 +63,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_FAT_WRITE=y +CONFIG_BCH=y CONFIG_OF_LIBFDT=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig new file mode 100644 index 0000000000..4309bd25eb --- /dev/null +++ b/configs/qemu_arm64_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_ARCH_QEMU=y +CONFIG_TARGET_QEMU_ARM_64BIT=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_OF_BOARD=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 3cd4d45433..db61b12869 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_QEMU=y +CONFIG_TARGET_QEMU_ARM_32BIT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig index 9a6d24be22..12482944af 100644 --- a/configs/rpi_0_w_defconfig +++ b/configs/rpi_0_w_defconfig @@ -12,14 +12,21 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_OF_EMBED=y +CONFIG_ENV_FAT_INTERFACE="mmc" +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 52bd9319b3..ec67aad810 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -19,16 +19,5 @@ CONFIG_CMD_TIMER=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_CLK=y -CONFIG_DM_GPIO=y -CONFIG_MISC=y -CONFIG_STM32_RCC=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_STM32=y -CONFIG_RAM=y -CONFIG_STM32_SDRAM=y -CONFIG_DM_RESET=y -CONFIG_STM32_RESET=y -CONFIG_STM32X7_SERIAL=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index afffddfc11..8190b82161 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -26,17 +26,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y # CONFIG_BLK is not set -CONFIG_CLK=y -CONFIG_DM_GPIO=y -CONFIG_MISC=y -CONFIG_STM32_RCC=y CONFIG_DM_MMC=y CONFIG_ARM_PL180_MMCI=y CONFIG_MTD_NOR_FLASH=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_STM32=y -CONFIG_RAM=y -CONFIG_STM32_SDRAM=y -CONFIG_DM_RESET=y -CONFIG_STM32_RESET=y -CONFIG_STM32X7_SERIAL=y diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index 321321fbe8..f8fa198ccb 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -39,10 +39,6 @@ CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y # CONFIG_BLK is not set -CONFIG_CLK=y -CONFIG_DM_GPIO=y -CONFIG_MISC=y -CONFIG_STM32_RCC=y CONFIG_DM_MMC=y # CONFIG_SPL_DM_MMC is not set CONFIG_ARM_PL180_MMCI=y @@ -53,14 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y -CONFIG_PINCTRL=y # CONFIG_PINCTRL_FULL is not set -CONFIG_PINCTRL_STM32=y -CONFIG_RAM=y -CONFIG_STM32_SDRAM=y -CONFIG_DM_RESET=y -CONFIG_STM32_RESET=y -CONFIG_STM32X7_SERIAL=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/README.m54418twr b/doc/README.m54418twr index 1d90fccbcf..0ca74aa114 100644 --- a/doc/README.m54418twr +++ b/doc/README.m54418twr @@ -63,7 +63,6 @@ Changed files: 1.2 Configuration settings for M54418TWR Development Board CONFIG_MCF5441x -- define for all MCF5441x CPUs CONFIG_M54418 -- define for all Freescale MCF54418 CPUs -CONFIG_M54418TWR -- define for M54418TWR board CONFIG_MCFUART -- define to use common CF Uart driver CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 diff --git a/doc/README.qemu-arm b/doc/README.qemu-arm index 2895e3b97f..aee789447a 100644 --- a/doc/README.qemu-arm +++ b/doc/README.qemu-arm @@ -4,11 +4,12 @@ # SPDX-License-Identifier: GPL-2.0+ # -U-Boot on QEMU's 'virt' machine on ARM -====================================== +U-Boot on QEMU's 'virt' machine on ARM & AArch64 +================================================ QEMU for ARM supports a special 'virt' machine designed for emulation and virtualization purposes. This document describes how to run U-Boot under it. +Both 32-bit ARM and AArch64 are supported. The 'virt' platform provides the following as the basic functionality: @@ -17,7 +18,7 @@ The 'virt' platform provides the following as the basic functionality: - A generated device tree blob placed at the start of RAM - A freely configurable amount of RAM, described by the DTB - A PL011 serial port, discoverable via the DTB - - An ARMv7 architected timer + - An ARMv7/ARMv8 architected timer - PSCI for rebooting the system - A generic ECAM-based PCI host controller, discoverable via the DTB @@ -25,19 +26,29 @@ Additionally, a number of optional peripherals can be added to the PCI bus. Building U-Boot --------------- -Set the CROSS_COMPILE and ARCH=arm environment variables as usual, and run: +Set the CROSS_COMPILE environment variable as usual, and run: +- For ARM: make qemu_arm_defconfig make +- For AArch64: + make qemu_arm64_defconfig + make + Running U-Boot -------------- The minimal QEMU command line to get U-Boot up and running is: +- For ARM: qemu-system-arm -machine virt,highmem=off -bios u-boot.bin +- For AArch64: + qemu-system-aarch64 -machine virt,highmem=off -cpu cortex-a57 -bios u-boot.bin + The 'highmem=off' parameter to the 'virt' machine is required for PCI to work -in U-Boot. +in U-Boot. Also, for some odd reason qemu-system-aarch64 needs to be explicitly +told to use a 64-bit CPU or it will boot in 32-bit mode. Additional peripherals that have been tested to work in both U-Boot and Linux can be enabled with the following command line parameters: diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index c80f90ec2f..4362d583cb 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -42,7 +42,9 @@ * |-->| TUNNEL PLL | * | -------------- * | | - * | |-->|CGU_TUN_IDIV|-----------> + * | |-->|CGU_TUN_IDIV_TUN|-----------> + * | |-->|CGU_TUN_IDIV_ROM|-----------> + * | |-->|CGU_TUN_IDIV_PWM|-----------> * | * | ------------ * |-->| HDMI PLL | @@ -60,7 +62,9 @@ DECLARE_GLOBAL_DATA_PTR; #define CGU_ARC_IDIV 0x080 -#define CGU_TUN_IDIV 0x380 +#define CGU_TUN_IDIV_TUN 0x380 +#define CGU_TUN_IDIV_ROM 0x390 +#define CGU_TUN_IDIV_PWM 0x3A0 #define CGU_HDMI_IDIV_APB 0x480 #define CGU_SYS_IDIV_APB 0x180 #define CGU_SYS_IDIV_AXI 0x190 @@ -114,8 +118,68 @@ DECLARE_GLOBAL_DATA_PTR; #define CREG_CORE_IF_CLK_DIV_1 0x0 #define CREG_CORE_IF_CLK_DIV_2 0x1 +#define MIN_PLL_RATE 100000000 /* 100 MHz */ #define PARENT_RATE 33333333 /* fixed clock - xtal */ -#define CGU_MAX_CLOCKS 24 +#define CGU_MAX_CLOCKS 26 + +#define CGU_SYS_CLOCKS 16 +#define MAX_AXI_CLOCKS 4 + +#define CGU_TUN_CLOCKS 3 +#define MAX_TUN_CLOCKS 6 + +struct hsdk_tun_idiv_cfg { + u32 oft; + u8 val[MAX_TUN_CLOCKS]; +}; + +struct hsdk_tun_clk_cfg { + const u32 clk_rate[MAX_TUN_CLOCKS]; + const u32 pll_rate[MAX_TUN_CLOCKS]; + const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS]; +}; + +static const struct hsdk_tun_clk_cfg tun_clk_cfg = { + { 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 }, + { 600000000, 600000000, 600000000, 600000000, 700000000, 600000000 }, { + { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } }, + { CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } }, + { CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } } + } +}; + +struct hsdk_sys_idiv_cfg { + u32 oft; + u8 val[MAX_AXI_CLOCKS]; +}; + +struct hsdk_axi_clk_cfg { + const u32 clk_rate[MAX_AXI_CLOCKS]; + const u32 pll_rate[MAX_AXI_CLOCKS]; + const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS]; +}; + +static const struct hsdk_axi_clk_cfg axi_clk_cfg = { + { 200000000, 400000000, 600000000, 800000000 }, + { 800000000, 800000000, 600000000, 800000000 }, { + { CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */ + { CGU_SYS_IDIV_AXI, { 4, 2, 1, 1 } }, /* AXI */ + { CGU_SYS_IDIV_ETH, { 2, 2, 2, 2 } }, /* ETH */ + { CGU_SYS_IDIV_USB, { 2, 2, 2, 2 } }, /* USB */ + { CGU_SYS_IDIV_SDIO, { 2, 2, 2, 2 } }, /* SDIO */ + { CGU_SYS_IDIV_HDMI, { 2, 2, 2, 2 } }, /* HDMI */ + { CGU_SYS_IDIV_GFX_CORE, { 1, 1, 1, 1 } }, /* GPU-CORE */ + { CGU_SYS_IDIV_GFX_DMA, { 2, 2, 2, 2 } }, /* GPU-DMA */ + { CGU_SYS_IDIV_GFX_CFG, { 4, 4, 3, 4 } }, /* GPU-CFG */ + { CGU_SYS_IDIV_DMAC_CORE,{ 2, 2, 2, 2 } }, /* DMAC-CORE */ + { CGU_SYS_IDIV_DMAC_CFG, { 4, 4, 3, 4 } }, /* DMAC-CFG */ + { CGU_SYS_IDIV_SDIO_REF, { 8, 8, 6, 8 } }, /* SDIO-REF */ + { CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */ + { CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */ + { CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */ + { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */ + } +}; struct hsdk_pll_cfg { u32 rate; @@ -201,6 +265,9 @@ static const struct hsdk_pll_devdata hdmi_pll_dat = { }; static ulong idiv_set(struct clk *, ulong); +static ulong cpu_clk_set(struct clk *, ulong); +static ulong axi_clk_set(struct clk *, ulong); +static ulong tun_clk_set(struct clk *, ulong); static ulong idiv_get(struct clk *); static int idiv_off(struct clk *); static ulong pll_set(struct clk *, ulong); @@ -218,11 +285,11 @@ struct hsdk_cgu_clock_map { static const struct hsdk_cgu_clock_map clock_map[] = { { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL }, - { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, idiv_set, idiv_off }, + { CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off }, { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL }, { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL }, { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, - { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, + { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off }, { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, @@ -238,7 +305,9 @@ static const struct hsdk_cgu_clock_map clock_map[] = { { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL }, - { CGU_TUN_PLL, 0, CGU_TUN_IDIV, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, + { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off }, + { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, + { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off }, { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL }, { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off } }; @@ -423,7 +492,7 @@ static ulong pll_set(struct clk *sclk, ulong rate) } } - pr_err("invalid rate=%ld, parent_rate=%d\n", best_rate, PARENT_RATE); + pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate, PARENT_RATE); return -EINVAL; } @@ -453,6 +522,94 @@ static ulong idiv_get(struct clk *sclk) return parent_rate / div_factor; } +/* Special behavior: wen we set this clock we set both idiv and pll */ +static ulong cpu_clk_set(struct clk *sclk, ulong rate) +{ + ulong ret; + + ret = pll_set(sclk, rate); + idiv_set(sclk, rate); + + return ret; +} + +/* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */ +static ulong axi_clk_set(struct clk *sclk, ulong rate) +{ + struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); + ulong pll_rate; + int i, freq_idx = -1; + ulong ret = 0; + + pll_rate = pll_get(sclk); + + for (i = 0; i < MAX_AXI_CLOCKS; i++) { + if (axi_clk_cfg.clk_rate[i] == rate) { + freq_idx = i; + break; + } + } + + if (freq_idx < 0) { + pr_err("axi clk: invalid rate=%ld Hz\n", rate); + return -EINVAL; + } + + /* configure PLL before dividers */ + if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate) + ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); + + /* configure SYS dividers */ + for (i = 0; i < CGU_SYS_CLOCKS; i++) { + clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft; + hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]); + } + + /* configure PLL after dividers */ + if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate) + ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); + + return ret; +} + +static ulong tun_clk_set(struct clk *sclk, ulong rate) +{ + struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); + ulong pll_rate; + int i, freq_idx = -1; + ulong ret = 0; + + pll_rate = pll_get(sclk); + + for (i = 0; i < MAX_TUN_CLOCKS; i++) { + if (tun_clk_cfg.clk_rate[i] == rate) { + freq_idx = i; + break; + } + } + + if (freq_idx < 0) { + pr_err("tun clk: invalid rate=%ld Hz\n", rate); + return -EINVAL; + } + + /* configure PLL before dividers */ + if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate) + ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]); + + /* configure SYS dividers */ + for (i = 0; i < CGU_TUN_CLOCKS; i++) { + clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft; + hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]); + } + + /* configure PLL after dividers */ + if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate) + ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]); + + return ret; +} + static ulong idiv_set(struct clk *sclk, ulong rate) { struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); @@ -466,14 +623,14 @@ static ulong idiv_set(struct clk *sclk, ulong rate) } if (div_factor & ~CGU_IDIV_MASK) { - pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: max divider valie is%d\n", + pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: max divider valie is%d\n", rate, parent_rate, div_factor, CGU_IDIV_MASK); div_factor = CGU_IDIV_MASK; } if (div_factor == 0) { - pr_err("invalid rate=%ld, parent_rate=%ld, div=%d: min divider valie is 1\n", + pr_err("invalid rate=%ld Hz, parent_rate=%ld Hz, div=%d: min divider valie is 1\n", rate, parent_rate, div_factor); div_factor = 1; @@ -559,6 +716,6 @@ U_BOOT_DRIVER(hsdk_cgu_clk) = { .id = UCLASS_CLK, .of_match = hsdk_cgu_clk_id, .probe = hsdk_cgu_clk_probe, - .platdata_auto_alloc_size = sizeof(struct hsdk_cgu_clk), + .priv_auto_alloc_size = sizeof(struct hsdk_cgu_clk), .ops = &hsdk_cgu_ops, }; diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index 635eb7876d..852c9e1fd7 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -34,10 +34,14 @@ #define EDMA3_QEESR 0x108c #define EDMA3_QSECR 0x1094 +#define EDMA_FILL_BUFFER_SIZE 512 + struct ti_edma3_priv { u32 base; }; +static u8 edma_fill_buffer[EDMA_FILL_BUFFER_SIZE] __aligned(ARCH_DMA_MINALIGN); + /** * qedma3_start - start qdma on a channel * @base: base address of edma @@ -391,7 +395,7 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg) } void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, - void *dst, void *src, size_t len) + void *dst, void *src, size_t len, size_t s_len) { struct edma3_slot_config slot; struct edma3_channel_config edma_channel; @@ -401,7 +405,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, unsigned int addr = (unsigned int) (dst); unsigned int max_acnt = 0x7FFFU; - if (len > max_acnt) { + if (len > s_len) { + b_cnt_value = (len / s_len); + rem_bytes = (len % s_len); + a_cnt_value = s_len; + } else if (len > max_acnt) { b_cnt_value = (len / max_acnt); rem_bytes = (len % max_acnt); a_cnt_value = max_acnt; @@ -412,7 +420,10 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, slot.acnt = a_cnt_value; slot.bcnt = b_cnt_value; slot.ccnt = 1; - slot.src_bidx = a_cnt_value; + if (len == s_len) + slot.src_bidx = a_cnt_value; + else + slot.src_bidx = 0; slot.dst_bidx = a_cnt_value; slot.src_cidx = 0; slot.dst_cidx = 0; @@ -438,8 +449,11 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, if (rem_bytes != 0) { slot.opt = 0; - slot.src = - (b_cnt_value * max_acnt) + ((unsigned int) src); + if (len == s_len) + slot.src = + (b_cnt_value * max_acnt) + ((unsigned int) src); + else + slot.src = (unsigned int) src; slot.acnt = rem_bytes; slot.bcnt = 1; slot.ccnt = 1; @@ -468,12 +482,39 @@ void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, } } +void __edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len) +{ + int xfer_len; + int max_xfer = EDMA_FILL_BUFFER_SIZE * 65535; + + memset((void *)edma_fill_buffer, val, sizeof(edma_fill_buffer)); + + while (len) { + xfer_len = len; + if (xfer_len > max_xfer) + xfer_len = max_xfer; + + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, + edma_fill_buffer, xfer_len, + EDMA_FILL_BUFFER_SIZE); + len -= xfer_len; + dst += xfer_len; + } +} + #ifndef CONFIG_DMA void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, void *dst, void *src, size_t len) { - __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len); + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len, len); +} + +void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, u8 val, size_t len) +{ + __edma3_fill(edma3_base_addr, edma_slot_num, dst, val, len); } #else @@ -488,7 +529,7 @@ static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst, switch (direction) { case DMA_MEM_TO_MEM: - __edma3_transfer(priv->base, 1, dst, src, len); + __edma3_transfer(priv->base, 1, dst, src, len, len); break; default: pr_err("Transfer type not implemented in DMA driver\n"); diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index d1c1ae1411..10a105df94 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -142,7 +142,7 @@ int pca953x_get_val(uint8_t chip) return (int)val; } -#ifdef CONFIG_CMD_PCA953X +#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD) /* * Display pca953x information */ @@ -193,7 +193,7 @@ static int pca953x_info(uint8_t chip) return 0; } -cmd_tbl_t cmd_pca953x[] = { +static cmd_tbl_t cmd_pca953x[] = { U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""), U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""), U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""), @@ -201,7 +201,7 @@ cmd_tbl_t cmd_pca953x[] = { U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""), }; -int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR; int ret = CMD_RET_USAGE, val; diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 6386835d5d..730460a999 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -163,7 +163,7 @@ int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]) return ret; } -#ifdef CONFIG_CMD_TCA642X +#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD) /* * Display tca642x information */ @@ -212,7 +212,7 @@ static int tca642x_info(uchar chip) return 0; } -cmd_tbl_t cmd_tca642x[] = { +static cmd_tbl_t cmd_tca642x[] = { U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""), U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""), U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""), @@ -220,7 +220,7 @@ cmd_tbl_t cmd_tca642x[] = { U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""), }; -int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR; int ret = CMD_RET_USAGE, val; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 30443d13a0..b12d6d9102 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -25,6 +25,7 @@ #include <config.h> #include <common.h> #include <malloc.h> +#include <memalign.h> #include <mmc.h> #include <part.h> #include <i2c.h> @@ -56,10 +57,6 @@ DECLARE_GLOBAL_DATA_PTR; #define SYSCTL_SRC (1 << 25) #define SYSCTL_SRD (1 << 26) -struct omap2_mmc_platform_config { - u32 reg_offset; -}; - struct omap_hsmmc_data { struct hsmmc *base_addr; #if !CONFIG_IS_ENABLED(DM_MMC) @@ -75,11 +72,45 @@ struct omap_hsmmc_data { int wp_gpio; #endif #endif + u8 controller_flags; +#ifndef CONFIG_OMAP34XX + struct omap_hsmmc_adma_desc *adma_desc_table; + uint desc_slot; +#endif }; +#ifndef CONFIG_OMAP34XX +struct omap_hsmmc_adma_desc { + u8 attr; + u8 reserved; + u16 len; + u32 addr; +}; + +#define ADMA_MAX_LEN 63488 + +/* Decriptor table defines */ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) + +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 +#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) +#endif + /* If we fail after 1 second wait, something is really bad */ #define MAX_RETRY_MS 1000 +/* DMA transfers can take a long time if a lot a data is transferred. + * The timeout must take in account the amount of data. Let's assume + * that the time will never exceed 333 ms per MB (in other word we assume + * that the bandwidth is always above 3MB/s). + */ +#define DMA_TIMEOUT_PER_MB 333 +#define OMAP_HSMMC_USE_ADMA BIT(2) + static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, unsigned int siz); @@ -246,6 +277,11 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) return -ETIMEDOUT; } } +#ifndef CONFIG_OMAP34XX + reg_val = readl(&mmc_base->hl_hwinfo); + if (reg_val & MADMA_EN) + priv->controller_flags |= OMAP_HSMMC_USE_ADMA; +#endif writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, &mmc_base->capa); @@ -258,7 +294,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) dsor = 240; mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE); start = get_timer(0); @@ -273,8 +309,8 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | - IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, - &mmc_base->ie); + IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC | + IE_CC, &mmc_base->ie); mmc_init_stream(mmc_base); @@ -326,6 +362,118 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit) } } } + +#ifndef CONFIG_OMAP34XX +static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct omap_hsmmc_adma_desc *desc; + u8 attr; + + desc = &priv->adma_desc_table[priv->desc_slot]; + + attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + if (!end) + priv->desc_slot++; + else + attr |= ADMA_DESC_ATTR_END; + + desc->len = len; + desc->addr = (u32)buf; + desc->reserved = 0; + desc->attr = attr; +} + +static void omap_hsmmc_prepare_adma_table(struct mmc *mmc, + struct mmc_data *data) +{ + uint total_len = data->blocksize * data->blocks; + uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN); + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + int i = desc_count; + char *buf; + + priv->desc_slot = 0; + priv->adma_desc_table = (struct omap_hsmmc_adma_desc *) + memalign(ARCH_DMA_MINALIGN, desc_count * + sizeof(struct omap_hsmmc_adma_desc)); + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + while (--i) { + omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false); + buf += ADMA_MAX_LEN; + total_len -= ADMA_MAX_LEN; + } + + omap_hsmmc_adma_desc(mmc, buf, total_len, true); + + flush_dcache_range((long)priv->adma_desc_table, + (long)priv->adma_desc_table + + ROUND(desc_count * + sizeof(struct omap_hsmmc_adma_desc), + ARCH_DMA_MINALIGN)); +} + +static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + char *buf; + + mmc_base = priv->base_addr; + omap_hsmmc_prepare_adma_table(mmc, data); + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + val = readl(&mmc_base->hctl); + val |= DMA_SELECT; + writel(val, &mmc_base->hctl); + + val = readl(&mmc_base->con); + val |= DMA_MASTER; + writel(val, &mmc_base->con); + + writel((u32)priv->adma_desc_table, &mmc_base->admasal); + + flush_dcache_range((u32)buf, + (u32)buf + + ROUND(data->blocksize * data->blocks, + ARCH_DMA_MINALIGN)); +} + +static void omap_hsmmc_dma_cleanup(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + + val = readl(&mmc_base->con); + val &= ~DMA_MASTER; + writel(val, &mmc_base->con); + + val = readl(&mmc_base->hctl); + val &= ~DMA_SELECT; + writel(val, &mmc_base->hctl); + + kfree(priv->adma_desc_table); +} +#else +#define omap_hsmmc_adma_desc +#define omap_hsmmc_prepare_adma_table +#define omap_hsmmc_prepare_data +#define omap_hsmmc_dma_cleanup +#endif + #if !CONFIG_IS_ENABLED(DM_MMC) static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) @@ -336,12 +484,20 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { struct omap_hsmmc_data *priv = dev_get_priv(dev); +#ifndef CONFIG_OMAP34XX + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; +#endif #endif struct hsmmc *mmc_base; unsigned int flags, mmc_stat; ulong start; mmc_base = priv->base_addr; + + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + return 0; + start = get_timer(0); while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) { if (get_timer(0) - start > MAX_RETRY_MS) { @@ -388,7 +544,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, /* enable default flags */ flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | - MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE); + MSBS_SGLEBLK); + flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE); if (cmd->resp_type & MMC_RSP_CRC) flags |= CCCE_CHECK; @@ -398,7 +555,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, if (data) { if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) { - flags |= (MSBS_MULTIBLK | BCE_ENABLE); + flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE); data->blocksize = 512; writel(data->blocksize | (data->blocks << 16), &mmc_base->blk); @@ -409,6 +566,14 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, flags |= (DP_DATA | DDIR_READ); else flags |= (DP_DATA | DDIR_WRITE); + +#ifndef CONFIG_OMAP34XX + if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && + !mmc_is_tuning_cmd(cmd->cmdidx)) { + omap_hsmmc_prepare_data(mmc, data); + flags |= DE_ENABLE; + } +#endif } writel(cmd->cmdarg, &mmc_base->arg); @@ -418,7 +583,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, start = get_timer(0); do { mmc_stat = readl(&mmc_base->stat); - if (get_timer(0) - start > MAX_RETRY_MS) { + if (get_timer(start) > MAX_RETRY_MS) { printf("%s : timeout: No status update\n", __func__); return -ETIMEDOUT; } @@ -445,6 +610,41 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, } } +#ifndef CONFIG_OMAP34XX + if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data && + !mmc_is_tuning_cmd(cmd->cmdidx)) { + u32 sz_mb, timeout; + + if (mmc_stat & IE_ADMAE) { + omap_hsmmc_dma_cleanup(mmc); + return -EIO; + } + + sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20); + timeout = sz_mb * DMA_TIMEOUT_PER_MB; + if (timeout < MAX_RETRY_MS) + timeout = MAX_RETRY_MS; + + start = get_timer(0); + do { + mmc_stat = readl(&mmc_base->stat); + if (mmc_stat & TC_MASK) { + writel(readl(&mmc_base->stat) | TC_MASK, + &mmc_base->stat); + break; + } + if (get_timer(start) > timeout) { + printf("%s : DMA timeout: No status update\n", + __func__); + return -ETIMEDOUT; + } + } while (1); + + omap_hsmmc_dma_cleanup(mmc); + return 0; + } +#endif + if (data && (data->flags & MMC_DATA_READ)) { mmc_read_data(mmc_base, data->dest, data->blocksize * data->blocks); @@ -612,7 +812,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) } mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + (ICE_STOP | DTO_15THDTO)); mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, (dsor << CLKD_OFFSET) | ICE_OSCILLATE); @@ -802,15 +1002,13 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) { struct omap_hsmmc_plat *plat = dev_get_platdata(dev); struct mmc_config *cfg = &plat->cfg; - struct omap2_mmc_platform_config *data = - (struct omap2_mmc_platform_config *)dev_get_driver_data(dev); const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); int val; plat->base_addr = map_physmem(devfdt_get_addr(dev), sizeof(struct hsmmc *), - MAP_NOCACHE) + data->reg_offset; + MAP_NOCACHE); cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; val = fdtdec_get_int(fdt, node, "bus-width", -1); @@ -886,31 +1084,10 @@ static int omap_hsmmc_probe(struct udevice *dev) } #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) -static const struct omap2_mmc_platform_config omap3_mmc_pdata = { - .reg_offset = 0, -}; - -static const struct omap2_mmc_platform_config am33xx_mmc_pdata = { - .reg_offset = 0x100, -}; - -static const struct omap2_mmc_platform_config omap4_mmc_pdata = { - .reg_offset = 0x100, -}; - static const struct udevice_id omap_hsmmc_ids[] = { - { - .compatible = "ti,omap3-hsmmc", - .data = (ulong)&omap3_mmc_pdata - }, - { - .compatible = "ti,omap4-hsmmc", - .data = (ulong)&omap4_mmc_pdata - }, - { - .compatible = "ti,am33xx-hsmmc", - .data = (ulong)&am33xx_mmc_pdata - }, + { .compatible = "ti,omap3-hsmmc" }, + { .compatible = "ti,omap4-hsmmc" }, + { .compatible = "ti,am33xx-hsmmc" }, { } }; #endif diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 122b8e786a..7b20b47964 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -529,7 +529,7 @@ config STI_ASC_SERIAL on STiH410 SoC. This is a basic implementation, it supports following baudrate 9600, 19200, 38400, 57600 and 115200. -config STM32X7_SERIAL +config STM32_SERIAL bool "STMicroelectronics STM32 SoCs on-chip UART" depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7) help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 7adcee3e10..5ef603ab15 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -44,7 +44,7 @@ obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o -obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o +obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32.c index d1580e3cb5..286b954fdd 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32.c @@ -11,7 +11,7 @@ #include <asm/io.h> #include <serial.h> #include <asm/arch/stm32.h> -#include "serial_stm32x7.h" +#include "serial_stm32.h" DECLARE_GLOBAL_DATA_PTR; @@ -148,7 +148,7 @@ static const struct dm_serial_ops stm32_serial_ops = { }; U_BOOT_DRIVER(serial_stm32) = { - .name = "serial_stm32x7", + .name = "serial_stm32", .id = UCLASS_SERIAL, .of_match = of_match_ptr(stm32_serial_id), .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata), diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32.h index f7dca39103..d08ba1f55f 100644 --- a/drivers/serial/serial_stm32x7.h +++ b/drivers/serial/serial_stm32.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SERIAL_STM32_X7_ -#define _SERIAL_STM32_X7_ +#ifndef _SERIAL_STM32_ +#define _SERIAL_STM32_ #define CR1_OFFSET(x) (x ? 0x0c : 0x00) #define CR3_OFFSET(x) (x ? 0x14 : 0x08) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index d16883fa10..1283818761 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -1106,7 +1106,7 @@ int file_fat_read_at(const char *filename, loff_t pos, void *buffer, if (ret) goto out_free_both; - printf("reading %s\n", filename); + debug("reading %s\n", filename); ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread); out_free_both: @@ -407,7 +407,7 @@ int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, /* If we requested a specific number of bytes, check we got it */ if (ret == 0 && len && *actread != len) - printf("** %s shorter than offset + len **\n", filename); + debug("** %s shorter than offset + len **\n", filename); fs_close(); return ret; diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 98692df495..72183f284a 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -18,7 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_M52277EVB /* M52277EVB board */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index ff0995e651..91e4bf80b2 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -7,8 +7,6 @@ #ifndef _M5253DEMO_H #define _M5253DEMO_H -#define CONFIG_M5253DEMO /* define board type */ - #define CONFIG_MCFTMR #define CONFIG_MCFUART diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h index d7252a1b62..8d7250a5ba 100644 --- a/include/configs/M5253EVBE.h +++ b/include/configs/M5253EVBE.h @@ -8,8 +8,6 @@ #ifndef _M5253EVBE_H #define _M5253EVBE_H -#define CONFIG_M5253EVBE /* define board type */ - #define CONFIG_MCFTMR #define CONFIG_MCFUART diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index bbc45bf7ba..38e785c068 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -21,7 +21,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_M5275EVB /* define board type */ #define CONFIG_MCFTMR diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 6469a919f6..3e2b6e174e 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -18,7 +18,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_M54418TWR /* M54418TWR board */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index bd0cb6fddc..d348ec9367 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -15,7 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ -#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */ #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 9b906a7c77..c7a5ee0aaf 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -19,7 +19,6 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ -#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0c6bcae33c..9d27358031 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -18,7 +18,6 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC834x 1 /* MPC834x specific */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ -#define CONFIG_TQM834X 1 /* TQM834X board specific */ #define CONFIG_SYS_TEXT_BASE 0x80000000 diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index f2de384631..f83659373e 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -14,8 +14,6 @@ /* * CPU and Board Configuration Options */ -#define CONFIG_ADP_AG101P - #define CONFIG_USE_INTERRUPT #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 595bd57a7f..b9fc5b5d08 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -9,7 +9,6 @@ #ifndef __AMCORE_CONFIG_H #define __AMCORE_CONFIG_H -#define CONFIG_AMCORE #define CONFIG_HOSTNAME AMCORE #define CONFIG_MCFTMR diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index ceab037cc1..540db79a27 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -39,8 +39,6 @@ #error No card type defined! #endif -#define CONFIG_ASTRO5373L /* define board type */ - /* Command line configuration */ /* * CONFIG_RAM defines if u-boot is loaded via BDM (or started from diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 29c595970a..a9c4d1ab23 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -29,7 +29,7 @@ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MALLOC_LEN SZ_2M -#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_BOOTM_LEN SZ_128M #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index e413b5158c..3da91e80c8 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_CYRUS - #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) #error Must call Cyrus CONFIG with a specific CPU enabled. #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 43646490ec..3ca5965150 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -303,17 +303,11 @@ #define CONFIG_CLOCKS #endif -#ifndef CONFIG_DRIVER_TI_EMAC -#endif - #ifdef CONFIG_USE_NAND #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS #endif -#ifdef CONFIG_USE_SPIFLASH -#endif - #if !defined(CONFIG_USE_NAND) && \ !defined(CONFIG_USE_NOR) && \ !defined(CONFIG_USE_SPIFLASH) diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ac8022275..e17b56e9bd 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -29,7 +29,7 @@ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MALLOC_LEN SZ_2M -#define CONFIG_SYS_BOOTM_LEN SZ_32M +#define CONFIG_SYS_BOOTM_LEN SZ_128M #define CONFIG_SYS_LOAD_ADDR 0x82000000 /* diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index b43c8c711e..12eb07d1f7 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -17,7 +17,6 @@ */ #define CONFIG_MPC831x #define CONFIG_MPC8313 -#define CONFIG_IDS8313 #define CONFIG_FSL_ELBC diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index df81c09d86..4e43104fac 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -34,11 +34,13 @@ "findfdt="\ "if test $board_name = 66AK2GGP; then " \ "setenv name_fdt keystone-k2g-evm.dtb; " \ + "else if test $board_name = 66AK2GG1; then " \ + "setenv name_fdt keystone-k2g-evm.dtb; " \ "else if test $board_name = 66AK2GIC; then " \ "setenv name_fdt keystone-k2g-ice.dtb; " \ "else if test $name_fdt = undefined; then " \ "echo WARNING: Could not determine device tree to use;"\ - "fi;fi;fi; setenv fdtfile ${name_fdt}\0" \ + "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \ "name_mon=skern-k2g.bin\0" \ "name_ubi=k2g-evm-ubifs.ubi\0" \ "name_uboot=u-boot-spi-k2g-evm.gph\0" \ @@ -74,7 +76,7 @@ #endif /* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c080000 +#define CONFIG_SPL_TEXT_BASE 0x0c0a0000 /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index f97773146a..69c4309139 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -15,7 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ -#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFC000000 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 394bfb7434..843e345ffd 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -14,57 +14,69 @@ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#include <configs/ti_omap3_common.h> + /* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. We use this rather than the inherited defines from - * ti_armv7_common.h for backwards compatibility. + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE 0x40200000 -#include <configs/ti_omap3_common.h> +#define CONFIG_SPL_FRAMEWORK #define CONFIG_MISC_INIT_R +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG -#define CONFIG_REVISION_TAG 1 +/* NAND */ +#if defined(CONFIG_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET 0x260000 +#define CONFIG_ENV_ADDR 0x260000 #define CONFIG_ENV_OVERWRITE +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ +/* NAND: SPL falcon mode configs */ +#if defined(CONFIG_SPL_OS_BOOT) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#endif /* CONFIG_SPL_OS_BOOT */ +#endif /* CONFIG_NAND */ -/* Status LED */ - -/* Enable Multi Bus support for I2C */ -#define CONFIG_I2C_MULTI_BUS 1 - -/* Probe all devices */ -#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}} - -/* USB */ +/* MUSB */ +#define CONFIG_USB_OMAP3 #define CONFIG_USB_MUSB_OMAP2PLUS #define CONFIG_USB_MUSB_PIO_ONLY -#define CONFIG_TWL4030_USB 1 +#define CONFIG_TWL4030_USB /* USB EHCI */ - #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 -/* commands to include */ - -#define CONFIG_VIDEO_OMAP3 /* DSS Support */ +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS -/* - * TWL4030 - */ -#define CONFIG_TWL4030_LED 1 +/* DSS Support */ +#define CONFIG_VIDEO_OMAP3 -/* - * Board NAND Info. - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ +/* TWL4030 LED Support */ +#define CONFIG_TWL4030_LED #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -91,6 +103,7 @@ "run bootscript; " \ "else " \ "if run loadimage; then " \ + "run loadfdt;" \ "run mmcboot;" \ "fi;" \ "fi; " \ @@ -105,13 +118,8 @@ #include <config_distro_bootcmd.h> #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "kernel_addr_r=0x80200000\0" \ - "rdaddr=0x81000000\0" \ - "initrd_addr_r=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ "fdt_high=0xffffffff\0" \ - "fdtaddr=0x80f80000\0" \ - "fdt_addr_r=0x80f80000\0" \ "usbtty=cdc_acm\0" \ "bootfile=uImage\0" \ "ramdisk=ramdisk.gz\0" \ @@ -127,7 +135,7 @@ "defaultdisplay=dvi\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "nandroot=ubi0:rootfs ubi.mtd=4\0" \ "nandrootfstype=ubifs\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ @@ -190,10 +198,10 @@ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ + "mmcboot=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ + "mmcbootz=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \ "run mmcargs; " \ "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ @@ -209,51 +217,4 @@ "userbutton_nonxm=gpio input 7;\0" \ BOOTENV -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x260000 -#define CONFIG_ENV_ADDR 0x260000 - -/* Defines for SPL */ - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index d95ccdf035..3ecfdbb3ce 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -89,28 +89,35 @@ #define MEM_LAYOUT_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV -#if defined(CONFIG_NAND) +#if defined(CONFIG_NAND) && defined(CONFIG_CMD_UBI) +/* NAND boot with uImage from NAND 'kernel' partition */ #define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "run nandboot\0" - #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ #devtypel #instance " " -#endif /* CONFIG_NAND */ +/* NAND boot with zImage from UBIFS '/boot/zImage' */ +#define BOOTENV_DEV_UBIFS_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "run nandbootubifs\0" +#define BOOTENV_DEV_NAME_UBIFS_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " +#endif /* CONFIG_NAND && CONFIG_CMD_UBI */ + +/* MMC boot with uImage from MMC 0:2 '/boot/uImage' */ #define BOOTENV_DEV_UIMAGE_MMC(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "setenv mmcdev " #instance"; " \ "run mmcboot\0" - #define BOOTENV_DEV_NAME_UIMAGE_MMC(devtypeu, devtypel, instance) \ #devtypel #instance " " +/* MMC boot with zImage from MMC 0:2 '/boot/zImage' */ #define BOOTENV_DEV_ZIMAGE_MMC(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "setenv mmcdev " #instance"; " \ "run mmcbootz\0" - #define BOOTENV_DEV_NAME_ZIMAGE_MMC(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -118,6 +125,7 @@ func(MMC, mmc, 0) \ func(ZIMAGE_MMC, zimage_mmc, 0) \ func(UIMAGE_MMC, uimage_mmc, 0) \ + func(UBIFS_NAND, ubifs_nand, 0) \ func(NAND, nand, 0) #include <config_distro_bootcmd.h> @@ -128,9 +136,11 @@ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "fdt_high=0xffffffff\0" \ + "bootdir=/boot\0" \ "bootenv=uEnv.txt\0" \ "optargs=\0" \ "mmcdev=0\0" \ + "mmcpart=2\0" \ "console=ttyO0,115200n8\0" \ "mmcargs=setenv bootargs console=${console} " \ "${mtdparts} " \ @@ -143,39 +153,52 @@ "root=ubi0:rootfs rw ubi.mtd=rootfs noinitrd " \ "rootfstype=ubifs rootwait\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "ext4bootenv=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ - "mmcbootenv=" \ - "mmc dev ${mmcdev}; " \ - "if mmc rescan && run loadbootenv; then " \ - "run importbootenv; " \ + "mmcbootenv=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "run loadbootenv && run importbootenv; " \ + "run ext4bootenv && run importbootenv; " \ "if test -n $uenvcmd; then " \ "echo Running uenvcmd ...; " \ "run uenvcmd; " \ "fi; " \ "fi\0" \ "loaduimage=setenv bootfile uImage; " \ - "fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "loadzimage=setenv bootfile zImage; " \ - "fatload mmc ${mmcdev} ${loadaddr} zImage\0" \ - "loaddtb=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loaddtb=ext4load mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loadubizimage=setenv bootfile zImage; " \ + "ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadubidtb=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=run mmcbootenv; " \ "if run loaduimage && run loaddtb; then " \ - "echo Booting ${bootfile} from mmc ...; " \ + "echo Booting ${bootdir}/${bootfile} from mmc ${mmcdev}:${mmcpart} ...; " \ "run mmcargs; " \ "bootm ${loadaddr} - ${fdtaddr}; " \ "fi\0" \ "mmcbootz=run mmcbootenv; " \ "if run loadzimage && run loaddtb; then " \ - "echo Booting ${bootfile} from mmc ...; " \ + "echo Booting ${bootdir}/${bootfile} from mmc ${mmcdev}:${mmcpart} ...; " \ "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr};" \ + "bootz ${loadaddr} - ${fdtaddr}; " \ "fi\0" \ - "nandboot=echo Booting uImage from nand ...; " \ - "run nandargs; " \ + "nandboot=" \ "nand read ${loadaddr} kernel; " \ "nand read ${fdtaddr} dtb; " \ + "echo Booting uImage from NAND MTD 'kernel' partition ...; " \ + "run nandargs; " \ "bootm ${loadaddr} - ${fdtaddr}\0" \ + "nandbootubifs=" \ + "ubi part rootfs; " \ + "ubifsmount ubi0:rootfs; " \ + "if run loadubizimage && run loadubidtb; then " \ + "echo Booting ${bootdir}/${bootfile} from NAND ubi0:rootfs ...; " \ + "run nandargs; " \ + "bootz ${loadaddr} - ${fdtaddr}; " \ + "fi\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 328cdf4757..7f1620db02 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -21,7 +21,6 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ -#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ #define CONFIG_SYS_TEXT_BASE 0xFF800000 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index a2a715b99d..041e69e1f7 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -36,7 +36,6 @@ /* * High Level Configuration Options */ -#define CONFIG_SBC8548 1 /* SBC8548 board specific */ /* * If you want to boot from the SODIMM flash, instead of the soldered diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 817c9d920d..03709adb2d 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -21,7 +21,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_SBC8641D 1 /* SBC8641D board specific */ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 75ca1ff2f6..cefadc1e81 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -9,7 +9,6 @@ #ifndef __STMARK2_CONFIG_H #define __STMARK2_CONFIG_H -#define CONFIG_STMARK2 #define CONFIG_HOSTNAME stmark2 #define CONFIG_MCFUART diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 562bb65636..7fb3aaf46d 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -266,7 +266,7 @@ "${bootdir}/${fit_bootfile}\0" \ "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ "get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \ - "burn_uboot_spi=sf probe; sf erase 0 0x90000; " \ + "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ "sf write ${loadaddr} 0 ${filesize}\0" \ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${loadaddr} 0 ${filesize}\0" \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 3ac11ccb8f..94a59f3e90 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -19,7 +19,6 @@ #define CONFIG_E300 1 #define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 -#define CONFIG_VE8313 1 #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfe000000 diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 4326984b06..f95d47a9a0 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -14,7 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ #define CONFIG_SYS_BOARD_NAME "XPedite5170" #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 5a56162e7c..c0df5ef02b 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -14,7 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_XPEDITE5200 1 #define CONFIG_SYS_BOARD_NAME "XPedite5200" #define CONFIG_SYS_FORM_PMC_XMC 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 624e9a82d0..b5e8231873 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -14,7 +14,6 @@ /* * High Level Configuration Options */ -#define CONFIG_XPEDITE550X 1 #define CONFIG_SYS_BOARD_NAME "XPedite5500" #define CONFIG_SYS_FORM_PMC_XMC 1 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h index 813ab71531..2cfe34eb35 100644 --- a/include/dt-bindings/clock/snps,hsdk-cgu.h +++ b/include/dt-bindings/clock/snps,hsdk-cgu.h @@ -33,8 +33,10 @@ #define CLK_SYS_UART_REF 18 #define CLK_SYS_EBI_REF 19 #define CLK_TUN_PLL 20 -#define CLK_TUN 21 -#define CLK_HDMI_PLL 22 -#define CLK_HDMI 23 +#define CLK_TUN_TUN 21 +#define CLK_TUN_ROM 22 +#define CLK_TUN_PWM 23 +#define CLK_HDMI_PLL 24 +#define CLK_HDMI 25 #endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */ diff --git a/include/dt-bindings/leds/leds-pca9532.h b/include/dt-bindings/leds/leds-pca9532.h new file mode 100644 index 0000000000..4d917aab7e --- /dev/null +++ b/include/dt-bindings/leds/leds-pca9532.h @@ -0,0 +1,18 @@ +/* + * This header provides constants for pca9532 LED bindings. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _DT_BINDINGS_LEDS_PCA9532_H +#define _DT_BINDINGS_LEDS_PCA9532_H + +#define PCA9532_TYPE_NONE 0 +#define PCA9532_TYPE_LED 1 +#define PCA9532_TYPE_N2100_BEEP 2 +#define PCA9532_TYPE_GPIO 3 +#define PCA9532_LED_TIMER2 4 + +#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index 799d9840aa..0a2342061c 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -67,7 +67,7 @@ "setenv fdtfile dra72-evm.dtb; fi;" \ "if test $board_name = dra71x; then " \ "setenv fdtfile dra71-evm.dtb; fi;" \ - "if test $board_name = dra76x; then " \ + "if test $board_name = dra76x_acd; then " \ "setenv fdtfile dra76-evm.dtb; fi;" \ "if test $board_name = beagle_x15; then " \ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ @@ -77,6 +77,8 @@ "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \ "if test $board_name = am572x_idk; then " \ "setenv fdtfile am572x-idk.dtb; fi;" \ + "if test $board_name = am574x_idk; then " \ + "setenv fdtfile am574x-idk.dtb; fi;" \ "if test $board_name = am57xx_evm; then " \ "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $board_name = am57xx_evm_reva3; then " \ diff --git a/include/pcmcia.h b/include/pcmcia.h index 94b54c210d..8df90ee2b7 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -60,115 +60,6 @@ typedef struct { ulong or; } pcmcia_win_t; -/* - * Definitions for PCMCIA control registers to operate in IDE mode - * - * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) - * to be done later (depending on CPU clock) - */ - -/* Window 0: - * Base: 0xFE100000 CS1 - * Port Size: 2 Bytes - * Port Size: 16 Bit - * Common Memory Space - */ - -#define CONFIG_SYS_PCMCIA_PBR0 0xFE100000 -#define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ - | PCMCIA_PPS_16 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_SLOT_x \ - | PCMCIA_PV \ - ) - -/* Window 1: - * Base: 0xFE100080 CS1 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CONFIG_SYS_PCMCIA_PBR1 0xFE100080 -#define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_SLOT_x \ - | PCMCIA_PV \ - ) - -/* Window 2: - * Base: 0xFE100100 CS2 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CONFIG_SYS_PCMCIA_PBR2 0xFE100100 -#define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_SLOT_x \ - | PCMCIA_PV \ - ) - -/* Window 3: - * not used - */ -#define CONFIG_SYS_PCMCIA_PBR3 0 -#define CONFIG_SYS_PCMCIA_POR3 0 - -/* Window 4: - * Base: 0xFE100C00 CS1 - * Port Size: 2 Bytes - * Port Size: 16 Bit - * Common Memory Space - */ - -#define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00 -#define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ - | PCMCIA_PPS_16 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_SLOT_x \ - | PCMCIA_PV \ - ) - -/* Window 5: - * Base: 0xFE100C80 CS1 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80 -#define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_SLOT_x \ - | PCMCIA_PV \ - ) - -/* Window 6: - * Base: 0xFE100D00 CS2 - * Port Size: 8 Bytes - * Port Size: 8 Bit - * Common Memory Space - */ - -#define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00 -#define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ - | PCMCIA_PPS_8 \ - | PCMCIA_PRS_MEM \ - | PCMCIA_SLOT_x \ - | PCMCIA_PV \ - ) - -/* Window 7: - * not used - */ -#define CONFIG_SYS_PCMCIA_PBR7 0 -#define CONFIG_SYS_PCMCIA_POR7 0 - /**********************************************************************/ /* diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 394243b3d2..c98f262079 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -18,7 +18,6 @@ CONFIG_ADDRESS CONFIG_ADDR_AUTO_INCR_BIT CONFIG_ADDR_MAP CONFIG_ADNPESC1 -CONFIG_ADP_AG101P CONFIG_AEABI CONFIG_AEMIF_CNTRL_BASE CONFIG_ALTERA_SPI_IDLE_VAL @@ -30,7 +29,6 @@ CONFIG_AM335X_USB0_MODE CONFIG_AM335X_USB1 CONFIG_AM335X_USB1_MODE CONFIG_AM437X_USB2PHY2_HOST -CONFIG_AMCORE CONFIG_ANDES_PCU CONFIG_ANDES_PCU_BASE CONFIG_APBH_DMA @@ -73,7 +71,6 @@ CONFIG_ARM_PL180_MMCI_BASE CONFIG_ARM_PL180_MMCI_CLOCK_FREQ CONFIG_ARM_THUMB CONFIG_ARP_TIMEOUT -CONFIG_ASTRO5373L CONFIG_ASTRO_COFDMDUOS2 CONFIG_ASTRO_TWIN7S2 CONFIG_ASTRO_V512 @@ -344,7 +341,6 @@ CONFIG_CSF_SIZE CONFIG_CTL_JTAG CONFIG_CTL_TBE CONFIG_CUSTOMER_BOARD_SUPPORT -CONFIG_CYRUS CONFIG_D2NET_V2 CONFIG_DA850_AM18X_EVM CONFIG_DA850_EVM_MAX_CPU_CLK @@ -1030,7 +1026,6 @@ CONFIG_IDE_PCMCIA CONFIG_IDE_PREINIT CONFIG_IDE_RESET CONFIG_IDE_SWAP_IO -CONFIG_IDS8313 CONFIG_IDT8T49N222A CONFIG_ID_EEPROM CONFIG_IMA @@ -1276,12 +1271,7 @@ CONFIG_LSXHL CONFIG_LYNXKDI CONFIG_M41T94_SPI_CS CONFIG_M520x -CONFIG_M52277EVB -CONFIG_M5253DEMO -CONFIG_M5253EVBE -CONFIG_M5275EVB CONFIG_M5301x -CONFIG_M54418TWR CONFIG_M54451EVB CONFIG_M54455EVB CONFIG_MACB0_PHY @@ -1362,8 +1352,6 @@ CONFIG_MODVERSIONS CONFIG_MONITOR_IS_IN_RAM CONFIG_MP CONFIG_MPC8308 -CONFIG_MPC8308RDB -CONFIG_MPC8308_P1M CONFIG_MPC8309 CONFIG_MPC830x CONFIG_MPC8313 @@ -1374,9 +1362,7 @@ CONFIG_MPC831x CONFIG_MPC832XEMDS CONFIG_MPC832x CONFIG_MPC8349 -CONFIG_MPC8349EMDS CONFIG_MPC8349ITX -CONFIG_MPC8349ITXGP CONFIG_MPC834x CONFIG_MPC8360 CONFIG_MPC837XEMDS @@ -1861,9 +1847,6 @@ CONFIG_SAR_REG CONFIG_SATA1 CONFIG_SATA2 CONFIG_SATA_ULI5288 -CONFIG_SBC8349 -CONFIG_SBC8548 -CONFIG_SBC8641D CONFIG_SCF0403_LCD CONFIG_SCIF CONFIG_SCIF_A @@ -2166,7 +2149,6 @@ CONFIG_STM32_GPIO CONFIG_STM32_HSE_HZ CONFIG_STM32_HZ CONFIG_STM32_SERIAL -CONFIG_STMARK2 CONFIG_STRIDER CONFIG_STRIDER_CON CONFIG_STRIDER_CON_DP @@ -4199,22 +4181,6 @@ CONFIG_SYS_PCMCIA_ATTR_BASE CONFIG_SYS_PCMCIA_IO_BASE CONFIG_SYS_PCMCIA_MEM_ADDR CONFIG_SYS_PCMCIA_MEM_SIZE -CONFIG_SYS_PCMCIA_PBR0 -CONFIG_SYS_PCMCIA_PBR1 -CONFIG_SYS_PCMCIA_PBR2 -CONFIG_SYS_PCMCIA_PBR3 -CONFIG_SYS_PCMCIA_PBR4 -CONFIG_SYS_PCMCIA_PBR5 -CONFIG_SYS_PCMCIA_PBR6 -CONFIG_SYS_PCMCIA_PBR7 -CONFIG_SYS_PCMCIA_POR0 -CONFIG_SYS_PCMCIA_POR1 -CONFIG_SYS_PCMCIA_POR2 -CONFIG_SYS_PCMCIA_POR3 -CONFIG_SYS_PCMCIA_POR4 -CONFIG_SYS_PCMCIA_POR5 -CONFIG_SYS_PCMCIA_POR6 -CONFIG_SYS_PCMCIA_POR7 CONFIG_SYS_PDCNT CONFIG_SYS_PEHLPAR CONFIG_SYS_PEPAR @@ -4751,7 +4717,6 @@ CONFIG_TMU_TIMER CONFIG_TPL_PAD_TO CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_TPS6586X_POWER -CONFIG_TQM834X CONFIG_TRACE CONFIG_TRACE_BUFFER_SIZE CONFIG_TRACE_EARLY @@ -4957,7 +4922,6 @@ CONFIG_U_QE CONFIG_VAL CONFIG_VAR_SIZE_SPL CONFIG_VCT_NOR -CONFIG_VE8313 CONFIG_VERY_BIG_RAM CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP @@ -5011,9 +4975,6 @@ CONFIG_XILINX_GPIO CONFIG_XILINX_LL_TEMAC_CLK CONFIG_XILINX_SPI_IDLE_VAL CONFIG_XILINX_TB_WATCHDOG -CONFIG_XPEDITE5140 -CONFIG_XPEDITE5200 -CONFIG_XPEDITE550X CONFIG_XR16L2751 CONFIG_XSENGINE CONFIG_XTFPGA diff --git a/tools/omapimage.c b/tools/omapimage.c index e7c46388f4..01e02649e1 100644 --- a/tools/omapimage.c +++ b/tools/omapimage.c @@ -145,7 +145,7 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, toc++; memset(toc, 0xff, sizeof(*toc)); - gph_set_header(gph, sbuf->st_size - OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE, + gph_set_header(gph, sbuf->st_size - OMAP_CH_HDR_SIZE, params->addr, 0); if (strncmp(params->imagename, "byteswap", 8) == 0) { |