diff options
256 files changed, 8658 insertions, 4824 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 95fc68906b..f59dc40f3e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,12 +2,12 @@ # Grab our configured image. The source for this is found at: # https://gitlab.denx.de/u-boot/gitlab-ci-runner -image: trini/u-boot-gitlab-ci-runner:xenial-20190720-24Jul2019 +image: trini/u-boot-gitlab-ci-runner:xenial-20190720-29Jul2019 # We run some tests in different order, to catch some failures quicker. stages: - - test.py - testsuites + - test.py - world build .buildman_and_testpy_template: &buildman_and_testpy_dfn @@ -28,17 +28,9 @@ stages: - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di ) - mkdir ~/grub2-arm64 - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di ) - - if [[ "${QEMU_TARGET}" != "" ]]; then - git clone git://git.qemu.org/qemu.git /tmp/qemu; - pushd /tmp/qemu; - git submodule update --init dtc && - git checkout ${QEMU_VERSION} && - ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} && - make -j$(nproc) all install; - popd; - fi + after_script: - - rm -rf ~/grub2* /tmp/uboot-test-hooks /tmp/qemu /tmp/venv + - rm -rf ~/grub2* /tmp/uboot-test-hooks /tmp/venv script: # From buildman, exit code 129 means warnings only. If we've been asked to # use clang only do one configuration. @@ -55,7 +47,7 @@ stages: # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom # value. - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD}; - export PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin; + export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin; export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; if [[ "${TEST_PY_BD}" != "" ]]; then ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID} @@ -203,8 +195,6 @@ evb-ast2500 test.py: variables: TEST_PY_BD: "evb-ast2500" TEST_PY_ID: "--id qemu" - QEMU_TARGET: "arm-softmmu" - QEMU_VERSION: "506179e42112be77bfd071f050b15762d3b2cd43" BUILDMAN: "^evb-ast2500$" <<: *buildman_and_testpy_dfn @@ -220,8 +210,6 @@ vexpress_ca15_tc2 test.py: variables: TEST_PY_BD: "vexpress_ca15_tc2" TEST_PY_ID: "--id qemu" - QEMU_TARGET: "arm-softmmu" - QEMU_VERSION: "v3.0.0" BUILDMAN: "^vexpress_ca15_tc2$" <<: *buildman_and_testpy_dfn @@ -230,7 +218,6 @@ vexpress_ca9x4 test.py: variables: TEST_PY_BD: "vexpress_ca9x4" TEST_PY_ID: "--id qemu" - QEMU_TARGET: "arm-softmmu" BUILDMAN: "^vexpress_ca9x4$" <<: *buildman_and_testpy_dfn @@ -240,7 +227,6 @@ integratorcp_cm926ejs test.py: TEST_PY_BD: "integratorcp_cm926ejs" TEST_PY_TEST_SPEC: "not sleep" TEST_PY_ID: "--id qemu" - QEMU_TARGET: "arm-softmmu" BUILDMAN: "^integratorcp_cm926ejs$" <<: *buildman_and_testpy_dfn @@ -249,7 +235,6 @@ qemu_arm test.py: variables: TEST_PY_BD: "qemu_arm" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "arm-softmmu" BUILDMAN: "^qemu_arm$" <<: *buildman_and_testpy_dfn @@ -258,7 +243,6 @@ qemu_arm64 test.py: variables: TEST_PY_BD: "qemu_arm64" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "aarch64-softmmu" BUILDMAN: "^qemu_arm64$" <<: *buildman_and_testpy_dfn @@ -267,7 +251,6 @@ qemu_mips test.py: variables: TEST_PY_BD: "qemu_mips" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "mips-softmmu" BUILDMAN: "^qemu_mips$" TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn @@ -277,7 +260,6 @@ qemu_mipsel test.py: variables: TEST_PY_BD: "qemu_mipsel" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "mipsel-softmmu" BUILDMAN: "^qemu_mipsel$" TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn @@ -287,7 +269,6 @@ qemu_mips64 test.py: variables: TEST_PY_BD: "qemu_mips64" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "mips64-softmmu" BUILDMAN: "^qemu_mips64$" TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn @@ -297,7 +278,6 @@ qemu_mips64el test.py: variables: TEST_PY_BD: "qemu_mips64el" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "mips64el-softmmu" BUILDMAN: "^qemu_mips64el$" TOOLCHAIN: "mips" <<: *buildman_and_testpy_dfn @@ -307,7 +287,6 @@ qemu-ppce500 test.py: variables: TEST_PY_BD: "qemu-ppce500" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "ppc-softmmu" BUILDMAN: "^qemu-ppce500$" TOOLCHAIN: "powerpc" <<: *buildman_and_testpy_dfn @@ -317,7 +296,6 @@ qemu-x86 test.py: variables: TEST_PY_BD: "qemu-x86" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "i386-softmmu" BUILDMAN: "^qemu-x86$" TOOLCHAIN: "i386" <<: *buildman_and_testpy_dfn @@ -327,7 +305,6 @@ qemu-x86_64 test.py: variables: TEST_PY_BD: "qemu-x86_64" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "x86_64-softmmu" BUILDMAN: "^qemu-x86_64$" TOOLCHAIN: "i386" <<: *buildman_and_testpy_dfn @@ -337,7 +314,6 @@ zynq_zc702 test.py: variables: TEST_PY_BD: "zynq_zc702" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "arm-softmmu" TEST_PY_ID: "--id qemu" BUILDMAN: "^zynq_zc702$" <<: *buildman_and_testpy_dfn @@ -347,7 +323,6 @@ xilinx_versal_virt test.py: variables: TEST_PY_BD: "xilinx_versal_virt" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "aarch64-softmmu" TEST_PY_ID: "--id qemu" BUILDMAN: "^xilinx_versal_virt$" <<: *buildman_and_testpy_dfn @@ -357,7 +332,6 @@ xtfpga test.py: variables: TEST_PY_BD: "xtfpga" TEST_PY_TEST_SPEC: "not sleep" - QEMU_TARGET: "xtensa-softmmu" TEST_PY_ID: "--id qemu" BUILDMAN: "^xtfpga$" TOOLCHAIN: "xtensa-dc233c-elf" diff --git a/MAINTAINERS b/MAINTAINERS index 4285d56626..c28251e698 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -94,6 +94,7 @@ M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> S: Maintainted T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git F: arch/arm/mach-socfpga/ +F: drivers/sysreset/sysreset_socfpga* ARM AMLOGIC SOC SUPPORT M: Neil Armstrong <narmstrong@baylibre.com> @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ VERSION = 2019 -PATCHLEVEL = 07 +PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = # *DOCUMENTATION* @@ -936,13 +936,6 @@ ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy) endif endif endif -ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y) - @echo >&2 "===================== WARNING ======================" - @echo >&2 "This board uses CONFIG_DM_I2C_COMPAT. Please remove" - @echo >&2 "(possibly in a subsequent patch in your series)" - @echo >&2 "before sending patches to the mailing list." - @echo >&2 "====================================================" -endif ifeq ($(CONFIG_MMC),y) ifneq ($(CONFIG_DM_MMC)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy) @echo >&2 "===================== WARNING ======================" @@ -1196,9 +1189,10 @@ u-boot.ldr: u-boot # --------------------------------------------------------------------------- # Use 'make BINMAN_DEBUG=1' to enable debugging quiet_cmd_binman = BINMAN $@ -cmd_binman = $(srctree)/tools/binman/binman build -u -d u-boot.dtb -O . -m \ +cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \ + build -u -d u-boot.dtb -O . -m \ -I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \ - $(if $(BINMAN_DEBUG),-D) $(BINMAN_$(@F)) + $(BINMAN_$(@F)) OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex @@ -212,7 +212,7 @@ board. This allows feature development which is not board- or architecture- specific to be undertaken on a native platform. The sandbox is also used to run some of U-Boot's tests. -See board/sandbox/README.sandbox for more details. +See doc/arch/index.rst for more details. Board Initialisation Flow: diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1cd7aeb7da..3f0e301d41 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -895,10 +895,14 @@ config ARCH_SOCFPGA select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 select SPL_SERIAL_SUPPORT + select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT select SUPPORT_SPL select SYS_NS16550 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYSRESET + select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 49d1faef32..aa94c49f37 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -240,6 +240,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo-z7.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ avnet-ultra96-rev1.dtb \ + avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ @@ -253,10 +254,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu104-revC.dtb \ zynqmp-zcu106-revA.dtb \ zynqmp-zcu111-revA.dtb \ + zynqmp-zcu1275-revA.dtb \ + zynqmp-zcu1275-revB.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ - zynqmp-zc1275-revA.dtb \ - zynqmp-zc1275-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm017-dc3.dtb \ @@ -778,7 +779,8 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ - mt7629-rfb.dtb + mt7629-rfb.dtb \ + mt8516-pumpkin.dtb dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts new file mode 100644 index 0000000000..ac641ff1a5 --- /dev/null +++ b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/* + * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM) + * http://ultrazed.org/product/ultrazed-ev-carrier-card + */ + +/dts-v1/; + +#include "avnet-ultrazedev-som-v1.0.dtsi" + +/ { + model = "Avnet UltraZed EV Carrier Card v1.0"; + compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0", + "xlnx,zynqmp"; + chosen { + stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; + }; + aliases { + ethernet0 = &gem3; + serial0 = &uart0; + }; +}; + +&uart0 { + device_type = "serial"; + status = "okay"; +}; + +&i2c_cc { + /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */ + eeprom: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + }; + + /* IDT Versa Clock 5P49V5935B */ + vc5: clock-generator@6a { + compatible = "idt,5p49v5935"; + reg = <0x6a>; + #clock-cells = <1>; + }; +}; + +/* Ethernet RJ-45 */ +&gem3 { + status = "okay"; +}; + +/* microSD card slot */ +&sdhci1 { + status = "okay"; + xlnx,mio_bank = <1>; + clock-frequency = <199998000>; + max-frequency = <50000000>; + no-1-8-v; + disable-wp; +}; diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi new file mode 100644 index 0000000000..b635db649f --- /dev/null +++ b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 + +/* + * UltraZed-EV SoM v1 + * http://ultrazed.org/product/ultrazed-ev + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "Avnet UltraZed EV SoM v1.0"; + compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp"; + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */ + <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */ + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + i2cswitch@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + /* I2C connected to Carrier Card via JX3A1/JX3C1 */ + i2c_cc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */ +&gem3 { + phy-mode = "rgmii-id"; + phy-handle = <&gem3phy>; + gem3phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */ +&sdhci0 { + status = "okay"; + xlnx,mio_bank = <0>; + clock-frequency = <199998000>; +}; diff --git a/arch/arm/dts/da850-evm-u-boot.dtsi b/arch/arm/dts/da850-evm-u-boot.dtsi index 1683f3472e..d9e8b9926a 100644 --- a/arch/arm/dts/da850-evm-u-boot.dtsi +++ b/arch/arm/dts/da850-evm-u-boot.dtsi @@ -10,6 +10,10 @@ soc@1c00000 { u-boot,dm-spl; }; + + nand { + compatible = "ti,davinci-nand"; + }; }; &flash { diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi index 80dda8ef58..541f4ca200 100644 --- a/arch/arm/dts/da850-lcdk-u-boot.dtsi +++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi @@ -9,4 +9,8 @@ aliases { i2c0 = &i2c0; }; + + nand { + compatible = "ti,davinci-nand"; + }; }; diff --git a/arch/arm/dts/mt8516-pumpkin.dts b/arch/arm/dts/mt8516-pumpkin.dts new file mode 100644 index 0000000000..cd43c1f5e3 --- /dev/null +++ b/arch/arm/dts/mt8516-pumpkin.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2019 BayLibre SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +/dts-v1/; + +#include <config.h> +#include "mt8516.dtsi" + +/ { + model = "Pumpkin MT8516"; + + chosen { + stdout-path = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x20000>; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; + +&pinctrl { + mmc0_pins_default: mmc0default { + mux { + function = "msdc"; + groups = "msdc0"; + }; + + conf-cmd-data { + pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1", + "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4", + "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC0_CLK"; + bias-pull-down; + }; + + conf-rst { + pins = "MSDC0_RSTB"; + bias-pull-up; + }; + }; + + uart0_pins: uart0 { + mux { + function = "uart"; + groups = "uart0_0_rxd_txd"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index abeac30593..097538cc4b 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -462,6 +462,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a7795-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a7795-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -1836,7 +1906,7 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts index b4f9567cb9..2aefa53cb1 100644 --- a/arch/arm/dts/r8a7796-salvator-x.dts +++ b/arch/arm/dts/r8a7796-salvator-x.dts @@ -68,6 +68,7 @@ ports { /* rsnd_port0 is on salvator-common */ rsnd_port1: port@1 { + reg = <1>; rsnd_endpoint1: endpoint { remote-endpoint = <&dw_hdmi0_snd_in>; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index cdf784899c..d5e2f4af83 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -1775,7 +1775,7 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2162,17 +2162,6 @@ dma-names = "rx", "tx"; }; }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - }; }; audma0: dma-controller@ec700000 { diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 9763d108e1..2554b1742d 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -317,6 +317,76 @@ reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a77965-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77965-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a77965-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a77965-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77965-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -1461,7 +1531,7 @@ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -1585,56 +1655,267 @@ }; }; + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + rcar_sound,ssi { ssi0: ssi-0 { interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; }; ssi1: ssi-1 { interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; }; ssi2: ssi-2 { interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; }; ssi3: ssi-3 { interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; }; ssi4: ssi-4 { interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; }; ssi5: ssi-5 { interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; }; ssi6: ssi-6 { interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; }; ssi7: ssi-7 { interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; }; ssi8: ssi-8 { interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; }; ssi9: ssi-9 { interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; }; }; }; @@ -2166,7 +2447,6 @@ du: display@feb00000 { compatible = "renesas,du-r8a77965"; reg = <0 0xfeb00000 0 0x80000>; - reg-names = "du"; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 144c0820cf..c727725899 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the ebisu board * @@ -19,7 +19,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -337,6 +337,15 @@ &i2c0 { status = "okay"; + io_expander: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + }; + hdmi-encoder@39 { compatible = "adi,adv7511w"; reg = <0x39>; @@ -398,7 +407,7 @@ }; port@a { - reg = <0xa>; + reg = <10>; adv7482_txa: endpoint { clock-lanes = <0>; @@ -440,6 +449,28 @@ }; }; +&i2c_dvfs { + status = "okay"; + + clock-frequency = <400000>; + + pmic: pmic@30 { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + rohm,ddr-backup-power = <0x1>; + rohm,rstbmode-level; + }; +}; + &lvds0 { status = "okay"; @@ -458,6 +489,13 @@ }; &lvds1 { + /* + * Even though the LVDS1 output is not connected, the encoder must be + * enabled to supply a pixel clock to the DU for the DPAD output when + * LVDS0 is in use. + */ + status = "okay"; + clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; @@ -495,6 +533,11 @@ function = "du"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + pwm3_pins: pwm3 { groups = "pwm3_b"; function = "pwm3"; @@ -650,6 +693,10 @@ status = "okay"; }; +&vin5 { + status = "okay"; +}; + &xhci0 { pinctrl-0 = <&usb30_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index d2ad665fe2..56cb566ffa 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the R-Car E3 (R8A77990) SoC * @@ -284,6 +284,76 @@ status = "disabled"; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a77990-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77990-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a77990-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a77990-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77990-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -1656,7 +1726,7 @@ }; csi40: csi2@feaa0000 { - compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; + compatible = "renesas,r8a77990-csi2"; reg = <0 0xfeaa0000 0 0x10000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 716>; diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts index db2bed1751..a7dc11e36f 100644 --- a/arch/arm/dts/r8a77995-draak.dts +++ b/arch/arm/dts/r8a77995-draak.dts @@ -20,7 +20,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -168,7 +168,6 @@ pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; status = "okay"; phy0: ethernet-phy@0 { @@ -179,6 +178,18 @@ }; }; +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &du { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; @@ -356,6 +367,13 @@ }; &lvds1 { + /* + * Even though the LVDS1 output is not connected, the encoder must be + * enabled to supply a pixel clock to the DU for the DPAD output when + * LVDS0 is in use. + */ + status = "okay"; + clocks = <&cpg CPG_MOD 727>, <&x12_clk>, <&extal_clk>; @@ -375,6 +393,16 @@ }; }; + can0_pins: can0 { + groups = "can0_data_a"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data_a"; + function = "can1"; + }; + du_pins: du { groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; function = "du"; diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts index f2bb7b5f11..cc3921095c 100644 --- a/arch/arm/dts/rk3288-phycore-rdk.dts +++ b/arch/arm/dts/rk3288-phycore-rdk.dts @@ -55,11 +55,6 @@ stdout-path = &uart2; }; - config { - u-boot,dm-pre-reloc; - u-boot,boot0 = &emmc; - }; - user_buttons: user-buttons { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 916dd486de..8754043b9b 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -16,11 +16,7 @@ chosen { stdout-path = &uart2; - }; - - config { - u-boot,dm-pre-reloc; - u-boot,boot0 = &spi_flash; + u-boot,spl-boot-order = &spi_flash; }; firmware { diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index a225c24572..2dba1328ac 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -29,6 +29,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> / { aliases { @@ -86,6 +87,63 @@ }; }; + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "SW4-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-2 { + gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "SW4-2"; + wakeup-source; + debounce-interval = <20>; + }; + key-3 { + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW4-3"; + wakeup-source; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_4>; + label = "SW4-4"; + wakeup-source; + debounce-interval = <20>; + }; + key-a { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_A>; + label = "TSW0"; + wakeup-source; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_B>; + label = "TSW1"; + wakeup-source; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + linux,code = <KEY_C>; + label = "TSW2"; + wakeup-source; + debounce-interval = <20>; + }; + }; + reg_1p8v: regulator0 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -572,6 +630,11 @@ function = "intc_ex"; }; + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22"; + bias-pull-up; + }; + pwm1_pins: pwm1 { groups = "pwm1_a"; function = "pwm1"; @@ -719,6 +782,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; @@ -857,11 +925,6 @@ status = "okay"; }; -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - &xhci0 { pinctrl-0 = <&usb30_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 82c30a3fbe..c22de576a5 100644 --- a/arch/arm/dts/zynqmp-zc1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * dts file for Xilinx ZynqMP ZC1275 + * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017 - 2018, Xilinx, Inc. * @@ -14,8 +14,9 @@ #include "zynqmp-clk-ccf.dtsi" / { - model = "ZynqMP ZC1275 RevA"; - compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + model = "ZynqMP ZCU1275 RevA"; + compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", + "xlnx,zynqmp"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 0473503afa..34c4becd43 100644 --- a/arch/arm/dts/zynqmp-zc1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP ZC1275 RevB + * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018, Xilinx, Inc. * @@ -14,8 +14,9 @@ #include "zynqmp-clk-ccf.dtsi" / { - model = "ZynqMP ZC1275 RevB"; - compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + model = "ZynqMP ZCU1275 RevB"; + compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", + "xlnx,zynqmp"; aliases { serial0 = &uart0; diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index d67f43f09c..0da78f30b6 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -52,9 +52,11 @@ enum { BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB }; +extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; + /** * Locations of the boot-device identifier in SRAM */ -#define RK3399_BROM_BOOTSOURCE_ID_ADDR 0xff8c0010 +#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10) #endif diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 905c774c15..de5a8f11a9 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -6,8 +6,4 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H - -/* provided to defeat compiler optimisation in board_init_f() */ -void gru_dummy_function(int i); - #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index e26381c7fd..28842c3b15 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -95,6 +95,4 @@ struct davinci_emif_regs { #define DAVINCI_ABCR_ASIZE_16BIT 1 #define DAVINCI_ABCR_ASIZE_8BIT 0 -void davinci_nand_init(struct nand_chip *nand); - #endif diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index 51af028590..cc2ec88505 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * K2HK: secure kernel command file + * K2x: Secure commands file * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> + * Copyright (C) 2012-2019 Texas Instruments Incorporated - http://www.ti.com/ */ +#include <asm/unaligned.h> #include <common.h> #include <command.h> #include <mach/mon.h> @@ -120,9 +120,9 @@ void board_fit_image_post_process(void **p_image, size_t *p_size) /* * Overwrite the image headers after authentication * and decryption. Update size to reflect removal - * of header. + * of header and restore original file size. */ - *p_size -= KS2_HS_SEC_HEADER_LEN; + *p_size = get_unaligned_le32(image + (*p_size - 4)); memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size); /* diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 60aef15f15..25ef7651f0 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -42,5 +42,6 @@ endchoice source "board/mediatek/mt7623/Kconfig" source "board/mediatek/mt7629/Kconfig" +source "board/mediatek/pumpkin/Kconfig" endif diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index aafeb355ef..52ab891425 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -21,6 +21,7 @@ config RCAR_GEN3 imply CMD_GPT imply CMD_UUID imply CMD_MMC_SWRITE if MMC + imply OF_BOARD_SETUP if PCI imply SUPPORT_EMMC_RPMB if MMC imply SPL imply SPL_BOARD_INIT diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 17f31e89f3..e337d06b99 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -7,6 +7,7 @@ config ROCKCHIP_RK3036 select SPL imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB + imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -16,6 +17,7 @@ config ROCKCHIP_RK3036 config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A + imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -34,8 +36,10 @@ config ROCKCHIP_RK3188 select SPL_RAM select SPL_DRIVERS_MISC_SUPPORT select SPL_ROCKCHIP_EARLYRETURN_TO_BROM + select SPL_ROCKCHIP_BACK_TO_BROM select BOARD_LATE_INIT - select ROCKCHIP_BROM_HELPER + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two @@ -57,11 +61,11 @@ config ROCKCHIP_RK322X select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_DRIVERS_MISC_SUPPORT + imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL_SUPPORT + imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL_SUPPORT - imply TPL_BOOTROM_SUPPORT imply TPL_ROCKCHIP_COMMON_BOARD - select ROCKCHIP_BROM_HELPER select TPL_LIBCOMMON_SUPPORT select TPL_LIBGENERIC_SUPPORT help @@ -73,11 +77,11 @@ config ROCKCHIP_RK322X config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A - select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL select SUPPORT_TPL - imply TPL_BOOTROM_SUPPORT + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_CLK imply TPL_DM imply TPL_DRIVERS_MISC_SUPPORT @@ -106,6 +110,8 @@ config ROCKCHIP_RK3328 select ARM64 select SUPPORT_SPL select SPL + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SERIAL_SUPPORT imply SPL_SEPARATE_BSS select ENABLE_ARM_SOC_BOOT0_HOOK @@ -125,6 +131,8 @@ config ROCKCHIP_RK3368 select SUPPORT_TPL select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL select TPL_NEEDS_SEPARATE_STACK if TPL + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT @@ -169,12 +177,12 @@ config ROCKCHIP_RK3399 select DM_PMIC select DM_REGULATOR_FIXED select BOARD_LATE_INIT - select ROCKCHIP_BROM_HELPER + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD imply TPL_SERIAL_SUPPORT imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE - imply TPL_BOOTROM_SUPPORT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_OF_CONTROL imply TPL_DM @@ -195,6 +203,7 @@ config ROCKCHIP_RK3399 config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A + imply ROCKCHIP_COMMON_BOARD help The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. @@ -211,6 +220,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 select ROCKCHIP_BROM_HELPER + select SPL_BOOTROM_SUPPORT depends on SPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, @@ -221,12 +231,28 @@ config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" default y select ROCKCHIP_BROM_HELPER + select TPL_BOOTROM_SUPPORT depends on TPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. +config ROCKCHIP_COMMON_BOARD + bool "Rockchip common board file" + help + Rockchip SoCs have similar boot process, Common board file is mainly + in charge of common process of board_init() and board_late_init() for + U-Boot proper. + +config SPL_ROCKCHIP_COMMON_BOARD + bool "Rockchip SPL common board file" + depends on SPL + help + Rockchip SoCs have similar boot process, SPL is mainly in charge of + load and boot Trust ATF/U-Boot firmware, and DRAM init if there is + no TPL for the board. + config TPL_ROCKCHIP_COMMON_BOARD bool "" depends on TPL diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index a12b8d4434..aed379a0dc 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -7,16 +7,11 @@ # inaccessible/protected memory (and the bootrom-helper assumes that # the stack-pointer is valid before switching to the U-Boot stack). obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o +obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o -obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o spl-boot-order.o -obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o -obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) @@ -25,14 +20,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o - -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o -obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board.o -obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108-board.o +obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o endif obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/board.c index c594c4d61c..b2a88e789d 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/board.c @@ -1,19 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. */ - #include <common.h> #include <clk.h> #include <dm.h> #include <ram.h> -#include <asm/gpio.h> +#include <syscon.h> #include <asm/io.h> +#include <asm/arch-rockchip/boot_mode.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/grf_rk3036.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <asm/arch-rockchip/sdram_rk3036.h> +#include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,23 +29,18 @@ int board_late_init(void) int board_init(void) { - return 0; -} + int ret; -#if !CONFIG_IS_ENABLED(RAM) -/* - * When CONFIG_RAM is enabled, the dram_init() function is implemented - * in sdram_common.c. - */ -int dram_init(void) -{ - gd->ram_size = sdram_size(); +#ifdef CONFIG_DM_REGULATOR + ret = regulators_enable_boot_on(false); + if (ret) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif return 0; } -#endif -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ @@ -59,7 +52,7 @@ void enable_caches(void) #include <usb.h> #include <usb/dwc2_udc.h> -static struct dwc2_plat_otg_data rk3036_otg_data = { +static struct dwc2_plat_otg_data otg_data = { .rx_fifo_sz = 512, .np_tx_fifo_sz = 16, .tx_fifo_sz = 128, @@ -73,8 +66,7 @@ int board_usb_init(int index, enum usb_init_type init) const void *blob = gd->fdt_blob; /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); + node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); while (node > 0) { mode = fdt_getprop(blob, node, "dr_mode", NULL); @@ -83,16 +75,15 @@ int board_usb_init(int index, enum usb_init_type init) break; } - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); + node = fdt_node_offset_by_compatible(blob, node, "snps,dwc2"); } if (!matched) { debug("Not found usb_otg device\n"); return -ENODEV; } - rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - return dwc2_udc_probe(&rk3036_otg_data); + return dwc2_udc_probe(&otg_data); } int board_usb_cleanup(int index, enum usb_init_type init) @@ -100,3 +91,14 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif + +#if CONFIG_IS_ENABLED(FASTBOOT) +int fastboot_set_reboot_flag(void) +{ + printf("Setting reboot to fastboot flag ...\n"); + /* Set boot mode to fastboot */ + writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/fit_spl_optee.its b/arch/arm/mach-rockchip/fit_spl_optee.its index 9be4b3c8d2..6ed5d486f2 100644 --- a/arch/arm/mach-rockchip/fit_spl_optee.its +++ b/arch/arm/mach-rockchip/fit_spl_optee.its @@ -11,7 +11,7 @@ #address-cells = <1>; images { - uboot@1 { + uboot { description = "U-Boot"; data = /incbin/("../../../u-boot-nodtb.bin"); type = "standalone"; @@ -20,7 +20,7 @@ compression = "none"; load = <0x61000000>; }; - optee@1 { + optee { description = "OP-TEE"; data = /incbin/("../../../tee.bin"); type = "firmware"; @@ -30,7 +30,7 @@ load = <0x68400000>; entry = <0x68400000>; }; - fdt@1 { + fdt { description = "dtb"; data = /incbin/("../../../u-boot.dtb"); type = "flat_dt"; @@ -39,12 +39,12 @@ }; configurations { - default = "conf@1"; - conf@1 { + default = "conf"; + conf { description = "Rockchip armv7 with OP-TEE"; - firmware = "optee@1"; - loadables = "uboot@1"; - fdt = "fdt@1"; + firmware = "optee"; + loadables = "uboot"; + fdt = "fdt"; }; }; }; diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c index 481af8a934..be458cfb64 100644 --- a/arch/arm/mach-rockchip/rk3036/rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -5,6 +5,9 @@ #include <asm/io.h> #include <asm/arch-rockchip/grf_rk3036.h> #include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) @@ -36,3 +39,16 @@ void board_debug_uart_init(void) GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); } #endif + +#if !CONFIG_IS_ENABLED(RAM) +/* + * When CONFIG_RAM is enabled, the dram_init() function is implemented + * in sdram_common.c. + */ +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c deleted file mode 100644 index 0945829d0e..0000000000 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/grf_rk3128.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <power/regulator.h> - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - setup_boot_mode(); - - return rk_board_late_init(); -} - -int board_init(void) -{ - int ret = 0; - - ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulator\n", __func__); - return ret; - } - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; - /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0xe00000; - gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start - + gd->ram_size - gd->bd->bi_dram[1].start; - - return 0; -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rk3128_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3128-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3128-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3128_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -#if CONFIG_IS_ENABLED(FASTBOOT) -int fastboot_set_reboot_flag(void) -{ - struct rk3128_grf *grf; - - printf("Setting reboot to fastboot flag ...\n"); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - /* Set boot mode to fastboot */ - writel(BOOT_FASTBOOT, &grf->os_reg[0]); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c index 11bba148c3..ee176de80b 100644 --- a/arch/arm/mach-rockchip/rk3128/rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/rk3128.c @@ -2,6 +2,9 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; int arch_cpu_init(void) { diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c deleted file mode 100644 index c3efe0d7a9..0000000000 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <clk.h> -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <fdtdec.h> -#include <led.h> -#include <malloc.h> -#include <ram.h> -#include <spl.h> -#include <syscon.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk3188.h> -#include <asm/arch-rockchip/hardware.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3188.h> -#include <asm/arch-rockchip/sdram.h> -#include <dm/root.h> -#include <dm/test.h> -#include <dm/util.h> -#include <power/regulator.h> - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - const void *blob = gd->fdt_blob; - struct udevice *dev; - const char *bootdev; - int node; - int ret; - - bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); - debug("Boot device %s\n", bootdev); - if (!bootdev) - goto fallback; - - node = fdt_path_offset(blob, bootdev); - if (node < 0) { - debug("node=%d\n", node); - goto fallback; - } - ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev); - if (ret) { - debug("device at node %s/%d not found: %d\n", bootdev, node, - ret); - goto fallback; - } - debug("Found device %s\n", dev->name); - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("Booting from device uclass '%s' not supported\n", - dev_get_uclass_name(dev)); - } - -fallback: -#endif - return BOOT_DEVICE_MMC1; -} - -static int setup_arm_clock(void) -{ - struct udevice *dev; - struct clk clk; - int ret; - - ret = rockchip_get_clk(&dev); - if (ret) - return ret; - - clk.id = CLK_ARM; - ret = clk_request(dev, &clk); - if (ret < 0) - return ret; - - ret = clk_set_rate(&clk, 600000000); - - clk_free(&clk); - return ret; -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("U-Boot SPL board init"); -#endif - -#ifdef CONFIG_ROCKCHIP_USB_UART - rk_clrsetreg(&grf->uoc0_con[0], - SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, - 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | - 1 << COMMON_ON_N_SHIFT); - rk_clrsetreg(&grf->uoc0_con[2], - SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); - rk_clrsetreg(&grf->uoc0_con[3], - OPMODE_MASK | XCVRSELECT_MASK | - TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, - OPMODE_NODRIVING << OPMODE_SHIFT | - XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | - 1 << TERMSEL_FULLSPEED_SHIFT | - 1 << SUSPENDN_SHIFT); - rk_clrsetreg(&grf->uoc0_con[0], - BYPASSSEL_MASK | BYPASSDMEN_MASK, - 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } - - setup_arm_clock(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} - -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_on(dev, 1); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - int ret; - - ret = setup_led(); - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } - - preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif - return; -} diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c deleted file mode 100644 index 94fd6c01eb..0000000000 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk3188.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3288.h> -#include <asm/arch-rockchip/boot_mode.h> - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - struct rk3188_grf *grf; - - setup_boot_mode(); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - if (IS_ERR(grf)) { - pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); - } else { - /* enable noc remap to mimic legacy loaders */ - rk_clrsetreg(&grf->soc_con0, - NOC_REMAP_MASK << NOC_REMAP_SHIFT, - NOC_REMAP_MASK << NOC_REMAP_SHIFT); - } - - return rk_board_late_init(); -} - -int board_init(void) -{ - return 0; -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 933484e0df..95f0e3ccbe 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -3,15 +3,25 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ #include <common.h> +#include <dm.h> +#include <syscon.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/grf_rk3188.h> #include <asm/arch-rockchip/hardware.h> +#define GRF_BASE 0x20008000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@1021c000", + [BROM_BOOTSOURCE_SD] = "dwmmc@10214000", +}; + #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; enum { GPIO1B1_SHIFT = 2, @@ -34,3 +44,77 @@ void board_debug_uart_init(void) GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); } #endif + +#ifdef CONFIG_SPL_BUILD +int arch_cpu_init(void) +{ + struct rk3188_grf *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(grf)) { + pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); + return 0; + } +#ifdef CONFIG_ROCKCHIP_USB_UART + rk_clrsetreg(&grf->uoc0_con[0], + SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK, + 1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT | + 1 << COMMON_ON_N_SHIFT); + rk_clrsetreg(&grf->uoc0_con[2], + SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT); + rk_clrsetreg(&grf->uoc0_con[3], + OPMODE_MASK | XCVRSELECT_MASK | + TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK, + OPMODE_NODRIVING << OPMODE_SHIFT | + XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT | + 1 << TERMSEL_FULLSPEED_SHIFT | + 1 << SUSPENDN_SHIFT); + rk_clrsetreg(&grf->uoc0_con[0], + BYPASSSEL_MASK | BYPASSDMEN_MASK, + 1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT); +#endif + + /* enable noc remap to mimic legacy loaders */ + rk_clrsetreg(&grf->soc_con0, + NOC_REMAP_MASK << NOC_REMAP_SHIFT, + NOC_REMAP_MASK << NOC_REMAP_SHIFT); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static int setup_led(void) +{ +#ifdef CONFIG_SPL_LED + struct udevice *dev; + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + ret = led_set_on(dev, 1); + if (ret) + return ret; +#endif + + return 0; +} + +void spl_board_init(void) +{ + int ret; + + ret = setup_led(); + if (ret) { + debug("LED ret=%d\n", ret); + hang(); + } +} +#endif diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c deleted file mode 100644 index c825e31c02..0000000000 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <dm.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch-rockchip/hardware.h> - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -u32 spl_boot_mode(const u32 boot_device) -{ - return MMCSD_MODE_RAW; -} - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -void rockchip_stimer_init(void) -{ - /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - - if (reg & TIMER_EN) - return; - - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} - -#define SGRF_DDR_CON0 0x10150000 -void board_init_f(ulong dummy) -{ - int ret; - - ret = spl_early_init(); - if (ret) { - printf("spl_early_init() failed: %d\n", ret); - hang(); - } - preloader_console_init(); - - /* Init secure timer */ - rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ - timer_init(); - - /* Disable the ddr secure region setting to make it non-secure */ - rk_clrreg(SGRF_DDR_CON0, 0x4000); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c deleted file mode 100644 index e7a1e54874..0000000000 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - */ -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk322x.h> -#include <asm/arch-rockchip/periph.h> - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int board_late_init(void) -{ - setup_boot_mode(); - - return rk_board_late_init(); -} - -int board_init(void) -{ -#include <asm/arch-rockchip/grf_rk322x.h> - /* Enable early UART2 channel 1 on the RK322x */ -#define GRF_BASE 0x11000000 - static struct rk322x_grf * const grf = (void *)GRF_BASE; - - /* - * The integrated macphy is enabled by default, disable it - * for saving power consuming. - */ - rk_clrsetreg(&grf->macphy_con[0], - MACPHY_CFG_ENABLE_MASK, - 0 << MACPHY_CFG_ENABLE_SHIFT); - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; - /* Reserve 0x200000 for OPTEE */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x200000; - gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start - + gd->ram_size - gd->bd->bi_dram[1].start; - - return 0; -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rk322x_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk322x_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -#if CONFIG_IS_ENABLED(FASTBOOT) -int fastboot_set_reboot_flag(void) -{ - struct rk322x_grf *grf; - - printf("Setting reboot to fastboot flag ...\n"); - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - /* Set boot mode to fastboot */ - writel(BOOT_FASTBOOT, &grf->os_reg[0]); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index e5250bc784..cd0bf8a70c 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -3,9 +3,15 @@ * (C) Copyright 2019 Rockchip Electronics Co., Ltd */ #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_rk322x.h> #include <asm/arch-rockchip/hardware.h> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@30020000", + [BROM_BOOTSOURCE_SD] = "dwmmc@30000000", +}; + #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { @@ -42,3 +48,26 @@ void board_debug_uart_init(void) CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } #endif + +int arch_cpu_init(void) +{ +#ifdef CONFIG_SPL_BUILD +#define SGRF_BASE 0x10150000 + static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE; + + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(&sgrf->soc_con[0], 0x4000); +#else +#define GRF_BASE 0x11000000 + static struct rk322x_grf * const grf = (void *)GRF_BASE; + /* + * The integrated macphy is enabled by default, disable it + * for saving power consuming. + */ + rk_clrsetreg(&grf->macphy_con[0], + MACPHY_CFG_ENABLE_MASK, + 0 << MACPHY_CFG_ENABLE_SHIFT); + +#endif + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c deleted file mode 100644 index c2e168192c..0000000000 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <fdtdec.h> -#include <i2c.h> -#include <led.h> -#include <malloc.h> -#include <ram.h> -#include <spl.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/hardware.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3288.h> -#include <asm/arch-rockchip/sdram.h> -#include <asm/arch-rockchip/sdram_common.h> -#include <asm/arch-rockchip/sys_proto.h> -#include <dm/root.h> -#include <dm/test.h> -#include <dm/util.h> -#include <power/regulator.h> -#include <power/rk8xx_pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - const void *blob = gd->fdt_blob; - struct udevice *dev; - const char *bootdev; - int node; - int ret; - - bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); - debug("Boot device %s\n", bootdev); - if (!bootdev) - goto fallback; - - node = fdt_path_offset(blob, bootdev); - if (node < 0) { - debug("node=%d\n", node); - goto fallback; - } - ret = device_get_global_by_ofnode(offset_to_ofnode(node), &dev); - if (ret) { - debug("device at node %s/%d not found: %d\n", bootdev, node, - ret); - goto fallback; - } - debug("Found device %s\n", dev->name); - switch (device_get_uclass_id(dev)) { - case UCLASS_SPI_FLASH: - return BOOT_DEVICE_SPI; - case UCLASS_MMC: - return BOOT_DEVICE_MMC1; - default: - debug("Booting from device uclass '%s' not supported\n", - dev_get_uclass_name(dev)); - } - -fallback: -#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ - defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \ - defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) - return BOOT_DEVICE_SPI; -#endif - return BOOT_DEVICE_MMC1; -} - -#if !defined(CONFIG_SPL_OF_PLATDATA) -static int phycore_init(void) -{ - struct udevice *pmic; - int ret; - - ret = uclass_first_device_err(UCLASS_PMIC, &pmic); - if (ret) - return ret; - -#if defined(CONFIG_SPL_POWER_SUPPORT) - /* Increase USB input current to 2A */ - ret = rk818_spl_configure_usb_input_current(pmic, 2000); - if (ret) - return ret; - - /* Close charger when USB lower then 3.26V */ - ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); - if (ret) - return ret; -#endif - - return 0; -} -#endif - -__weak int arch_cpu_init(void) -{ - return 0; -} - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -void rockchip_stimer_init(void) -{ - /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - - if (reg & TIMER_EN) - return; - - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(COUNTER_FREQUENCY)); - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - -#ifdef CONFIG_DEBUG_UART - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - debug("\nspl:debug uart enabled in %s\n", __func__); -#endif - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Init secure timer */ - rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ - timer_init(); - - arch_cpu_init(); - - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return; - } - -#if !defined(CONFIG_SPL_OF_PLATDATA) - if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { - ret = phycore_init(); - if (ret) { - debug("Failed to set up phycore power settings: %d\n", - ret); - return; - } - } -#endif - -#if !defined(CONFIG_SUPPORT_TPL) - debug("\nspl:init dram\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -#endif - -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif -} - -static int setup_led(void) -{ -#ifdef CONFIG_SPL_LED - struct udevice *dev; - char *led_name; - int ret; - - led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); - if (!led_name) - return 0; - ret = led_get_by_label(led_name, &dev); - if (ret) { - debug("%s: get=%d\n", __func__, ret); - return ret; - } - ret = led_set_on(dev, 1); - if (ret) - return ret; -#endif - - return 0; -} - -void spl_board_init(void) -{ - int ret; - - ret = setup_led(); - if (ret) { - debug("LED ret=%d\n", ret); - hang(); - } - - preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -#endif - return; -} - -#ifdef CONFIG_SPL_OS_BOOT - -#define PMU_BASE 0xff730000 -int dram_init_banksize(void) -{ - struct rk3288_pmu *const pmu = (void *)PMU_BASE; - size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]); - - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = size; - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c deleted file mode 100644 index a250d50387..0000000000 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3288.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/pmu_rk3288.h> -#include <asm/arch-rockchip/qos_rk3288.h> -#include <asm/arch-rockchip/boot_mode.h> -#include <asm/gpio.h> -#include <dt-bindings/clock/rk3288-cru.h> -#include <power/regulator.h> - -DECLARE_GLOBAL_DATA_PTR; - -__weak int rk_board_late_init(void) -{ - return 0; -} - -int rk3288_qos_init(void) -{ - int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; - /* set vop qos to higher priority */ - writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); - - if (!fdt_node_check_compatible(gd->fdt_blob, 0, - "rockchip,rk3288-tinker")) - { - /* set isp qos to higher priority */ - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); - writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); - } - return 0; -} - -static void rk3288_detect_reset_reason(void) -{ - struct rk3288_cru *cru = rockchip_get_cru(); - const char *reason; - - if (IS_ERR(cru)) - return; - - switch (cru->cru_glb_rst_st) { - case GLB_POR_RST: - reason = "POR"; - break; - case FST_GLB_RST_ST: - case SND_GLB_RST_ST: - reason = "RST"; - break; - case FST_GLB_TSADC_RST_ST: - case SND_GLB_TSADC_RST_ST: - reason = "THERMAL"; - break; - case FST_GLB_WDT_RST_ST: - case SND_GLB_WDT_RST_ST: - reason = "WDOG"; - break; - default: - reason = "unknown reset"; - } - - env_set("reset_reason", reason); - - /* - * Clear cru_glb_rst_st, so we can determine the last reset cause - * for following resets. - */ - rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); -} - -int board_late_init(void) -{ - setup_boot_mode(); - rk3288_qos_init(); - rk3288_detect_reset_reason(); - - return rk_board_late_init(); -} - -#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) -static int veyron_init(void) -{ - struct udevice *dev; - struct clk clk; - int ret; - - ret = regulator_get_by_platname("vdd_arm", &dev); - if (ret) { - debug("Cannot set regulator name\n"); - return ret; - } - - /* Slowly raise to max CPU voltage to prevent overshoot */ - ret = regulator_set_value(dev, 1200000); - if (ret) - return ret; - udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ - ret = regulator_set_value(dev, 1400000); - if (ret) - return ret; - udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ - - ret = rockchip_get_clk(&clk.dev); - if (ret) - return ret; - clk.id = PLL_APLL; - ret = clk_set_rate(&clk, 1800000000); - if (IS_ERR_VALUE(ret)) - return ret; - - ret = regulator_get_by_platname("vcc33_sd", &dev); - if (ret) { - debug("Cannot get regulator name\n"); - return ret; - } - - ret = regulator_set_value(dev, 3300000); - if (ret) - return ret; - - ret = regulators_enable_boot_on(false); - if (ret) { - debug("%s: Cannot enable boot on regulators\n", __func__); - return ret; - } - - return 0; -} -#endif - -int board_init(void) -{ -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - return 0; -#else - int ret; - - /* We do some SoC one time setting here */ - if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { - ret = veyron_init(); - if (ret) - return ret; - } - - return 0; -#endif -} - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rk3288_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node, phy_node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - u32 grf_phy_offset; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3288-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - node = fdtdec_lookup_phandle(blob, node, "phys"); - if (node <= 0) { - debug("Not found usb phy device\n"); - return -ENODEV; - } - - phy_node = fdt_parent_offset(blob, node); - if (phy_node <= 0) { - debug("Not found usb phy device\n"); - return -ENODEV; - } - - rk3288_otg_data.phy_of_node = phy_node; - grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); - - /* find the grf node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3288-grf"); - if (node <= 0) { - debug("Not found grf device\n"); - return -ENODEV; - } - rk3288_otg_data.regs_phy = grf_phy_offset + - fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3288_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif - -static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - static const struct { - char *name; - int id; - } clks[] = { - { "osc", CLK_OSC }, - { "apll", CLK_ARM }, - { "dpll", CLK_DDR }, - { "cpll", CLK_CODEC }, - { "gpll", CLK_GENERAL }, -#ifdef CONFIG_ROCKCHIP_RK3036 - { "mpll", CLK_NEW }, -#else - { "npll", CLK_NEW }, -#endif - }; - int ret, i; - struct udevice *dev; - - ret = rockchip_get_clk(&dev); - if (ret) { - printf("clk-uclass not found\n"); - return 0; - } - - for (i = 0; i < ARRAY_SIZE(clks); i++) { - struct clk clk; - ulong rate; - - clk.id = clks[i].id; - ret = clk_request(dev, &clk); - if (ret < 0) - continue; - - rate = clk_get_rate(&clk); - printf("%s: %lu\n", clks[i].name, rate); - - clk_free(&clk); - } - - return 0; -} - -U_BOOT_CMD( - clock, 2, 1, do_clock, - "display information about clocks", - "" -); - -int board_early_init_f(void) -{ - const uintptr_t GRF_SOC_CON0 = 0xff770244; - const uintptr_t GRF_SOC_CON2 = 0xff77024c; - struct udevice *dev; - int ret; - - /* - * This init is done in SPL, but when chain-loading U-Boot SPL will - * have been skipped. Allow the clock driver to check if it needs - * setting up. - */ - ret = rockchip_get_clk(&dev); - if (ret) { - debug("CLK init failed: %d\n", ret); - return ret; - } - - rk_setreg(GRF_SOC_CON2, 1 << 0); - - /* - * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is - * cleared - */ - rk_clrreg(GRF_SOC_CON0, 1 << 12); - - return 0; -} diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index de8d9c24f1..87d0786ba8 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -66,6 +66,7 @@ config TARGET_FENNEC_RK3288 config TARGET_FIREFLY_RK3288 bool "Firefly-RK3288" select BOARD_LATE_INIT + select SPL_BOARD_INIT if SPL help Firefly is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It @@ -84,6 +85,7 @@ config TARGET_MIQI_RK3288 config TARGET_PHYCORE_RK3288 bool "phyCORE-RK3288" select BOARD_LATE_INIT + select SPL_BOARD_INIT if SPL help Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 7552472fbc..b462c09069 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -2,13 +2,29 @@ /* * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ +#include <common.h> +#include <dm.h> +#include <clk.h> #include <asm/armv7.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/qos_rk3288.h> +#include <asm/arch-rockchip/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xff770000 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000", +}; + #ifdef CONFIG_SPL_BUILD static void configure_l2ctlr(void) { @@ -30,6 +46,24 @@ static void configure_l2ctlr(void) } #endif +int rk3288_qos_init(void) +{ + int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; + /* set vop qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); + + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + "rockchip,rk3288-tinker")) { + /* set isp qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); + } + + return 0; +} + int arch_cpu_init(void) { #ifdef CONFIG_SPL_BUILD @@ -40,6 +74,14 @@ int arch_cpu_init(void) /* Use rkpwm by default */ rk_setreg(&grf->soc_con2, 1 << 0); + + /* + * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is + * cleared + */ + rk_clrreg(&grf->soc_con0, 1 << 12); + + rk3288_qos_init(); #endif return 0; @@ -57,3 +99,103 @@ void board_debug_uart_init(void) GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); } #endif + +static void rk3288_detect_reset_reason(void) +{ + struct rk3288_cru *cru = rockchip_get_cru(); + const char *reason; + + if (IS_ERR(cru)) + return; + + switch (cru->cru_glb_rst_st) { + case GLB_POR_RST: + reason = "POR"; + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + reason = "RST"; + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + reason = "THERMAL"; + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + reason = "WDOG"; + break; + default: + reason = "unknown reset"; + } + + env_set("reset_reason", reason); + + /* + * Clear cru_glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); +} + +__weak int rk3288_board_late_init(void) +{ + return 0; +} + +int rk_board_late_init(void) +{ + rk3288_detect_reset_reason(); + + return rk3288_board_late_init(); +} + +static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + static const struct { + char *name; + int id; + } clks[] = { + { "osc", CLK_OSC }, + { "apll", CLK_ARM }, + { "dpll", CLK_DDR }, + { "cpll", CLK_CODEC }, + { "gpll", CLK_GENERAL }, +#ifdef CONFIG_ROCKCHIP_RK3036 + { "mpll", CLK_NEW }, +#else + { "npll", CLK_NEW }, +#endif + }; + int ret, i; + struct udevice *dev; + + ret = rockchip_get_clk(&dev); + if (ret) { + printf("clk-uclass not found\n"); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(clks); i++) { + struct clk clk; + ulong rate; + + clk.id = clks[i].id; + ret = clk_request(dev, &clk); + if (ret < 0) + continue; + + rate = clk_get_rate(&clk); + printf("%s: %lu\n", clks[i].name, rate); + + clk_free(&clk); + } + + return 0; +} + +U_BOOT_CMD( + clock, 2, 1, do_clock, + "display information about clocks", + "" +); diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c deleted file mode 100644 index f24fd89e3f..0000000000 --- a/arch/arm/mach-rockchip/rk3328-board-spl.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_debug_uart_init(void) -{ -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - preloader_console_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -u32 spl_boot_mode(const u32 boot_device) -{ - return MMCSD_MODE_RAW; -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index 1cf829dc34..592f287613 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -4,12 +4,24 @@ */ #include <common.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include <asm/arch-rockchip/uart.h> #include <asm/armv8/mmu.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; +#define CRU_BASE 0xFF440000 +#define GRF_BASE 0xFF100000 +#define UART2_BASE 0xFF130000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000", + [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000", +}; + static struct mm_region rk3328_mem_map[] = { { .virt = 0x0UL, @@ -32,20 +44,52 @@ static struct mm_region rk3328_mem_map[] = { struct mm_region *mem_map = rk3328_mem_map; -int dram_init_banksize(void) +int arch_cpu_init(void) { - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); - - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + /* We do some SoC one time setting here. */ return 0; } -int arch_cpu_init(void) +void board_debug_uart_init(void) { - /* We do some SoC one time setting here. */ + struct rk3328_grf_regs * const grf = (void *)GRF_BASE; + struct rk_uart * const uart = (void *)UART2_BASE; + enum{ + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_UART2_TX_M1 = 1, - return 0; + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_UART2_RX_M1 = 1, + }; + enum { + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + }; + + /* uart_sel_clk default select 24MHz */ + writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148); + + /* init uart baud rate 1500000 */ + writel(0x83, &uart->lcr); + writel(0x1, &uart->rbr); + writel(0x3, &uart->lcr); + + /* Enable early UART2 */ + rk_clrsetreg(&grf->com_iomux, + IOMUX_SEL_UART2_MASK, + IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_SEL_MASK, + GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A1_SEL_MASK, + GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); + + /* enable FIFO */ + writel(0x1, &uart->sfe); } diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c deleted file mode 100644 index 6ba106c63b..0000000000 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <asm/io.h> -#include <asm/arch-rockchip/periph.h> - -__weak int arch_cpu_init(void) -{ - return 0; -} - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) - -void rockchip_stimer_init(void) -{ - /* If Timer already enabled, don't re-init it */ - u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - - if (reg & TIMER_EN) - return; - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* Init secure timer */ - rockchip_stimer_init(); - /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ - timer_init(); - - arch_cpu_init(); - preloader_console_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return; - } -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 47786f52ee..7ccd417a18 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -8,6 +8,7 @@ #include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_rk3368.h> #include <asm/arch-rockchip/grf_rk3368.h> @@ -52,16 +53,10 @@ static struct mm_region rk3368_mem_map[] = { struct mm_region *mem_map = rk3368_mem_map; -int dram_init_banksize(void) -{ - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); - - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; - - return 0; -} +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000", + [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000", +}; #ifdef CONFIG_ARCH_EARLY_INIT_R static int mcu_init(void) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c deleted file mode 100644 index 7154d8e5d0..0000000000 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#include <common.h> -#include <debug_uart.h> -#include <dm.h> -#include <ram.h> -#include <spl.h> -#include <spl_gpio.h> -#include <syscon.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> -#include <asm/arch-rockchip/grf_rk3399.h> -#include <asm/arch-rockchip/hardware.h> -#include <asm/arch-rockchip/periph.h> -#include <asm/arch-rockchip/sys_proto.h> -#include <power/regulator.h> - -void board_return_to_bootrom(void) -{ - back_to_bootrom(BROM_BOOT_NEXTSTAGE); -} - -static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { - [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", - [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", - [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", -}; - -const char *board_spl_was_booted_from(void) -{ - u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR); - const char *bootdevice_ofpath = NULL; - - if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) - bootdevice_ofpath = boot_devices[bootdevice_brom_id]; - - if (bootdevice_ofpath) - debug("%s: brom_bootdevice_id %x maps to '%s'\n", - __func__, bootdevice_brom_id, bootdevice_ofpath); - else - debug("%s: failed to resolve brom_bootdevice_id %x\n", - __func__, bootdevice_brom_id); - - return bootdevice_ofpath; -} - -u32 spl_boot_device(void) -{ - u32 boot_device = BOOT_DEVICE_MMC1; - - if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) - return BOOT_DEVICE_BOOTROM; - - return boot_device; -} - -const char *spl_decode_boot_device(u32 boot_device) -{ - int i; - static const struct { - u32 boot_device; - const char *ofpath; - } spl_boot_devices_tbl[] = { - { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" }, - { BOOT_DEVICE_MMC2, "/sdhci@fe330000" }, - { BOOT_DEVICE_SPI, "/spi@ff1d0000" }, - }; - - for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) - if (spl_boot_devices_tbl[i].boot_device == boot_device) - return spl_boot_devices_tbl[i].ofpath; - - return NULL; -} - -void spl_perform_fixups(struct spl_image_info *spl_image) -{ - void *blob = spl_image->fdt_addr; - const char *boot_ofpath; - int chosen; - - /* - * Inject the ofpath of the device the full U-Boot (or Linux in - * Falcon-mode) was booted from into the FDT, if a FDT has been - * loaded at the same time. - */ - if (!blob) - return; - - boot_ofpath = spl_decode_boot_device(spl_image->boot_device); - if (!boot_ofpath) { - pr_err("%s: could not map boot_device to ofpath\n", __func__); - return; - } - - chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); - if (chosen < 0) { - pr_err("%s: could not find/create '/chosen'\n", __func__); - return; - } - fdt_setprop_string(blob, chosen, - "u-boot,spl-boot-device", boot_ofpath); -} - -__weak void rockchip_stimer_init(void) -{ -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - struct rk3399_pmusgrf_regs *sgrf; - struct rk3399_grf_regs *grf; - int ret; - -#ifdef CONFIG_DEBUG_UART - debug_uart_init(); - -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB - int sum, i; - - /* - * Add a delay and ensure that the compiler does not optimise this out. - * This is needed since the power rails tail a while to turn on, and - * we get garbage serial output otherwise. - */ - sum = 0; - for (i = 0; i < 150000; i++) - sum += i; - gru_dummy_function(sum); -#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ - - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug("U-Boot SPL board init\n"); -#endif - - ret = spl_early_init(); - if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - /* - * Disable DDR and SRAM security regions. - * - * As we are entered from the BootROM, the region from - * 0x0 through 0xfffff (i.e. the first MB of memory) will - * be protected. This will cause issues with the DW_MMC - * driver, which tries to DMA from/to the stack (likely) - * located in this range. - */ - sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); - rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); - rk_clrreg(&sgrf->slv_secure_con4, 0x2000); - - /* eMMC clock generator: disable the clock multipilier */ - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrreg(&grf->emmccore_con[11], 0x0ff); - - rockchip_stimer_init(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - pr_err("DRAM init failed: %d\n", ret); - return; - } -} - -#if defined(SPL_GPIO_SUPPORT) -static void rk3399_force_power_on_reset(void) -{ - ofnode node; - struct gpio_desc sysreset_gpio; - - debug("%s: trying to force a power-on reset\n", __func__); - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - debug("%s: no /config node?\n", __func__); - return; - } - - if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, - &sysreset_gpio, GPIOD_IS_OUT)) { - debug("%s: could not find a /config/sysreset-gpio\n", __func__); - return; - } - - dm_gpio_set_value(&sysreset_gpio, 1); -} -#endif - -void spl_board_init(void) -{ -#if defined(SPL_GPIO_SUPPORT) - struct rk3399_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the TRM - * "3.9.4 Global software reset"), when issuing a software reset. - * This may cause issues during boot-up for some configurations of - * the application software stack. - * - * To work around this, we test whether the last reset reason was - * a power-on reset and (if not) issue an overtemp-reset to reset - * the entire module. - * - * While this was previously fixed by modifying the various places - * that could generate a software reset (e.g. U-Boot's sysreset - * driver, the ATF or Linux), we now have it here to ensure that - * we no longer have to track this through the various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); -#endif - -#if defined(SPL_DM_REGULATOR) - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - if (regulators_enable_boot_on(false)) - debug("%s: Cannot enable boot on regulator\n", __func__); -#endif - - preloader_console_init(); -} - -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); - - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c deleted file mode 100644 index 443c87cccc..0000000000 --- a/arch/arm/mach-rockchip/rk3399-board.c +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2017 Rockchip Electronics Co., Ltd - */ - -#include <common.h> -#include <asm/arch-rockchip/boot_mode.h> - -int board_late_init(void) -{ - setup_boot_mode(); - return 0; -} diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 0f09ea5c49..863024d071 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -4,18 +4,29 @@ */ #include <common.h> +#include <spl.h> #include <spl_gpio.h> +#include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/gpio.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> +#include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; #define GRF_EMMCCORE_CON11 0xff77f02c #define GRF_BASE 0xff770000 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", +}; + static struct mm_region rk3399_mem_map[] = { { .virt = 0x0UL, @@ -67,24 +78,30 @@ void rockchip_stimer_init(void) } #endif -int dram_init_banksize(void) +int arch_cpu_init(void) { - size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); - - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; - return 0; -} +#ifdef CONFIG_SPL_BUILD + struct rk3399_pmusgrf_regs *sgrf; + struct rk3399_grf_regs *grf; -int arch_cpu_init(void) -{ - /* We do some SoC one time setting here. */ - struct rk3399_grf_regs * const grf = (void *)GRF_BASE; + /* + * Disable DDR and SRAM security regions. + * + * As we are entered from the BootROM, the region from + * 0x0 through 0xfffff (i.e. the first MB of memory) will + * be protected. This will cause issues with the DW_MMC + * driver, which tries to DMA from/to the stack (likely) + * located in this range. + */ + sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); + rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); + rk_clrreg(&sgrf->slv_secure_con4, 0x2000); - /* Emmc clock generator: disable the clock multipilier */ + /* eMMC clock generator: disable the clock multipilier */ + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); rk_clrreg(&grf->emmccore_con[11], 0x0ff); +#endif return 0; } @@ -146,3 +163,111 @@ void board_debug_uart_init(void) #endif } #endif + +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +const char *spl_decode_boot_device(u32 boot_device) +{ + int i; + static const struct { + u32 boot_device; + const char *ofpath; + } spl_boot_devices_tbl[] = { + { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" }, + { BOOT_DEVICE_MMC2, "/sdhci@fe330000" }, + { BOOT_DEVICE_SPI, "/spi@ff1d0000" }, + }; + + for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) + if (spl_boot_devices_tbl[i].boot_device == boot_device) + return spl_boot_devices_tbl[i].ofpath; + + return NULL; +} + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + void *blob = spl_image->fdt_addr; + const char *boot_ofpath; + int chosen; + + /* + * Inject the ofpath of the device the full U-Boot (or Linux in + * Falcon-mode) was booted from into the FDT, if a FDT has been + * loaded at the same time. + */ + if (!blob) + return; + + boot_ofpath = spl_decode_boot_device(spl_image->boot_device); + if (!boot_ofpath) { + pr_err("%s: could not map boot_device to ofpath\n", __func__); + return; + } + + chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); + if (chosen < 0) { + pr_err("%s: could not find/create '/chosen'\n", __func__); + return; + } + fdt_setprop_string(blob, chosen, + "u-boot,spl-boot-device", boot_ofpath); +} + +#if defined(SPL_GPIO_SUPPORT) +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} +#endif + +void spl_board_init(void) +{ +#if defined(SPL_GPIO_SUPPORT) + struct rk3399_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); +#endif + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif +} +#endif diff --git a/arch/arm/mach-rockchip/rv1108-board.c b/arch/arm/mach-rockchip/rv1108-board.c deleted file mode 100644 index 3412f2c063..0000000000 --- a/arch/arm/mach-rockchip/rv1108-board.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Google, Inc - */ - -#include <common.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rv1108_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - const void *blob = gd->fdt_blob; - bool matched = false; - int node, phy_node; - u32 grf_phy_offset; - const char *mode; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, "rockchip,rk3066-usb"); - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3066-usb"); - } - - if (!matched) { - debug("usb_otg device not found\n"); - return -ENODEV; - } - - rv1108_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - node = fdtdec_lookup_phandle(blob, node, "phys"); - if (node <= 0) { - debug("phys node not found\n"); - return -ENODEV; - } - - phy_node = fdt_parent_offset(blob, node); - if (phy_node <= 0) { - debug("usb phy node not found\n"); - return -ENODEV; - } - - rv1108_otg_data.phy_of_node = phy_node; - grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); - - /* find the grf node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rv1108-grf"); - if (node <= 0) { - debug("grf node not found\n"); - return -ENODEV; - } - - rv1108_otg_data.regs_phy = grf_phy_offset + fdtdec_get_addr(blob, node, - "reg"); - - return dwc2_udc_probe(&rv1108_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c index 66aeb3ffcc..6362af995b 100644 --- a/arch/arm/mach-rockchip/rv1108/rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/rv1108.c @@ -3,13 +3,3 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd * Author: Andy Yan <andy.yan@rock-chips.com> */ - -#include <common.h> - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index 8684dbd4fa..22a4aca940 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -11,6 +11,69 @@ #include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; + +#define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024) + +struct tos_parameter_t { + u32 version; + u32 checksum; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } tee_mem; + struct { + char name[8]; + s64 phy_addr; + u32 size; + u32 flags; + } drm_mem; + s64 reserve[8]; +}; + +int dram_init_banksize(void) +{ + size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + gd->ram_top); + +#ifdef CONFIG_ARM64 + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#else +#ifdef CONFIG_SPL_OPTEE + struct tos_parameter_t *tos_parameter; + + tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + TRUST_PARAMETER_OFFSET); + + if (tos_parameter->tee_mem.flags == 1) { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + - CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + tos_parameter->tee_mem.size; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } else { + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 32M for OPTEE with TA */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0x2000000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + top - gd->bd->bi_dram[1].start; + } +#else + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; +#endif +#endif + + return 0; +} + size_t rockchip_sdram_size(phys_addr_t reg) { u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c new file mode 100644 index 0000000000..33137cc5ef --- /dev/null +++ b/arch/arm/mach-rockchip/spl.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_return_to_bootrom(void) +{ + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +} + +__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { +}; + +const char *board_spl_was_booted_from(void) +{ + u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); + const char *bootdevice_ofpath = NULL; + + if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) + bootdevice_ofpath = boot_devices[bootdevice_brom_id]; + + if (bootdevice_ofpath) + debug("%s: brom_bootdevice_id %x maps to '%s'\n", + __func__, bootdevice_brom_id, bootdevice_ofpath); + else + debug("%s: failed to resolve brom_bootdevice_id %x\n", + __func__, bootdevice_brom_id); + + return bootdevice_ofpath; +} + +u32 spl_boot_device(void) +{ + u32 boot_device = BOOT_DEVICE_MMC1; + +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ + defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) + return BOOT_DEVICE_SPI; +#endif + if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) + return BOOT_DEVICE_BOOTROM; + + return boot_device; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +#if !defined(CONFIG_ROCKCHIP_RK3188) +#define TIMER_LOAD_COUNT_L 0x00 +#define TIMER_LOAD_COUNT_H 0x04 +#define TIMER_CONTROL_REG 0x10 +#define TIMER_EN 0x1 +#define TIMER_FMODE BIT(0) +#define TIMER_RMODE BIT(1) + +__weak void rockchip_stimer_init(void) +{ + /* If Timer already enabled, don't re-init it */ + u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + + if (reg & TIMER_EN) + return; +#ifndef CONFIG_ARM64 + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(COUNTER_FREQUENCY)); +#endif + writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); + writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + + TIMER_CONTROL_REG); +} +#endif + +__weak int board_early_init_f(void) +{ + return 0; +} + +__weak int arch_cpu_init(void) +{ + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; +#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT) + struct udevice *dev; +#endif + +#ifdef CONFIG_DEBUG_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + debug("\nspl:debug uart enabled in %s\n", __func__); +#endif + + board_early_init_f(); + + ret = spl_early_init(); + if (ret) { + printf("spl_early_init() failed: %d\n", ret); + hang(); + } + arch_cpu_init(); +#if !defined(CONFIG_SUPPORT_TPL) || defined(CONFIG_SPL_OS_BOOT) + debug("\nspl:init dram\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } +#endif +#if !defined(CONFIG_ROCKCHIP_RK3188) + rockchip_stimer_init(); +#endif +#ifdef CONFIG_SYS_ARCH_TIMER + /* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */ + timer_init(); +#endif + preloader_console_init(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index e66720447f..fc1181cb27 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -8,7 +8,6 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o -obj-y += reset_manager.o ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 42beaecdd6..6ad037e325 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -11,6 +11,7 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +#define RSTMGR_CTRL_SWCOLDRSTREQ_LSB 0 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 /* diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c deleted file mode 100644 index e0a01ed07a..0000000000 --- a/arch/arm/mach-socfpga/reset_manager.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Altera Corporation <www.altera.com> - */ - - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/reset_manager.h> - -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -#include <asm/arch/mailbox_s10.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_TARGET_SOCFPGA_STRATIX10) -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; -#endif - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) - puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); - mbox_reset_cold(); -#else - writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB, - &reset_manager_base->ctrl); -#endif - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 9bb5a5c202..6cf17eb94e 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -65,6 +65,24 @@ config PMUFW_INIT_FILE Include external PMUFW (Platform Management Unit FirmWare) to a Xilinx bootable image (boot.bin). +config ZYNQMP_SPL_PM_CFG_OBJ_FILE + string "PMU firmware configuration object to load at runtime by SPL" + depends on SPL + help + Path to a binary PMU firmware configuration object to be linked + into U-Boot SPL and loaded at runtime into the PMU firmware. + + The ZynqMP Power Management Unit (PMU) needs a configuration + object for most SoC peripherals to work. To have it loaded by + U-Boot SPL set here the file name (absolute path or relative to + the top source tree) of your configuration, which must be a + binary blob. It will be linked in the SPL binary and loaded + into the PMU firmware by U-Boot SPL during board + initialization. + + Leave this option empty if your PMU firmware has a hard-coded + configuration object or you are loading it by any other means. + config ZYNQMP_USB bool "Configure ZynqMP USB" diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 8a3b074724..f3765e45b1 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -8,3 +8,7 @@ obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o + +ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"") +obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o +endif diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 385c8825f2..915badc6fb 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -72,4 +72,6 @@ int chip_id(unsigned char id); void tcm_init(u8 mode); #endif +void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/pmu_ipc.c b/arch/arm/mach-zynqmp/pmu_ipc.c new file mode 100644 index 0000000000..d8858ea3ff --- /dev/null +++ b/arch/arm/mach-zynqmp/pmu_ipc.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Inter-Processor Communication with the Platform Management Unit (PMU) + * firmware. + * + * (C) Copyright 2019 Luca Ceresoli + * Luca Ceresoli <luca@lucaceresoli.net> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +/* IPI bitmasks, register base and register offsets */ +#define IPI_BIT_MASK_APU 0x00001 +#define IPI_BIT_MASK_PMU0 0x10000 +#define IPI_REG_BASE_APU 0xFF300000 +#define IPI_REG_BASE_PMU0 0xFF330000 +#define IPI_REG_OFFSET_TRIG 0x00 +#define IPI_REG_OFFSET_OBR 0x04 + +/* IPI mailbox buffer offsets */ +#define IPI_BUF_BASE_APU 0xFF990400 +#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0 +#define IPI_BUF_OFFSET_REQ 0x00 +#define IPI_BUF_OFFSET_RESP 0x20 + +#define PMUFW_PAYLOAD_ARG_CNT 8 + +/* PMUFW commands */ +#define PMUFW_CMD_SET_CONFIGURATION 2 + +static void pmu_ipc_send_request(const u32 *req, size_t req_len) +{ + u32 *mbx = (u32 *)(IPI_BUF_BASE_APU + + IPI_BUF_OFFSET_TARGET_PMU + + IPI_BUF_OFFSET_REQ); + size_t i; + + for (i = 0; i < req_len; i++) + writel(req[i], &mbx[i]); +} + +static void pmu_ipc_read_response(unsigned int *value, size_t count) +{ + u32 *mbx = (u32 *)(IPI_BUF_BASE_APU + + IPI_BUF_OFFSET_TARGET_PMU + + IPI_BUF_OFFSET_RESP); + size_t i; + + for (i = 0; i < count; i++) + value[i] = readl(&mbx[i]); +} + +/** + * Send request to PMU and get the response. + * + * @req: Request buffer. Byte 0 is the API ID, other bytes are optional + * parameters. + * @req_len: Request length in number of 32-bit words. + * @res: Response buffer. Byte 0 is the error code, other bytes are + * optional parameters. Optional, if @res_maxlen==0 the parameters + * will not be read. + * @res_maxlen: Space allocated for the response in number of 32-bit words. + * + * @return Error code returned by the PMU (i.e. the first word of the response) + */ +static int pmu_ipc_request(const u32 *req, size_t req_len, + u32 *res, size_t res_maxlen) +{ + u32 status; + + if (req_len > PMUFW_PAYLOAD_ARG_CNT || + res_maxlen > PMUFW_PAYLOAD_ARG_CNT) + return -EINVAL; + + pmu_ipc_send_request(req, req_len); + + /* Raise Inter-Processor Interrupt to PMU and wait for response */ + writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG); + do { + status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR); + } while (status & IPI_BIT_MASK_PMU0); + + pmu_ipc_read_response(res, res_maxlen); + + return 0; +} + +/** + * Send a configuration object to the PMU firmware. + * + * @cfg_obj: Pointer to the configuration object + * @size: Size of @cfg_obj in bytes + */ +void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) +{ + const u32 request[] = { + PMUFW_CMD_SET_CONFIGURATION, + (u32)((u64)cfg_obj) + }; + u32 response; + int err; + + printf("Loading PMUFW cfg obj (%ld bytes)\n", size); + + err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1); + if (err) + panic("Cannot load PMUFW configuration object (%d)\n", err); + if (response != 0) + panic("PMUFW returned 0x%08x status!\n", response); +} diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h index 9985e3c494..98e1826e2c 100644 --- a/arch/sandbox/include/asm/spi.h +++ b/arch/sandbox/include/asm/spi.h @@ -1,5 +1,5 @@ /* - * Simulate a SPI port and clients (see README.sandbox for details) + * Simulate a SPI port and clients (see doc/arch/sandbox.rst for details) * * Copyright (c) 2011-2013 The Chromium OS Authors. * See file CREDITS for list of people who contributed to this diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c index 9ba1fbd0e2..47b921a748 100644 --- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c @@ -8,7 +8,7 @@ #define GPIO7A3_HUB_RST 227 -int rk_board_late_init(void) +int rk3288_board_late_init(void) { int ret; diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS index b77a5f6622..42324a3f73 100644 --- a/board/davinci/da8xxevm/MAINTAINERS +++ b/board/davinci/da8xxevm/MAINTAINERS @@ -7,10 +7,6 @@ F: configs/da850evm_defconfig F: configs/da850evm_nand_defconfig F: configs/da850evm_direct_nor_defconfig -AM18XXEVM BOARD -S: Orphan -F: configs/da850_am18xxevm_defconfig - OMAPL138_LCDK BOARD M: Peter Howard <phoward@gme.net.au> S: Maintained diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850 index 5775b7d80f..8cebdcc1bb 100644 --- a/board/davinci/da8xxevm/README.da850 +++ b/board/davinci/da8xxevm/README.da850 @@ -29,9 +29,7 @@ Compilation =========== The exact build target you need will depend on the board you have. For Logic PD boards, or other boards which store the ethernet MAC address at -the end of SPI flash, run 'make da850evm'. For boards which store the -ethernet MAC address in the i2c EEPROM located at 0x50, run -'make da850_am18xxevm'. Once this build completes you will have a +the end of SPI flash, run 'make da850evm'. Once this build completes you will have a u-boot.ais file that needs to be written to the correct persistent storage. diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index dd11551428..578d928443 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -11,11 +11,11 @@ #include <common.h> #include <i2c.h> #include <net.h> -#include <spi.h> -#include <spi_flash.h> #include <asm/arch/hardware.h> #include <asm/ti-common/davinci_nand.h> #include <asm/io.h> +#include <ns16550.h> +#include <dm/platdata.h> #include <linux/errno.h> #include <asm/mach-types.h> #include <asm/arch/davinci_misc.h> @@ -357,3 +357,17 @@ int board_mmc_init(bd_t *bis) } #endif #endif + +#ifdef CONFIG_SPL_BUILD +static const struct ns16550_platdata serial_pdata = { + .base = DAVINCI_UART2_BASE, + .reg_shift = 2, + .clock = 228000000, + .fcr = UART_FCR_DEFVAL, +}; + +U_BOOT_DEVICE(omapl138_uart) = { + .name = "ns16550_serial", + .platdata = &serial_pdata, +}; +#endif diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 0de1f4243e..607667ac63 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -50,7 +50,7 @@ int mach_cpu_init(void) #define MODEM_ENABLE_GPIO 111 -int board_init(void) +int board_early_init_f(void) { gpio_request(MODEM_ENABLE_GPIO, "modem_enable"); gpio_direction_output(MODEM_ENABLE_GPIO, 0); diff --git a/board/firefly/firefly-rk3288/firefly-rk3288.c b/board/firefly/firefly-rk3288/firefly-rk3288.c index bdc02a6a79..a3f784f0a3 100644 --- a/board/firefly/firefly-rk3288/firefly-rk3288.c +++ b/board/firefly/firefly-rk3288/firefly-rk3288.c @@ -4,3 +4,39 @@ */ #include <common.h> + +#ifdef CONFIG_SPL_BUILD +static int setup_led(void) +{ +#ifdef CONFIG_SPL_LED + struct udevice *dev; + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + ret = led_set_on(dev, 1); + if (ret) + return ret; +#endif + + return 0; +} + +void spl_board_init(void) +{ + int ret; + + ret = setup_led(); + if (ret) { + debug("LED ret=%d\n", ret); + hang(); + } +} +#endif diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c index 10b04a1ce5..b0f9a5f9b7 100644 --- a/board/geekbuying/geekbox/geekbox.c +++ b/board/geekbuying/geekbox/geekbox.c @@ -4,8 +4,3 @@ */ #include <common.h> - -int board_init(void) -{ - return 0; -} diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c index b116b1a549..b6b4f19d84 100644 --- a/board/google/gru/gru.c +++ b/board/google/gru/gru.c @@ -5,12 +5,28 @@ #include <common.h> -int board_init(void) +#ifdef CONFIG_SPL_BUILD +/* provided to defeat compiler optimisation in board_init_f() */ +void gru_dummy_function(int i) { - return 0; } -/* provided to defeat compiler optimisation in board_init_f() */ -void gru_dummy_function(int i) +int board_early_init_f(void) { +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + int sum, i; + + /* + * Add a delay and ensure that the compiler does not optimise this out. + * This is needed since the power rails tail a while to turn on, and + * we get garbage serial output otherwise. + */ + sum = 0; + for (i = 0; i < 150000; i++) + sum += i; + gru_dummy_function(sum); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + + return 0; } +#endif diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c index 19edb18a66..dd2c014c60 100644 --- a/board/google/veyron/veyron.c +++ b/board/google/veyron/veyron.c @@ -3,10 +3,93 @@ * (C) Copyright 2015 Google, Inc */ +#include <clk.h> #include <common.h> +#include <dm.h> +#include <asm/arch-rockchip/clock.h> +#include <dt-bindings/clock/rk3288-cru.h> +#include <power/regulator.h> /* * We should increase the DDR voltage to 1.2V using the PWM regulator. * There is a U-Boot driver for this but it may need to add support for the * 'voltage-table' property. */ +#ifndef CONFIG_SPL_BUILD +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) +static int veyron_init(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = regulator_get_by_platname("vdd_arm", &dev); + if (ret) { + debug("Cannot set regulator name\n"); + return ret; + } + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = regulator_set_value(dev, 1200000); + if (ret) + return ret; + udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ + ret = regulator_set_value(dev, 1400000); + if (ret) + return ret; + udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ + + ret = rockchip_get_clk(&clk.dev); + if (ret) + return ret; + clk.id = PLL_APLL; + ret = clk_set_rate(&clk, 1800000000); + if (IS_ERR_VALUE(ret)) + return ret; + + ret = regulator_get_by_platname("vcc33_sd", &dev); + if (ret) { + debug("Cannot get regulator name\n"); + return ret; + } + + ret = regulator_set_value(dev, 3300000); + if (ret) + return ret; + + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulators\n", __func__); + return ret; + } + + return 0; +} +#endif + +int board_early_init_f(void) +{ + struct udevice *dev; + int ret; + +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) + if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { + ret = veyron_init(); + if (ret) + return ret; + } +#endif + /* + * This init is done in SPL, but when chain-loading U-Boot SPL will + * have been skipped. Allow the clock driver to check if it needs + * setting up. + */ + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return ret; + } + + return 0; +} +#endif diff --git a/board/mediatek/pumpkin/Kconfig b/board/mediatek/pumpkin/Kconfig new file mode 100644 index 0000000000..34b1c0b09d --- /dev/null +++ b/board/mediatek/pumpkin/Kconfig @@ -0,0 +1,13 @@ +if TARGET_MT8516 + +config SYS_BOARD + default "pumpkin" + +config SYS_CONFIG_NAME + default "pumpkin" + +config MTK_BROM_HEADER_INFO + string + default "media=emmc" + +endif diff --git a/board/mediatek/pumpkin/MAINTAINERS b/board/mediatek/pumpkin/MAINTAINERS new file mode 100644 index 0000000000..16beadc027 --- /dev/null +++ b/board/mediatek/pumpkin/MAINTAINERS @@ -0,0 +1,6 @@ +Pumpkin +M: Fabien Parent <fparent@baylibre.com> +S: Maintained +F: board/mediatek/pumpkin +F: include/configs/pumpkin.h +F: configs/pumpkin_defconfig diff --git a/board/mediatek/pumpkin/Makefile b/board/mediatek/pumpkin/Makefile new file mode 100644 index 0000000000..75fce4a393 --- /dev/null +++ b/board/mediatek/pumpkin/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += pumpkin.o diff --git a/board/mediatek/pumpkin/pumpkin.c b/board/mediatek/pumpkin/pumpkin.c new file mode 100644 index 0000000000..666e4d6a26 --- /dev/null +++ b/board/mediatek/pumpkin/pumpkin.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 BayLibre SAS + */ + +#include <common.h> + +int board_init(void) +{ + return 0; +} diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index ffe1833b06..92f3bd25f4 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -8,10 +8,13 @@ #include <common.h> #include <dm.h> #include <environment.h> +#include <fdtdec.h> #include <i2c.h> #include <i2c_eeprom.h> #include <netdev.h> #include "som.h" +#include <power/regulator.h> +#include <power/rk8xx_pmic.h> static int valid_rk3288_som(struct rk3288_som *som) { @@ -27,7 +30,7 @@ static int valid_rk3288_som(struct rk3288_som *som) return hw == som->bs; } -int rk_board_late_init(void) +int rk3288_board_late_init(void) { int ret; struct udevice *dev; @@ -68,3 +71,47 @@ int rk_board_late_init(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_OF_PLATDATA) +static int phycore_init(void) +{ + struct udevice *pmic; + int ret; + + ret = uclass_first_device_err(UCLASS_PMIC, &pmic); + if (ret) + return ret; + +#if defined(CONFIG_SPL_POWER_SUPPORT) + /* Increase USB input current to 2A */ + ret = rk818_spl_configure_usb_input_current(pmic, 2000); + if (ret) + return ret; + + /* Close charger when USB lower then 3.26V */ + ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); + if (ret) + return ret; +#endif + + return 0; +} +#endif + +void spl_board_init(void) +{ +#if !defined(CONFIG_SPL_OF_PLATDATA) + int ret; + + if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { + ret = phycore_init(); + if (ret) { + debug("Failed to set up phycore power settings: %d\n", + ret); + return; + } + } +#endif +} +#endif diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 292867e496..37f8a46d7e 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -8,6 +8,8 @@ */ #include <common.h> +#include <dm.h> +#include <dm/uclass-internal.h> #include <asm/arch/rmobile.h> #ifdef CONFIG_RCAR_GEN3 @@ -46,4 +48,51 @@ int dram_init_banksize(void) return 0; } + +#if CONFIG_IS_ENABLED(OF_BOARD_SETUP) && CONFIG_IS_ENABLED(PCI) +int ft_board_setup(void *blob, bd_t *bd) +{ + struct udevice *dev; + struct uclass *uc; + fdt_addr_t regs_addr; + int i, off, ret; + + ret = uclass_get(UCLASS_PCI, &uc); + if (ret) + return ret; + + uclass_foreach_dev(dev, uc) { + struct pci_controller hose = { 0 }; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (hose.region_count == MAX_PCI_REGIONS) { + printf("maximum number of regions parsed, aborting\n"); + break; + } + + if (bd->bi_dram[i].size) { + pci_set_region(&hose.regions[hose.region_count++], + bd->bi_dram[i].start, + bd->bi_dram[i].start, + bd->bi_dram[i].size, + PCI_REGION_MEM | + PCI_REGION_PREFETCH | + PCI_REGION_SYS_MEMORY); + } + } + + regs_addr = devfdt_get_addr_index(dev, 0); + off = fdt_node_offset_by_compat_reg(blob, + "renesas,pcie-rcar-gen3", regs_addr); + if (off < 0) { + printf("Failed to find PCIe node@%llx\n", regs_addr); + return off; + } + + fdt_pci_dma_ranges(blob, off, &hose); + } + + return 0; +} +#endif #endif diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c index 53e753fc17..b81f970883 100644 --- a/board/rockchip/evb_px5/evb-px5.c +++ b/board/rockchip/evb_px5/evb-px5.c @@ -2,9 +2,3 @@ /* * Copyright (c) 2017 Andy Yan */ -#include <common.h> - -int board_init(void) -{ - return 0; -} diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c index bc9ef5e98b..779bc646b2 100644 --- a/board/rockchip/evb_rk3328/evb-rk3328.c +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -3,68 +3,3 @@ * (C) Copyright 2016 Rockchip Electronics Co., Ltd */ -#include <common.h> -#include <asm/armv8/mmu.h> -#include <dwc3-uboot.h> -#include <power/regulator.h> -#include <usb.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - int ret; - - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - return ret; -} - -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) -#include <usb.h> -#include <usb/dwc2_udc.h> - -static struct dwc2_plat_otg_data rk3328_otg_data = { - .rx_fifo_sz = 512, - .np_tx_fifo_sz = 16, - .tx_fifo_sz = 128, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const char *mode; - bool matched = false; - const void *blob = gd->fdt_blob; - - /* find the usb_otg node */ - node = fdt_node_offset_by_compatible(blob, -1, - "rockchip,rk3328-usb"); - - while (node > 0) { - mode = fdt_getprop(blob, node, "dr_mode", NULL); - if (mode && strcmp(mode, "otg") == 0) { - matched = true; - break; - } - - node = fdt_node_offset_by_compatible(blob, node, - "rockchip,rk3328-usb"); - } - if (!matched) { - debug("Not found usb_otg device\n"); - return -ENODEV; - } - - rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); - - return dwc2_udc_probe(&rk3328_otg_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return 0; -} -#endif diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index eb1b832274..b9049abcc7 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -5,19 +5,15 @@ #include <common.h> #include <dm.h> -#include <dm/pinctrl.h> #include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -int board_init(void) +#ifndef CONFIG_SPL_BUILD +int board_early_init_f(void) { struct udevice *regulator; int ret; - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - ret = regulator_get_by_platname("vcc5v0_host", ®ulator); if (ret) { debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); @@ -25,11 +21,10 @@ int board_init(void) } ret = regulator_set_enable(regulator, true); - if (ret) { - debug("%s vcc5v0-host-en set fail!\n", __func__); - goto out; - } + if (ret) + debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret); out: return 0; } +#endif diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index 457b110cd5..733f29376e 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -47,23 +47,9 @@ int mach_cpu_init(void) return 0; } - -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = 0x8000000; return 0; } - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0x60000000; - gd->bd->bi_dram[0].size = 0x8000000; - - return 0; -} diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index 9bb93c7d16..b81f970883 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -2,18 +2,3 @@ /* * Copyright (c) 2017 Andy Yan */ -#include <common.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk3368.h> -#include <syscon.h> - -int mach_cpu_init(void) -{ - return 0; -} - -int board_init(void) -{ - return 0; -} diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c index 44f13183a5..e6b018d89c 100644 --- a/board/rockchip/tinker_rk3288/tinker-rk3288.c +++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c @@ -21,7 +21,7 @@ static int get_ethaddr_from_eeprom(u8 *addr) return i2c_eeprom_read(dev, 0, addr, 6); } -int rk_board_late_init(void) +int rk3288_board_late_init(void) { u8 ethaddr[6]; diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c index 6cd5a5f18e..1b0d504631 100644 --- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c @@ -2,21 +2,3 @@ /* * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH */ -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <asm/io.h> -#include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/grf_rk3368.h> -#include <asm/arch-rockchip/timer.h> -#include <syscon.h> - -int mach_cpu_init(void) -{ - return 0; -} - -int board_init(void) -{ - return 0; -} diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 251cd2d566..a7e7f022ba 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -21,21 +21,6 @@ #include <power/regulator.h> #include <u-boot/sha256.h> -int board_init(void) -{ - int ret; - - /* - * We need to call into regulators_enable_boot_on() again, as the call - * during SPL may have not included all regulators. - */ - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - return 0; -} - static void setup_macaddr(void) { #if CONFIG_IS_ENABLED(CMD_NET) diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 2eb7120e84..68a127b9ac 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -2,18 +2,3 @@ /* * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ - -#include <common.h> -#include <dm.h> -#include <power/regulator.h> - -int board_init(void) -{ - int ret; - - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - return 0; -} diff --git a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c new file mode 100644 index 0000000000..d4f0ee796f --- /dev/null +++ b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Xilinx, Inc. + */ + +#include <asm/arch/ps7_init_gpl.h> + +static unsigned long ps7_pll_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U), + EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U), + EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U), + EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U), + EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U), + EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U), + EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U), + EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U), + EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U), + EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U), + EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U), + EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U), + EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U), + EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U), + EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), + EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index efc1d356d6..04fc7f32fe 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -7,3 +7,9 @@ F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* F: configs/avnet_ultra96_rev1_defconfig + +ARM ZYNQMP AVNET ULTRAZED EV BOARD +M: Luca Ceresoli <luca@lucaceresoli.net> +S: Maintained +F: arch/arm/dts/avnet-ultrazedev-* +F: configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 80f8ca7e1e..5ace6cc1b4 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -33,6 +33,13 @@ ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),) obj-y += $(init-objs) endif +ifdef CONFIG_SPL_BUILD +ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"") +obj-$(CONFIG_SPL_BUILD) += pm_cfg_obj.o +$(obj)/pm_cfg_obj.o: $(shell cd $(srctree); readlink -f $(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE)) FORCE +endif +endif + obj-$(CONFIG_MMC_SDHCI_ZYNQ) += tap_delays.o ifndef CONFIG_SPL_BUILD diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c new file mode 100644 index 0000000000..ac3f716392 --- /dev/null +++ b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +static unsigned long psu_pll_init_data(void) +{ + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000002U); + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); + mask_poll(0xFF5E0040, 0x00000001U); + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000001U); + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000002U); + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U); + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); + mask_poll(0xFD1A0044, 0x00000004U); + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); + + return 1; +} + +static unsigned long psu_clock_init_data(void) +{ + psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U); + psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); + psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U); + psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U); + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U); + psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010602U); + psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010602U); + psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U); + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U); + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00B4, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U); + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U); + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); + + return 1; +} + +static unsigned long psu_ddr_init_data(void) +{ + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U); + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000300U); + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U); + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00409410U); + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x009280D2U); + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0048051FU); + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020126U); + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U); + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002705U); + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x09340301U); + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280200U); + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U); + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU); + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x131C2813U); + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0004041CU); + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0808050FU); + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU); + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U); + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U); + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U); + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U); + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x05050D08U); + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0002040CU); + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1308010EU); + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U); + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201C9C2U); + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048C820DU); + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U); + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U); + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000A0BU); + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U); + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U); + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U); + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F08U); + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U); + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U); + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000600U); + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U); + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U); + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F12090U); + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x4B025810U); + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xEA601518U); + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU); + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU); + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08261009U); + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28380008U); + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U); + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U); + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01A42B08U); + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00371009U); + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00001010U); + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000300U); + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000834U); + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U); + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U); + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U); + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U); + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U); + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU); + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U); + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U); + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U); + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U); + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU); + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U); + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AEA58U); + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU); + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU); + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U); + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U); + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU); + psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U); + psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U); + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU); + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); + psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); + psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U); + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09094F4FU); + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU); + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U); + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U); + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x200E0000U); + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U); + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x000E0000U); + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); + + return 1; +} + +static unsigned long psu_ddr_qos_init_data(void) +{ + return 1; +} + +static unsigned long psu_mio_init_data(void) +{ + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U); + psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180060, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180064, 0x000000FEU, 0x00000040U); + psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180070, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180074, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF180078, 0x000000FEU, 0x00000018U); + psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180080, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180084, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); + psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); + psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U); + psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U); + psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U); + psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x50000000U); + psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02006U); + psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U); + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); + + return 1; +} + +static unsigned long psu_peripherals_pre_init_data(void) +{ + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); + + return 1; +} + +static unsigned long psu_peripherals_init_data(void) +{ + psu_mask_write(0xFD1A0100, 0x000F807EU, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); + psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U); + psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U); + psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U); + psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U); + psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U); + psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U); + psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); + psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); + psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U); + psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000400U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); + psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); + psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); + psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); + psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + + mask_delay(1); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U); + + mask_delay(5); + psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U); + psu_mask_write(0xFF0A0244, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0248, 0x03FFFFFFU, 0x00000020U); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0020U); + mask_delay(1); + psu_mask_write(0xFF0A0008, 0xFFFFFFFFU, 0xFFDF0000U); + mask_delay(5); + + return 1; +} + +static unsigned long psu_afi_config(void) +{ + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); + psu_mask_write(0xFD615000, 0x00000F00U, 0x00000A00U); + + return 1; +} + +static unsigned long psu_ddr_phybringup_data(void) +{ + unsigned int regval = 0; + unsigned int pll_retry = 10; + unsigned int pll_locked = 0; + + while ((pll_retry > 0) && (!pll_locked)) { + Xil_Out32(0xFD080004, 0x00040010); + Xil_Out32(0xFD080004, 0x00040011); + + while ((Xil_In32(0xFD080030) & 0x1) != 1) + ; + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31; + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16; + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16; + pll_retry--; + } + Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); + if (!pll_locked) + return 0; + + Xil_Out32(0xFD080004U, 0x00040063U); + + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) + ; + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) + ; + Xil_Out32(0xFD0701B0U, 0x00000001U); + Xil_Out32(0xFD070320U, 0x00000001U); + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) + ; + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); + regval = Xil_In32(0xFD080030); + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); + regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); + if (regval != 0) + return 0; + + Xil_Out32(0xFD080200U, 0x100091C7U); + int cur_R006_tREFPRD; + + cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U; + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); + + Xil_Out32(0xFD080004, 0x00060001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80004001) != 0x80004001) + regval = Xil_In32(0xFD080030); + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); + + Xil_Out32(0xFD080200U, 0x800091C7U); + prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD); + + Xil_Out32(0xFD080004, 0x0000C001); + regval = Xil_In32(0xFD080030); + while ((regval & 0x80000C01) != 0x80000C01) + regval = Xil_In32(0xFD080030); + + Xil_Out32(0xFD070180U, 0x01000040U); + Xil_Out32(0xFD070060U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + + return 1; +} + +static void init_peripheral(void) +{ + psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); +} + +int psu_init(void) +{ + int status = 1; + + status &= psu_mio_init_data(); + status &= psu_peripherals_pre_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); + init_peripheral(); + + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) + return 1; + return 0; +} diff --git a/board/xilinx/zynqmp/pm_cfg_obj.S b/board/xilinx/zynqmp/pm_cfg_obj.S new file mode 100644 index 0000000000..c4ca77e396 --- /dev/null +++ b/board/xilinx/zynqmp/pm_cfg_obj.S @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +.section .rodata + +.global zynqmp_pm_cfg_obj +.type zynqmp_pm_cfg_obj, @object +.global zynqmp_pm_cfg_obj_size +.type zynqmp_pm_cfg_obj_size, @object + +zynqmp_pm_cfg_obj: +.align 4 +.incbin CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE + +zynqmp_pm_cfg_obj_end: + +zynqmp_pm_cfg_obj_size: +.int zynqmp_pm_cfg_obj_end - zynqmp_pm_cfg_obj diff --git a/board/xilinx/zynqmp/pm_cfg_obj.h b/board/xilinx/zynqmp/pm_cfg_obj.h new file mode 100644 index 0000000000..86e785490c --- /dev/null +++ b/board/xilinx/zynqmp/pm_cfg_obj.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Luca Ceresoli <luca@lucaceresoli.net> + * + * Declaration of PMU config object binary blob linked in at build time. + */ + +extern const u32 zynqmp_pm_cfg_obj[]; +extern const int zynqmp_pm_cfg_obj_size; diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h index c476c902eb..1c1bf32ada 100644 --- a/board/xilinx/zynqmp/xil_io.h +++ b/board/xilinx/zynqmp/xil_io.h @@ -9,17 +9,17 @@ #define xil_printf(...) -void Xil_Out32(unsigned long addr, unsigned long val) +static void Xil_Out32(unsigned long addr, unsigned long val) { writel(val, addr); } -int Xil_In32(unsigned long addr) +static int Xil_In32(unsigned long addr) { return readl(addr); } -void usleep(u32 sleep) +static void __maybe_unused usleep(u32 sleep) { udelay(sleep); } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index c840e92d9c..057ca1fbf7 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -22,6 +22,8 @@ #include <zynqmppl.h> #include <g_dnl.h> +#include "pm_cfg_obj.h" + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ @@ -327,6 +329,13 @@ int board_early_init_f(void) int board_init(void) { +#if defined(CONFIG_SPL_BUILD) + /* Check *at build time* if the filename is an non-empty string */ + if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) + zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, + zynqmp_pm_cfg_obj_size); +#endif + printf("EL Level:\tEL%d\n", current_el()); #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ diff --git a/cmd/cache.c b/cmd/cache.c index 233f428054..2c687173a8 100644 --- a/cmd/cache.c +++ b/cmd/cache.c @@ -22,7 +22,7 @@ void __weak invalidate_icache_all(void) static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { - case 2: /* on / off */ + case 2: /* on / off / flush */ switch (parse_argv(argv[1])) { case 0: icache_disable(); @@ -33,6 +33,8 @@ static int do_icache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case 2: invalidate_icache_all(); break; + default: + return CMD_RET_USAGE; } break; case 1: /* get status */ @@ -54,7 +56,7 @@ void __weak flush_dcache_all(void) static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { switch (argc) { - case 2: /* on / off */ + case 2: /* on / off / flush */ switch (parse_argv(argv[1])) { case 0: dcache_disable(); @@ -65,6 +67,8 @@ static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case 2: flush_dcache_all(); break; + default: + return CMD_RET_USAGE; } break; case 1: /* get status */ diff --git a/cmd/fpga.c b/cmd/fpga.c index bc48abdd6d..eba989a730 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -458,7 +458,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper, "0-device key, 1-user key, 2-no encryption.\n" "The optional Userkey address specifies from which address key\n" "has to be used for decryption if user key is selected.\n" - "NOTE: the sceure bitstream has to be created using xilinx\n" + "NOTE: the secure bitstream has to be created using Xilinx\n" "bootgen tool only.\n" #endif ); diff --git a/cmd/help.c b/cmd/help.c index fa2010c67e..a1a0b99b6f 100644 --- a/cmd/help.c +++ b/cmd/help.c @@ -27,6 +27,7 @@ U_BOOT_CMD( " - print detailed usage of 'command'" ); +#ifdef CONFIG_CMDLINE /* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */ ll_entry_declare(cmd_tbl_t, question_mark, cmd) = { "?", CONFIG_SYS_MAXARGS, cmd_always_repeatable, do_help, @@ -35,3 +36,4 @@ ll_entry_declare(cmd_tbl_t, question_mark, cmd) = { "" #endif /* CONFIG_SYS_LONGHELP */ }; +#endif diff --git a/common/board_r.c b/common/board_r.c index ee4dcedd5f..84aec7fc71 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -49,7 +49,7 @@ #include <linux/err.h> #include <efi_loader.h> #include <wdt.h> -#if defined(CONFIG_DM_GPIO_HOG) +#if defined(CONFIG_GPIO_HOG) #include <asm/gpio.h> #endif @@ -799,7 +799,7 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CMD_NET initr_ethaddr, #endif -#if defined(CONFIG_DM_GPIO_HOG) +#if defined(CONFIG_GPIO_HOG) gpio_hog_probe_all, #endif #ifdef CONFIG_BOARD_LATE_INIT diff --git a/common/bootm.c b/common/bootm.c index bea516025f..4629cdd82d 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -7,17 +7,12 @@ #ifndef USE_HOSTCC #include <common.h> #include <bootstage.h> -#include <bzlib.h> #include <errno.h> #include <fdt_support.h> #include <lmb.h> #include <malloc.h> #include <mapmem.h> #include <asm/io.h> -#include <linux/lzo.h> -#include <lzma/LzmaTypes.h> -#include <lzma/LzmaDec.h> -#include <lzma/LzmaTools.h> #if defined(CONFIG_CMD_USB) #include <usb.h> #endif @@ -299,23 +294,7 @@ static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc, } #endif /* USE_HOSTC */ -/** - * print_decomp_msg() - Print a suitable decompression/loading message - * - * @type: OS type (IH_OS_...) - * @comp_type: Compression type being used (IH_COMP_...) - * @is_xip: true if the load address matches the image start - */ -static void print_decomp_msg(int comp_type, int type, bool is_xip) -{ - const char *name = genimg_get_type_name(type); - - if (comp_type == IH_COMP_NONE) - printf(" %s %s ... ", is_xip ? "XIP" : "Loading", name); - else - printf(" Uncompressing %s ... ", name); -} - +#if !defined(USE_HOSTCC) || defined(CONFIG_FIT_SIGNATURE) /** * handle_decomp_error() - display a decompression error * @@ -325,16 +304,18 @@ static void print_decomp_msg(int comp_type, int type, bool is_xip) * * @comp_type: Compression type being used (IH_COMP_...) * @uncomp_size: Number of bytes uncompressed - * @unc_len: Amount of space available for decompression - * @ret: Error code to report - * @return BOOTM_ERR_RESET, indicating that the board must be reset + * @ret: errno error code received from compression library + * @return Appropriate BOOTM_ERR_ error code */ -static int handle_decomp_error(int comp_type, size_t uncomp_size, - size_t unc_len, int ret) +static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret) { const char *name = genimg_get_comp_name(comp_type); - if (uncomp_size >= unc_len) + /* ENOSYS means unimplemented compression type, don't reset. */ + if (ret == -ENOSYS) + return BOOTM_ERR_UNIMPLEMENTED; + + if (uncomp_size >= CONFIG_SYS_BOOTM_LEN) printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n"); else printf("%s: uncompress error %d\n", name, ret); @@ -351,93 +332,7 @@ static int handle_decomp_error(int comp_type, size_t uncomp_size, return BOOTM_ERR_RESET; } - -int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, - void *load_buf, void *image_buf, ulong image_len, - uint unc_len, ulong *load_end) -{ - int ret = 0; - - *load_end = load; - print_decomp_msg(comp, type, load == image_start); - - /* - * Load the image to the right place, decompressing if needed. After - * this, image_len will be set to the number of uncompressed bytes - * loaded, ret will be non-zero on error. - */ - switch (comp) { - case IH_COMP_NONE: - if (load == image_start) - break; - if (image_len <= unc_len) - memmove_wd(load_buf, image_buf, image_len, CHUNKSZ); - else - ret = 1; - break; -#ifdef CONFIG_GZIP - case IH_COMP_GZIP: { - ret = gunzip(load_buf, unc_len, image_buf, &image_len); - break; - } -#endif /* CONFIG_GZIP */ -#ifdef CONFIG_BZIP2 - case IH_COMP_BZIP2: { - uint size = unc_len; - - /* - * If we've got less than 4 MB of malloc() space, - * use slower decompression algorithm which requires - * at most 2300 KB of memory. - */ - ret = BZ2_bzBuffToBuffDecompress(load_buf, &size, - image_buf, image_len, - CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); - image_len = size; - break; - } -#endif /* CONFIG_BZIP2 */ -#ifdef CONFIG_LZMA - case IH_COMP_LZMA: { - SizeT lzma_len = unc_len; - - ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len, - image_buf, image_len); - image_len = lzma_len; - break; - } -#endif /* CONFIG_LZMA */ -#ifdef CONFIG_LZO - case IH_COMP_LZO: { - size_t size = unc_len; - - ret = lzop_decompress(image_buf, image_len, load_buf, &size); - image_len = size; - break; - } -#endif /* CONFIG_LZO */ -#ifdef CONFIG_LZ4 - case IH_COMP_LZ4: { - size_t size = unc_len; - - ret = ulz4fn(image_buf, image_len, load_buf, &size); - image_len = size; - break; - } -#endif /* CONFIG_LZ4 */ - default: - printf("Unimplemented compression type %d\n", comp); - return BOOTM_ERR_UNIMPLEMENTED; - } - - if (ret) - return handle_decomp_error(comp, image_len, unc_len, ret); - *load_end = load + image_len; - - puts("OK\n"); - - return 0; -} +#endif #ifndef USE_HOSTCC static int bootm_load_os(bootm_headers_t *images, int boot_progress) @@ -456,10 +351,11 @@ static int bootm_load_os(bootm_headers_t *images, int boot_progress) load_buf = map_sysmem(load, 0); image_buf = map_sysmem(os.image_start, image_len); - err = bootm_decomp_image(os.comp, load, os.image_start, os.type, - load_buf, image_buf, image_len, - CONFIG_SYS_BOOTM_LEN, &load_end); + err = image_decomp(os.comp, load, os.image_start, os.type, + load_buf, image_buf, image_len, + CONFIG_SYS_BOOTM_LEN, &load_end); if (err) { + err = handle_decomp_error(os.comp, load_end - load, err); bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); return err; } @@ -919,11 +815,6 @@ void __weak switch_to_non_secure_mode(void) #else /* USE_HOSTCC */ -void memmove_wd(void *to, void *from, size_t len, ulong chunksz) -{ - memmove(to, from, len); -} - #if defined(CONFIG_FIT_SIGNATURE) static int bootm_host_load_image(const void *fit, int req_image_type) { @@ -957,13 +848,16 @@ static int bootm_host_load_image(const void *fit, int req_image_type) /* Allow the image to expand by a factor of 4, should be safe */ load_buf = malloc((1 << 20) + len * 4); - ret = bootm_decomp_image(imape_comp, 0, data, image_type, load_buf, - (void *)data, len, CONFIG_SYS_BOOTM_LEN, - &load_end); + ret = image_decomp(imape_comp, 0, data, image_type, load_buf, + (void *)data, len, CONFIG_SYS_BOOTM_LEN, + &load_end); free(load_buf); - if (ret && ret != BOOTM_ERR_UNIMPLEMENTED) - return ret; + if (ret) { + ret = handle_decomp_error(imape_comp, load_end - 0, ret); + if (ret != BOOTM_ERR_UNIMPLEMENTED) + return ret; + } return 0; } diff --git a/common/image-fit.c b/common/image-fit.c index a74b44f298..e346fed550 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -22,6 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ +#include <bootm.h> #include <image.h> #include <bootstage.h> #include <u-boot/crc.h> @@ -1521,6 +1522,10 @@ int fit_check_format(const void *fit) * compatible list, "foo,bar", matches a compatible string in the root of fdt1. * "bim,bam" in fdt2 matches the second string which isn't as good as fdt1. * + * As an optimization, the compatible property from the FDT's root node can be + * copied into the configuration node in the FIT image. This is required to + * match configurations with compressed FDTs. + * * returns: * offset to the configuration to use if one was found * -1 otherwise @@ -1553,48 +1558,62 @@ int fit_conf_find_compat(const void *fit, const void *fdt) for (noffset = fdt_next_node(fit, confs_noffset, &ndepth); (noffset >= 0) && (ndepth > 0); noffset = fdt_next_node(fit, noffset, &ndepth)) { - const void *kfdt; + const void *fdt; const char *kfdt_name; - int kfdt_noffset; + int kfdt_noffset, compat_noffset; const char *cur_fdt_compat; int len; - size_t size; + size_t sz; int i; if (ndepth > 1) continue; - kfdt_name = fdt_getprop(fit, noffset, "fdt", &len); - if (!kfdt_name) { - debug("No fdt property found.\n"); - continue; - } - kfdt_noffset = fdt_subnode_offset(fit, images_noffset, - kfdt_name); - if (kfdt_noffset < 0) { - debug("No image node named \"%s\" found.\n", - kfdt_name); - continue; - } - /* - * Get a pointer to this configuration's fdt. - */ - if (fit_image_get_data(fit, kfdt_noffset, &kfdt, &size)) { - debug("Failed to get fdt \"%s\".\n", kfdt_name); - continue; + /* If there's a compat property in the config node, use that. */ + if (fdt_getprop(fit, noffset, "compatible", NULL)) { + fdt = fit; /* search in FIT image */ + compat_noffset = noffset; /* search under config node */ + } else { /* Otherwise extract it from the kernel FDT. */ + kfdt_name = fdt_getprop(fit, noffset, "fdt", &len); + if (!kfdt_name) { + debug("No fdt property found.\n"); + continue; + } + kfdt_noffset = fdt_subnode_offset(fit, images_noffset, + kfdt_name); + if (kfdt_noffset < 0) { + debug("No image node named \"%s\" found.\n", + kfdt_name); + continue; + } + + if (!fit_image_check_comp(fit, kfdt_noffset, + IH_COMP_NONE)) { + debug("Can't extract compat from \"%s\" " + "(compressed)\n", kfdt_name); + continue; + } + + /* search in this config's kernel FDT */ + if (fit_image_get_data(fit, kfdt_noffset, &fdt, &sz)) { + debug("Failed to get fdt \"%s\".\n", kfdt_name); + continue; + } + + compat_noffset = 0; /* search kFDT under root node */ } len = fdt_compat_len; cur_fdt_compat = fdt_compat; /* * Look for a match for each U-Boot compatibility string in - * turn in this configuration's fdt. + * turn in the compat string property. */ for (i = 0; len > 0 && (!best_match_offset || best_match_pos > i); i++) { int cur_len = strlen(cur_fdt_compat) + 1; - if (!fdt_node_check_compatible(kfdt, 0, + if (!fdt_node_check_compatible(fdt, compat_noffset, cur_fdt_compat)) { best_match_offset = noffset; best_match_pos = i; @@ -1795,11 +1814,12 @@ int fit_image_load(bootm_headers_t *images, ulong addr, const char *fit_uname_config; const char *fit_base_uname_config; const void *fit; - const void *buf; + void *buf; + void *loadbuf; size_t size; int type_ok, os_ok; - ulong load, data, len; - uint8_t os; + ulong load, load_end, data, len; + uint8_t os, comp; #ifndef USE_HOSTCC uint8_t os_arch; #endif @@ -1895,12 +1915,6 @@ int fit_image_load(bootm_headers_t *images, ulong addr, images->os.arch = os_arch; #endif - if (image_type == IH_TYPE_FLATDT && - !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) { - puts("FDT image is compressed"); - return -EPROTONOSUPPORT; - } - bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL); type_ok = fit_image_check_type(fit, noffset, image_type) || fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) || @@ -1931,7 +1945,8 @@ int fit_image_load(bootm_headers_t *images, ulong addr, bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL_OK); /* get image data address and length */ - if (fit_image_get_data_and_size(fit, noffset, &buf, &size)) { + if (fit_image_get_data_and_size(fit, noffset, + (const void **)&buf, &size)) { printf("Could not find %s subimage data!\n", prop_name); bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA); return -ENOENT; @@ -1939,30 +1954,15 @@ int fit_image_load(bootm_headers_t *images, ulong addr, #if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS) /* perform any post-processing on the image data */ - board_fit_image_post_process((void **)&buf, &size); + board_fit_image_post_process(&buf, &size); #endif len = (ulong)size; - /* verify that image data is a proper FDT blob */ - if (image_type == IH_TYPE_FLATDT && fdt_check_header(buf)) { - puts("Subimage data is not a FDT"); - return -ENOEXEC; - } - bootstage_mark(bootstage_id + BOOTSTAGE_SUB_GET_DATA_OK); - /* - * Work-around for eldk-4.2 which gives this warning if we try to - * cast in the unmap_sysmem() call: - * warning: initialization discards qualifiers from pointer target type - */ - { - void *vbuf = (void *)buf; - - data = map_to_sysmem(vbuf); - } - + data = map_to_sysmem(buf); + load = data; if (load_op == FIT_LOAD_IGNORED) { /* Don't load */ } else if (fit_image_get_load(fit, noffset, &load)) { @@ -1974,8 +1974,6 @@ int fit_image_load(bootm_headers_t *images, ulong addr, } } else if (load_op != FIT_LOAD_OPTIONAL_NON_ZERO || load) { ulong image_start, image_end; - ulong load_end; - void *dst; /* * move image data to the load address, @@ -1993,14 +1991,45 @@ int fit_image_load(bootm_headers_t *images, ulong addr, printf(" Loading %s from 0x%08lx to 0x%08lx\n", prop_name, data, load); + } else { + load = data; /* No load address specified */ + } + + comp = IH_COMP_NONE; + loadbuf = buf; + /* Kernel images get decompressed later in bootm_load_os(). */ + if (!(image_type == IH_TYPE_KERNEL || + image_type == IH_TYPE_KERNEL_NOLOAD) && + !fit_image_get_comp(fit, noffset, &comp) && + comp != IH_COMP_NONE) { + ulong max_decomp_len = len * 20; + if (load == data) { + loadbuf = malloc(max_decomp_len); + load = map_to_sysmem(loadbuf); + } else { + loadbuf = map_sysmem(load, max_decomp_len); + } + if (image_decomp(comp, load, data, image_type, + loadbuf, buf, len, max_decomp_len, &load_end)) { + printf("Error decompressing %s\n", prop_name); - dst = map_sysmem(load, len); - memmove(dst, buf, len); - data = load; + return -ENOEXEC; + } + len = load_end - load; + } else if (load != data) { + loadbuf = map_sysmem(load, len); + memcpy(loadbuf, buf, len); } + + /* verify that image data is a proper FDT blob */ + if (image_type == IH_TYPE_FLATDT && fdt_check_header(loadbuf)) { + puts("Subimage data is not a FDT"); + return -ENOEXEC; + } + bootstage_mark(bootstage_id + BOOTSTAGE_SUB_LOAD); - *datap = data; + *datap = load; *lenp = len; if (fit_unamep) *fit_unamep = (char *)fit_uname; diff --git a/common/image.c b/common/image.c index 9f9538fac2..495883185d 100644 --- a/common/image.c +++ b/common/image.c @@ -32,6 +32,12 @@ #include <linux/errno.h> #include <asm/io.h> +#include <bzlib.h> +#include <linux/lzo.h> +#include <lzma/LzmaTypes.h> +#include <lzma/LzmaDec.h> +#include <lzma/LzmaTools.h> + #ifdef CONFIG_CMD_BDI extern int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif @@ -375,6 +381,106 @@ void image_print_contents(const void *ptr) } } +/** + * print_decomp_msg() - Print a suitable decompression/loading message + * + * @type: OS type (IH_OS_...) + * @comp_type: Compression type being used (IH_COMP_...) + * @is_xip: true if the load address matches the image start + */ +static void print_decomp_msg(int comp_type, int type, bool is_xip) +{ + const char *name = genimg_get_type_name(type); + + if (comp_type == IH_COMP_NONE) + printf(" %s %s\n", is_xip ? "XIP" : "Loading", name); + else + printf(" Uncompressing %s\n", name); +} + +int image_decomp(int comp, ulong load, ulong image_start, int type, + void *load_buf, void *image_buf, ulong image_len, + uint unc_len, ulong *load_end) +{ + int ret = 0; + + *load_end = load; + print_decomp_msg(comp, type, load == image_start); + + /* + * Load the image to the right place, decompressing if needed. After + * this, image_len will be set to the number of uncompressed bytes + * loaded, ret will be non-zero on error. + */ + switch (comp) { + case IH_COMP_NONE: + if (load == image_start) + break; + if (image_len <= unc_len) + memmove_wd(load_buf, image_buf, image_len, CHUNKSZ); + else + ret = -ENOSPC; + break; +#ifdef CONFIG_GZIP + case IH_COMP_GZIP: { + ret = gunzip(load_buf, unc_len, image_buf, &image_len); + break; + } +#endif /* CONFIG_GZIP */ +#ifdef CONFIG_BZIP2 + case IH_COMP_BZIP2: { + uint size = unc_len; + + /* + * If we've got less than 4 MB of malloc() space, + * use slower decompression algorithm which requires + * at most 2300 KB of memory. + */ + ret = BZ2_bzBuffToBuffDecompress(load_buf, &size, + image_buf, image_len, + CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0); + image_len = size; + break; + } +#endif /* CONFIG_BZIP2 */ +#ifdef CONFIG_LZMA + case IH_COMP_LZMA: { + SizeT lzma_len = unc_len; + + ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len, + image_buf, image_len); + image_len = lzma_len; + break; + } +#endif /* CONFIG_LZMA */ +#ifdef CONFIG_LZO + case IH_COMP_LZO: { + size_t size = unc_len; + + ret = lzop_decompress(image_buf, image_len, load_buf, &size); + image_len = size; + break; + } +#endif /* CONFIG_LZO */ +#ifdef CONFIG_LZ4 + case IH_COMP_LZ4: { + size_t size = unc_len; + + ret = ulz4fn(image_buf, image_len, load_buf, &size); + image_len = size; + break; + } +#endif /* CONFIG_LZ4 */ + default: + printf("Unimplemented compression type %d\n", comp); + return -ENOSYS; + } + + *load_end = load + image_len; + + return ret; +} + #ifndef USE_HOSTCC #if CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT) @@ -551,6 +657,11 @@ void memmove_wd(void *to, void *from, size_t len, ulong chunksz) memmove(to, from, len); #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ } +#else /* USE_HOSTCC */ +void memmove_wd(void *to, void *from, size_t len, ulong chunksz) +{ + memmove(to, from, len); +} #endif /* !USE_HOSTCC */ void genimg_print_size(uint32_t size) diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig new file mode 100644 index 0000000000..b326231b68 --- /dev/null +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_ZYNQMP_TWO_SDHCI=y +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=0 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_TEXT_BASE=0xfffc0000 +CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK_ZYNQMP=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 33253b1332..51c37e2e1a 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -111,6 +111,7 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_E1000=y +CONFIG_RTC_RX8025=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig deleted file mode 100644 index f7054b4a1e..0000000000 --- a/configs/da850_am18xxevm_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_DAVINCI=y -CONFIG_SYS_TEXT_BASE=0xc1080000 -CONFIG_TARGET_DA850EVM=y -CONFIG_MAC_ADDR_IN_EEPROM=y -CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x800 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50" -CONFIG_BOOTDELAY=3 -CONFIG_MISC_INIT_R=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_TEXT_BASE=0x80000000 -CONFIG_SPL_SPI_LOAD=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="U-Boot > " -CONFIG_CRC32_VERIFY=y -# CONFIG_CMD_EEPROM is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_GPIO is not set -# CONFIG_CMD_GPT is not set -# CONFIG_CMD_PART is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_TIME is not set -# CONFIG_CMD_EXT4 is not set -# CONFIG_CMD_FS_GENERIC is not set -CONFIG_CMD_DIAG=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="da850-evm" -CONFIG_SPL_OF_PLATDATA=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_DM=y -CONFIG_SPL_DM=y -CONFIG_DA8XX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y -CONFIG_SYS_I2C_DAVINCI=y -CONFIG_MTD_DEVICE=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_DM_SERIAL=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_DAVINCI_SPI=y -CONFIG_USB=y -CONFIG_DM_USB=y -# CONFIG_SPL_DM_USB is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_DA8XX=y -CONFIG_USB_STORAGE=y -# CONFIG_FAT_WRITE is not set diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 99300cb297..7de1d2ffc4 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -52,6 +52,7 @@ CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_DM_MMC=y +CONFIG_MTD=y CONFIG_MTD_DEVICE=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index dcb4d96d0d..e3c2d13986 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -42,6 +42,7 @@ CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DAVINCI=y # CONFIG_MMC is not set +CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 7065205783..96602e514a 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 5e6bb54551..0eb7384340 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set +# CONFIG_SPL_SYSRESET is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 921af0d476..a76ae9d326 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set +# CONFIG_SPL_SYSRESET is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 466ae860cd..26b4950f8f 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -18,6 +18,7 @@ CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_TEXT_BASE=0x80000000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5 CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -26,33 +27,35 @@ CONFIG_CRC32_VERIFY=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPIO is not set CONFIG_CMD_NAND=y +# CONFIG_CMD_SPI is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MTDPARTS=y CONFIG_CMD_DIAG=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="da850-lcdk" +CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_DM_MMC=y +CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000 CONFIG_SPL_NAND_SIMPLE=y -CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y +CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_DAVINCI_SPI=y +CONFIG_USE_TINY_PRINTF=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/pumpkin_defconfig b/configs/pumpkin_defconfig new file mode 100644 index 0000000000..d3d695fa13 --- /dev/null +++ b/configs/pumpkin_defconfig @@ -0,0 +1,65 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_SYS_TEXT_BASE=0x4C000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_MT8516=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0x11005000 +CONFIG_DEBUG_UART_CLOCK=26000000 +# CONFIG_PSCI_RESET is not set +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_MISC is not set +CONFIG_DEFAULT_DEVICE_TREE="mt8516-pumpkin" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +# CONFIG_NET is not set +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +# CONFIG_INPUT is not set +CONFIG_DM_MMC=y +# CONFIG_MMC_QUIRKS is not set +CONFIG_MMC_MTK=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT8516=y +CONFIG_RAM=y +CONFIG_BAUDRATE=921600 +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_MTK=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_MTK_SERIAL=y +CONFIG_WDT=y +CONFIG_WDT_MTK=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 827b8761cd..c177ff8ad5 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -89,7 +89,6 @@ CONFIG_BOARD=y CONFIG_BOARD_SANDBOX=y CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 62594e3c21..aa09c4571a 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -107,7 +107,6 @@ CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_SANDBOX=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 2429ae4621..a70793b7ad 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -75,7 +75,6 @@ CONFIG_BOARD=y CONFIG_BOARD_SANDBOX=y CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index da9229fc79..381bad2003 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -81,7 +81,6 @@ CONFIG_BOARD=y CONFIG_BOARD_SANDBOX=y CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 27034cfaa9..b715c3f0f0 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -3,6 +3,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_FIRMWARE=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_BOOTSTAGE_STASH_ADDR=0x0 @@ -95,7 +96,6 @@ CONFIG_BOARD=y CONFIG_BOARD_SANDBOX=y CONFIG_PM8916_GPIO=y CONFIG_SANDBOX_GPIO=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 2d5e158871..1dadc122cf 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_RTC_RX8025=y CONFIG_SYS_NS16550=y CONFIG_USB=y # CONFIG_USB_EHCI_HCD is not set diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index aa73661a92..4808b49850 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -12,7 +12,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_IP_DEFRAG=y # CONFIG_UDP_FUNCTION_FASTBOOT is not set CONFIG_SANDBOX_GPIO=y -CONFIG_DM_I2C_COMPAT=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCI_SANDBOX=y diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 77c7904a2c..f6b9eb6c2c 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -114,6 +114,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_TSEC_ENET=y +CONFIG_RTC_RX8025=y CONFIG_BAUDRATE=9600 CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig index ed6c1b8296..c73a97a050 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig @@ -30,7 +30,7 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA" CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y CONFIG_FPGA_XILINX=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig index 0c2491aceb..0d4302ea73 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig @@ -31,7 +31,7 @@ CONFIG_CMD_SF=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revB" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_CLK_ZYNQMP=y diff --git a/doc/README.gpt b/doc/README.gpt index 62013a3f89..facd7afc3a 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -229,7 +229,7 @@ U-BOOT> gpt rename mmc 0 1 primary The GPT functionality may be tested with the 'sandbox' board by creating a disk image as described under 'Block Device Emulation' in -board/sandbox/README.sandbox: +doc/arch/index.rst: =>host bind 0 ./disk.raw => gpt read host 0 diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst new file mode 100644 index 0000000000..d8f7d155fc --- /dev/null +++ b/doc/board/AndesTech/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Andes Tech +========== + +.. toctree:: + :maxdepth: 2 + + adp-ag101p + ax25-ae350 diff --git a/doc/board/atmel/index.rst b/doc/board/atmel/index.rst new file mode 100644 index 0000000000..8ba00fc227 --- /dev/null +++ b/doc/board/atmel/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Atmel +===== + +.. toctree:: + :maxdepth: 2 + + at91ek diff --git a/doc/board/freescale/index.rst b/doc/board/freescale/index.rst new file mode 100644 index 0000000000..8d42b35b96 --- /dev/null +++ b/doc/board/freescale/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Freescale +========= + +.. toctree:: + :maxdepth: 2 + + b4860qds diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst new file mode 100644 index 0000000000..34e62baff6 --- /dev/null +++ b/doc/board/renesas/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +======= + +.. toctree:: + :maxdepth: 2 + + sh7752evb + sh7753evb diff --git a/doc/board/sifive/index.rst b/doc/board/sifive/index.rst new file mode 100644 index 0000000000..ad614c9bf2 --- /dev/null +++ b/doc/board/sifive/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +SiFive +====== + +.. toctree:: + :maxdepth: 2 + + fu540 diff --git a/doc/board/xilinx/index.rst b/doc/board/xilinx/index.rst new file mode 100644 index 0000000000..2416fbd216 --- /dev/null +++ b/doc/board/xilinx/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Xilinx +====== + +.. toctree:: + :maxdepth: 2 + + zynq diff --git a/doc/device-tree-bindings/gpio/gpio.txt b/doc/device-tree-bindings/gpio/gpio.txt index e774439369..e146917ff3 100644 --- a/doc/device-tree-bindings/gpio/gpio.txt +++ b/doc/device-tree-bindings/gpio/gpio.txt @@ -252,6 +252,7 @@ Example: boot_rescue { gpio-hog; input; + line-name = "foo-bar-gpio"; gpios = <7 GPIO_ACTIVE_LOW>; }; }; @@ -259,9 +260,13 @@ Example: For the above Example you can than access the gpio in your boardcode with: - desc = gpio_hog_lookup_name("boot_rescue.gpio-hog"); - if (desc) { - if (dm_gpio_get_value(desc)) - printf("\nBooting into Rescue System\n"); - else - printf("\nBoot normal\n"); + struct gpio_desc *desc; + int ret; + + ret = gpio_hog_lookup_name("boot_rescue", &desc); + if (ret) + return; + if (dm_gpio_get_value(desc) == 1) + printf("\nBooting into Rescue System\n"); + else if (dm_gpio_get_value(desc) == 0) + printf("\nBoot normal\n"); diff --git a/doc/uImage.FIT/kernel_fdts_compressed.its b/doc/uImage.FIT/kernel_fdts_compressed.its new file mode 100644 index 0000000000..8f81106efc --- /dev/null +++ b/doc/uImage.FIT/kernel_fdts_compressed.its @@ -0,0 +1,73 @@ +/* + * U-Boot uImage source file with a kernel and multiple compressed FDT blobs. + * Since the FDTs are compressed, configurations must provide a compatible + * string to match directly. + */ + +/dts-v1/; + +/ { + description = "Image with single Linux kernel and compressed FDT blobs"; + #address-cells = <1>; + + images { + kernel { + description = "Vanilla Linux kernel"; + data = /incbin/("./vmlinux.bin.gz"); + type = "kernel"; + arch = "ppc"; + os = "linux"; + compression = "gzip"; + load = <00000000>; + entry = <00000000>; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha1"; + }; + }; + fdt@1 { + description = "Flattened Device Tree blob 1"; + data = /incbin/("./myboard-var1.dtb"); + type = "flat_dt"; + arch = "ppc"; + compression = "gzip"; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha1"; + }; + }; + fdt@2 { + description = "Flattened Device Tree blob 2"; + data = /incbin/("./myboard-var2.dtb"); + type = "flat_dt"; + arch = "ppc"; + compression = "lzma"; + hash-1 { + algo = "crc32"; + }; + hash-2 { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "conf@1"; + conf@1 { + description = "Boot Linux kernel with FDT blob 1"; + kernel = "kernel"; + fdt = "fdt@1"; + compatible = "myvendor,myboard-variant1"; + }; + conf@2 { + description = "Boot Linux kernel with FDT blob 2"; + kernel = "kernel"; + fdt = "fdt@2"; + compatible = "myvendor,myboard-variant2"; + }; + }; +}; diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index d701b9bb76..f8e27ed34e 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -240,6 +240,7 @@ o config-1 |- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...] |- fpga = "fpga sub-node unit-name" |- loadables = "loadables sub-node unit-name" + |- compatible = "vendor,board-style device tree compatible string" Mandatory properties: @@ -263,6 +264,12 @@ o config-1 of strings. U-Boot will load each binary at its given start-address and may optionaly invoke additional post-processing steps on this binary based on its component image node type. + - compatible : The root compatible string of the U-Boot device tree that + this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is + enabled. If this property is not provided, the compatible string will be + extracted from the fdt blob instead. This is only possible if the fdt is + not compressed, so images with compressed fdts that want to use compatible + string matching must always provide this property. The FDT blob is required to properly boot FDT based kernel, so the minimal configuration for 2.6 FDT kernel is (kernel, fdt) pair. diff --git a/drivers/Makefile b/drivers/Makefile index 603aa98590..41933605ce 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -4,7 +4,9 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/ -obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ +obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ +obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/ +obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ @@ -81,7 +83,6 @@ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-$(CONFIG_FASTBOOT) += fastboot/ -obj-y += firmware/ obj-$(CONFIG_FPGA) += fpga/ obj-y += misc/ obj-$(CONFIG_MMC) += mmc/ @@ -96,7 +97,6 @@ obj-y += rtc/ obj-y += scsi/ obj-y += sound/ obj-y += spmi/ -obj-y += sysreset/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 9bb9959c9d..dda686cfb3 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -562,6 +562,9 @@ static int rk3188_clk_probe(struct udevice *dev) #endif rkclk_init(priv->cru, priv->grf, priv->has_bwadj); + + /* Init CPU frequency */ + rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj); #endif return 0; diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 0e4526288e..b85b56efe5 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -9,31 +9,27 @@ #include <errno.h> #include "sequencer.h" -static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = +static const struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = (struct socfpga_sdr_rw_load_manager *) (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800); -static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs = - (struct socfpga_sdr_rw_load_jump_manager *) +static const struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs + = (struct socfpga_sdr_rw_load_jump_manager *) (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00); -static struct socfpga_sdr_reg_file *sdr_reg_file = +static const struct socfpga_sdr_reg_file *sdr_reg_file = (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS; -static struct socfpga_sdr_scc_mgr *sdr_scc_mgr = +static const struct socfpga_sdr_scc_mgr *sdr_scc_mgr = (struct socfpga_sdr_scc_mgr *) (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00); -static struct socfpga_phy_mgr_cmd *phy_mgr_cmd = +static const struct socfpga_phy_mgr_cmd *phy_mgr_cmd = (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS; -static struct socfpga_phy_mgr_cfg *phy_mgr_cfg = +static const struct socfpga_phy_mgr_cfg *phy_mgr_cfg = (struct socfpga_phy_mgr_cfg *) (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40); -static struct socfpga_data_mgr *data_mgr = +static const struct socfpga_data_mgr *data_mgr = (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = +static const struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; -const struct socfpga_sdram_rw_mgr_config *rwcfg; -const struct socfpga_sdram_io_config *iocfg; -const struct socfpga_sdram_misc_config *misccfg; - #define DELTA_D 1 /* @@ -55,37 +51,20 @@ const struct socfpga_sdram_misc_config *misccfg; #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \ STATIC_SKIP_DELAY_LOOPS) -/* calibration steps requested by the rtl */ -static u16 dyn_calib_steps; - -/* - * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option - * instead of static, we use boolean logic to select between - * non-skip and skip values - * - * The mask is set to include all bits when not-skipping, but is - * zero when skipping - */ - -static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ - #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \ - ((non_skip_value) & skip_delay_mask) - -static struct gbl_type *gbl; -static struct param_type *param; + ((non_skip_value) & seq->skip_delay_mask) -static void set_failing_group_stage(u32 group, u32 stage, - u32 substage) +static void set_failing_group_stage(struct socfpga_sdrseq *seq, + u32 group, u32 stage, u32 substage) { /* * Only set the global stage if there was not been any other * failing group */ - if (gbl->error_stage == CAL_STAGE_NIL) { - gbl->error_substage = substage; - gbl->error_stage = stage; - gbl->error_group = group; + if (seq->gbl.error_stage == CAL_STAGE_NIL) { + seq->gbl.error_substage = substage; + seq->gbl.error_stage = stage; + seq->gbl.error_group = group; } } @@ -110,7 +89,7 @@ static void reg_file_set_sub_stage(u8 set_sub_stage) * * Initialize PHY Manager. */ -static void phy_mgr_initialize(void) +static void phy_mgr_initialize(struct socfpga_sdrseq *seq) { u32 ratio; @@ -132,15 +111,17 @@ static void phy_mgr_initialize(void) writel(0, &phy_mgr_cfg->cal_debug_info); /* Init params only if we do NOT skip calibration. */ - if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) + if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) return; - ratio = rwcfg->mem_dq_per_read_dqs / - rwcfg->mem_virtual_groups_per_read_dqs; - param->read_correct_mask_vg = (1 << ratio) - 1; - param->write_correct_mask_vg = (1 << ratio) - 1; - param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1; - param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1; + ratio = seq->rwcfg->mem_dq_per_read_dqs / + seq->rwcfg->mem_virtual_groups_per_read_dqs; + seq->param.read_correct_mask_vg = (1 << ratio) - 1; + seq->param.write_correct_mask_vg = (1 << ratio) - 1; + seq->param.read_correct_mask = (1 << seq->rwcfg->mem_dq_per_read_dqs) + - 1; + seq->param.write_correct_mask = (1 << seq->rwcfg->mem_dq_per_write_dqs) + - 1; } /** @@ -150,7 +131,8 @@ static void phy_mgr_initialize(void) * * Set Rank and ODT mask (On-Die Termination). */ -static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) +static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq, + const u32 rank, const u32 odt_mode) { u32 odt_mask_0 = 0; u32 odt_mask_1 = 0; @@ -160,14 +142,14 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) odt_mask_0 = 0x0; odt_mask_1 = 0x0; } else { /* RW_MGR_ODT_MODE_READ_WRITE */ - switch (rwcfg->mem_number_of_ranks) { + switch (seq->rwcfg->mem_number_of_ranks) { case 1: /* 1 Rank */ /* Read: ODT = 0 ; Write: ODT = 1 */ odt_mask_0 = 0x0; odt_mask_1 = 0x1; break; case 2: /* 2 Ranks */ - if (rwcfg->mem_number_of_cs_per_dimm == 1) { + if (seq->rwcfg->mem_number_of_cs_per_dimm == 1) { /* * - Dual-Slot , Single-Rank (1 CS per DIMM) * OR @@ -307,16 +289,18 @@ static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay) scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); } -static void scc_mgr_set_dqs_io_in_delay(u32 delay) +static void scc_mgr_set_dqs_io_in_delay(struct socfpga_sdrseq *seq, + u32 delay) { - scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, - delay); + scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, + seq->rwcfg->mem_dq_per_write_dqs, delay); } -static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay) +static void scc_mgr_set_dm_in_delay(struct socfpga_sdrseq *seq, u32 dm, + u32 delay) { scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, - rwcfg->mem_dq_per_write_dqs + 1 + dm, + seq->rwcfg->mem_dq_per_write_dqs + 1 + dm, delay); } @@ -325,16 +309,18 @@ static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay) scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay); } -static void scc_mgr_set_dqs_out1_delay(u32 delay) +static void scc_mgr_set_dqs_out1_delay(struct socfpga_sdrseq *seq, + u32 delay) { - scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, - delay); + scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, + seq->rwcfg->mem_dq_per_write_dqs, delay); } -static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay) +static void scc_mgr_set_dm_out1_delay(struct socfpga_sdrseq *seq, u32 dm, + u32 delay) { scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, - rwcfg->mem_dq_per_write_dqs + 1 + dm, + seq->rwcfg->mem_dq_per_write_dqs + 1 + dm, delay); } @@ -372,12 +358,13 @@ static void scc_mgr_load_dm(u32 dm) * This function sets the SCC Manager (Scan Chain Control Manager) register * and optionally triggers the SCC update for all ranks. */ -static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val, +static void scc_mgr_set_all_ranks(struct socfpga_sdrseq *seq, + const u32 off, const u32 grp, const u32 val, const int update) { u32 r; - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { scc_mgr_set(off, grp, val); @@ -388,7 +375,8 @@ static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val, } } -static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) +static void scc_mgr_set_dqs_en_phase_all_ranks(struct socfpga_sdrseq *seq, + u32 read_group, u32 phase) { /* * USER although the h/w doesn't support different phases per @@ -398,12 +386,12 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) * for efficiency, the scan chain update should occur only * once to sr0. */ - scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET, + scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase, 0); } -static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group, - u32 phase) +static void scc_mgr_set_dqdqs_output_phase_all_ranks(struct socfpga_sdrseq *seq, + u32 write_group, u32 phase) { /* * USER although the h/w doesn't support different phases per @@ -413,12 +401,12 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group, * for efficiency, the scan chain update should occur only * once to sr0. */ - scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, + scc_mgr_set_all_ranks(seq, SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase, 0); } -static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, - u32 delay) +static void scc_mgr_set_dqs_en_delay_all_ranks(struct socfpga_sdrseq *seq, + u32 read_group, u32 delay) { /* * In shadow register mode, the T11 settings are stored in @@ -428,7 +416,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, * select_shadow_regs_for_update with update_scan_chains * set to 0. */ - scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET, + scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay, 1); } @@ -439,10 +427,11 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, * * This function sets the OCT output delay in SCC manager. */ -static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay) +static void scc_mgr_set_oct_out1_delay(struct socfpga_sdrseq *seq, + const u32 write_group, const u32 delay) { - const int ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; + const int ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; const int base = write_group * ratio; int i; /* @@ -490,7 +479,7 @@ static void scc_mgr_set_hhp_extras(void) * * Zero all DQS config. */ -static void scc_mgr_zero_all(void) +static void scc_mgr_zero_all(struct socfpga_sdrseq *seq) { int i, r; @@ -498,23 +487,26 @@ static void scc_mgr_zero_all(void) * USER Zero all DQS config settings, across all groups and all * shadow registers */ - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { /* * The phases actually don't exist on a per-rank basis, * but there's no harm updating them several times, so * let's keep the code simple. */ - scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve); + scc_mgr_set_dqs_bus_in_delay(i, + seq->iocfg->dqs_in_reserve + ); scc_mgr_set_dqs_en_phase(i, 0); scc_mgr_set_dqs_en_delay(i, 0); } - for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) { scc_mgr_set_dqdqs_output_phase(i, 0); /* Arria V/Cyclone V don't have out2. */ - scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve); + scc_mgr_set_oct_out1_delay(seq, i, + seq->iocfg->dqs_out_reserve); } } @@ -551,10 +543,11 @@ static void scc_set_bypass_mode(const u32 write_group) * * Load DQS settings for Write Group, do not trigger SCC update. */ -static void scc_mgr_load_dqs_for_write_group(const u32 write_group) +static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq, + const u32 write_group) { - const int ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; + const int ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; const int base = write_group * ratio; int i; /* @@ -573,14 +566,15 @@ static void scc_mgr_load_dqs_for_write_group(const u32 write_group) * * Zero DQ, DM, DQS and OCT configs for a group. */ -static void scc_mgr_zero_group(const u32 write_group, const int out_only) +static void scc_mgr_zero_group(struct socfpga_sdrseq *seq, + const u32 write_group, const int out_only) { int i, r; - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { /* Zero all DQ config settings. */ - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) { scc_mgr_set_dq_out1_delay(i, 0); if (!out_only) scc_mgr_set_dq_in_delay(i, 0); @@ -592,8 +586,8 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) /* Zero all DM config settings. */ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { if (!out_only) - scc_mgr_set_dm_in_delay(i, 0); - scc_mgr_set_dm_out1_delay(i, 0); + scc_mgr_set_dm_in_delay(seq, i, 0); + scc_mgr_set_dm_out1_delay(seq, i, 0); } /* Multicast to all DM enables. */ @@ -601,12 +595,13 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) /* Zero all DQS IO settings. */ if (!out_only) - scc_mgr_set_dqs_io_in_delay(0); + scc_mgr_set_dqs_io_in_delay(seq, 0); /* Arria V/Cyclone V don't have out2. */ - scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve); - scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve); - scc_mgr_load_dqs_for_write_group(write_group); + scc_mgr_set_dqs_out1_delay(seq, seq->iocfg->dqs_out_reserve); + scc_mgr_set_oct_out1_delay(seq, write_group, + seq->iocfg->dqs_out_reserve); + scc_mgr_load_dqs_for_write_group(seq, write_group); /* Multicast to all DQS IO enables (only 1 in total). */ writel(0, &sdr_scc_mgr->dqs_io_ena); @@ -620,69 +615,76 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) * apply and load a particular input delay for the DQ pins in a group * group_bgn is the index of the first dq pin (in the write group) */ -static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay) +static void scc_mgr_apply_group_dq_in_delay(struct socfpga_sdrseq *seq, + u32 group_bgn, u32 delay) { u32 i, p; - for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) { + for (i = 0, p = group_bgn; i < seq->rwcfg->mem_dq_per_read_dqs; + i++, p++) { scc_mgr_set_dq_in_delay(p, delay); scc_mgr_load_dq(p); } } /** - * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group + * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the + * DQ pins in a group * @delay: Delay value * * Apply and load a particular output delay for the DQ pins in a group. */ -static void scc_mgr_apply_group_dq_out1_delay(const u32 delay) +static void scc_mgr_apply_group_dq_out1_delay(struct socfpga_sdrseq *seq, + const u32 delay) { int i; - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) { scc_mgr_set_dq_out1_delay(i, delay); scc_mgr_load_dq(i); } } /* apply and load a particular output delay for the DM pins in a group */ -static void scc_mgr_apply_group_dm_out1_delay(u32 delay1) +static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq, + u32 delay1) { u32 i; for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { - scc_mgr_set_dm_out1_delay(i, delay1); + scc_mgr_set_dm_out1_delay(seq, i, delay1); scc_mgr_load_dm(i); } } /* apply and load delay on both DQS and OCT out1 */ -static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group, - u32 delay) +static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq, + u32 write_group, u32 delay) { - scc_mgr_set_dqs_out1_delay(delay); + scc_mgr_set_dqs_out1_delay(seq, delay); scc_mgr_load_dqs_io(); - scc_mgr_set_oct_out1_delay(write_group, delay); - scc_mgr_load_dqs_for_write_group(write_group); + scc_mgr_set_oct_out1_delay(seq, write_group, delay); + scc_mgr_load_dqs_for_write_group(seq, write_group); } /** - * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT + * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output + * side: DQ, DM, DQS, OCT * @write_group: Write group * @delay: Delay value * * Apply a delay to the entire output side: DQ, DM, DQS, OCT. */ -static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group, +static void scc_mgr_apply_group_all_out_delay_add(struct socfpga_sdrseq *seq, + const u32 write_group, const u32 delay) { u32 i, new_delay; /* DQ shift */ - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) scc_mgr_load_dq(i); /* DM shift */ @@ -691,49 +693,51 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group, /* DQS shift */ new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay; - if (new_delay > iocfg->io_out2_delay_max) { + if (new_delay > seq->iocfg->io_out2_delay_max) { debug_cond(DLEVEL >= 1, "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n", __func__, __LINE__, write_group, delay, new_delay, - iocfg->io_out2_delay_max, - new_delay - iocfg->io_out2_delay_max); - new_delay -= iocfg->io_out2_delay_max; - scc_mgr_set_dqs_out1_delay(new_delay); + seq->iocfg->io_out2_delay_max, + new_delay - seq->iocfg->io_out2_delay_max); + new_delay -= seq->iocfg->io_out2_delay_max; + scc_mgr_set_dqs_out1_delay(seq, new_delay); } scc_mgr_load_dqs_io(); /* OCT shift */ new_delay = READ_SCC_OCT_OUT2_DELAY + delay; - if (new_delay > iocfg->io_out2_delay_max) { + if (new_delay > seq->iocfg->io_out2_delay_max) { debug_cond(DLEVEL >= 1, "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n", __func__, __LINE__, write_group, delay, - new_delay, iocfg->io_out2_delay_max, - new_delay - iocfg->io_out2_delay_max); - new_delay -= iocfg->io_out2_delay_max; - scc_mgr_set_oct_out1_delay(write_group, new_delay); + new_delay, seq->iocfg->io_out2_delay_max, + new_delay - seq->iocfg->io_out2_delay_max); + new_delay -= seq->iocfg->io_out2_delay_max; + scc_mgr_set_oct_out1_delay(seq, write_group, new_delay); } - scc_mgr_load_dqs_for_write_group(write_group); + scc_mgr_load_dqs_for_write_group(seq, write_group); } /** - * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks + * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output + * side to all ranks * @write_group: Write group * @delay: Delay value * * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks. */ static void -scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group, +scc_mgr_apply_group_all_out_delay_add_all_ranks(struct socfpga_sdrseq *seq, + const u32 write_group, const u32 delay) { int r; - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { - scc_mgr_apply_group_all_out_delay_add(write_group, delay); + scc_mgr_apply_group_all_out_delay_add(seq, write_group, delay); writel(0, &sdr_scc_mgr->update); } } @@ -744,7 +748,7 @@ scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group, * Optimization used to recover some slots in ddr3 inst_rom could be * applied to other protocols if we wanted to */ -static void set_jump_as_return(void) +static void set_jump_as_return(struct socfpga_sdrseq *seq) { /* * To save space, we replace return with jump to special shared @@ -752,7 +756,7 @@ static void set_jump_as_return(void) * we always jump. */ writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); + writel(seq->rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); } /** @@ -761,7 +765,8 @@ static void set_jump_as_return(void) * * Delay for N memory clocks. */ -static void delay_for_n_mem_clocks(const u32 clocks) +static void delay_for_n_mem_clocks(struct socfpga_sdrseq *seq, + const u32 clocks) { u32 afi_clocks; u16 c_loop; @@ -771,7 +776,7 @@ static void delay_for_n_mem_clocks(const u32 clocks) debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks); /* Scale (rounding up) to get afi clocks. */ - afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio); + afi_clocks = DIV_ROUND_UP(clocks, seq->misccfg->afi_rate_ratio); if (afi_clocks) /* Temporary underflow protection */ afi_clocks--; @@ -807,10 +812,10 @@ static void delay_for_n_mem_clocks(const u32 clocks) writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->idle_loop1, + writel(seq->rwcfg->idle_loop1, &sdr_rw_load_jump_mgr_regs->load_jump_add1); - writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | + writel(seq->rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); } else { writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), @@ -819,14 +824,14 @@ static void delay_for_n_mem_clocks(const u32 clocks) writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->idle_loop2, + writel(seq->rwcfg->idle_loop2, &sdr_rw_load_jump_mgr_regs->load_jump_add0); - writel(rwcfg->idle_loop2, + writel(seq->rwcfg->idle_loop2, &sdr_rw_load_jump_mgr_regs->load_jump_add1); do { - writel(rwcfg->idle_loop2, + writel(seq->rwcfg->idle_loop2, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); } while (c_loop-- != 0); @@ -843,7 +848,8 @@ static void delay_for_n_mem_clocks(const u32 clocks) * * Load instruction registers. */ -static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) +static void rw_mgr_mem_init_load_regs(struct socfpga_sdrseq *seq, + u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) { u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; @@ -873,58 +879,59 @@ static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) * * Load user calibration values and optionally precharge the banks. */ -static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, +static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq, + const u32 fin1, const u32 fin2, const int precharge) { u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; u32 r; - for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) { /* set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF); /* precharge all banks ... */ if (precharge) - writel(rwcfg->precharge_all, grpaddr); + writel(seq->rwcfg->precharge_all, grpaddr); /* * USER Use Mirror-ed commands for odd ranks if address * mirrorring is on */ - if ((rwcfg->mem_address_mirroring >> r) & 0x1) { - set_jump_as_return(); - writel(rwcfg->mrs2_mirr, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs3_mirr, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs1_mirr, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); + if ((seq->rwcfg->mem_address_mirroring >> r) & 0x1) { + set_jump_as_return(seq); + writel(seq->rwcfg->mrs2_mirr, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs3_mirr, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs1_mirr, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); writel(fin1, grpaddr); } else { - set_jump_as_return(); - writel(rwcfg->mrs2, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs3, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs1, grpaddr); - set_jump_as_return(); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs2, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs3, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs1, grpaddr); + set_jump_as_return(seq); writel(fin2, grpaddr); } if (precharge) continue; - set_jump_as_return(); - writel(rwcfg->zqcl, grpaddr); + set_jump_as_return(seq); + writel(seq->rwcfg->zqcl, grpaddr); /* tZQinit = tDLLK = 512 ck cycles */ - delay_for_n_mem_clocks(512); + delay_for_n_mem_clocks(seq, 512); } } @@ -933,7 +940,7 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, * * Initialize RW Manager. */ -static void rw_mgr_mem_initialize(void) +static void rw_mgr_mem_initialize(struct socfpga_sdrseq *seq) { debug("%s:%d\n", __func__, __LINE__); @@ -964,10 +971,10 @@ static void rw_mgr_mem_initialize(void) * One possible solution is n = 0 , a = 256 , b = 106 => a = FF, * b = 6A */ - rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, - misccfg->tinit_cntr1_val, - misccfg->tinit_cntr2_val, - rwcfg->init_reset_0_cke_0); + rw_mgr_mem_init_load_regs(seq, seq->misccfg->tinit_cntr0_val, + seq->misccfg->tinit_cntr1_val, + seq->misccfg->tinit_cntr2_val, + seq->rwcfg->init_reset_0_cke_0); /* Indicate that memory is stable. */ writel(1, &phy_mgr_cfg->reset_mem_stbl); @@ -986,18 +993,18 @@ static void rw_mgr_mem_initialize(void) * One possible solution is n = 2 , a = 131 , b = 256 => a = 83, * b = FF */ - rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, - misccfg->treset_cntr1_val, - misccfg->treset_cntr2_val, - rwcfg->init_reset_1_cke_0); + rw_mgr_mem_init_load_regs(seq, seq->misccfg->treset_cntr0_val, + seq->misccfg->treset_cntr1_val, + seq->misccfg->treset_cntr2_val, + seq->rwcfg->init_reset_1_cke_0); /* Bring up clock enable. */ /* tXRP < 250 ck cycles */ - delay_for_n_mem_clocks(250); + delay_for_n_mem_clocks(seq, 250); - rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset, - 0); + rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_dll_reset_mirr, + seq->rwcfg->mrs0_dll_reset, 0); } /** @@ -1006,9 +1013,10 @@ static void rw_mgr_mem_initialize(void) * At the end of calibration we have to program the user settings in * and hand off the memory to the user. */ -static void rw_mgr_mem_handoff(void) +static void rw_mgr_mem_handoff(struct socfpga_sdrseq *seq) { - rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1); + rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_user_mirr, + seq->rwcfg->mrs0_user, 1); /* * Need to wait tMOD (12CK or 15ns) time before issuing other * commands, but we will have plenty of NIOS cycles before actual @@ -1024,12 +1032,12 @@ static void rw_mgr_mem_handoff(void) * Issue write test command. Two variants are provided, one that just tests * a write pattern and another that tests datamask functionality. */ -static void rw_mgr_mem_calibrate_write_test_issue(u32 group, - u32 test_dm) +static void rw_mgr_mem_calibrate_write_test_issue(struct socfpga_sdrseq *seq, + u32 group, u32 test_dm) { const u32 quick_write_mode = (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) && - misccfg->enable_super_quick_calibration; + seq->misccfg->enable_super_quick_calibration; u32 mcc_instruction; u32 rw_wl_nop_cycles; @@ -1059,7 +1067,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, * one counter left to issue this command in "multiple-group" mode */ - rw_wl_nop_cycles = gbl->rw_wl_nop_cycles; + rw_wl_nop_cycles = seq->gbl.rw_wl_nop_cycles; if (rw_wl_nop_cycles == -1) { /* @@ -1072,16 +1080,16 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, /* CNTR 3 - Not used */ if (test_dm) { - mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; - writel(rwcfg->lfsr_wr_rd_dm_bank_0_data, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_data, &sdr_rw_load_jump_mgr_regs->load_jump_add2); - writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } else { - mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1; - writel(rwcfg->lfsr_wr_rd_bank_0_data, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0_wl_1; + writel(seq->rwcfg->lfsr_wr_rd_bank_0_data, &sdr_rw_load_jump_mgr_regs->load_jump_add2); - writel(rwcfg->lfsr_wr_rd_bank_0_nop, + writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } } else if (rw_wl_nop_cycles == 0) { @@ -1094,12 +1102,12 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, /* CNTR 3 - Not used */ if (test_dm) { - mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; - writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_dqs, &sdr_rw_load_jump_mgr_regs->load_jump_add2); } else { - mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; - writel(rwcfg->lfsr_wr_rd_bank_0_dqs, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_bank_0_dqs, &sdr_rw_load_jump_mgr_regs->load_jump_add2); } } else { @@ -1117,12 +1125,12 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, */ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3); if (test_dm) { - mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; - writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } else { - mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; - writel(rwcfg->lfsr_wr_rd_bank_0_nop, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } } @@ -1144,10 +1152,10 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1); if (test_dm) { - writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait, + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_wait, &sdr_rw_load_jump_mgr_regs->load_jump_add1); } else { - writel(rwcfg->lfsr_wr_rd_bank_0_wait, + writel(seq->rwcfg->lfsr_wr_rd_bank_0_wait, &sdr_rw_load_jump_mgr_regs->load_jump_add1); } @@ -1157,7 +1165,8 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, } /** - * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass + * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple + * pass * @rank_bgn: Rank number * @write_group: Write Group * @use_dm: Use DM @@ -1168,36 +1177,38 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, * Test writes, can check for a single bit pass or multiple bit pass. */ static int -rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, +rw_mgr_mem_calibrate_write_test(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 write_group, const u32 use_dm, const u32 all_correct, u32 *bit_chk, const u32 all_ranks) { const u32 rank_end = all_ranks ? - rwcfg->mem_number_of_ranks : + seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); - const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs / - rwcfg->mem_virtual_groups_per_write_dqs; - const u32 correct_mask_vg = param->write_correct_mask_vg; + const u32 shift_ratio = seq->rwcfg->mem_dq_per_write_dqs / + seq->rwcfg->mem_virtual_groups_per_write_dqs; + const u32 correct_mask_vg = seq->param.write_correct_mask_vg; - u32 tmp_bit_chk, base_rw_mgr; + u32 tmp_bit_chk, base_rw_mgr, group; int vg, r; - *bit_chk = param->write_correct_mask; + *bit_chk = seq->param.write_correct_mask; for (r = rank_bgn; r < rank_end; r++) { /* Set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); tmp_bit_chk = 0; - for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1; + for (vg = seq->rwcfg->mem_virtual_groups_per_write_dqs - 1; vg >= 0; vg--) { /* Reset the FIFOs to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); - rw_mgr_mem_calibrate_write_test_issue( - write_group * - rwcfg->mem_virtual_groups_per_write_dqs + vg, - use_dm); + group = write_group * + seq->rwcfg->mem_virtual_groups_per_write_dqs + + vg; + rw_mgr_mem_calibrate_write_test_issue(seq, group, + use_dm); base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); tmp_bit_chk <<= shift_ratio; @@ -1207,14 +1218,14 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, *bit_chk &= tmp_bit_chk; } - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); if (all_correct) { debug_cond(DLEVEL >= 2, "write_test(%u,%u,ALL) : %u == %u => %i\n", write_group, use_dm, *bit_chk, - param->write_correct_mask, - *bit_chk == param->write_correct_mask); - return *bit_chk == param->write_correct_mask; + seq->param.write_correct_mask, + *bit_chk == seq->param.write_correct_mask); + return *bit_chk == seq->param.write_correct_mask; } else { debug_cond(DLEVEL >= 2, "write_test(%u,%u,ONE) : %u != %i => %i\n", @@ -1233,47 +1244,49 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, * read test to ensure memory works. */ static int -rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group, +rw_mgr_mem_calibrate_read_test_patterns(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 group, const u32 all_ranks) { const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; const u32 addr_offset = - (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2; + (group * seq->rwcfg->mem_virtual_groups_per_read_dqs) + << 2; const u32 rank_end = all_ranks ? - rwcfg->mem_number_of_ranks : + seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); - const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs / - rwcfg->mem_virtual_groups_per_read_dqs; - const u32 correct_mask_vg = param->read_correct_mask_vg; + const u32 shift_ratio = seq->rwcfg->mem_dq_per_read_dqs / + seq->rwcfg->mem_virtual_groups_per_read_dqs; + const u32 correct_mask_vg = seq->param.read_correct_mask_vg; u32 tmp_bit_chk, base_rw_mgr, bit_chk; int vg, r; int ret = 0; - bit_chk = param->read_correct_mask; + bit_chk = seq->param.read_correct_mask; for (r = rank_bgn; r < rank_end; r++) { /* Set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); /* Load up a constant bursts of read commands */ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->guaranteed_read, + writel(seq->rwcfg->guaranteed_read, &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->guaranteed_read_cont, + writel(seq->rwcfg->guaranteed_read_cont, &sdr_rw_load_jump_mgr_regs->load_jump_add1); tmp_bit_chk = 0; - for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; + for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; vg--) { /* Reset the FIFOs to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET); - writel(rwcfg->guaranteed_read, + writel(seq->rwcfg->guaranteed_read, addr + addr_offset + (vg << 2)); base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); @@ -1284,33 +1297,35 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group, bit_chk &= tmp_bit_chk; } - writel(rwcfg->clear_dqs_enable, addr + (group << 2)); + writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2)); - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); - if (bit_chk != param->read_correct_mask) + if (bit_chk != seq->param.read_correct_mask) ret = -EIO; debug_cond(DLEVEL >= 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n", __func__, __LINE__, group, bit_chk, - param->read_correct_mask, ret); + seq->param.read_correct_mask, ret); return ret; } /** - * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test + * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read + * test * @rank_bgn: Rank number * @all_ranks: Test all ranks * * Load up the patterns we are going to use during a read test. */ -static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, +static void rw_mgr_mem_calibrate_read_load_patterns(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const int all_ranks) { const u32 rank_end = all_ranks ? - rwcfg->mem_number_of_ranks : + seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); u32 r; @@ -1318,34 +1333,35 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, for (r = rank_bgn; r < rank_end; r++) { /* set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); /* Load up a constant bursts */ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->guaranteed_write_wait0, + writel(seq->rwcfg->guaranteed_write_wait0, &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->guaranteed_write_wait1, + writel(seq->rwcfg->guaranteed_write_wait1, &sdr_rw_load_jump_mgr_regs->load_jump_add1); writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2); - writel(rwcfg->guaranteed_write_wait2, + writel(seq->rwcfg->guaranteed_write_wait2, &sdr_rw_load_jump_mgr_regs->load_jump_add2); writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3); - writel(rwcfg->guaranteed_write_wait3, + writel(seq->rwcfg->guaranteed_write_wait3, &sdr_rw_load_jump_mgr_regs->load_jump_add3); - writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS | - RW_MGR_RUN_SINGLE_GROUP_OFFSET); + writel(seq->rwcfg->guaranteed_write, + SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_RUN_SINGLE_GROUP_OFFSET); } - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); } /** @@ -1363,36 +1379,37 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, * checks than the regular read test. */ static int -rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, +rw_mgr_mem_calibrate_read_test(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 group, const u32 num_tries, const u32 all_correct, u32 *bit_chk, const u32 all_groups, const u32 all_ranks) { - const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks : + const u32 rank_end = all_ranks ? seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); const u32 quick_read_mode = ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) && - misccfg->enable_super_quick_calibration); - u32 correct_mask_vg = param->read_correct_mask_vg; + seq->misccfg->enable_super_quick_calibration); + u32 correct_mask_vg = seq->param.read_correct_mask_vg; u32 tmp_bit_chk; u32 base_rw_mgr; u32 addr; int r, vg, ret; - *bit_chk = param->read_correct_mask; + *bit_chk = seq->param.read_correct_mask; for (r = rank_bgn; r < rank_end; r++) { /* set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->read_b2b_wait1, + writel(seq->rwcfg->read_b2b_wait1, &sdr_rw_load_jump_mgr_regs->load_jump_add1); writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2); - writel(rwcfg->read_b2b_wait2, + writel(seq->rwcfg->read_b2b_wait2, &sdr_rw_load_jump_mgr_regs->load_jump_add2); if (quick_read_mode) @@ -1403,21 +1420,21 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, else writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->read_b2b, + writel(seq->rwcfg->read_b2b, &sdr_rw_load_jump_mgr_regs->load_jump_add0); if (all_groups) - writel(rwcfg->mem_if_read_dqs_width * - rwcfg->mem_virtual_groups_per_read_dqs - 1, + writel(seq->rwcfg->mem_if_read_dqs_width * + seq->rwcfg->mem_virtual_groups_per_read_dqs - 1, &sdr_rw_load_mgr_regs->load_cntr3); else writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3); - writel(rwcfg->read_b2b, + writel(seq->rwcfg->read_b2b, &sdr_rw_load_jump_mgr_regs->load_jump_add3); tmp_bit_chk = 0; - for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; - vg--) { + for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1; + vg >= 0; vg--) { /* Reset the FIFOs to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | @@ -1431,14 +1448,15 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, RW_MGR_RUN_SINGLE_GROUP_OFFSET; } - writel(rwcfg->read_b2b, addr + + writel(seq->rwcfg->read_b2b, addr + ((group * - rwcfg->mem_virtual_groups_per_read_dqs + + seq->rwcfg->mem_virtual_groups_per_read_dqs + vg) << 2)); base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); - tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs / - rwcfg->mem_virtual_groups_per_read_dqs; + tmp_bit_chk <<= + seq->rwcfg->mem_dq_per_read_dqs / + seq->rwcfg->mem_virtual_groups_per_read_dqs; tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr); } @@ -1446,16 +1464,16 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, } addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; - writel(rwcfg->clear_dqs_enable, addr + (group << 2)); + writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2)); - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); if (all_correct) { - ret = (*bit_chk == param->read_correct_mask); + ret = (*bit_chk == seq->param.read_correct_mask); debug_cond(DLEVEL >= 2, "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n", __func__, __LINE__, group, all_groups, *bit_chk, - param->read_correct_mask, ret); + seq->param.read_correct_mask, ret); } else { ret = (*bit_chk != 0x00); debug_cond(DLEVEL >= 2, @@ -1477,13 +1495,15 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, * Perform a READ test across all memory ranks. */ static int -rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries, +rw_mgr_mem_calibrate_read_test_all_ranks(struct socfpga_sdrseq *seq, + const u32 grp, const u32 num_tries, const u32 all_correct, const u32 all_groups) { u32 bit_chk; - return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct, - &bit_chk, all_groups, 1); + return rw_mgr_mem_calibrate_read_test(seq, 0, grp, num_tries, + all_correct, &bit_chk, all_groups, + 1); } /** @@ -1503,11 +1523,11 @@ static void rw_mgr_incr_vfifo(const u32 grp) * * Decrease VFIFO value. */ -static void rw_mgr_decr_vfifo(const u32 grp) +static void rw_mgr_decr_vfifo(struct socfpga_sdrseq *seq, const u32 grp) { u32 i; - for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++) + for (i = 0; i < seq->misccfg->read_valid_fifo_size - 1; i++) rw_mgr_incr_vfifo(grp); } @@ -1517,15 +1537,16 @@ static void rw_mgr_decr_vfifo(const u32 grp) * * Push VFIFO until a failing read happens. */ -static int find_vfifo_failing_read(const u32 grp) +static int find_vfifo_failing_read(struct socfpga_sdrseq *seq, + const u32 grp) { u32 v, ret, fail_cnt = 0; - for (v = 0; v < misccfg->read_valid_fifo_size; v++) { + for (v = 0; v < seq->misccfg->read_valid_fifo_size; v++) { debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n", __func__, __LINE__, v); - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, - PASS_ONE_BIT, 0); + ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, + PASS_ONE_BIT, 0); if (!ret) { fail_cnt++; @@ -1553,21 +1574,22 @@ static int find_vfifo_failing_read(const u32 grp) * * Find working or non-working DQS enable phase setting. */ -static int sdr_find_phase_delay(int working, int delay, const u32 grp, - u32 *work, const u32 work_inc, u32 *pd) +static int sdr_find_phase_delay(struct socfpga_sdrseq *seq, int working, + int delay, const u32 grp, u32 *work, + const u32 work_inc, u32 *pd) { - const u32 max = delay ? iocfg->dqs_en_delay_max : - iocfg->dqs_en_phase_max; + const u32 max = delay ? seq->iocfg->dqs_en_delay_max : + seq->iocfg->dqs_en_phase_max; u32 ret; for (; *pd <= max; (*pd)++) { if (delay) - scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *pd); else - scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *pd); - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, - PASS_ONE_BIT, 0); + ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, + PASS_ONE_BIT, 0); if (!working) ret = !ret; @@ -1590,22 +1612,22 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp, * * Find working or non-working DQS enable phase setting. */ -static int sdr_find_phase(int working, const u32 grp, u32 *work, - u32 *i, u32 *p) +static int sdr_find_phase(struct socfpga_sdrseq *seq, int working, + const u32 grp, u32 *work, u32 *i, u32 *p) { - const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1); + const u32 end = seq->misccfg->read_valid_fifo_size + (working ? 0 : 1); int ret; for (; *i < end; (*i)++) { if (working) *p = 0; - ret = sdr_find_phase_delay(working, 0, grp, work, - iocfg->delay_per_opa_tap, p); + ret = sdr_find_phase_delay(seq, working, 0, grp, work, + seq->iocfg->delay_per_opa_tap, p); if (!ret) return 0; - if (*p > iocfg->dqs_en_phase_max) { + if (*p > seq->iocfg->dqs_en_phase_max) { /* Fiddle with FIFO. */ rw_mgr_incr_vfifo(grp); if (!working) @@ -1626,22 +1648,22 @@ static int sdr_find_phase(int working, const u32 grp, u32 *work, * * Find working DQS enable phase setting. */ -static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d, - u32 *p, u32 *i) +static int sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp, + u32 *work_bgn, u32 *d, u32 *p, u32 *i) { - const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap / - iocfg->delay_per_dqs_en_dchain_tap; + const u32 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap / + seq->iocfg->delay_per_dqs_en_dchain_tap; int ret; *work_bgn = 0; for (*d = 0; *d <= dtaps_per_ptap; (*d)++) { *i = 0; - scc_mgr_set_dqs_en_delay_all_ranks(grp, *d); - ret = sdr_find_phase(1, grp, work_bgn, i, p); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *d); + ret = sdr_find_phase(seq, 1, grp, work_bgn, i, p); if (!ret) return 0; - *work_bgn += iocfg->delay_per_dqs_en_dchain_tap; + *work_bgn += seq->iocfg->delay_per_dqs_en_dchain_tap; } /* Cannot find working solution */ @@ -1658,43 +1680,44 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d, * * Find DQS enable backup phase setting. */ -static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p) +static void sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp, + u32 *work_bgn, u32 *p) { u32 tmp_delay, d; int ret; /* Special case code for backing up a phase */ if (*p == 0) { - *p = iocfg->dqs_en_phase_max; - rw_mgr_decr_vfifo(grp); + *p = seq->iocfg->dqs_en_phase_max; + rw_mgr_decr_vfifo(seq, grp); } else { (*p)--; } - tmp_delay = *work_bgn - iocfg->delay_per_opa_tap; - scc_mgr_set_dqs_en_phase_all_ranks(grp, *p); + tmp_delay = *work_bgn - seq->iocfg->delay_per_opa_tap; + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *p); - for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; + for (d = 0; d <= seq->iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; d++) { - scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d); - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, - PASS_ONE_BIT, 0); + ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, + PASS_ONE_BIT, 0); if (ret) { *work_bgn = tmp_delay; break; } - tmp_delay += iocfg->delay_per_dqs_en_dchain_tap; + tmp_delay += seq->iocfg->delay_per_dqs_en_dchain_tap; } /* Restore VFIFO to old state before we decremented it (if needed). */ (*p)++; - if (*p > iocfg->dqs_en_phase_max) { + if (*p > seq->iocfg->dqs_en_phase_max) { *p = 0; rw_mgr_incr_vfifo(grp); } - scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0); } /** @@ -1706,19 +1729,20 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p) * * Find non-working DQS enable phase setting. */ -static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i) +static int sdr_nonworking_phase(struct socfpga_sdrseq *seq, + const u32 grp, u32 *work_end, u32 *p, u32 *i) { int ret; (*p)++; - *work_end += iocfg->delay_per_opa_tap; - if (*p > iocfg->dqs_en_phase_max) { + *work_end += seq->iocfg->delay_per_opa_tap; + if (*p > seq->iocfg->dqs_en_phase_max) { /* Fiddle with FIFO. */ *p = 0; rw_mgr_incr_vfifo(grp); } - ret = sdr_find_phase(0, grp, work_end, i, p); + ret = sdr_find_phase(seq, 0, grp, work_end, i, p); if (ret) { /* Cannot see edge of failing read. */ debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n", @@ -1736,7 +1760,8 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i) * * Find center of the working DQS enable window. */ -static int sdr_find_window_center(const u32 grp, const u32 work_bgn, +static int sdr_find_window_center(struct socfpga_sdrseq *seq, + const u32 grp, const u32 work_bgn, const u32 work_end) { u32 work_mid; @@ -1748,37 +1773,41 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n", work_bgn, work_end, work_mid); /* Get the middle delay to be less than a VFIFO delay */ - tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap; + tmp_delay = (seq->iocfg->dqs_en_phase_max + 1) + * seq->iocfg->delay_per_opa_tap; debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay); work_mid %= tmp_delay; debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid); - tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap); - if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap) - tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap; - p = tmp_delay / iocfg->delay_per_opa_tap; + tmp_delay = rounddown(work_mid, seq->iocfg->delay_per_opa_tap); + if (tmp_delay > seq->iocfg->dqs_en_phase_max + * seq->iocfg->delay_per_opa_tap) { + tmp_delay = seq->iocfg->dqs_en_phase_max + * seq->iocfg->delay_per_opa_tap; + } + p = tmp_delay / seq->iocfg->delay_per_opa_tap; debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay); d = DIV_ROUND_UP(work_mid - tmp_delay, - iocfg->delay_per_dqs_en_dchain_tap); - if (d > iocfg->dqs_en_delay_max) - d = iocfg->dqs_en_delay_max; - tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap; + seq->iocfg->delay_per_dqs_en_dchain_tap); + if (d > seq->iocfg->dqs_en_delay_max) + d = seq->iocfg->dqs_en_delay_max; + tmp_delay += d * seq->iocfg->delay_per_dqs_en_dchain_tap; debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay); - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); - scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d); /* * push vfifo until we can successfully calibrate. We can do this * because the largest possible margin in 1 VFIFO cycle. */ - for (i = 0; i < misccfg->read_valid_fifo_size; i++) { + for (i = 0; i < seq->misccfg->read_valid_fifo_size; i++) { debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n"); - if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, + if (rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, PASS_ONE_BIT, 0)) { debug_cond(DLEVEL >= 2, @@ -1797,12 +1826,15 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, } /** - * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use + * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to + * use * @grp: Read/Write Group * * Find a good DQS enable to use. */ -static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) +static int +rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq, + const u32 grp) { u32 d, p, i; u32 dtaps_per_ptap; @@ -1814,19 +1846,19 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); - scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); - scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, 0); /* Step 0: Determine number of delay taps for each phase tap. */ - dtaps_per_ptap = iocfg->delay_per_opa_tap / - iocfg->delay_per_dqs_en_dchain_tap; + dtaps_per_ptap = seq->iocfg->delay_per_opa_tap / + seq->iocfg->delay_per_dqs_en_dchain_tap; /* Step 1: First push vfifo until we get a failing read. */ - find_vfifo_failing_read(grp); + find_vfifo_failing_read(seq, grp); /* Step 2: Find first working phase, increment in ptaps. */ work_bgn = 0; - ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i); + ret = sdr_working_phase(seq, grp, &work_bgn, &d, &p, &i); if (ret) return ret; @@ -1842,13 +1874,13 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) * Step 3a: If we have room, back off by one and * increment in dtaps. */ - sdr_backup_phase(grp, &work_bgn, &p); + sdr_backup_phase(seq, grp, &work_bgn, &p); /* * Step 4a: go forward from working phase to non working * phase, increment in ptaps. */ - ret = sdr_nonworking_phase(grp, &work_end, &p, &i); + ret = sdr_nonworking_phase(seq, grp, &work_end, &p, &i); if (ret) return ret; @@ -1856,14 +1888,14 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) /* Special case code for backing up a phase */ if (p == 0) { - p = iocfg->dqs_en_phase_max; - rw_mgr_decr_vfifo(grp); + p = seq->iocfg->dqs_en_phase_max; + rw_mgr_decr_vfifo(seq, grp); } else { p = p - 1; } - work_end -= iocfg->delay_per_opa_tap; - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + work_end -= seq->iocfg->delay_per_opa_tap; + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p); d = 0; @@ -1872,12 +1904,12 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) } /* The dtap increment to find the failing edge is done here. */ - sdr_find_phase_delay(0, 1, grp, &work_end, - iocfg->delay_per_dqs_en_dchain_tap, &d); + sdr_find_phase_delay(seq, 0, 1, grp, &work_end, + seq->iocfg->delay_per_dqs_en_dchain_tap, &d); /* Go back to working dtap */ if (d != 0) - work_end -= iocfg->delay_per_dqs_en_dchain_tap; + work_end -= seq->iocfg->delay_per_dqs_en_dchain_tap; debug_cond(DLEVEL >= 2, "%s:%d p/d: ptap=%u dtap=%u end=%u\n", @@ -1903,8 +1935,8 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) /* Special case code for backing up a phase */ if (p == 0) { - p = iocfg->dqs_en_phase_max; - rw_mgr_decr_vfifo(grp); + p = seq->iocfg->dqs_en_phase_max; + rw_mgr_decr_vfifo(seq, grp); debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n", __func__, __LINE__, p); } else { @@ -1913,7 +1945,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) __func__, __LINE__, p); } - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p); /* * Increase dtap until we first see a passing read (in case the @@ -1927,14 +1959,14 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) initial_failing_dtap = d; - found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d); + found_passing_read = !sdr_find_phase_delay(seq, 1, 1, grp, NULL, 0, &d); if (found_passing_read) { /* Find a failing read. */ debug_cond(DLEVEL >= 2, "%s:%d find failing read\n", __func__, __LINE__); d++; - found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0, - &d); + found_failing_read = !sdr_find_phase_delay(seq, 0, 1, grp, NULL, + 0, &d); } else { debug_cond(DLEVEL >= 1, "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n", @@ -1944,7 +1976,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) /* * The dynamically calculated dtaps_per_ptap is only valid if we * found a passing/failing read. If we didn't, it means d hit the max - * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its + * (seq->iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its * statically calculated value. */ if (found_passing_read && found_failing_read) @@ -1955,7 +1987,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap); /* Step 6: Find the centre of the window. */ - ret = sdr_find_window_center(grp, work_bgn, work_end); + ret = sdr_find_window_center(seq, grp, work_bgn, work_end); return ret; } @@ -1973,33 +2005,35 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) * * Test if the found edge is valid. */ -static u32 search_stop_check(const int write, const int d, const int rank_bgn, +static u32 search_stop_check(struct socfpga_sdrseq *seq, const int write, + const int d, const int rank_bgn, const u32 write_group, const u32 read_group, u32 *bit_chk, u32 *sticky_bit_chk, const u32 use_read_test) { - const u32 ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; - const u32 correct_mask = write ? param->write_correct_mask : - param->read_correct_mask; - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; + const u32 ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; + const u32 correct_mask = write ? seq->param.write_correct_mask : + seq->param.read_correct_mask; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; u32 ret; /* * Stop searching when the read test doesn't pass AND when * we've seen a passing read on every bit. */ if (write) { /* WRITE-ONLY */ - ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, - 0, PASS_ONE_BIT, - bit_chk, 0); + ret = !rw_mgr_mem_calibrate_write_test(seq, rank_bgn, + write_group, 0, + PASS_ONE_BIT, bit_chk, + 0); } else if (use_read_test) { /* READ-ONLY */ - ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group, + ret = !rw_mgr_mem_calibrate_read_test(seq, rank_bgn, read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT, bit_chk, 0, 0); } else { /* READ-ONLY */ - rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, + rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group, 0, PASS_ONE_BIT, bit_chk, 0); *bit_chk = *bit_chk >> (per_dqs * (read_group - (write_group * ratio))); @@ -2028,29 +2062,30 @@ static u32 search_stop_check(const int write, const int d, const int rank_bgn, * * Find left edge of DQ/DQS working phase. */ -static void search_left_edge(const int write, const int rank_bgn, - const u32 write_group, const u32 read_group, const u32 test_bgn, - u32 *sticky_bit_chk, - int *left_edge, int *right_edge, const u32 use_read_test) -{ - const u32 delay_max = write ? iocfg->io_out1_delay_max : - iocfg->io_in_delay_max; - const u32 dqs_max = write ? iocfg->io_out1_delay_max : - iocfg->dqs_in_delay_max; - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; +static void search_left_edge(struct socfpga_sdrseq *seq, const int write, + const int rank_bgn, const u32 write_group, + const u32 read_group, const u32 test_bgn, + u32 *sticky_bit_chk, int *left_edge, + int *right_edge, const u32 use_read_test) +{ + const u32 delay_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->io_in_delay_max; + const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->dqs_in_delay_max; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; u32 stop, bit_chk; int i, d; for (d = 0; d <= dqs_max; d++) { if (write) - scc_mgr_apply_group_dq_out1_delay(d); + scc_mgr_apply_group_dq_out1_delay(seq, d); else - scc_mgr_apply_group_dq_in_delay(test_bgn, d); + scc_mgr_apply_group_dq_in_delay(seq, test_bgn, d); writel(0, &sdr_scc_mgr->update); - stop = search_stop_check(write, d, rank_bgn, write_group, + stop = search_stop_check(seq, write, d, rank_bgn, write_group, read_group, &bit_chk, sticky_bit_chk, use_read_test); if (stop == 1) @@ -2080,9 +2115,9 @@ static void search_left_edge(const int write, const int rank_bgn, /* Reset DQ delay chains to 0 */ if (write) - scc_mgr_apply_group_dq_out1_delay(0); + scc_mgr_apply_group_dq_out1_delay(seq, 0); else - scc_mgr_apply_group_dq_in_delay(test_bgn, 0); + scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0); *sticky_bit_chk = 0; for (i = per_dqs - 1; i >= 0; i--) { @@ -2138,31 +2173,33 @@ static void search_left_edge(const int write, const int rank_bgn, * * Find right edge of DQ/DQS working phase. */ -static int search_right_edge(const int write, const int rank_bgn, - const u32 write_group, const u32 read_group, - const int start_dqs, const int start_dqs_en, - u32 *sticky_bit_chk, - int *left_edge, int *right_edge, const u32 use_read_test) -{ - const u32 delay_max = write ? iocfg->io_out1_delay_max : - iocfg->io_in_delay_max; - const u32 dqs_max = write ? iocfg->io_out1_delay_max : - iocfg->dqs_in_delay_max; - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; +static int search_right_edge(struct socfpga_sdrseq *seq, const int write, + const int rank_bgn, const u32 write_group, + const u32 read_group, const int start_dqs, + const int start_dqs_en, u32 *sticky_bit_chk, + int *left_edge, int *right_edge, + const u32 use_read_test) +{ + const u32 delay_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->io_in_delay_max; + const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->dqs_in_delay_max; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; u32 stop, bit_chk; int i, d; for (d = 0; d <= dqs_max - start_dqs; d++) { if (write) { /* WRITE-ONLY */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, + write_group, d + start_dqs); } else { /* READ-ONLY */ scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs); - if (iocfg->shift_dqs_en_when_shift_dqs) { + if (seq->iocfg->shift_dqs_en_when_shift_dqs) { u32 delay = d + start_dqs_en; - if (delay > iocfg->dqs_en_delay_max) - delay = iocfg->dqs_en_delay_max; + if (delay > seq->iocfg->dqs_en_delay_max) + delay = seq->iocfg->dqs_en_delay_max; scc_mgr_set_dqs_en_delay(read_group, delay); } scc_mgr_load_dqs(read_group); @@ -2170,12 +2207,13 @@ static int search_right_edge(const int write, const int rank_bgn, writel(0, &sdr_scc_mgr->update); - stop = search_stop_check(write, d, rank_bgn, write_group, + stop = search_stop_check(seq, write, d, rank_bgn, write_group, read_group, &bit_chk, sticky_bit_chk, use_read_test); if (stop == 1) { if (write && (d == 0)) { /* WRITE-ONLY */ - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; + for (i = 0; + i < seq->rwcfg->mem_dq_per_write_dqs; i++) { /* * d = 0 failed, but it passed when @@ -2263,11 +2301,12 @@ static int search_right_edge(const int write, const int rank_bgn, * * Find index and value of the middle of the DQ/DQS working phase. */ -static int get_window_mid_index(const int write, int *left_edge, +static int get_window_mid_index(struct socfpga_sdrseq *seq, + const int write, int *left_edge, int *right_edge, int *mid_min) { - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; int i, mid, min_index; /* Find middle of window for each DQ bit */ @@ -2310,15 +2349,16 @@ static int get_window_mid_index(const int write, int *left_edge, * * Align the DQ/DQS windows in each group. */ -static void center_dq_windows(const int write, int *left_edge, int *right_edge, +static void center_dq_windows(struct socfpga_sdrseq *seq, + const int write, int *left_edge, int *right_edge, const int mid_min, const int orig_mid_min, const int min_index, const int test_bgn, int *dq_margin, int *dqs_margin) { - const s32 delay_max = write ? iocfg->io_out1_delay_max : - iocfg->io_in_delay_max; - const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; + const s32 delay_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->io_in_delay_max; + const s32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET : SCC_MGR_IO_IN_DELAY_OFFSET; const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off; @@ -2385,9 +2425,12 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge, * * Per-bit deskew DQ and centering. */ -static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, - const u32 rw_group, const u32 test_bgn, - const int use_read_test, const int update_fom) +static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq, + const u32 rank_bgn, + const u32 rw_group, + const u32 test_bgn, + const int use_read_test, + const int update_fom) { const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET + @@ -2397,36 +2440,36 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, * signed numbers. */ u32 sticky_bit_chk; - int32_t left_edge[rwcfg->mem_dq_per_read_dqs]; - int32_t right_edge[rwcfg->mem_dq_per_read_dqs]; - int32_t orig_mid_min, mid_min; - int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en; - int32_t dq_margin, dqs_margin; + s32 left_edge[seq->rwcfg->mem_dq_per_read_dqs]; + s32 right_edge[seq->rwcfg->mem_dq_per_read_dqs]; + s32 orig_mid_min, mid_min; + s32 new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en; + s32 dq_margin, dqs_margin; int i, min_index; int ret; debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn); start_dqs = readl(addr); - if (iocfg->shift_dqs_en_when_shift_dqs) - start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset); + if (seq->iocfg->shift_dqs_en_when_shift_dqs) + start_dqs_en = readl(addr - seq->iocfg->dqs_en_delay_offset); /* set the left and right edge of each bit to an illegal value */ - /* use (iocfg->io_in_delay_max + 1) as an illegal value */ + /* use (seq->iocfg->io_in_delay_max + 1) as an illegal value */ sticky_bit_chk = 0; - for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) { - left_edge[i] = iocfg->io_in_delay_max + 1; - right_edge[i] = iocfg->io_in_delay_max + 1; + for (i = 0; i < seq->rwcfg->mem_dq_per_read_dqs; i++) { + left_edge[i] = seq->iocfg->io_in_delay_max + 1; + right_edge[i] = seq->iocfg->io_in_delay_max + 1; } /* Search for the left edge of the window for each bit */ - search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn, + search_left_edge(seq, 0, rank_bgn, rw_group, rw_group, test_bgn, &sticky_bit_chk, left_edge, right_edge, use_read_test); /* Search for the right edge of the window for each bit */ - ret = search_right_edge(0, rank_bgn, rw_group, rw_group, + ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group, start_dqs, start_dqs_en, &sticky_bit_chk, left_edge, right_edge, use_read_test); @@ -2437,7 +2480,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, * dqs/ck relationships. */ scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs); - if (iocfg->shift_dqs_en_when_shift_dqs) + if (seq->iocfg->shift_dqs_en_when_shift_dqs) scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en); scc_mgr_load_dqs(rw_group); @@ -2447,26 +2490,27 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, "%s:%d vfifo_center: failed to find edge [%u]: %d %d", __func__, __LINE__, i, left_edge[i], right_edge[i]); if (use_read_test) { - set_failing_group_stage(rw_group * - rwcfg->mem_dq_per_read_dqs + i, + set_failing_group_stage(seq, rw_group * + seq->rwcfg->mem_dq_per_read_dqs + i, CAL_STAGE_VFIFO, CAL_SUBSTAGE_VFIFO_CENTER); } else { - set_failing_group_stage(rw_group * - rwcfg->mem_dq_per_read_dqs + i, + set_failing_group_stage(seq, rw_group * + seq->rwcfg->mem_dq_per_read_dqs + i, CAL_STAGE_VFIFO_AFTER_WRITES, CAL_SUBSTAGE_VFIFO_CENTER); } return -EIO; } - min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min); + min_index = get_window_mid_index(seq, 0, left_edge, right_edge, + &mid_min); /* Determine the amount we can change DQS (which is -mid_min) */ orig_mid_min = mid_min; new_dqs = start_dqs - mid_min; - if (new_dqs > iocfg->dqs_in_delay_max) - new_dqs = iocfg->dqs_in_delay_max; + if (new_dqs > seq->iocfg->dqs_in_delay_max) + new_dqs = seq->iocfg->dqs_in_delay_max; else if (new_dqs < 0) new_dqs = 0; @@ -2474,10 +2518,10 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n", mid_min, new_dqs); - if (iocfg->shift_dqs_en_when_shift_dqs) { - if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max) + if (seq->iocfg->shift_dqs_en_when_shift_dqs) { + if (start_dqs_en - mid_min > seq->iocfg->dqs_en_delay_max) mid_min += start_dqs_en - mid_min - - iocfg->dqs_en_delay_max; + seq->iocfg->dqs_en_delay_max; else if (start_dqs_en - mid_min < 0) mid_min += start_dqs_en - mid_min; } @@ -2486,15 +2530,15 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, debug_cond(DLEVEL >= 1, "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n", start_dqs, - iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1, + seq->iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1, new_dqs, mid_min); /* Add delay to bring centre of all DQ windows to the same "level". */ - center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min, + center_dq_windows(seq, 0, left_edge, right_edge, mid_min, orig_mid_min, min_index, test_bgn, &dq_margin, &dqs_margin); /* Move DQS-en */ - if (iocfg->shift_dqs_en_when_shift_dqs) { + if (seq->iocfg->shift_dqs_en_when_shift_dqs) { final_dqs_en = start_dqs_en - mid_min; scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en); scc_mgr_load_dqs(rw_group); @@ -2520,7 +2564,8 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, } /** - * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device + * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the + * device * @rw_group: Read/Write Group * @phase: DQ/DQS phase * @@ -2528,13 +2573,14 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, * device, the sequencer uses a guaranteed write mechanism to write data into * the memory device. */ -static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, +static int rw_mgr_mem_calibrate_guaranteed_write(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 phase) { int ret; /* Set a particular DQ/DQS phase. */ - scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase); + scc_mgr_set_dqdqs_output_phase_all_ranks(seq, rw_group, phase); debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n", __func__, __LINE__, rw_group, phase); @@ -2544,16 +2590,16 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, * Load up the patterns used by read calibration using the * current DQDQS phase. */ - rw_mgr_mem_calibrate_read_load_patterns(0, 1); + rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1); - if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ) + if (seq->gbl.phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ) return 0; /* * Altera EMI_RM 2015.05.04 :: Figure 1-26 * Back-to-Back reads of the patterns used for calibration. */ - ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1); + ret = rw_mgr_mem_calibrate_read_test_patterns(seq, 0, rw_group, 1); if (ret) debug_cond(DLEVEL >= 1, "%s:%d Guaranteed read test failed: g=%u p=%u\n", @@ -2569,8 +2615,10 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, * DQS enable calibration ensures reliable capture of the DQ signal without * glitches on the DQS line. */ -static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, - const u32 test_bgn) +static int +rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdrseq *seq, + const u32 rw_group, + const u32 test_bgn) { /* * Altera EMI_RM 2015.05.04 :: Figure 1-27 @@ -2578,18 +2626,18 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, */ /* We start at zero, so have one less dq to devide among */ - const u32 delay_step = iocfg->io_in_delay_max / - (rwcfg->mem_dq_per_read_dqs - 1); + const u32 delay_step = seq->iocfg->io_in_delay_max / + (seq->rwcfg->mem_dq_per_read_dqs - 1); int ret; u32 i, p, d, r; debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn); /* Try different dq_in_delays since the DQ path is shorter than DQS. */ - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { for (i = 0, p = test_bgn, d = 0; - i < rwcfg->mem_dq_per_read_dqs; + i < seq->rwcfg->mem_dq_per_read_dqs; i++, p++, d += delay_step) { debug_cond(DLEVEL >= 1, "%s:%d: g=%u r=%u i=%u p=%u d=%u\n", @@ -2606,15 +2654,15 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different * dq_in_delay values */ - ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group); + ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(seq, rw_group); debug_cond(DLEVEL >= 1, "%s:%d: g=%u found=%u; Reseting delay chain to zero\n", __func__, __LINE__, rw_group, !ret); - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { - scc_mgr_apply_group_dq_in_delay(test_bgn, 0); + scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0); writel(0, &sdr_scc_mgr->update); } @@ -2632,7 +2680,8 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, * within a group. */ static int -rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, +rw_mgr_mem_calibrate_dq_dqs_centering(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 test_bgn, const int use_read_test, const int update_fom) @@ -2646,9 +2695,9 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, */ grp_calibrated = 1; for (rank_bgn = 0, sr = 0; - rank_bgn < rwcfg->mem_number_of_ranks; + rank_bgn < seq->rwcfg->mem_number_of_ranks; rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) { - ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group, + ret = rw_mgr_mem_calibrate_vfifo_center(seq, rank_bgn, rw_group, test_bgn, use_read_test, update_fom); @@ -2679,7 +2728,8 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, * - DQS input phase and DQS input delay (DQ/DQS Centering) * - we also do a per-bit deskew on the DQ lines. */ -static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) +static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 test_bgn) { u32 p, d; u32 dtaps_per_ptap; @@ -2697,8 +2747,9 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) failed_substage = CAL_SUBSTAGE_GUARANTEED_READ; /* USER Determine number of delay taps for each phase tap. */ - dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap, - iocfg->delay_per_dqs_en_dchain_tap) - 1; + dtaps_per_ptap = DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap, + seq->iocfg->delay_per_dqs_en_dchain_tap) + - 1; for (d = 0; d <= dtaps_per_ptap; d += 2) { /* @@ -2708,18 +2759,22 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) * output side yet. */ if (d > 0) { - scc_mgr_apply_group_all_out_delay_add_all_ranks( - rw_group, d); + scc_mgr_apply_group_all_out_delay_add_all_ranks(seq, + rw_group, + d); } - for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) { + for (p = 0; p <= seq->iocfg->dqdqs_out_phase_max; p++) { /* 1) Guaranteed Write */ - ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p); + ret = rw_mgr_mem_calibrate_guaranteed_write(seq, + rw_group, + p); if (ret) break; /* 2) DQS Enable Calibration */ - ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group, + ret = rw_mgr_mem_calibrate_dqs_enable_calibration(seq, + rw_group, test_bgn); if (ret) { failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; @@ -2731,8 +2786,10 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) * If doing read after write calibration, do not update * FOM now. Do it then. */ - ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, - test_bgn, 1, 0); + ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq, + rw_group, + test_bgn, + 1, 0); if (ret) { failed_substage = CAL_SUBSTAGE_VFIFO_CENTER; continue; @@ -2744,7 +2801,8 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) } /* Calibration Stage 1 failed. */ - set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage); + set_failing_group_stage(seq, rw_group, CAL_STAGE_VFIFO, + failed_substage); return 0; /* Calibration Stage 1 completed OK. */ @@ -2755,7 +2813,7 @@ cal_done_ok: * first case). */ if (d > 2) - scc_mgr_zero_group(rw_group, 1); + scc_mgr_zero_group(seq, rw_group, 1); return 1; } @@ -2770,7 +2828,8 @@ cal_done_ok: * This function implements UniPHY calibration Stage 3, as explained in * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". */ -static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, +static int rw_mgr_mem_calibrate_vfifo_end(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 test_bgn) { int ret; @@ -2782,9 +2841,10 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES); reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); - ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1); + ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq, rw_group, test_bgn, 0, + 1); if (ret) - set_failing_group_stage(rw_group, + set_failing_group_stage(seq, rw_group, CAL_STAGE_VFIFO_AFTER_WRITES, CAL_SUBSTAGE_VFIFO_CENTER); return ret; @@ -2799,7 +2859,7 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". * Calibrate LFIFO to find smallest read latency. */ -static u32 rw_mgr_mem_calibrate_lfifo(void) +static u32 rw_mgr_mem_calibrate_lfifo(struct socfpga_sdrseq *seq) { int found_one = 0; @@ -2810,14 +2870,15 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY); /* Load up the patterns used by read calibration for all ranks */ - rw_mgr_mem_calibrate_read_load_patterns(0, 1); + rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1); do { - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u", - __func__, __LINE__, gbl->curr_read_lat); + __func__, __LINE__, seq->gbl.curr_read_lat); - if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS, + if (!rw_mgr_mem_calibrate_read_test_all_ranks(seq, 0, + NUM_READ_TESTS, PASS_ALL_BITS, 1)) break; @@ -2826,26 +2887,26 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) * Reduce read latency and see if things are * working correctly. */ - gbl->curr_read_lat--; - } while (gbl->curr_read_lat > 0); + seq->gbl.curr_read_lat--; + } while (seq->gbl.curr_read_lat > 0); /* Reset the fifos to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); if (found_one) { /* Add a fudge factor to the read latency that was determined */ - gbl->curr_read_lat += 2; - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + seq->gbl.curr_read_lat += 2; + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); debug_cond(DLEVEL >= 2, "%s:%d lfifo: success: using read_lat=%u\n", - __func__, __LINE__, gbl->curr_read_lat); + __func__, __LINE__, seq->gbl.curr_read_lat); } else { - set_failing_group_stage(0xff, CAL_STAGE_LFIFO, + set_failing_group_stage(seq, 0xff, CAL_STAGE_LFIFO, CAL_SUBSTAGE_READ_LATENCY); debug_cond(DLEVEL >= 2, "%s:%d lfifo: failed at initial read_lat=%u\n", - __func__, __LINE__, gbl->curr_read_lat); + __func__, __LINE__, seq->gbl.curr_read_lat); } return found_one; @@ -2853,7 +2914,8 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) /** * search_window() - Search for the/part of the window with DM/DQS shift - * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift + * @search_dm: If 1, search for the DM shift, if 0, search for DQS + * shift * @rank_bgn: Rank number * @write_group: Write Group * @bgn_curr: Current window begin @@ -2865,20 +2927,21 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) * * Search for the/part of the window with DM/DQS shift. */ -static void search_window(const int search_dm, - const u32 rank_bgn, const u32 write_group, - int *bgn_curr, int *end_curr, int *bgn_best, - int *end_best, int *win_best, int new_dqs) +static void search_window(struct socfpga_sdrseq *seq, + const int search_dm, const u32 rank_bgn, + const u32 write_group, int *bgn_curr, int *end_curr, + int *bgn_best, int *end_best, int *win_best, + int new_dqs) { u32 bit_chk; - const int max = iocfg->io_out1_delay_max - new_dqs; + const int max = seq->iocfg->io_out1_delay_max - new_dqs; int d, di; /* Search for the/part of the window with DM/DQS shift. */ for (di = max; di >= 0; di -= DELTA_D) { if (search_dm) { d = di; - scc_mgr_apply_group_dm_out1_delay(d); + scc_mgr_apply_group_dm_out1_delay(seq, d); } else { /* For DQS, we go from 0...max */ d = max - di; @@ -2886,14 +2949,15 @@ static void search_window(const int search_dm, * Note: This only shifts DQS, so are we limiting * ourselves to width of DQ unnecessarily. */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, + write_group, d + new_dqs); } writel(0, &sdr_scc_mgr->update); - if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1, - PASS_ALL_BITS, &bit_chk, + if (rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group, + 1, PASS_ALL_BITS, &bit_chk, 0)) { /* Set current end of the window. */ *end_curr = search_dm ? -d : d; @@ -2902,7 +2966,7 @@ static void search_window(const int search_dm, * If a starting edge of our window has not been seen * this is our current start of the DM window. */ - if (*bgn_curr == iocfg->io_out1_delay_max + 1) + if (*bgn_curr == seq->iocfg->io_out1_delay_max + 1) *bgn_curr = search_dm ? -d : d; /* @@ -2916,8 +2980,8 @@ static void search_window(const int search_dm, } } else { /* We just saw a failing test. Reset temp edge. */ - *bgn_curr = iocfg->io_out1_delay_max + 1; - *end_curr = iocfg->io_out1_delay_max + 1; + *bgn_curr = seq->iocfg->io_out1_delay_max + 1; + *end_curr = seq->iocfg->io_out1_delay_max + 1; /* Early exit is only applicable to DQS. */ if (search_dm) @@ -2928,7 +2992,8 @@ static void search_window(const int search_dm, * chain space is less than already seen largest * window we can exit. */ - if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d) + if (*win_best - 1 > seq->iocfg->io_out1_delay_max + - new_dqs - d) break; } } @@ -2944,22 +3009,23 @@ static void search_window(const int search_dm, * certain windows. */ static int -rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, +rw_mgr_mem_calibrate_writes_center(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 write_group, const u32 test_bgn) { int i; u32 sticky_bit_chk; u32 min_index; - int left_edge[rwcfg->mem_dq_per_write_dqs]; - int right_edge[rwcfg->mem_dq_per_write_dqs]; + int left_edge[seq->rwcfg->mem_dq_per_write_dqs]; + int right_edge[seq->rwcfg->mem_dq_per_write_dqs]; int mid; int mid_min, orig_mid_min; int new_dqs, start_dqs; int dq_margin, dqs_margin, dm_margin; - int bgn_curr = iocfg->io_out1_delay_max + 1; - int end_curr = iocfg->io_out1_delay_max + 1; - int bgn_best = iocfg->io_out1_delay_max + 1; - int end_best = iocfg->io_out1_delay_max + 1; + int bgn_curr = seq->iocfg->io_out1_delay_max + 1; + int end_curr = seq->iocfg->io_out1_delay_max + 1; + int bgn_best = seq->iocfg->io_out1_delay_max + 1; + int end_best = seq->iocfg->io_out1_delay_max + 1; int win_best = 0; int ret; @@ -2970,37 +3036,39 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET) + - (rwcfg->mem_dq_per_write_dqs << 2)); + (seq->rwcfg->mem_dq_per_write_dqs << 2)); /* Per-bit deskew. */ /* * Set the left and right edge of each bit to an illegal value. - * Use (iocfg->io_out1_delay_max + 1) as an illegal value. + * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value. */ sticky_bit_chk = 0; - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { - left_edge[i] = iocfg->io_out1_delay_max + 1; - right_edge[i] = iocfg->io_out1_delay_max + 1; + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) { + left_edge[i] = seq->iocfg->io_out1_delay_max + 1; + right_edge[i] = seq->iocfg->io_out1_delay_max + 1; } /* Search for the left edge of the window for each bit. */ - search_left_edge(1, rank_bgn, write_group, 0, test_bgn, + search_left_edge(seq, 1, rank_bgn, write_group, 0, test_bgn, &sticky_bit_chk, left_edge, right_edge, 0); /* Search for the right edge of the window for each bit. */ - ret = search_right_edge(1, rank_bgn, write_group, 0, + ret = search_right_edge(seq, 1, rank_bgn, write_group, 0, start_dqs, 0, &sticky_bit_chk, left_edge, right_edge, 0); if (ret) { - set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES, + set_failing_group_stage(seq, test_bgn + ret - 1, + CAL_STAGE_WRITES, CAL_SUBSTAGE_WRITES_CENTER); return -EINVAL; } - min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min); + min_index = get_window_mid_index(seq, 1, left_edge, right_edge, + &mid_min); /* Determine the amount we can change DQS (which is -mid_min). */ orig_mid_min = mid_min; @@ -3011,11 +3079,11 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, __func__, __LINE__, start_dqs, new_dqs, mid_min); /* Add delay to bring centre of all DQ windows to the same "level". */ - center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min, + center_dq_windows(seq, 1, left_edge, right_edge, mid_min, orig_mid_min, min_index, 0, &dq_margin, &dqs_margin); /* Move DQS */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs); writel(0, &sdr_scc_mgr->update); /* Centre DM */ @@ -3023,17 +3091,17 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, /* * Set the left and right edge of each bit to an illegal value. - * Use (iocfg->io_out1_delay_max + 1) as an illegal value. + * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value. */ - left_edge[0] = iocfg->io_out1_delay_max + 1; - right_edge[0] = iocfg->io_out1_delay_max + 1; + left_edge[0] = seq->iocfg->io_out1_delay_max + 1; + right_edge[0] = seq->iocfg->io_out1_delay_max + 1; /* Search for the/part of the window with DM shift. */ - search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr, + search_window(seq, 1, rank_bgn, write_group, &bgn_curr, &end_curr, &bgn_best, &end_best, &win_best, 0); /* Reset DM delay chains to 0. */ - scc_mgr_apply_group_dm_out1_delay(0); + scc_mgr_apply_group_dm_out1_delay(seq, 0); /* * Check to see if the current window nudges up aganist 0 delay. @@ -3041,12 +3109,12 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, * search begins as a new search. */ if (end_curr != 0) { - bgn_curr = iocfg->io_out1_delay_max + 1; - end_curr = iocfg->io_out1_delay_max + 1; + bgn_curr = seq->iocfg->io_out1_delay_max + 1; + end_curr = seq->iocfg->io_out1_delay_max + 1; } /* Search for the/part of the window with DQS shifts. */ - search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr, + search_window(seq, 0, rank_bgn, write_group, &bgn_curr, &end_curr, &bgn_best, &end_best, &win_best, new_dqs); /* Assign left and right edge for cal and reporting. */ @@ -3057,7 +3125,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, __func__, __LINE__, left_edge[0], right_edge[0]); /* Move DQS (back to orig). */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs); /* Move DM */ @@ -3074,7 +3142,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, else dm_margin = left_edge[0] - mid; - scc_mgr_apply_group_dm_out1_delay(mid); + scc_mgr_apply_group_dm_out1_delay(seq, mid); writel(0, &sdr_scc_mgr->update); debug_cond(DLEVEL >= 2, @@ -3082,7 +3150,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, __func__, __LINE__, left_edge[0], right_edge[0], mid, dm_margin); /* Export values. */ - gbl->fom_out += dq_margin + dqs_margin; + seq->gbl.fom_out += dq_margin + dqs_margin; debug_cond(DLEVEL >= 2, "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n", @@ -3111,7 +3179,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, * This function implements UniPHY calibration Stage 2, as explained in * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". */ -static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, +static int rw_mgr_mem_calibrate_writes(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 group, const u32 test_bgn) { int ret; @@ -3123,9 +3192,10 @@ static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, reg_file_set_stage(CAL_STAGE_WRITES); reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER); - ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn); + ret = rw_mgr_mem_calibrate_writes_center(seq, rank_bgn, group, + test_bgn); if (ret) - set_failing_group_stage(group, CAL_STAGE_WRITES, + set_failing_group_stage(seq, group, CAL_STAGE_WRITES, CAL_SUBSTAGE_WRITES_CENTER); return ret; @@ -3136,29 +3206,30 @@ static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, * * Precharge all banks and activate row 0 in bank "000..." and bank "111...". */ -static void mem_precharge_and_activate(void) +static void mem_precharge_and_activate(struct socfpga_sdrseq *seq) { int r; - for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) { /* Set rank. */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF); /* Precharge all banks. */ - writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | + writel(seq->rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->activate_0_and_1_wait1, + writel(seq->rwcfg->activate_0_and_1_wait1, &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->activate_0_and_1_wait2, + writel(seq->rwcfg->activate_0_and_1_wait2, &sdr_rw_load_jump_mgr_regs->load_jump_add1); /* Activate rows. */ - writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | - RW_MGR_RUN_SINGLE_GROUP_OFFSET); + writel(seq->rwcfg->activate_0_and_1, + SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_RUN_SINGLE_GROUP_OFFSET); } } @@ -3167,14 +3238,15 @@ static void mem_precharge_and_activate(void) * * Configure memory RLAT and WLAT parameters. */ -static void mem_init_latency(void) +static void mem_init_latency(struct socfpga_sdrseq *seq) { /* * For AV/CV, LFIFO is hardened and always runs at full rate * so max latency in AFI clocks, used here, is correspondingly * smaller. */ - const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1; + const u32 max_latency = (1 << seq->misccfg->max_latency_count_width) + - 1; u32 rlat, wlat; debug("%s:%d\n", __func__, __LINE__); @@ -3186,17 +3258,17 @@ static void mem_init_latency(void) wlat = readl(&data_mgr->t_wl_add); wlat += readl(&data_mgr->mem_t_add); - gbl->rw_wl_nop_cycles = wlat - 1; + seq->gbl.rw_wl_nop_cycles = wlat - 1; /* Read in readl latency. */ rlat = readl(&data_mgr->t_rl_add); /* Set a pretty high read latency initially. */ - gbl->curr_read_lat = rlat + 16; - if (gbl->curr_read_lat > max_latency) - gbl->curr_read_lat = max_latency; + seq->gbl.curr_read_lat = rlat + 16; + if (seq->gbl.curr_read_lat > max_latency) + seq->gbl.curr_read_lat = max_latency; - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); /* Advertise write latency. */ writel(wlat, &phy_mgr_cfg->afi_wlat); @@ -3207,22 +3279,22 @@ static void mem_init_latency(void) * * Set VFIFO and LFIFO to instant-on settings in skip calibration mode. */ -static void mem_skip_calibrate(void) +static void mem_skip_calibrate(struct socfpga_sdrseq *seq) { u32 vfifo_offset; u32 i, j, r; debug("%s:%d\n", __func__, __LINE__); /* Need to update every shadow register set used by the interface */ - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { /* * Set output phase alignment settings appropriate for * skip calibration. */ - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { scc_mgr_set_dqs_en_phase(i, 0); - if (iocfg->dll_chain_length == 6) + if (seq->iocfg->dll_chain_length == 6) scc_mgr_set_dqdqs_output_phase(i, 6); else scc_mgr_set_dqdqs_output_phase(i, 7); @@ -3245,20 +3317,22 @@ static void mem_skip_calibrate(void) * Hence, to make DQS aligned to CK, we need to delay * DQS by: * (720 - 90 - 180 - 2) * - * (360 / iocfg->dll_chain_length) + * (360 / seq->iocfg->dll_chain_length) * - * Dividing the above by (360 / iocfg->dll_chain_length) + * Dividing the above by + (360 / seq->iocfg->dll_chain_length) * gives us the number of ptaps, which simplies to: * - * (1.25 * iocfg->dll_chain_length - 2) + * (1.25 * seq->iocfg->dll_chain_length - 2) */ scc_mgr_set_dqdqs_output_phase(i, - ((125 * iocfg->dll_chain_length) / 100) - 2); + ((125 * seq->iocfg->dll_chain_length) + / 100) - 2); } writel(0xff, &sdr_scc_mgr->dqs_ena); writel(0xff, &sdr_scc_mgr->dqs_io_ena); - for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) { writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET); } @@ -3268,7 +3342,7 @@ static void mem_skip_calibrate(void) } /* Compensate for simulation model behaviour */ - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { scc_mgr_set_dqs_bus_in_delay(i, 10); scc_mgr_load_dqs(i); } @@ -3278,7 +3352,7 @@ static void mem_skip_calibrate(void) * ArriaV has hard FIFOs that can only be initialized by incrementing * in sequencer. */ - vfifo_offset = misccfg->calib_vfifo_offset; + vfifo_offset = seq->misccfg->calib_vfifo_offset; for (j = 0; j < vfifo_offset; j++) writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy); writel(0, &phy_mgr_cmd->fifo_reset); @@ -3287,8 +3361,8 @@ static void mem_skip_calibrate(void) * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal * setting from generation-time constant. */ - gbl->curr_read_lat = misccfg->calib_lfifo_offset; - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + seq->gbl.curr_read_lat = seq->misccfg->calib_lfifo_offset; + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); } /** @@ -3296,7 +3370,7 @@ static void mem_skip_calibrate(void) * * Perform memory calibration. */ -static u32 mem_calibrate(void) +static u32 mem_calibrate(struct socfpga_sdrseq *seq) { u32 i; u32 rank_bgn, sr; @@ -3306,25 +3380,25 @@ static u32 mem_calibrate(void) u32 failing_groups = 0; u32 group_failed = 0; - const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; + const u32 rwdqs_ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; debug("%s:%d\n", __func__, __LINE__); /* Initialize the data settings */ - gbl->error_substage = CAL_SUBSTAGE_NIL; - gbl->error_stage = CAL_STAGE_NIL; - gbl->error_group = 0xff; - gbl->fom_in = 0; - gbl->fom_out = 0; + seq->gbl.error_substage = CAL_SUBSTAGE_NIL; + seq->gbl.error_stage = CAL_STAGE_NIL; + seq->gbl.error_group = 0xff; + seq->gbl.fom_in = 0; + seq->gbl.fom_out = 0; /* Initialize WLAT and RLAT. */ - mem_init_latency(); + mem_init_latency(seq); /* Initialize bit slips. */ - mem_precharge_and_activate(); + mem_precharge_and_activate(seq); - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET); /* Only needed once to set all groups, pins, DQ, DQS, DM. */ @@ -3335,12 +3409,12 @@ static u32 mem_calibrate(void) } /* Calibration is skipped. */ - if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) { + if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) { /* * Set VFIFO and LFIFO to instant-on settings in skip * calibration mode. */ - mem_skip_calibrate(); + mem_skip_calibrate(seq); /* * Do not remove this line as it makes sure all of our @@ -3356,13 +3430,13 @@ static u32 mem_calibrate(void) * Zero all delay chain/phase settings for all * groups and all shadow register sets. */ - scc_mgr_zero_all(); + scc_mgr_zero_all(seq); run_groups = ~0; for (write_group = 0, write_test_bgn = 0; write_group - < rwcfg->mem_if_write_dqs_width; write_group++, - write_test_bgn += rwcfg->mem_dq_per_write_dqs) { + < seq->rwcfg->mem_if_write_dqs_width; write_group++, + write_test_bgn += seq->rwcfg->mem_dq_per_write_dqs) { /* Initialize the group failure */ group_failed = 0; @@ -3376,22 +3450,22 @@ static u32 mem_calibrate(void) writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET); - scc_mgr_zero_group(write_group, 0); + scc_mgr_zero_group(seq, write_group, 0); for (read_group = write_group * rwdqs_ratio, read_test_bgn = 0; read_group < (write_group + 1) * rwdqs_ratio; read_group++, - read_test_bgn += rwcfg->mem_dq_per_read_dqs) { + read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) { if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO) continue; /* Calibrate the VFIFO */ - if (rw_mgr_mem_calibrate_vfifo(read_group, + if (rw_mgr_mem_calibrate_vfifo(seq, read_group, read_test_bgn)) continue; - if (!(gbl->phy_debug_mode_flags & + if (!(seq->gbl.phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; @@ -3401,7 +3475,7 @@ static u32 mem_calibrate(void) /* Calibrate the output side */ for (rank_bgn = 0, sr = 0; - rank_bgn < rwcfg->mem_number_of_ranks; + rank_bgn < seq->rwcfg->mem_number_of_ranks; rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) { if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) continue; @@ -3412,13 +3486,13 @@ static u32 mem_calibrate(void) continue; /* Calibrate WRITEs */ - if (!rw_mgr_mem_calibrate_writes(rank_bgn, + if (!rw_mgr_mem_calibrate_writes(seq, rank_bgn, write_group, write_test_bgn)) continue; group_failed = 1; - if (!(gbl->phy_debug_mode_flags & + if (!(seq->gbl.phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; } @@ -3431,15 +3505,16 @@ static u32 mem_calibrate(void) read_test_bgn = 0; read_group < (write_group + 1) * rwdqs_ratio; read_group++, - read_test_bgn += rwcfg->mem_dq_per_read_dqs) { + read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) { if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) continue; - if (!rw_mgr_mem_calibrate_vfifo_end(read_group, + if (!rw_mgr_mem_calibrate_vfifo_end(seq, + read_group, read_test_bgn)) continue; - if (!(gbl->phy_debug_mode_flags & + if (!(seq->gbl.phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; @@ -3465,7 +3540,7 @@ grp_failed: /* A group failed, increment the counter. */ continue; /* Calibrate the LFIFO */ - if (!rw_mgr_mem_calibrate_lfifo()) + if (!rw_mgr_mem_calibrate_lfifo(seq)) return 0; } @@ -3482,7 +3557,7 @@ grp_failed: /* A group failed, increment the counter. */ * * This function triggers the entire memory calibration procedure. */ -static int run_mem_calibrate(void) +static int run_mem_calibrate(struct socfpga_sdrseq *seq) { int pass; u32 ctrl_cfg; @@ -3497,17 +3572,17 @@ static int run_mem_calibrate(void) writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK, &sdr_ctrl->ctrl_cfg); - phy_mgr_initialize(); - rw_mgr_mem_initialize(); + phy_mgr_initialize(seq); + rw_mgr_mem_initialize(seq); /* Perform the actual memory calibration. */ - pass = mem_calibrate(); + pass = mem_calibrate(seq); - mem_precharge_and_activate(); + mem_precharge_and_activate(seq); writel(0, &phy_mgr_cmd->fifo_reset); /* Handoff. */ - rw_mgr_mem_handoff(); + rw_mgr_mem_handoff(seq); /* * In Hard PHY this is a 2-bit control: * 0: AFI Mux Select @@ -3528,25 +3603,25 @@ static int run_mem_calibrate(void) * This function reports the results of the memory calibration * and writes debug information into the register file. */ -static void debug_mem_calibrate(int pass) +static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) { u32 debug_info; if (pass) { debug("%s: CALIBRATION PASSED\n", __FILE__); - gbl->fom_in /= 2; - gbl->fom_out /= 2; + seq->gbl.fom_in /= 2; + seq->gbl.fom_out /= 2; - if (gbl->fom_in > 0xff) - gbl->fom_in = 0xff; + if (seq->gbl.fom_in > 0xff) + seq->gbl.fom_in = 0xff; - if (gbl->fom_out > 0xff) - gbl->fom_out = 0xff; + if (seq->gbl.fom_out > 0xff) + seq->gbl.fom_out = 0xff; /* Update the FOM in the register file */ - debug_info = gbl->fom_in; - debug_info |= gbl->fom_out << 8; + debug_info = seq->gbl.fom_in; + debug_info |= seq->gbl.fom_out << 8; writel(debug_info, &sdr_reg_file->fom); writel(debug_info, &phy_mgr_cfg->cal_debug_info); @@ -3554,18 +3629,18 @@ static void debug_mem_calibrate(int pass) } else { debug("%s: CALIBRATION FAILED\n", __FILE__); - debug_info = gbl->error_stage; - debug_info |= gbl->error_substage << 8; - debug_info |= gbl->error_group << 16; + debug_info = seq->gbl.error_stage; + debug_info |= seq->gbl.error_substage << 8; + debug_info |= seq->gbl.error_group << 16; writel(debug_info, &sdr_reg_file->failing_stage); writel(debug_info, &phy_mgr_cfg->cal_debug_info); writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status); /* Update the failing group/stage in the register file */ - debug_info = gbl->error_stage; - debug_info |= gbl->error_substage << 8; - debug_info |= gbl->error_group << 16; + debug_info = seq->gbl.error_stage; + debug_info |= seq->gbl.error_substage << 8; + debug_info |= seq->gbl.error_group << 16; writel(debug_info, &sdr_reg_file->failing_stage); } @@ -3599,10 +3674,11 @@ static void hc_initialize_rom_data(void) * * Initialize SDR register file. */ -static void initialize_reg_file(void) +static void initialize_reg_file(struct socfpga_sdrseq *seq) { /* Initialize the register file with the correct data */ - writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature); + writel(seq->misccfg->reg_file_init_seq_signature, + &sdr_reg_file->signature); writel(0, &sdr_reg_file->debug_data_addr); writel(0, &sdr_reg_file->cur_stage); writel(0, &sdr_reg_file->fom); @@ -3666,15 +3742,15 @@ static void initialize_hps_phy(void) * * Initialize the register file with usable initial data. */ -static void initialize_tracking(void) +static void initialize_tracking(struct socfpga_sdrseq *seq) { /* * Initialize the register file with the correct data. * Compute usable version of value in case we skip full * computation later. */ - writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, - iocfg->delay_per_dchain_tap) - 1, + writel(DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap, + seq->iocfg->delay_per_dchain_tap) - 1, &sdr_reg_file->dtaps_per_ptap); /* trk_sample_count */ @@ -3693,23 +3769,22 @@ static void initialize_tracking(void) &sdr_reg_file->delays); /* mux delay */ - writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) | - (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0), + writel((seq->rwcfg->idle << 24) | (seq->rwcfg->activate_1 << 16) | + (seq->rwcfg->sgle_read << 8) | (seq->rwcfg->precharge_all << 0), &sdr_reg_file->trk_rw_mgr_addr); - writel(rwcfg->mem_if_read_dqs_width, + writel(seq->rwcfg->mem_if_read_dqs_width, &sdr_reg_file->trk_read_dqs_width); /* trefi [7:0] */ - writel((rwcfg->refresh_all << 24) | (1000 << 0), + writel((seq->rwcfg->refresh_all << 24) | (1000 << 0), &sdr_reg_file->trk_rfsh); } int sdram_calibration_full(struct socfpga_sdr *sdr) { - struct param_type my_param; - struct gbl_type my_gbl; u32 pass; + struct socfpga_sdrseq seq; /* * For size reasons, this file uses hard coded addresses. @@ -3718,60 +3793,61 @@ int sdram_calibration_full(struct socfpga_sdr *sdr) if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) return -ENODEV; - memset(&my_param, 0, sizeof(my_param)); - memset(&my_gbl, 0, sizeof(my_gbl)); - - param = &my_param; - gbl = &my_gbl; + memset(&seq, 0, sizeof(seq)); - rwcfg = socfpga_get_sdram_rwmgr_config(); - iocfg = socfpga_get_sdram_io_config(); - misccfg = socfpga_get_sdram_misc_config(); + seq.rwcfg = socfpga_get_sdram_rwmgr_config(); + seq.iocfg = socfpga_get_sdram_io_config(); + seq.misccfg = socfpga_get_sdram_misc_config(); /* Set the calibration enabled by default */ - gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; + seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; /* * Only sweep all groups (regardless of fail state) by default * Set enabled read test by default. */ #if DISABLE_GUARANTEED_READ - gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ; + seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ; #endif /* Initialize the register file */ - initialize_reg_file(); + initialize_reg_file(&seq); /* Initialize any PHY CSR */ initialize_hps_phy(); scc_mgr_initialize(); - initialize_tracking(); + initialize_tracking(&seq); debug("%s: Preparing to start memory calibration\n", __FILE__); debug("%s:%d\n", __func__, __LINE__); debug_cond(DLEVEL >= 1, "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ", - rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm, - rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs, - rwcfg->mem_virtual_groups_per_read_dqs, - rwcfg->mem_virtual_groups_per_write_dqs); + seq.rwcfg->mem_number_of_ranks, + seq.rwcfg->mem_number_of_cs_per_dimm, + seq.rwcfg->mem_dq_per_read_dqs, + seq.rwcfg->mem_dq_per_write_dqs, + seq.rwcfg->mem_virtual_groups_per_read_dqs, + seq.rwcfg->mem_virtual_groups_per_write_dqs); debug_cond(DLEVEL >= 1, "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ", - rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width, - rwcfg->mem_data_width, rwcfg->mem_data_mask_width, - iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap); + seq.rwcfg->mem_if_read_dqs_width, + seq.rwcfg->mem_if_write_dqs_width, + seq.rwcfg->mem_data_width, seq.rwcfg->mem_data_mask_width, + seq.iocfg->delay_per_opa_tap, + seq.iocfg->delay_per_dchain_tap); debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u", - iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length); + seq.iocfg->delay_per_dqs_en_dchain_tap, + seq.iocfg->dll_chain_length); debug_cond(DLEVEL >= 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ", - iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max, - iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max); + seq.iocfg->dqs_en_phase_max, seq.iocfg->dqdqs_out_phase_max, + seq.iocfg->dqs_en_delay_max, seq.iocfg->dqs_in_delay_max); debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ", - iocfg->io_in_delay_max, iocfg->io_out1_delay_max, - iocfg->io_out2_delay_max); + seq.iocfg->io_in_delay_max, seq.iocfg->io_out1_delay_max, + seq.iocfg->io_out2_delay_max); debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n", - iocfg->dqs_in_reserve, iocfg->dqs_out_reserve); + seq.iocfg->dqs_in_reserve, seq.iocfg->dqs_out_reserve); hc_initialize_rom_data(); @@ -3783,17 +3859,17 @@ int sdram_calibration_full(struct socfpga_sdr *sdr) * Load global needed for those actions that require * some dynamic calibration support. */ - dyn_calib_steps = STATIC_CALIB_STEPS; + seq.dyn_calib_steps = STATIC_CALIB_STEPS; /* * Load global to allow dynamic selection of delay loop settings * based on calibration mode. */ - if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS)) - skip_delay_mask = 0xff; + if (!(seq.dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS)) + seq.skip_delay_mask = 0xff; else - skip_delay_mask = 0x0; + seq.skip_delay_mask = 0x0; - pass = run_mem_calibrate(); - debug_mem_calibrate(pass); + pass = run_mem_calibrate(&seq); + debug_mem_calibrate(&seq, pass); return pass; } diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index d7f6935201..4a03c3fdf9 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -6,14 +6,16 @@ #ifndef _SEQUENCER_H_ #define _SEQUENCER_H_ -#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \ - / rwcfg->mem_if_write_dqs_width) -#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \ - / rwcfg->mem_if_write_dqs_width) +#define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \ + / seq->rwcfg->mem_if_write_dqs_width) +#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \ + seq->rwcfg->true_mem_data_mask_width \ + / seq->rwcfg->mem_if_write_dqs_width) -#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \ - / rwcfg->mem_if_write_dqs_width) -#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS) +#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \ + / seq->rwcfg->mem_if_write_dqs_width) +#define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \ + / NUM_SHADOW_REGS) #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 @@ -256,6 +258,26 @@ struct socfpga_sdr { u8 _align9[0xea4]; }; +struct socfpga_sdrseq { + const struct socfpga_sdram_rw_mgr_config *rwcfg; + const struct socfpga_sdram_io_config *iocfg; + const struct socfpga_sdram_misc_config *misccfg; + /* calibration steps requested by the rtl */ + u16 dyn_calib_steps; + /* + * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option + * instead of static, we use boolean logic to select between + * non-skip and skip values + * + * The mask is set to include all bits when not-skipping, but is + * zero when skipping + */ + + u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ + struct gbl_type gbl; + struct param_type param; +}; + int sdram_calibration_full(struct socfpga_sdr *sdr); #endif /* _SEQUENCER_H_ */ diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 7d8f161b26..873bc8c796 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -1,9 +1,13 @@ config FIRMWARE bool "Enable Firmware driver support" +config SPL_FIRMWARE + bool "Enable Firmware driver support in SPL" + depends on FIRMWARE + config SPL_ARM_PSCI_FW bool - select FIRMWARE + select SPL_FIRMWARE config ARM_PSCI_FW bool @@ -13,6 +17,7 @@ config TI_SCI_PROTOCOL tristate "TI System Control Interface (TISCI) Message Protocol" depends on K3_SEC_PROXY select FIRMWARE + select SPL_FIRMWARE if SPL help TI System Control Interface (TISCI) Message Protocol is used to manage compute systems such as ARM, DSP etc with the system controller in diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 8f59193e3c..105a299812 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -58,9 +58,17 @@ config FPGA_ZYNQMPPL config FPGA_SPARTAN3 bool "Enable Spartan3 FPGA driver" + depends on FPGA_XILINX help Enable Spartan3 FPGA driver for loading in BIT format. +config FPGA_VIRTEX2 + bool "Enable Xilinx Virtex-II and later FPGA driver" + depends on FPGA_XILINX + help + Enable Virtex-II FPGA driver for loading in BIT format. This driver + also supports many newer Xilinx FPGA families. + config FPGA_ZYNQPL bool "Enable Xilinx FPGA for Zynq" depends on ARCH_ZYNQ diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 6755956e85..c929cd2cc5 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -11,9 +11,9 @@ /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif /* Note: The assumption is that we cannot possibly run fast enough to @@ -26,7 +26,7 @@ #endif #ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ +#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ #endif static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -41,8 +41,8 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); - ret_val = CYC2_ps_load (desc, buf, bsize); + PRINTF("%s: Launching Passive Serial Loader\n", __func__); + ret_val = CYC2_ps_load(desc, buf, bsize); break; case fast_passive_parallel: @@ -50,16 +50,16 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) * done in the write() callback. Use the existing PS load * function for FPP, too. */ - PRINTF ("%s: Launching Fast Passive Parallel Loader\n", - __FUNCTION__); + PRINTF("%s: Launching Fast Passive Parallel Loader\n", + __func__); ret_val = CYC2_ps_load(desc, buf, bsize); break; /* Add new interface types here */ default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; @@ -71,59 +71,58 @@ int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); - ret_val = CYC2_ps_dump (desc, buf, bsize); + PRINTF("%s: Launching Passive Serial Dump\n", __func__); + ret_val = CYC2_ps_dump(desc, buf, bsize); break; /* Add new interface types here */ default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } -int CYC2_info( Altera_desc *desc ) +int CYC2_info(Altera_desc *desc) { return FPGA_SUCCESS; } /* ------------------------------------------------------------------------- */ -/* CYCLON2 Passive Serial Generic Implementation */ +/* CYCLON2 Passive Serial Generic Implementation */ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; int ret = 0; - PRINTF ("%s: start with interface functions @ 0x%p\n", - __FUNCTION__, fn); + PRINTF("%s: start with interface functions @ 0x%p\n", + __func__, fn); if (fn) { int cookie = desc->cookie; /* make a local copy */ unsigned long ts; /* timestamp */ - PRINTF ("%s: Function Table:\n" + PRINTF("%s: Function Table:\n" "ptr:\t0x%p\n" "struct: 0x%p\n" "config:\t0x%p\n" "status:\t0x%p\n" "write:\t0x%p\n" "done:\t0x%p\n\n", - __FUNCTION__, &fn, fn, fn->config, fn->status, + __func__, &fn, fn, fn->config, fn->status, fn->write, fn->done); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Loading FPGA Device %d...", cookie); + printf("Loading FPGA Device %d...", cookie); #endif /* * Run the pre configuration function if there is one. */ - if (*fn->pre) { + if (*fn->pre) (*fn->pre) (cookie); - } /* Establish the initial state */ (*fn->config) (false, true, cookie); /* De-assert nCONFIG */ @@ -133,22 +132,23 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) udelay(2); /* T_cfg > 2us */ /* Wait for nSTATUS to be asserted */ - ts = get_timer (0); /* get current time */ + ts = get_timer(0); /* get current time */ do { - CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ - puts ("** Timeout waiting for STATUS to go high.\n"); + CONFIG_FPGA_DELAY(); + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + /* check the time */ + puts("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); return FPGA_FAIL; } } while (!(*fn->status) (cookie)); /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CONFIG_FPGA_DELAY(); ret = (*fn->write) (buf, bsize, true, cookie); if (ret) { - puts ("** Write failed.\n"); + puts("** Write failed.\n"); (*fn->abort) (cookie); return FPGA_FAIL; } @@ -156,39 +156,41 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) puts(" OK? ..."); #endif - CONFIG_FPGA_DELAY (); + CONFIG_FPGA_DELAY(); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc (' '); /* terminate the dotted line */ + putc(' '); /* terminate the dotted line */ #endif - /* - * Checking FPGA's CONF_DONE signal - correctly booted ? - */ + /* + * Checking FPGA's CONF_DONE signal - correctly booted ? + */ - if ( ! (*fn->done) (cookie) ) { - puts ("** Booting failed! CONF_DONE is still deasserted.\n"); - (*fn->abort) (cookie); - return (FPGA_FAIL); - } + if (!(*fn->done) (cookie)) { + puts("** Booting failed! CONF_DONE is still deasserted.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - puts(" OK\n"); + puts(" OK\n"); #endif - ret_val = FPGA_SUCCESS; + ret_val = FPGA_SUCCESS; #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (ret_val == FPGA_SUCCESS) { - puts ("Done.\n"); - } - else { - puts ("Fail.\n"); - } + if (ret_val == FPGA_SUCCESS) + puts("Done.\n"); + else + puts("Fail.\n"); #endif - (*fn->post) (cookie); + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) + (*fn->post) (cookie); } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -198,7 +200,6 @@ static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ - printf ("%s: Passive Serial Dumping is unavailable\n", - __FUNCTION__); + printf("%s: Passive Serial Dumping is unavailable\n", __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 285280e507..5fb9d6a191 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) fpgamgr_program_write(rbf_data, rbf_size); status = fpgamgr_program_finish(); - if (status) { - config_pins(gd->fdt_blob, "fpga"); - puts("FPGA: Enter user mode.\n"); - } + if (status) + return status; + + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); return status; } diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 02773d6a0e..395736875f 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -3,6 +3,8 @@ * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * Keith Outwater, keith_outwater@mvis.com + * + * Copyright (c) 2019 SED Systems, a division of Calian Ltd. */ /* @@ -19,16 +21,16 @@ #endif #ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif /* * If the SelectMap interface can be overrun by the processor, define - * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration - * file and add board-specific support for checking BUSY status. By default, - * assume that the SelectMap interface cannot be overrun. + * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board + * configuration file and add board-specific support for checking BUSY status. + * By default, assume that the SelectMap interface cannot be overrun. */ #ifndef CONFIG_SYS_FPGA_CHECK_BUSY #undef CONFIG_SYS_FPGA_CHECK_BUSY @@ -65,7 +67,7 @@ * an XC2V1000, if anyone can ever get ahold of one. */ #ifndef CONFIG_SYS_FPGA_WAIT_INIT -#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */ +#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ #endif /* @@ -74,14 +76,14 @@ * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ #ifndef CONFIG_SYS_FPGA_WAIT_BUSY -#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/ +#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ #endif /* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG -#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ +#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ #endif static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -97,18 +99,18 @@ static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, switch (desc->iface) { case slave_serial: - PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); + PRINTF("%s: Launching Slave Serial Load\n", __func__); ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: - PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); + PRINTF("%s: Launching Slave Parallel Load\n", __func__); ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } @@ -119,18 +121,18 @@ static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case slave_serial: - PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); + PRINTF("%s: Launching Slave Serial Dump\n", __func__); ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: - PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); + PRINTF("%s: Launching Slave Parallel Dump\n", __func__); ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } @@ -141,8 +143,8 @@ static int virtex2_info(xilinx_desc *desc) } /* - * Virtex-II Slave SelectMap configuration loader. Configuration via - * SelectMap is as follows: + * Virtex-II Slave SelectMap or Serial configuration loader. Configuration + * is as follows: * 1. Set the FPGA's PROG_B line low. * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high. * 3. Write data to the SelectMap port. If INIT_B goes low at any time @@ -154,200 +156,236 @@ static int virtex2_info(xilinx_desc *desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) { - int ret_val = FPGA_FAIL; - xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; + unsigned long ts; - PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", - __FUNCTION__, __LINE__, fn); + PRINTF("%s:%d: Start with interface functions @ 0x%p\n", + __func__, __LINE__, fn); - if (fn) { - size_t bytecount = 0; - unsigned char *data = (unsigned char *) buf; - int cookie = desc->cookie; - unsigned long ts; - - /* Gotta split this one up (so the stack won't blow??) */ - PRINTF ("%s:%d: Function Table:\n" - " base 0x%p\n" - " struct 0x%p\n" - " pre 0x%p\n" - " prog 0x%p\n" - " init 0x%p\n" - " error 0x%p\n", - __FUNCTION__, __LINE__, - &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); - PRINTF (" clock 0x%p\n" - " cs 0x%p\n" - " write 0x%p\n" - " rdata 0x%p\n" - " wdata 0x%p\n" - " busy 0x%p\n" - " abort 0x%p\n" - " post 0x%p\n\n", - fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, - fn->busy, fn->abort, fn->post); + if (!fn) { + printf("%s:%d: NULL Interface function table!\n", + __func__, __LINE__); + return FPGA_FAIL; + } + + /* Gotta split this one up (so the stack won't blow??) */ + PRINTF("%s:%d: Function Table:\n" + " base 0x%p\n" + " struct 0x%p\n" + " pre 0x%p\n" + " prog 0x%p\n" + " init 0x%p\n" + " error 0x%p\n", + __func__, __LINE__, + &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); + PRINTF(" clock 0x%p\n" + " cs 0x%p\n" + " write 0x%p\n" + " rdata 0x%p\n" + " wdata 0x%p\n" + " busy 0x%p\n" + " abort 0x%p\n" + " post 0x%p\n\n", + fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, + fn->busy, fn->abort, fn->post); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Initializing FPGA Device %d...\n", cookie); + printf("Initializing FPGA Device %d...\n", cookie); #endif - /* - * Run the pre configuration function if there is one. - */ - if (*fn->pre) { - (*fn->pre) (cookie); + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) + (*fn->pre)(cookie); + + /* + * Assert the program line. The minimum pulse width for + * Virtex II devices is 300 nS (Tprogram parameter in datasheet). + * There is no maximum value for the pulse width. Check to make + * sure that INIT_B goes low after assertion of PROG_B + */ + (*fn->pgm)(true, true, cookie); + udelay(10); + ts = get_timer(0); + do { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + (*fn->abort)(cookie); + return FPGA_FAIL; + } + } while (!(*fn->init)(cookie)); + + (*fn->pgm)(false, true, cookie); + CONFIG_FPGA_DELAY(); + if (fn->clk) + (*fn->clk)(true, true, cookie); + + /* + * Start a timer and wait for INIT_B to go high + */ + ts = get_timer(0); + do { + CONFIG_FPGA_DELAY(); + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + (*fn->abort)(cookie); + return FPGA_FAIL; } + } while ((*fn->init)(cookie) && (*fn->busy)(cookie)); - /* - * Assert the program line. The minimum pulse width for - * Virtex II devices is 300 nS (Tprogram parameter in datasheet). - * There is no maximum value for the pulse width. Check to make - * sure that INIT_B goes low after assertion of PROG_B - */ - (*fn->pgm) (true, true, cookie); - udelay (10); - ts = get_timer (0); - do { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { - printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" - " to assert.\n", __FUNCTION__, __LINE__, - CONFIG_SYS_FPGA_WAIT_INIT); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } while (!(*fn->init) (cookie)); + if (fn->wr) + (*fn->wr)(true, true, cookie); + if (fn->cs) + (*fn->cs)(true, true, cookie); - (*fn->pgm) (false, true, cookie); - CONFIG_FPGA_DELAY (); - (*fn->clk) (true, true, cookie); + mdelay(10); + return FPGA_SUCCESS; +} - /* - * Start a timer and wait for INIT_B to go high - */ - ts = get_timer (0); - do { - CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { - printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" - " to deassert.\n", __FUNCTION__, __LINE__, - CONFIG_SYS_FPGA_WAIT_INIT); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); +static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, + int cookie) +{ + int ret_val = FPGA_SUCCESS; + int num_done = 0; + unsigned long ts; + + /* + * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. + */ + CONFIG_FPGA_DELAY(); + if (fn->cs) + (*fn->cs)(false, true, cookie); + if (fn->wr) + (*fn->wr)(false, true, cookie); - (*fn->wr) (true, true, cookie); - (*fn->cs) (true, true, cookie); +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('\n'); +#endif - udelay (10000); + /* + * Check for successful configuration. FPGA INIT_B and DONE + * should both be high upon successful configuration. Continue pulsing + * clock with data set to all ones until DONE is asserted and for 8 + * clock cycles afterwards. + */ + ts = get_timer(0); + while (true) { + if ((*fn->done)(cookie) == FPGA_SUCCESS && + !((*fn->init)(cookie))) { + if (num_done++ >= 8) + break; + } + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { + printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); + (*fn->abort)(cookie); + ret_val = FPGA_FAIL; + break; + } + if (fn->wbulkdata) { + unsigned char dummy = 0xff; + (*fn->wbulkdata)(&dummy, 1, true, cookie); + } else { + (*fn->wdata)(0xff, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); + } + } + + if (ret_val == FPGA_SUCCESS) { +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + printf("Initialization of FPGA device %d complete\n", cookie); +#endif /* - * Load the data byte by byte + * Run the post configuration function if there is one. */ - while (bytecount < bsize) { -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc ()) { - (*fn->abort) (cookie); - return FPGA_FAIL; - } + if (*fn->post) + (*fn->post)(cookie); + } else { +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + printf("** Initialization of FPGA device %d FAILED\n", + cookie); #endif + } + return ret_val; +} - if ((*fn->done) (cookie) == FPGA_SUCCESS) { - PRINTF ("%s:%d:done went active early, bytecount = %d\n", - __FUNCTION__, __LINE__, bytecount); - break; - } - -#ifdef CONFIG_SYS_FPGA_CHECK_ERROR - if ((*fn->init) (cookie)) { - printf ("\n%s:%d: ** Error: INIT asserted during" - " configuration\n", __FUNCTION__, __LINE__); - printf ("%d = buffer offset, %d = buffer size\n", - bytecount, bsize); - (*fn->abort) (cookie); - return FPGA_FAIL; - } +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; + size_t bytecount = 0; + unsigned char *data = (unsigned char *)buf; + int cookie = desc->cookie; + + ret_val = virtex2_slave_pre(fn, cookie); + if (ret_val != FPGA_SUCCESS) + return ret_val; + + /* + * Load the data byte by byte + */ + while (bytecount < bsize) { +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) { + (*fn->abort)(cookie); + return FPGA_FAIL; + } #endif - (*fn->wdata) (data[bytecount++], true, cookie); - CONFIG_FPGA_DELAY (); - - /* - * Cycle the clock pin - */ - (*fn->clk) (false, true, cookie); - CONFIG_FPGA_DELAY (); - (*fn->clk) (true, true, cookie); + if ((*fn->done)(cookie) == FPGA_SUCCESS) { + PRINTF("%s:%d:done went active early, bytecount = %d\n", + __func__, __LINE__, bytecount); + break; + } -#ifdef CONFIG_SYS_FPGA_CHECK_BUSY - ts = get_timer (0); - while ((*fn->busy) (cookie)) { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { - printf ("%s:%d: ** Timeout after %d ticks waiting for" - " BUSY to deassert\n", - __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } +#ifdef CONFIG_SYS_FPGA_CHECK_ERROR + if ((*fn->init)(cookie)) { + printf("\n%s:%d: ** Error: INIT asserted during configuration\n", + __func__, __LINE__); + printf("%zu = buffer offset, %zu = buffer size\n", + bytecount, bsize); + (*fn->abort)(cookie); + return FPGA_FAIL; + } #endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % (bsize / 40) == 0) - putc ('.'); -#endif - } + (*fn->wdata)(data[bytecount++], true, cookie); + CONFIG_FPGA_DELAY(); /* - * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. + * Cycle the clock pin */ - CONFIG_FPGA_DELAY (); - (*fn->cs) (false, true, cookie); - (*fn->wr) (false, true, cookie); - -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc ('\n'); -#endif + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); - /* - * Check for successful configuration. FPGA INIT_B and DONE should - * both be high upon successful configuration. - */ - ts = get_timer (0); - ret_val = FPGA_SUCCESS; - while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { - printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to" - "assert and INIT to deassert\n", - __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); - (*fn->abort) (cookie); - ret_val = FPGA_FAIL; - break; +#ifdef CONFIG_SYS_FPGA_CHECK_BUSY + ts = get_timer(0); + while ((*fn->busy)(cookie)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { + printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", + __func__, __LINE__, + CONFIG_SYS_FPGA_WAIT_BUSY); + (*fn->abort)(cookie); + return FPGA_FAIL; } } - - if (ret_val == FPGA_SUCCESS) { -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Initialization of FPGA device %d complete\n", cookie); #endif - /* - * Run the post configuration function if there is one. - */ - if (*fn->post) { - (*fn->post) (cookie); - } - } else { + #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("** Initialization of FPGA device %d FAILED\n", - cookie); + if (bytecount % (bsize / 40) == 0) + putc('.'); #endif - } - } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); } - return ret_val; + + return virtex2_slave_post(fn, cookie); } /* @@ -356,64 +394,127 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; if (fn) { - unsigned char *data = (unsigned char *) buf; + unsigned char *data = (unsigned char *)buf; size_t bytecount = 0; int cookie = desc->cookie; - printf ("Starting Dump of FPGA Device %d...\n", cookie); + printf("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (true, true, cookie); - (*fn->clk) (true, true, cookie); + (*fn->cs)(true, true, cookie); + (*fn->clk)(true, true, cookie); while (bytecount < bsize) { #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc ()) { - (*fn->abort) (cookie); + if (ctrlc()) { + (*fn->abort)(cookie); return FPGA_FAIL; } #endif /* * Cycle the clock and read the data */ - (*fn->clk) (false, true, cookie); - (*fn->clk) (true, true, cookie); - (*fn->rdata) (&(data[bytecount++]), cookie); + (*fn->clk)(false, true, cookie); + (*fn->clk)(true, true, cookie); + (*fn->rdata)(&data[bytecount++], cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) - putc ('.'); + putc('.'); #endif } /* * Deassert CS_B and cycle the clock to deselect the device. */ - (*fn->cs) (false, false, cookie); - (*fn->clk) (false, true, cookie); - (*fn->clk) (true, true, cookie); + (*fn->cs)(false, false, cookie); + (*fn->clk)(false, true, cookie); + (*fn->clk)(true, true, cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc ('\n'); + putc('\n'); #endif - puts ("Done.\n"); + puts("Done.\n"); } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); + printf("%s:%d: NULL Interface function table!\n", + __func__, __LINE__); } return ret_val; } static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { - printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); - return FPGA_FAIL; + int ret_val = FPGA_FAIL; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; + unsigned char *data = (unsigned char *)buf; + int cookie = desc->cookie; + + ret_val = virtex2_slave_pre(fn, cookie); + if (ret_val != FPGA_SUCCESS) + return ret_val; + + if (fn->wbulkdata) { + /* Load the data in a single chunk */ + (*fn->wbulkdata)(data, bsize, true, cookie); + } else { + size_t bytecount = 0; + + /* + * Load the data bit by bit + */ + while (bytecount < bsize) { + unsigned char curr_data = data[bytecount++]; + int bit; + +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) { + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#endif + + if ((*fn->done)(cookie) == FPGA_SUCCESS) { + PRINTF("%s:%d:done went active early, bytecount = %d\n", + __func__, __LINE__, bytecount); + break; + } + +#ifdef CONFIG_SYS_FPGA_CHECK_ERROR + if ((*fn->init)(cookie)) { + printf("\n%s:%d: ** Error: INIT asserted during configuration\n", + __func__, __LINE__); + printf("%zu = buffer offset, %zu = buffer size\n", + bytecount, bsize); + (*fn->abort)(cookie); + return FPGA_FAIL; + } +#endif + + for (bit = 7; bit >= 0; --bit) { + unsigned char curr_bit = (curr_data >> bit) & 1; + (*fn->wdata)(curr_bit, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); + } + + /* Slave serial never uses a busy pin */ + +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc('.'); +#endif + } + } + + return virtex2_slave_post(fn, cookie); } static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); + printf("%s: Slave Serial Dumping is unsupported\n", __func__); return FPGA_FAIL; } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 800584f512..7d9c97f537 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -14,7 +14,7 @@ config DM_GPIO particular GPIOs that they provide. The uclass interface is defined in include/asm-generic/gpio.h. -config DM_GPIO_HOG +config GPIO_HOG bool "Enable GPIO hog support" depends on DM_GPIO default n diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 308d0863ad..01cfa2f788 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -144,7 +144,7 @@ static int gpio_find_and_xlate(struct gpio_desc *desc, return gpio_xlate_offs_flags(desc->dev, desc, args); } -#if defined(CONFIG_DM_GPIO_HOG) +#if defined(CONFIG_GPIO_HOG) struct gpio_hog_priv { struct gpio_desc gpiod; @@ -181,9 +181,8 @@ static int gpio_hog_ofdata_to_platdata(struct udevice *dev) return ret; } nodename = dev_read_string(dev, "line-name"); - if (!nodename) - nodename = dev_read_name(dev); - device_set_name(dev, nodename); + if (nodename) + device_set_name(dev, nodename); return 0; } @@ -202,9 +201,15 @@ static int gpio_hog_probe(struct udevice *dev) dev->name); return ret; } - dm_gpio_set_dir(&priv->gpiod); - if (plat->gpiod_flags == GPIOD_IS_OUT) - dm_gpio_set_value(&priv->gpiod, plat->value); + + if (plat->gpiod_flags == GPIOD_IS_OUT) { + ret = dm_gpio_set_value(&priv->gpiod, plat->value); + if (ret < 0) { + debug("%s: node %s could not set gpio.\n", __func__, + dev->name); + return ret; + } + } return 0; } @@ -213,32 +218,38 @@ int gpio_hog_probe_all(void) { struct udevice *dev; int ret; + int retval = 0; for (uclass_first_device(UCLASS_NOP, &dev); dev; uclass_find_next_device(&dev)) { if (dev->driver == DM_GET_DRIVER(gpio_hog)) { ret = device_probe(dev); - if (ret) - return ret; + if (ret) { + printf("Failed to probe device %s err: %d\n", + dev->name, ret); + retval = ret; + } } } - return 0; + return retval; } -struct gpio_desc *gpio_hog_lookup_name(const char *name) +int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc) { struct udevice *dev; + *desc = NULL; gpio_hog_probe_all(); if (!uclass_get_device_by_name(UCLASS_NOP, name, &dev)) { struct gpio_hog_priv *priv = dev_get_priv(dev); - return &priv->gpiod; + *desc = &priv->gpiod; + return 0; } - return NULL; + return -ENODEV; } U_BOOT_DRIVER(gpio_hog) = { @@ -250,9 +261,9 @@ U_BOOT_DRIVER(gpio_hog) = { .platdata_auto_alloc_size = sizeof(struct gpio_hog_data), }; #else -struct gpio_desc *gpio_hog_lookup_name(const char *name) +int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc) { - return NULL; + return 0; } #endif @@ -755,13 +766,45 @@ int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count) return vector; } +/** + * gpio_request_tail: common work for requesting a gpio. + * + * ret: return value from previous work in function which calls + * this function. + * This seems bogus (why calling this function instead not + * calling it and end caller function instead?). + * Because on error in caller function we want to set some + * default values in gpio desc and have a common error + * debug message, which provides this function. + * nodename: Name of node for which gpio gets requested + * used for gpio label name. + * args: pointer to output arguments structure + * list_name: Name of GPIO list + * used for gpio label name. + * index: gpio index in gpio list + * used for gpio label name. + * desc: pointer to gpio descriptor, filled from this + * function. + * flags: gpio flags to use. + * add_index: should index added to gpio label name + * gpio_dev: pointer to gpio device from which the gpio + * will be requested. If NULL try to get the + * gpio device with uclass_get_device_by_ofnode() + * + * return: In error case this function sets default values in + * gpio descriptor, also emmits a debug message. + * On success it returns 0 else the error code from + * function calls, or the error code passed through + * ret to this function. + * + */ static int gpio_request_tail(int ret, const char *nodename, struct ofnode_phandle_args *args, const char *list_name, int index, struct gpio_desc *desc, int flags, - bool add_index, struct udevice *dev) + bool add_index, struct udevice *gpio_dev) { - desc->dev = dev; + desc->dev = gpio_dev; desc->offset = 0; desc->flags = 0; if (ret) @@ -771,7 +814,8 @@ static int gpio_request_tail(int ret, const char *nodename, ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node, &desc->dev); if (ret) { - debug("%s: uclass_get_device_by_ofnode failed\n", __func__); + debug("%s: uclass_get_device_by_ofnode failed\n", + __func__); goto err; } } @@ -989,10 +1033,8 @@ int gpio_dev_request_index(struct udevice *dev, const char *nodename, static int gpio_post_bind(struct udevice *dev) { -#if defined(CONFIG_DM_GPIO_HOG) struct udevice *child; ofnode node; -#endif #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_gpio_ops *ops = (struct dm_gpio_ops *)device_get_ops(dev); @@ -1024,16 +1066,21 @@ static int gpio_post_bind(struct udevice *dev) } #endif -#if defined(CONFIG_DM_GPIO_HOG) - dev_for_each_subnode(node, dev) { - if (ofnode_read_bool(node, "gpio-hog")) { - const char *name = ofnode_get_name(node); - - device_bind_driver_to_node(dev, "gpio_hog", name, - node, &child); + if (IS_ENABLED(CONFIG_GPIO_HOG)) { + dev_for_each_subnode(node, dev) { + if (ofnode_read_bool(node, "gpio-hog")) { + const char *name = ofnode_get_name(node); + int ret; + + ret = device_bind_driver_to_node(dev, + "gpio_hog", + name, node, + &child); + if (ret) + return ret; + } } } -#endif return 0; } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 4772db3837..03d2fed341 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -12,18 +12,7 @@ config DM_I2C write and speed, is implemented with the bus drivers operations, which provide methods for bus setting and data transfer. Each chip device (bus child) info is kept as parent platdata. The interface - is defined in include/i2c.h. When i2c bus driver supports the i2c - uclass, but the device drivers not, then DM_I2C_COMPAT config can - be used as compatibility layer. - -config DM_I2C_COMPAT - bool "Enable I2C compatibility layer" - depends on DM - help - Enable old-style I2C functions for compatibility with existing code. - This option can be enabled as a temporary measure to avoid needing - to convert all code for a board in a single commit. It should not - be enabled for any board in an official release. + is defined in include/i2c.h. config I2C_CROS_EC_TUNNEL tristate "Chrome OS EC tunnel I2C bus" diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index dc40055efb..c2f75d8755 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -3,7 +3,6 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_DM_I2C) += i2c-uclass.o -obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c deleted file mode 100644 index b3ade88113..0000000000 --- a/drivers/i2c/i2c-uclass-compat.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2014 Google, Inc - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <i2c.h> - -static int cur_busnum __attribute__((section(".data"))); - -static int i2c_compat_get_device(uint chip_addr, int alen, - struct udevice **devp) -{ - struct dm_i2c_chip *chip; - int ret; - - ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, alen, devp); - if (ret) - return ret; - chip = dev_get_parent_platdata(*devp); - if (chip->offset_len != alen) { - printf("I2C chip %x: requested alen %d does not match chip offset_len %d\n", - chip_addr, alen, chip->offset_len); - return -EADDRNOTAVAIL; - } - - return 0; -} - -int i2c_probe(uint8_t chip_addr) -{ - struct udevice *bus, *dev; - int ret; - - ret = uclass_get_device_by_seq(UCLASS_I2C, cur_busnum, &bus); - if (ret) { - debug("Cannot find I2C bus %d: err=%d\n", cur_busnum, ret); - return ret; - } - - if (!bus) - return -ENOENT; - - return dm_i2c_probe(bus, chip_addr, 0, &dev); -} - -int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, - int len) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, alen, &dev); - if (ret) - return ret; - - return dm_i2c_read(dev, addr, buffer, len); -} - -int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, - int len) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, alen, &dev); - if (ret) - return ret; - - return dm_i2c_write(dev, addr, buffer, len); -} - -int i2c_get_bus_num_fdt(int node) -{ - struct udevice *bus; - int ret; - - ret = uclass_get_device_by_of_offset(UCLASS_I2C, node, &bus); - if (ret) - return ret; - - return bus->seq; -} - -unsigned int i2c_get_bus_num(void) -{ - return cur_busnum; -} - -int i2c_set_bus_num(unsigned int bus) -{ - cur_busnum = bus; - - return 0; -} - -void i2c_init(int speed, int slaveaddr) -{ - /* Nothing to do here - the init happens through driver model */ -} - -void board_i2c_init(const void *blob) -{ - /* Nothing to do here - the init happens through driver model */ -} - -uint8_t i2c_reg_read(uint8_t chip_addr, uint8_t offset) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, 1, &dev); - if (ret) - return 0xff; - return dm_i2c_reg_read(dev, offset); -} - -void i2c_reg_write(uint8_t chip_addr, uint8_t offset, uint8_t val) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, 1, &dev); - if (!ret) - dm_i2c_reg_write(dev, offset, val); -} diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index cfa9b535c8..33c2f16be8 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -31,6 +31,7 @@ #include <common.h> #include <asm/io.h> #include <nand.h> +#include <dm/uclass.h> #include <asm/ti-common/davinci_nand.h> /* Definitions for 4-bit hardware ECC */ @@ -730,7 +731,7 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd) return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1; } -void davinci_nand_init(struct nand_chip *nand) +static void davinci_nand_init(struct nand_chip *nand) { #if defined CONFIG_KEYSTONE_RBL_NAND int i; @@ -785,10 +786,53 @@ void davinci_nand_init(struct nand_chip *nand) nand->dev_ready = nand_davinci_dev_ready; } -int board_nand_init(struct nand_chip *chip) __attribute__((weak)); +#ifdef CONFIG_SYS_NAND_SELF_INIT +static int davinci_nand_probe(struct udevice *dev) +{ + struct nand_chip *nand = dev_get_priv(dev); + struct mtd_info *mtd = nand_to_mtd(nand); + int ret; + + nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + + davinci_nand_init(nand); + + ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS); + if (ret) + return ret; + + return nand_register(0, mtd); +} + +static const struct udevice_id davinci_nand_ids[] = { + { .compatible = "ti,davinci-nand" }, + { } +}; + +U_BOOT_DRIVER(davinci_nand) = { + .name = "davinci-nand", + .id = UCLASS_MTD, + .of_match = davinci_nand_ids, + .probe = davinci_nand_probe, + .priv_auto_alloc_size = sizeof(struct nand_chip), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(davinci_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s: %d\n", dev->name, ret); +} +#else +int board_nand_init(struct nand_chip *chip) __attribute__((weak)); int board_nand_init(struct nand_chip *chip) { davinci_nand_init(chip); return 0; } +#endif /* CONFIG_SYS_NAND_SELF_INIT */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0a1d228a88..084e095229 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -196,7 +196,7 @@ config ETH_SANDBOX_RAW This driver is a bridge from the bottom of the network stack in U-Boot to the RAW AF_PACKET API in Linux. This allows real network traffic to be tested from within sandbox. See - board/sandbox/README.sandbox for more details. + doc/arch/index.rst for more details. config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 938cc75496..3004335c57 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -14,6 +14,7 @@ #include "pinctrl-mtk-common.h" +#if CONFIG_IS_ENABLED(PINCONF) /** * struct mtk_drive_desc - the structure that holds the information * of the driving current @@ -39,6 +40,7 @@ static const struct mtk_drive_desc mtk_drive[] = { [DRV_GRP3] = { 2, 8, 2, 2 }, [DRV_GRP4] = { 2, 16, 2, 1 }, }; +#endif static const char *mtk_pinctrl_dummy_name = "_dummy"; diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index ef23ca278a..5e1502ed96 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -4745,7 +4745,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP3_17_15, GP_0_30_FN, FN_IP3_14_12, GP_0_29_FN, FN_IP3_11_8, @@ -4777,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_11_9, GP_0_2_FN, FN_IP0_8_6, GP_0_1_FN, FN_IP0_5_3, - GP_0_0_FN, FN_IP0_2_0 } + GP_0_0_FN, FN_IP0_2_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, GP_1_29_FN, FN_IP6_13_11, @@ -4811,9 +4811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP3_28_26, GP_1_2_FN, FN_IP3_25_23, GP_1_1_FN, FN_IP3_22_20, - GP_1_0_FN, FN_IP3_19_18, } + GP_1_0_FN, FN_IP3_19_18, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 0, 0, 0, 0, GP_2_29_FN, FN_IP7_15_13, @@ -4845,9 +4845,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP8_3_2, GP_2_2_FN, FN_IP8_1_0, GP_2_1_FN, FN_IP7_30_29, - GP_2_0_FN, FN_IP7_28_27 } + GP_2_0_FN, FN_IP7_28_27 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP11_21_18, GP_3_30_FN, FN_IP11_17_15, GP_3_29_FN, FN_IP11_14_13, @@ -4879,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP9_3_2, GP_3_2_FN, FN_IP9_1_0, GP_3_1_FN, FN_IP8_30_29, - GP_3_0_FN, FN_IP8_28 } + GP_3_0_FN, FN_IP8_28 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP14_18_16, GP_4_30_FN, FN_IP14_15_12, GP_4_29_FN, FN_IP14_11_9, @@ -4913,9 +4913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP11_31_30, GP_4_2_FN, FN_IP11_29_27, GP_4_1_FN, FN_IP11_26_24, - GP_4_0_FN, FN_IP11_23_22 } + GP_4_0_FN, FN_IP11_23_22 )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP7_24_22, GP_5_30_FN, FN_IP7_21_19, GP_5_29_FN, FN_IP7_18_16, @@ -4947,10 +4947,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP14_30_28, GP_5_2_FN, FN_IP14_27_25, GP_5_1_FN, FN_IP14_24_22, - GP_5_0_FN, FN_IP14_21_19 } + GP_5_0_FN, FN_IP14_21_19 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { + GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3), + GROUP( /* IP0_31 [1] */ 0, 0, /* IP0_30_27 [4] */ @@ -4983,10 +4984,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP0_2_0 [3] */ FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { + GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4), + GROUP( /* IP1_31_30 [2] */ 0, 0, 0, 0, /* IP1_29_28 [2] */ @@ -5020,10 +5022,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_3_0 [4] */ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { + GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3), + GROUP( /* IP2_31_29 [3] */ 0, 0, 0, 0, 0, 0, 0, 0, /* IP2_28_26 [3] */ @@ -5049,10 +5052,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_5_3 [3] */ FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, /* IP2_2_0 [3] */ - FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { + GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4), + GROUP( /* IP3_31_29 [3] */ FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 0, 0, 0, @@ -5082,10 +5086,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_3_0 [4] */ FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP4_31_30 [2] */ 0, 0, 0, 0, /* IP4_29_27 [3] */ @@ -5115,10 +5120,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, /* IP4_2_0 [3] */ FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, - } + )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3), + GROUP( /* IP5_31_30 [2] */ 0, 0, 0, 0, /* IP5_29_27 [3] */ @@ -5152,10 +5158,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_INTC_EN0_N, FN_I2C1_SCL, /* IP5_2_0 [3] */ FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, - FN_VI2_R3, 0, 0, } + FN_VI2_R3, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3), + GROUP( /* IP6_31_29 [3] */ FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, @@ -5188,10 +5195,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, /* IP6_2_0 [3] */ FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, - FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), + GROUP( /* IP7_31 [1] */ 0, 0, /* IP7_30_29 [2] */ @@ -5223,11 +5231,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, /* IP7_2_0 [3] */ FN_ETH_MDIO, 0, FN_HRTS0_N_E, - FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2) { + GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2), + GROUP( /* IP8_31 [1] */ 0, 0, /* IP8_30_29 [2] */ @@ -5264,10 +5273,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP8_3_2 [2] */ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, /* IP8_1_0 [2] */ - FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2), + GROUP( /* IP9_31_28 [4] */ FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, @@ -5299,10 +5309,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP9_3_2 [2] */ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, /* IP9_1_0 [2] */ - FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 2, 4, 3, 4, 4, 4, 4, 3, 4) { + GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4), + GROUP( /* IP10_31_30 [2] */ 0, 0, 0, 0, /* IP10_29_26 [4] */ @@ -5338,10 +5349,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP10_3_0 [4] */ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, - FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4), + GROUP( /* IP11_31_30 [2] */ FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, /* IP11_29_27 [3] */ @@ -5373,10 +5385,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP11_3_0 [4] */ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, - FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2), + GROUP( /* IP12_31 [1] */ 0, 0, /* IP12_30_28 [3] */ @@ -5412,10 +5425,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP12_3_2 [2] */ FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, /* IP12_1_0 [2] */ - FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { + GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30_29 [2] */ @@ -5448,10 +5462,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_2_0 [3] */ FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, - FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } + FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, - 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3), + GROUP( /* IP14_30 [1] */ 0, 0, /* IP14_30_28 [3] */ @@ -5486,10 +5501,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP14_2_0 [3] */ FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, - FN_REMOCON, 0, } + FN_REMOCON, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { + GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP( /* IP15_31_30 [2] */ 0, 0, 0, 0, /* IP15_29_28 [2] */ @@ -5521,10 +5537,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_IIC2_SCL, FN_I2C2_SCL, 0, /* IP15_2_0 [3] */ FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, - FN_LCDOUT15, FN_SCIF_CLK_B, 0, } + FN_LCDOUT15, FN_SCIF_CLK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { + GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3), + GROUP( /* IP16_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5552,11 +5569,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, /* IP16_2_0 [3] */ FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, - FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { + GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1, + 1, 1, 1, 2, 1, 1, 2, 1, 1), + GROUP( /* SEL_SCIF1 [3] */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, FN_SEL_SCIF1_4, 0, 0, 0, @@ -5602,11 +5620,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SOF3 [1] */ FN_SEL_SOF3_0, FN_SEL_SOF3_1, /* SEL_SOF0 [1] */ - FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + FN_SEL_SOF0_0, FN_SEL_SOF0_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 3, 1, 1, 1, 2, 1, 2, 1, 2, - 1, 1, 1, 3, 3, 2, 3, 2, 2) { + GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1, + 3, 3, 2, 3, 2, 2), + GROUP( /* RESERVED [3] */ 0, 0, 0, 0, 0, 0, 0, 0, /* SEL_TMU1 [1] */ @@ -5644,11 +5663,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SIM [2] */ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, /* SEL_SSI8 [2] */ - FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 1, 1, 2, 4, 4, 2, 2, - 4, 2, 3, 2, 3, 2) { + GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2), + GROUP( /* SEL_IICDVFS [1] */ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, /* SEL_IIC0 [1] */ @@ -5679,7 +5698,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, FN_SEL_I2C2_4, 0, 0, 0, /* SEL_I2C1 [2] */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index 8166955459..d6095d6f67 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -5431,7 +5431,7 @@ static const struct { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP1_22_20, GP_0_30_FN, FN_IP1_19_17, GP_0_29_FN, FN_IP1_16_14, @@ -5463,9 +5463,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0, } + GP_0_0_FN, FN_IP0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5497,9 +5497,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP2_2_0, GP_1_2_FN, FN_IP1_31_29, GP_1_1_FN, FN_IP1_28_26, - GP_1_0_FN, FN_IP1_25_23, } + GP_1_0_FN, FN_IP1_25_23, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7_6, GP_2_30_FN, FN_IP6_5_3, GP_2_29_FN, FN_IP6_2_0, @@ -5531,9 +5531,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_4_2, GP_2_2_FN, FN_IP4_1_0, GP_2_1_FN, FN_IP3_30_28, - GP_2_0_FN, FN_IP3_27_25 } + GP_2_0_FN, FN_IP3_27_25 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP9_18_17, GP_3_30_FN, FN_IP9_16, GP_3_29_FN, FN_IP9_15_13, @@ -5565,9 +5565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP7_12_11, GP_3_2_FN, FN_IP7_10_9, GP_3_1_FN, FN_IP7_8_6, - GP_3_0_FN, FN_IP7_5_3 } + GP_3_0_FN, FN_IP7_5_3 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP15_5_4, GP_4_30_FN, FN_IP15_3_2, GP_4_29_FN, FN_IP15_1_0, @@ -5599,9 +5599,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP9_24_23, GP_4_2_FN, FN_IP9_22_21, GP_4_1_FN, FN_IP9_20_19, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP3_24_22, GP_5_30_FN, FN_IP13_9_7, GP_5_29_FN, FN_IP13_6_5, @@ -5633,9 +5633,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP11_18_17, GP_5_2_FN, FN_IP11_16_15, GP_5_1_FN, FN_IP11_14_12, - GP_5_0_FN, FN_IP11_11_9 } + GP_5_0_FN, FN_IP11_11_9 )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( GP_6_31_FN, FN_DU0_DOTCLKIN, GP_6_30_FN, FN_USB1_OVC, GP_6_29_FN, FN_IP14_31_29, @@ -5667,9 +5667,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP13_13, GP_6_2_FN, FN_IP13_12, GP_6_1_FN, FN_IP13_11, - GP_6_0_FN, FN_IP13_10 } + GP_6_0_FN, FN_IP13_10 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5701,11 +5701,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP15_26_24, GP_7_2_FN, FN_IP15_23_21, GP_7_1_FN, FN_IP15_20_18, - GP_7_0_FN, FN_IP15_17_15 } + GP_7_0_FN, FN_IP15_17_15 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31 [1] */ 0, 0, /* IP0_30_29 [2] */ @@ -5760,10 +5761,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ FN_D1, 0, /* IP0_0 [1] */ - FN_D0, 0, } + FN_D0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2), + GROUP( /* IP1_31_29 [3] */ FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 0, 0, 0, @@ -5796,10 +5798,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, /* IP1_1_0 [2] */ FN_A7, FN_MSIOF1_SYNC, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) { + GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), + GROUP( /* IP2_31_30 [2] */ 0, 0, 0, 0, /* IP2_29_27 [3] */ @@ -5832,10 +5835,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A20, FN_SPCLK, 0, 0, /* IP2_2_0 [3] */ FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, - FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, } + FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP( /* IP3_31 [1] */ 0, 0, /* IP3_30_28 [3] */ @@ -5870,10 +5874,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, /* IP3_2_0 [3] */ FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) { + GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, + 3, 3, 2), + GROUP( /* IP4_31 [1] */ 0, 0, /* IP4_30_28 [3] */ @@ -5912,10 +5918,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 0, 0, 0, /* IP4_1_0 [2] */ - FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, } + FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, + )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) { + GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3), + GROUP( /* IP5_31_29 [3] */ FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 0, 0, 0, 0, 0, @@ -5950,10 +5958,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_2_0 [3] */ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, FN_MSIOF2_TXD_D, FN_VI1_R3_B, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { + GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), + GROUP( /* IP6_31_30 [2] */ 0, 0, 0, 0, /* IP6_29_27 [3] */ @@ -5990,10 +5999,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP6_2_0 [3] */ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) { + GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), + GROUP( /* IP7_31_30 [2] */ 0, 0, 0, 0, /* IP7_29_27 [3] */ @@ -6031,10 +6041,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_2_0 [3] */ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, FN_SCIF_CLK_B, FN_GPS_MAG_D, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP8_31 [1] */ 0, 0, /* IP8_30_28 [3] */ @@ -6074,10 +6085,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, /* IP8_2_0 [3] */ FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) { + GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, + 1, 1, 3, 3), + GROUP( /* IP9_31_29 [3] */ FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, @@ -6117,10 +6130,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP9_2_0 [3] */ FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) { + GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3), + GROUP( /* IP10_31_29 [3] */ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 0, 0, 0, @@ -6154,11 +6168,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, /* IP10_2_0 [3] */ FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, - FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } + FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, - 3, 3, 3, 3, 3) { + GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, + 2, 3, 3, 3, 3, 3), + GROUP( /* IP11_31_30 [2] */ FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, /* IP11_29_28 [2] */ @@ -6201,10 +6216,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP11_2_0 [3] */ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, - FN_I2C1_SDA_D, 0, 0, 0, } + FN_I2C1_SDA_D, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), + GROUP( /* IP12_31_30 [2] */ 0, 0, 0, 0, /* IP12_29_27 [3] */ @@ -6242,11 +6258,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP12_3_2 [2] */ FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, /* IP12_1_0 [2] */ - FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, } + FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, - 3, 2, 2, 3) { + GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, + 1, 1, 1, 3, 2, 2, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30_28 [3] */ @@ -6293,10 +6310,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP13_2_0 [3] */ FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, FN_ADICLK_B, FN_MSIOF0_SS1_C, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, - 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { + GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, + 1, 1, 2), + GROUP( /* IP14_31_29 [3] */ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, @@ -6336,10 +6355,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP14_2 [1] */ FN_SD2_CLK, FN_MMC_CLK, /* IP14_1_0 [2] */ - FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, } + FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), + GROUP( /* IP15_31_30 [2] */ 0, 0, 0, 0, /* IP15_29_27 [3] */ @@ -6377,10 +6397,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP15_3_2 [2] */ FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, /* IP15_1_0 [2] */ - FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { + GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3), + GROUP( /* IP16_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -6409,11 +6430,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP16_2_0 [3] */ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, - 3, 2, 2, 2, 1, 2, 2, 2) { + GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, + 2, 2, 1, 2, 2, 2), + GROUP( /* RESERVED [1] */ 0, 0, /* SEL_SCIF1 [2] */ @@ -6454,11 +6476,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_TSIF0 [2] */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, /* SEL_SOF0 [2] */ - FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 3, 1, 1, 3, 2, 1, 1, 2, 2, - 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2, + 1, 2, 2, 2, 1, 1, 1), + GROUP( /* SEL_SCIF0 [3] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, @@ -6502,11 +6525,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [1] */ 0, 0, /* SEL_SSI8 [1] */ - FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + FN_SEL_SSI8_0, FN_SEL_SSI8_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 2, 2, 3, 2, 2, 2, 1) { + GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, + 3, 2, 2, 2, 1), + GROUP( /* SEL_HSCIF2 [2] */ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, @@ -6544,11 +6568,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [2] */ 0, 0, 0, 0, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, - 3, 2, 2, 1, 1, 1, 1, 3, 2, - 2, 3, 1, 1, 1, 2, 2, 2, 2) { + GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1, + 1, 1, 2, 2, 2, 2), + GROUP( /* SEL_SOF1 [3] */ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, FN_SEL_SOF1_4, @@ -6590,7 +6615,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [2] */ 0, 0, 0, 0, /* RESERVED [2] */ - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 95bb5237d9..1c90412093 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -1991,7 +1991,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2023,9 +2023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0 } + GP_0_0_FN, FN_IP0_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2057,9 +2057,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP1_8, GP_1_2_FN, FN_IP1_7, GP_1_1_FN, FN_IP1_6, - GP_1_0_FN, FN_IP1_5, } + GP_1_0_FN, FN_IP1_5, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_A15, GP_2_30_FN, FN_A14, GP_2_29_FN, FN_A13, @@ -2091,9 +2091,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_D3, GP_2_2_FN, FN_D2, GP_2_1_FN, FN_D1, - GP_2_0_FN, FN_D0 } + GP_2_0_FN, FN_D0 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2125,9 +2125,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_A19, GP_3_2_FN, FN_A18, GP_3_1_FN, FN_A17, - GP_3_0_FN, FN_A16 } + GP_3_0_FN, FN_A16 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2159,9 +2159,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_VI0_VSYNC_N, GP_4_2_FN, FN_VI0_HSYNC_N, GP_4_1_FN, FN_VI0_CLKENB, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2193,9 +2193,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_VI1_VSYNC_N, GP_5_2_FN, FN_VI1_HSYNC_N, GP_5_1_FN, FN_VI1_CLKENB, - GP_5_0_FN, FN_VI1_CLK } + GP_5_0_FN, FN_VI1_CLK )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2227,9 +2227,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP2_3, GP_6_2_FN, FN_IP2_2, GP_6_1_FN, FN_IP2_1, - GP_6_0_FN, FN_IP2_0 } + GP_6_0_FN, FN_IP2_0 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2261,9 +2261,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP3_3, GP_7_2_FN, FN_IP3_2, GP_7_1_FN, FN_IP3_1, - GP_7_0_FN, FN_IP3_0 } + GP_7_0_FN, FN_IP3_0 )) }, - { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) { + { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2295,9 +2295,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_8_3_FN, FN_IP4_3_2, GP_8_2_FN, FN_IP4_1, GP_8_1_FN, FN_IP4_0, - GP_8_0_FN, FN_VI4_CLK } + GP_8_0_FN, FN_VI4_CLK )) }, - { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) { + { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2329,9 +2329,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_9_3_FN, FN_IP5_2, GP_9_2_FN, FN_IP5_1, GP_9_1_FN, FN_IP5_0, - GP_9_0_FN, FN_VI5_CLK } + GP_9_0_FN, FN_VI5_CLK )) }, - { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) { + { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP( GP_10_31_FN, FN_CAN1_RX, GP_10_30_FN, FN_CAN1_TX, GP_10_29_FN, FN_CAN_CLK, @@ -2363,9 +2363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_10_3_FN, FN_IP6_2, GP_10_2_FN, FN_HRTS0_N, GP_10_1_FN, FN_IP6_1, - GP_10_0_FN, FN_IP6_0 } + GP_10_0_FN, FN_IP6_0 )) }, - { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) { + { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP( 0, 0, 0, 0, GP_11_29_FN, FN_AVS2, @@ -2397,13 +2397,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_11_3_FN, FN_IP7_6, GP_11_2_FN, FN_IP7_5_4, GP_11_1_FN, FN_IP7_3_2, - GP_11_0_FN, FN_IP7_1_0 } + GP_11_0_FN, FN_IP7_1_0 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP0_27_24 [4] */ @@ -2455,13 +2456,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ FN_DU0_DR1_DATA1, 0, /* IP0_0 [1] */ - FN_DU0_DR0_DATA0, 0 } + FN_DU0_DR0_DATA0, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP1_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP1_27_24 [4] */ @@ -2513,13 +2515,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_1 [1] */ FN_DU0_EXVSYNC_DU0_VSYNC, 0, /* IP1_0 [1] */ - FN_DU0_EXHSYNC_DU0_HSYNC, 0 } + FN_DU0_EXHSYNC_DU0_HSYNC, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, - 4, 4, - 4, 3, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 3, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP2_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP2_27_24 [4] */ @@ -2561,13 +2564,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_1 [1] */ FN_VI2_CLKENB, FN_AVB_RX_DV, /* IP2_0 [1] */ - FN_VI2_CLK, FN_AVB_RX_CLK } + FN_VI2_CLK, FN_AVB_RX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, - 4, 4, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP3_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP3_27_24 [4] */ @@ -2607,12 +2611,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_1 [1] */ FN_VI3_CLKENB, FN_AVB_TXD4, /* IP3_0 [1] */ - FN_VI3_CLK, FN_AVB_TX_CLK } + FN_VI3_CLK, FN_AVB_TX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, - 4, 3, 1, - 1, 1, 1, 2, 2, 2, - 2, 2, 2, 2, 2, 1, 2, 1, 1) { + GROUP(4, 3, 1, + 1, 1, 1, 2, 2, 2, + 2, 2, 2, 2, 2, 1, 2, 1, 1), + GROUP( /* IP4_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP4_27_25 [3] */ @@ -2648,13 +2653,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP4_1 [1] */ FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5, /* IP4_0 [1] */ - FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 } + FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, - 4, 4, - 4, 4, - 4, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 4, + 4, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP5_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP5_27_24 [4] */ @@ -2688,13 +2694,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_1 [1] */ FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B, /* IP5_0 [1] */ - FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B } + FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, - 4, 4, - 4, 1, 2, 1, - 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 1, 2, 1, + 2, 2, 2, 2, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP6_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP6_27_24 [4] */ @@ -2730,13 +2737,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP6_1 [1] */ FN_MSIOF0_SYNC, FN_HCTS0_N, /* IP6_0 [1] */ - FN_MSIOF0_SCK, FN_HSCK0 } + FN_MSIOF0_SCK, FN_HSCK0 )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, - 4, 4, - 3, 1, 1, 1, 1, 1, - 2, 2, 2, 2, - 1, 1, 2, 2, 2) { + GROUP(4, 4, + 3, 1, 1, 1, 1, 1, + 2, 2, 2, 2, + 1, 1, 2, 2, 2), + GROUP( /* IP7_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP7_27_24 [4] */ @@ -2770,7 +2778,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_3_2 [2] */ FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0, /* IP7_1_0 [2] */ - FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 } + FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 657ebca783..91ac815f3d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -4619,7 +4619,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP2_17_16, GP_0_30_FN, FN_IP2_15_14, GP_0_29_FN, FN_IP2_13_12, @@ -4651,9 +4651,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_27_26, GP_0_2_FN, FN_IP0_25, GP_0_1_FN, FN_IP0_24, - GP_0_0_FN, FN_IP0_23_22, } + GP_0_0_FN, FN_IP0_23_22, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4685,9 +4685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP2_29_27, GP_1_2_FN, FN_IP2_26_24, GP_1_1_FN, FN_IP2_23_21, - GP_1_0_FN, FN_IP2_20_18, } + GP_1_0_FN, FN_IP2_20_18, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7_6, GP_2_30_FN, FN_IP6_5_4, GP_2_29_FN, FN_IP6_3_2, @@ -4719,9 +4719,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_11_10, GP_2_2_FN, FN_IP4_9_8, GP_2_1_FN, FN_IP4_7_5, - GP_2_0_FN, FN_IP4_4_2 } + GP_2_0_FN, FN_IP4_4_2 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP8_22_20, GP_3_30_FN, FN_IP8_19_17, GP_3_29_FN, FN_IP8_16_15, @@ -4753,9 +4753,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP6_11, GP_3_2_FN, FN_IP6_10, GP_3_1_FN, FN_IP6_9, - GP_3_0_FN, FN_IP6_8 } + GP_3_0_FN, FN_IP6_8 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP11_17_16, GP_4_30_FN, FN_IP11_15_14, GP_4_29_FN, FN_IP11_13_11, @@ -4787,9 +4787,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP9_2_0, GP_4_2_FN, FN_IP8_31_29, GP_4_1_FN, FN_IP8_28_26, - GP_4_0_FN, FN_IP8_25_23 } + GP_4_0_FN, FN_IP8_25_23 )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4821,9 +4821,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP11_29_27, GP_5_2_FN, FN_IP11_26_24, GP_5_1_FN, FN_IP11_23_21, - GP_5_0_FN, FN_IP11_20_18 } + GP_5_0_FN, FN_IP11_20_18 )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4855,11 +4855,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_SD0_DATA1, GP_6_2_FN, FN_SD0_DATA0, GP_6_1_FN, FN_SD0_CMD, - GP_6_0_FN, FN_SD0_CLK } + GP_6_0_FN, FN_SD0_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, - 2, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, + 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31_30 [2] */ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, /* IP0_29_28 [2] */ @@ -4909,11 +4910,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ 0, 0, /* IP0_0 [1] */ - FN_SD1_CD, FN_CAN0_RX, } + FN_SD1_CD, FN_CAN0_RX, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, - 2, 2) { + GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, + 3, 2, 2, 2, 2), + GROUP( /* IP1_31_30 [2] */ FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, /* IP1_29_28 [2] */ @@ -4949,10 +4951,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_3_2 [2] */ FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, /* IP1_1_0 [2] */ - FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2), + GROUP( /* IP2_31_30 [2] */ FN_A20, FN_SPCLK, 0, 0, /* IP2_29_27 [3] */ @@ -4984,10 +4987,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_3_2 [2] */ FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, /* IP2_1_0 [2] */ - FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { + GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, + 2, 2, 2, 2), + GROUP( /* IP3_31 [1] */ FN_RD_WR_N, FN_ATAG1_N, /* IP3_30 [1] */ @@ -5024,10 +5029,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_3_2 [2] */ FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N, /* IP3_1_0 [2] */ - FN_A21, FN_MOSI_IO0, 0, 0, } + FN_A21, FN_MOSI_IO0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { + GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2), + GROUP( /* IP4_31_30 [2] */ FN_DU0_DG4, FN_LCDOUT12, 0, 0, /* IP4_29_28 [2] */ @@ -5059,10 +5065,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 0, 0, 0, 0, /* IP4_1_0 [2] */ - FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, } + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { + GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, + 2, 2, 2), + GROUP( /* IP5_31_30 [2] */ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0, /* IP5_29_28 [2] */ @@ -5094,11 +5102,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_3_2 [2] */ FN_DU0_DG6, FN_LCDOUT14, 0, 0, /* IP5_1_0 [2] */ - FN_DU0_DG5, FN_LCDOUT13, 0, 0, } + FN_DU0_DG5, FN_LCDOUT13, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, - 2, 2) { + GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 2, 2, 2, 2), + GROUP( /* IP6_31_29 [3] */ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, FN_ADIDATA, 0, 0, @@ -5140,10 +5149,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, /* IP6_1_0 [2] */ - FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, } + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP7_31 [1] */ FN_DREQ0_N, FN_SCIFB1_RXD, /* IP7_30 [1] */ @@ -5177,10 +5187,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_TXD1, FN_ADICLK, 0, 0, /* IP7_2_0 [3] */ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, - FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, } + FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3), + GROUP( /* IP8_31_29 [3] */ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, 0, FN_TS_SDEN_D, FN_FMCLK_C, 0, @@ -5212,10 +5223,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, /* IP8_2_0 [3] */ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, - FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3), + GROUP( /* IP9_31 [1] */ 0, 0, /* IP9_30_28 [3] */ @@ -5248,10 +5260,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, FN_TPUTO1_C, 0, 0, /* IP9_2_0 [3] */ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, - 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, } + 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP10_31_30 [2] */ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0, /* IP10_29_27 [3] */ @@ -5283,10 +5296,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IP10_2_0 [3] */ FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3), + GROUP( /* IP11_31_30 [2] */ 0, 0, 0, 0, /* IP11_29_27 [3] */ @@ -5318,10 +5332,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IP11_2_0 [3] */ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3), + GROUP( /* IP12_31_30 [2] */ 0, 0, 0, 0, /* IP12_29_27 [3] */ @@ -5353,10 +5368,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_CAN1_RX_C, FN_DACK1_B, 0, 0, /* IP12_2_0 [3] */ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, - 0, FN_DREQ1_N_B, 0, 0, } + 0, FN_DREQ1_N_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30 [1] */ @@ -5393,11 +5409,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, /* IP13_2_0 [3] */ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, - 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, } + 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, - 2, 1) { + GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1), + GROUP( /* SEL_ADG [2] */ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, /* RESERVED [1] */ @@ -5431,11 +5447,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C05 [2] */ FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, - 2, 2, 2, 1, 1, 2) { + GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, + 2, 2, 1, 1, 2, 2, 2, 1, 1, 2), + GROUP( /* SEL_IEB [2] */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_IIC0 [2] */ @@ -5482,11 +5499,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_HSCIF1 [1] */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, /* RESERVED [2] */ - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* SEL_SCIF0 [2] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, /* SEL_SCIF1 [2] */ @@ -5539,7 +5557,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [1] */ 0, 0, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index 89ae6f6ed7..ba17a55775 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -2,7 +2,7 @@ /* * R8A7795 ES2.0+ processor support - PFC hardware block. * - * Copyright (C) 2015-2017 Renesas Electronics Corporation + * Copyright (C) 2015-2019 Renesas Electronics Corporation */ #include <common.h> @@ -202,8 +202,8 @@ #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) /* GPSR7 */ -#define GPSR7_3 FM(HDMI1_CEC) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_3 FM(GP7_03) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -352,7 +352,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -463,7 +463,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -499,8 +499,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -592,8 +592,8 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS1), PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), - PINMUX_SINGLE(HDMI0_CEC), - PINMUX_SINGLE(HDMI1_CEC), + PINMUX_SINGLE(GP7_02), + PINMUX_SINGLE(GP7_03), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -1131,7 +1131,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1164,7 +1164,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1223,7 +1223,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1270,7 +1270,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1279,7 +1279,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1410,10 +1410,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -2133,22 +2132,6 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; -/* - HDMI ------------------------------------------------------------------- */ -static const unsigned int hdmi0_cec_pins[] = { - /* HDMI0_CEC */ - RCAR_GP_PIN(7, 2), -}; -static const unsigned int hdmi0_cec_mux[] = { - HDMI0_CEC_MARK, -}; -static const unsigned int hdmi1_cec_pins[] = { - /* HDMI1_CEC */ - RCAR_GP_PIN(7, 3), -}; -static const unsigned int hdmi1_cec_mux[] = { - HDMI1_CEC_MARK, -}; - /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -4227,8 +4210,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hdmi0_cec), - SH_PFC_PIN_GROUP(hdmi1_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4613,14 +4594,6 @@ static const char * const du_groups[] = { "du_disp", }; -static const char * const hdmi0_groups[] = { - "hdmi0_cec", -}; - -static const char * const hdmi1_groups[] = { - "hdmi1_cec", -}; - static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -5039,8 +5012,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hdmi0), - SH_PFC_FUNCTION(hdmi1), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5090,7 +5061,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5122,9 +5093,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5156,9 +5127,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5190,9 +5161,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5224,9 +5195,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5258,9 +5229,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5292,9 +5263,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5326,9 +5297,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5360,14 +5331,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5375,9 +5346,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5385,9 +5356,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5395,9 +5366,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5405,9 +5376,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5415,9 +5386,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5425,9 +5396,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5435,9 +5406,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5445,9 +5416,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5455,9 +5426,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5465,9 +5436,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5475,9 +5446,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5485,9 +5456,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5495,9 +5466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5505,9 +5476,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5515,9 +5486,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5525,9 +5496,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5535,9 +5506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5545,9 +5516,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5555,7 +5526,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5563,8 +5534,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5585,11 +5557,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5612,11 +5585,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5643,7 +5617,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5764,8 +5738,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ } }, @@ -5899,10 +5873,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -6019,8 +5995,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ - [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ + [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ } }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 24fbbf19aa..a92c8ad18c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -2,7 +2,7 @@ /* * R8A7796 processor support - PFC hardware block. * - * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2016-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c * @@ -209,7 +209,7 @@ /* GPSR7 */ #define GPSR7_3 FM(GP7_03) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -358,7 +358,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -469,7 +469,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -502,12 +502,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -600,7 +600,7 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -1024,35 +1024,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1118,28 +1118,28 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), - PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), - PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1172,7 +1172,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1231,7 +1231,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1277,8 +1277,8 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1287,7 +1287,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1415,10 +1415,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -1502,11 +1501,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), - /* I2C */ - PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), - /* * Static pins can not be muxed between different functions but * still need mark entries in the pinmux list. Add each static @@ -2143,15 +2137,6 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; -/* - HDMI ------------------------------------------------------------------- */ -static const unsigned int hdmi0_cec_pins[] = { - /* HDMI0_CEC */ - RCAR_GP_PIN(7, 2), -}; -static const unsigned int hdmi0_cec_mux[] = { - HDMI0_CEC_MARK, -}; - /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -4127,8 +4112,8 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[310]; - struct sh_pfc_pin_group automotive[33]; + struct sh_pfc_pin_group common[312]; + struct sh_pfc_pin_group automotive[30]; } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4163,6 +4148,9 @@ static const struct { SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4171,7 +4159,6 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hdmi0_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4443,9 +4430,6 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk), }, .automotive = { - SH_PFC_PIN_GROUP(canfd0_data_a), - SH_PFC_PIN_GROUP(canfd0_data_b), - SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -4588,10 +4572,6 @@ static const char * const du_groups[] = { "du_disp", }; -static const char * const hdmi0_groups[] = { - "hdmi0_cec", -}; - static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -4985,8 +4965,8 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[48]; - struct sh_pfc_function automotive[6]; + struct sh_pfc_function common[49]; + struct sh_pfc_function automotive[4]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4994,8 +4974,9 @@ static const struct { SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hdmi0), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5039,8 +5020,6 @@ static const struct { SH_PFC_FUNCTION(vin5), }, .automotive = { - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), @@ -5051,7 +5030,7 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5083,9 +5062,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5117,9 +5096,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5151,9 +5130,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5185,9 +5164,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5219,9 +5198,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5253,9 +5232,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5287,9 +5266,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5321,14 +5300,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5336,9 +5315,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5346,9 +5325,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5356,9 +5335,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5366,9 +5345,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5376,9 +5355,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5386,9 +5365,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5396,9 +5375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5406,9 +5385,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5416,9 +5395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5426,9 +5405,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5436,9 +5415,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5446,9 +5425,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5456,9 +5435,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5466,9 +5445,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5476,9 +5455,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5486,9 +5465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5496,9 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5506,9 +5485,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5516,7 +5495,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5524,8 +5503,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5546,11 +5526,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5573,11 +5554,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5603,7 +5585,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5724,7 +5706,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ @@ -5858,10 +5840,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -5978,7 +5962,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 7c24836d2c..2523904aec 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -3,7 +3,7 @@ * R8A77965 processor support - PFC hardware block. * * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> - * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c * @@ -210,7 +210,7 @@ /* GPSR7 */ #define GPSR7_3 FM(GP7_03) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -359,7 +359,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -470,7 +470,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -503,12 +503,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -560,6 +560,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -585,6 +588,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -597,7 +601,7 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -622,13 +626,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -681,14 +687,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1019,35 +1027,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1114,26 +1122,28 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), - PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), - PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1166,7 +1176,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1225,7 +1235,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1271,8 +1281,8 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1281,7 +1291,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1410,10 +1420,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -1497,11 +1506,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), - /* I2C */ - PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), - /* * Static pins can not be muxed between different functions but * still need mark entries in the pinmux list. Add each static @@ -2481,52 +2485,92 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), }; + static const unsigned int i2c1_a_mux[] = { SDA1_A_MARK, SCL1_A_MARK, }; + static const unsigned int i2c1_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), }; + static const unsigned int i2c1_b_mux[] = { SDA1_B_MARK, SCL1_B_MARK, }; + static const unsigned int i2c2_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), }; + static const unsigned int i2c2_a_mux[] = { SDA2_A_MARK, SCL2_A_MARK, }; + static const unsigned int i2c2_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; + static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), }; + static const unsigned int i2c6_a_mux[] = { SDA6_A_MARK, SCL6_A_MARK, }; + static const unsigned int i2c6_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), }; + static const unsigned int i2c6_b_mux[] = { SDA6_B_MARK, SCL6_B_MARK, }; + static const unsigned int i2c6_c_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), }; + static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; @@ -4416,10 +4460,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4810,6 +4857,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4820,6 +4871,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -5169,8 +5228,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), @@ -5208,7 +5270,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5240,9 +5302,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5274,9 +5336,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5308,9 +5370,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5342,9 +5404,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5376,9 +5438,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5410,9 +5472,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5444,9 +5506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5478,14 +5540,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5493,9 +5555,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5503,9 +5565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5513,9 +5575,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5523,9 +5585,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5533,9 +5595,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5543,9 +5605,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5553,9 +5615,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5563,9 +5625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5573,9 +5635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5583,9 +5645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5593,9 +5655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5603,9 +5665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5613,9 +5675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5623,9 +5685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5633,9 +5695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5643,9 +5705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5653,9 +5715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5663,9 +5725,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5673,7 +5735,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5681,8 +5743,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5703,11 +5766,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5730,11 +5794,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5760,7 +5825,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5881,7 +5946,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ @@ -6015,10 +6080,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -6135,7 +6202,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 823edb559d..33ecd93398 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -173,19 +173,19 @@ #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -200,18 +200,18 @@ #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -472,7 +472,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), - PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT), PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), @@ -498,7 +497,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), - PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), PINMUX_IPSR_GPSR(IP3_15_12, HRX3), PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), @@ -529,7 +528,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), PINMUX_IPSR_GPSR(IP4_11_8, HRX1), - PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), @@ -619,7 +618,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5), PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), - PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS), + PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N), PINMUX_IPSR_GPSR(IP6_23_20, D12), PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), @@ -666,7 +665,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1), PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), - PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC), PINMUX_IPSR_GPSR(IP7_23_20, SCL2), @@ -1470,7 +1469,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ @@ -1493,7 +1492,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { /* RX, TX */ @@ -1523,7 +1522,7 @@ static const unsigned int scif3_ctrl_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; /* - SCIF4 ------------------------------------------------------------------ */ @@ -1546,7 +1545,7 @@ static const unsigned int scif4_ctrl_pins[] = { RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; static const unsigned int scif4_ctrl_mux[] = { - RTS4_N_TANS_MARK, CTS4_N_MARK, + RTS4_N_MARK, CTS4_N_MARK, }; /* - TMU -------------------------------------------------------------------- */ @@ -2074,7 +2073,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2106,9 +2105,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2140,9 +2139,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2174,9 +2173,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2208,9 +2207,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2242,9 +2241,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2276,14 +2275,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -2291,9 +2290,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -2301,9 +2300,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -2311,9 +2310,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -2321,9 +2320,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -2331,9 +2330,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -2341,9 +2340,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -2351,9 +2350,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -2361,9 +2360,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -2371,7 +2370,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, #undef F_ #undef FM @@ -2379,8 +2378,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 4, 4, 4, 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( /* RESERVED 31, 30, 29, 28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 27, 26, 25, 24 */ @@ -2402,21 +2402,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_3 MOD_SEL0_2 MOD_SEL0_1 - MOD_SEL0_0 } + MOD_SEL0_0 )) }, { }, }; enum ioctrl_regs { - IOCTRL30, - IOCTRL31, - IOCTRL32, + POCCTRL0, + POCCTRL1, + POCCTRL2, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [IOCTRL30] = { 0xe6060380 }, - [IOCTRL31] = { 0xe6060384 }, - [IOCTRL32] = { 0xe6060388 }, + [POCCTRL0] = { 0xe6060380 }, + [POCCTRL1] = { 0xe6060384 }, + [POCCTRL2] = { 0xe6060388 }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -2425,13 +2427,13 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, { int bit = pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) return bit; if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) return bit + 22; - *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) return bit - 10; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 1cf08ae471..5313f2f509 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2,7 +2,7 @@ /* * R8A77990 processor support - PFC hardware block. * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c * @@ -168,7 +168,7 @@ #define GPSR5_7 F_(SCK2_A, IP12_7_4) #define GPSR5_6 F_(TX1, IP12_3_0) #define GPSR5_5 F_(RX1, IP11_31_28) -#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20) +#define GPSR5_4 F_(RTS0_N_A, IP11_23_20) #define GPSR5_3 F_(CTS0_N_A, IP11_19_16) #define GPSR5_2 F_(TX0_A, IP11_15_12) #define GPSR5_1 F_(RX0_A, IP11_11_8) @@ -222,7 +222,7 @@ #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -243,10 +243,10 @@ #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -292,8 +292,8 @@ #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ @@ -417,7 +417,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) -#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) @@ -432,8 +432,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ -#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) -#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) @@ -454,8 +452,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define PINMUX_MOD_SELS \ \ - MOD_SEL1_31 \ -MOD_SEL0_30_29 MOD_SEL1_30 \ +MOD_SEL0_30_29 \ MOD_SEL1_29 \ MOD_SEL0_28 MOD_SEL1_28 \ MOD_SEL0_27_26 \ @@ -674,7 +671,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), PINMUX_IPSR_GPSR(IP3_15_12, A4), - PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0), PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), @@ -824,7 +821,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), - PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2), PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), PINMUX_IPSR_GPSR(IP5_31_28, D2), @@ -848,7 +845,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), - PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0), PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), @@ -987,23 +984,23 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), - PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1), /* IPSR9 */ PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), - PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), - PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), - PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), @@ -1040,57 +1037,57 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), - PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A), + PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B), PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), - PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A), + PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B), PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), - PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), - PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A), PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), - PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A), PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), - PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), - PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0), - PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), @@ -1099,7 +1096,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), - PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), @@ -1183,7 +1180,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), - PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), + PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A), PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), @@ -1251,7 +1248,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), - PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B), PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), @@ -2842,7 +2839,7 @@ static const unsigned int scif0_ctrl_a_pins[] = { }; static const unsigned int scif0_ctrl_a_mux[] = { - RTS0_N_TANS_A_MARK, CTS0_N_A_MARK, + RTS0_N_A_MARK, CTS0_N_A_MARK, }; static const unsigned int scif0_data_b_pins[] = { @@ -2888,7 +2885,7 @@ static const unsigned int scif1_ctrl_pins[] = { }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; /* - SCIF2 ------------------------------------------------------------------ */ @@ -2944,7 +2941,7 @@ static const unsigned int scif3_ctrl_a_pins[] = { }; static const unsigned int scif3_ctrl_a_mux[] = { - RTS3_N_TANS_A_MARK, CTS3_N_A_MARK, + RTS3_N_A_MARK, CTS3_N_A_MARK, }; static const unsigned int scif3_data_b_pins[] = { @@ -2999,7 +2996,7 @@ static const unsigned int scif4_ctrl_a_pins[] = { }; static const unsigned int scif4_ctrl_a_mux[] = { - RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, + RTS4_N_A_MARK, CTS4_N_A_MARK, }; static const unsigned int scif4_data_b_pins[] = { @@ -3035,7 +3032,7 @@ static const unsigned int scif4_ctrl_c_pins[] = { }; static const unsigned int scif4_ctrl_c_mux[] = { - RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, + RTS4_N_C_MARK, CTS4_N_C_MARK, }; /* - SCIF5 ------------------------------------------------------------------ */ @@ -3769,8 +3766,8 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[245]; - struct sh_pfc_pin_group automotive[23]; + struct sh_pfc_pin_group common[247]; + struct sh_pfc_pin_group automotive[21]; } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -3801,6 +3798,8 @@ static const struct { SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_in_0), @@ -4020,8 +4019,6 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk_b), }, .automotive = { - SH_PFC_PIN_GROUP(canfd0_data), - SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -4468,8 +4465,8 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[45]; - struct sh_pfc_function automotive[6]; + struct sh_pfc_function common[47]; + struct sh_pfc_function automotive[4]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4477,6 +4474,8 @@ static const struct { SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4519,8 +4518,6 @@ static const struct { SH_PFC_FUNCTION(vin5), }, .automotive = { - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), @@ -4531,7 +4528,7 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4563,9 +4560,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4597,9 +4594,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4631,9 +4628,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4665,9 +4662,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4699,9 +4696,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4733,9 +4730,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4767,14 +4764,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -4782,9 +4779,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -4792,9 +4789,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -4802,9 +4799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -4812,9 +4809,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -4822,9 +4819,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -4832,9 +4829,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -4842,9 +4839,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -4852,9 +4849,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -4862,9 +4859,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -4872,9 +4869,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -4882,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -4892,9 +4889,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -4902,9 +4899,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -4912,9 +4909,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -4922,9 +4919,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -4932,7 +4929,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, #undef F_ #undef FM @@ -4940,8 +4937,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, - 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) { + GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, + 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), + GROUP( /* RESERVED 31 */ 0, 0, MOD_SEL0_30_29 @@ -4965,13 +4963,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_4 MOD_SEL0_3 MOD_SEL0_2 - MOD_SEL0_1_0 } + MOD_SEL0_1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, - 1, 2, 2, 2, 1, 1, 2, 1, 4) { - MOD_SEL1_31 - MOD_SEL1_30 + GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, + 2, 2, 2, 1, 1, 2, 1, 4), + GROUP( + /* RESERVED 31, 30 */ + 0, 0, 0, 0, MOD_SEL1_29 MOD_SEL1_28 /* RESERVED 27 */ @@ -4992,17 +4991,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_6_5 MOD_SEL1_4 /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) }, { }, }; enum ioctrl_regs { - IOCTRL30, + POCCTRL0, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [IOCTRL30] = { 0xe6060380, }, + [POCCTRL0] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -5011,7 +5012,7 @@ static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, { int bit = -EINVAL; - *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -5127,7 +5128,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ - [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */ + [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */ [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index ed678584cb..724cf4ae3c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -290,7 +290,7 @@ #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -301,7 +301,7 @@ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -860,7 +860,7 @@ static const u16 pinmux_data[] = { /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_3_0, SDA1), - PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N), PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), @@ -895,7 +895,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), - PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N), PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), PINMUX_IPSR_GPSR(IP12_11_8, SCK2), @@ -1707,7 +1707,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_a_pins[] = { @@ -1743,7 +1743,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; /* - SCIF2 ------------------------------------------------------------------ */ @@ -2377,7 +2377,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2409,9 +2409,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( GP_1_31_FN, GPSR1_31, GP_1_30_FN, GPSR1_30, GP_1_29_FN, GPSR1_29, @@ -2443,9 +2443,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( GP_2_31_FN, GPSR2_31, GP_2_30_FN, GPSR2_30, GP_2_29_FN, GPSR2_29, @@ -2477,9 +2477,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2511,9 +2511,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( GP_4_31_FN, GPSR4_31, GP_4_30_FN, GPSR4_30, GP_4_29_FN, GPSR4_29, @@ -2545,9 +2545,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2579,9 +2579,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2613,14 +2613,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -2628,9 +2628,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -2638,9 +2638,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -2648,9 +2648,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -2658,9 +2658,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -2668,9 +2668,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -2678,9 +2678,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -2688,9 +2688,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -2698,9 +2698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -2708,9 +2708,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -2718,9 +2718,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -2728,9 +2728,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -2738,9 +2738,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -2748,9 +2748,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2758,7 +2758,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, #undef F_ #undef FM @@ -2766,8 +2766,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, - 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { + GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, + 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1), + GROUP( /* RESERVED 31 */ 0, 0, MOD_SEL0_30 @@ -2795,11 +2796,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_3 MOD_SEL0_2 MOD_SEL0_1 - MOD_SEL0_0 } + MOD_SEL0_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 1, 1, 1, 1, 1, 1, 2, 4, 4, - 4, 4, 4, 4) { + GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4), + GROUP( MOD_SEL1_31 MOD_SEL1_30 MOD_SEL1_29 @@ -2819,7 +2820,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED 7, 6, 5, 4 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) }, { }, }; @@ -2836,6 +2837,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po return bit; } +enum ioctrl_regs { + TDSELCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [TDSELCTRL] = { 0xe60603c0, }, + { /* sentinel */ }, +}; + static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, }; @@ -2855,6 +2865,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index d1271dad44..f2973bebef 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -469,7 +469,7 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev, const struct sh_pfc_pin *pin = NULL; int i, ret, idx; - for (i = 1; i < pfc->info->nr_pins; i++) { + for (i = 0; i < pfc->info->nr_pins; i++) { if (priv->pfc.info->pins[i].pin != pin_selector) continue; @@ -505,7 +505,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev, const struct sh_pfc_pin *pin = NULL; int i, idx; - for (i = 1; i < pfc->info->nr_pins; i++) { + for (i = 0; i < pfc->info->nr_pins; i++) { if (priv->pfc.info->pins[i].pin != pin_selector) continue; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 6629e1f772..f6159b8a3a 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -41,7 +41,8 @@ struct sh_pfc_pin { .name = #alias, \ .pins = n##_pins, \ .mux = n##_mux, \ - .nr_pins = ARRAY_SIZE(n##_pins), \ + .nr_pins = ARRAY_SIZE(n##_pins) + \ + BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ } #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) @@ -110,40 +111,54 @@ struct pinmux_func { struct pinmux_cfg_reg { u32 reg; u8 reg_width, field_width; +#ifdef DEBUG + u16 nr_enum_ids; /* for variable width regs only */ +#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, +#else +#define SET_NR_ENUM_IDS(n) +#endif const u16 *enum_ids; const u8 *var_field_width; }; +#define GROUP(...) __VA_ARGS__ + /* * Describe a config register consisting of several fields of the same width * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) * - f_width: Width of the fixed-width register fields (in bits) - * This macro must be followed by initialization data: For each register field - * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified, - * one for each possible combination of the register field bit values. + * - ids: For each register field (from left to right, i.e. MSB to LSB), + * 2^f_width enum IDs must be specified, one for each possible + * combination of the register field bit values, all wrapped using + * the GROUP() macro. */ -#define PINMUX_CFG_REG(name, r, r_width, f_width) \ - .reg = r, .reg_width = r_width, .field_width = f_width, \ - .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) +#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ + .reg = r, .reg_width = r_width, \ + .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ + BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ + (r_width / f_width) * (1 << f_width)), \ + .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ + { ids } /* * Describe a config register consisting of several fields of different widths * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) - * - var_fw0, var_fwn...: List of widths of the register fields (in bits), - * From left to right (i.e. MSB to LSB) - * This macro must be followed by initialization data: For each register field - * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified, - * one for each possible combination of the register field bit values. + * - f_widths: List of widths of the register fields (in bits), from left + * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. + * - ids: For each register field (from left to right, i.e. MSB to LSB), + * 2^f_widths[i] enum IDs must be specified, one for each possible + * combination of the register field bit values, all wrapped using + * the GROUP() macro. */ -#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ - .reg = r, .reg_width = r_width, \ - .var_field_width = (const u8 [r_width]) \ - { var_fw0, var_fwn, 0 }, \ - .enum_ids = (const u16 []) +#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ + .reg = r, .reg_width = r_width, \ + .var_field_width = (const u8 []) { f_widths, 0 }, \ + SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ + .enum_ids = (const u16 []) { ids } struct pinmux_drive_reg_field { u16 pin; @@ -186,12 +201,14 @@ struct pinmux_data_reg { * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) - * This macro must be followed by initialization data: For each register bit - * (from left to right, i.e. MSB to LSB), one enum ID must be specified. + * - ids: For each register bit (from left to right, i.e. MSB to LSB), one + * enum ID must be specified, all wrapped using the GROUP() macro. */ -#define PINMUX_DATA_REG(name, r, r_width) \ - .reg = r, .reg_width = r_width, \ - .enum_ids = (const u16 [r_width]) \ +#define PINMUX_DATA_REG(name, r, r_width, ids) \ + .reg = r, .reg_width = r_width + \ + BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ + r_width), \ + .enum_ids = (const u16 [r_width]) { ids } struct pinmux_irq { const short *gpios; @@ -371,8 +388,8 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; /* * Describe a pinmux configuration in which a pin is physically multiplexed * with other pins. - * - ipsr: IPSR field - * - fn: Function name, also referring to the IPSR field + * - ipsr: IPSR field (unused, for documentation purposes only) + * - fn: Function name * - psel: Physical multiplexing selector */ #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ @@ -632,7 +649,9 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; */ #define PORTCR(nr, reg) \ { \ - PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ + GROUP(2, 2, 1, 3), \ + GROUP( \ /* PULMD[1:0], handled by .set_bias() */ \ 0, 0, 0, 0, \ /* IE and OE */ \ @@ -644,7 +663,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT##nr##_FN2, PORT##nr##_FN3, \ PORT##nr##_FN4, PORT##nr##_FN5, \ PORT##nr##_FN6, PORT##nr##_FN7 \ - } \ + )) \ } /* diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index ee4cbcb02f..822a3fe265 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -14,6 +14,7 @@ #include <common.h> #include <dm.h> +#include <dm/lists.h> #include <dm/of_access.h> #include <reset-uclass.h> #include <linux/bitops.h> @@ -130,6 +131,23 @@ static int socfpga_reset_remove(struct udevice *dev) return 0; } +static int socfpga_reset_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + + /* + * The sysreset driver does not have a device node, so bind it here. + * Bind it to the node, too, so that it can get its base address. + */ + ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset", + dev->node, &sys_child); + if (ret) + debug("Warning: No sysreset driver: ret=%d\n", ret); + + return 0; +} + static const struct udevice_id socfpga_reset_match[] = { { .compatible = "altr,rst-mgr" }, { /* sentinel */ }, @@ -139,6 +157,7 @@ U_BOOT_DRIVER(socfpga_reset) = { .name = "socfpga-reset", .id = UCLASS_RESET, .of_match = socfpga_reset_match, + .bind = socfpga_reset_bind, .probe = socfpga_reset_probe, .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), .ops = &socfpga_reset_ops, diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 0b58a18f5f..860b73d369 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -86,6 +86,11 @@ config RTC_RX8010SJ help Support for Epson RX8010SJ Real Time Clock devices. +config RTC_RX8025 + bool "Enable RX8025 driver" + help + Support for Epson RX8025 Real Time Clock devices. + config RTC_PL031 bool "Enable ARM AMBA PL031 RTC driver" help diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 7bd9f8b42a..e717dcbbfe 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -10,8 +10,9 @@ #include <common.h> #include <command.h> -#include <rtc.h> +#include <dm.h> #include <i2c.h> +#include <rtc.h> /*---------------------------------------------------------------------*/ #undef DEBUG_RTC @@ -27,6 +28,18 @@ # define CONFIG_SYS_I2C_RTC_ADDR 0x32 #endif +#ifdef CONFIG_DM_RTC +#define DEV_TYPE struct udevice +#else +/* Local udevice */ +struct ludevice { + u8 chip; +}; + +#define DEV_TYPE struct ludevice + +#endif + /* * RTC register addresses */ @@ -68,21 +81,35 @@ */ /* static uchar rtc_read (uchar reg); */ +#ifdef CONFIG_DM_RTC +/* + * on mpc85xx based board with DM and offset len 1 + * accessing rtc works fine. May we can drop this ? + */ +#define rtc_read(reg) buf[(reg) & 0xf] +#else #define rtc_read(reg) buf[((reg) + 1) & 0xf] +#endif -static void rtc_write (uchar reg, uchar val); +static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val); /* * Get the current time from the RTC */ -int rtc_get (struct rtc_time *tmp) +static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) { int rel = 0; uchar sec, min, hour, mday, wday, mon, year, ctl2; uchar buf[16]; - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) +#ifdef CONFIG_DM_RTC + if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { +#else + if (i2c_read(dev->chip, 0, 0, buf, 16)) { +#endif printf("Error reading from RTC\n"); + return -EIO; + } sec = rtc_read(RTC_SEC_REG_ADDR); min = rtc_read(RTC_MIN_REG_ADDR); @@ -92,9 +119,9 @@ int rtc_get (struct rtc_time *tmp) mon = rtc_read(RTC_MON_REG_ADDR); year = rtc_read(RTC_YR_REG_ADDR); - DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); + DEBUGR("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); /* dump status */ ctl2 = rtc_read(RTC_CTL2_REG_ADDR); @@ -113,13 +140,14 @@ int rtc_get (struct rtc_time *tmp) rel = -1; } - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412) - tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_hour = bcd2bin(hour & 0x3F); else - tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 + + tmp->tm_hour = bcd2bin(hour & 0x1F) % 12 + ((hour & 0x20) ? 12 : 0); + tmp->tm_mday = bcd2bin (mday & 0x3F); tmp->tm_mon = bcd2bin (mon & 0x1F); tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); @@ -127,9 +155,9 @@ int rtc_get (struct rtc_time *tmp) tmp->tm_yday = 0; tmp->tm_isdst= 0; - DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); return rel; } @@ -137,54 +165,142 @@ int rtc_get (struct rtc_time *tmp) /* * Set the RTC */ -int rtc_set (struct rtc_time *tmp) +static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp) { - DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); if (tmp->tm_year < 1970 || tmp->tm_year > 2069) printf("WARNING: year should be between 1970 and 2069!\n"); - rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); - rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); - rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); - rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100))) + return -EIO; - rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); + if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon))) + return -EIO; - return 0; + if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday))) + return -EIO; + + if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday))) + return -EIO; + + if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour))) + return -EIO; + + if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min))) + return -EIO; + + if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec))) + return -EIO; + + return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); } /* * Reset the RTC */ -void rtc_reset (void) +static int rx8025_rtc_reset(DEV_TYPE *dev) { uchar buf[16]; uchar ctl2; - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) +#ifdef CONFIG_DM_RTC + if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { +#else + if (i2c_read(dev->chip, 0, 0, buf, 16)) { +#endif printf("Error reading from RTC\n"); + return -EIO; + } ctl2 = rtc_read(RTC_CTL2_REG_ADDR); ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET); ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL; - rtc_write (RTC_CTL2_REG_ADDR, ctl2); + + return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2); } /* * Helper functions */ -static void rtc_write (uchar reg, uchar val) +static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val) { uchar buf[2]; buf[0] = reg << 4; buf[1] = val; - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0) + +#ifdef CONFIG_DM_RTC + if (dm_i2c_write(dev, 0, buf, 2)) { +#else + if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) { +#endif printf("Error writing to RTC\n"); + return -EIO; + } + return 0; } + +#ifdef CONFIG_DM_RTC +static int rx8025_probe(struct udevice *dev) +{ + uchar buf[16]; + int ret = 0; + + if (i2c_get_chip_offset_len(dev) != 1) + ret = i2c_set_chip_offset_len(dev, 1); + + if (ret) + return ret; + + return dm_i2c_read(dev, 0, buf, sizeof(buf)); +} + +static const struct rtc_ops rx8025_rtc_ops = { + .get = rx8025_rtc_get, + .set = rx8025_rtc_set, + .reset = rx8025_rtc_reset, +}; + +static const struct udevice_id rx8025_rtc_ids[] = { + { .compatible = "epson,rx8025" }, + { } +}; + +U_BOOT_DRIVER(rx8010sj_rtc) = { + .name = "rx8025_rtc", + .id = UCLASS_RTC, + .probe = rx8025_probe, + .of_match = rx8025_rtc_ids, + .ops = &rx8025_rtc_ops, +}; +#else +int rtc_get(struct rtc_time *tm) +{ + struct ludevice dev = { + .chip = CONFIG_SYS_I2C_RTC_ADDR, + }; + + return rx8025_rtc_get(&dev, tm); +} + +int rtc_set(struct rtc_time *tm) +{ + struct ludevice dev = { + .chip = CONFIG_SYS_I2C_RTC_ADDR, + }; + + return rx8025_rtc_set(&dev, tm); +} + +void rtc_reset(void) +{ + struct ludevice dev = { + .chip = CONFIG_SYS_I2C_RTC_ADDR, + }; + + rx8025_rtc_reset(&dev); +} +#endif diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 30aed2c4c1..90c41ab44d 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -50,10 +50,25 @@ config SYSRESET_MICROBLAZE config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW + select SPL_ARM_PSCI_FW if SPL help Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. +config SYSRESET_SOCFPGA + bool "Enable support for Intel SOCFPGA family" + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) + help + This enables the system reset driver support for Intel SOCFPGA SoCs + (Cyclone 5, Arria 5 and Arria 10). + +config SYSRESET_SOCFPGA_S10 + bool "Enable support for Intel SOCFPGA Stratix 10" + depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 + help + This enables the system reset driver support for Intel SOCFPGA + Stratix SoCs. + config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" depends on TI_SCI_PROTOCOL diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 8e1c845dfe..cf01492295 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o +obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o +obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c new file mode 100644 index 0000000000..d6c26a5b23 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pepperl+Fuchs + * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +struct socfpga_sysreset_data { + struct socfpga_reset_manager *rstmgr_base; +}; + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + struct socfpga_sysreset_data *data = dev_get_priv(dev); + + switch (type) { + case SYSRESET_WARM: + writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &data->rstmgr_base->ctrl); + break; + case SYSRESET_COLD: + writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB), + &data->rstmgr_base->ctrl); + break; + default: + return -EPROTONOSUPPORT; + } + return -EINPROGRESS; +} + +static int socfpga_sysreset_probe(struct udevice *dev) +{ + struct socfpga_sysreset_data *data = dev_get_priv(dev); + + data->rstmgr_base = devfdt_get_addr_ptr(dev); + return 0; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data), + .ops = &socfpga_sysreset, + .probe = socfpga_sysreset_probe, +}; diff --git a/drivers/sysreset/sysreset_socfpga_s10.c b/drivers/sysreset/sysreset_socfpga_s10.c new file mode 100644 index 0000000000..9837aadf64 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga_s10.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pepperl+Fuchs + * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/arch/mailbox_s10.h> + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); + return -EINPROGRESS; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .ops = &socfpga_sysreset, +}; diff --git a/include/ACEX1K.h b/include/ACEX1K.h index 9814bba284..7c5253c66c 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -60,6 +60,16 @@ typedef struct { #define Altera_EP2C35_SIZE 883905 #define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */ +#define ALTERA_EP4CE6_SIZE 368011 /* 2944088 Bits */ +#define ALTERA_EP4CE10_SIZE 368011 /* 2944088 Bits */ +#define ALTERA_EP4CE15_SIZE 510856 /* 4086848 Bits */ +#define ALTERA_EP4CE22_SIZE 718569 /* 5748552 Bits */ +#define ALTERA_EP4CE30_SIZE 1191788 /* 9534304 Bits */ +#define ALTERA_EP4CE40_SIZE 1191788 /* 9534304 Bits */ +#define ALTERA_EP4CE55_SIZE 1861195 /* 14889560 Bits */ +#define ALTERA_EP4CE75_SIZE 2495719 /* 19965752 Bits */ +#define ALTERA_EP4CE115_SIZE 3571462 /* 28571696 Bits */ + /* Descriptor Macros *********************************************************************/ /* ACEX1K devices */ diff --git a/include/_exports.h b/include/_exports.h index c15050e30b..0dee05f077 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -40,8 +40,7 @@ EXPORT_FUNC(simple_strtol, long, simple_strtol, const char *, char **, unsigned int) EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct) -#if defined(CONFIG_CMD_I2C) && \ - (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT)) +#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C) EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int) EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int) #else diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 37f71e5708..d6cf18744f 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -352,9 +352,10 @@ int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc); * gpio_hog_lookup_name() - Look up a named GPIO and return the gpio descr. * * @name: Name to look up - * @return: Returns gpio_desc for gpio + * @desc: Returns GPIO description, on success, else NULL + * @return: Returns 0 if OK, else -ENODEV */ -struct gpio_desc *gpio_hog_lookup_name(const char *name); +int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc); /** * gpio_hog_probe_all() - probe all gpio devices with @@ -523,12 +524,13 @@ int gpio_request_list_by_name_nodev(ofnode node, const char *list_name, * gpio_dev_request_index() - request single GPIO from gpio device * * @dev: GPIO device - * @nodename: Name of node + * @nodename: Name of node for which gpio gets requested, used + * for the gpio label name * @list_name: Name of GPIO list (e.g. "board-id-gpios") * @index: Index number of the GPIO in that list use request (0=first) * @flags: GPIOD_* flags - * @dtflags: GPIO flags read from DT - * @desc: GPIO descriotor filled from this function + * @dtflags: GPIO flags read from DT defined see GPIOD_* + * @desc: returns GPIO descriptor filled from this function * @return: return value from gpio_request_tail() */ int gpio_dev_request_index(struct udevice *dev, const char *nodename, diff --git a/include/bootm.h b/include/bootm.h index f771b733f5..edeeacb0df 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -59,23 +59,6 @@ int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], void arch_preboot_os(void); -/** - * bootm_decomp_image() - decompress the operating system - * - * @comp: Compression algorithm that is used (IH_COMP_...) - * @load: Destination load address in U-Boot memory - * @image_start Image start address (where we are decompressing from) - * @type: OS type (IH_OS_...) - * @load_bug: Place to decompress to - * @image_buf: Address to decompress from - * @image_len: Number of bytes in @image_buf to decompress - * @unc_len: Available space for decompression - * @return 0 if OK, -ve on error (BOOTM_ERR_...) - */ -int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, - void *load_buf, void *image_buf, ulong image_len, - uint unc_len, ulong *load_end); - /* * boards should define this to disable devices when EFI exits from boot * services. diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 2e8481890f..c2c5c1f668 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -14,7 +14,6 @@ #include <configs/ti_omap3_common.h> -#undef CONFIG_DM_I2C_COMPAT #define CONFIG_REVISION_TAG /* Hardware drivers */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 15ac17985f..89deeac4e7 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -225,7 +225,6 @@ */ #define CONFIG_SYS_RTC_BUS_NUM 0x01 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#define CONFIG_RTC_RX8025 /* Pass Ethernet MAC to VxWorks */ #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 2dab17afab..ff536131ba 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -174,6 +174,10 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_NAND_LOAD + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_NAND_SELF_INIT +#endif #endif /* diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index da615e5063..db4a663c53 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -17,14 +17,6 @@ #undef CONFIG_SYS_USE_NOR /* -* Disable DM_* for SPL build and can be re-enabled after adding -* DM support in SPL -*/ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_I2C -#undef CONFIG_DM_I2C_COMPAT -#endif -/* * SoC Configuration */ #define CONFIG_MACH_OMAPL138_LCDK diff --git a/include/configs/pumpkin.h b/include/configs/pumpkin.h new file mode 100644 index 0000000000..b2dda642cc --- /dev/null +++ b/include/configs/pumpkin.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Pumpkin board + * + * Copyright (C) 2019 BayLibre, SAS + * Author: Fabien Parent <fparent@baylibre.com + */ + +#ifndef __PUMPKIN_H +#define __PUMPKIN_H + +#include <linux/sizes.h> + +#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MALLOC_LEN SZ_4M + +#define CONFIG_CPU_ARMV8 +#define COUNTER_FREQUENCY 13000000 + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_COM1 0x11005000 +#define CONFIG_SYS_NS16550_CLK 26000000 + +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Environment settings */ +#include <config_distro_bootcmd.h> + +#define MMCBOOT \ + "mmcdev=0\0" \ + "kernel_partition=2\0" \ + "rootfs_partition=3\0" \ + "mmc_discover_partition=" \ + "part start mmc ${mmcdev} ${kernel_partition} kernel_part_addr;" \ + "part size mmc ${mmcdev} ${kernel_partition} kernel_part_size;\0" \ + "mmcboot=" \ + "mmc dev ${mmcdev};" \ + "run mmc_discover_partition;" \ + "mmc read ${kerneladdr} ${kernel_part_addr} ${kernel_part_size};" \ + "setenv bootargs ${bootargs} root=/dev/mmcblk${mmcdev}p${rootfs_partition} rootwait; " \ + "bootm ${kerneladdr}; \0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kerneladdr=0x4A000000\0" \ + MMCBOOT \ + "bootcmd=run mmcboot;\0" + +#endif diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 20d62439fb..d12696d6b3 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -19,6 +19,8 @@ #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 +#define CONFIG_IRAM_BASE 0x10080000 + #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 #define CONFIG_SYS_LOAD_ADDR 0x60800800 diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 1d41702846..92524b06ad 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -15,8 +15,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_NS16550_MEM32 - #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ #endif @@ -25,6 +23,7 @@ #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" +#define CONFIG_IRAM_BASE 0x10080000 /* spl size 32kb sram - 2kb bootrom */ #define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index cc08699944..9582cdfb64 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -24,6 +24,7 @@ #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) #define CONFIG_ROCKCHIP_CHIP_TAG "RK32" +#define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 5472a90633..da10e29139 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,6 +9,8 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */ + #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 @@ -25,6 +27,8 @@ #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 +#define CONFIG_IRAM_BASE 0xff700000 + /* RAW SD card / eMMC locations. */ #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 2a81c803b6..6ed7525304 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -8,12 +8,14 @@ #include "rockchip-common.h" +#define CONFIG_IRAM_BASE 0xff090000 + +#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 + #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0x00400000 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8a1e3118ae..340413dbba 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -23,7 +23,7 @@ #define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_IRAM_BASE 0xff8c0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00280000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 8df0180284..12ad60d443 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -15,7 +15,7 @@ #define COUNTER_FREQUENCY 24000000 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 -#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_IRAM_BASE 0xff8c0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 6f61f01538..691aa51e98 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -8,6 +8,8 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" +#define CONFIG_IRAM_BASE 0x10080000 + #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h index b36d7e56fb..fc1db2442e 100644 --- a/include/configs/socfpga_dbm_soc1.h +++ b/include/configs/socfpga_dbm_soc1.h @@ -87,7 +87,8 @@ "echo Running bootscript... ; " \ "source ${kernel_addr_r} ; " \ "fi ; " \ - "fi\0" + "fi\0" \ + "socfpga_legacy_reset_compat=1\0" /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 8d2971c6e2..90ad8172e2 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -113,7 +113,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "scriptaddr=0x02100000\0" \ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ - "then source ${scriptaddr}; fi\0" + "then source ${scriptaddr}; fi\0" \ + "socfpga_legacy_reset_compat=1\0" /* * Generic Interrupt Controller Definitions diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 29a92b9146..5416c4b170 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -145,6 +145,7 @@ "run ubi_ubi ; " \ "else echo \"Unsupported boot mode: \"${bootmode} ; " \ "fi\0" \ + "socfpga_legacy_reset_compat=1\0" #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3f84fabdb6..7d266d1bcd 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -187,7 +187,6 @@ #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 /* I2C RTC */ -#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ /* I2C W83782G HW-Monitoring IC */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1c3430d849..a4f2af4962 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -225,7 +225,6 @@ */ #define CONFIG_SYS_RTC_BUS_NUM 0x01 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#define CONFIG_RTC_RX8025 /* Pass Ethernet MAC to VxWorks */ #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 684faaee2e..bbcb20737b 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -62,7 +62,6 @@ #if defined(CONFIG_ZYNQMP_USB) #define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_USB_CABLE_CHECK #define CONFIG_THOR_RESET_OFF #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b51914d1e0..62fbf8866f 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -65,7 +65,6 @@ # define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 # define DFU_DEFAULT_POLL_TIMEOUT 300 -# define CONFIG_USB_CABLE_CHECK # define CONFIG_THOR_RESET_OFF # define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h index 05a4b59173..de82d8a15e 100644 --- a/include/dt-bindings/power/r8a77965-sysc.h +++ b/include/dt-bindings/power/r8a77965-sysc.h @@ -21,7 +21,6 @@ #define R8A77965_PD_A3VC 14 #define R8A77965_PD_3DG_A 17 #define R8A77965_PD_3DG_B 18 -#define R8A77965_PD_A3IR 24 #define R8A77965_PD_A2VC1 26 /* Always-on power area */ diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h index bf54779d16..85cc5f23cf 100644 --- a/include/dt-bindings/power/r8a77970-sysc.h +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -16,13 +16,12 @@ #define R8A77970_PD_CA53_CPU0 5 #define R8A77970_PD_CA53_CPU1 6 -#define R8A77970_PD_CR7 13 #define R8A77970_PD_CA53_SCU 21 #define R8A77970_PD_A2IR0 23 -#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A3IR 24 #define R8A77970_PD_A2IR1 27 -#define R8A77970_PD_A2IR2 28 -#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2DP 28 +#define R8A77970_PD_A2CN 29 #define R8A77970_PD_A2SC0 30 #define R8A77970_PD_A2SC1 31 diff --git a/include/exports.h b/include/exports.h index a4b862f191..bf8d53c6b0 100644 --- a/include/exports.h +++ b/include/exports.h @@ -32,8 +32,7 @@ long simple_strtol(const char *cp, char **endp, unsigned int base); int strcmp(const char *cs, const char *ct); unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); -#if defined(CONFIG_CMD_I2C) && \ - (!defined(CONFIG_DM_I2C) || defined(CONFIG_DM_I2C_COMPAT)) +#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); #endif diff --git a/include/fpga.h b/include/fpga.h index 51de5c55f8..ec5144334d 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -15,7 +15,7 @@ /* fpga_xxxx function return value definitions */ #define FPGA_SUCCESS 0 -#define FPGA_FAIL -1 +#define FPGA_FAIL 1 /* device numbers must be non-negative */ #define FPGA_INVALID_DEVICE -1 diff --git a/include/i2c.h b/include/i2c.h index a5c760c711..33570f5404 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -271,86 +271,6 @@ int i2c_get_chip_offset_len(struct udevice *dev); */ int i2c_deblock(struct udevice *bus); -#ifdef CONFIG_DM_I2C_COMPAT -/** - * i2c_probe() - Compatibility function for driver model - * - * Calls dm_i2c_probe() on the current bus - */ -int i2c_probe(uint8_t chip_addr); - -/** - * i2c_read() - Compatibility function for driver model - * - * Calls dm_i2c_read() with the device corresponding to @chip_addr, and offset - * set to @addr. @alen must match the current setting for the device. - */ -int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, - int len); - -/** - * i2c_write() - Compatibility function for driver model - * - * Calls dm_i2c_write() with the device corresponding to @chip_addr, and offset - * set to @addr. @alen must match the current setting for the device. - */ -int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, - int len); - -/** - * i2c_get_bus_num_fdt() - Compatibility function for driver model - * - * @return the bus number associated with the given device tree node - */ -int i2c_get_bus_num_fdt(int node); - -/** - * i2c_get_bus_num() - Compatibility function for driver model - * - * @return the 'current' bus number - */ -unsigned int i2c_get_bus_num(void); - -/** - * i2c_set_bus_num() - Compatibility function for driver model - * - * Sets the 'current' bus - */ -int i2c_set_bus_num(unsigned int bus); - -static inline void I2C_SET_BUS(unsigned int bus) -{ - i2c_set_bus_num(bus); -} - -static inline unsigned int I2C_GET_BUS(void) -{ - return i2c_get_bus_num(); -} - -/** - * i2c_init() - Compatibility function for driver model - * - * This function does nothing. - */ -void i2c_init(int speed, int slaveaddr); - -/** - * board_i2c_init() - Compatibility function for driver model - * - * @param blob Device tree blbo - * @return the number of I2C bus - */ -void board_i2c_init(const void *blob); - -/* - * Compatibility functions for driver model. - */ -uint8_t i2c_reg_read(uint8_t addr, uint8_t reg); -void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val); - -#endif - /** * struct dm_i2c_ops - driver operations for I2C uclass * diff --git a/include/image.h b/include/image.h index 5f82194951..27d7cb9d1e 100644 --- a/include/image.h +++ b/include/image.h @@ -850,6 +850,23 @@ static inline int image_check_target_arch(const image_header_t *hdr) #endif /* USE_HOSTCC */ /** + * image_decomp() - decompress an image + * + * @comp: Compression algorithm that is used (IH_COMP_...) + * @load: Destination load address in U-Boot memory + * @image_start Image start address (where we are decompressing from) + * @type: OS type (IH_OS_...) + * @load_bug: Place to decompress to + * @image_buf: Address to decompress from + * @image_len: Number of bytes in @image_buf to decompress + * @unc_len: Available space for decompression + * @return 0 if OK, -ve on error (BOOTM_ERR_...) + */ +int image_decomp(int comp, ulong load, ulong image_start, int type, + void *load_buf, void *image_buf, ulong image_len, + uint unc_len, ulong *load_end); + +/** * Set up properties in the FDT * * This sets up properties in the FDT that is to be passed to linux. diff --git a/include/virtex2.h b/include/virtex2.h index a48113060e..7e8d93f24d 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,7 +11,7 @@ #include <xilinx.h> /* - * Slave SelectMap Implementation function table. + * Slave SelectMap or Serial Implementation function table. */ typedef struct { xilinx_pre_fn pre; @@ -24,18 +24,11 @@ typedef struct { xilinx_wr_fn wr; xilinx_rdata_fn rdata; xilinx_wdata_fn wdata; + xilinx_bwr_fn wbulkdata; xilinx_busy_fn busy; xilinx_abort_fn abort; xilinx_post_fn post; -} xilinx_virtex2_slave_selectmap_fns; - -/* Slave Serial Implementation function table */ -typedef struct { - xilinx_pgm_fn pgm; - xilinx_clk_fn clk; - xilinx_rdata_fn rdata; - xilinx_wdata_fn wdata; -} xilinx_virtex2_slave_serial_fns; +} xilinx_virtex2_slave_fns; #if defined(CONFIG_FPGA_VIRTEX2) extern struct xilinx_fpga_op virtex2_op; diff --git a/lib/uuid.c b/lib/uuid.c index 7d7a2749b6..ca8be2cdca 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -240,25 +240,25 @@ void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format) #if defined(CONFIG_RANDOM_UUID) || defined(CONFIG_CMD_UUID) void gen_rand_uuid(unsigned char *uuid_bin) { - struct uuid uuid; - unsigned int *ptr = (unsigned int *)&uuid; + u32 ptr[4]; + struct uuid *uuid = (struct uuid *)ptr; int i; srand(get_ticks() + rand()); /* Set all fields randomly */ - for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++) - *(ptr + i) = cpu_to_be32(rand()); + for (i = 0; i < 4; i++) + ptr[i] = rand(); - clrsetbits_be16(&uuid.time_hi_and_version, + clrsetbits_be16(&uuid->time_hi_and_version, UUID_VERSION_MASK, UUID_VERSION << UUID_VERSION_SHIFT); - clrsetbits_8(&uuid.clock_seq_hi_and_reserved, + clrsetbits_8(&uuid->clock_seq_hi_and_reserved, UUID_VARIANT_MASK, UUID_VARIANT << UUID_VARIANT_SHIFT); - memcpy(uuid_bin, &uuid, sizeof(struct uuid)); + memcpy(uuid_bin, uuid, 16); } /* diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 495988cdcf..89119aea22 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1552,7 +1552,6 @@ CONFIG_RTC_MCP79411 CONFIG_RTC_MXS CONFIG_RTC_PCF8563 CONFIG_RTC_PT7C4338 -CONFIG_RTC_RX8025 CONFIG_RUN_FROM_DDR0 CONFIG_RUN_FROM_DDR1 CONFIG_RUN_FROM_IRAM_ONLY @@ -4294,7 +4293,6 @@ CONFIG_USB_ATMEL_CLK_SEL_PLLB CONFIG_USB_ATMEL_CLK_SEL_UPLL CONFIG_USB_BIN_FIXUP CONFIG_USB_BOOTING -CONFIG_USB_CABLE_CHECK CONFIG_USB_DEVICE CONFIG_USB_DEV_BASE CONFIG_USB_DEV_PULLUP_GPIO diff --git a/scripts/dtc/libfdt/fdt_sw.c b/scripts/dtc/libfdt/fdt_sw.c index 6d33cc29d0..d8ef748a72 100644 --- a/scripts/dtc/libfdt/fdt_sw.c +++ b/scripts/dtc/libfdt/fdt_sw.c @@ -114,7 +114,7 @@ int fdt_resize(void *fdt, void *buf, int bufsize) FDT_SW_CHECK_HEADER(fdt); - headsize = fdt_off_dt_struct(fdt); + headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); tailsize = fdt_size_dt_strings(fdt); if ((headsize + tailsize) > bufsize) diff --git a/test/compression.c b/test/compression.c index 7bc0f73e09..dc5e94684f 100644 --- a/test/compression.c +++ b/test/compression.c @@ -471,15 +471,15 @@ static int run_bootm_test(struct unit_test_state *uts, int comp_type, unc_len = strlen(plain); compress(uts, (void *)plain, unc_len, compress_buff, compress_size, &compress_size); - err = bootm_decomp_image(comp_type, load_addr, image_start, - IH_TYPE_KERNEL, map_sysmem(load_addr, 0), - compress_buff, compress_size, unc_len, - &load_end); + err = image_decomp(comp_type, load_addr, image_start, + IH_TYPE_KERNEL, map_sysmem(load_addr, 0), + compress_buff, compress_size, unc_len, + &load_end); ut_assertok(err); - err = bootm_decomp_image(comp_type, load_addr, image_start, - IH_TYPE_KERNEL, map_sysmem(load_addr, 0), - compress_buff, compress_size, unc_len - 1, - &load_end); + err = image_decomp(comp_type, load_addr, image_start, + IH_TYPE_KERNEL, map_sysmem(load_addr, 0), + compress_buff, compress_size, unc_len - 1, + &load_end); ut_assert(err); /* We can't detect corruption when not decompressing */ @@ -487,10 +487,10 @@ static int run_bootm_test(struct unit_test_state *uts, int comp_type, return 0; memset(compress_buff + compress_size / 2, '\x49', compress_size / 2); - err = bootm_decomp_image(comp_type, load_addr, image_start, - IH_TYPE_KERNEL, map_sysmem(load_addr, 0), - compress_buff, compress_size, 0x10000, - &load_end); + err = image_decomp(comp_type, load_addr, image_start, + IH_TYPE_KERNEL, map_sysmem(load_addr, 0), + compress_buff, compress_size, 0x10000, + &load_end); ut_assert(err); return 0; diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py index 49d6fea571..8009d2907b 100755 --- a/test/py/tests/test_fit.py +++ b/test/py/tests/test_fit.py @@ -24,7 +24,7 @@ base_its = ''' type = "kernel"; arch = "sandbox"; os = "linux"; - compression = "none"; + compression = "%(compression)s"; load = <0x40000>; entry = <0x8>; }; @@ -39,11 +39,11 @@ base_its = ''' }; fdt@1 { description = "snow"; - data = /incbin/("u-boot.dtb"); + data = /incbin/("%(fdt)s"); type = "flat_dt"; arch = "sandbox"; %(fdt_load)s - compression = "none"; + compression = "%(compression)s"; signature@1 { algo = "sha1,rsa2048"; key-name-hint = "dev"; @@ -56,7 +56,7 @@ base_its = ''' arch = "sandbox"; os = "linux"; %(ramdisk_load)s - compression = "none"; + compression = "%(compression)s"; }; ramdisk@2 { description = "snow"; @@ -221,6 +221,10 @@ def test_fit(u_boot_console): print(data, file=fd) return fname + def make_compressed(filename): + util.run_and_log(cons, ['gzip', '-f', '-k', filename]) + return filename + '.gz' + def find_matching(text, match): """Find a match in a line of text, and return the unmatched line portion @@ -312,6 +316,7 @@ def test_fit(u_boot_console): loadables1 = make_kernel('test-loadables1.bin', 'lenrek') loadables2 = make_ramdisk('test-loadables2.bin', 'ksidmar') kernel_out = make_fname('kernel-out.bin') + fdt = make_fname('u-boot.dtb') fdt_out = make_fname('fdt-out.dtb') ramdisk_out = make_fname('ramdisk-out.bin') loadables1_out = make_fname('loadables1-out.bin') @@ -326,6 +331,7 @@ def test_fit(u_boot_console): 'kernel_addr' : 0x40000, 'kernel_size' : filesize(kernel), + 'fdt' : fdt, 'fdt_out' : fdt_out, 'fdt_addr' : 0x80000, 'fdt_size' : filesize(control_dtb), @@ -351,6 +357,7 @@ def test_fit(u_boot_console): 'loadables2_load' : '', 'loadables_config' : '', + 'compression' : 'none', } # Make a basic FIT and a script to load it @@ -417,6 +424,20 @@ def test_fit(u_boot_console): check_equal(loadables2, loadables2_out, 'Loadables2 (ramdisk) not loaded') + # Kernel, FDT and Ramdisk all compressed + with cons.log.section('(Kernel + FDT + Ramdisk) compressed'): + params['compression'] = 'gzip' + params['kernel'] = make_compressed(kernel) + params['fdt'] = make_compressed(fdt) + params['ramdisk'] = make_compressed(ramdisk) + fit = make_fit(mkimage, params) + cons.restart_uboot() + output = cons.run_command_list(cmd.splitlines()) + check_equal(kernel, kernel_out, 'Kernel not loaded') + check_equal(control_dtb, fdt_out, 'FDT not loaded') + check_equal(ramdisk, ramdisk_out, 'Ramdisk not loaded') + + cons = u_boot_console try: # We need to use our own device tree file. Remember to restore it diff --git a/tools/binman/README b/tools/binman/README index 756c6a0010..b4f6392ab7 100644 --- a/tools/binman/README +++ b/tools/binman/README @@ -481,6 +481,29 @@ name-prefix: distinguish binaries with otherwise identical names. +Image Properties +---------------- + +Image nodes act like sections but also have a few extra properties: + +filename: + Output filename for the image. This defaults to image.bin (or in the + case of multiple images <nodename>.bin where <nodename> is the name of + the image node. + +allow-repack: + Create an image that can be repacked. With this option it is possible + to change anything in the image after it is created, including updating + the position and size of image components. By default this is not + permitted since it is not possibly to know whether this might violate a + constraint in the image description. For example, if a section has to + increase in size to hold a larger binary, that might cause the section + to fall out of its allow region (e.g. read-only portion of flash). + + Adding this property causes the original offset and size values in the + image description to be stored in the FDT and fdtmap. + + Entry Documentation ------------------- @@ -557,6 +580,35 @@ or just a selection: $ binman extract -i image.bin "*u-boot*" -O outdir +Replacing files in an image +--------------------------- + +You can replace files in an existing firmware image created by binman, provided +that there is an 'fdtmap' entry in the image. For example: + + $ binman replace -i image.bin section/cbfs/u-boot + +which will write the contents of the file 'u-boot' from the current directory +to the that entry, compressing if necessary. If the entry size changes, you must +add the 'allow-repack' property to the original image before generating it (see +above), otherwise you will get an error. + +You can also use a particular file, in this case u-boot.bin: + + $ binman replace -i image.bin section/cbfs/u-boot -f u-boot.bin + +It is possible to replace all files from a source directory which uses the same +hierarchy as the entries: + + $ binman replace -i image.bin -I indir + +Files that are missing will generate a warning. + +You can also replace just a selection of entries: + + $ binman replace -i image.bin "*u-boot*" -I indir + + Logging ------- @@ -644,22 +696,35 @@ large enough to hold all the entries. 7. CheckEntries() - checks that the entries do not overlap, nor extend outside the image. -8. SetCalculatedProperties() - update any calculated properties in the device +8. SetImagePos() - sets the image position of every entry. This is the absolute +position 'image-pos', as opposed to 'offset' which is relative to the containing +section. This must be done after all offsets are known, which is why it is quite +late in the ordering. + +9. SetCalculatedProperties() - update any calculated properties in the device tree. This sets the correct 'offset' and 'size' vaues, for example. -9. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry. +10. ProcessEntryContents() - this calls Entry.ProcessContents() on each entry. The default implementatoin does nothing. This can be overriden to adjust the contents of an entry in some way. For example, it would be possible to create an entry containing a hash of the contents of some other entries. At this stage the offset and size of entries should not be adjusted unless absolutely necessary, since it requires a repack (going back to PackEntries()). -10. WriteSymbols() - write the value of symbols into the U-Boot SPL binary. +11. ResetForPack() - if the ProcessEntryContents() step failed, in that an entry +has changed its size, then there is no alternative but to go back to step 5 and +try again, repacking the entries with the updated size. ResetForPack() removes +the fixed offset/size values added by binman, so that the packing can start from +scratch. + +12. WriteSymbols() - write the value of symbols into the U-Boot SPL binary. See 'Access to binman entry offsets at run time' below for a description of what happens in this stage. -11. BuildImage() - builds the image and writes it to a file. This is the final -step. +13. BuildImage() - builds the image and writes it to a file + +14. WriteMap() - writes a text file containing a map of the image. This is the +final step. Automatic .dtsi inclusion @@ -909,10 +974,10 @@ Some ideas: - Allow easy building of images by specifying just the board name - Support building an image for a board (-b) more completely, with a configurable build directory -- Support updating binaries in an image (with no size change / repacking) -- Support updating binaries in an image (with repacking) - Support adding FITs to an image - Support for ARM Trusted Firmware (ATF) +- Detect invalid properties in nodes +- Sort the fdtmap by offset -- Simon Glass <sjg@chromium.org> diff --git a/tools/binman/README.entries b/tools/binman/README.entries index 7ce88ee5da..0f0e367d02 100644 --- a/tools/binman/README.entries +++ b/tools/binman/README.entries @@ -230,7 +230,9 @@ Properties / Entry arguments: None An FDT map is just a header followed by an FDT containing a list of all the -entries in the image. +entries in the image. The root node corresponds to the image node in the +original FDT, and an image-name property indicates the image name in that +original tree. The header is the string _FDTMAP_ followed by 8 unused bytes. @@ -244,6 +246,7 @@ FDT with the position of each entry. Example output for a simple image with U-Boot and an FDT map: / { + image-name = "binman"; size = <0x00000112>; image-pos = <0x00000000>; offset = <0x00000000>; @@ -259,6 +262,9 @@ Example output for a simple image with U-Boot and an FDT map: }; }; +If allow-repack is used then 'orig-offset' and 'orig-size' properties are +added as necessary. See the binman README. + Entry: files: Entry containing a set of files @@ -308,7 +314,8 @@ see www.flashrom.org/Flashrom for more information. When used, this entry will be populated with an FMAP which reflects the entries in the current image. Note that any hierarchy is squashed, since -FMAP does not support this. +FMAP does not support this. Also, CBFS entries appear as a single entry - +the sub-entries are ignored. diff --git a/tools/binman/cbfs_util.py b/tools/binman/cbfs_util.py index 45e16da0aa..99d77878c9 100644 --- a/tools/binman/cbfs_util.py +++ b/tools/binman/cbfs_util.py @@ -208,6 +208,7 @@ class CbfsFile(object): cbfs_offset: Offset of file data in bytes from start of CBFS, or None to place this file anyway data: Contents of file, uncompressed + orig_data: Original data added to the file, possibly compressed data_len: Length of (possibly compressed) data in bytes ftype: File type (TYPE_...) compression: Compression type (COMPRESS_...) @@ -226,6 +227,7 @@ class CbfsFile(object): self.offset = None self.cbfs_offset = cbfs_offset self.data = data + self.orig_data = data self.ftype = ftype self.compress = compress self.memlen = None @@ -240,9 +242,9 @@ class CbfsFile(object): """Handle decompressing data if necessary""" indata = self.data if self.compress == COMPRESS_LZ4: - data = tools.Decompress(indata, 'lz4') + data = tools.Decompress(indata, 'lz4', with_header=False) elif self.compress == COMPRESS_LZMA: - data = tools.Decompress(indata, 'lzma') + data = tools.Decompress(indata, 'lzma', with_header=False) else: data = indata self.memlen = len(data) @@ -361,9 +363,9 @@ class CbfsFile(object): elif self.ftype == TYPE_RAW: orig_data = data if self.compress == COMPRESS_LZ4: - data = tools.Compress(orig_data, 'lz4') + data = tools.Compress(orig_data, 'lz4', with_header=False) elif self.compress == COMPRESS_LZMA: - data = tools.Compress(orig_data, 'lzma') + data = tools.Compress(orig_data, 'lzma', with_header=False) self.memlen = len(orig_data) self.data_len = len(data) attr = struct.pack(ATTR_COMPRESSION_FORMAT, @@ -715,7 +717,7 @@ class CbfsReader(object): file_pos = fd.tell() data = fd.read(FILE_HEADER_LEN) if len(data) < FILE_HEADER_LEN: - print('File header at %x ran out of data' % file_pos) + print('File header at %#x ran out of data' % file_pos) return False magic, size, ftype, attr, offset = struct.unpack(FILE_HEADER_FORMAT, data) @@ -724,7 +726,7 @@ class CbfsReader(object): pos = fd.tell() name = self._read_string(fd) if name is None: - print('String at %x ran out of data' % pos) + print('String at %#x ran out of data' % pos) return False if DEBUG: diff --git a/tools/binman/cbfs_util_test.py b/tools/binman/cbfs_util_test.py index 0fe4aa494e..772c794ece 100755 --- a/tools/binman/cbfs_util_test.py +++ b/tools/binman/cbfs_util_test.py @@ -372,7 +372,7 @@ class TestCbfs(unittest.TestCase): with io.BytesIO(newdata) as fd: fd.seek(pos) self.assertEqual(False, cbr._read_next_file(fd)) - self.assertIn('File header at 0 ran out of data', stdout.getvalue()) + self.assertIn('File header at 0x0 ran out of data', stdout.getvalue()) def test_cbfs_bad_file_string(self): """Check handling of an incomplete filename string""" @@ -394,7 +394,7 @@ class TestCbfs(unittest.TestCase): with io.BytesIO(newdata) as fd: fd.seek(pos) self.assertEqual(False, cbr._read_next_file(fd)) - self.assertIn('String at %x ran out of data' % + self.assertIn('String at %#x ran out of data' % cbfs_util.FILE_HEADER_LEN, stdout.getvalue()) def test_cbfs_debug(self): diff --git a/tools/binman/cmdline.py b/tools/binman/cmdline.py index a43aec649e..1e38593579 100644 --- a/tools/binman/cmdline.py +++ b/tools/binman/cmdline.py @@ -84,6 +84,23 @@ controlled by a description in the board device tree.''' extract_parser.add_argument('-U', '--uncompressed', action='store_true', help='Output raw uncompressed data for compressed entries') + replace_parser = subparsers.add_parser('replace', + help='Replace entries in an image') + replace_parser.add_argument('-C', '--compressed', action='store_true', + help='Input data is already compressed if needed for the entry') + replace_parser.add_argument('-i', '--image', type=str, required=True, + help='Image filename to extract') + replace_parser.add_argument('-f', '--filename', type=str, + help='Input filename to read from') + replace_parser.add_argument('-F', '--fix-size', action='store_true', + help="Don't allow entries to be resized") + replace_parser.add_argument('-I', '--indir', type=str, default='', + help='Path to directory to use for input files') + replace_parser.add_argument('-m', '--map', action='store_true', + default=False, help='Output a map file for the updated image') + replace_parser.add_argument('paths', type=str, nargs='*', + help='Paths within file to extract (wildcard)') + test_parser = subparsers.add_parser('test', help='Run tests') test_parser.add_argument('-P', '--processes', type=int, help='set number of processes to use for running tests') diff --git a/tools/binman/control.py b/tools/binman/control.py index dc898be617..9e7587864c 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -128,7 +128,7 @@ def ExtractEntries(image_fname, output_fname, outdir, entry_paths, otherwise outdir: Output directory to use (for any number of files), else None entry_paths: List of entry paths to extract - decomp: True to compress the entry data + decomp: True to decompress the entry data Returns: List of EntryInfo records that were written @@ -138,9 +138,9 @@ def ExtractEntries(image_fname, output_fname, outdir, entry_paths, # Output an entry to a single file, as a special case if output_fname: if not entry_paths: - raise ValueError('Must specify an entry path to write with -o') + raise ValueError('Must specify an entry path to write with -f') if len(entry_paths) != 1: - raise ValueError('Must specify exactly one entry path to write with -o') + raise ValueError('Must specify exactly one entry path to write with -f') entry = image.FindEntryPath(entry_paths[0]) data = entry.ReadData(decomp) tools.WriteFile(output_fname, data) @@ -169,6 +169,287 @@ def ExtractEntries(image_fname, output_fname, outdir, entry_paths, return einfos +def BeforeReplace(image, allow_resize): + """Handle getting an image ready for replacing entries in it + + Args: + image: Image to prepare + """ + state.PrepareFromLoadedData(image) + image.LoadData() + + # If repacking, drop the old offset/size values except for the original + # ones, so we are only left with the constraints. + if allow_resize: + image.ResetForPack() + + +def ReplaceOneEntry(image, entry, data, do_compress, allow_resize): + """Handle replacing a single entry an an image + + Args: + image: Image to update + entry: Entry to write + data: Data to replace with + do_compress: True to compress the data if needed, False if data is + already compressed so should be used as is + allow_resize: True to allow entries to change size (this does a re-pack + of the entries), False to raise an exception + """ + if not entry.WriteData(data, do_compress): + if not image.allow_repack: + entry.Raise('Entry data size does not match, but allow-repack is not present for this image') + if not allow_resize: + entry.Raise('Entry data size does not match, but resize is disabled') + + +def AfterReplace(image, allow_resize, write_map): + """Handle write out an image after replacing entries in it + + Args: + image: Image to write + allow_resize: True to allow entries to change size (this does a re-pack + of the entries), False to raise an exception + write_map: True to write a map file + """ + tout.Info('Processing image') + ProcessImage(image, update_fdt=True, write_map=write_map, + get_contents=False, allow_resize=allow_resize) + + +def WriteEntryToImage(image, entry, data, do_compress=True, allow_resize=True, + write_map=False): + BeforeReplace(image, allow_resize) + tout.Info('Writing data to %s' % entry.GetPath()) + ReplaceOneEntry(image, entry, data, do_compress, allow_resize) + AfterReplace(image, allow_resize=allow_resize, write_map=write_map) + + +def WriteEntry(image_fname, entry_path, data, do_compress=True, + allow_resize=True, write_map=False): + """Replace an entry in an image + + This replaces the data in a particular entry in an image. This size of the + new data must match the size of the old data unless allow_resize is True. + + Args: + image_fname: Image filename to process + entry_path: Path to entry to extract + data: Data to replace with + do_compress: True to compress the data if needed, False if data is + already compressed so should be used as is + allow_resize: True to allow entries to change size (this does a re-pack + of the entries), False to raise an exception + write_map: True to write a map file + + Returns: + Image object that was updated + """ + tout.Info("Write entry '%s', file '%s'" % (entry_path, image_fname)) + image = Image.FromFile(image_fname) + entry = image.FindEntryPath(entry_path) + WriteEntryToImage(image, entry, data, do_compress=do_compress, + allow_resize=allow_resize, write_map=write_map) + + return image + + +def ReplaceEntries(image_fname, input_fname, indir, entry_paths, + do_compress=True, allow_resize=True, write_map=False): + """Replace the data from one or more entries from input files + + Args: + image_fname: Image filename to process + input_fname: Single input ilename to use if replacing one file, None + otherwise + indir: Input directory to use (for any number of files), else None + entry_paths: List of entry paths to extract + do_compress: True if the input data is uncompressed and may need to be + compressed if the entry requires it, False if the data is already + compressed. + write_map: True to write a map file + + Returns: + List of EntryInfo records that were written + """ + image = Image.FromFile(image_fname) + + # Replace an entry from a single file, as a special case + if input_fname: + if not entry_paths: + raise ValueError('Must specify an entry path to read with -f') + if len(entry_paths) != 1: + raise ValueError('Must specify exactly one entry path to write with -f') + entry = image.FindEntryPath(entry_paths[0]) + data = tools.ReadFile(input_fname) + tout.Notice("Read %#x bytes from file '%s'" % (len(data), input_fname)) + WriteEntryToImage(image, entry, data, do_compress=do_compress, + allow_resize=allow_resize, write_map=write_map) + return + + # Otherwise we will input from a path given by the entry path of each entry. + # This means that files must appear in subdirectories if they are part of + # a sub-section. + einfos = image.GetListEntries(entry_paths)[0] + tout.Notice("Replacing %d matching entries in image '%s'" % + (len(einfos), image_fname)) + + BeforeReplace(image, allow_resize) + + for einfo in einfos: + entry = einfo.entry + if entry.GetEntries(): + tout.Info("Skipping section entry '%s'" % entry.GetPath()) + continue + + path = entry.GetPath()[1:] + fname = os.path.join(indir, path) + + if os.path.exists(fname): + tout.Notice("Write entry '%s' from file '%s'" % + (entry.GetPath(), fname)) + data = tools.ReadFile(fname) + ReplaceOneEntry(image, entry, data, do_compress, allow_resize) + else: + tout.Warning("Skipping entry '%s' from missing file '%s'" % + (entry.GetPath(), fname)) + + AfterReplace(image, allow_resize=allow_resize, write_map=write_map) + return image + + +def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt): + """Prepare the images to be processed and select the device tree + + This function: + - reads in the device tree + - finds and scans the binman node to create all entries + - selects which images to build + - Updates the device tress with placeholder properties for offset, + image-pos, etc. + + Args: + dtb_fname: Filename of the device tree file to use (.dts or .dtb) + selected_images: List of images to output, or None for all + update_fdt: True to update the FDT wth entry offsets, etc. + """ + # Import these here in case libfdt.py is not available, in which case + # the above help option still works. + import fdt + import fdt_util + global images + + # Get the device tree ready by compiling it and copying the compiled + # output into a file in our output directly. Then scan it for use + # in binman. + dtb_fname = fdt_util.EnsureCompiled(dtb_fname) + fname = tools.GetOutputFilename('u-boot.dtb.out') + tools.WriteFile(fname, tools.ReadFile(dtb_fname)) + dtb = fdt.FdtScan(fname) + + node = _FindBinmanNode(dtb) + if not node: + raise ValueError("Device tree '%s' does not have a 'binman' " + "node" % dtb_fname) + + images = _ReadImageDesc(node) + + if select_images: + skip = [] + new_images = OrderedDict() + for name, image in images.items(): + if name in select_images: + new_images[name] = image + else: + skip.append(name) + images = new_images + tout.Notice('Skipping images: %s' % ', '.join(skip)) + + state.Prepare(images, dtb) + + # Prepare the device tree by making sure that any missing + # properties are added (e.g. 'pos' and 'size'). The values of these + # may not be correct yet, but we add placeholders so that the + # size of the device tree is correct. Later, in + # SetCalculatedProperties() we will insert the correct values + # without changing the device-tree size, thus ensuring that our + # entry offsets remain the same. + for image in images.values(): + image.ExpandEntries() + if update_fdt: + image.AddMissingProperties() + image.ProcessFdt(dtb) + + for dtb_item in state.GetAllFdts(): + dtb_item.Sync(auto_resize=True) + dtb_item.Pack() + dtb_item.Flush() + return images + + +def ProcessImage(image, update_fdt, write_map, get_contents=True, + allow_resize=True): + """Perform all steps for this image, including checking and # writing it. + + This means that errors found with a later image will be reported after + earlier images are already completed and written, but that does not seem + important. + + Args: + image: Image to process + update_fdt: True to update the FDT wth entry offsets, etc. + write_map: True to write a map file + get_contents: True to get the image contents from files, etc., False if + the contents is already present + allow_resize: True to allow entries to change size (this does a re-pack + of the entries), False to raise an exception + """ + if get_contents: + image.GetEntryContents() + image.GetEntryOffsets() + + # We need to pack the entries to figure out where everything + # should be placed. This sets the offset/size of each entry. + # However, after packing we call ProcessEntryContents() which + # may result in an entry changing size. In that case we need to + # do another pass. Since the device tree often contains the + # final offset/size information we try to make space for this in + # AddMissingProperties() above. However, if the device is + # compressed we cannot know this compressed size in advance, + # since changing an offset from 0x100 to 0x104 (for example) can + # alter the compressed size of the device tree. So we need a + # third pass for this. + passes = 5 + for pack_pass in range(passes): + try: + image.PackEntries() + image.CheckSize() + image.CheckEntries() + except Exception as e: + if write_map: + fname = image.WriteMap() + print("Wrote map file '%s' to show errors" % fname) + raise + image.SetImagePos() + if update_fdt: + image.SetCalculatedProperties() + for dtb_item in state.GetAllFdts(): + dtb_item.Sync() + dtb_item.Flush() + sizes_ok = image.ProcessEntryContents() + if sizes_ok: + break + image.ResetForPack() + if not sizes_ok: + image.Raise('Entries changed size after packing (tried %s passes)' % + passes) + + image.WriteSymbols() + image.BuildImage() + if write_map: + image.WriteMap() + + def Binman(args): """The main control code for binman @@ -178,8 +459,6 @@ def Binman(args): Args: args: Command line arguments Namespace object """ - global images - if args.full_help: pager = os.getenv('PAGER') if not pager: @@ -190,7 +469,11 @@ def Binman(args): return 0 if args.cmd == 'ls': - ListEntries(args.image, args.paths) + try: + tools.PrepareOutputDir(None) + ListEntries(args.image, args.paths) + finally: + tools.FinaliseOutputDir() return 0 if args.cmd == 'extract': @@ -202,6 +485,16 @@ def Binman(args): tools.FinaliseOutputDir() return 0 + if args.cmd == 'replace': + try: + tools.PrepareOutputDir(None) + ReplaceEntries(args.image, args.filename, args.indir, args.paths, + do_compress=not args.compressed, + allow_resize=not args.fix_size, write_map=args.map) + finally: + tools.FinaliseOutputDir() + return 0 + # Try to figure out which device tree contains our image description if args.dt: dtb_fname = args.dt @@ -216,11 +509,6 @@ def Binman(args): args.indir.append(board_pathname) try: - # Import these here in case libfdt.py is not available, in which case - # the above help option still works. - import fdt - import fdt_util - tout.Init(args.verbosity) elf.debug = args.debug cbfs_util.VERBOSE = args.verbosity > 2 @@ -231,103 +519,13 @@ def Binman(args): tools.SetToolPaths(args.toolpath) state.SetEntryArgs(args.entry_arg) - # Get the device tree ready by compiling it and copying the compiled - # output into a file in our output directly. Then scan it for use - # in binman. - dtb_fname = fdt_util.EnsureCompiled(dtb_fname) - fname = tools.GetOutputFilename('u-boot.dtb.out') - tools.WriteFile(fname, tools.ReadFile(dtb_fname)) - dtb = fdt.FdtScan(fname) - - node = _FindBinmanNode(dtb) - if not node: - raise ValueError("Device tree '%s' does not have a 'binman' " - "node" % dtb_fname) - - images = _ReadImageDesc(node) - - if args.image: - skip = [] - new_images = OrderedDict() - for name, image in images.items(): - if name in args.image: - new_images[name] = image - else: - skip.append(name) - images = new_images - if skip and args.verbosity >= 2: - print('Skipping images: %s' % ', '.join(skip)) - - state.Prepare(images, dtb) - - # Prepare the device tree by making sure that any missing - # properties are added (e.g. 'pos' and 'size'). The values of these - # may not be correct yet, but we add placeholders so that the - # size of the device tree is correct. Later, in - # SetCalculatedProperties() we will insert the correct values - # without changing the device-tree size, thus ensuring that our - # entry offsets remain the same. - for image in images.values(): - image.ExpandEntries() - if args.update_fdt: - image.AddMissingProperties() - image.ProcessFdt(dtb) - - for dtb_item in state.GetFdts(): - dtb_item.Sync(auto_resize=True) - dtb_item.Pack() - dtb_item.Flush() - + images = PrepareImagesAndDtbs(dtb_fname, args.image, + args.update_fdt) for image in images.values(): - # Perform all steps for this image, including checking and - # writing it. This means that errors found with a later - # image will be reported after earlier images are already - # completed and written, but that does not seem important. - image.GetEntryContents() - image.GetEntryOffsets() - - # We need to pack the entries to figure out where everything - # should be placed. This sets the offset/size of each entry. - # However, after packing we call ProcessEntryContents() which - # may result in an entry changing size. In that case we need to - # do another pass. Since the device tree often contains the - # final offset/size information we try to make space for this in - # AddMissingProperties() above. However, if the device is - # compressed we cannot know this compressed size in advance, - # since changing an offset from 0x100 to 0x104 (for example) can - # alter the compressed size of the device tree. So we need a - # third pass for this. - passes = 3 - for pack_pass in range(passes): - try: - image.PackEntries() - image.CheckSize() - image.CheckEntries() - except Exception as e: - if args.map: - fname = image.WriteMap() - print("Wrote map file '%s' to show errors" % fname) - raise - image.SetImagePos() - if args.update_fdt: - image.SetCalculatedProperties() - for dtb_item in state.GetFdts(): - dtb_item.Sync() - sizes_ok = image.ProcessEntryContents() - if sizes_ok: - break - image.ResetForPack() - if not sizes_ok: - image.Raise('Entries expanded after packing (tried %s passes)' % - passes) - - image.WriteSymbols() - image.BuildImage() - if args.map: - image.WriteMap() + ProcessImage(image, args.update_fdt, args.map) # Write the updated FDTs to our output files - for dtb_item in state.GetFdts(): + for dtb_item in state.GetAllFdts(): tools.WriteFile(dtb_item._fname, dtb_item.GetContents()) finally: diff --git a/tools/binman/elf.py b/tools/binman/elf.py index 8147b3437d..af40024cea 100644 --- a/tools/binman/elf.py +++ b/tools/binman/elf.py @@ -17,6 +17,7 @@ import struct import tempfile import tools +import tout ELF_TOOLS = True try: @@ -25,9 +26,6 @@ try: except: # pragma: no cover ELF_TOOLS = False -# This is enabled from control.py -debug = False - Symbol = namedtuple('Symbol', ['section', 'address', 'size', 'weak']) # Information about an ELF file: @@ -143,9 +141,8 @@ def LookupAndWriteSymbols(elf_fname, entry, section): value = -1 pack_string = pack_string.lower() value_bytes = struct.pack(pack_string, value) - if debug: - print('%s:\n insert %s, offset %x, value %x, length %d' % - (msg, name, offset, value, len(value_bytes))) + tout.Debug('%s:\n insert %s, offset %x, value %x, length %d' % + (msg, name, offset, value, len(value_bytes))) entry.data = (entry.data[:offset] + value_bytes + entry.data[offset + sym.size:]) diff --git a/tools/binman/elf_test.py b/tools/binman/elf_test.py index e2506377f2..416e43baf0 100644 --- a/tools/binman/elf_test.py +++ b/tools/binman/elf_test.py @@ -14,6 +14,7 @@ import command import elf import test_util import tools +import tout binman_dir = os.path.dirname(os.path.realpath(sys.argv[0])) @@ -130,14 +131,16 @@ class TestElf(unittest.TestCase): def testDebug(self): """Check that enabling debug in the elf module produced debug output""" - elf.debug = True - entry = FakeEntry(20) - section = FakeSection() - elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms') - with test_util.capture_sys_output() as (stdout, stderr): - syms = elf.LookupAndWriteSymbols(elf_fname, entry, section) - elf.debug = False - self.assertTrue(len(stdout.getvalue()) > 0) + try: + tout.Init(tout.DEBUG) + entry = FakeEntry(20) + section = FakeSection() + elf_fname = os.path.join(binman_dir, 'test', 'u_boot_binman_syms') + with test_util.capture_sys_output() as (stdout, stderr): + syms = elf.LookupAndWriteSymbols(elf_fname, entry, section) + self.assertTrue(len(stdout.getvalue()) > 0) + finally: + tout.Init(tout.WARNING) def testMakeElf(self): """Test for the MakeElf function""" diff --git a/tools/binman/entry.py b/tools/binman/entry.py index 1c382f3b85..6a2c6e0d92 100644 --- a/tools/binman/entry.py +++ b/tools/binman/entry.py @@ -23,6 +23,7 @@ import sys import fdt_util import state import tools +from tools import ToHex, ToHexSize import tout modules = {} @@ -69,7 +70,7 @@ class Entry(object): orig_offset: Original offset value read from node orig_size: Original size value read from node """ - def __init__(self, section, etype, node, read_node=True, name_prefix=''): + def __init__(self, section, etype, node, name_prefix=''): self.section = section self.etype = etype self._node = node @@ -88,8 +89,6 @@ class Entry(object): self.image_pos = None self._expand_size = False self.compress = 'none' - if read_node: - self.ReadNode() @staticmethod def Lookup(node_path, etype): @@ -154,14 +153,19 @@ class Entry(object): def ReadNode(self): """Read entry information from the node + This must be called as the first thing after the Entry is created. + This reads all the fields we recognise from the node, ready for use. """ if 'pos' in self._node.props: self.Raise("Please use 'offset' instead of 'pos'") self.offset = fdt_util.GetInt(self._node, 'offset') self.size = fdt_util.GetInt(self._node, 'size') - self.orig_offset = self.offset - self.orig_size = self.size + self.orig_offset = fdt_util.GetInt(self._node, 'orig-offset') + self.orig_size = fdt_util.GetInt(self._node, 'orig-size') + if self.GetImage().copy_to_orig: + self.orig_offset = self.offset + self.orig_size = self.size # These should not be set in input files, but are set in an FDT map, # which is also read by this code. @@ -185,19 +189,18 @@ class Entry(object): def GetDefaultFilename(self): return None - def GetFdtSet(self): - """Get the set of device trees used by this entry + def GetFdts(self): + """Get the device trees used by this entry Returns: - Set containing the filename from this entry, if it is a .dtb, else - an empty set + Empty dict, if this entry is not a .dtb, otherwise: + Dict: + key: Filename from this entry (without the path) + value: Tuple: + Fdt object for this dtb, or None if not available + Filename of file containing this dtb """ - fname = self.GetDefaultFilename() - # It would be better to use isinstance(self, Entry_blob_dtb) here but - # we cannot access Entry_blob_dtb - if fname and fname.endswith('.dtb'): - return set([fname]) - return set() + return {} def ExpandEntries(self): pass @@ -207,6 +210,12 @@ class Entry(object): for prop in ['offset', 'size', 'image-pos']: if not prop in self._node.props: state.AddZeroProp(self._node, prop) + if self.GetImage().allow_repack: + if self.orig_offset is not None: + state.AddZeroProp(self._node, 'orig-offset', True) + if self.orig_size is not None: + state.AddZeroProp(self._node, 'orig-size', True) + if self.compress != 'none': state.AddZeroProp(self._node, 'uncomp-size') err = state.CheckAddHashProp(self._node) @@ -219,6 +228,11 @@ class Entry(object): state.SetInt(self._node, 'size', self.size) base = self.section.GetRootSkipAtStart() if self.section else 0 state.SetInt(self._node, 'image-pos', self.image_pos - base) + if self.GetImage().allow_repack: + if self.orig_offset is not None: + state.SetInt(self._node, 'orig-offset', self.orig_offset, True) + if self.orig_size is not None: + state.SetInt(self._node, 'orig-size', self.orig_size, True) if self.uncomp_size is not None: state.SetInt(self._node, 'uncomp-size', self.uncomp_size) state.CheckSetHashValue(self._node, self.GetData) @@ -271,15 +285,26 @@ class Entry(object): """ size_ok = True new_size = len(data) - if state.AllowEntryExpansion(): + if state.AllowEntryExpansion() and new_size > self.contents_size: + # self.data will indicate the new size needed + size_ok = False + elif state.AllowEntryContraction() and new_size < self.contents_size: + size_ok = False + + # If not allowed to change, try to deal with it or give up + if size_ok: if new_size > self.contents_size: - tout.Debug("Entry '%s' size change from %#x to %#x" % ( - self._node.path, self.contents_size, new_size)) - # self.data will indicate the new size needed - size_ok = False - elif new_size != self.contents_size: - self.Raise('Cannot update entry size from %d to %d' % - (self.contents_size, new_size)) + self.Raise('Cannot update entry size from %d to %d' % + (self.contents_size, new_size)) + + # Don't let the data shrink. Pad it if necessary + if size_ok and new_size < self.contents_size: + data += tools.GetBytes(0, self.contents_size - new_size) + + if not size_ok: + tout.Debug("Entry '%s' size change from %s to %s" % ( + self._node.path, ToHex(self.contents_size), + ToHex(new_size))) self.SetContents(data) return size_ok @@ -295,6 +320,9 @@ class Entry(object): def ResetForPack(self): """Reset offset/size fields so that packing can be done again""" + self.Detail('ResetForPack: offset %s->%s, size %s->%s' % + (ToHex(self.offset), ToHex(self.orig_offset), + ToHex(self.size), ToHex(self.orig_size))) self.offset = self.orig_offset self.size = self.orig_size @@ -316,6 +344,9 @@ class Entry(object): Returns: New section offset pointer (after this entry) """ + self.Detail('Packing: offset=%s, size=%s, content_size=%x' % + (ToHex(self.offset), ToHex(self.size), + self.contents_size)) if self.offset is None: if self.offset_unset: self.Raise('No offset set with offset-unset: should another ' @@ -347,6 +378,8 @@ class Entry(object): if self.offset != tools.Align(self.offset, self.align): self.Raise("Offset %#x (%d) does not match align %#x (%d)" % (self.offset, self.offset, self.align, self.align)) + self.Detail(' - packed: offset=%#x, size=%#x, content_size=%#x, next_offset=%x' % + (self.offset, self.size, self.contents_size, new_offset)) return new_offset @@ -354,6 +387,11 @@ class Entry(object): """Convenience function to raise an error referencing a node""" raise ValueError("Node '%s': %s" % (self._node.path, msg)) + def Detail(self, msg): + """Convenience function to log detail referencing a node""" + tag = "Node '%s'" % self._node.path + tout.Detail('%30s: %s' % (tag, msg)) + def GetEntryArgsOrProps(self, props, required=False): """Return the values of a set of properties @@ -390,6 +428,7 @@ class Entry(object): return self._node.path def GetData(self): + self.Detail('GetData: size %s' % ToHexSize(self.data)) return self.data def GetOffsets(self): @@ -675,8 +714,75 @@ features to produce new behaviours. """ # Use True here so that we get an uncompressed section to work from, # although compressed sections are currently not supported - data = self.section.ReadData(True) - tout.Info('%s: Reading data from offset %#x-%#x, size %#x (avail %#x)' % - (self.GetPath(), self.offset, self.offset + self.size, - self.size, len(data))) - return data[self.offset:self.offset + self.size] + data = self.section.ReadChildData(self, decomp) + return data + + def LoadData(self, decomp=True): + data = self.ReadData(decomp) + self.contents_size = len(data) + self.ProcessContentsUpdate(data) + self.Detail('Loaded data size %x' % len(data)) + + def GetImage(self): + """Get the image containing this entry + + Returns: + Image object containing this entry + """ + return self.section.GetImage() + + def WriteData(self, data, decomp=True): + """Write the data to an entry in the image + + This is used when the image has been read in and we want to replace the + data for a particular entry in that image. + + The image must be re-packed and written out afterwards. + + Args: + data: Data to replace it with + decomp: True to compress the data if needed, False if data is + already compressed so should be used as is + + Returns: + True if the data did not result in a resize of this entry, False if + the entry must be resized + """ + self.contents_size = self.size + ok = self.ProcessContentsUpdate(data) + self.Detail('WriteData: size=%x, ok=%s' % (len(data), ok)) + section_ok = self.section.WriteChildData(self) + return ok and section_ok + + def WriteChildData(self, child): + """Handle writing the data in a child entry + + This should be called on the child's parent section after the child's + data has been updated. It + + This base-class implementation does nothing, since the base Entry object + does not have any children. + + Args: + child: Child Entry that was written + + Returns: + True if the section could be updated successfully, False if the + data is such that the section could not updat + """ + return True + + def GetSiblingOrder(self): + """Get the relative order of an entry amoung its siblings + + Returns: + 'start' if this entry is first among siblings, 'end' if last, + otherwise None + """ + entries = list(self.section.GetEntries().values()) + if entries: + if self == entries[0]: + return 'start' + elif self == entries[-1]: + return 'end' + return 'middle' diff --git a/tools/binman/entry_test.py b/tools/binman/entry_test.py index b6ad3edb8d..cc1fb795da 100644 --- a/tools/binman/entry_test.py +++ b/tools/binman/entry_test.py @@ -57,7 +57,7 @@ class TestEntry(unittest.TestCase): def testEntryContents(self): """Test the Entry bass class""" import entry - base_entry = entry.Entry(None, None, None, read_node=False) + base_entry = entry.Entry(None, None, None) self.assertEqual(True, base_entry.ObtainContents()) def testUnknownEntry(self): @@ -73,16 +73,30 @@ class TestEntry(unittest.TestCase): """Test Entry.GetUniqueName""" Node = collections.namedtuple('Node', ['name', 'parent']) base_node = Node('root', None) - base_entry = entry.Entry(None, None, base_node, read_node=False) + base_entry = entry.Entry(None, None, base_node) self.assertEqual('root', base_entry.GetUniqueName()) sub_node = Node('subnode', base_node) - sub_entry = entry.Entry(None, None, sub_node, read_node=False) + sub_entry = entry.Entry(None, None, sub_node) self.assertEqual('root.subnode', sub_entry.GetUniqueName()) def testGetDefaultFilename(self): """Trivial test for this base class function""" - base_entry = entry.Entry(None, None, None, read_node=False) + base_entry = entry.Entry(None, None, None) self.assertIsNone(base_entry.GetDefaultFilename()) + def testBlobFdt(self): + """Test the GetFdtEtype() method of the blob-dtb entries""" + base = entry.Entry.Create(None, self.GetNode(), 'blob-dtb') + self.assertIsNone(base.GetFdtEtype()) + + dtb = entry.Entry.Create(None, self.GetNode(), 'u-boot-dtb') + self.assertEqual('u-boot-dtb', dtb.GetFdtEtype()) + + def testWriteChildData(self): + """Test the WriteChildData() method of the base class""" + base = entry.Entry.Create(None, self.GetNode(), 'blob-dtb') + self.assertTrue(base.WriteChildData(base)) + + if __name__ == "__main__": unittest.main() diff --git a/tools/binman/etype/_testing.py b/tools/binman/etype/_testing.py index ae24fe8105..25a6206bf3 100644 --- a/tools/binman/etype/_testing.py +++ b/tools/binman/etype/_testing.py @@ -31,8 +31,8 @@ class Entry__testing(Entry): return-invalid-entry: Return an invalid entry from GetOffsets() return-unknown-contents: Refuse to provide any contents (to cause a failure) - bad-update-contents: Implement ProcessContents() incorrectly so as to - cause a failure + bad-update-contents: Return a larger size in ProcessContents + bad-shrink-contents: Return a larger size in ProcessContents never-complete-process-fdt: Refund to process the FDT (to cause a failure) require-args: Require that all used args are present (generating an @@ -42,12 +42,17 @@ class Entry__testing(Entry): """ def __init__(self, section, etype, node): Entry.__init__(self, section, etype, node) + + def ReadNode(self): + Entry.ReadNode(self) self.return_invalid_entry = fdt_util.GetBool(self._node, 'return-invalid-entry') self.return_unknown_contents = fdt_util.GetBool(self._node, 'return-unknown-contents') self.bad_update_contents = fdt_util.GetBool(self._node, 'bad-update-contents') + self.bad_shrink_contents = fdt_util.GetBool(self._node, + 'bad-shrink-contents') self.return_contents_once = fdt_util.GetBool(self._node, 'return-contents-once') self.bad_update_contents_twice = fdt_util.GetBool(self._node, @@ -73,7 +78,7 @@ class Entry__testing(Entry): if self.force_bad_datatype: self.GetEntryArgsOrProps([EntryArg('test-bad-datatype-arg', bool)]) self.return_contents = True - self.contents = b'a' + self.contents = b'aa' def ObtainContents(self): if self.return_unknown_contents or not self.return_contents: @@ -90,14 +95,25 @@ class Entry__testing(Entry): return {} def ProcessContents(self): + data = self.contents if self.bad_update_contents: # Request to update the contents with something larger, to cause a # failure. if self.bad_update_contents_twice: - self.contents += b'a' + data = self.data + b'a' else: - self.contents = b'aa' - return self.ProcessContentsUpdate(self.contents) + data = b'aaa' + return self.ProcessContentsUpdate(data) + if self.bad_shrink_contents: + # Request to update the contents with something smaller, to cause a + # failure. + data = b'a' + return self.ProcessContentsUpdate(data) + if self.bad_shrink_contents: + # Request to update the contents with something smaller, to cause a + # failure. + data = b'a' + return self.ProcessContentsUpdate(data) return True def ProcessFdt(self, fdt): diff --git a/tools/binman/etype/blob.py b/tools/binman/etype/blob.py index 00cad33718..d15d0789e5 100644 --- a/tools/binman/etype/blob.py +++ b/tools/binman/etype/blob.py @@ -67,15 +67,3 @@ class Entry_blob(Entry): def GetDefaultFilename(self): return self._filename - - def ReadData(self, decomp=True): - indata = Entry.ReadData(self, decomp) - if decomp: - data = tools.Decompress(indata, self.compress) - if self.uncomp_size: - tout.Info("%s: Decompressing data size %#x with algo '%s' to data size %#x" % - (self.GetPath(), len(indata), self.compress, - len(data))) - else: - data = indata - return data diff --git a/tools/binman/etype/blob_dtb.py b/tools/binman/etype/blob_dtb.py index 88ed55d886..5b559967d7 100644 --- a/tools/binman/etype/blob_dtb.py +++ b/tools/binman/etype/blob_dtb.py @@ -23,11 +23,42 @@ class Entry_blob_dtb(Entry_blob): def ObtainContents(self): """Get the device-tree from the list held by the 'state' module""" self._filename = self.GetDefaultFilename() - self._pathname, _ = state.GetFdtContents(self._filename) + self._pathname, _ = state.GetFdtContents(self.GetFdtEtype()) return Entry_blob.ReadBlobContents(self) def ProcessContents(self): """Re-read the DTB contents so that we get any calculated properties""" - _, indata = state.GetFdtContents(self._filename) + _, indata = state.GetFdtContents(self.GetFdtEtype()) data = self.CompressData(indata) return self.ProcessContentsUpdate(data) + + def GetFdtEtype(self): + """Get the entry type of this device tree + + This can be 'u-boot-dtb', 'u-boot-spl-dtb' or 'u-boot-tpl-dtb' + Returns: + Entry type if any, e.g. 'u-boot-dtb' + """ + return None + + def GetFdts(self): + """Get the device trees used by this entry + + Returns: + Dict: + key: Filename from this entry (without the path) + value: Tuple: + Fdt object for this dtb, or None if not available + Filename of file containing this dtb + """ + fname = self.GetDefaultFilename() + return {self.GetFdtEtype(): [self, fname]} + + def WriteData(self, data, decomp=True): + ok = Entry_blob.WriteData(self, data, decomp) + + # Update the state module, since it has the authoritative record of the + # device trees used. If we don't do this, then state.GetFdtContents() + # will still return the old contents + state.UpdateFdtContents(self.GetFdtEtype(), data) + return ok diff --git a/tools/binman/etype/cbfs.py b/tools/binman/etype/cbfs.py index edf2189fd2..28a9c81a8a 100644 --- a/tools/binman/etype/cbfs.py +++ b/tools/binman/etype/cbfs.py @@ -168,8 +168,9 @@ class Entry_cbfs(Entry): self._cbfs_arg = fdt_util.GetString(node, 'cbfs-arch', 'x86') self._cbfs_entries = OrderedDict() self._ReadSubnodes() + self.reader = None - def ObtainContents(self): + def ObtainContents(self, skip=None): arch = cbfs_util.find_arch(self._cbfs_arg) if arch is None: self.Raise("Invalid architecture '%s'" % self._cbfs_arg) @@ -179,7 +180,7 @@ class Entry_cbfs(Entry): for entry in self._cbfs_entries.values(): # First get the input data and put it in a file. If not available, # try later. - if not entry.ObtainContents(): + if entry != skip and not entry.ObtainContents(): return False data = entry.GetData() cfile = None @@ -202,7 +203,8 @@ class Entry_cbfs(Entry): def _ReadSubnodes(self): """Read the subnodes to find out what should go in this IFWI""" for node in self._node.subnodes: - entry = Entry.Create(self.section, node) + entry = Entry.Create(self, node) + entry.ReadNode() entry._cbfs_name = fdt_util.GetString(node, 'cbfs-name', entry.name) entry._type = fdt_util.GetString(node, 'cbfs-type') compress = fdt_util.GetString(node, 'cbfs-compress', 'none') @@ -261,3 +263,19 @@ class Entry_cbfs(Entry): def GetEntries(self): return self._cbfs_entries + + def ReadData(self, decomp=True): + data = Entry.ReadData(self, True) + return data + + def ReadChildData(self, child, decomp=True): + if not self.reader: + data = Entry.ReadData(self, True) + self.reader = cbfs_util.CbfsReader(data) + reader = self.reader + cfile = reader.files.get(child.name) + return cfile.data if decomp else cfile.orig_data + + def WriteChildData(self, child): + self.ObtainContents(skip=child) + return True diff --git a/tools/binman/etype/fdtmap.py b/tools/binman/etype/fdtmap.py index ddb9738e5c..b1810b9ddb 100644 --- a/tools/binman/etype/fdtmap.py +++ b/tools/binman/etype/fdtmap.py @@ -14,6 +14,7 @@ from entry import Entry from fdt import Fdt import state import tools +import tout FDTMAP_MAGIC = b'_FDTMAP_' FDTMAP_HDR_LEN = 16 @@ -59,6 +60,7 @@ class Entry_fdtmap(Entry): Example output for a simple image with U-Boot and an FDT map: / { + image-name = "binman"; size = <0x00000112>; image-pos = <0x00000000>; offset = <0x00000000>; @@ -73,6 +75,9 @@ class Entry_fdtmap(Entry): offset = <0x00000004>; }; }; + + If allow-repack is used then 'orig-offset' and 'orig-size' properties are + added as necessary. See the binman README. """ def __init__(self, section, etype, node): Entry.__init__(self, section, etype, node) @@ -91,29 +96,38 @@ class Entry_fdtmap(Entry): with fsw.add_node(subnode.name): _AddNode(subnode) - # Get the FDT data into an Fdt object - data = state.GetFdtContents()[1] - infdt = Fdt.FromData(data) - infdt.Scan() - - # Find the node for the image containing the Fdt-map entry - path = self.section.GetPath() - node = infdt.GetNode(path) - if not node: - self.Raise("Internal error: Cannot locate node for path '%s'" % - path) - - # Build a new tree with all nodes and properties starting from that node - fsw = libfdt.FdtSw() - fsw.finish_reservemap() - with fsw.add_node(''): - _AddNode(node) - fdt = fsw.as_fdt() - - # Pack this new FDT and return its contents - fdt.pack() - outfdt = Fdt.FromData(fdt.as_bytearray()) - data = FDTMAP_MAGIC + tools.GetBytes(0, 8) + outfdt.GetContents() + data = state.GetFdtContents('fdtmap')[1] + # If we have an fdtmap it means that we are using this as the + # fdtmap for this image. + if data is None: + # Get the FDT data into an Fdt object + data = state.GetFdtContents()[1] + infdt = Fdt.FromData(data) + infdt.Scan() + + # Find the node for the image containing the Fdt-map entry + path = self.section.GetPath() + self.Detail("Fdtmap: Using section '%s' (path '%s')" % + (self.section.name, path)) + node = infdt.GetNode(path) + if not node: + self.Raise("Internal error: Cannot locate node for path '%s'" % + path) + + # Build a new tree with all nodes and properties starting from that + # node + fsw = libfdt.FdtSw() + fsw.finish_reservemap() + with fsw.add_node(''): + fsw.property_string('image-node', node.name) + _AddNode(node) + fdt = fsw.as_fdt() + + # Pack this new FDT and return its contents + fdt.pack() + outfdt = Fdt.FromData(fdt.as_bytearray()) + data = outfdt.GetContents() + data = FDTMAP_MAGIC + tools.GetBytes(0, 8) + data return data def ObtainContents(self): diff --git a/tools/binman/etype/fill.py b/tools/binman/etype/fill.py index 68efe42ec0..623b7f4e95 100644 --- a/tools/binman/etype/fill.py +++ b/tools/binman/etype/fill.py @@ -23,6 +23,9 @@ class Entry_fill(Entry): """ def __init__(self, section, etype, node): Entry.__init__(self, section, etype, node) + + def ReadNode(self): + Entry.ReadNode(self) if self.size is None: self.Raise("'fill' entry must have a size property") self.fill_value = fdt_util.GetByte(self._node, 'fill-byte', 0) diff --git a/tools/binman/etype/fmap.py b/tools/binman/etype/fmap.py index f8d8d866f1..835ba5012e 100644 --- a/tools/binman/etype/fmap.py +++ b/tools/binman/etype/fmap.py @@ -8,6 +8,8 @@ from entry import Entry import fmap_util import tools +from tools import ToHexSize +import tout class Entry_fmap(Entry): @@ -26,7 +28,8 @@ class Entry_fmap(Entry): When used, this entry will be populated with an FMAP which reflects the entries in the current image. Note that any hierarchy is squashed, since - FMAP does not support this. + FMAP does not support this. Also, CBFS entries appear as a single entry - + the sub-entries are ignored. """ def __init__(self, section, etype, node): Entry.__init__(self, section, etype, node) @@ -39,7 +42,9 @@ class Entry_fmap(Entry): """ def _AddEntries(areas, entry): entries = entry.GetEntries() - if entries: + tout.Debug("fmap: Add entry '%s' type '%s' (%s subentries)" % + (entry.GetPath(), entry.etype, ToHexSize(entries))) + if entries and entry.etype != 'cbfs': for subentry in entries.values(): _AddEntries(areas, subentry) else: @@ -49,7 +54,7 @@ class Entry_fmap(Entry): areas.append(fmap_util.FmapArea(pos or 0, entry.size or 0, tools.FromUnicode(entry.name), 0)) - entries = self.section.image.GetEntries() + entries = self.GetImage().GetEntries() areas = [] for entry in entries.values(): _AddEntries(areas, entry) diff --git a/tools/binman/etype/image_header.py b/tools/binman/etype/image_header.py index 8f9c5aa5d9..4b69eda1a2 100644 --- a/tools/binman/etype/image_header.py +++ b/tools/binman/etype/image_header.py @@ -86,8 +86,20 @@ class Entry_image_header(Entry): if self.location not in ['start', 'end']: self.Raise("Invalid location '%s', expected 'start' or 'end'" % self.location) - image_size = self.section.GetImageSize() or 0 - self.offset = (0 if self.location != 'end' else image_size - 8) + order = self.GetSiblingOrder() + if self.location != order and not self.section.GetSort(): + self.Raise("Invalid sibling order '%s' for image-header: Must be at '%s' to match location" % + (order, self.location)) + if self.location != 'end': + offset = 0 + else: + image_size = self.section.GetImageSize() + if image_size is None: + # We don't know the image, but this must be the last entry, + # so we can assume it goes + offset = offset + else: + offset = image_size - IMAGE_HEADER_LEN return Entry.Pack(self, offset) def ProcessContents(self): diff --git a/tools/binman/etype/intel_descriptor.py b/tools/binman/etype/intel_descriptor.py index adea578080..fb5e889ebf 100644 --- a/tools/binman/etype/intel_descriptor.py +++ b/tools/binman/etype/intel_descriptor.py @@ -47,8 +47,12 @@ class Entry_intel_descriptor(Entry_blob): def __init__(self, section, etype, node): Entry_blob.__init__(self, section, etype, node) self._regions = [] + + def Pack(self, offset): + """Put this entry at the start of the image""" if self.offset is None: - self.offset = self.section.GetStartOffset() + offset = self.section.GetStartOffset() + return Entry_blob.Pack(self, offset) def GetOffsets(self): offset = self.data.find(FD_SIGNATURE) diff --git a/tools/binman/etype/intel_ifwi.py b/tools/binman/etype/intel_ifwi.py index 8c79b2dd29..9cbdf3698a 100644 --- a/tools/binman/etype/intel_ifwi.py +++ b/tools/binman/etype/intel_ifwi.py @@ -94,6 +94,7 @@ class Entry_intel_ifwi(Entry_blob): """Read the subnodes to find out what should go in this IFWI""" for node in self._node.subnodes: entry = Entry.Create(self.section, node) + entry.ReadNode() entry._ifwi_replace = fdt_util.GetBool(node, 'replace') entry._ifwi_subpart = fdt_util.GetString(node, 'ifwi-subpart') entry._ifwi_entry_name = fdt_util.GetString(node, 'ifwi-entry') diff --git a/tools/binman/etype/section.py b/tools/binman/etype/section.py index 6db3c7a6f0..5d34fc546a 100644 --- a/tools/binman/etype/section.py +++ b/tools/binman/etype/section.py @@ -17,6 +17,7 @@ import sys from entry import Entry import fdt_util import tools +import tout class Entry_section(Entry): @@ -45,29 +46,15 @@ class Entry_section(Entry): def __init__(self, section, etype, node, test=False): if not test: Entry.__init__(self, section, etype, node) - if section: - self.image = section.image self._entries = OrderedDict() self._pad_byte = 0 self._sort = False self._skip_at_start = None self._end_4gb = False - if not test: - self._ReadNode() - self._ReadEntries() - - def _Raise(self, msg): - """Raises an error for this section - - Args: - msg: Error message to use in the raise string - Raises: - ValueError() - """ - raise ValueError("Section '%s': %s" % (self._node.path, msg)) - def _ReadNode(self): + def ReadNode(self): """Read properties from the image node""" + Entry.ReadNode(self) self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0) self._sort = fdt_util.GetBool(self._node, 'sort-by-offset') self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb') @@ -87,19 +74,32 @@ class Entry_section(Entry): if filename: self._filename = filename + self._ReadEntries() + def _ReadEntries(self): for node in self._node.subnodes: if node.name == 'hash': continue entry = Entry.Create(self, node) + entry.ReadNode() entry.SetPrefix(self._name_prefix) self._entries[node.name] = entry - def GetFdtSet(self): - fdt_set = set() + def _Raise(self, msg): + """Raises an error for this section + + Args: + msg: Error message to use in the raise string + Raises: + ValueError() + """ + raise ValueError("Section '%s': %s" % (self._node.path, msg)) + + def GetFdts(self): + fdts = {} for entry in self._entries.values(): - fdt_set.update(entry.GetFdtSet()) - return fdt_set + fdts.update(entry.GetFdts()) + return fdts def ProcessFdt(self, fdt): """Allow entries to adjust the device tree @@ -149,6 +149,8 @@ class Entry_section(Entry): base = self.pad_before + entry.offset - self._skip_at_start section_data = (section_data[:base] + data + section_data[base + len(data):]) + self.Detail('GetData: %d entries, total size %#x' % + (len(self._entries), len(section_data))) return section_data def GetOffsets(self): @@ -371,7 +373,7 @@ class Entry_section(Entry): Image size as an integer number of bytes, which may be None if the image size is dynamic and its sections have not yet been packed """ - return self.image.size + return self.GetImage().size def FindEntryType(self, etype): """Find an entry type in the section @@ -460,3 +462,64 @@ class Entry_section(Entry): self.image_pos, None, self.offset, self) for entry in self._entries.values(): entry.ListEntries(entries, indent + 1) + + def LoadData(self, decomp=True): + for entry in self._entries.values(): + entry.LoadData(decomp) + self.Detail('Loaded data') + + def GetImage(self): + """Get the image containing this section + + Note that a top-level section is actually an Image, so this function may + return self. + + Returns: + Image object containing this section + """ + if not self.section: + return self + return self.section.GetImage() + + def GetSort(self): + """Check if the entries in this section will be sorted + + Returns: + True if to be sorted, False if entries will be left in the order + they appear in the device tree + """ + return self._sort + + def ReadData(self, decomp=True): + tout.Info("ReadData path='%s'" % self.GetPath()) + parent_data = self.section.ReadData(True) + tout.Info('%s: Reading data from offset %#x-%#x, size %#x' % + (self.GetPath(), self.offset, self.offset + self.size, + self.size)) + data = parent_data[self.offset:self.offset + self.size] + return data + + def ReadChildData(self, child, decomp=True): + """Read the data for a particular child entry + + Args: + child: Child entry to read data for + decomp: True to return uncompressed data, False to leave the data + compressed if it is compressed + + Returns: + Data contents of entry + """ + parent_data = self.ReadData(True) + data = parent_data[child.offset:child.offset + child.size] + if decomp: + indata = data + data = tools.Decompress(indata, child.compress) + if child.uncomp_size: + tout.Info("%s: Decompressing data size %#x with algo '%s' to data size %#x" % + (child.GetPath(), len(indata), child.compress, + len(data))) + return data + + def WriteChildData(self, child): + return True diff --git a/tools/binman/etype/u_boot_dtb.py b/tools/binman/etype/u_boot_dtb.py index 6263c4ebee..6c805a666d 100644 --- a/tools/binman/etype/u_boot_dtb.py +++ b/tools/binman/etype/u_boot_dtb.py @@ -26,3 +26,6 @@ class Entry_u_boot_dtb(Entry_blob_dtb): def GetDefaultFilename(self): return 'u-boot.dtb' + + def GetFdtEtype(self): + return 'u-boot-dtb' diff --git a/tools/binman/etype/u_boot_dtb_with_ucode.py b/tools/binman/etype/u_boot_dtb_with_ucode.py index 188888e022..cb6c3730d7 100644 --- a/tools/binman/etype/u_boot_dtb_with_ucode.py +++ b/tools/binman/etype/u_boot_dtb_with_ucode.py @@ -36,6 +36,9 @@ class Entry_u_boot_dtb_with_ucode(Entry_blob_dtb): def GetDefaultFilename(self): return 'u-boot.dtb' + def GetFdtEtype(self): + return 'u-boot-dtb' + def ProcessFdt(self, fdt): # So the module can be loaded without it import fdt @@ -53,11 +56,11 @@ class Entry_u_boot_dtb_with_ucode(Entry_blob_dtb): return True # Remove the microcode - fname = self.GetDefaultFilename() - fdt = state.GetFdt(fname) + etype = self.GetFdtEtype() + fdt = state.GetFdtForEtype(etype) self.ucode = fdt.GetNode('/microcode') if not self.ucode: - raise self.Raise("No /microcode node found in '%s'" % fname) + raise self.Raise("No /microcode node found in '%s'" % etype) # There's no need to collate it (move all microcode into one place) # if we only have one chunk of microcode. diff --git a/tools/binman/etype/u_boot_spl_dtb.py b/tools/binman/etype/u_boot_spl_dtb.py index e7354646f1..1bcd449bf3 100644 --- a/tools/binman/etype/u_boot_spl_dtb.py +++ b/tools/binman/etype/u_boot_spl_dtb.py @@ -23,3 +23,6 @@ class Entry_u_boot_spl_dtb(Entry_blob_dtb): def GetDefaultFilename(self): return 'spl/u-boot-spl.dtb' + + def GetFdtEtype(self): + return 'u-boot-spl-dtb' diff --git a/tools/binman/etype/u_boot_tpl_dtb.py b/tools/binman/etype/u_boot_tpl_dtb.py index bdeb0f75a2..81a3970459 100644 --- a/tools/binman/etype/u_boot_tpl_dtb.py +++ b/tools/binman/etype/u_boot_tpl_dtb.py @@ -23,3 +23,6 @@ class Entry_u_boot_tpl_dtb(Entry_blob_dtb): def GetDefaultFilename(self): return 'tpl/u-boot-tpl.dtb' + + def GetFdtEtype(self): + return 'u-boot-tpl-dtb' diff --git a/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py b/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py index 71e04fcd44..ce19a49e2e 100644 --- a/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py +++ b/tools/binman/etype/u_boot_tpl_dtb_with_ucode.py @@ -23,3 +23,6 @@ class Entry_u_boot_tpl_dtb_with_ucode(Entry_u_boot_dtb_with_ucode): def GetDefaultFilename(self): return 'tpl/u-boot-tpl.dtb' + + def GetFdtEtype(self): + return 'u-boot-tpl-dtb' diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 6a40d1fdbb..0f3b70b3bb 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -69,8 +69,15 @@ FILES_DATA = (b"sorry I'm late\nOh, don't bother apologising, I'm " + COMPRESS_DATA = b'compress xxxxxxxxxxxxxxxxxxxxxx data' REFCODE_DATA = b'refcode' +# The expected size for the device tree in some tests EXTRACT_DTB_SIZE = 0x3c9 +# Properties expected to be in the device tree when update_dtb is used +BASE_DTB_PROPS = ['offset', 'size', 'image-pos'] + +# Extra properties expected to be in the device tree when allow-repack is used +REPACK_DTB_PROPS = ['orig-offset', 'orig-size'] + class TestFunctional(unittest.TestCase): """Functional tests for binman @@ -180,6 +187,13 @@ class TestFunctional(unittest.TestCase): if not self.have_lz4: self.skipTest('lz4 --no-frame-crc not available') + def _CleanupOutputDir(self): + """Remove the temporary output directory""" + if self.preserve_outdirs: + print('Preserving output dir: %s' % tools.outdir) + else: + tools._FinaliseForTest() + def setUp(self): # Enable this to turn on debugging output # tout.Init(tout.DEBUG) @@ -187,10 +201,29 @@ class TestFunctional(unittest.TestCase): def tearDown(self): """Remove the temporary output directory""" - if self.preserve_outdirs: - print('Preserving output dir: %s' % tools.outdir) - else: - tools._FinaliseForTest() + self._CleanupOutputDir() + + def _SetupImageInTmpdir(self): + """Set up the output image in a new temporary directory + + This is used when an image has been generated in the output directory, + but we want to run binman again. This will create a new output + directory and fail to delete the original one. + + This creates a new temporary directory, copies the image to it (with a + new name) and removes the old output directory. + + Returns: + Tuple: + Temporary directory to use + New image filename + """ + image_fname = tools.GetOutputFilename('image.bin') + tmpdir = tempfile.mkdtemp(prefix='binman.') + updated_fname = os.path.join(tmpdir, 'image-updated.bin') + tools.WriteFile(updated_fname, tools.ReadFile(image_fname)) + self._CleanupOutputDir() + return tmpdir, updated_fname @classmethod def _ResetDtbs(self): @@ -283,12 +316,12 @@ class TestFunctional(unittest.TestCase): Returns: Contents of device-tree binary """ - tools.PrepareOutputDir(None) - dtb = fdt_util.EnsureCompiled(self.TestFile(fname)) + tmpdir = tempfile.mkdtemp(prefix='binmant.') + dtb = fdt_util.EnsureCompiled(self.TestFile(fname), tmpdir) with open(dtb, 'rb') as fd: data = fd.read() TestFunctional._MakeInputFile(outfile, data) - tools.FinaliseOutputDir() + shutil.rmtree(tmpdir) return data def _GetDtbContentsForSplTpl(self, dtb_data, name): @@ -1229,7 +1262,7 @@ class TestFunctional(unittest.TestCase): state.SetAllowEntryExpansion(False) with self.assertRaises(ValueError) as e: self._DoReadFile('059_change_size.dts', True) - self.assertIn("Node '/binman/_testing': Cannot update entry size from 1 to 2", + self.assertIn("Node '/binman/_testing': Cannot update entry size from 2 to 3", str(e.exception)) finally: state.SetAllowEntryExpansion(True) @@ -1240,12 +1273,12 @@ class TestFunctional(unittest.TestCase): update_dtb=True) dtb = fdt.Fdt(out_dtb_fname) dtb.Scan() - props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos']) + props = self._GetPropTree(dtb, BASE_DTB_PROPS + REPACK_DTB_PROPS) self.assertEqual({ 'image-pos': 0, 'offset': 0, '_testing:offset': 32, - '_testing:size': 1, + '_testing:size': 2, '_testing:image-pos': 32, 'section@0/u-boot:offset': 0, 'section@0/u-boot:size': len(U_BOOT_DATA), @@ -1552,6 +1585,7 @@ class TestFunctional(unittest.TestCase): self.assertFalse(os.path.exists(tools.GetOutputFilename('image1.bin'))) self.assertTrue(os.path.exists(tools.GetOutputFilename('image2.bin'))) + self._CleanupOutputDir() def testUpdateFdtAll(self): """Test that all device trees are updated with offset/size info""" @@ -1583,8 +1617,8 @@ class TestFunctional(unittest.TestCase): for item in ['', 'spl', 'tpl']: dtb = fdt.Fdt.FromData(data[start:]) dtb.Scan() - props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos', - 'spl', 'tpl']) + props = self._GetPropTree(dtb, BASE_DTB_PROPS + REPACK_DTB_PROPS + + ['spl', 'tpl']) expected = dict(base_expected) if item: expected[item] = 0 @@ -2052,8 +2086,7 @@ class TestFunctional(unittest.TestCase): fdt_data = fdtmap_data[16:] dtb = fdt.Fdt.FromData(fdt_data) dtb.Scan() - props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos'], - prefix='/') + props = self._GetPropTree(dtb, BASE_DTB_PROPS, prefix='/') self.assertEqual({ 'image-pos': 0, 'offset': 0, @@ -2129,23 +2162,23 @@ class TestFunctional(unittest.TestCase): def testEntryExpand(self): """Test expanding an entry after it is packed""" data = self._DoReadFile('121_entry_expand.dts') - self.assertEqual(b'aa', data[:2]) - self.assertEqual(U_BOOT_DATA, data[2:2 + len(U_BOOT_DATA)]) - self.assertEqual(b'aa', data[-2:]) + self.assertEqual(b'aaa', data[:3]) + self.assertEqual(U_BOOT_DATA, data[3:3 + len(U_BOOT_DATA)]) + self.assertEqual(b'aaa', data[-3:]) def testEntryExpandBad(self): """Test expanding an entry after it is packed, twice""" with self.assertRaises(ValueError) as e: self._DoReadFile('122_entry_expand_twice.dts') - self.assertIn("Image '/binman': Entries expanded after packing", + self.assertIn("Image '/binman': Entries changed size after packing", str(e.exception)) def testEntryExpandSection(self): """Test expanding an entry within a section after it is packed""" data = self._DoReadFile('123_entry_expand_section.dts') - self.assertEqual(b'aa', data[:2]) - self.assertEqual(U_BOOT_DATA, data[2:2 + len(U_BOOT_DATA)]) - self.assertEqual(b'aa', data[-2:]) + self.assertEqual(b'aaa', data[:3]) + self.assertEqual(U_BOOT_DATA, data[3:3 + len(U_BOOT_DATA)]) + self.assertEqual(b'aaa', data[-3:]) def testCompressDtb(self): """Test that compress of device-tree files is supported""" @@ -2172,8 +2205,7 @@ class TestFunctional(unittest.TestCase): update_dtb=True) dtb = fdt.Fdt(out_dtb_fname) dtb.Scan() - props = self._GetPropTree(dtb, ['offset', 'size', 'image-pos', - 'uncomp-size']) + props = self._GetPropTree(dtb, BASE_DTB_PROPS + ['uncomp-size']) del props['cbfs/u-boot:size'] self.assertEqual({ 'offset': 0, @@ -2333,7 +2365,7 @@ class TestFunctional(unittest.TestCase): image_fname = tools.GetOutputFilename('image.bin') image = Image.FromFile(image_fname) self.assertTrue(isinstance(image, Image)) - self.assertEqual('image', image.image_name) + self.assertEqual('image', image.image_name[-5:]) def testReadImageFail(self): """Test failing to read an image image's FDT map""" @@ -2355,9 +2387,12 @@ class TestFunctional(unittest.TestCase): fdt_size = entries['section'].GetEntries()['u-boot-dtb'].size fdtmap_offset = entries['fdtmap'].offset - image_fname = tools.GetOutputFilename('image.bin') - with test_util.capture_sys_output() as (stdout, stderr): - self._DoBinman('ls', '-i', image_fname) + try: + tmpdir, updated_fname = self._SetupImageInTmpdir() + with test_util.capture_sys_output() as (stdout, stderr): + self._DoBinman('ls', '-i', updated_fname) + finally: + shutil.rmtree(tmpdir) lines = stdout.getvalue().splitlines() expected = [ 'Name Image-pos Size Entry-type Offset Uncomp-size', @@ -2369,7 +2404,7 @@ class TestFunctional(unittest.TestCase): ' u-boot 138 4 u-boot 38', ' u-boot-dtb 180 10f u-boot-dtb 80 3c9', ' u-boot-dtb 500 %x u-boot-dtb 400 3c9' % fdt_size, -' fdtmap %x 395 fdtmap %x' % +' fdtmap %x 3b4 fdtmap %x' % (fdtmap_offset, fdtmap_offset), ' image-header bf8 8 image-header bf8', ] @@ -2378,9 +2413,12 @@ class TestFunctional(unittest.TestCase): def testListCmdFail(self): """Test failing to list an image""" self._DoReadFile('005_simple.dts') - image_fname = tools.GetOutputFilename('image.bin') - with self.assertRaises(ValueError) as e: - self._DoBinman('ls', '-i', image_fname) + try: + tmpdir, updated_fname = self._SetupImageInTmpdir() + with self.assertRaises(ValueError) as e: + self._DoBinman('ls', '-i', updated_fname) + finally: + shutil.rmtree(tmpdir) self.assertIn("Cannot find FDT map in image", str(e.exception)) def _RunListCmd(self, paths, expected): @@ -2480,7 +2518,7 @@ class TestFunctional(unittest.TestCase): def testExtractCbfsRaw(self): """Test extracting CBFS compressed data without decompressing it""" data = self._RunExtractCmd('section/cbfs/u-boot-dtb', decomp=False) - dtb = tools.Decompress(data, 'lzma') + dtb = tools.Decompress(data, 'lzma', with_header=False) self.assertEqual(EXTRACT_DTB_SIZE, len(dtb)) def testExtractBadEntry(self): @@ -2506,10 +2544,14 @@ class TestFunctional(unittest.TestCase): """Test extracting a file fron an image on the command line""" self._CheckLz4() self._DoReadFileRealDtb('130_list_fdtmap.dts') - image_fname = tools.GetOutputFilename('image.bin') fname = os.path.join(self._indir, 'output.extact') - with test_util.capture_sys_output() as (stdout, stderr): - self._DoBinman('extract', '-i', image_fname, 'u-boot', '-f', fname) + try: + tmpdir, updated_fname = self._SetupImageInTmpdir() + with test_util.capture_sys_output() as (stdout, stderr): + self._DoBinman('extract', '-i', updated_fname, 'u-boot', + '-f', fname) + finally: + shutil.rmtree(tmpdir) data = tools.ReadFile(fname) self.assertEqual(U_BOOT_DATA, data) @@ -2641,7 +2683,7 @@ class TestFunctional(unittest.TestCase): image_fname = tools.GetOutputFilename('image.bin') with self.assertRaises(ValueError) as e: control.ExtractEntries(image_fname, 'fname', None, []) - self.assertIn('Must specify an entry path to write with -o', + self.assertIn('Must specify an entry path to write with -f', str(e.exception)) def testExtractTooManyEntryPaths(self): @@ -2651,7 +2693,7 @@ class TestFunctional(unittest.TestCase): image_fname = tools.GetOutputFilename('image.bin') with self.assertRaises(ValueError) as e: control.ExtractEntries(image_fname, 'fname', None, ['a', 'b']) - self.assertIn('Must specify exactly one entry path to write with -o', + self.assertIn('Must specify exactly one entry path to write with -f', str(e.exception)) def testPackAlignSection(self): @@ -2719,6 +2761,481 @@ class TestFunctional(unittest.TestCase): self.assertEqual(len(U_BOOT_DATA), entry.contents_size) self.assertEqual(len(U_BOOT_DATA), entry.size) + def _RunReplaceCmd(self, entry_name, data, decomp=True, allow_resize=True, + dts='132_replace.dts'): + """Replace an entry in an image + + This writes the entry data to update it, then opens the updated file and + returns the value that it now finds there. + + Args: + entry_name: Entry name to replace + data: Data to replace it with + decomp: True to compress the data if needed, False if data is + already compressed so should be used as is + allow_resize: True to allow entries to change size, False to raise + an exception + + Returns: + Tuple: + data from entry + data from fdtmap (excluding header) + Image object that was modified + """ + dtb_data = self._DoReadFileDtb(dts, use_real_dtb=True, + update_dtb=True)[1] + + self.assertIn('image', control.images) + image = control.images['image'] + entries = image.GetEntries() + orig_dtb_data = entries['u-boot-dtb'].data + orig_fdtmap_data = entries['fdtmap'].data + + image_fname = tools.GetOutputFilename('image.bin') + updated_fname = tools.GetOutputFilename('image-updated.bin') + tools.WriteFile(updated_fname, tools.ReadFile(image_fname)) + image = control.WriteEntry(updated_fname, entry_name, data, decomp, + allow_resize) + data = control.ReadEntry(updated_fname, entry_name, decomp) + + # The DT data should not change unless resized: + if not allow_resize: + new_dtb_data = entries['u-boot-dtb'].data + self.assertEqual(new_dtb_data, orig_dtb_data) + new_fdtmap_data = entries['fdtmap'].data + self.assertEqual(new_fdtmap_data, orig_fdtmap_data) + + return data, orig_fdtmap_data[fdtmap.FDTMAP_HDR_LEN:], image + + def testReplaceSimple(self): + """Test replacing a single file""" + expected = b'x' * len(U_BOOT_DATA) + data, expected_fdtmap, _ = self._RunReplaceCmd('u-boot', expected, + allow_resize=False) + self.assertEqual(expected, data) + + # Test that the state looks right. There should be an FDT for the fdtmap + # that we jsut read back in, and it should match what we find in the + # 'control' tables. Checking for an FDT that does not exist should + # return None. + path, fdtmap = state.GetFdtContents('fdtmap') + self.assertIsNotNone(path) + self.assertEqual(expected_fdtmap, fdtmap) + + dtb = state.GetFdtForEtype('fdtmap') + self.assertEqual(dtb.GetContents(), fdtmap) + + missing_path, missing_fdtmap = state.GetFdtContents('missing') + self.assertIsNone(missing_path) + self.assertIsNone(missing_fdtmap) + + missing_dtb = state.GetFdtForEtype('missing') + self.assertIsNone(missing_dtb) + + self.assertEqual('/binman', state.fdt_path_prefix) + + def testReplaceResizeFail(self): + """Test replacing a file by something larger""" + expected = U_BOOT_DATA + b'x' + with self.assertRaises(ValueError) as e: + self._RunReplaceCmd('u-boot', expected, allow_resize=False, + dts='139_replace_repack.dts') + self.assertIn("Node '/u-boot': Entry data size does not match, but resize is disabled", + str(e.exception)) + + def testReplaceMulti(self): + """Test replacing entry data where multiple images are generated""" + data = self._DoReadFileDtb('133_replace_multi.dts', use_real_dtb=True, + update_dtb=True)[0] + expected = b'x' * len(U_BOOT_DATA) + updated_fname = tools.GetOutputFilename('image-updated.bin') + tools.WriteFile(updated_fname, data) + entry_name = 'u-boot' + control.WriteEntry(updated_fname, entry_name, expected, + allow_resize=False) + data = control.ReadEntry(updated_fname, entry_name) + self.assertEqual(expected, data) + + # Check the state looks right. + self.assertEqual('/binman/image', state.fdt_path_prefix) + + # Now check we can write the first image + image_fname = tools.GetOutputFilename('first-image.bin') + updated_fname = tools.GetOutputFilename('first-updated.bin') + tools.WriteFile(updated_fname, tools.ReadFile(image_fname)) + entry_name = 'u-boot' + control.WriteEntry(updated_fname, entry_name, expected, + allow_resize=False) + data = control.ReadEntry(updated_fname, entry_name) + self.assertEqual(expected, data) + + # Check the state looks right. + self.assertEqual('/binman/first-image', state.fdt_path_prefix) + + def testUpdateFdtAllRepack(self): + """Test that all device trees are updated with offset/size info""" + data = self._DoReadFileRealDtb('134_fdt_update_all_repack.dts') + SECTION_SIZE = 0x300 + DTB_SIZE = 602 + FDTMAP_SIZE = 608 + base_expected = { + 'offset': 0, + 'size': SECTION_SIZE + DTB_SIZE * 2 + FDTMAP_SIZE, + 'image-pos': 0, + 'section:offset': 0, + 'section:size': SECTION_SIZE, + 'section:image-pos': 0, + 'section/u-boot-dtb:offset': 4, + 'section/u-boot-dtb:size': 636, + 'section/u-boot-dtb:image-pos': 4, + 'u-boot-spl-dtb:offset': SECTION_SIZE, + 'u-boot-spl-dtb:size': DTB_SIZE, + 'u-boot-spl-dtb:image-pos': SECTION_SIZE, + 'u-boot-tpl-dtb:offset': SECTION_SIZE + DTB_SIZE, + 'u-boot-tpl-dtb:image-pos': SECTION_SIZE + DTB_SIZE, + 'u-boot-tpl-dtb:size': DTB_SIZE, + 'fdtmap:offset': SECTION_SIZE + DTB_SIZE * 2, + 'fdtmap:size': FDTMAP_SIZE, + 'fdtmap:image-pos': SECTION_SIZE + DTB_SIZE * 2, + } + main_expected = { + 'section:orig-size': SECTION_SIZE, + 'section/u-boot-dtb:orig-offset': 4, + } + + # We expect three device-tree files in the output, with the first one + # within a fixed-size section. + # Read them in sequence. We look for an 'spl' property in the SPL tree, + # and 'tpl' in the TPL tree, to make sure they are distinct from the + # main U-Boot tree. All three should have the same positions and offset + # except that the main tree should include the main_expected properties + start = 4 + for item in ['', 'spl', 'tpl', None]: + if item is None: + start += 16 # Move past fdtmap header + dtb = fdt.Fdt.FromData(data[start:]) + dtb.Scan() + props = self._GetPropTree(dtb, + BASE_DTB_PROPS + REPACK_DTB_PROPS + ['spl', 'tpl'], + prefix='/' if item is None else '/binman/') + expected = dict(base_expected) + if item: + expected[item] = 0 + else: + # Main DTB and fdtdec should include the 'orig-' properties + expected.update(main_expected) + # Helpful for debugging: + #for prop in sorted(props): + #print('prop %s %s %s' % (prop, props[prop], expected[prop])) + self.assertEqual(expected, props) + if item == '': + start = SECTION_SIZE + else: + start += dtb._fdt_obj.totalsize() + + def testFdtmapHeaderMiddle(self): + """Test an FDT map in the middle of an image when it should be at end""" + with self.assertRaises(ValueError) as e: + self._DoReadFileRealDtb('135_fdtmap_hdr_middle.dts') + self.assertIn("Invalid sibling order 'middle' for image-header: Must be at 'end' to match location", + str(e.exception)) + + def testFdtmapHeaderStartBad(self): + """Test an FDT map in middle of an image when it should be at start""" + with self.assertRaises(ValueError) as e: + self._DoReadFileRealDtb('136_fdtmap_hdr_startbad.dts') + self.assertIn("Invalid sibling order 'end' for image-header: Must be at 'start' to match location", + str(e.exception)) + + def testFdtmapHeaderEndBad(self): + """Test an FDT map at the start of an image when it should be at end""" + with self.assertRaises(ValueError) as e: + self._DoReadFileRealDtb('137_fdtmap_hdr_endbad.dts') + self.assertIn("Invalid sibling order 'start' for image-header: Must be at 'end' to match location", + str(e.exception)) + + def testFdtmapHeaderNoSize(self): + """Test an image header at the end of an image with undefined size""" + self._DoReadFileRealDtb('138_fdtmap_hdr_nosize.dts') + + def testReplaceResize(self): + """Test replacing a single file in an entry with a larger file""" + expected = U_BOOT_DATA + b'x' + data, _, image = self._RunReplaceCmd('u-boot', expected, + dts='139_replace_repack.dts') + self.assertEqual(expected, data) + + entries = image.GetEntries() + dtb_data = entries['u-boot-dtb'].data + dtb = fdt.Fdt.FromData(dtb_data) + dtb.Scan() + + # The u-boot section should now be larger in the dtb + node = dtb.GetNode('/binman/u-boot') + self.assertEqual(len(expected), fdt_util.GetInt(node, 'size')) + + # Same for the fdtmap + fdata = entries['fdtmap'].data + fdtb = fdt.Fdt.FromData(fdata[fdtmap.FDTMAP_HDR_LEN:]) + fdtb.Scan() + fnode = fdtb.GetNode('/u-boot') + self.assertEqual(len(expected), fdt_util.GetInt(fnode, 'size')) + + def testReplaceResizeNoRepack(self): + """Test replacing an entry with a larger file when not allowed""" + expected = U_BOOT_DATA + b'x' + with self.assertRaises(ValueError) as e: + self._RunReplaceCmd('u-boot', expected) + self.assertIn('Entry data size does not match, but allow-repack is not present for this image', + str(e.exception)) + + def testEntryShrink(self): + """Test contracting an entry after it is packed""" + try: + state.SetAllowEntryContraction(True) + data = self._DoReadFileDtb('140_entry_shrink.dts', + update_dtb=True)[0] + finally: + state.SetAllowEntryContraction(False) + self.assertEqual(b'a', data[:1]) + self.assertEqual(U_BOOT_DATA, data[1:1 + len(U_BOOT_DATA)]) + self.assertEqual(b'a', data[-1:]) + + def testEntryShrinkFail(self): + """Test not being allowed to contract an entry after it is packed""" + data = self._DoReadFileDtb('140_entry_shrink.dts', update_dtb=True)[0] + + # In this case there is a spare byte at the end of the data. The size of + # the contents is only 1 byte but we still have the size before it + # shrunk. + self.assertEqual(b'a\0', data[:2]) + self.assertEqual(U_BOOT_DATA, data[2:2 + len(U_BOOT_DATA)]) + self.assertEqual(b'a\0', data[-2:]) + + def testDescriptorOffset(self): + """Test that the Intel descriptor is always placed at at the start""" + data = self._DoReadFileDtb('141_descriptor_offset.dts') + image = control.images['image'] + entries = image.GetEntries() + desc = entries['intel-descriptor'] + self.assertEqual(0xff800000, desc.offset); + self.assertEqual(0xff800000, desc.image_pos); + + def testReplaceCbfs(self): + """Test replacing a single file in CBFS without changing the size""" + self._CheckLz4() + expected = b'x' * len(U_BOOT_DATA) + data = self._DoReadFileRealDtb('142_replace_cbfs.dts') + updated_fname = tools.GetOutputFilename('image-updated.bin') + tools.WriteFile(updated_fname, data) + entry_name = 'section/cbfs/u-boot' + control.WriteEntry(updated_fname, entry_name, expected, + allow_resize=True) + data = control.ReadEntry(updated_fname, entry_name) + self.assertEqual(expected, data) + + def testReplaceResizeCbfs(self): + """Test replacing a single file in CBFS with one of a different size""" + self._CheckLz4() + expected = U_BOOT_DATA + b'x' + data = self._DoReadFileRealDtb('142_replace_cbfs.dts') + updated_fname = tools.GetOutputFilename('image-updated.bin') + tools.WriteFile(updated_fname, data) + entry_name = 'section/cbfs/u-boot' + control.WriteEntry(updated_fname, entry_name, expected, + allow_resize=True) + data = control.ReadEntry(updated_fname, entry_name) + self.assertEqual(expected, data) + + def _SetupForReplace(self): + """Set up some files to use to replace entries + + This generates an image, copies it to a new file, extracts all the files + in it and updates some of them + + Returns: + List + Image filename + Output directory + Expected values for updated entries, each a string + """ + data = self._DoReadFileRealDtb('143_replace_all.dts') + + updated_fname = tools.GetOutputFilename('image-updated.bin') + tools.WriteFile(updated_fname, data) + + outdir = os.path.join(self._indir, 'extract') + einfos = control.ExtractEntries(updated_fname, None, outdir, []) + + expected1 = b'x' + U_BOOT_DATA + b'y' + u_boot_fname1 = os.path.join(outdir, 'u-boot') + tools.WriteFile(u_boot_fname1, expected1) + + expected2 = b'a' + U_BOOT_DATA + b'b' + u_boot_fname2 = os.path.join(outdir, 'u-boot2') + tools.WriteFile(u_boot_fname2, expected2) + + expected_text = b'not the same text' + text_fname = os.path.join(outdir, 'text') + tools.WriteFile(text_fname, expected_text) + + dtb_fname = os.path.join(outdir, 'u-boot-dtb') + dtb = fdt.FdtScan(dtb_fname) + node = dtb.GetNode('/binman/text') + node.AddString('my-property', 'the value') + dtb.Sync(auto_resize=True) + dtb.Flush() + + return updated_fname, outdir, expected1, expected2, expected_text + + def _CheckReplaceMultiple(self, entry_paths): + """Handle replacing the contents of multiple entries + + Args: + entry_paths: List of entry paths to replace + + Returns: + List + Dict of entries in the image: + key: Entry name + Value: Entry object + Expected values for updated entries, each a string + """ + updated_fname, outdir, expected1, expected2, expected_text = ( + self._SetupForReplace()) + control.ReplaceEntries(updated_fname, None, outdir, entry_paths) + + image = Image.FromFile(updated_fname) + image.LoadData() + return image.GetEntries(), expected1, expected2, expected_text + + def testReplaceAll(self): + """Test replacing the contents of all entries""" + entries, expected1, expected2, expected_text = ( + self._CheckReplaceMultiple([])) + data = entries['u-boot'].data + self.assertEqual(expected1, data) + + data = entries['u-boot2'].data + self.assertEqual(expected2, data) + + data = entries['text'].data + self.assertEqual(expected_text, data) + + # Check that the device tree is updated + data = entries['u-boot-dtb'].data + dtb = fdt.Fdt.FromData(data) + dtb.Scan() + node = dtb.GetNode('/binman/text') + self.assertEqual('the value', node.props['my-property'].value) + + def testReplaceSome(self): + """Test replacing the contents of a few entries""" + entries, expected1, expected2, expected_text = ( + self._CheckReplaceMultiple(['u-boot2', 'text'])) + + # This one should not change + data = entries['u-boot'].data + self.assertEqual(U_BOOT_DATA, data) + + data = entries['u-boot2'].data + self.assertEqual(expected2, data) + + data = entries['text'].data + self.assertEqual(expected_text, data) + + def testReplaceCmd(self): + """Test replacing a file fron an image on the command line""" + self._DoReadFileRealDtb('143_replace_all.dts') + + try: + tmpdir, updated_fname = self._SetupImageInTmpdir() + + fname = os.path.join(tmpdir, 'update-u-boot.bin') + expected = b'x' * len(U_BOOT_DATA) + tools.WriteFile(fname, expected) + + self._DoBinman('replace', '-i', updated_fname, 'u-boot', '-f', fname) + data = tools.ReadFile(updated_fname) + self.assertEqual(expected, data[:len(expected)]) + map_fname = os.path.join(tmpdir, 'image-updated.map') + self.assertFalse(os.path.exists(map_fname)) + finally: + shutil.rmtree(tmpdir) + + def testReplaceCmdSome(self): + """Test replacing some files fron an image on the command line""" + updated_fname, outdir, expected1, expected2, expected_text = ( + self._SetupForReplace()) + + self._DoBinman('replace', '-i', updated_fname, '-I', outdir, + 'u-boot2', 'text') + + tools.PrepareOutputDir(None) + image = Image.FromFile(updated_fname) + image.LoadData() + entries = image.GetEntries() + + # This one should not change + data = entries['u-boot'].data + self.assertEqual(U_BOOT_DATA, data) + + data = entries['u-boot2'].data + self.assertEqual(expected2, data) + + data = entries['text'].data + self.assertEqual(expected_text, data) + + def testReplaceMissing(self): + """Test replacing entries where the file is missing""" + updated_fname, outdir, expected1, expected2, expected_text = ( + self._SetupForReplace()) + + # Remove one of the files, to generate a warning + u_boot_fname1 = os.path.join(outdir, 'u-boot') + os.remove(u_boot_fname1) + + with test_util.capture_sys_output() as (stdout, stderr): + control.ReplaceEntries(updated_fname, None, outdir, []) + self.assertIn("Skipping entry '/u-boot' from missing file", + stdout.getvalue()) + + def testReplaceCmdMap(self): + """Test replacing a file fron an image on the command line""" + self._DoReadFileRealDtb('143_replace_all.dts') + + try: + tmpdir, updated_fname = self._SetupImageInTmpdir() + + fname = os.path.join(self._indir, 'update-u-boot.bin') + expected = b'x' * len(U_BOOT_DATA) + tools.WriteFile(fname, expected) + + self._DoBinman('replace', '-i', updated_fname, 'u-boot', + '-f', fname, '-m') + map_fname = os.path.join(tmpdir, 'image-updated.map') + self.assertTrue(os.path.exists(map_fname)) + finally: + shutil.rmtree(tmpdir) + + def testReplaceNoEntryPaths(self): + """Test replacing an entry without an entry path""" + self._DoReadFileRealDtb('143_replace_all.dts') + image_fname = tools.GetOutputFilename('image.bin') + with self.assertRaises(ValueError) as e: + control.ReplaceEntries(image_fname, 'fname', None, []) + self.assertIn('Must specify an entry path to read with -f', + str(e.exception)) + + def testReplaceTooManyEntryPaths(self): + """Test extracting some entries""" + self._DoReadFileRealDtb('143_replace_all.dts') + image_fname = tools.GetOutputFilename('image.bin') + with self.assertRaises(ValueError) as e: + control.ReplaceEntries(image_fname, 'fname', None, ['a', 'b']) + self.assertIn('Must specify exactly one entry path to write with -f', + str(e.exception)) + if __name__ == "__main__": unittest.main() diff --git a/tools/binman/image.py b/tools/binman/image.py index fb6e591ca6..7b39a1ddce 100644 --- a/tools/binman/image.py +++ b/tools/binman/image.py @@ -10,6 +10,7 @@ from __future__ import print_function from collections import OrderedDict import fnmatch from operator import attrgetter +import os import re import sys @@ -32,22 +33,37 @@ class Image(section.Entry_section): Attributes: filename: Output filename for image + image_node: Name of node containing the description for this image + fdtmap_dtb: Fdt object for the fdtmap when loading from a file + fdtmap_data: Contents of the fdtmap when loading from a file + allow_repack: True to add properties to allow the image to be safely + repacked later Args: + copy_to_orig: Copy offset/size to orig_offset/orig_size after reading + from the device tree test: True if this is being called from a test of Images. This this case there is no device tree defining the structure of the section, so we create a section manually. """ - def __init__(self, name, node, test=False): - self.image = self - section.Entry_section.__init__(self, None, 'section', node, test) + def __init__(self, name, node, copy_to_orig=True, test=False): + section.Entry_section.__init__(self, None, 'section', node, test=test) + self.copy_to_orig = copy_to_orig self.name = 'main-section' self.image_name = name self._filename = '%s.bin' % self.image_name + self.fdtmap_dtb = None + self.fdtmap_data = None + self.allow_repack = False if not test: - filename = fdt_util.GetString(self._node, 'filename') - if filename: - self._filename = filename + self.ReadNode() + + def ReadNode(self): + section.Entry_section.ReadNode(self) + filename = fdt_util.GetString(self._node, 'filename') + if filename: + self._filename = filename + self.allow_repack = fdt_util.GetBool(self._node, 'allow-repack') @classmethod def FromFile(cls, fname): @@ -78,12 +94,22 @@ class Image(section.Entry_section): data[pos + fdtmap.FDTMAP_HDR_LEN:pos + 256]) dtb_size = probe_dtb.GetFdtObj().totalsize() fdtmap_data = data[pos:pos + dtb_size + fdtmap.FDTMAP_HDR_LEN] - dtb = fdt.Fdt.FromData(fdtmap_data[fdtmap.FDTMAP_HDR_LEN:]) + fdt_data = fdtmap_data[fdtmap.FDTMAP_HDR_LEN:] + out_fname = tools.GetOutputFilename('fdtmap.in.dtb') + tools.WriteFile(out_fname, fdt_data) + dtb = fdt.Fdt(out_fname) dtb.Scan() # Return an Image with the associated nodes - image = Image('image', dtb.GetRoot()) + root = dtb.GetRoot() + image = Image('image', root, copy_to_orig=False) + + image.image_node = fdt_util.GetString(root, 'image-node', 'image') + image.fdtmap_dtb = dtb + image.fdtmap_data = fdtmap_data image._data = data + image._filename = fname + image.image_name, _ = os.path.splitext(fname) return image def Raise(self, msg): @@ -117,16 +143,14 @@ class Image(section.Entry_section): """Write symbol values into binary files for access at run time""" section.Entry_section.WriteSymbols(self, self) - def BuildSection(self, fd, base_offset): - """Write the section to a file""" - fd.seek(base_offset) - fd.write(self.GetData()) - def BuildImage(self): """Write the image to a file""" fname = tools.GetOutputFilename(self._filename) + tout.Info("Writing image to '%s'" % fname) with open(fname, 'wb') as fd: - self.BuildSection(fd, 0) + data = self.GetData() + fd.write(data) + tout.Info("Wrote %#x bytes" % len(data)) def WriteMap(self): """Write a map of the image to a .map file diff --git a/tools/binman/state.py b/tools/binman/state.py index 382bda3221..d704ed2c7c 100644 --- a/tools/binman/state.py +++ b/tools/binman/state.py @@ -8,12 +8,24 @@ import hashlib import re +import fdt import os import tools +import tout -# Records the device-tree files known to binman, keyed by filename (e.g. -# 'u-boot-spl.dtb') -fdt_files = {} +# Records the device-tree files known to binman, keyed by entry type (e.g. +# 'u-boot-spl-dtb'). These are the output FDT files, which can be updated by +# binman. They have been copied to <xxx>.out files. +# +# key: entry type +# value: tuple: +# Fdt object +# Filename +# Entry object, or None if not known +output_fdt_info = {} + +# Prefix to add to an fdtmap path to turn it into a path to the /binman node +fdt_path_prefix = '' # Arguments passed to binman to provide arguments to entries entry_args = {} @@ -22,12 +34,6 @@ entry_args = {} # ftest.py) use_fake_dtb = False -# Set of all device tree files references by images -fdt_set = set() - -# Same as above, but excluding the main one -fdt_subset = set() - # The DTB which contains the full image information main_dtb = None @@ -36,35 +42,47 @@ main_dtb = None # Entry.ProcessContentsUpdate() allow_entry_expansion = True -def GetFdt(fname): - """Get the Fdt object for a particular device-tree filename +# Don't allow entries to contract after they have been packed. Instead just +# leave some wasted space. If allowed, this is detected and forces a re-pack, +# but may result in entries that oscillate in size, thus causing a pack error. +# An example is a compressed device tree where the original offset values +# result in a larger compressed size than the new ones, but then after updating +# to the new ones, the compressed size increases, etc. +allow_entry_contraction = False + +def GetFdtForEtype(etype): + """Get the Fdt object for a particular device-tree entry Binman keeps track of at least one device-tree file called u-boot.dtb but can also have others (e.g. for SPL). This function looks up the given - filename and returns the associated Fdt object. + entry and returns the associated Fdt object. Args: - fname: Filename to look up (e.g. 'u-boot.dtb'). + etype: Entry type of device tree (e.g. 'u-boot-dtb') Returns: - Fdt object associated with the filename + Fdt object associated with the entry type """ - return fdt_files[fname] + value = output_fdt_info.get(etype); + if not value: + return None + return value[0] -def GetFdtPath(fname): +def GetFdtPath(etype): """Get the full pathname of a particular Fdt object - Similar to GetFdt() but returns the pathname associated with the Fdt. + Similar to GetFdtForEtype() but returns the pathname associated with the + Fdt. Args: - fname: Filename to look up (e.g. 'u-boot.dtb'). + etype: Entry type of device tree (e.g. 'u-boot-dtb') Returns: Full path name to the associated Fdt """ - return fdt_files[fname]._fname + return output_fdt_info[etype][0]._fname -def GetFdtContents(fname='u-boot.dtb'): +def GetFdtContents(etype='u-boot-dtb'): """Looks up the FDT pathname and contents This is used to obtain the Fdt pathname and contents when needed by an @@ -72,21 +90,40 @@ def GetFdtContents(fname='u-boot.dtb'): the real dtb. Args: - fname: Filename to look up (e.g. 'u-boot.dtb'). + etype: Entry type to look up (e.g. 'u-boot.dtb'). Returns: tuple: pathname to Fdt Fdt data (as bytes) """ - if fname in fdt_files and not use_fake_dtb: - pathname = GetFdtPath(fname) - data = GetFdt(fname).GetContents() + if etype not in output_fdt_info: + return None, None + if not use_fake_dtb: + pathname = GetFdtPath(etype) + data = GetFdtForEtype(etype).GetContents() else: + fname = output_fdt_info[etype][1] pathname = tools.GetInputFilename(fname) data = tools.ReadFile(pathname) return pathname, data +def UpdateFdtContents(etype, data): + """Update the contents of a particular device tree + + The device tree is updated and written back to its file. This affects what + is returned from future called to GetFdtContents(), etc. + + Args: + etype: Entry type (e.g. 'u-boot-dtb') + data: Data to replace the DTB with + """ + dtb, fname, entry = output_fdt_info[etype] + dtb_fname = dtb.GetFilename() + tools.WriteFile(dtb_fname, data) + dtb = fdt.FdtScan(dtb_fname) + output_fdt_info[etype] = [dtb, fname, entry] + def SetEntryArgs(args): """Set the value of the entry args @@ -120,14 +157,14 @@ def GetEntryArg(name): def Prepare(images, dtb): """Get device tree files ready for use - This sets up a set of device tree files that can be retrieved by GetFdts(). - At present there is only one, that for U-Boot proper. + This sets up a set of device tree files that can be retrieved by + GetAllFdts(). This includes U-Boot proper and any SPL device trees. Args: images: List of images being used dtb: Main dtb """ - global fdt_set, fdt_subset, fdt_files, main_dtb + global output_fdt_info, main_dtb, fdt_path_prefix # Import these here in case libfdt.py is not available, in which case # the above help option still works. import fdt @@ -138,33 +175,82 @@ def Prepare(images, dtb): # since it is assumed to be the one passed in with options.dt, and # was handled just above. main_dtb = dtb - fdt_files.clear() - fdt_files['u-boot.dtb'] = dtb - fdt_subset = set() + output_fdt_info.clear() + fdt_path_prefix = '' + output_fdt_info['u-boot-dtb'] = [dtb, 'u-boot.dtb', None] + output_fdt_info['u-boot-spl-dtb'] = [dtb, 'spl/u-boot-spl.dtb', None] + output_fdt_info['u-boot-tpl-dtb'] = [dtb, 'tpl/u-boot-tpl.dtb', None] if not use_fake_dtb: + fdt_set = {} for image in images.values(): - fdt_subset.update(image.GetFdtSet()) - fdt_subset.discard('u-boot.dtb') - for other_fname in fdt_subset: + fdt_set.update(image.GetFdts()) + for etype, other in fdt_set.items(): + entry, other_fname = other infile = tools.GetInputFilename(other_fname) other_fname_dtb = fdt_util.EnsureCompiled(infile) out_fname = tools.GetOutputFilename('%s.out' % os.path.split(other_fname)[1]) tools.WriteFile(out_fname, tools.ReadFile(other_fname_dtb)) other_dtb = fdt.FdtScan(out_fname) - fdt_files[other_fname] = other_dtb + output_fdt_info[etype] = [other_dtb, out_fname, entry] + +def PrepareFromLoadedData(image): + """Get device tree files ready for use with a loaded image -def GetFdts(): + Loaded images are different from images that are being created by binman, + since there is generally already an fdtmap and we read the description from + that. This provides the position and size of every entry in the image with + no calculation required. + + This function uses the same output_fdt_info[] as Prepare(). It finds the + device tree files, adds a reference to the fdtmap and sets the FDT path + prefix to translate from the fdtmap (where the root node is the image node) + to the normal device tree (where the image node is under a /binman node). + + Args: + images: List of images being used + """ + global output_fdt_info, main_dtb, fdt_path_prefix + + tout.Info('Preparing device trees') + output_fdt_info.clear() + fdt_path_prefix = '' + output_fdt_info['fdtmap'] = [image.fdtmap_dtb, 'u-boot.dtb', None] + main_dtb = None + tout.Info(" Found device tree type 'fdtmap' '%s'" % image.fdtmap_dtb.name) + for etype, value in image.GetFdts().items(): + entry, fname = value + out_fname = tools.GetOutputFilename('%s.dtb' % entry.etype) + tout.Info(" Found device tree type '%s' at '%s' path '%s'" % + (etype, out_fname, entry.GetPath())) + entry._filename = entry.GetDefaultFilename() + data = entry.ReadData() + + tools.WriteFile(out_fname, data) + dtb = fdt.Fdt(out_fname) + dtb.Scan() + image_node = dtb.GetNode('/binman') + if 'multiple-images' in image_node.props: + image_node = dtb.GetNode('/binman/%s' % image.image_node) + fdt_path_prefix = image_node.path + output_fdt_info[etype] = [dtb, None, entry] + tout.Info(" FDT path prefix '%s'" % fdt_path_prefix) + + +def GetAllFdts(): """Yield all device tree files being used by binman Yields: Device trees being used (U-Boot proper, SPL, TPL) """ - yield main_dtb - for other_fname in fdt_subset: - yield fdt_files[other_fname] - -def GetUpdateNodes(node): + if main_dtb: + yield main_dtb + for etype in output_fdt_info: + dtb = output_fdt_info[etype][0] + if dtb != main_dtb: + yield dtb + +def GetUpdateNodes(node, for_repack=False): """Yield all the nodes that need to be updated in all device trees The property referenced by this node is added to any device trees which @@ -173,25 +259,32 @@ def GetUpdateNodes(node): Args: node: Node object in the main device tree to look up + for_repack: True if we want only nodes which need 'repack' properties + added to them (e.g. 'orig-offset'), False to return all nodes. We + don't add repack properties to SPL/TPL device trees. Yields: Node objects in each device tree that is in use (U-Boot proper, which is node, SPL and TPL) """ yield node - for dtb in fdt_files.values(): + for dtb, fname, entry in output_fdt_info.values(): if dtb != node.GetFdt(): - other_node = dtb.GetNode(node.path) + if for_repack and entry.etype != 'u-boot-dtb': + continue + other_node = dtb.GetNode(fdt_path_prefix + node.path) + #print(' try', fdt_path_prefix + node.path, other_node) if other_node: yield other_node -def AddZeroProp(node, prop): +def AddZeroProp(node, prop, for_repack=False): """Add a new property to affected device trees with an integer value of 0. Args: prop_name: Name of property + for_repack: True is this property is only needed for repacking """ - for n in GetUpdateNodes(node): + for n in GetUpdateNodes(node, for_repack): n.AddZeroProp(prop) def AddSubnode(node, name): @@ -221,15 +314,18 @@ def AddString(node, prop, value): for n in GetUpdateNodes(node): n.AddString(prop, value) -def SetInt(node, prop, value): +def SetInt(node, prop, value, for_repack=False): """Update an integer property in affected device trees with an integer value This is not allowed to change the size of the FDT. Args: prop_name: Name of property + for_repack: True is this property is only needed for repacking """ - for n in GetUpdateNodes(node): + for n in GetUpdateNodes(node, for_repack): + tout.Detail("File %s: Update node '%s' prop '%s' to %#x" % + (n.GetFdt().name, n.path, prop, value)) n.SetInt(prop, value) def CheckAddHashProp(node): @@ -274,3 +370,22 @@ def AllowEntryExpansion(): raised """ return allow_entry_expansion + +def SetAllowEntryContraction(allow): + """Set whether post-pack contraction of entries is allowed + + Args: + allow: True to allow contraction, False to raise an exception + """ + global allow_entry_contraction + + allow_entry_contraction = allow + +def AllowEntryContraction(): + """Check whether post-pack contraction of entries is allowed + + Returns: + True if contraction should be allowed, False if an exception should be + raised + """ + return allow_entry_contraction diff --git a/tools/binman/test/132_replace.dts b/tools/binman/test/132_replace.dts new file mode 100644 index 0000000000..6ebdcda45c --- /dev/null +++ b/tools/binman/test/132_replace.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + size = <0xc00>; + u-boot { + }; + fdtmap { + }; + u-boot-dtb { + }; + image-header { + location = "end"; + }; + }; +}; diff --git a/tools/binman/test/133_replace_multi.dts b/tools/binman/test/133_replace_multi.dts new file mode 100644 index 0000000000..38b2f39d02 --- /dev/null +++ b/tools/binman/test/133_replace_multi.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + multiple-images; + first-image { + size = <0xc00>; + u-boot { + }; + fdtmap { + }; + u-boot-dtb { + }; + image-header { + location = "end"; + }; + }; + + image { + fdtmap { + }; + u-boot { + }; + u-boot-dtb { + }; + }; + }; +}; diff --git a/tools/binman/test/134_fdt_update_all_repack.dts b/tools/binman/test/134_fdt_update_all_repack.dts new file mode 100644 index 0000000000..625d37673b --- /dev/null +++ b/tools/binman/test/134_fdt_update_all_repack.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + allow-repack; + section { + size = <0x300>; + u-boot-dtb { + offset = <4>; + }; + }; + u-boot-spl-dtb { + }; + u-boot-tpl-dtb { + }; + fdtmap { + }; + }; +}; diff --git a/tools/binman/test/135_fdtmap_hdr_middle.dts b/tools/binman/test/135_fdtmap_hdr_middle.dts new file mode 100644 index 0000000000..d6211da8ae --- /dev/null +++ b/tools/binman/test/135_fdtmap_hdr_middle.dts @@ -0,0 +1,16 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot { + }; + image-header { + location = "end"; + }; + fdtmap { + }; + }; +}; diff --git a/tools/binman/test/136_fdtmap_hdr_startbad.dts b/tools/binman/test/136_fdtmap_hdr_startbad.dts new file mode 100644 index 0000000000..ec5f4bc7e3 --- /dev/null +++ b/tools/binman/test/136_fdtmap_hdr_startbad.dts @@ -0,0 +1,16 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot { + }; + fdtmap { + }; + image-header { + location = "start"; + }; + }; +}; diff --git a/tools/binman/test/137_fdtmap_hdr_endbad.dts b/tools/binman/test/137_fdtmap_hdr_endbad.dts new file mode 100644 index 0000000000..ebacd71eb2 --- /dev/null +++ b/tools/binman/test/137_fdtmap_hdr_endbad.dts @@ -0,0 +1,16 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + image-header { + location = "end"; + }; + u-boot { + }; + fdtmap { + }; + }; +}; diff --git a/tools/binman/test/138_fdtmap_hdr_nosize.dts b/tools/binman/test/138_fdtmap_hdr_nosize.dts new file mode 100644 index 0000000000..c362f8fdff --- /dev/null +++ b/tools/binman/test/138_fdtmap_hdr_nosize.dts @@ -0,0 +1,16 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot { + }; + fdtmap { + }; + image-header { + location = "end"; + }; + }; +}; diff --git a/tools/binman/test/139_replace_repack.dts b/tools/binman/test/139_replace_repack.dts new file mode 100644 index 0000000000..a3daf6f9b4 --- /dev/null +++ b/tools/binman/test/139_replace_repack.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + size = <0xc00>; + allow-repack; + u-boot { + }; + fdtmap { + }; + u-boot-dtb { + }; + image-header { + location = "end"; + }; + }; +}; diff --git a/tools/binman/test/140_entry_shrink.dts b/tools/binman/test/140_entry_shrink.dts new file mode 100644 index 0000000000..b750d63898 --- /dev/null +++ b/tools/binman/test/140_entry_shrink.dts @@ -0,0 +1,20 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + _testing { + bad-shrink-contents; + }; + + u-boot { + }; + + _testing2 { + type = "_testing"; + bad-shrink-contents; + }; + }; +}; diff --git a/tools/binman/test/141_descriptor_offset.dts b/tools/binman/test/141_descriptor_offset.dts new file mode 100644 index 0000000000..f9bff016aa --- /dev/null +++ b/tools/binman/test/141_descriptor_offset.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + sort-by-offset; + end-at-4gb; + size = <0x800000>; + u-boot { + offset = <0xffff0000>; + }; + intel-descriptor { + filename = "descriptor.bin"; + }; + }; +}; diff --git a/tools/binman/test/142_replace_cbfs.dts b/tools/binman/test/142_replace_cbfs.dts new file mode 100644 index 0000000000..d64142f9d5 --- /dev/null +++ b/tools/binman/test/142_replace_cbfs.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + size = <0xe00>; + allow-repack; + u-boot { + }; + section { + align = <0x100>; + cbfs { + size = <0x400>; + u-boot { + cbfs-type = "raw"; + }; + u-boot-dtb { + cbfs-type = "raw"; + cbfs-compress = "lzma"; + cbfs-offset = <0x80>; + }; + }; + u-boot-dtb { + compress = "lz4"; + }; + }; + fdtmap { + }; + image-header { + location = "end"; + }; + }; +}; diff --git a/tools/binman/test/143_replace_all.dts b/tools/binman/test/143_replace_all.dts new file mode 100644 index 0000000000..c5744a3c1c --- /dev/null +++ b/tools/binman/test/143_replace_all.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + size = <0xc00>; + allow-repack; + u-boot { + }; + fdtmap { + }; + u-boot2 { + type = "u-boot"; + }; + text { + text = "some text"; + }; + u-boot-dtb { + }; + image-header { + location = "end"; + }; + }; +}; diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index c1a1d3534d..514e0dd4a3 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -71,6 +71,10 @@ def run_tests(args): print(err) for _, err in result.failures: print(err) + if result.errors or result.failures: + print('dtoc tests FAILED') + return 1 + return 0 def RunTestCoverage(): """Run the tests and check that we get 100% coverage""" @@ -101,7 +105,8 @@ parser.add_option('-T', '--test-coverage', action='store_true', # Run our meagre tests if options.test: - run_tests(args) + ret_code = run_tests(args) + sys.exit(ret_code) elif options.test_coverage: RunTestCoverage() diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py index d9471c4381..6770be79fb 100644 --- a/tools/dtoc/fdt.py +++ b/tools/dtoc/fdt.py @@ -362,6 +362,23 @@ class Node: value = tools.GetBytes(0, len) self.props[prop_name] = Prop(self, None, prop_name, value) + def _CheckProp(self, prop_name): + """Check if a property is present + + Args: + prop_name: Name of property + + Returns: + self + + Raises: + ValueError if the property is missing + """ + if prop_name not in self.props: + raise ValueError("Fdt '%s', node '%s': Missing property '%s'" % + (self._fdt._fname, self.path, prop_name)) + return self + def SetInt(self, prop_name, val): """Update an integer property int the device tree. @@ -374,7 +391,7 @@ class Node: prop_name: Name of property val: Value to set """ - self.props[prop_name].SetInt(val) + self._CheckProp(prop_name).props[prop_name].SetInt(val) def SetData(self, prop_name, val): """Set the data value of a property @@ -386,7 +403,7 @@ class Node: prop_name: Name of property to set val: Data value to set """ - self.props[prop_name].SetData(val) + self._CheckProp(prop_name).props[prop_name].SetData(val) def SetString(self, prop_name, val): """Set the string value of a property @@ -400,7 +417,7 @@ class Node: """ if sys.version_info[0] >= 3: # pragma: no cover val = bytes(val, 'utf-8') - self.props[prop_name].SetData(val + b'\0') + self._CheckProp(prop_name).props[prop_name].SetData(val + b'\0') def AddString(self, prop_name, val): """Add a new string property to a node @@ -481,29 +498,35 @@ class Fdt: Properties: fname: Filename of fdt _root: Root of device tree (a Node object) + name: Helpful name for this Fdt for the user (useful when creating the + DT from data rather than a file) """ def __init__(self, fname): self._fname = fname self._cached_offsets = False self.phandle_to_node = {} + self.name = '' if self._fname: + self.name = self._fname self._fname = fdt_util.EnsureCompiled(self._fname) with open(self._fname, 'rb') as fd: self._fdt_obj = libfdt.Fdt(fd.read()) @staticmethod - def FromData(data): + def FromData(data, name=''): """Create a new Fdt object from the given data Args: data: Device-tree data blob + name: Helpful name for this Fdt for the user Returns: Fdt object containing the data """ fdt = Fdt(None) fdt._fdt_obj = libfdt.Fdt(bytes(data)) + fdt.name = name return fdt def LookupPhandle(self, phandle): @@ -551,6 +574,8 @@ class Fdt: parts = path.split('/') if len(parts) < 2: return None + if len(parts) == 2 and parts[1] == '': + return node for part in parts[1:]: node = node.FindNode(part) if not node: @@ -670,6 +695,14 @@ class Fdt: node = Node(fdt, parent, offset, name, path) return node + def GetFilename(self): + """Get the filename of the device tree + + Returns: + String filename + """ + return self._fname + def FdtScan(fname): """Returns a new Fdt object""" dtb = Fdt(fname) diff --git a/tools/dtoc/fdt_util.py b/tools/dtoc/fdt_util.py index f47879ac00..b105faec74 100644 --- a/tools/dtoc/fdt_util.py +++ b/tools/dtoc/fdt_util.py @@ -43,12 +43,14 @@ def fdt_cells_to_cpu(val, cells): out = out << 32 | fdt32_to_cpu(val[1]) return out -def EnsureCompiled(fname, capture_stderr=False): +def EnsureCompiled(fname, tmpdir=None, capture_stderr=False): """Compile an fdt .dts source file into a .dtb binary blob if needed. Args: fname: Filename (if .dts it will be compiled). It not it will be left alone + tmpdir: Temporary directory for output files, or None to use the + tools-module output directory Returns: Filename of resulting .dtb file @@ -57,8 +59,12 @@ def EnsureCompiled(fname, capture_stderr=False): if ext != '.dts': return fname - dts_input = tools.GetOutputFilename('source.dts') - dtb_output = tools.GetOutputFilename('source.dtb') + if tmpdir: + dts_input = os.path.join(tmpdir, 'source.dts') + dtb_output = os.path.join(tmpdir, 'source.dtb') + else: + dts_input = tools.GetOutputFilename('source.dts') + dtb_output = tools.GetOutputFilename('source.dtb') search_paths = [os.path.join(os.getcwd(), 'include')] root, _ = os.path.splitext(fname) diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py index bf469dbd54..028c8cbaa8 100755 --- a/tools/dtoc/test_fdt.py +++ b/tools/dtoc/test_fdt.py @@ -9,7 +9,9 @@ from __future__ import print_function from optparse import OptionParser import glob import os +import shutil import sys +import tempfile import unittest # Bring in the patman libraries @@ -77,11 +79,16 @@ class TestFdt(unittest.TestCase): """Test the GetNode() method""" node = self.dtb.GetNode('/spl-test') self.assertTrue(isinstance(node, fdt.Node)) + node = self.dtb.GetNode('/i2c@0/pmic@9') self.assertTrue(isinstance(node, fdt.Node)) self.assertEqual('pmic@9', node.name) self.assertIsNone(self.dtb.GetNode('/i2c@0/pmic@9/missing')) + node = self.dtb.GetNode('/') + self.assertTrue(isinstance(node, fdt.Node)) + self.assertEqual(0, node.Offset()) + def testFlush(self): """Check that we can flush the device tree out to its file""" fname = self.dtb._fname @@ -421,6 +428,32 @@ class TestProp(unittest.TestCase): self.dtb.Sync(auto_resize=True) self.assertTrue(dtb2.GetContents() != self.dtb.GetContents()) + def testMissingSetInt(self): + """Test handling of a missing property with SetInt""" + with self.assertRaises(ValueError) as e: + self.node.SetInt('one', 1) + self.assertIn("node '/spl-test': Missing property 'one'", + str(e.exception)) + + def testMissingSetData(self): + """Test handling of a missing property with SetData""" + with self.assertRaises(ValueError) as e: + self.node.SetData('one', b'data') + self.assertIn("node '/spl-test': Missing property 'one'", + str(e.exception)) + + def testMissingSetString(self): + """Test handling of a missing property with SetString""" + with self.assertRaises(ValueError) as e: + self.node.SetString('one', 1) + self.assertIn("node '/spl-test': Missing property 'one'", + str(e.exception)) + + def testGetFilename(self): + """Test the dtb filename can be provided""" + self.assertEqual(tools.GetOutputFilename('source.dtb'), + self.dtb.GetFilename()) + class TestFdtUtil(unittest.TestCase): """Tests for the fdt_util module @@ -514,10 +547,23 @@ class TestFdtUtil(unittest.TestCase): self.assertEqual(0x12345678, fdt_util.fdt_cells_to_cpu(val, 1)) def testEnsureCompiled(self): - """Test a degenerate case of this function""" + """Test a degenerate case of this function (file already compiled)""" dtb = fdt_util.EnsureCompiled('tools/dtoc/dtoc_test_simple.dts') self.assertEqual(dtb, fdt_util.EnsureCompiled(dtb)) + def testEnsureCompiledTmpdir(self): + """Test providing a temporary directory""" + try: + old_outdir = tools.outdir + tools.outdir= None + tmpdir = tempfile.mkdtemp(prefix='test_fdt.') + dtb = fdt_util.EnsureCompiled('tools/dtoc/dtoc_test_simple.dts', + tmpdir) + self.assertEqual(tmpdir, os.path.dirname(dtb)) + shutil.rmtree(tmpdir) + finally: + tools.outdir= old_outdir + def RunTestCoverage(): """Run the tests and check that we get 100% coverage""" diff --git a/tools/logos/u-boot_logo.svg b/tools/logos/u-boot_logo.svg index e45ef2ef77..3b743af195 100644 --- a/tools/logos/u-boot_logo.svg +++ b/tools/logos/u-boot_logo.svg @@ -85,13 +85,6 @@ inkscape:groupmode="layer" id="layer1" transform="translate(0,0)"> - <rect - style="fill:#000000;fill-opacity:1;stroke:none;stroke-width:0" - id="rect31" - width="186" - height="186" - x="0" - y="0" /> <circle style="fill:#004466;fill-opacity:1;stroke-width:0;stroke:none" id="path835" diff --git a/tools/patman/tools.py b/tools/patman/tools.py index e945b54fa2..0d4705db76 100644 --- a/tools/patman/tools.py +++ b/tools/patman/tools.py @@ -9,6 +9,7 @@ import command import glob import os import shutil +import struct import sys import tempfile @@ -82,6 +83,7 @@ def FinaliseOutputDir(): """Tidy up: delete output directory if temporary and not preserved.""" if outdir and not preserve_outdir: _RemoveOutputDir() + outdir = None def GetOutputFilename(fname): """Return a filename within the output directory. @@ -100,6 +102,7 @@ def _FinaliseForTest(): if outdir: _RemoveOutputDir() + outdir = None def SetInputDirs(dirname): """Add a list of input directories, where input files are kept. @@ -377,7 +380,7 @@ def ToBytes(string): return string.encode('utf-8') return string -def Compress(indata, algo): +def Compress(indata, algo, with_header=True): """Compress some data using a given algorithm Note that for lzma this uses an old version of the algorithm, not that @@ -408,9 +411,12 @@ def Compress(indata, algo): data = Run('gzip', '-c', fname, binary=True) else: raise ValueError("Unknown algorithm '%s'" % algo) + if with_header: + hdr = struct.pack('<I', len(data)) + data = hdr + data return data -def Decompress(indata, algo): +def Decompress(indata, algo, with_header=True): """Decompress some data using a given algorithm Note that for lzma this uses an old version of the algorithm, not that @@ -428,6 +434,9 @@ def Decompress(indata, algo): """ if algo == 'none': return indata + if with_header: + data_len = struct.unpack('<I', indata[:4])[0] + indata = indata[4:4 + data_len] fname = GetOutputFilename('%s.decomp.tmp' % algo) with open(fname, 'wb') as fd: fd.write(indata) @@ -473,3 +482,19 @@ def RunIfwiTool(ifwi_file, cmd, fname=None, subpart=None, entry_name=None): if entry_name: args += ['-d', '-e', entry_name] Run(*args) + +def ToHex(val): + """Convert an integer value (or None) to a string + + Returns: + hex value, or 'None' if the value is None + """ + return 'None' if val is None else '%#x' % val + +def ToHexSize(val): + """Return the size of an object in hex + + Returns: + hex value of size, or 'None' if the value is None + """ + return 'None' if val is None else '%#x' % len(val) diff --git a/tools/patman/tout.py b/tools/patman/tout.py index 15acce28cb..2a384851b0 100644 --- a/tools/patman/tout.py +++ b/tools/patman/tout.py @@ -4,16 +4,14 @@ # Terminal output logging. # +from __future__ import print_function + import sys import terminal # Output verbosity levels that we support -ERROR = 0 -WARNING = 1 -NOTICE = 2 -INFO = 3 -DEBUG = 4 +ERROR, WARNING, NOTICE, INFO, DETAIL, DEBUG = range(6) in_progress = False @@ -87,7 +85,7 @@ def _Output(level, msg, color=None): ClearProgress() if color: msg = _color.Color(color, msg) - _stdout.write(msg + '\n') + print(msg) def DoOutput(level, msg): """Output a message to the terminal. @@ -105,7 +103,7 @@ def Error(msg): Args: msg; Message to display. """ - _Output(0, msg, _color.RED) + _Output(ERROR, msg, _color.RED) def Warning(msg): """Display a warning message @@ -113,7 +111,7 @@ def Warning(msg): Args: msg; Message to display. """ - _Output(1, msg, _color.YELLOW) + _Output(WARNING, msg, _color.YELLOW) def Notice(msg): """Display an important infomation message @@ -121,7 +119,7 @@ def Notice(msg): Args: msg; Message to display. """ - _Output(2, msg) + _Output(NOTICE, msg) def Info(msg): """Display an infomation message @@ -129,7 +127,7 @@ def Info(msg): Args: msg; Message to display. """ - _Output(3, msg) + _Output(INFO, msg) def Detail(msg): """Display a detailed message @@ -137,7 +135,7 @@ def Detail(msg): Args: msg; Message to display. """ - _Output(4, msg) + _Output(DETAIL, msg) def Debug(msg): """Display a debug message @@ -145,7 +143,7 @@ def Debug(msg): Args: msg; Message to display. """ - _Output(5, msg) + _Output(DEBUG, msg) def UserOutput(msg): """Display a message regardless of the current output level. diff --git a/tools/zynqmp_pm_cfg_obj_convert.py b/tools/zynqmp_pm_cfg_obj_convert.py new file mode 100755 index 0000000000..dd27f47921 --- /dev/null +++ b/tools/zynqmp_pm_cfg_obj_convert.py @@ -0,0 +1,301 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net> + +import sys +import re +import struct +import logging +import argparse + +parser = argparse.ArgumentParser( + description='Convert a PMU configuration object from C source to a binary blob.') +parser.add_argument('-D', '--debug', action="store_true") +parser.add_argument( + "in_file", metavar='INPUT_FILE', + help='PMU configuration object (C source as produced by Xilinx XSDK)') +parser.add_argument( + "out_file", metavar='OUTPUT_FILE', + help='PMU configuration object binary blob') +args = parser.parse_args() + +logging.basicConfig(format='%(levelname)s:%(message)s', + level=(logging.DEBUG if args.debug else logging.WARNING)) + +pm_define = { + 'PM_CAP_ACCESS' : 0x1, + 'PM_CAP_CONTEXT' : 0x2, + 'PM_CAP_WAKEUP' : 0x4, + + 'NODE_UNKNOWN' : 0, + 'NODE_APU' : 1, + 'NODE_APU_0' : 2, + 'NODE_APU_1' : 3, + 'NODE_APU_2' : 4, + 'NODE_APU_3' : 5, + 'NODE_RPU' : 6, + 'NODE_RPU_0' : 7, + 'NODE_RPU_1' : 8, + 'NODE_PLD' : 9, + 'NODE_FPD' : 10, + 'NODE_OCM_BANK_0' : 11, + 'NODE_OCM_BANK_1' : 12, + 'NODE_OCM_BANK_2' : 13, + 'NODE_OCM_BANK_3' : 14, + 'NODE_TCM_0_A' : 15, + 'NODE_TCM_0_B' : 16, + 'NODE_TCM_1_A' : 17, + 'NODE_TCM_1_B' : 18, + 'NODE_L2' : 19, + 'NODE_GPU_PP_0' : 20, + 'NODE_GPU_PP_1' : 21, + 'NODE_USB_0' : 22, + 'NODE_USB_1' : 23, + 'NODE_TTC_0' : 24, + 'NODE_TTC_1' : 25, + 'NODE_TTC_2' : 26, + 'NODE_TTC_3' : 27, + 'NODE_SATA' : 28, + 'NODE_ETH_0' : 29, + 'NODE_ETH_1' : 30, + 'NODE_ETH_2' : 31, + 'NODE_ETH_3' : 32, + 'NODE_UART_0' : 33, + 'NODE_UART_1' : 34, + 'NODE_SPI_0' : 35, + 'NODE_SPI_1' : 36, + 'NODE_I2C_0' : 37, + 'NODE_I2C_1' : 38, + 'NODE_SD_0' : 39, + 'NODE_SD_1' : 40, + 'NODE_DP' : 41, + 'NODE_GDMA' : 42, + 'NODE_ADMA' : 43, + 'NODE_NAND' : 44, + 'NODE_QSPI' : 45, + 'NODE_GPIO' : 46, + 'NODE_CAN_0' : 47, + 'NODE_CAN_1' : 48, + 'NODE_EXTERN' : 49, + 'NODE_APLL' : 50, + 'NODE_VPLL' : 51, + 'NODE_DPLL' : 52, + 'NODE_RPLL' : 53, + 'NODE_IOPLL' : 54, + 'NODE_DDR' : 55, + 'NODE_IPI_APU' : 56, + 'NODE_IPI_RPU_0' : 57, + 'NODE_GPU' : 58, + 'NODE_PCIE' : 59, + 'NODE_PCAP' : 60, + 'NODE_RTC' : 61, + 'NODE_LPD' : 62, + 'NODE_VCU' : 63, + 'NODE_IPI_RPU_1' : 64, + 'NODE_IPI_PL_0' : 65, + 'NODE_IPI_PL_1' : 66, + 'NODE_IPI_PL_2' : 67, + 'NODE_IPI_PL_3' : 68, + 'NODE_PL' : 69, + 'NODE_ID_MA' : 70, + + 'XILPM_RESET_PCIE_CFG' : 1000, + 'XILPM_RESET_PCIE_BRIDGE' : 1001, + 'XILPM_RESET_PCIE_CTRL' : 1002, + 'XILPM_RESET_DP' : 1003, + 'XILPM_RESET_SWDT_CRF' : 1004, + 'XILPM_RESET_AFI_FM5' : 1005, + 'XILPM_RESET_AFI_FM4' : 1006, + 'XILPM_RESET_AFI_FM3' : 1007, + 'XILPM_RESET_AFI_FM2' : 1008, + 'XILPM_RESET_AFI_FM1' : 1009, + 'XILPM_RESET_AFI_FM0' : 1010, + 'XILPM_RESET_GDMA' : 1011, + 'XILPM_RESET_GPU_PP1' : 1012, + 'XILPM_RESET_GPU_PP0' : 1013, + 'XILPM_RESET_GPU' : 1014, + 'XILPM_RESET_GT' : 1015, + 'XILPM_RESET_SATA' : 1016, + 'XILPM_RESET_ACPU3_PWRON' : 1017, + 'XILPM_RESET_ACPU2_PWRON' : 1018, + 'XILPM_RESET_ACPU1_PWRON' : 1019, + 'XILPM_RESET_ACPU0_PWRON' : 1020, + 'XILPM_RESET_APU_L2' : 1021, + 'XILPM_RESET_ACPU3' : 1022, + 'XILPM_RESET_ACPU2' : 1023, + 'XILPM_RESET_ACPU1' : 1024, + 'XILPM_RESET_ACPU0' : 1025, + 'XILPM_RESET_DDR' : 1026, + 'XILPM_RESET_APM_FPD' : 1027, + 'XILPM_RESET_SOFT' : 1028, + 'XILPM_RESET_GEM0' : 1029, + 'XILPM_RESET_GEM1' : 1030, + 'XILPM_RESET_GEM2' : 1031, + 'XILPM_RESET_GEM3' : 1032, + 'XILPM_RESET_QSPI' : 1033, + 'XILPM_RESET_UART0' : 1034, + 'XILPM_RESET_UART1' : 1035, + 'XILPM_RESET_SPI0' : 1036, + 'XILPM_RESET_SPI1' : 1037, + 'XILPM_RESET_SDIO0' : 1038, + 'XILPM_RESET_SDIO1' : 1039, + 'XILPM_RESET_CAN0' : 1040, + 'XILPM_RESET_CAN1' : 1041, + 'XILPM_RESET_I2C0' : 1042, + 'XILPM_RESET_I2C1' : 1043, + 'XILPM_RESET_TTC0' : 1044, + 'XILPM_RESET_TTC1' : 1045, + 'XILPM_RESET_TTC2' : 1046, + 'XILPM_RESET_TTC3' : 1047, + 'XILPM_RESET_SWDT_CRL' : 1048, + 'XILPM_RESET_NAND' : 1049, + 'XILPM_RESET_ADMA' : 1050, + 'XILPM_RESET_GPIO' : 1051, + 'XILPM_RESET_IOU_CC' : 1052, + 'XILPM_RESET_TIMESTAMP' : 1053, + 'XILPM_RESET_RPU_R50' : 1054, + 'XILPM_RESET_RPU_R51' : 1055, + 'XILPM_RESET_RPU_AMBA' : 1056, + 'XILPM_RESET_OCM' : 1057, + 'XILPM_RESET_RPU_PGE' : 1058, + 'XILPM_RESET_USB0_CORERESET' : 1059, + 'XILPM_RESET_USB1_CORERESET' : 1060, + 'XILPM_RESET_USB0_HIBERRESET' : 1061, + 'XILPM_RESET_USB1_HIBERRESET' : 1062, + 'XILPM_RESET_USB0_APB' : 1063, + 'XILPM_RESET_USB1_APB' : 1064, + 'XILPM_RESET_IPI' : 1065, + 'XILPM_RESET_APM_LPD' : 1066, + 'XILPM_RESET_RTC' : 1067, + 'XILPM_RESET_SYSMON' : 1068, + 'XILPM_RESET_AFI_FM6' : 1069, + 'XILPM_RESET_LPD_SWDT' : 1070, + 'XILPM_RESET_FPD' : 1071, + 'XILPM_RESET_RPU_DBG1' : 1072, + 'XILPM_RESET_RPU_DBG0' : 1073, + 'XILPM_RESET_DBG_LPD' : 1074, + 'XILPM_RESET_DBG_FPD' : 1075, + 'XILPM_RESET_APLL' : 1076, + 'XILPM_RESET_DPLL' : 1077, + 'XILPM_RESET_VPLL' : 1078, + 'XILPM_RESET_IOPLL' : 1079, + 'XILPM_RESET_RPLL' : 1080, + 'XILPM_RESET_GPO3_PL_0' : 1081, + 'XILPM_RESET_GPO3_PL_1' : 1082, + 'XILPM_RESET_GPO3_PL_2' : 1083, + 'XILPM_RESET_GPO3_PL_3' : 1084, + 'XILPM_RESET_GPO3_PL_4' : 1085, + 'XILPM_RESET_GPO3_PL_5' : 1086, + 'XILPM_RESET_GPO3_PL_6' : 1087, + 'XILPM_RESET_GPO3_PL_7' : 1088, + 'XILPM_RESET_GPO3_PL_8' : 1089, + 'XILPM_RESET_GPO3_PL_9' : 1090, + 'XILPM_RESET_GPO3_PL_10' : 1091, + 'XILPM_RESET_GPO3_PL_11' : 1092, + 'XILPM_RESET_GPO3_PL_12' : 1093, + 'XILPM_RESET_GPO3_PL_13' : 1094, + 'XILPM_RESET_GPO3_PL_14' : 1095, + 'XILPM_RESET_GPO3_PL_15' : 1096, + 'XILPM_RESET_GPO3_PL_16' : 1097, + 'XILPM_RESET_GPO3_PL_17' : 1098, + 'XILPM_RESET_GPO3_PL_18' : 1099, + 'XILPM_RESET_GPO3_PL_19' : 1100, + 'XILPM_RESET_GPO3_PL_20' : 1101, + 'XILPM_RESET_GPO3_PL_21' : 1102, + 'XILPM_RESET_GPO3_PL_22' : 1103, + 'XILPM_RESET_GPO3_PL_23' : 1104, + 'XILPM_RESET_GPO3_PL_24' : 1105, + 'XILPM_RESET_GPO3_PL_25' : 1106, + 'XILPM_RESET_GPO3_PL_26' : 1107, + 'XILPM_RESET_GPO3_PL_27' : 1108, + 'XILPM_RESET_GPO3_PL_28' : 1109, + 'XILPM_RESET_GPO3_PL_29' : 1110, + 'XILPM_RESET_GPO3_PL_30' : 1111, + 'XILPM_RESET_GPO3_PL_31' : 1112, + 'XILPM_RESET_RPU_LS' : 1113, + 'XILPM_RESET_PS_ONLY' : 1114, + 'XILPM_RESET_PL' : 1115, + 'XILPM_RESET_GPIO5_EMIO_92' : 1116, + 'XILPM_RESET_GPIO5_EMIO_93' : 1117, + 'XILPM_RESET_GPIO5_EMIO_94' : 1118, + 'XILPM_RESET_GPIO5_EMIO_95' : 1119, + + 'PM_CONFIG_MASTER_SECTION_ID' : 0x101, + 'PM_CONFIG_SLAVE_SECTION_ID' : 0x102, + 'PM_CONFIG_PREALLOC_SECTION_ID' : 0x103, + 'PM_CONFIG_POWER_SECTION_ID' : 0x104, + 'PM_CONFIG_RESET_SECTION_ID' : 0x105, + 'PM_CONFIG_SHUTDOWN_SECTION_ID' : 0x106, + 'PM_CONFIG_SET_CONFIG_SECTION_ID' : 0x107, + 'PM_CONFIG_GPO_SECTION_ID' : 0x108, + + 'PM_SLAVE_FLAG_IS_SHAREABLE' : 0x1, + 'PM_MASTER_USING_SLAVE_MASK' : 0x2, + + 'PM_CONFIG_GPO1_MIO_PIN_34_MAP' : (1 << 10), + 'PM_CONFIG_GPO1_MIO_PIN_35_MAP' : (1 << 11), + 'PM_CONFIG_GPO1_MIO_PIN_36_MAP' : (1 << 12), + 'PM_CONFIG_GPO1_MIO_PIN_37_MAP' : (1 << 13), + + 'PM_CONFIG_GPO1_BIT_2_MASK' : (1 << 2), + 'PM_CONFIG_GPO1_BIT_3_MASK' : (1 << 3), + 'PM_CONFIG_GPO1_BIT_4_MASK' : (1 << 4), + 'PM_CONFIG_GPO1_BIT_5_MASK' : (1 << 5), + + 'SUSPEND_TIMEOUT' : 0xFFFFFFFF, + + 'PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK' : 0x00000001, + 'PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK' : 0x00000100, + 'PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK' : 0x00000200, +} + +in_file = open(args.in_file, mode='r') +out_file = open(args.out_file, mode='wb') + +num_re = re.compile(r"^([0-9]+)U?$") +const_re = re.compile(r"^([A-Z_][A-Z0-9_]*)$") + +def process_item(item): + logging.debug("* ITEM " + item) + + value = 0 + for item in item.split('|'): + item = item.strip() + + num_match = num_re .match(item) + const_match = const_re.match(item) + + if num_match: + num = int(num_match.group(1)) + logging.debug(" - num " + str(num)) + value |= num + elif const_match: + name = const_match.group(1) + if not name in pm_define: + sys.stderr.write("Unknown define " + name + "!\n") + exit(1) + num = pm_define[name] + logging.debug(" - def " + hex(num)) + value |= num + + logging.debug(" = res " + hex(value)) + out_file.write(struct.pack('<L', value)) + + +# Read all code +code = in_file.read() + +# remove comments +code = re.sub('//.*?\n|/\*.*?\*/', '', code, flags=re.DOTALL) + +# remove everything outside the XPm_ConfigObject array definition +code = re.search('const u32 XPm_ConfigObject.*= {\n(.*)};', + code, flags=re.DOTALL).group(1) + +# Process each comma-separated array item +for item in code.split(','): + item = item.strip() + if item: + process_item(item) + +print("Wrote %d bytes" % out_file.tell()) diff --git a/tools/zynqmp_psu_init_minimize.sh b/tools/zynqmp_psu_init_minimize.sh new file mode 100755 index 0000000000..384bb56e1a --- /dev/null +++ b/tools/zynqmp_psu_init_minimize.sh @@ -0,0 +1,148 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com> +# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net> + +usage() +{ + cat <<EOF + +Transform a pair of psu_init_gpl.c and .h files produced by the Xilinx +Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that is almost +checkpatch compliant. Minor coding style might still be needed. Must be +run from the top-level U-Boot source directory. + +Usage: zynqmp_psu_init_minimize.sh INPUT_DIR OUTPUT_DIR +Example: zynqmp_psu_init_minimize.sh \\ + /path/to/original/psu_init_gpl_c_and_h/ \\ + board/xilinx/zynqmp/<my_board>/ + +Notes: INPUT_DIR must contain both .c and .h files. + If INPUT_DIR and OUTPUT_DIR are the same directory, + psu_init_gpl.c will be overwritten. + +EOF +} + +set -o errexit -o errtrace +set -o nounset + +if [ $# -ne 2 ] +then + usage >&2 + exit 1 +fi + +IN="${1}/psu_init_gpl.c" +OUT="${2}/psu_init_gpl.c" +TMP=$(mktemp /tmp/psu_init_gpl.XXXXXX) +trap "rm ${TMP}" ERR + +# Step through a temp file to allow both $IN!=$OUT and $IN==$OUT +sed -e '/sleep.h/d' \ + -e '/xil_io.h/d' \ + ${IN} >${TMP} +cp ${TMP} ${OUT} + +# preprocess to expand defines, then remove cpp lines starting with '#' +gcc -I${1} -E ${OUT} -o ${TMP} +sed '/^#/d' ${TMP} >${OUT} + +# Remove trivial code before psu_pll_init_data() +sed -ni '/psu_pll_init_data/,$p' ${OUT} + +# Functions are lowercase in U-Boot, rename them +sed -i 's/PSU_Mask_Write/psu_mask_write/g' ${OUT} +sed -i 's/mask_pollOnValue/mask_pollonvalue/g' ${OUT} +sed -i 's/RegValue/regvalue/g' ${OUT} +sed -i 's/MaskStatus/maskstatus/g' ${OUT} + +sed -i '/&= psu_peripherals_powerdwn_data()/d' ${OUT} + +FUNCS_TO_REMOVE="psu_protection +psu_..._protection +psu_init_xppu_aper_ram +mask_delay(u32 +mask_read(u32 +dpll_prog +mask_poll(u32 +mask_pollonvalue(u32 +psu_ps_pl_reset_config_data +psu_ps_pl_isolation_removal_data +psu_apply_master_tz +psu_post_config_data +psu_post_config_data +psu_peripherals_powerdwn_data +psu_init_ddr_self_refresh +xmpu +xppu +" +for i in $FUNCS_TO_REMOVE; do +sed -i "/$i/,/^}$/d" ${OUT} +done + +scripts/Lindent ${OUT} + +# Prepend 'static' to internal functions +sed -i 's/^.*data(void)$/static &/g' ${OUT} +sed -i 's/^.*psu_afi_config(void)$/static &/g' ${OUT} +sed -i 's/^void init_peripheral/static &/g' ${OUT} +sed -i 's/^int serdes/static &/g' ${OUT} +sed -i 's/^int init_serdes/static &/g' ${OUT} +sed -i 's/^unsigned long /static &/g' ${OUT} + +sed -i 's/()$/(void)/g' ${OUT} +sed -i 's/0X/0x/g' ${OUT} + +# return (0) -> return 0 +sed -ri 's/return \(([0-9]+)\)/return \1/g' ${OUT} + +# Add header +cat << EOF >${TMP} +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2015 Xilinx, Inc. All rights reserved. + */ + +#include <asm/arch/psu_init_gpl.h> +#include <xil_io.h> + +EOF + +cat ${OUT} >>${TMP} +cp ${TMP} ${OUT} + +# Temporarily convert newlines to do some mangling across lines +tr "\n" "\r" <${OUT} >${TMP} + +# Cleanup empty loops. E.g.: +# |while (e) {| +# | | ==> |while (e)| +# | } | | ; | +# | | +sed -i -r 's| \{\r+(\t*)\}\r\r|\n\1\t;\n|g' ${TMP} + +# Remove empty line between variable declaration +sed -i -r 's|\r(\r\t(unsigned )?int )|\1|g' ${TMP} + +# Remove empty lines at function beginning/end +sed -i -e 's|\r{\r\r|\r{\r|g' ${TMP} +sed -i -e 's|\r\r}\r|\r}\r|g' ${TMP} + +# Remove empty lines after '{' line +sed -i -e 's| {\r\r| {\r|g' ${TMP} + +# Remove braces {} around single statement blocks. E.g.: +# | while (e) { | | while (e) | +# | stg(); | => | stg();| +# | } | +sed -i -r 's| \{(\r[^\r]*;)\r\t*\}|\1|g' ${TMP} + +# Remove Unnecessary parentheses around 'n_code <= 0x3C' and similar. E.g.: +# if ((p_code >= 0x26) && ...) -> if (p_code >= 0x26 && ...) +sed -i -r 's|\((._code .= [x[:xdigit:]]+)\)|\1|g' ${TMP} + +# Convert back newlines +tr "\r" "\n" <${TMP} >${OUT} + +rm ${TMP} |
