diff options
134 files changed, 2900 insertions, 759 deletions
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index c5aa41a0e6..0ba3dad8cc 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -143,15 +143,12 @@ void __efi_runtime EFIAPI efi_reset_system( efi_status_t reset_status, unsigned long data_size, void *reset_data) { - switch (reset_type) { - case EFI_RESET_COLD: - case EFI_RESET_WARM: - case EFI_RESET_PLATFORM_SPECIFIC: + if (reset_type == EFI_RESET_COLD || + reset_type == EFI_RESET_WARM || + reset_type == EFI_RESET_PLATFORM_SPECIFIC) { psci_system_reset(); - break; - case EFI_RESET_SHUTDOWN: + } else if (reset_type == EFI_RESET_SHUTDOWN) { psci_system_off(); - break; } while (1) { } diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index e122be59c7..1279dc8658 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -212,8 +212,12 @@ static int zynqmp_mmio_rawwrite(const u32 address, { u32 data; u32 value_local = value; + int ret; + + ret = zynqmp_mmio_read(address, &data); + if (ret) + return ret; - zynqmp_mmio_read(address, &data); data &= ~mask; value_local &= mask; value_local |= data; diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 078c21b401..493652ea8c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -147,7 +147,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zturn.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ - zynqmp-mini-emmc.dtb \ + zynqmp-mini-emmc0.dtb \ + zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi index 00da3f2c40..ca294914bb 100644 --- a/arch/arm/dts/am3517.dtsi +++ b/arch/arm/dts/am3517.dtsi @@ -26,7 +26,7 @@ interrupt-names = "mc"; }; - davinci_emac: ethernet@0x5c000000 { + davinci_emac: ethernet@5c000000 { compatible = "ti,am3517-emac"; ti,hwmods = "davinci_emac"; status = "disabled"; @@ -41,7 +41,7 @@ local-mac-address = [ 00 00 00 00 00 00 ]; }; - davinci_mdio: ethernet@0x5c030000 { + davinci_mdio: ethernet@5c030000 { compatible = "ti,davinci_mdio"; ti,hwmods = "davinci_mdio"; status = "disabled"; @@ -99,9 +99,5 @@ status = "disabled"; }; -&smartreflex_mpu_iva { - status = "disabled"; -}; - /include/ "am35xx-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi index 4ee2e79514..3c31e21cbe 100644 --- a/arch/arm/dts/meson-gx.dtsi +++ b/arch/arm/dts/meson-gx.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber * @@ -6,44 +7,6 @@ * * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> @@ -169,6 +132,7 @@ compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; #address-cells = <1>; #size-cells = <1>; + read-only; sn: sn@14 { reg = <0x14 0x10>; diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts index ee4ada61c5..54954b314a 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2.dts +++ b/arch/arm/dts/meson-gxbb-odroidc2.dts @@ -1,45 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber * Copyright (c) 2016 BayLibre, Inc. * Author: Kevin Hilman <khilman@kernel.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -53,6 +16,7 @@ aliases { serial0 = &uart_AO; + ethernet0 = ðmac; }; chosen { @@ -310,7 +274,7 @@ pinctrl-names = "default", "clk-gate"; bus-width = <8>; - max-frequency = <200000000>; + max-frequency = <100000000>; non-removable; disable-wp; cap-mmc-highspeed; diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi index 3290a4dc35..562c26a0ba 100644 --- a/arch/arm/dts/meson-gxbb.dtsi +++ b/arch/arm/dts/meson-gxbb.dtsi @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Andreas Färber - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "meson-gx.dtsi" @@ -284,14 +247,17 @@ * MALI_0 and MALI_1 muxed to a single clock by a glitch * free mux to safely change frequency while running. */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + assigned-clocks = <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_MALI_0_SEL>, <&clkc CLKID_MALI_0>, <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + assigned-clock-parents = <0>, /* Do Nothing */ + <&clkc CLKID_GP0_PLL>, <0>, /* Do Nothing */ <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, + assigned-clock-rates = <744000000>, + <0>, /* Do Nothing */ + <744000000>, <0>; /* Do Nothing */ }; }; diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi index f825506cdf..eb327664a4 100644 --- a/arch/arm/dts/meson-gxl-mali.dtsi +++ b/arch/arm/dts/meson-gxl-mali.dtsi @@ -29,14 +29,17 @@ * MALI_0 and MALI_1 muxed to a single clock by a glitch * free mux to safely change frequency while running. */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + assigned-clocks = <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_MALI_0_SEL>, <&clkc CLKID_MALI_0>, <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + assigned-clock-parents = <0>, /* Do Nothing */ + <&clkc CLKID_GP0_PLL>, <0>, /* Do Nothing */ <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, + assigned-clock-rates = <744000000>, + <0>, /* Do Nothing */ + <744000000>, <0>; /* Do Nothing */ }; }; diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts index c3515599ed..d32cf38463 100644 --- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts @@ -28,6 +28,7 @@ aliases { serial2 = &uart_AO_B; + ethernet0 = ðmac; }; gpio-keys-polled { diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts index 9139761c79..3e3eb31748 100644 --- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts @@ -17,6 +17,7 @@ aliases { serial0 = &uart_AO; + ethernet0 = ðmac; }; chosen { @@ -270,3 +271,15 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +&usb0 { + status = "okay"; +}; + +&usb2_phy0 { + /* + * even though the schematics don't show it: + * HDMI_5V is also used as supply for the USB VBUS. + */ + phy-supply = <&hdmi_5v>; +}; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts index 6e2bf85829..5896e8a5d8 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dts +++ b/arch/arm/dts/meson-gxl-s905x-p212.dts @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi index 2db1377819..0cfd701809 100644 --- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi +++ b/arch/arm/dts/meson-gxl-s905x-p212.dtsi @@ -16,6 +16,7 @@ aliases { serial0 = &uart_AO; serial1 = &uart_A; + ethernet0 = ðmac; }; chosen { @@ -184,3 +185,7 @@ pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; }; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-gxl-s905x.dtsi b/arch/arm/dts/meson-gxl-s905x.dtsi index 3314a0b3da..40c19f69e9 100644 --- a/arch/arm/dts/meson-gxl-s905x.dtsi +++ b/arch/arm/dts/meson-gxl-s905x.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "meson-gxl.dtsi" diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi index c8514110b9..dba365ed4b 100644 --- a/arch/arm/dts/meson-gxl.dtsi +++ b/arch/arm/dts/meson-gxl.dtsi @@ -1,44 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione <carlo@endlessm.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "meson-gx.dtsi" @@ -57,6 +20,67 @@ no-map; }; }; + + soc { + usb0: usb@c9000000 { + status = "disabled"; + compatible = "amlogic,meson-gxl-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc CLKID_USB>; + clock-names = "usb_general"; + resets = <&reset RESET_USB_OTG>; + reset-names = "usb_otg"; + + dwc3: dwc3@c9000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xc9000000 0x0 0x100000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>; + }; + }; + }; +}; + +&apb { + usb2_phy0: phy@78000 { + compatible = "amlogic,meson-gxl-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0x78000 0x0 0x20>; + clocks = <&clkc CLKID_USB>; + clock-names = "phy"; + resets = <&reset RESET_USB_OTG>; + reset-names = "phy"; + status = "okay"; + }; + + usb2_phy1: phy@78020 { + compatible = "amlogic,meson-gxl-usb2-phy"; + #phy-cells = <0>; + reg = <0x0 0x78020 0x0 0x20>; + clocks = <&clkc CLKID_USB>; + clock-names = "phy"; + resets = <&reset RESET_USB_OTG>; + reset-names = "phy"; + status = "okay"; + }; + + usb3_phy: phy@78080 { + compatible = "amlogic,meson-gxl-usb3-phy"; + #phy-cells = <0>; + reg = <0x0 0x78080 0x0 0x20>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>; + clock-names = "phy", "peripheral"; + resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; + reset-names = "phy", "peripheral"; + status = "okay"; + }; }; ðmac { diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index bb224662bb..12e35618f8 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -30,8 +30,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw14 { label = "sw14"; diff --git a/arch/arm/dts/zynq-zturn.dts b/arch/arm/dts/zynq-zturn.dts index 8aa384b59b..cc41efcb46 100644 --- a/arch/arm/dts/zynq-zturn.dts +++ b/arch/arm/dts/zynq-zturn.dts @@ -49,8 +49,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; K1 { label = "K1"; diff --git a/arch/arm/dts/zynqmp-mini-emmc.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index e5b3c5fc78..24dd1ab9df 100644 --- a/arch/arm/dts/zynqmp-mini-emmc.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -18,7 +18,6 @@ aliases { serial0 = &dcc; mmc0 = &sdhci0; - mmc1 = &sdhci1; }; chosen { @@ -36,6 +35,12 @@ u-boot,dm-pre-reloc; }; + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + amba: amba { compatible = "simple-bus"; #address-cells = <2>; @@ -50,15 +55,6 @@ clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; }; - - sdhci1: sdhci@ff170000 { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - reg = <0x0 0xff170000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <1>; - }; }; }; @@ -69,7 +65,3 @@ &sdhci0 { status = "okay"; }; - -&sdhci1 { - status = "okay"; -}; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts new file mode 100644 index 0000000000..d1549b6dc6 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP Mini Configuration + * + * (C) Copyright 2018, Xilinx, Inc. + * + * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> + */ + +/dts-v1/; + +/ { + model = "ZynqMP MINI EMMC"; + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &dcc; + mmc0 = &sdhci1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; + }; + + clk_xin: clk_xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdhci1: sdhci@ff170000 { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0x0 0xff170000 0x0 0x1000>; + clock-names = "clk_xin", "clk_xin"; + xlnx,device_id = <1>; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index c6aaa08a00..6e575a063b 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -48,8 +48,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw4 { label = "sw4"; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index b7c638bc9e..ddc3fbae1f 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -45,8 +45,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw19 { label = "sw19"; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index bbcd26031d..a30268b7b1 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -45,8 +45,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw19 { label = "sw19"; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index aa9055b715..6c1a0f7a3b 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -45,8 +45,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; sw19 { label = "sw19"; diff --git a/arch/arm/mach-bcm283x/reset.c b/arch/arm/mach-bcm283x/reset.c index f8a17755e3..7712d4664c 100644 --- a/arch/arm/mach-bcm283x/reset.c +++ b/arch/arm/mach-bcm283x/reset.c @@ -59,13 +59,11 @@ void __efi_runtime EFIAPI efi_reset_system( { u32 val; - switch (reset_type) { - case EFI_RESET_COLD: - case EFI_RESET_WARM: - case EFI_RESET_PLATFORM_SPECIFIC: + if (reset_type == EFI_RESET_COLD || + reset_type == EFI_RESET_WARM || + reset_type == EFI_RESET_PLATFORM_SPECIFIC) { reset_cpu(0); - break; - case EFI_RESET_SHUTDOWN: + } else if (reset_type == EFI_RESET_SHUTDOWN) { /* * We set the watchdog hard reset bit here to distinguish this reset * from the normal (full) reset. bootcode.bin will not reboot after a @@ -76,7 +74,6 @@ void __efi_runtime EFIAPI efi_reset_system( val |= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT; writel(val, &wdog_regs->rsts); reset_cpu(0); - break; } while (1) { } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5c23b2cb57..18c7fb2d49 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -735,6 +735,12 @@ config I8259_PIC slave) interrupt controllers. Include this to have U-Boot set up the interrupt correctly. +config PINCTRL_ICH6 + bool + help + Intel ICH6 compatible chipset pinctrl driver. It needs to work + together with the ICH6 compatible gpio driver. + config I8254_TIMER bool default y diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index d5a17d08cf..af9e26caab 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -18,7 +18,8 @@ obj-y += cpu.o cpu_x86.o ifndef CONFIG_$(SPL_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) -AFLAGS_call32.o := -fpic -fshort-wchar +AFLAGS_call32.o := -fpic -fshort-wchar \ + $(if $(CONFIG_EFI_STUB_64BIT),-m64) extra-y += call32.o endif diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index ac58b03810..022a9f2e51 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -12,6 +12,7 @@ config INTEL_BAYTRAIL imply AHCI_PCI imply ICH_SPI imply INTEL_ICH6_GPIO + imply PINCTRL_ICH6 imply MMC imply MMC_PCI imply MMC_SDHCI diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 29baf087aa..56e98131d7 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -80,7 +80,7 @@ static void set_max_freq(void) perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; /* - * Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of + * Set guaranteed vid [22:16] from IACORE_VIDS to bits [7:0] of * the PERF_CTL */ msr = msr_read(MSR_IACORE_VIDS); diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index a5697a62a5..b35102a3f0 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -242,11 +242,6 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev, version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); -#if CONFIG_USBDEBUG - /* mrc.bin reconfigures USB, so reinit it to have debug */ - early_usbdebug_init(); -#endif - return 0; } diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 305cd3d237..3adc155818 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -16,16 +16,75 @@ DECLARE_GLOBAL_DATA_PTR; +/** + * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number + * + * @priv: IRQ router driver's priv data + * @reg: PIRQ routing register offset from the base address + * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) + */ +static inline int pirq_reg_to_linkno(struct irq_router *priv, int reg) +{ + int linkno = 0; + + if (priv->has_regmap) { + struct pirq_regmap *map = priv->regmap; + int i; + + for (i = 0; i < priv->link_num; i++) { + if (reg - priv->link_base == map->offset) { + linkno = map->link; + break; + } + map++; + } + } else { + linkno = reg - priv->link_base; + } + + return linkno; +} + +/** + * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset + * + * @priv: IRQ router driver's priv data + * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc) + * @return: PIRQ routing register offset from the base address + */ +static inline int pirq_linkno_to_reg(struct irq_router *priv, int linkno) +{ + int reg = 0; + + if (priv->has_regmap) { + struct pirq_regmap *map = priv->regmap; + int i; + + for (i = 0; i < priv->link_num; i++) { + if (linkno == map->link) { + reg = map->offset + priv->link_base; + break; + } + map++; + } + } else { + reg = linkno + priv->link_base; + } + + return reg; +} + bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq) { struct irq_router *priv = dev_get_priv(dev); u8 pirq; - int base = priv->link_base; if (priv->config == PIRQ_VIA_PCI) - dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq); + dm_pci_read_config8(dev->parent, + pirq_linkno_to_reg(priv, link), &pirq); else - pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base)); + pirq = readb((uintptr_t)priv->ibase + + pirq_linkno_to_reg(priv, link)); pirq &= 0xf; @@ -40,22 +99,23 @@ int pirq_translate_link(struct udevice *dev, int link) { struct irq_router *priv = dev_get_priv(dev); - return LINK_V2N(link, priv->link_base); + return pirq_reg_to_linkno(priv, link); } void pirq_assign_irq(struct udevice *dev, int link, u8 irq) { struct irq_router *priv = dev_get_priv(dev); - int base = priv->link_base; /* IRQ# 0/1/2/8/13 are reserved */ if (irq < 3 || irq == 8 || irq == 13) return; if (priv->config == PIRQ_VIA_PCI) - dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq); + dm_pci_write_config8(dev->parent, + pirq_linkno_to_reg(priv, link), irq); else - writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base)); + writeb(irq, (uintptr_t)priv->ibase + + pirq_linkno_to_reg(priv, link)); } static struct irq_info *check_dup_entry(struct irq_info *slot_base, @@ -78,7 +138,7 @@ static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot, { slot->bus = bus; slot->devfn = (device << 3) | 0; - slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base); + slot->irq[pin - 1].link = pirq_linkno_to_reg(priv, pirq); slot->irq[pin - 1].bitmap = priv->irq_mask; } @@ -89,6 +149,7 @@ static int create_pirq_routing_table(struct udevice *dev) int node; int len, count; const u32 *cell; + struct pirq_regmap *map; struct irq_routing_table *rt; struct irq_info *slot, *slot_base; int irq_entries = 0; @@ -112,10 +173,43 @@ static int create_pirq_routing_table(struct udevice *dev) return -EINVAL; } - ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1); - if (ret == -1) - return ret; - priv->link_base = ret; + cell = fdt_getprop(blob, node, "intel,pirq-link", &len); + if (!cell || len != 8) + return -EINVAL; + priv->link_base = fdt_addr_to_cpu(cell[0]); + priv->link_num = fdt_addr_to_cpu(cell[1]); + if (priv->link_num > CONFIG_MAX_PIRQ_LINKS) { + debug("Limiting supported PIRQ link number from %d to %d\n", + priv->link_num, CONFIG_MAX_PIRQ_LINKS); + priv->link_num = CONFIG_MAX_PIRQ_LINKS; + } + + cell = fdt_getprop(blob, node, "intel,pirq-regmap", &len); + if (cell) { + if (len % sizeof(struct pirq_regmap)) + return -EINVAL; + + count = len / sizeof(struct pirq_regmap); + if (count < priv->link_num) { + printf("Number of pirq-regmap entires is wrong\n"); + return -EINVAL; + } + + count = priv->link_num; + priv->regmap = calloc(count, sizeof(struct pirq_regmap)); + if (!priv->regmap) + return -ENOMEM; + + priv->has_regmap = true; + map = priv->regmap; + for (i = 0; i < count; i++) { + map->link = fdt_addr_to_cpu(cell[0]); + map->offset = fdt_addr_to_cpu(cell[1]); + + cell += sizeof(struct pirq_regmap) / sizeof(u32); + map++; + } + } priv->irq_mask = fdtdec_get_int(blob, node, "intel,pirq-mask", PIRQ_BITMAP); @@ -199,7 +293,7 @@ static int create_pirq_routing_table(struct udevice *dev) * routing information in the device tree. */ if (slot->irq[pr.pin - 1].link != - LINK_N2V(pr.pirq, priv->link_base)) + pirq_linkno_to_reg(priv, pr.pirq)) debug("WARNING: Inconsistent PIRQ routing information\n"); continue; } @@ -237,7 +331,7 @@ static void irq_enable_sci(struct udevice *dev) } } -int irq_router_common_init(struct udevice *dev) +int irq_router_probe(struct udevice *dev) { int ret; @@ -256,11 +350,6 @@ int irq_router_common_init(struct udevice *dev) return 0; } -int irq_router_probe(struct udevice *dev) -{ - return irq_router_common_init(dev); -} - ulong write_pirq_routing_table(ulong addr) { if (!gd->arch.pirq_routing_table) diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index 82d5489a17..5f0e60837c 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -13,11 +13,13 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE imply AHCI_PCI imply ICH_SPI imply INTEL_ICH6_GPIO + imply PINCTRL_ICH6 imply SCSI imply SCSI_AHCI imply SPI_FLASH imply USB imply USB_EHCI_HCD + imply USB_XHCI_HCD imply VIDEO_VESA if NORTHBRIDGE_INTEL_IVYBRIDGE diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 27cfb26317..716134e9ff 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -8,7 +8,6 @@ else obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o obj-y += early_me.o obj-y += lpc.o -obj-y += model_206ax.o obj-y += northbridge.o ifndef CONFIG_SPL_BUILD obj-y += sata.o @@ -18,4 +17,5 @@ ifndef CONFIG_$(SPL_)X86_32BIT_INIT obj-y += sdram_nop.o endif endif +obj-y += model_206ax.o obj-y += bd82x6x.o diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index c5441aafea..33e5c6263d 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -393,10 +393,6 @@ static void configure_mca(void) msr_write(IA32_MC0_STATUS + (i * 4), msr); } -#if CONFIG_USBDEBUG -static unsigned ehci_debug_addr; -#endif - static int model_206ax_init(struct udevice *dev) { int ret; @@ -404,17 +400,6 @@ static int model_206ax_init(struct udevice *dev) /* Clear out pending MCEs */ configure_mca(); -#if CONFIG_USBDEBUG - /* Is this caution really needed? */ - if (!ehci_debug_addr) - ehci_debug_addr = get_ehci_debug(); - set_ehci_debug(0); -#endif - -#if CONFIG_USBDEBUG - set_ehci_debug(ehci_debug_addr); -#endif - /* Enable the local cpu apics */ enable_lapic_tpr(); diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile index 476e37cfe5..7039f8b9b6 100644 --- a/arch/x86/cpu/quark/Makefile +++ b/arch/x86/cpu/quark/Makefile @@ -2,6 +2,6 @@ # # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> -obj-y += car.o dram.o irq.o msg_port.o quark.o +obj-y += car.o dram.o msg_port.o quark.o obj-y += mrc.o mrc_util.o hte.o smc.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c deleted file mode 100644 index 6928c33600..0000000000 --- a/arch/x86/cpu/quark/irq.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> - * Copyright (C) 2015 Google, Inc - */ - -#include <common.h> -#include <dm.h> -#include <asm/irq.h> -#include <asm/arch/device.h> -#include <asm/arch/quark.h> - -int quark_irq_router_probe(struct udevice *dev) -{ - struct quark_rcba *rcba; - u32 base; - - qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); - base &= ~MEM_BAR_EN; - rcba = (struct quark_rcba *)base; - - /* - * Route Quark PCI device interrupt pin to PIRQ - * - * Route device#23's INTA/B/C/D to PIRQA/B/C/D - * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H - */ - writew(PIRQC, &rcba->rmu_ir); - writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), - &rcba->d23_ir); - writew(PIRQD, &rcba->core_ir); - writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), - &rcba->d20d21_ir); - - return irq_router_common_init(dev); -} - -static const struct udevice_id quark_irq_router_ids[] = { - { .compatible = "intel,quark-irq-router" }, - { } -}; - -U_BOOT_DRIVER(quark_irq_router_drv) = { - .name = "quark_intel_irq", - .id = UCLASS_IRQ, - .of_match = quark_irq_router_ids, - .probe = quark_irq_router_probe, -}; diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 46141c434d..4fd686424d 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -7,6 +7,7 @@ #include <mmc.h> #include <asm/io.h> #include <asm/ioapic.h> +#include <asm/irq.h> #include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> @@ -313,12 +314,37 @@ static void quark_usb_init(void) writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); } +static void quark_irq_init(void) +{ + struct quark_rcba *rcba; + u32 base; + + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); + base &= ~MEM_BAR_EN; + rcba = (struct quark_rcba *)base; + + /* + * Route Quark PCI device interrupt pin to PIRQ + * + * Route device#23's INTA/B/C/D to PIRQA/B/C/D + * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H + */ + writew(PIRQC, &rcba->rmu_ir); + writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), + &rcba->d23_ir); + writew(PIRQD, &rcba->core_ir); + writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), + &rcba->d20d21_ir); +} + int arch_early_init_r(void) { quark_pcie_init(); quark_usb_init(); + quark_irq_init(); + return 0; } diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index b535b2a406..ac2961356b 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -2,5 +2,5 @@ # # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> -obj-y += fsp_configs.o irq.o +obj-y += fsp_configs.o obj-y += tnc.o diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c deleted file mode 100644 index 208cd61b55..0000000000 --- a/arch/x86/cpu/queensbay/irq.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * Copyright (C) 2015 Google, Inc - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/irq.h> -#include <asm/pci.h> -#include <asm/arch/device.h> -#include <asm/arch/tnc.h> - -int queensbay_irq_router_probe(struct udevice *dev) -{ - struct tnc_rcba *rcba; - u32 base; - - dm_pci_read_config32(dev->parent, LPC_RCBA, &base); - base &= ~MEM_BAR_EN; - rcba = (struct tnc_rcba *)base; - - /* Make sure all internal PCI devices are using INTA */ - writel(INTA, &rcba->d02ip); - writel(INTA, &rcba->d03ip); - writel(INTA, &rcba->d27ip); - writel(INTA, &rcba->d31ip); - writel(INTA, &rcba->d23ip); - writel(INTA, &rcba->d24ip); - writel(INTA, &rcba->d25ip); - writel(INTA, &rcba->d26ip); - - /* - * Route TunnelCreek PCI device interrupt pin to PIRQ - * - * Since PCIe downstream ports received INTx are routed to PIRQ - * A/B/C/D directly and not configurable, we have to route PCIe - * root ports' INTx to PIRQ A/B/C/D as well. For other devices - * on TunneCreek, route them to PIRQ E/F/G/H. - */ - writew(PIRQE, &rcba->d02ir); - writew(PIRQF, &rcba->d03ir); - writew(PIRQG, &rcba->d27ir); - writew(PIRQH, &rcba->d31ir); - writew(PIRQA, &rcba->d23ir); - writew(PIRQB, &rcba->d24ir); - writew(PIRQC, &rcba->d25ir); - writew(PIRQD, &rcba->d26ir); - - return irq_router_common_init(dev); -} - -static const struct udevice_id queensbay_irq_router_ids[] = { - { .compatible = "intel,queensbay-irq-router" }, - { } -}; - -U_BOOT_DRIVER(queensbay_irq_router_drv) = { - .name = "queensbay_intel_irq", - .id = UCLASS_IRQ, - .of_match = queensbay_irq_router_ids, - .probe = queensbay_irq_router_probe, -}; diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 439c14d8bc..76556fc7f7 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -98,6 +98,43 @@ int arch_cpu_init(void) return x86_cpu_init_f(); } +static void tnc_irq_init(void) +{ + struct tnc_rcba *rcba; + u32 base; + + pci_read_config32(TNC_LPC, LPC_RCBA, &base); + base &= ~MEM_BAR_EN; + rcba = (struct tnc_rcba *)base; + + /* Make sure all internal PCI devices are using INTA */ + writel(INTA, &rcba->d02ip); + writel(INTA, &rcba->d03ip); + writel(INTA, &rcba->d27ip); + writel(INTA, &rcba->d31ip); + writel(INTA, &rcba->d23ip); + writel(INTA, &rcba->d24ip); + writel(INTA, &rcba->d25ip); + writel(INTA, &rcba->d26ip); + + /* + * Route TunnelCreek PCI device interrupt pin to PIRQ + * + * Since PCIe downstream ports received INTx are routed to PIRQ + * A/B/C/D directly and not configurable, we have to route PCIe + * root ports' INTx to PIRQ A/B/C/D as well. For other devices + * on TunneCreek, route them to PIRQ E/F/G/H. + */ + writew(PIRQE, &rcba->d02ir); + writew(PIRQF, &rcba->d03ir); + writew(PIRQG, &rcba->d27ir); + writew(PIRQH, &rcba->d31ir); + writew(PIRQA, &rcba->d23ir); + writew(PIRQB, &rcba->d24ir); + writew(PIRQC, &rcba->d25ir); + writew(PIRQD, &rcba->d26ir); +} + int arch_early_init_r(void) { int ret = 0; @@ -106,5 +143,7 @@ int arch_early_init_r(void) ret = disable_igd(); #endif + tnc_irq_init(); + return ret; } diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index fab919a358..26b9f85a5d 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -26,14 +26,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - u-boot,dm-pre-reloc; cpu@0 { device_type = "cpu"; compatible = "intel,core-gen3"; reg = <0>; intel,apic-id = <0>; - u-boot,dm-pre-reloc; }; cpu@1 { @@ -41,7 +39,6 @@ compatible = "intel,core-gen3"; reg = <1>; intel,apic-id = <1>; - u-boot,dm-pre-reloc; }; cpu@2 { @@ -49,7 +46,6 @@ compatible = "intel,core-gen3"; reg = <2>; intel,apic-id = <2>; - u-boot,dm-pre-reloc; }; cpu@3 { @@ -57,7 +53,6 @@ compatible = "intel,core-gen3"; reg = <3>; intel,apic-id = <3>; - u-boot,dm-pre-reloc; }; }; diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts index ea836eec95..c1cda73d96 100644 --- a/arch/x86/dts/cougarcanyon2.dts +++ b/arch/x86/dts/cougarcanyon2.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/interrupt-router/intel-irq.h> + /include/ "skeleton.dtsi" /include/ "serial.dtsi" /include/ "keyboard.dtsi" @@ -27,6 +29,39 @@ stdout-path = "/serial"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,core-gen3"; + reg = <3>; + intel,apic-id = <3>; + }; + }; + microcode { update@0 { #include "microcode/m12306a2_00000008.dtsi" @@ -66,10 +101,56 @@ #address-cells = <1>; #size-cells = <1>; + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,actl-8bit; + intel,actl-addr = <0x44>; + intel,pirq-link = <0x60 8>; + intel,pirq-regmap = < + PIRQA 0 + PIRQB 1 + PIRQC 2 + PIRQD 3 + PIRQE 8 + PIRQF 9 + PIRQG 10 + PIRQH 11 + >; + intel,pirq-mask = <0xcee0>; + intel,pirq-routing = < + /* Panther Point PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 22, 1) INTB PIRQB + PCI_BDF(0, 22, 2) INTC PIRQC + PCI_BDF(0, 22, 3) INTD PIRQD + PCI_BDF(0, 25, 0) INTA PIRQA + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTB PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 28, 4) INTA PIRQA + PCI_BDF(0, 28, 5) INTB PIRQB + PCI_BDF(0, 28, 6) INTC PIRQC + PCI_BDF(0, 28, 7) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 31, 2) INTB PIRQB + PCI_BDF(0, 31, 3) INTC PIRQC + PCI_BDF(0, 31, 5) INTB PIRQB + PCI_BDF(0, 31, 6) INTC PIRQC + >; + }; + spi0: spi { #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + intel,spi-lock-down; + spi-flash@0 { reg = <0>; compatible = "winbond,w25q64bv", "spi-flash"; diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 4fe076a8e9..d8faa9d504 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -151,7 +151,7 @@ #size-cells = <1>; irq-router { - compatible = "intel,queensbay-irq-router"; + compatible = "intel,irq-router"; intel,pirq-config = "pci"; intel,actl-addr = <0x58>; intel,pirq-link = <0x60 8>; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index d86fdc06fd..3454abdd33 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -97,7 +97,7 @@ #size-cells = <1>; irq-router { - compatible = "intel,quark-irq-router"; + compatible = "intel,irq-router"; intel,pirq-config = "pci"; intel,actl-addr = <0x58>; intel,pirq-link = <0x60 8>; diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 169b2819ca..e5c916070c 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -22,6 +22,11 @@ enum pirq_config { PIRQ_VIA_IBASE }; +struct pirq_regmap { + int link; + int offset; +}; + /** * Intel interrupt router control block * @@ -29,6 +34,8 @@ enum pirq_config { * * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE * @link_base: link value base number + * @link_num: number of PIRQ links supported + * @has_regmap: has mapping table between PIRQ link and routing register offset * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding @@ -39,6 +46,9 @@ enum pirq_config { struct irq_router { int config; u32 link_base; + int link_num; + bool has_regmap; + struct pirq_regmap *regmap; u16 irq_mask; u32 bdf; u32 ibase; @@ -52,17 +62,6 @@ struct pirq_routing { int pirq; }; -/* PIRQ link number and value conversion */ -#define LINK_V2N(link, base) (link - base) -#define LINK_N2V(link, base) (link + base) - #define PIRQ_BITMAP 0xdef8 -/** - * irq_router_common_init() - Perform common x86 interrupt init - * - * This creates the PIRQ routing table and routes the IRQs - */ -int irq_router_common_init(struct udevice *dev); - #endif /* _ARCH_IRQ_H_ */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 5a64f6eddc..0e054da1e9 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o -obj-y += pinctrl_ich6.o +obj-$(CONFIG_PINCTRL_ICH6) += pinctrl_ich6.o obj-y += pirq_routing.o obj-y += relocate.o obj-y += physmem.o @@ -58,10 +58,10 @@ CFLAGS_reloc_ia32_efi.o += -fpic -fshort-wchar # When building for 64-bit we must remove the i386-specific flags CFLAGS_REMOVE_reloc_x86_64_efi.o += -mregparm=3 -march=i386 -m32 -CFLAGS_reloc_x86_64_efi.o += -fpic -fshort-wchar +CFLAGS_reloc_x86_64_efi.o += -fpic -fshort-wchar -m64 AFLAGS_REMOVE_crt0_x86_64_efi.o += -mregparm=3 -march=i386 -m32 -AFLAGS_crt0_x86_64_efi.o += -fpic -fshort-wchar +AFLAGS_crt0_x86_64_efi.o += -fpic -fshort-wchar -m64 extra-$(CONFIG_EFI_STUB_32BIT) += crt0_ia32_efi.o reloc_ia32_efi.o extra-$(CONFIG_EFI_STUB_64BIT) += crt0_x86_64_efi.o reloc_x86_64_efi.o diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index bcd3588818..da8be22085 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -37,20 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; #define CPGMACSS_SW_RST (1 << 1) #define PHY_GPIO 30 -/* This is only needed until SPL gets OF support */ -#ifdef CONFIG_SPL_BUILD -static const struct ns16550_platdata am3517_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(am3517_uart) = { - "ns16550_serial", - &am3517_serial -}; -#endif /* * Routine: board_init diff --git a/board/synopsys/hsdk/README b/board/synopsys/hsdk/README new file mode 100644 index 0000000000..e3793e4829 --- /dev/null +++ b/board/synopsys/hsdk/README @@ -0,0 +1,121 @@ +================================================================================ +Useful notes on bulding and using of U-Boot on ARC HS Development Kit (AKA HSDK) +================================================================================ + + BOARD OVERVIEW + + The DesignWare ARC HS Development Kit is a ready-to-use platform for rapid + software development on the ARC HS3x family of processors. + + For more information please visit: + https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit + + User guide is availalble here: + https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf + + It has the following features useful for U-Boot: + * On-board 2-channel FTDI TTL-to-USB converter + - The first channel is used for serial debug port (which makes it possible + to use a serial connection on pretty much any host machine be it + Windows, Linux or Mac). + On Linux machine typucally FTDI serial port would be /dev/ttyUSB0. + There's no HW flow-control and baud-rate is 115200. + + - The second channel is used for built-in Digilent USB JTAG probe. + That means no extra hardware is required to access ARC core from a + debugger on development host. Both proprietary MetaWare debugger and + open source OpenOCD + GDB client are supported. + + - Also with help of this FTDI chip it is possible to reset entire + board with help of a special `rff-ftdi-reset` utility, see: + https://github.com/foss-for-synopsys-dwc-arc-processors/rff-ftdi-reset + + * Micro SD-card slot + - U-Boot expects to see the very first partition on the card formatted as + FAT file-system and uses it for keeping its environment in `uboot.env` + file. Note uboot.env is not just a text file but it is auto-generated + file created by U-Boot on invocation of `saveenv` command. + It contains a checksum which makes this saved environment invalid in + case of maual modification. + + - There might be more useful files on that first FAT partition like + Linux kernl image in form of uImage (with or without built-in + initramfs), device tree blob (.dtb) etc. + + - Except FAT partition there might be others following the first FAT one + like Ext file-system with rootfs etc. + + * 1 Gb Ethernet socket + - U-Boot might get payload from TFTP server. This might be uImage, rootfs + image and anything else. + + * 2 MiB of SPI-flash + - SPI-flahs is used as a storage for image of an application auto-executed + by bootROM on power-on. Typically U-Boot gets programmed there but + there might be other uses. But note bootROM expects to find a special + header preceeding application image itself so before flashing anything + make sure required image is prepended. In case of U-Boot this is done + by invocation of `headerize-hsdk.py` with `make bsp-generate` command. + + + BUILDING U-BOOT + + 1. Configure U-Boot: + ------------------------->8---------------------- + make hsdk_defconfig + ------------------------->8---------------------- + + 2. To build Elf file (for example to be used with host debugger via JTAG + connection to the target board): + ------------------------->8---------------------- + make mdbtrick + ------------------------->8---------------------- + + This will produce `u-boot` Elf file. + + 3. To build artifacts required for U-Boot update in n-board SPI-flash: + ------------------------->8---------------------- + make bsp-generate + ------------------------->8---------------------- + + This will produce `u-boot.head` and `u-boot-update.scr` which should + be put on the first FAT partition of micro SD-card to be inserted in the + HSDK board. + + + EXECUTING U-BOOT + + 1. The HSDK board is supposed to auto-start U-Boot image stored in on-board + SPI-flash on power-on. For that make sure DIP-switches in the corner of + the board are in their default positions: BIM in 1:off, 2:on state + while both BMC and BCS should be in 1:on, 2:on state. + + 2. Though it is possible to load U-Boot as a simple Elf file via JTAG right + in DDR and start it from the debugger. + + 2.1. In case of proprietary MetaWare debugger run: + ------------------------->8---------------------- + mdb -digilent -run -cl u-boot + ------------------------->8---------------------- + + + UPDATION U-BOOT IMAGE IN ON-BOARD SPI-FLASH + + 1. Create `u-boot.head` and `u-boot-update.scr` as discribed above with + `make bsp-generate` command. + + 2. Copy `u-boot.head` and `u-boot-update.scr` to the first the first FAT + partition of micro SD-card. + + 3. Connect USB cable from the HSDK board to the developemnt host and + fire-up serial terminal. + + 3. Insert prepared micro SD-card in the HSDK board, press reset button + and stop auto-execution of existing `bootcmd` pressing any key in serial + terminal and enter the following command: + ------------------------->8---------------------- + mmc rescan && fatload mmc 0:1 ${loadaddr} u-boot-update.scr && source ${loadaddr} + ------------------------->8---------------------- + Wait before you see "u-boot update: OK" message. + + 4. Press RESET button and enjoy updated U-Boot version. diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk new file mode 100644 index 0000000000..16fb59c438 --- /dev/null +++ b/board/synopsys/hsdk/config.mk @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Synopsys, Inc. All rights reserved. + +bsp-generate: u-boot u-boot.bin + $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \ + --arc-id 0x52 --image $(srctree)/u-boot.bin \ + --elf $(srctree)/u-boot + $(Q)mkimage -T script -C none -n 'uboot update script' \ + -d $(srctree)/u-boot-update.txt \ + $(srctree)/u-boot-update.scr &> /dev/null diff --git a/board/synopsys/hsdk/headerize-hsdk.py b/board/synopsys/hsdk/headerize-hsdk.py new file mode 100644 index 0000000000..fce749723e --- /dev/null +++ b/board/synopsys/hsdk/headerize-hsdk.py @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Synopsys, Inc. All rights reserved. +# Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + +import os, getopt, sys, zlib +from elftools.elf.elffile import ELFFile + + +def usage(exit_code): + print("usage:") + print(sys.argv[0] + " --arc-id 0x52 --image u-boot.bin --elf u-boot") + sys.exit(exit_code) + + +def elf_get_entry(filename): + with open(filename, 'rb') as f: + elffile = ELFFile(f) + return elffile.header['e_entry'] + + +def calc_check_sum(filename): + # u-boot.head check_sum for preloader - it is sum of all u-boot binary bytes + with open(filename, "rb") as file: + ba = bytearray(file.read()) + return sum(ba) & 0xFF + + +def arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id): + if arc_id not in [0x52, 0x53]: + print("unknown ARC ID: " + hex(arc_id)) + sys.exit(2) + + if not os.path.isfile(uboot_bin_filename): + print("uboot bin file not exists: " + uboot_bin_filename) + sys.exit(2) + + if not os.path.isfile(uboot_elf_filename): + print("uboot elf file not exists: " + uboot_elf_filename) + sys.exit(2) + + +def main(): + try: + opts, args = getopt.getopt(sys.argv[1:], + "ha:i:l:e:", ["help", "arc-id=", "image=", "elf="]) + except getopt.GetoptError as err: + print(err) + usage(2) + + # default filenames + uboot_elf_filename = "u-boot" + uboot_bin_filename = "u-boot.bin" + headerised_filename = "u-boot.head" + uboot_scrypt_file = "u-boot-update.txt" + + # initial header values: place where preloader will store u-boot binary, + # should be equal to CONFIG_SYS_TEXT_BASE + image_copy_adr = 0x81000000 + + # initial constant header values, do not change these values + arc_id = 0x52 # 0x52 for 1st HSDK release (hardcoded in RTL) + magic1 = 0xdeadbeafaf # big endian byte order + flash_address = 0x0 + flash_type = 0x0 # 0 - SPI flash, 1 - NOR flash + magic2 = [ # big endian byte order + 0x20202a2020202020202020202a20202020207c5c2e20202020202e2f7c20202020207c2d, + 0x2e5c2020202f2e2d7c20202020205c2020602d2d2d6020202f20202020202f205f202020, + 0x205f20205c20202020207c205f60712070205f207c2020202020272e5f3d2f205c3d5f2e, + 0x272020202020202020605c202f60202020202020202020202020206f2020202020202020] + + for opt, arg in opts: + if opt in ('-h', "--help"): usage(0) + if opt in ('-a', "--arc-id"): arc_id = int(arg, 16) + if opt in ('-i', "--image"): uboot_bin_filename = arg + if opt in ('-e', "--elf"): uboot_elf_filename = arg + + arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id) + + uboot_img_size = os.path.getsize(uboot_bin_filename) + jump_address = elf_get_entry(uboot_elf_filename) + check_sum = calc_check_sum(uboot_bin_filename) + + # write header to file + with open(headerised_filename, "wb") as file: + file.write(arc_id.to_bytes(2, byteorder='little')) + file.write(uboot_img_size.to_bytes(4, byteorder='little')) + file.write(check_sum.to_bytes(1, byteorder='little')) + file.write(image_copy_adr.to_bytes(4, byteorder='little')) + file.write(magic1.to_bytes(5, byteorder='big')) + file.write(jump_address.to_bytes(4, byteorder='little')) + for i in range(12): file.write(0xFF.to_bytes(1, byteorder='little')) + for byte in magic2: file.write(byte.to_bytes(36, byteorder='big')) + for i in range(208 - len(magic2) * 36): + file.write(0xFF.to_bytes(1, byteorder='little')) + file.write(flash_address.to_bytes(4, byteorder='little')) + for i in range(11): file.write(0xFF.to_bytes(1, byteorder='little')) + file.write(flash_type.to_bytes(1, byteorder='little')) + + # append u-boot image to header + with open(headerised_filename, "ab") as fo: + with open(uboot_bin_filename,'rb') as fi: + fo.write(fi.read()) + + # calc u-boot headerized image CRC32 (will be used by uboot update + # command for check) + headerised_image_crc = "" + with open(headerised_filename, "rb") as fi: + headerised_image_crc = hex(zlib.crc32(fi.read()) & 0xffffffff) + + load_addr = 0x81000000 + crc_store_adr = load_addr - 0x8 + crc_calc_adr = crc_store_adr - 0x4 + load_size = os.path.getsize(headerised_filename) + crc_calc_cmd = \ + "crc32 " + hex(load_addr) + " " + hex(load_size) + " " + hex(crc_calc_adr) + crc_check_cmd = \ + "mw.l " + hex(crc_store_adr) + " " + headerised_image_crc + " && " + \ + crc_calc_cmd + " && " + \ + "cmp.l " + hex(crc_store_adr) + " " + hex(crc_calc_adr) + " 1" + + # make errase size to be allighned by 64K + if load_size & 0xFFFF == 0: + errase_size = load_size + else: + errase_size = load_size - (load_size & 0xFFFF) + 0x10000 + + # u-bood CMD to load u-bood with header to SPI flash + sf_load_image_cmd = \ + "fatload mmc 0:1 " + hex(load_addr) + " " + headerised_filename + " && " + \ + "sf probe 0:0 && " + \ + crc_check_cmd + " && " + \ + "sf protect unlock 0x0 " + hex(errase_size) + " && " + \ + "sf erase 0x0 " + hex(errase_size) + " && " + \ + "sf write " + hex(load_addr) + " 0x0 " + hex(load_size) + " && " + \ + "sf protect lock 0x0 " + hex(errase_size) + + update_uboot_cmd = sf_load_image_cmd + " && echo \"u-boot update: OK\"" + + with open(uboot_scrypt_file, "wb") as fo: + fo.write(update_uboot_cmd.encode('ascii')) + + +if __name__ == "__main__": + try: + main() + except Exception as err: + print(err) + sys.exit(2) diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index 4deaddc914..d4a15ae93d 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -196,7 +196,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */ {SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ {SPI2_D1, (M14 | PIN_INPUT_SLEW)}, /* spi2_d1.gpio7_15 */ {SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_d0.gpio7_16 */ @@ -481,7 +481,7 @@ const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = { {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ @@ -701,7 +701,7 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 72355e801b..f1f6bd5316 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -139,7 +139,7 @@ const struct pad_conf_entry dra72x_core_padconf_array_common[] = { {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ @@ -349,7 +349,7 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = { {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ {SPI1_CS1, (M14 | PIN_INPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ @@ -673,7 +673,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ @@ -858,8 +858,8 @@ const struct pad_conf_entry dra76x_core_padconf_array[] = { {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */ - {SPI1_CS2, (M6 | 0x000f0000)}, /* spi1_cs2.hdmi1_hpd */ - {SPI1_CS3, (M6 | 0x000f0000)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */ {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index e4f86d187a..1106f5c2a8 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -9,6 +9,7 @@ #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <watchdog.h> #include <wdt.h> #include <zynqpl.h> #include <asm/arch/hardware.h> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 080fb59ef7..81c10fcf8a 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -596,6 +596,8 @@ int board_late_init(void) new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + bootseq_len); + if (!new_targets) + return -ENOMEM; if (bootseq >= 0) sprintf(new_targets, "%s%x %s", mode, bootseq, diff --git a/cmd/Kconfig b/cmd/Kconfig index e283cb9a8a..1eb55e5250 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1219,6 +1219,7 @@ config CMD_DNS config CMD_LINK_LOCAL bool "linklocal" + select LIB_RAND help Acquire a network IP address using the link-local protocol diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 707d159bac..f55a40dc84 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -263,6 +263,7 @@ static efi_status_t do_bootefi_exec(void *efi, { struct efi_loaded_image loaded_image_info = {}; struct efi_object loaded_image_info_obj = {}; + struct efi_object mem_obj = {}; struct efi_device_path *memdp = NULL; efi_status_t ret; @@ -279,6 +280,12 @@ static efi_status_t do_bootefi_exec(void *efi, /* actual addresses filled in after efi_load_pe() */ memdp = efi_dp_from_mem(0, 0, 0); device_path = image_path = memdp; + efi_add_handle(&mem_obj); + + ret = efi_add_protocol(mem_obj.handle, &efi_guid_device_path, + device_path); + if (ret != EFI_SUCCESS) + goto exit; } else { assert(device_path && image_path); } @@ -343,6 +350,8 @@ static efi_status_t do_bootefi_exec(void *efi, exit: /* image has returned, loaded-image obj goes *poof*: */ list_del(&loaded_image_info_obj.link); + if (mem_obj.handle) + list_del(&mem_obj.link); return ret; } diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 11489b0123..ddc888a4fd 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -720,7 +720,7 @@ int env_get_f(const char *name, char *buf, unsigned len) /** * Decode the integer value of an environment variable and return it. * - * @param name Name of environemnt variable + * @param name Name of environment variable * @param base Number base to use (normally 10, or 16 for hex) * @param default_val Default value to return if the variable is not * found diff --git a/common/image.c b/common/image.c index 214ac33720..4f201289ee 100644 --- a/common/image.c +++ b/common/image.c @@ -1413,7 +1413,7 @@ int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images, * @cmd_end: pointer to a ulong variable, will hold cmdline end * * boot_get_cmdline() allocates space for kernel command line below - * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environemnt + * BOOTMAPSZ + env_get_bootm_low() address. If "bootargs" U-Boot environment * variable is present its contents is copied to allocated kernel * command line. * diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 431710a93b..1f1479718e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -334,7 +334,7 @@ config SPL_SAVEENV example OS may set "reboot_image" environment variable to "recovery" inorder to boot recovery image by SPL. The SPL read "reboot_image" and act accordingly and change the reboot_image - to default mode using setenv and save the environemnt. + to default mode using setenv and save the environment. config SPL_ETH_SUPPORT bool "Support Ethernet" diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 8a94fd3ce0..3b8e2900eb 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -30,6 +30,9 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1920k(u-boot),256k(u-boot-env),8m(kernel),512k(dtb),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y @@ -42,3 +45,4 @@ CONFIG_USB=y CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_AM35X=y CONFIG_BCH=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 6c79b77d06..eeee2521c6 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -3,13 +3,18 @@ CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2" CONFIG_TARGET_COUGARCANYON2=y +# CONFIG_HAVE_INTEL_ME is not set # CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_SMP=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y @@ -31,6 +36,7 @@ CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_CPU=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_USB_STORAGE=y diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig index 815b51e27a..a2f072b2f2 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_defconfig @@ -13,12 +13,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTM is not set -CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y # CONFIG_CMD_SF_TEST is not set -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y @@ -30,10 +26,10 @@ CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_OF_EMBED=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y # CONFIG_DM_ETH is not set CONFIG_DEBUG_EFI_CONSOLE=y -CONFIG_SPI=y -CONFIG_ICH_SPI=y # CONFIG_REGEX is not set CONFIG_EFI=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index a1ab39e3b7..ffb9693c10 100644 --- a/configs/xilinx_zynqmp_mini_emmc_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x10000 # CONFIG_CMD_ZYNQMP is not set -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc" +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_BOOTDELAY=-1 @@ -45,4 +45,5 @@ CONFIG_OF_EMBED=y # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig new file mode 100644 index 0000000000..edca32d28e --- /dev/null +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x10000 +# CONFIG_CMD_ZYNQMP is not set +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1" +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=-1 +CONFIG_SUPPORT_RAW_INITRD=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig index 52b3f75902..9e667ff7d5 100644 --- a/configs/xilinx_zynqmp_r5_defconfig +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -5,10 +5,12 @@ CONFIG_DEBUG_UART_BASE=0xff010000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5" CONFIG_DEBUG_UART=y +CONFIG_BOOTSTAGE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="ZynqMP r5> " # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_EMBED=y CONFIG_DEBUG_UART_ZYNQ=y CONFIG_ZYNQ_SERIAL=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 9b0f9dfdc0..49a14d87a8 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 8def1c5ea9..05dad41acb 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 618f1ed36f..b3711b43e8 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SDRAM=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y diff --git a/disk/part_efi.c b/disk/part_efi.c index 5c1039f013..2945892a24 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -23,6 +23,11 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * GUID for basic data partions. + */ +static const efi_guid_t partition_basic_data_guid = PARTITION_BASIC_DATA_GUID; + #ifdef CONFIG_HAVE_BLOCK_DEVICE /** * efi_crc32() - EFI version of crc32 function @@ -502,12 +507,12 @@ int gpt_fill_pte(struct blk_desc *dev_desc, } else { /* default partition type GUID */ memcpy(bin_type_guid, - &PARTITION_BASIC_DATA_GUID, 16); + &partition_basic_data_guid, 16); } #else /* partition type GUID */ memcpy(gpt_e[i].partition_type_guid.b, - &PARTITION_BASIC_DATA_GUID, 16); + &partition_basic_data_guid, 16); #endif #if CONFIG_IS_ENABLED(PARTITION_UUIDS) diff --git a/doc/README.x86 b/doc/README.x86 index 04f02202b4..78664c3d0a 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -256,7 +256,9 @@ the board manual. The SPI-0 flash should have flash descriptor plus ME firmware and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0 flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program this image to the SPI-0 flash according to the board manual just once and we are -all set. For programming U-Boot we just need to program SPI-1 flash. +all set. For programming U-Boot we just need to program SPI-1 flash. Since the +default u-boot.rom image for this board is set to 2MB, it should be programmed +to the last 2MB of the 8MB chip, address range [600000, 7FFFFF]. --- diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt index 04ad34654c..09e97b4300 100644 --- a/doc/device-tree-bindings/misc/intel,irq-router.txt +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt @@ -22,6 +22,12 @@ Required properties : - intel,pirq-link : Specifies the PIRQ link information with two cells. The first cell is the register offset that controls the first PIRQ link routing. The second cell is the total number of PIRQ links the router supports. +- intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links, + encoded as 2 cells a group for each link. The first cell is the PIRQ link + number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing + register offset from the interrupt router's base address. If this property + is omitted, it indicates a consecutive register offset from the first PIRQ + link, as specified by the first cell of intel,pirq-link. - intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the 8259 PIC. Bit N is 1 means IRQ N is available to be routed. - intel,pirq-routing : Specifies all PCI devices' IRQ routing information, diff --git a/doc/mvebu/cmd/bubt.txt b/doc/mvebu/cmd/bubt.txt index 6f9f525936..a539c15bcd 100644 --- a/doc/mvebu/cmd/bubt.txt +++ b/doc/mvebu/cmd/bubt.txt @@ -44,15 +44,6 @@ Notes: CONFIG_SYS_MMC_ENV_PART=1 Valid values for this parameter are 1 for BOOT0 and 2 for BOOT1. Please never use partition number 0 here! - The eMMC has 2 boot partitions (BOOT0 and BOOT1) and a user data partition (DATA). - The boot partitions are numbered as partition 1 and 2 in MMC driver. - Number 0 is used for user data partition and should not be utilized for storing - boot images and U-Boot environment in RAW mode since it will break file system - structures usually located here. - The default boot partition is BOOT0. It is selected by the following parameter: - CONFIG_SYS_MMC_ENV_PART=1 - Valid values for this parameter are 1 for BOOT0 and 2 for BOOT1. - Please never use partition number 0 here! - The partition number is ignored if the target device is SD card. - The boot image offset starts at block 0 for eMMC and block 1 for SD devices. The block 0 on SD devices is left for MBR storage. diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 9663294685..8d84e3fc13 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -111,9 +111,9 @@ struct zynq_gpio_privdata { struct zynq_platform_data { const char *label; u16 ngpio; - int max_bank; - int bank_min[ZYNQMP_GPIO_MAX_BANK]; - int bank_max[ZYNQMP_GPIO_MAX_BANK]; + u32 max_bank; + u32 bank_min[ZYNQMP_GPIO_MAX_BANK]; + u32 bank_max[ZYNQMP_GPIO_MAX_BANK]; }; static const struct zynq_platform_data zynqmp_gpio_def = { @@ -165,7 +165,7 @@ static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, struct udevice *dev) { struct zynq_gpio_privdata *priv = dev_get_priv(dev); - int bank; + u32 bank; for (bank = 0; bank < priv->p_data->max_bank; bank++) { if ((pin_num >= priv->p_data->bank_min[bank]) && @@ -188,7 +188,7 @@ static int gpio_is_valid(unsigned gpio, struct udevice *dev) { struct zynq_gpio_privdata *priv = dev_get_priv(dev); - return (gpio >= 0) && (gpio < priv->p_data->ngpio); + return gpio < priv->p_data->ngpio; } static int check_gpio(unsigned gpio, struct udevice *dev) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 40e28abda6..cdeba914f9 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -161,8 +161,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, /* We shouldn't wait for data inihibit for stop commands, even though they might use busy signaling */ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION || - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) + ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)) mask &= ~SDHCI_DATA_INHIBIT; while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { @@ -184,8 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); mask = SDHCI_INT_RESPONSE; - if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || - cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) + if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || + cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data) mask = SDHCI_INT_DATA_AVAIL; if (!(cmd->resp_type & MMC_RSP_PRESENT)) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 5b6d525608..b05334dfc8 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -92,7 +92,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) u32 ctrl; struct sdhci_host *host; struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); - u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; u8 deviceid; debug("%s\n", __func__); diff --git a/drivers/mtd/ubi/attach.c b/drivers/mtd/ubi/attach.c index ba40e58e51..b4ba339c80 100644 --- a/drivers/mtd/ubi/attach.c +++ b/drivers/mtd/ubi/attach.c @@ -789,7 +789,7 @@ static int check_corruption(struct ubi_device *ubi, struct ubi_vid_hdr *vid_hdr, ubi_dump_vid_hdr(vid_hdr); pr_err("hexdump of PEB %d offset %d, length %d", pnum, ubi->leb_start, ubi->leb_size); - ubi_dbg_print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + ubi_dbg_print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, ubi->peb_buf, ubi->leb_size, 1); err = 1; diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c index 412ea9f6f5..0a7427522c 100644 --- a/drivers/mtd/ubi/debug.c +++ b/drivers/mtd/ubi/debug.c @@ -5,6 +5,7 @@ * Author: Artem Bityutskiy (Битюцкий Артём) */ +#include <hexdump.h> #include <ubi_uboot.h> #include "ubi.h" #ifndef __UBOOT__ @@ -39,7 +40,7 @@ void ubi_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len) ubi_msg(ubi, "dumping %d bytes of data from PEB %d, offset %d", len, pnum, offset); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); out: vfree(buf); return; @@ -60,7 +61,7 @@ void ubi_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr) pr_err("\timage_seq %d\n", be32_to_cpu(ec_hdr->image_seq)); pr_err("\thdr_crc %#08x\n", be32_to_cpu(ec_hdr->hdr_crc)); pr_err("erase counter header hexdump:\n"); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, ec_hdr, UBI_EC_HDR_SIZE, 1); } @@ -85,7 +86,7 @@ void ubi_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr) (unsigned long long)be64_to_cpu(vid_hdr->sqnum)); pr_err("\thdr_crc %08x\n", be32_to_cpu(vid_hdr->hdr_crc)); pr_err("Volume identifier header hexdump:\n"); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, vid_hdr, UBI_VID_HDR_SIZE, 1); } diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h index 9b10fb9412..8ad0c62733 100644 --- a/drivers/mtd/ubi/debug.h +++ b/drivers/mtd/ubi/debug.h @@ -16,6 +16,8 @@ void ubi_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr); #include <linux/random.h> #endif +#include <hexdump.h> + #define ubi_assert(expr) do { \ if (unlikely(!(expr))) { \ pr_crit("UBI assert failed in %s at %u (pid %d)\n", \ @@ -24,8 +26,8 @@ void ubi_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr); } \ } while (0) -#define ubi_dbg_print_hex_dump(l, ps, pt, r, g, b, len, a) \ - print_hex_dump(l, ps, pt, r, g, b, len, a) +#define ubi_dbg_print_hex_dump(ps, pt, r, g, b, len, a) \ + print_hex_dump(ps, pt, r, g, b, len, a) #define ubi_dbg_msg(type, fmt, ...) \ pr_debug("UBI DBG " type " (pid %d): " fmt "\n", current->pid, \ diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index fc0a61fa79..8ef7823b37 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -78,6 +78,7 @@ #include <linux/err.h> #include <linux/slab.h> #else +#include <hexdump.h> #include <ubi_uboot.h> #endif @@ -1353,11 +1354,11 @@ static int self_check_write(struct ubi_device *ubi, const void *buf, int pnum, ubi_msg(ubi, "data differ at position %d", i); ubi_msg(ubi, "hex dump of the original buffer from %d to %d", i, i + dump_len); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, buf + i, dump_len, 1); ubi_msg(ubi, "hex dump of the read buffer from %d to %d", i, i + dump_len); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, buf1 + i, dump_len, 1); dump_stack(); err = -EINVAL; @@ -1419,7 +1420,7 @@ int ubi_self_check_all_ff(struct ubi_device *ubi, int pnum, int offset, int len) fail: ubi_err(ubi, "self-check failed for PEB %d", pnum); ubi_msg(ubi, "hex dump of the %d-%d region", offset, offset + len); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, buf, len, 1); err = -EINVAL; error: dump_stack(); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f2cc75f494..e88f056d84 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -362,6 +362,16 @@ config MPC8XX_FEC This driver implements support for the Fast Ethernet Controller on MPC8XX +config SNI_AVE + bool "Socionext AVE Ethernet support" + depends on DM_ETH && ARCH_UNIPHIER + select PHYLIB + select SYSCON + select REGMAP + help + This driver implements support for the Socionext AVE Ethernet + controller, as found on the Socionext UniPhier family. + config ETHER_ON_FEC1 bool "FEC1" depends on MPC8XX_FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 584bfdf2f9..058dd00768 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -70,3 +70,4 @@ obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ +obj-$(CONFIG_SNI_AVE) += sni_ave.o diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index e2395dbeb9..9919d3919f 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -910,8 +910,22 @@ out: return ret; } +static int cpsw_reap_completed_packets(struct cpsw_priv *priv) +{ + int timeout = CPDMA_TIMEOUT; + + /* reap completed packets */ + while (timeout-- && + (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0)) + ; + + return timeout; +} + static void _cpsw_halt(struct cpsw_priv *priv) { + cpsw_reap_completed_packets(priv); + writel(0, priv->dma_regs + CPDMA_TXCONTROL); writel(0, priv->dma_regs + CPDMA_RXCONTROL); @@ -925,18 +939,12 @@ static void _cpsw_halt(struct cpsw_priv *priv) static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) { - void *buffer; - int len; - int timeout = CPDMA_TIMEOUT; + int timeout; flush_dcache_range((unsigned long)packet, (unsigned long)packet + ALIGN(length, PKTALIGN)); - /* first reap completed packets */ - while (timeout-- && - (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0)) - ; - + timeout = cpsw_reap_completed_packets(priv); if (timeout == -1) { printf("cpdma_process timeout\n"); return -ETIMEDOUT; diff --git a/drivers/net/designware.c b/drivers/net/designware.c index cf125210d8..10a87096b7 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -280,6 +280,15 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); + /* + * When a MII PHY is used, we must set the PS bit for the DMA + * reset to succeed. + */ + if (priv->phydev->interface == PHY_INTERFACE_MODE_MII) + writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf); + else + writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf); + start = get_timer(0); while (readl(&dma_p->busmode) & DMAMAC_SRST) { if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 4e1aff6e3a..e6585ef8b3 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -15,6 +15,7 @@ #include <net.h> #include <malloc.h> #include <miiphy.h> +#include <wait_bit.h> #include <asm/io.h> #include <linux/errno.h> #include <asm/types.h> @@ -40,10 +41,24 @@ DECLARE_GLOBAL_DATA_PTR; #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +static int smi_wait_ready(struct mvgbe_device *dmvgbe) +{ + int ret; + + ret = wait_for_bit_le32(&MVGBE_SMI_REG, MVGBE_PHY_SMI_BUSY_MASK, false, + MVGBE_PHY_SMI_TIMEOUT_MS, false); + if (ret) { + printf("Error: SMI busy timeout\n"); + return ret; + } + + return 0; +} + /* * smi_reg_read - miiphy_read callback function. * - * Returns 16bit phy register value, or 0xffff on error + * Returns 16bit phy register value, or -EFAULT on error */ static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, int reg_ofs) @@ -74,16 +89,9 @@ static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, return -EFAULT; } - timeout = MVGBE_PHY_SMI_TIMEOUT; /* wait till the SMI is not busy */ - do { - /* read smi register */ - smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); - if (timeout-- == 0) { - printf("Err..(%s) SMI busy timeout\n", __func__); - return -EFAULT; - } - } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); + if (smi_wait_ready(dmvgbe) < 0) + return -EFAULT; /* fill the phy address and regiser offset and read opcode */ smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) @@ -119,10 +127,9 @@ static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, } /* - * smi_reg_write - imiiphy_write callback function. + * smi_reg_write - miiphy_write callback function. * - * Returns 0 if write succeed, -EINVAL on bad parameters - * -ETIME on timeout + * Returns 0 if write succeed, -EFAULT on error */ static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, int reg_ofs, u16 data) @@ -131,7 +138,6 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, struct mvgbe_device *dmvgbe = to_mvgbe(dev); struct mvgbe_registers *regs = dmvgbe->regs; u32 smi_reg; - u32 timeout; /* Phyadr write request*/ if (phy_adr == MV_PHY_ADR_REQUEST && @@ -147,19 +153,12 @@ static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, } if (reg_ofs > PHYREG_MASK) { printf("Err..(%s) Invalid register offset\n", __func__); - return -EINVAL; + return -EFAULT; } /* wait till the SMI is not busy */ - timeout = MVGBE_PHY_SMI_TIMEOUT; - do { - /* read smi register */ - smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); - if (timeout-- == 0) { - printf("Err..(%s) SMI busy timeout\n", __func__); - return -ETIME; - } - } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); + if (smi_wait_ready(dmvgbe) < 0) + return -EFAULT; /* fill the phy addr and reg offset and write opcode and data */ smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h index c20d1d7edf..1dc9bbea2f 100644 --- a/drivers/net/mvgbe.h +++ b/drivers/net/mvgbe.h @@ -216,6 +216,7 @@ /* SMI register fields */ #define MVGBE_PHY_SMI_TIMEOUT 10000 +#define MVGBE_PHY_SMI_TIMEOUT_MS 1000 #define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */ #define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS) #define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 7036b517b4..45e5eda955 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -1025,6 +1025,8 @@ static int mvneta_rxq_init(struct mvneta_port *pp, if (rxq->descs == NULL) return -ENOMEM; + WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN)); + rxq->last_desc = rxq->size - 1; /* Set Rx descriptors queue starting address */ @@ -1061,6 +1063,8 @@ static int mvneta_txq_init(struct mvneta_port *pp, if (txq->descs == NULL) return -ENOMEM; + WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN)); + txq->last_desc = txq->size - 1; /* Set maximum bandwidth for enabled TXQs */ @@ -1694,18 +1698,20 @@ static int mvneta_probe(struct udevice *dev) * be active. Make this area DMA safe by disabling the D-cache */ if (!buffer_loc.tx_descs) { + u32 size; + /* Align buffer area for descs and rx_buffers to 1MiB */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; + size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc), + ARCH_DMA_MINALIGN); buffer_loc.rx_descs = (struct mvneta_rx_desc *) - ((phys_addr_t)bd_space + - MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); - buffer_loc.rx_buffers = (phys_addr_t) - (bd_space + - MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + - MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); + ((phys_addr_t)bd_space + size); + size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc), + ARCH_DMA_MINALIGN); + buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size); } pp->base = (void __iomem *)pdata->iobase; diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 9b60d1aac5..a04a118f90 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -284,6 +284,38 @@ int cs4340_startup(struct phy_device *phydev) return 0; } +int cs4223_phy_init(struct phy_device *phydev) +{ + int reg_value; + + reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); + if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) { + printf("%s CS4223 Firmware not present in EERPOM\n", __func__); + return -ENOSYS; + } + + return 0; +} + +int cs4223_config(struct phy_device *phydev) +{ + return cs4223_phy_init(phydev); +} + +int cs4223_probe(struct phy_device *phydev) +{ + phydev->flags = PHY_FLAG_BROKEN_RESET; + return 0; +} + +int cs4223_startup(struct phy_device *phydev) +{ + phydev->link = 1; + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + return 0; +} + struct phy_driver cs4340_driver = { .name = "Cortina CS4315/CS4340", .uid = PHY_UID_CS4340, @@ -298,9 +330,23 @@ struct phy_driver cs4340_driver = { .shutdown = &gen10g_shutdown, }; +struct phy_driver cs4223_driver = { + .name = "Cortina CS4223", + .uid = PHY_UID_CS4223, + .mask = 0x0ffff00f, + .features = PHY_10G_FEATURES, + .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | + MDIO_DEVS_AN), + .config = &cs4223_config, + .probe = &cs4223_probe, + .startup = &cs4223_startup, + .shutdown = &gen10g_shutdown, +}; + int phy_cortina_init(void) { phy_register(&cs4340_driver); + phy_register(&cs4223_driver); return 0; } @@ -319,7 +365,7 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) return -EIO; *phy_id |= (phy_reg & 0xffff); - if (*phy_id == PHY_UID_CS4340) + if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223)) return 0; /* diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 17040bd6cc..ea54a15310 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -705,6 +705,31 @@ unforce: return res; } +static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) +{ + int val; + + val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); + if (val < 0) + return val; + + val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | + PORT_REG_PHYS_CTRL_FC_VALUE); + val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | + PORT_REG_PHYS_CTRL_PCS_AN_RST | + PORT_REG_PHYS_CTRL_FC_FORCE | + PORT_REG_PHYS_CTRL_DUPLEX_VALUE | + PORT_REG_PHYS_CTRL_DUPLEX_FORCE | + PORT_REG_PHYS_CTRL_SPD1000; + + if (port == CONFIG_MV88E61XX_CPU_PORT) + val |= PORT_REG_PHYS_CTRL_LINK_VALUE | + PORT_REG_PHYS_CTRL_LINK_FORCE; + + return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, + val); +} + static int mv88e61xx_set_cpu_port(struct phy_device *phydev) { int val; @@ -748,6 +773,11 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev) if (val < 0) return val; } + } else { + val = mv88e61xx_fixed_port_setup(phydev, + CONFIG_MV88E61XX_CPU_PORT); + if (val < 0) + return val; } return 0; @@ -810,27 +840,6 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) return 0; } -static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) -{ - int val; - - val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); - if (val < 0) - return val; - - val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | - PORT_REG_PHYS_CTRL_FC_VALUE); - val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | - PORT_REG_PHYS_CTRL_PCS_AN_RST | - PORT_REG_PHYS_CTRL_FC_FORCE | - PORT_REG_PHYS_CTRL_DUPLEX_VALUE | - PORT_REG_PHYS_CTRL_DUPLEX_FORCE | - PORT_REG_PHYS_CTRL_SPD1000; - - return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, - val); -} - static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) { int val; diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c new file mode 100644 index 0000000000..ba51ea5e38 --- /dev/null +++ b/drivers/net/sni_ave.c @@ -0,0 +1,995 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * sni_ave.c - Socionext UniPhier AVE ethernet driver + * Copyright 2016-2018 Socionext inc. + */ + +#include <clk.h> +#include <dm.h> +#include <fdt_support.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <miiphy.h> +#include <net.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> + +#define AVE_GRST_DELAY_MSEC 40 +#define AVE_MIN_XMITSIZE 60 +#define AVE_SEND_TIMEOUT_COUNT 1000 +#define AVE_MDIO_TIMEOUT_USEC 10000 +#define AVE_HALT_TIMEOUT_USEC 10000 + +/* General Register Group */ +#define AVE_IDR 0x000 /* ID */ +#define AVE_VR 0x004 /* Version */ +#define AVE_GRR 0x008 /* Global Reset */ +#define AVE_CFGR 0x00c /* Configuration */ + +/* Interrupt Register Group */ +#define AVE_GIMR 0x100 /* Global Interrupt Mask */ +#define AVE_GISR 0x104 /* Global Interrupt Status */ + +/* MAC Register Group */ +#define AVE_TXCR 0x200 /* TX Setup */ +#define AVE_RXCR 0x204 /* RX Setup */ +#define AVE_RXMAC1R 0x208 /* MAC address (lower) */ +#define AVE_RXMAC2R 0x20c /* MAC address (upper) */ +#define AVE_MDIOCTR 0x214 /* MDIO Control */ +#define AVE_MDIOAR 0x218 /* MDIO Address */ +#define AVE_MDIOWDR 0x21c /* MDIO Data */ +#define AVE_MDIOSR 0x220 /* MDIO Status */ +#define AVE_MDIORDR 0x224 /* MDIO Rd Data */ + +/* Descriptor Control Register Group */ +#define AVE_DESCC 0x300 /* Descriptor Control */ +#define AVE_TXDC 0x304 /* TX Descriptor Configuration */ +#define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */ +#define AVE_IIRQC 0x34c /* Interval IRQ Control */ + +/* 64bit descriptor memory */ +#define AVE_DESC_SIZE_64 12 /* Descriptor Size */ +#define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ +#define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ + +/* 32bit descriptor memory */ +#define AVE_DESC_SIZE_32 8 /* Descriptor Size */ +#define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ +#define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ + +/* RMII Bridge Register Group */ +#define AVE_RSTCTRL 0x8028 /* Reset control */ +#define AVE_RSTCTRL_RMIIRST BIT(16) +#define AVE_LINKSEL 0x8034 /* Link speed setting */ +#define AVE_LINKSEL_100M BIT(0) + +/* AVE_GRR */ +#define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ +#define AVE_GRR_GRST BIT(0) /* Reset all MAC */ + +/* AVE_CFGR */ +#define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ + +/* AVE_GISR (common with GIMR) */ +#define AVE_GIMR_CLR 0 +#define AVE_GISR_CLR GENMASK(31, 0) + +/* AVE_TXCR */ +#define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ +#define AVE_TXCR_TXSPD_1G BIT(17) +#define AVE_TXCR_TXSPD_100 BIT(16) + +/* AVE_RXCR */ +#define AVE_RXCR_RXEN BIT(30) /* Rx enable */ +#define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ +#define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ + +/* AVE_MDIOCTR */ +#define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ +#define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ + +/* AVE_MDIOSR */ +#define AVE_MDIOSR_STS BIT(0) /* access status */ + +/* AVE_DESCC */ +#define AVE_DESCC_RXDSTPSTS BIT(20) +#define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ +#define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */ +#define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ + +/* AVE_TXDC/RXDC */ +#define AVE_DESC_SIZE(priv, num) \ + ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \ + AVE_DESC_SIZE_32)) + +/* Command status for descriptor */ +#define AVE_STS_OWN BIT(31) /* Descriptor ownership */ +#define AVE_STS_OK BIT(27) /* Normal transmit */ +#define AVE_STS_1ST BIT(26) /* Head of buffer chain */ +#define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ +#define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) +#define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) + +#define AVE_DESC_OFS_CMDSTS 0 +#define AVE_DESC_OFS_ADDRL 4 +#define AVE_DESC_OFS_ADDRU 8 + +/* Parameter for ethernet frame */ +#define AVE_RXCR_MTU 1518 + +/* SG */ +#define SG_ETPINMODE 0x540 +#define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ +#define SG_ETPINMODE_RMII(ins) BIT(ins) + +#define AVE_MAX_CLKS 4 +#define AVE_MAX_RSTS 2 + +enum desc_id { + AVE_DESCID_TX, + AVE_DESCID_RX, +}; + +struct ave_private { + phys_addr_t iobase; + unsigned int nclks; + struct clk clk[AVE_MAX_CLKS]; + unsigned int nrsts; + struct reset_ctl rst[AVE_MAX_RSTS]; + struct regmap *regmap; + unsigned int regmap_arg; + + struct mii_dev *bus; + struct phy_device *phydev; + int phy_mode; + int max_speed; + + int rx_pos; + int rx_siz; + int rx_off; + int tx_num; + + u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN]; + void *tx_adj_buf; + + const struct ave_soc_data *data; +}; + +struct ave_soc_data { + bool is_desc_64bit; + const char *clock_names[AVE_MAX_CLKS]; + const char *reset_names[AVE_MAX_RSTS]; + int (*get_pinmode)(struct ave_private *priv); +}; + +static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry, + int offset) +{ + int desc_size; + u32 addr; + + if (priv->data->is_desc_64bit) { + desc_size = AVE_DESC_SIZE_64; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; + } else { + desc_size = AVE_DESC_SIZE_32; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; + } + + addr += entry * desc_size + offset; + + return readl(priv->iobase + addr); +} + +static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id, + int entry) +{ + return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS); +} + +static void ave_desc_write(struct ave_private *priv, enum desc_id id, + int entry, int offset, u32 val) +{ + int desc_size; + u32 addr; + + if (priv->data->is_desc_64bit) { + desc_size = AVE_DESC_SIZE_64; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; + } else { + desc_size = AVE_DESC_SIZE_32; + addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; + } + + addr += entry * desc_size + offset; + writel(val, priv->iobase + addr); +} + +static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id, + int entry, u32 val) +{ + ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val); +} + +static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id, + int entry, uintptr_t paddr) +{ + ave_desc_write(priv, id, entry, + AVE_DESC_OFS_ADDRL, lower_32_bits(paddr)); + if (priv->data->is_desc_64bit) + ave_desc_write(priv, id, entry, + AVE_DESC_OFS_ADDRU, upper_32_bits(paddr)); +} + +static void ave_cache_invalidate(uintptr_t vaddr, int len) +{ + invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), + roundup(vaddr + len, ARCH_DMA_MINALIGN)); +} + +static void ave_cache_flush(uintptr_t vaddr, int len) +{ + flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), + roundup(vaddr + len, ARCH_DMA_MINALIGN)); +} + +static int ave_mdiobus_read(struct mii_dev *bus, + int phyid, int devad, int regnum) +{ + struct ave_private *priv = bus->priv; + u32 mdioctl, mdiosr; + int ret; + + /* write address */ + writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); + + /* read request */ + mdioctl = readl(priv->iobase + AVE_MDIOCTR); + writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR); + + ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, + !(mdiosr & AVE_MDIOSR_STS), + AVE_MDIO_TIMEOUT_USEC); + if (ret) { + pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n", + priv->phydev->dev->name, phyid, regnum); + return ret; + } + + return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0); +} + +static int ave_mdiobus_write(struct mii_dev *bus, + int phyid, int devad, int regnum, u16 val) +{ + struct ave_private *priv = bus->priv; + u32 mdioctl, mdiosr; + int ret; + + /* write address */ + writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); + + /* write data */ + writel(val, priv->iobase + AVE_MDIOWDR); + + /* write request */ + mdioctl = readl(priv->iobase + AVE_MDIOCTR); + writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, + priv->iobase + AVE_MDIOCTR); + + ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, + !(mdiosr & AVE_MDIOSR_STS), + AVE_MDIO_TIMEOUT_USEC); + if (ret) + pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n", + priv->phydev->dev->name, phyid, regnum); + + return ret; +} + +static int ave_adjust_link(struct ave_private *priv) +{ + struct phy_device *phydev = priv->phydev; + struct eth_pdata *pdata = dev_get_platdata(phydev->dev); + u32 val, txcr, rxcr, rxcr_org; + u16 rmt_adv = 0, lcl_adv = 0; + u8 cap; + + /* set RGMII speed */ + val = readl(priv->iobase + AVE_TXCR); + val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); + + if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) + val |= AVE_TXCR_TXSPD_1G; + else if (phydev->speed == SPEED_100) + val |= AVE_TXCR_TXSPD_100; + + writel(val, priv->iobase + AVE_TXCR); + + /* set RMII speed (100M/10M only) */ + if (!phy_interface_is_rgmii(phydev)) { + val = readl(priv->iobase + AVE_LINKSEL); + if (phydev->speed == SPEED_10) + val &= ~AVE_LINKSEL_100M; + else + val |= AVE_LINKSEL_100M; + writel(val, priv->iobase + AVE_LINKSEL); + } + + /* check current RXCR/TXCR */ + rxcr = readl(priv->iobase + AVE_RXCR); + txcr = readl(priv->iobase + AVE_TXCR); + rxcr_org = rxcr; + + if (phydev->duplex) { + rxcr |= AVE_RXCR_FDUPEN; + + if (phydev->pause) + rmt_adv |= LPA_PAUSE_CAP; + if (phydev->asym_pause) + rmt_adv |= LPA_PAUSE_ASYM; + if (phydev->advertising & ADVERTISED_Pause) + lcl_adv |= ADVERTISE_PAUSE_CAP; + if (phydev->advertising & ADVERTISED_Asym_Pause) + lcl_adv |= ADVERTISE_PAUSE_ASYM; + + cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); + if (cap & FLOW_CTRL_TX) + txcr |= AVE_TXCR_FLOCTR; + else + txcr &= ~AVE_TXCR_FLOCTR; + if (cap & FLOW_CTRL_RX) + rxcr |= AVE_RXCR_FLOCTR; + else + rxcr &= ~AVE_RXCR_FLOCTR; + } else { + rxcr &= ~AVE_RXCR_FDUPEN; + rxcr &= ~AVE_RXCR_FLOCTR; + txcr &= ~AVE_TXCR_FLOCTR; + } + + if (rxcr_org != rxcr) { + /* disable Rx mac */ + writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR); + /* change and enable TX/Rx mac */ + writel(txcr, priv->iobase + AVE_TXCR); + writel(rxcr, priv->iobase + AVE_RXCR); + } + + pr_notice("%s: phy:%s speed:%d mac:%pM\n", + phydev->dev->name, phydev->drv->name, phydev->speed, + pdata->enetaddr); + + return phydev->link; +} + +static int ave_mdiobus_init(struct ave_private *priv, const char *name) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) + return -ENOMEM; + + bus->read = ave_mdiobus_read; + bus->write = ave_mdiobus_write; + snprintf(bus->name, sizeof(bus->name), "%s", name); + bus->priv = priv; + + return mdio_register(bus); +} + +static int ave_phy_init(struct ave_private *priv, void *dev) +{ + struct phy_device *phydev; + int mask = GENMASK(31, 0), ret; + + phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static void ave_stop(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + u32 val; + int ret; + + val = readl(priv->iobase + AVE_GRR); + if (val) + return; + + val = readl(priv->iobase + AVE_RXCR); + val &= ~AVE_RXCR_RXEN; + writel(val, priv->iobase + AVE_RXCR); + + writel(0, priv->iobase + AVE_DESCC); + ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val, + AVE_HALT_TIMEOUT_USEC); + if (ret) + pr_warn("%s: halt timeout\n", priv->phydev->dev->name); + + writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); + + phy_shutdown(priv->phydev); +} + +static void ave_reset(struct ave_private *priv) +{ + u32 val; + + /* reset RMII register */ + val = readl(priv->iobase + AVE_RSTCTRL); + val &= ~AVE_RSTCTRL_RMIIRST; + writel(val, priv->iobase + AVE_RSTCTRL); + + /* assert reset */ + writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR); + mdelay(AVE_GRST_DELAY_MSEC); + + /* 1st, negate PHY reset only */ + writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); + mdelay(AVE_GRST_DELAY_MSEC); + + /* negate reset */ + writel(0, priv->iobase + AVE_GRR); + mdelay(AVE_GRST_DELAY_MSEC); + + /* negate RMII register */ + val = readl(priv->iobase + AVE_RSTCTRL); + val |= AVE_RSTCTRL_RMIIRST; + writel(val, priv->iobase + AVE_RSTCTRL); +} + +static int ave_start(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + uintptr_t paddr; + u32 val; + int i; + + ave_reset(priv); + + priv->rx_pos = 0; + priv->rx_off = 2; /* RX data has 2byte offsets */ + priv->tx_num = 0; + priv->tx_adj_buf = + (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0], + PKTALIGN); + priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off); + + val = 0; + if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII) + val |= AVE_CFGR_MII; + writel(val, priv->iobase + AVE_CFGR); + + /* use one descriptor for Tx */ + writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC); + ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0); + ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0); + + /* use PKTBUFSRX descriptors for Rx */ + writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC); + for (i = 0; i < PKTBUFSRX; i++) { + paddr = (uintptr_t)net_rx_packets[i]; + ave_cache_flush(paddr, priv->rx_siz + priv->rx_off); + ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr); + ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz); + } + + writel(AVE_GISR_CLR, priv->iobase + AVE_GISR); + writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR); + + writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU, + priv->iobase + AVE_RXCR); + writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC); + + phy_startup(priv->phydev); + ave_adjust_link(priv); + + return 0; +} + +static int ave_write_hwaddr(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + u8 *mac = pdata->enetaddr; + + writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, + priv->iobase + AVE_RXMAC1R); + writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R); + + return 0; +} + +static int ave_send(struct udevice *dev, void *packet, int length) +{ + struct ave_private *priv = dev_get_priv(dev); + u32 val; + void *ptr = packet; + int count; + + /* adjust alignment for descriptor */ + if ((uintptr_t)ptr & 0x3) { + memcpy(priv->tx_adj_buf, (const void *)ptr, length); + ptr = priv->tx_adj_buf; + } + + /* padding for minimum length */ + if (length < AVE_MIN_XMITSIZE) { + memset(ptr + length, 0, AVE_MIN_XMITSIZE - length); + length = AVE_MIN_XMITSIZE; + } + + /* check ownership and wait for previous xmit done */ + count = AVE_SEND_TIMEOUT_COUNT; + do { + val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); + } while ((val & AVE_STS_OWN) && --count); + if (!count) + return -ETIMEDOUT; + + ave_cache_flush((uintptr_t)ptr, length); + ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr); + + val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | + (length & AVE_STS_PKTLEN_TX_MASK); + ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val); + priv->tx_num++; + + count = AVE_SEND_TIMEOUT_COUNT; + do { + val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); + } while ((val & AVE_STS_OWN) && --count); + if (!count) + return -ETIMEDOUT; + + if (!(val & AVE_STS_OK)) + pr_warn("%s: bad send packet status:%08x\n", + priv->phydev->dev->name, le32_to_cpu(val)); + + return 0; +} + +static int ave_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ave_private *priv = dev_get_priv(dev); + uchar *ptr; + int length = 0; + u32 cmdsts; + + while (1) { + cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX, + priv->rx_pos); + if (!(cmdsts & AVE_STS_OWN)) + /* hardware ownership, no received packets */ + return -EAGAIN; + + ptr = net_rx_packets[priv->rx_pos] + priv->rx_off; + if (cmdsts & AVE_STS_OK) + break; + + pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n", + priv->phydev->dev->name, priv->rx_pos, + le32_to_cpu(cmdsts), ptr); + } + + length = cmdsts & AVE_STS_PKTLEN_RX_MASK; + + /* invalidate after DMA is done */ + ave_cache_invalidate((uintptr_t)ptr, length); + *packetp = ptr; + + return length; +} + +static int ave_free_packet(struct udevice *dev, uchar *packet, int length) +{ + struct ave_private *priv = dev_get_priv(dev); + + ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos], + priv->rx_siz + priv->rx_off); + + ave_desc_write_cmdsts(priv, AVE_DESCID_RX, + priv->rx_pos, priv->rx_siz); + + if (++priv->rx_pos >= PKTBUFSRX) + priv->rx_pos = 0; + + return 0; +} + +static int ave_pro4_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 0) + return -EINVAL; + + mask = SG_ETPINMODE_RMII(0); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, ®); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_ld11_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 0) + return -EINVAL; + + mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_INTERNAL: + break; + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, ®); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_ld20_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 0) + return -EINVAL; + + mask = SG_ETPINMODE_RMII(0); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_RGMII: + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, ®); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_pxs3_get_pinmode(struct ave_private *priv) +{ + u32 reg, mask, val = 0; + + if (priv->regmap_arg > 1) + return -EINVAL; + + mask = SG_ETPINMODE_RMII(priv->regmap_arg); + + switch (priv->phy_mode) { + case PHY_INTERFACE_MODE_RMII: + val = SG_ETPINMODE_RMII(priv->regmap_arg); + break; + case PHY_INTERFACE_MODE_RGMII: + break; + default: + return -EINVAL; + } + + regmap_read(priv->regmap, SG_ETPINMODE, ®); + reg &= ~mask; + reg |= val; + regmap_write(priv->regmap, SG_ETPINMODE, reg); + + return 0; +} + +static int ave_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ave_private *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + const char *phy_mode; + const u32 *valp; + int ret, nc, nr; + const char *name; + + priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); + if (!priv->data) + return -EINVAL; + + pdata->iobase = devfdt_get_addr(dev); + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", + NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); + return -EINVAL; + } + + pdata->max_speed = 0; + valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", + NULL); + if (valp) + pdata->max_speed = fdt32_to_cpu(*valp); + + for (nc = 0; nc < AVE_MAX_CLKS; nc++) { + name = priv->data->clock_names[nc]; + if (!name) + break; + ret = clk_get_by_name(dev, name, &priv->clk[nc]); + if (ret) { + dev_err(dev, "Failed to get clocks property: %d\n", + ret); + goto out_clk_free; + } + priv->nclks++; + } + + for (nr = 0; nr < AVE_MAX_RSTS; nr++) { + name = priv->data->reset_names[nr]; + if (!name) + break; + ret = reset_get_by_name(dev, name, &priv->rst[nr]); + if (ret) { + dev_err(dev, "Failed to get resets property: %d\n", + ret); + goto out_reset_free; + } + priv->nrsts++; + } + + ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode", + NULL, 1, 0, &args); + if (ret) { + dev_err(dev, "Failed to get syscon-phy-mode property: %d\n", + ret); + goto out_reset_free; + } + + priv->regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(priv->regmap)) { + ret = PTR_ERR(priv->regmap); + dev_err(dev, "can't get syscon: %d\n", ret); + goto out_reset_free; + } + + if (args.args_count != 1) { + ret = -EINVAL; + dev_err(dev, "Invalid argument of syscon-phy-mode\n"); + goto out_reset_free; + } + + priv->regmap_arg = args.args[0]; + + return 0; + +out_reset_free: + while (--nr >= 0) + reset_free(&priv->rst[nr]); +out_clk_free: + while (--nc >= 0) + clk_free(&priv->clk[nc]); + + return ret; +} + +static int ave_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ave_private *priv = dev_get_priv(dev); + int ret, nc, nr; + + priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); + if (!priv->data) + return -EINVAL; + + priv->iobase = pdata->iobase; + priv->phy_mode = pdata->phy_interface; + priv->max_speed = pdata->max_speed; + + ret = priv->data->get_pinmode(priv); + if (ret) { + dev_err(dev, "Invalid phy-mode\n"); + return -EINVAL; + } + + for (nc = 0; nc < priv->nclks; nc++) { + ret = clk_enable(&priv->clk[nc]); + if (ret) { + dev_err(dev, "Failed to enable clk: %d\n", ret); + goto out_clk_release; + } + } + + for (nr = 0; nr < priv->nrsts; nr++) { + ret = reset_deassert(&priv->rst[nr]); + if (ret) { + dev_err(dev, "Failed to deassert reset: %d\n", ret); + goto out_reset_release; + } + } + + ave_reset(priv); + + ret = ave_mdiobus_init(priv, dev->name); + if (ret) { + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); + goto out_reset_release; + } + + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = ave_phy_init(priv, dev); + if (ret) { + dev_err(dev, "Failed to initialize phy: %d\n", ret); + goto out_mdiobus_release; + } + + return 0; + +out_mdiobus_release: + mdio_unregister(priv->bus); + mdio_free(priv->bus); +out_reset_release: + reset_release_all(priv->rst, nr); +out_clk_release: + clk_release_all(priv->clk, nc); + + return ret; +} + +static int ave_remove(struct udevice *dev) +{ + struct ave_private *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + reset_release_all(priv->rst, priv->nrsts); + clk_release_all(priv->clk, priv->nclks); + + return 0; +} + +static const struct eth_ops ave_ops = { + .start = ave_start, + .stop = ave_stop, + .send = ave_send, + .recv = ave_recv, + .free_pkt = ave_free_packet, + .write_hwaddr = ave_write_hwaddr, +}; + +static const struct ave_soc_data ave_pro4_data = { + .is_desc_64bit = false, + .clock_names = { + "gio", "ether", "ether-gb", "ether-phy", + }, + .reset_names = { + "gio", "ether", + }, + .get_pinmode = ave_pro4_get_pinmode, +}; + +static const struct ave_soc_data ave_pxs2_data = { + .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_pro4_get_pinmode, +}; + +static const struct ave_soc_data ave_ld11_data = { + .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_ld11_get_pinmode, +}; + +static const struct ave_soc_data ave_ld20_data = { + .is_desc_64bit = true, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_ld20_get_pinmode, +}; + +static const struct ave_soc_data ave_pxs3_data = { + .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, + .get_pinmode = ave_pxs3_get_pinmode, +}; + +static const struct udevice_id ave_ids[] = { + { + .compatible = "socionext,uniphier-pro4-ave4", + .data = (ulong)&ave_pro4_data, + }, + { + .compatible = "socionext,uniphier-pxs2-ave4", + .data = (ulong)&ave_pxs2_data, + }, + { + .compatible = "socionext,uniphier-ld11-ave4", + .data = (ulong)&ave_ld11_data, + }, + { + .compatible = "socionext,uniphier-ld20-ave4", + .data = (ulong)&ave_ld20_data, + }, + { + .compatible = "socionext,uniphier-pxs3-ave4", + .data = (ulong)&ave_pxs3_data, + }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(ave) = { + .name = "ave", + .id = UCLASS_ETH, + .of_match = ave_ids, + .probe = ave_probe, + .remove = ave_remove, + .ofdata_to_platdata = ave_ofdata_to_platdata, + .ops = &ave_ops, + .priv_auto_alloc_size = sizeof(struct ave_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index d20b808c12..8dbd3c50c1 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -334,8 +334,8 @@ static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr) enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16); enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16); - writel(enetaddr_hi, ®s->mac_a1); - writel(enetaddr_lo, ®s->mac_a0); + writel(enetaddr_hi, ®s->mac_a0); + writel(enetaddr_lo, ®s->mac_a1); return 0; } diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 37840420fa..03a46da2f8 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -796,8 +796,9 @@ int tsec_probe(struct udevice *dev) parent = ofnode_get_parent(phandle_args.node); if (ofnode_valid(parent)) { - int reg = ofnode_read_u32_default(parent, "reg", 0); - priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520); + int reg = ofnode_get_addr_index(parent, 0); + + priv->phyregs_sgmii = (struct tsec_mii_mng *)reg; } else { debug("No parent node for PHY?\n"); return -ENOENT; diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c index 5d196cfb3f..f17839c70f 100644 --- a/drivers/net/vsc9953.c +++ b/drivers/net/vsc9953.c @@ -2468,6 +2468,139 @@ void vsc9953_default_configuration(void) debug("VSC9953: failed to set default aggregation code mode\n"); } +static void vcap_entry2cache_init(u32 target, u32 entry_words) +{ + int i; + + for (i = 0; i < entry_words; i++) { + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_ENTRY_DAT(target, i)), 0x00); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_MASK_DAT(target, i)), 0xFF); + } + + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_TG_DAT(target)), 0x00); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(target)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(entry_words)); +} + +static void vcap_action2cache_init(u32 target, u32 action_words, + u32 counter_words) +{ + int i; + + for (i = 0; i < action_words; i++) + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_ACTION_DAT(target, i)), 0x00); + + for (i = 0; i < counter_words; i++) + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CACHE_CNT_DAT(target, i)), 0x00); +} + +static int vcap_cmd(u32 target, u16 ix, int cmd, int sel, int entry_count) +{ + u32 tgt = target; + u32 value = (VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(cmd) | + VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(ix) | + VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT); + + if ((sel & TCAM_SEL_ENTRY) && ix >= entry_count) + return CMD_RET_FAILURE; + + if (!(sel & TCAM_SEL_ENTRY)) + value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS; + + if (!(sel & TCAM_SEL_ACTION)) + value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS; + + if (!(sel & TCAM_SEL_COUNTER)) + value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS; + + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_UPDATE_CTRL(tgt)), value); + + do { + value = in_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_UPDATE_CTRL(tgt))); + + } while (value & VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT); + + return CMD_RET_SUCCESS; +} + +static void vsc9953_vcap_init(void) +{ + u32 tgt = VSC9953_ES0; + int cmd_ret; + + /* write entries */ + vcap_entry2cache_init(tgt, ENTRY_WORDS_ES0); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, + ENTRY_WORDS_ES0); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n", + __LINE__); + + /* write actions and counters */ + vcap_action2cache_init(tgt, BITS_TO_DWORD(ES0_ACT_WIDTH), + BITS_TO_DWORD(ES0_CNT_WIDTH)); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(tgt)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(ES0_ACT_COUNT)); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, + TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_ES0); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", + __LINE__); + + tgt = VSC9953_IS1; + + /* write entries */ + vcap_entry2cache_init(tgt, ENTRY_WORDS_IS1); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, + ENTRY_WORDS_IS1); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n", + __LINE__); + + /* write actions and counters */ + vcap_action2cache_init(tgt, BITS_TO_DWORD(IS1_ACT_WIDTH), + BITS_TO_DWORD(IS1_CNT_WIDTH)); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(tgt)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(IS1_ACT_COUNT)); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, + TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS1); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", + __LINE__); + + tgt = VSC9953_IS2; + + /* write entries */ + vcap_entry2cache_init(tgt, ENTRY_WORDS_IS2); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, + ENTRY_WORDS_IS2); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid selection: TCAM_SEL_ENTRY\n", + __LINE__); + + /* write actions and counters */ + vcap_action2cache_init(tgt, BITS_TO_DWORD(IS2_ACT_WIDTH), + BITS_TO_DWORD(IS2_CNT_WIDTH)); + out_le32((unsigned int *)(VSC9953_OFFSET + + VSC9953_VCAP_CFG_MV_CFG(tgt)), + VSC9953_VCAP_CFG_MV_CFG_SIZE(IS2_ACT_COUNT)); + cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, + TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS2); + if (cmd_ret != CMD_RET_SUCCESS) + debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", + __LINE__); +} + void vsc9953_init(bd_t *bis) { u32 i; @@ -2604,6 +2737,7 @@ void vsc9953_init(bd_t *bis) } } + vsc9953_vcap_init(); vsc9953_default_configuration(); #ifdef CONFIG_CMD_ETHSW diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a218c92314..a817f2e5d6 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -185,7 +185,7 @@ struct zynq_gem_priv { bool int_pcs; }; -static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, +static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u32 op, u16 *data) { u32 mgtcr; @@ -216,10 +216,10 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, return 0; } -static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, +static int phyread(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u16 *val) { - u32 ret; + int ret; ret = phy_setup_op(priv, phy_addr, regnum, ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); @@ -231,7 +231,7 @@ static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, return ret; } -static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, +static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u16 data) { debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, @@ -244,7 +244,7 @@ static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, static int phy_detection(struct udevice *dev) { int i; - u16 phyreg; + u16 phyreg = 0; struct zynq_gem_priv *priv = dev->priv; if (priv->phyaddr != -1) { @@ -633,10 +633,16 @@ static int zynq_gem_probe(struct udevice *dev) /* Align rxbuffers to ARCH_DMA_MINALIGN */ priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); + if (!priv->rxbuffers) + return -ENOMEM; + memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); /* Align bd_space to MMU_SECTION_SHIFT */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + if (!bd_space) + return -ENOMEM; + mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 1cd1e409e3..46e9c71bdf 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -810,8 +810,8 @@ error: return ret; } -static int decode_regions(struct pci_controller *hose, ofnode parent_node, - ofnode node) +static void decode_regions(struct pci_controller *hose, ofnode parent_node, + ofnode node) { int pci_addr_cells, addr_cells, size_cells; int cells_per_record; @@ -820,8 +820,11 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, int i; prop = ofnode_get_property(node, "ranges", &len); - if (!prop) - return -EINVAL; + if (!prop) { + debug("%s: Cannot decode regions\n", __func__); + return; + } + pci_addr_cells = ofnode_read_simple_addr_cells(node); addr_cells = ofnode_read_simple_addr_cells(parent_node); size_cells = ofnode_read_simple_size_cells(node); @@ -883,7 +886,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, bd_t *bd = gd->bd; if (!bd) - return 0; + return; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { if (bd->bi_dram[i].size) { @@ -908,13 +911,12 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); #endif - return 0; + return; } static int pci_uclass_pre_probe(struct udevice *bus) { struct pci_controller *hose; - int ret; debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name, bus->parent->name); @@ -923,12 +925,7 @@ static int pci_uclass_pre_probe(struct udevice *bus) /* For bridges, use the top-level PCI controller */ if (!device_is_on_pci_bus(bus)) { hose->ctlr = bus; - ret = decode_regions(hose, dev_ofnode(bus->parent), - dev_ofnode(bus)); - if (ret) { - debug("%s: Cannot decode regions\n", __func__); - return ret; - } + decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus)); } else { struct pci_controller *parent_hose; @@ -1185,6 +1182,11 @@ static int _dm_pci_bus_to_phys(struct udevice *ctlr, struct pci_region *res; int i; + if (hose->region_count == 0) { + *pa = bus_addr; + return 0; + } + for (i = 0; i < hose->region_count; i++) { res = &hose->regions[i]; @@ -1248,6 +1250,11 @@ int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, ctlr = pci_get_controller(dev); hose = dev_get_uclass_priv(ctlr); + if (hose->region_count == 0) { + *ba = phys_addr; + return 0; + } + for (i = 0; i < hose->region_count; i++) { res = &hose->regions[i]; diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 3650af2157..a191772ff0 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -15,14 +15,16 @@ #include <linux/compiler.h> #include <serial.h> -#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ -#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ -#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ +DECLARE_GLOBAL_DATA_PTR; -#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ -#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ -#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ -#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ +#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ +#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ +#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ + +#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ +#define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */ +#define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ +#define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ @@ -93,7 +95,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) return -EAGAIN; writel(c, ®s->tx_rx_fifo); @@ -101,7 +103,7 @@ static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) return 0; } -int zynq_serial_setbrg(struct udevice *dev, int baudrate) +static int zynq_serial_setbrg(struct udevice *dev, int baudrate) { struct zynq_uart_priv *priv = dev_get_priv(dev); unsigned long clock; @@ -137,6 +139,10 @@ static int zynq_serial_probe(struct udevice *dev) { struct zynq_uart_priv *priv = dev_get_priv(dev); + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + _uart_zynq_serial_init(priv->regs); return 0; diff --git a/drivers/timer/cadence-ttc.c b/drivers/timer/cadence-ttc.c index 3541e5c841..4125a078b3 100644 --- a/drivers/timer/cadence-ttc.c +++ b/drivers/timer/cadence-ttc.c @@ -31,6 +31,28 @@ struct cadence_ttc_priv { struct cadence_ttc_regs *regs; }; +#if CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{ + u64 ticks = 0; + u32 rate = 1; + u64 us; + int ret; + + ret = dm_timer_init(); + if (!ret) { + /* The timer is available */ + rate = timer_get_rate(gd->timer); + timer_get_count(gd->timer, &ticks); + } else { + return 0; + } + + us = (ticks * 1000) / rate; + return us; +} +#endif + static int cadence_ttc_get_count(struct udevice *dev, u64 *count) { struct cadence_ttc_priv *priv = dev_get_priv(dev); diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index c7fefd2031..cf869998bf 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -21,6 +21,17 @@ DECLARE_GLOBAL_DATA_PTR; +static unsigned long cpu_mhz_from_cpuid(void) +{ + if (gd->arch.x86_vendor != X86_VENDOR_INTEL) + return 0; + + if (cpuid_eax(0) < 0x16) + return 0; + + return cpuid_eax(0x16); +} + /* * According to Intel 64 and IA-32 System Programming Guide, * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be @@ -343,13 +354,21 @@ static void tsc_timer_ensure_setup(void) if (!gd->arch.clock_rate) { unsigned long fast_calibrate; + fast_calibrate = cpu_mhz_from_cpuid(); + if (fast_calibrate) + goto done; + fast_calibrate = cpu_mhz_from_msr(); - if (!fast_calibrate) { - fast_calibrate = quick_pit_calibrate(); - if (!fast_calibrate) - panic("TSC frequency is ZERO"); - } + if (fast_calibrate) + goto done; + + fast_calibrate = quick_pit_calibrate(); + if (fast_calibrate) + goto done; + + panic("TSC frequency is ZERO"); +done: gd->arch.clock_rate = fast_calibrate * 1000000; } } diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index c7348fcf4b..a3101afa0d 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -240,6 +240,7 @@ /* #define DUMP_MSGS */ #include <config.h> +#include <hexdump.h> #include <malloc.h> #include <common.h> #include <console.h> diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c index ce046e75a9..4bbd030aad 100644 --- a/drivers/usb/gadget/storage_common.c +++ b/drivers/usb/gadget/storage_common.c @@ -124,7 +124,7 @@ # define dump_msg(fsg, label, buf, length) do { \ if (length < 512) { \ DBG(fsg, "%s, length %u:\n", label, length); \ - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, \ + print_hex_dump("", DUMP_PREFIX_OFFSET, \ 16, 1, buf, length, 0); \ } \ } while (0) @@ -139,7 +139,7 @@ # ifdef VERBOSE_DEBUG # define dump_cdb(fsg) \ - print_hex_dump(KERN_DEBUG, "SCSI CDB: ", DUMP_PREFIX_NONE, \ + print_hex_dump("SCSI CDB: ", DUMP_PREFIX_NONE, \ 16, 1, (fsg)->cmnd, (fsg)->cmnd_size, 0) \ # else diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index e8fd6bf6ae..b995aef997 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -23,9 +23,8 @@ static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, hcor = (struct xhci_hcor *)((uintptr_t) hccr + HC_LENGTH(xhci_readl(&hccr->cr_capbase))); - debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", - (u32)hccr, (u32)hcor, - (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + debug("XHCI-PCI init hccr %p and hcor %p hc_length %d\n", + hccr, hcor, (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); *ret_hccr = hccr; *ret_hcor = hcor; diff --git a/env/Kconfig b/env/Kconfig index f403906b6f..8618376f25 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -3,6 +3,7 @@ menu "Environment" config ENV_IS_NOWHERE bool "Environment is not stored" depends on !ENV_IS_IN_EEPROM + depends on !ENV_IS_IN_EXT4 depends on !ENV_IS_IN_FAT depends on !ENV_IS_IN_FLASH depends on !ENV_IS_IN_MMC @@ -15,7 +16,7 @@ config ENV_IS_NOWHERE default y help Define this if you don't want to or can't have an environment stored - on a storage medium. In this case the environemnt will still exist + on a storage medium. In this case the environment will still exist while U-Boot is running, but once U-Boot exits it will not be stored. U-Boot will therefore always start up with a default environment. @@ -391,7 +392,7 @@ config ENV_FAT_DEVICE_AND_PART partition table then means device D. config ENV_FAT_FILE - string "Name of the FAT file to use for the environemnt" + string "Name of the FAT file to use for the environment" depends on ENV_IS_IN_FAT default "uboot.env" help @@ -423,7 +424,7 @@ config ENV_EXT4_DEVICE_AND_PART partition table then means device D. config ENV_EXT4_FILE - string "Name of the EXT4 file to use for the environemnt" + string "Name of the EXT4 file to use for the environment" depends on ENV_IS_IN_EXT4 default "uboot.env" help diff --git a/examples/api/Makefile b/examples/api/Makefile index 476ca7103c..ca4eb1f71a 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -32,6 +32,7 @@ OBJ-y += libgenwrap.o EXT_COBJ-y += lib/crc32.o EXT_COBJ-y += lib/ctype.o EXT_COBJ-y += lib/div64.o +EXT_COBJ-y += lib/hexdump.o EXT_COBJ-y += lib/string.o EXT_COBJ-y += lib/time.o EXT_COBJ-y += lib/vsprintf.o diff --git a/fs/btrfs/chunk-map.c b/fs/btrfs/chunk-map.c index b3b5ef7652..beb6a4bb92 100644 --- a/fs/btrfs/chunk-map.c +++ b/fs/btrfs/chunk-map.c @@ -158,7 +158,7 @@ int btrfs_read_chunk_tree(void) do { found_key = btrfs_path_leaf_key(&path); if (btrfs_comp_keys_type(&key, found_key)) - break; + continue; chunk = btrfs_path_item_ptr(&path, struct btrfs_chunk); btrfs_chunk_to_cpu(chunk); diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index ee84130703..782aa9a250 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -15,6 +15,8 @@ * various local functions of those subsystems. */ +#include <hexdump.h> + #ifndef __UBOOT__ #include <linux/module.h> #include <linux/debugfs.h> @@ -307,7 +309,7 @@ void ubifs_dump_node(const struct ubifs_info *c, const void *node) /* If the magic is incorrect, just hexdump the first bytes */ if (le32_to_cpu(ch->magic) != UBIFS_NODE_MAGIC) { pr_err("Not a node, first %zu bytes:", UBIFS_CH_SZ); - print_hex_dump(KERN_ERR, "", DUMP_PREFIX_OFFSET, 32, 1, + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1, (void *)node, UBIFS_CH_SZ, 1); return; } @@ -482,7 +484,7 @@ void ubifs_dump_node(const struct ubifs_info *c, const void *node) (int)le16_to_cpu(dn->compr_type)); pr_err("\tdata size %d\n", dlen); pr_err("\tdata:\n"); - print_hex_dump(KERN_ERR, "\t", DUMP_PREFIX_OFFSET, 32, 1, + print_hex_dump("\t", DUMP_PREFIX_OFFSET, 32, 1, (void *)&dn->data, dlen, 0); break; } diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 4a977ae8cb..8ff668eec6 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -16,6 +16,7 @@ */ #ifdef __UBOOT__ +#include <hexdump.h> #include <linux/err.h> #endif #include "ubifs.h" @@ -236,7 +237,7 @@ void ubifs_scanned_corruption(const struct ubifs_info *c, int lnum, int offs, if (len > 8192) len = 8192; ubifs_err(c, "first %d bytes from LEB %d:%d", len, lnum, offs); - print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 4, buf, len, 1); + print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 4, buf, len, 1); } /** diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 3684f4d6d6..5da053002e 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -62,6 +62,12 @@ #define CONFIG_ENV_SIZE SZ_16K #define CONFIG_EXTRA_ENV_SETTINGS \ + "upgrade=if mmc rescan && " \ + "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ + "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ + "\"Fail to upgrade.\n" \ + "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ + "; fi\0" \ "core_dccm_0=0x10\0" \ "core_dccm_1=0x6\0" \ "core_dccm_2=0x10\0" \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index f373b1e24e..dc4db2bec8 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -43,7 +43,7 @@ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #endif -/* Environemnt is in SPI flash */ +/* Environment is in SPI flash */ #if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET 0x40000 /* 256K */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index a59e88171f..5381ed1f45 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -25,23 +25,46 @@ #define CONFIG_MACH_TYPE MACH_TYPE_PCM051 /* set to negative value for no autoboot */ +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance"; "\ + "setenv bootpart " #instance":2 ; "\ + "run mmcboot\0" + +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel "=" \ + "run nandboot\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(MMC, mmc, 1) \ + func(LEGACY_MMC, legacy_mmc, 1) \ + func(NAND, nand, 0) + +#define CONFIG_BOOTCOMMAND \ + "run distro_bootcmd" + +#include <config_distro_bootcmd.h> + +#include <environment/ti/dfu.h> +#include <environment/ti/mmc.h> + #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80007fc0\0" \ - "fdtaddr=0x80000000\0" \ - "rdaddr=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ "bootfile=uImage\0" \ - "fdtfile=pcm051.dtb\0" \ + "fdtfile=am335x-wega-rdk.dtb\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ "bootenv=uEnv.txt\0" \ "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ @@ -57,31 +80,12 @@ "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ + "run args_mmc; " \ "bootm ${loadaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootscript; then " \ - "run bootscript;" \ - "else " \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ - "fi ;" \ - "fi;" \ + BOOTENV /* Clock Defines */ #define V_OSCK 25000000 /* Clock output from T2 */ diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index ca11b97c7c..ad6bc3d1bf 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -39,6 +39,9 @@ #define CONFIG_ZYNQ_EEPROM_BUS 5 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54 +#define CONFIG_SPD_EEPROM +#define CONFIG_DDR_SPD + #include <configs/xilinx_zynqmp.h> #endif /* __CONFIG_ZYNQMP_ZCU102_H */ diff --git a/include/cortina.h b/include/cortina.h index 4cb0985519..ba7fafe9c4 100644 --- a/include/cortina.h +++ b/include/cortina.h @@ -64,6 +64,10 @@ #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 +/* Cortina CS4223 */ +#define CS4223_EEPROM_STATUS 0x5001 +#define CS4223_EEPROM_FIRMWARE_LOADDONE 0x1 + #define mseq_edc_bist_done (0x1<<0) #define mseq_edc_bist_fail (0x1<<8) diff --git a/include/efi.h b/include/efi.h index 98bddbac1a..e30a3c51c6 100644 --- a/include/efi.h +++ b/include/efi.h @@ -89,12 +89,11 @@ typedef u64 efi_virtual_addr_t; typedef void *efi_handle_t; #define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ - ((efi_guid_t) \ {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \ ((a) >> 24) & 0xff, \ (b) & 0xff, ((b) >> 8) & 0xff, \ (c) & 0xff, ((c) >> 8) & 0xff, \ - (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }) + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } } /* Generic EFI table header */ struct efi_table_hdr { diff --git a/include/environment.h b/include/environment.h index 50c62c5645..70b7eda428 100644 --- a/include/environment.h +++ b/include/environment.h @@ -292,7 +292,7 @@ int env_import_redund(const char *buf1, int buf1_status, /** * env_get_char() - Get a character from the early environment * - * This reads from the pre-relocation environemnt + * This reads from the pre-relocation environment * * @index: Index of character to read (0 = first) * @return character read, or -ve on error diff --git a/include/fat.h b/include/fat.h index 7dada411e5..09e1423685 100644 --- a/include/fat.h +++ b/include/fat.h @@ -180,7 +180,7 @@ static inline u32 clust_to_sect(fsdata *fsdata, u32 clust) return fsdata->data_begin + clust * fsdata->clust_size; } -static inline u32 sect_to_clust(fsdata *fsdata, u32 sect) +static inline u32 sect_to_clust(fsdata *fsdata, int sect) { return (sect - fsdata->data_begin) / fsdata->clust_size; } diff --git a/include/hexdump.h b/include/hexdump.h new file mode 100644 index 0000000000..f7b76ff712 --- /dev/null +++ b/include/hexdump.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Synopsys, Inc. All rights reserved. + * + */ + +#ifndef HEXDUMP_H +#define HEXDUMP_H + +#include <linux/ctype.h> +#include <linux/types.h> + +enum { + DUMP_PREFIX_NONE, + DUMP_PREFIX_ADDRESS, + DUMP_PREFIX_OFFSET +}; + +extern const char hex_asc[]; +#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] +#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] + +static inline char *hex_byte_pack(char *buf, u8 byte) +{ + *buf++ = hex_asc_hi(byte); + *buf++ = hex_asc_lo(byte); + return buf; +} + +/** + * hex_to_bin - convert a hex digit to its real value + * @ch: ascii character represents hex digit + * + * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad + * input. + */ +static inline int hex_to_bin(char ch) +{ + if ((ch >= '0') && (ch <= '9')) + return ch - '0'; + ch = tolower(ch); + if ((ch >= 'a') && (ch <= 'f')) + return ch - 'a' + 10; + return -1; +} + +/** + * hex2bin - convert an ascii hexadecimal string to its binary representation + * @dst: binary result + * @src: ascii hexadecimal string + * @count: result length + * + * Return 0 on success, -1 in case of bad input. + */ +static inline int hex2bin(u8 *dst, const char *src, size_t count) +{ + while (count--) { + int hi = hex_to_bin(*src++); + int lo = hex_to_bin(*src++); + + if ((hi < 0) || (lo < 0)) + return -1; + + *dst++ = (hi << 4) | lo; + } + return 0; +} + +/** + * bin2hex - convert binary data to an ascii hexadecimal string + * @dst: ascii hexadecimal result + * @src: binary data + * @count: binary data length + */ +static inline char *bin2hex(char *dst, const void *src, size_t count) +{ + const unsigned char *_src = src; + + while (count--) + dst = hex_byte_pack(dst, *_src++); + return dst; +} + +int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, + char *linebuf, size_t linebuflen, bool ascii); +void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, + int groupsize, const void *buf, size_t len, bool ascii); +void print_hex_dump_bytes(const char *prefix_str, int prefix_type, + const void *buf, size_t len); + +#endif /* HEXDUMP_H */ diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h index cff850f850..8fae186d1a 100644 --- a/include/linux/byteorder/generic.h +++ b/include/linux/byteorder/generic.h @@ -1,10 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _LINUX_BYTEORDER_GENERIC_H #define _LINUX_BYTEORDER_GENERIC_H /* - * linux/byteorder_generic.h + * linux/byteorder/generic.h * Generic Byte-reordering support * + * The "... p" macros, like le64_to_cpup, can be used with pointers + * to unaligned data, but there will be a performance penalty on + * some architectures. Use get_unaligned for unaligned data. + * * Francois-Rene Rideau <fare@tunes.org> 19970707 * gathered all the good ideas from all asm-foo/byteorder.h into one file, * cleaned them up. @@ -78,12 +83,6 @@ * */ - -#if defined(__KERNEL__) -/* - * inside the kernel, we can use nicknames; - * outside of it, we must avoid POSIX namespace pollution... - */ #define cpu_to_le64 __cpu_to_le64 #define le64_to_cpu __le64_to_cpu #define cpu_to_le32 __cpu_to_le32 @@ -120,18 +119,8 @@ #define be32_to_cpus __be32_to_cpus #define cpu_to_be16s __cpu_to_be16s #define be16_to_cpus __be16_to_cpus -#endif - /* - * Handle ntohl and suches. These have various compatibility - * issues - like we want to give the prototype even though we - * also have a macro for them in case some strange program - * wants to take the address of the thing or something.. - * - * Note that these used to return a "long" in libc5, even though - * long is often 64-bit these days.. Thus the casts. - * * They have to be macros in order to do the constant folding * correctly - if the argument passed into a inline function * it is no longer constant according to gcc.. @@ -142,39 +131,77 @@ #undef htonl #undef htons -/* - * Do the prototypes. Somebody might want to take the - * address or some such sick thing.. - */ -#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) -extern __u32 ntohl(__u32); -extern __u32 htonl(__u32); -#else -extern unsigned long int ntohl(unsigned long int); -extern unsigned long int htonl(unsigned long int); -#endif -extern unsigned short int ntohs(unsigned short int); -extern unsigned short int htons(unsigned short int); - - -#if defined(__GNUC__) && (__GNUC__ >= 2) - #define ___htonl(x) __cpu_to_be32(x) #define ___htons(x) __cpu_to_be16(x) #define ___ntohl(x) __be32_to_cpu(x) #define ___ntohs(x) __be16_to_cpu(x) -#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) #define htonl(x) ___htonl(x) #define ntohl(x) ___ntohl(x) -#else -#define htonl(x) ((unsigned long)___htonl(x)) -#define ntohl(x) ((unsigned long)___ntohl(x)) -#endif #define htons(x) ___htons(x) #define ntohs(x) ___ntohs(x) -#endif /* OPTIMIZE */ +static inline void le16_add_cpu(__le16 *var, u16 val) +{ + *var = cpu_to_le16(le16_to_cpu(*var) + val); +} + +static inline void le32_add_cpu(__le32 *var, u32 val) +{ + *var = cpu_to_le32(le32_to_cpu(*var) + val); +} + +static inline void le64_add_cpu(__le64 *var, u64 val) +{ + *var = cpu_to_le64(le64_to_cpu(*var) + val); +} + +/* XXX: this stuff can be optimized */ +static inline void le32_to_cpu_array(u32 *buf, unsigned int words) +{ + while (words--) { + __le32_to_cpus(buf); + buf++; + } +} + +static inline void cpu_to_le32_array(u32 *buf, unsigned int words) +{ + while (words--) { + __cpu_to_le32s(buf); + buf++; + } +} + +static inline void be16_add_cpu(__be16 *var, u16 val) +{ + *var = cpu_to_be16(be16_to_cpu(*var) + val); +} + +static inline void be32_add_cpu(__be32 *var, u32 val) +{ + *var = cpu_to_be32(be32_to_cpu(*var) + val); +} + +static inline void be64_add_cpu(__be64 *var, u64 val) +{ + *var = cpu_to_be64(be64_to_cpu(*var) + val); +} + +static inline void cpu_to_be32_array(__be32 *dst, const u32 *src, size_t len) +{ + int i; + + for (i = 0; i < len; i++) + dst[i] = cpu_to_be32(src[i]); +} + +static inline void be32_to_cpu_array(u32 *dst, const __be32 *src, size_t len) +{ + int i; + for (i = 0; i < len; i++) + dst[i] = be32_to_cpu(src[i]); +} #endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/include/linux/compat.h b/include/linux/compat.h index 8711fe2b48..6e3feb64d2 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -193,7 +193,6 @@ typedef unsigned long blkcnt_t; #define init_waitqueue_head(...) do { } while (0) #define wait_event_interruptible(...) 0 #define wake_up_interruptible(...) do { } while (0) -#define print_hex_dump(...) do { } while (0) #define dump_stack(...) do { } while (0) #define task_pid_nr(x) 0 diff --git a/include/pe.h b/include/pe.h index d73eb142cb..36e1908b7e 100644 --- a/include/pe.h +++ b/include/pe.h @@ -201,10 +201,13 @@ typedef struct _IMAGE_RELOCATION #define IMAGE_REL_BASED_MIPS_JMPADDR 5 #define IMAGE_REL_BASED_ARM_MOV32A 5 /* yes, 5 too */ #define IMAGE_REL_BASED_ARM_MOV32 5 /* yes, 5 too */ +#define IMAGE_REL_BASED_RISCV_HI20 5 /* yes, 5 too */ #define IMAGE_REL_BASED_SECTION 6 #define IMAGE_REL_BASED_REL 7 #define IMAGE_REL_BASED_ARM_MOV32T 7 /* yes, 7 too */ #define IMAGE_REL_BASED_THUMB_MOV32 7 /* yes, 7 too */ +#define IMAGE_REL_BASED_RISCV_LOW12I 7 /* yes, 7 too */ +#define IMAGE_REL_BASED_RISCV_LOW12S 8 #define IMAGE_REL_BASED_MIPS_JMPADDR16 9 #define IMAGE_REL_BASED_IA64_IMM64 9 /* yes, 9 too */ #define IMAGE_REL_BASED_DIR64 10 diff --git a/include/phy.h b/include/phy.h index 52bf99717c..7c3fc5ce40 100644 --- a/include/phy.h +++ b/include/phy.h @@ -65,6 +65,7 @@ typedef enum { PHY_INTERFACE_MODE_XAUI, PHY_INTERFACE_MODE_RXAUI, PHY_INTERFACE_MODE_SFI, + PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_NONE, /* Must be last */ PHY_INTERFACE_MODE_COUNT, @@ -87,6 +88,7 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_XAUI] = "xaui", [PHY_INTERFACE_MODE_RXAUI] = "rxaui", [PHY_INTERFACE_MODE_SFI] = "sfi", + [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_NONE] = "", }; @@ -314,6 +316,7 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_CS4340 0x13e51002 +#define PHY_UID_CS4223 0x03e57003 #define PHY_UID_TN2020 0x00a19410 #endif diff --git a/include/vsc9953.h b/include/vsc9953.h index bb7f8ecde5..fe072da516 100644 --- a/include/vsc9953.h +++ b/include/vsc9953.h @@ -186,6 +186,76 @@ #define MIIMIND_OPR_PEND 0x00000004 +#define VSC9953_BITMASK(offset) ((BIT(offset)) - 1) +#define VSC9953_ENC_BITFIELD(target, offset, width) \ + (((target) & VSC9953_BITMASK(width)) << (offset)) + +#define VSC9953_IO_ADDR(target, offset) ((target) + (offset << 2)) + +#define VSC9953_IO_REG(target, offset) (VSC9953_IO_ADDR(target, offset)) +#define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri) \ + VSC9953_IO_REG(target, (0x2 + (ri))) + +#define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \ + VSC9953_IO_REG(target, (0x42 + (ri))) + +#define VSC9953_VCAP_CACHE_TG_DAT(target) VSC9953_IO_REG(target, 0xe2) +#define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1) +#define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \ + VSC9953_ENC_BITFIELD(target, 0, 16) + +#define VSC9953_VCAP_CFG_UPDATE_CTRL(target) VSC9953_IO_REG(target, 0x0) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \ + VSC9953_ENC_BITFIELD(target, 22, 3) + +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \ + VSC9953_ENC_BITFIELD(target, 3, 16) + +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) +#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) +#define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \ + VSC9953_IO_REG(target, (0x82 + (ri))) + +#define VSC9953_VCAP_CACHE_CNT_DAT(target, ri) \ + VSC9953_IO_REG(target, (0xc2 + (ri))) + +#define VSC9953_PORT_OFFSET 1 +#define VSC9953_IS1_CNT 256 +#define VSC9953_IS2_CNT 1024 +#define VSC9953_ES0_CNT 1024 + +#define BITS_TO_DWORD(in) (1 + (((in) - 1) / 32)) +#define ENTRY_WORDS_ES0 BITS_TO_DWORD(29) +#define ENTRY_WORDS_IS1 BITS_TO_DWORD(376) +#define ENTRY_WORDS_IS2 BITS_TO_DWORD(376) +#define ES0_ACT_WIDTH BITS_TO_DWORD(91) +#define ES0_CNT_WIDTH BITS_TO_DWORD(1) +#define IS1_ACT_WIDTH BITS_TO_DWORD(320) +#define IS1_CNT_WIDTH BITS_TO_DWORD(4) +#define IS2_ACT_WIDTH BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET) +#define IS2_CNT_WIDTH BITS_TO_DWORD(4 * 32) +#define ES0_ACT_COUNT (VSC9953_ES0_CNT + VSC9953_MAX_PORTS) +#define IS1_ACT_COUNT (VSC9953_IS1_CNT + 1) +#define IS2_ACT_COUNT (VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2) + +/* TCAM entries */ +enum tcam_sel { + TCAM_SEL_ENTRY = BIT(0), + TCAM_SEL_ACTION = BIT(1), + TCAM_SEL_COUNTER = BIT(2), + TCAM_SEL_ALL = VSC9953_BITMASK(3), +}; + +enum tcam_cmd { + TCAM_CMD_WRITE = 0, + TCAM_CMD_READ = 1, + TCAM_CMD_MOVE_UP = 2, + TCAM_CMD_MOVE_DOWN = 3, + TCAM_CMD_INITIALIZE = 4, +}; + struct vsc9953_mdio_info { struct vsc9953_mii_mng *regs; char *name; diff --git a/lib/Kconfig b/lib/Kconfig index 15c6a52d4a..dd54516f30 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -285,6 +285,11 @@ config ERRNO_STR - if errno is null or positive number - a pointer to "Success" message - if errno is negative - a pointer to errno related message +config HEXDUMP + bool "Enable hexdump" + help + This enables functions for printing dumps of binary data. + config OF_LIBFDT bool "Enable the FDT library" default y if OF_CONTROL diff --git a/lib/Makefile b/lib/Makefile index c0511cbff8..427d359159 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_REGEX) += slre.o obj-y += string.o obj-y += tables_csum.o obj-y += time.o +obj-y += hexdump.o obj-$(CONFIG_TRACE) += trace.o obj-$(CONFIG_LIB_UUID) += uuid.o obj-$(CONFIG_LIB_RAND) += rand.o diff --git a/lib/efi/Makefile b/lib/efi/Makefile index 18d081ac46..f1a3929e32 100644 --- a/lib/efi/Makefile +++ b/lib/efi/Makefile @@ -7,9 +7,11 @@ obj-$(CONFIG_EFI_STUB) += efi_info.o CFLAGS_REMOVE_efi_stub.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) -CFLAGS_efi_stub.o := -fpic -fshort-wchar -DEFI_STUB +CFLAGS_efi_stub.o := -fpic -fshort-wchar -DEFI_STUB \ + $(if $(CONFIG_EFI_STUB_64BIT),-m64) CFLAGS_REMOVE_efi.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) -CFLAGS_efi.o := -fpic -fshort-wchar -DEFI_STUB +CFLAGS_efi.o := -fpic -fshort-wchar -DEFI_STUB \ + $(if $(CONFIG_EFI_STUB_64BIT),-m64) extra-$(CONFIG_EFI_STUB) += efi_stub.o efi.o diff --git a/lib/efi/efi_stub.c b/lib/efi/efi_stub.c index 3138739ee5..09023a2f67 100644 --- a/lib/efi/efi_stub.c +++ b/lib/efi/efi_stub.c @@ -281,7 +281,8 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table) ret = efi_init(priv, "Payload", image, sys_table); if (ret) { - printhex2(ret); puts(" efi_init() failed\n"); + printhex2(ret); + puts(" efi_init() failed\n"); return ret; } global_priv = priv; @@ -294,7 +295,8 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table) size = 0; ret = boot->get_memory_map(&size, NULL, &key, &desc_size, &version); if (ret != EFI_BUFFER_TOO_SMALL) { - printhex2(BITS_PER_LONG); + printhex2(EFI_BITS_PER_LONG); + putc(' '); printhex2(ret); puts(" No memory map\n"); return ret; @@ -303,7 +305,7 @@ efi_status_t efi_main(efi_handle_t image, struct efi_system_table *sys_table) desc = efi_malloc(priv, size, &ret); if (!desc) { printhex2(ret); - puts(" No memory for memory descriptor: "); + puts(" No memory for memory descriptor\n"); return ret; } ret = setup_info_table(priv, size + 128); diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 3cffe9ef46..ecdb77e5b6 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -126,6 +126,20 @@ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel, case IMAGE_REL_BASED_DIR64: *x64 += (uint64_t)delta; break; +#ifdef __riscv + case IMAGE_REL_BASED_RISCV_HI20: + *x32 = ((*x32 & 0xfffff000) + (uint32_t)delta) | + (*x32 & 0x00000fff); + break; + case IMAGE_REL_BASED_RISCV_LOW12I: + case IMAGE_REL_BASED_RISCV_LOW12S: + /* We know that we're 4k aligned */ + if (delta & 0xfff) { + printf("Unsupported reloc offset\n"); + return EFI_LOAD_ERROR; + } + break; +#endif default: printf("Unknown Relocation off %x type %x\n", offset, type); diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 65f2bcf140..4874eb602f 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -28,6 +28,10 @@ static efi_status_t __efi_runtime EFIAPI efi_unimplemented(void); static efi_status_t __efi_runtime EFIAPI efi_device_error(void); static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void); +/* + * TODO(sjg@chromium.org): These defines and structs should come from the elf + * header for each arch (or a generic header) rather than being repeated here. + */ #if defined(CONFIG_ARM64) #define R_RELATIVE 1027 #define R_MASK 0xffffffffULL diff --git a/lib/hexdump.c b/lib/hexdump.c new file mode 100644 index 0000000000..bf14b5bdbd --- /dev/null +++ b/lib/hexdump.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * lib/hexdump.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. See README and COPYING for + * more details. + */ + +#include <common.h> +#include <hexdump.h> +#include <linux/ctype.h> +#include <linux/compat.h> +#include <linux/log2.h> +#include <asm/unaligned.h> + +const char hex_asc[] = "0123456789abcdef"; +const char hex_asc_upper[] = "0123456789ABCDEF"; + +#ifdef CONFIG_HEXDUMP +/** + * hex_dump_to_buffer - convert a blob of data to "hex ASCII" in memory + * @buf: data blob to dump + * @len: number of bytes in the @buf + * @rowsize: number of bytes to print per line; must be 16 or 32 + * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) + * @linebuf: where to put the converted data + * @linebuflen: total size of @linebuf, including space for terminating NUL + * @ascii: include ASCII after the hex output + * + * hex_dump_to_buffer() works on one "line" of output at a time, i.e., + * 16 or 32 bytes of input data converted to hex + ASCII output. + * + * Given a buffer of u8 data, hex_dump_to_buffer() converts the input data + * to a hex + ASCII dump at the supplied memory location. + * The converted output is always NUL-terminated. + * + * E.g.: + * hex_dump_to_buffer(frame->data, frame->len, 16, 1, + * linebuf, sizeof(linebuf), true); + * + * example output buffer: + * 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO + * + * Return: + * The amount of bytes placed in the buffer without terminating NUL. If the + * output was truncated, then the return value is the number of bytes + * (excluding the terminating NUL) which would have been written to the final + * string if enough space had been available. + */ +int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize, + char *linebuf, size_t linebuflen, bool ascii) +{ + const u8 *ptr = buf; + int ngroups; + u8 ch; + int j, lx = 0; + int ascii_column; + int ret; + + if (rowsize != 16 && rowsize != 32) + rowsize = 16; + + if (len > rowsize) /* limit to one line at a time */ + len = rowsize; + if (!is_power_of_2(groupsize) || groupsize > 8) + groupsize = 1; + if ((len % groupsize) != 0) /* no mixed size output */ + groupsize = 1; + + ngroups = len / groupsize; + ascii_column = rowsize * 2 + rowsize / groupsize + 1; + + if (!linebuflen) + goto overflow1; + + if (!len) + goto nil; + + if (groupsize == 8) { + const u64 *ptr8 = buf; + + for (j = 0; j < ngroups; j++) { + ret = snprintf(linebuf + lx, linebuflen - lx, + "%s%16.16llx", j ? " " : "", + get_unaligned(ptr8 + j)); + if (ret >= linebuflen - lx) + goto overflow1; + lx += ret; + } + } else if (groupsize == 4) { + const u32 *ptr4 = buf; + + for (j = 0; j < ngroups; j++) { + ret = snprintf(linebuf + lx, linebuflen - lx, + "%s%8.8x", j ? " " : "", + get_unaligned(ptr4 + j)); + if (ret >= linebuflen - lx) + goto overflow1; + lx += ret; + } + } else if (groupsize == 2) { + const u16 *ptr2 = buf; + + for (j = 0; j < ngroups; j++) { + ret = snprintf(linebuf + lx, linebuflen - lx, + "%s%4.4x", j ? " " : "", + get_unaligned(ptr2 + j)); + if (ret >= linebuflen - lx) + goto overflow1; + lx += ret; + } + } else { + for (j = 0; j < len; j++) { + if (linebuflen < lx + 2) + goto overflow2; + ch = ptr[j]; + linebuf[lx++] = hex_asc_hi(ch); + if (linebuflen < lx + 2) + goto overflow2; + linebuf[lx++] = hex_asc_lo(ch); + if (linebuflen < lx + 2) + goto overflow2; + linebuf[lx++] = ' '; + } + if (j) + lx--; + } + if (!ascii) + goto nil; + + while (lx < ascii_column) { + if (linebuflen < lx + 2) + goto overflow2; + linebuf[lx++] = ' '; + } + for (j = 0; j < len; j++) { + if (linebuflen < lx + 2) + goto overflow2; + ch = ptr[j]; + linebuf[lx++] = (isascii(ch) && isprint(ch)) ? ch : '.'; + } +nil: + linebuf[lx] = '\0'; + return lx; +overflow2: + linebuf[lx++] = '\0'; +overflow1: + return ascii ? ascii_column + len : (groupsize * 2 + 1) * ngroups - 1; +} + +/** + * print_hex_dump - print a text hex dump to syslog for a binary blob of data + * @prefix_str: string to prefix each line with; + * caller supplies trailing spaces for alignment if desired + * @prefix_type: controls whether prefix of an offset, address, or none + * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE) + * @rowsize: number of bytes to print per line; must be 16 or 32 + * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1) + * @buf: data blob to dump + * @len: number of bytes in the @buf + * @ascii: include ASCII after the hex output + * + * Given a buffer of u8 data, print_hex_dump() prints a hex + ASCII dump + * to the stdio, with an optional leading prefix. + * + * print_hex_dump() works on one "line" of output at a time, i.e., + * 16 or 32 bytes of input data converted to hex + ASCII output. + * print_hex_dump() iterates over the entire input @buf, breaking it into + * "line size" chunks to format and print. + * + * E.g.: + * print_hex_dump("raw data: ", DUMP_PREFIX_ADDRESS, 16, 1, frame->data, + * frame->len, true); + * + * Example output using %DUMP_PREFIX_OFFSET and 1-byte mode: + * 0009ab42: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO + * Example output using %DUMP_PREFIX_ADDRESS and 4-byte mode: + * ffffffff88089af0: 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~. + */ +void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize, + int groupsize, const void *buf, size_t len, bool ascii) +{ + const u8 *ptr = buf; + int i, linelen, remaining = len; + char linebuf[32 * 3 + 2 + 32 + 1]; + + if (rowsize != 16 && rowsize != 32) + rowsize = 16; + + for (i = 0; i < len; i += rowsize) { + linelen = min(remaining, rowsize); + remaining -= rowsize; + + hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize, + linebuf, sizeof(linebuf), ascii); + + switch (prefix_type) { + case DUMP_PREFIX_ADDRESS: + printf("%s%p: %s\n", prefix_str, ptr + i, linebuf); + break; + case DUMP_PREFIX_OFFSET: + printf("%s%.8x: %s\n", prefix_str, i, linebuf); + break; + default: + printf("%s%s\n", prefix_str, linebuf); + break; + } + } +} + +/** + * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params + * @prefix_str: string to prefix each line with; + * caller supplies trailing spaces for alignment if desired + * @prefix_type: controls whether prefix of an offset, address, or none + * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE) + * @buf: data blob to dump + * @len: number of bytes in the @buf + * + * Calls print_hex_dump(), rowsize of 16, groupsize of 1, + * and ASCII output included. + */ +void print_hex_dump_bytes(const char *prefix_str, int prefix_type, + const void *buf, size_t len) +{ + print_hex_dump(prefix_str, prefix_type, 16, 1, buf, len, true); +} +#else +/* + * Some code in U-Boot copy-pasted from Linux kernel uses both + * functions below so to keep stuff compilable we keep these stubs here. + */ +void print_hex_dump(const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, + size_t len, bool ascii) +{ +} + +void print_hex_dump_bytes(const char *prefix_str, int prefix_type, + const void *buf, size_t len) +{ +} +#endif /* CONFIG_HEXDUMP */ diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 8514f50498..8b1b29fb5a 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -15,6 +15,7 @@ #include <charset.h> #include <efi_loader.h> #include <div64.h> +#include <hexdump.h> #include <uuid.h> #include <stdarg.h> #include <linux/ctype.h> @@ -315,17 +316,6 @@ static char *device_path_string(char *buf, char *end, void *dp, int field_width, #endif #ifdef CONFIG_CMD_NET -static const char hex_asc[] = "0123456789abcdef"; -#define hex_asc_lo(x) hex_asc[((x) & 0x0f)] -#define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] - -static inline char *pack_hex_byte(char *buf, u8 byte) -{ - *buf++ = hex_asc_hi(byte); - *buf++ = hex_asc_lo(byte); - return buf; -} - static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width, int precision, int flags) { @@ -335,7 +325,7 @@ static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width, int i; for (i = 0; i < 6; i++) { - p = pack_hex_byte(p, addr[i]); + p = hex_byte_pack(p, addr[i]); if (!(flags & SPECIAL) && i != 5) *p++ = ':'; } @@ -354,8 +344,8 @@ static char *ip6_addr_string(char *buf, char *end, u8 *addr, int field_width, int i; for (i = 0; i < 8; i++) { - p = pack_hex_byte(p, addr[2 * i]); - p = pack_hex_byte(p, addr[2 * i + 1]); + p = hex_byte_pack(p, addr[2 * i]); + p = hex_byte_pack(p, addr[2 * i + 1]); if (!(flags & SPECIAL) && i != 7) *p++ = ':'; } @@ -182,7 +182,8 @@ void arp_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len) (net_read_ip(&arp->ar_spa).s_addr & net_netmask.s_addr)) udelay(5000); #endif - net_send_packet((uchar *)et, eth_hdr_size + ARP_HDR_SIZE); + memcpy(net_tx_packet, et, eth_hdr_size + ARP_HDR_SIZE); + net_send_packet(net_tx_packet, eth_hdr_size + ARP_HDR_SIZE); return; case ARPOP_REPLY: /* arp reply */ diff --git a/net/eth-uclass.c b/net/eth-uclass.c index d20a1cf160..e4b49229e3 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -395,7 +395,7 @@ int eth_initialize(void) * This is accomplished by attempting to probe each device and calling * their write_hwaddr() operation. */ - uclass_first_device(UCLASS_ETH, &dev); + uclass_first_device_check(UCLASS_ETH, &dev); if (!dev) { printf("No ethernet found.\n"); bootstage_error(BOOTSTAGE_ID_NET_ETH_START); @@ -424,7 +424,7 @@ int eth_initialize(void) eth_write_hwaddr(dev); - uclass_next_device(&dev); + uclass_next_device_check(&dev); num_devices++; } while (dev); @@ -393,6 +393,7 @@ void net_init(void) int net_loop(enum proto_t protocol) { int ret = -EINVAL; + enum net_loop_state prev_net_state = net_state; net_restarted = 0; net_dev_exists = 0; @@ -430,6 +431,7 @@ restart: case 1: /* network not configured */ eth_halt(); + net_set_state(prev_net_state); return -ENODEV; case 2: @@ -655,6 +657,7 @@ done: net_set_udp_handler(NULL); net_set_icmp_handler(NULL); #endif + net_set_state(prev_net_state); return ret; } @@ -822,6 +822,8 @@ static void nfs_handler(uchar *pkt, unsigned dest, struct in_addr sip, case STATE_READ_REQ: rlen = nfs_read_reply(pkt, len); + if (rlen == -NFS_RPC_DROP) + break; net_set_timeout_handler(nfs_timeout, nfs_timeout_handler); if (rlen > 0) { nfs_offset += rlen; diff --git a/net/ping.c b/net/ping.c index 5464f2f785..3e5461a36a 100644 --- a/net/ping.c +++ b/net/ping.c @@ -107,7 +107,8 @@ void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len) icmph->type = ICMP_ECHO_REPLY; icmph->checksum = 0; icmph->checksum = compute_ip_checksum(icmph, len - IP_HDR_SIZE); - net_send_packet((uchar *)et, eth_hdr_size + len); + memcpy(net_tx_packet, et, eth_hdr_size + len); + net_send_packet(net_tx_packet, eth_hdr_size + len); return; /* default: return;*/ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index ef7604c463..f8c3fff1d1 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -385,8 +385,14 @@ cmd_efi_ld = $(LD) -nostdlib -znocombreloc -T $(EFI_LDS_PATH) -shared \ EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS) -$(obj)/%_efi.so: $(obj)/%.o arch/$(ARCH)/lib/$(EFI_CRT0) \ - arch/$(ARCH)/lib/$(EFI_RELOC) +$(obj)/efi_crt0.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_CRT0:.o=.S) + $(call if_changed_dep,as_o_S) + +$(obj)/efi_reloc.o: $(srctree)/arch/$(ARCH)/lib/$(EFI_RELOC:.o=.c) $(recordmcount_source) FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) + +$(obj)/%_efi.so: $(obj)/%.o $(obj)/efi_crt0.o $(obj)/efi_reloc.o $(call cmd,efi_ld) # ACPI @@ -399,6 +405,7 @@ cmd_acpi_c_asl= \ $(obj)/dsdt.c: $(src)/dsdt.asl $(call cmd,acpi_c_asl) + $(Q)sed -i -e "s,dsdt_aml_code,AmlCode," $@ # Bzip2 # --------------------------------------------------------------------------- diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ef018b5b40..252f13826d 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -167,8 +167,14 @@ ifdef CONFIG_ARCH_ZYNQ MKIMAGEFLAGS_boot.bin = -T zynqimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) endif ifdef CONFIG_ARCH_ZYNQMP +ifneq ($(CONFIG_PMUFW_INIT_FILE),"") +spl/boot.bin: zynqmp-check-pmufw +zynqmp-check-pmufw: FORCE + ( cd $(srctree) && test -r $(CONFIG_PMUFW_INIT_FILE) ) \ + || ( echo "Cannot read $(CONFIG_PMUFW_INIT_FILE)" && false ) +endif MKIMAGEFLAGS_boot.bin = -T zynqmpimage -R $(srctree)/$(CONFIG_BOOT_INIT_FILE) \ - -n $(srctree)/$(CONFIG_PMUFW_INIT_FILE) + -n "$(shell cd $(srctree); readlink -f $(CONFIG_PMUFW_INIT_FILE))" endif spl/boot.bin: $(obj)/u-boot-spl.bin FORCE diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e99ba6b85a..1a54337594 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4581,7 +4581,6 @@ CONFIG_USART1 CONFIG_USART_BASE CONFIG_USART_ID CONFIG_USBBOOTCOMMAND -CONFIG_USBDEBUG CONFIG_USBD_CONFIGURATION_STR CONFIG_USBD_CTRL_INTERFACE_STR CONFIG_USBD_DATA_INTERFACE_STR diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 4b2caf6960..a5d75958e1 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -737,7 +737,8 @@ int fw_env_set(int argc, char *argv[], struct env_opts *opts) int fw_parse_script(char *fname, struct env_opts *opts) { FILE *fp; - char dump[1024]; /* Maximum line length in the file */ + char *line = NULL; + size_t linesize = 0; char *name; char *val; int lineno = 0; @@ -763,36 +764,34 @@ int fw_parse_script(char *fname, struct env_opts *opts) } } - while (fgets(dump, sizeof(dump), fp)) { + while ((len = getline(&line, &linesize, fp)) != -1) { lineno++; - len = strlen(dump); /* - * Read a whole line from the file. If the line is too long - * or is not terminated, reports an error and exit. + * Read a whole line from the file. If the line is not + * terminated, reports an error and exit. */ - if (dump[len - 1] != '\n') { + if (line[len - 1] != '\n') { fprintf(stderr, - "Line %d not corrected terminated or too long\n", + "Line %d not correctly terminated\n", lineno); ret = -1; break; } /* Drop ending line feed / carriage return */ - dump[--len] = '\0'; - if (len && dump[len - 1] == '\r') - dump[--len] = '\0'; + line[--len] = '\0'; + if (len && line[len - 1] == '\r') + line[--len] = '\0'; /* Skip comment or empty lines */ - if (len == 0 || dump[0] == '#') + if (len == 0 || line[0] == '#') continue; /* - * Search for variable's name, - * remove leading whitespaces + * Search for variable's name remove leading whitespaces */ - name = skip_blanks(dump); + name = skip_blanks(line); if (!name) continue; @@ -829,6 +828,7 @@ int fw_parse_script(char *fname, struct env_opts *opts) } } + free(line); /* Close file if not stdin */ if (strcmp(fname, "-") != 0) @@ -842,10 +842,10 @@ int fw_parse_script(char *fname, struct env_opts *opts) } /** - * environment_end() - compute offset of first byte right after environemnt + * environment_end() - compute offset of first byte right after environment * @dev - index of enviroment buffer * Return: - * device offset of first byte right after environemnt + * device offset of first byte right after environment */ off_t environment_end(int dev) { @@ -1760,19 +1760,20 @@ static int get_config(char *fname) FILE *fp; int i = 0; int rc; - char dump[128]; + char *line = NULL; + size_t linesize = 0; char *devname; fp = fopen(fname, "r"); if (fp == NULL) return -1; - while (i < 2 && fgets(dump, sizeof(dump), fp)) { - /* Skip incomplete conversions and comment strings */ - if (dump[0] == '#') + while (i < 2 && getline(&line, &linesize, fp) != -1) { + /* Skip comment strings */ + if (line[0] == '#') continue; - rc = sscanf(dump, "%ms %lli %lx %lx %lx", + rc = sscanf(line, "%ms %lli %lx %lx %lx", &devname, &DEVOFFSET(i), &ENVSIZE(i), &DEVESIZE(i), &ENVSECTORS(i)); @@ -1788,6 +1789,7 @@ static int get_config(char *fname) i++; } + free(line); fclose(fp); have_redund_env = i - 1; |