diff options
46 files changed, 1686 insertions, 269 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 48700206f8..00be305c39 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -535,6 +535,11 @@ config TARGET_MX6SABRESD select DM select DM_THERMAL +config TARGET_MX6CUBOXI + bool "Support Solid-run mx6 boards" + select CPU_V7 + select SUPPORT_SPL + config TARGET_MX6SLEVK bool "Support mx6slevk" select CPU_V7 @@ -922,6 +927,7 @@ source "board/siemens/draco/Kconfig" source "board/siemens/pxm2/Kconfig" source "board/siemens/rut/Kconfig" source "board/silica/pengwyn/Kconfig" +source "board/solidrun/mx6cuboxi/Kconfig" source "board/solidrun/hummingboard/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index d7956e57de..eb8669bb2e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -49,13 +49,6 @@ static const iomux_cfg_t iomux_boot[] = { MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, -#elif defined(CONFIG_MX28) - MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD, - MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, #endif }; @@ -65,10 +58,10 @@ static uint8_t mxs_get_bootmode_index(void) int i; uint8_t masked; +#if defined(CONFIG_MX23) /* Setup IOMUX of bootmode pads to GPIO */ mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot)); -#if defined(CONFIG_MX23) /* Setup bootmode pins as GPIO input */ gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0); gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1); @@ -83,21 +76,11 @@ static uint8_t mxs_get_bootmode_index(void) bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; #elif defined(CONFIG_MX28) - /* Setup bootmode pins as GPIO input */ - gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0); - gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1); - gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2); - gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3); - gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4); - gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5); - - /* Read bootmode pads */ - bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4; - bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5; + /* The global boot mode will be detected by ROM code and its value + * is stored at the fixed address 0x00019BF0 in OCRAM. + */ +#define GLOBAL_BOOT_MODE_ADDR 0x00019BF0 + bootmode = __raw_readl(GLOBAL_BOOT_MODE_ADDR); #endif for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) { diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 3c991e152d..fcccd0c9ba 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_SOCFPGA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index fef2231a39..653d58ef24 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -514,17 +514,21 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* MR2 */ val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | ((tcwl - 3) & 3) << 3; + debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs)); mmdc0->mdscr = MR(val, 2, 3, cs); /* MR3 */ + debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs)); mmdc0->mdscr = MR(0, 3, 3, cs); /* MR1 */ val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; + debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs)); mmdc0->mdscr = MR(val, 1, 3, cs); /* MR0 */ val = ((tcl - 1) << 4) | /* CAS */ (1 << 8) | /* DLL Reset */ ((twr - 3) << 9); /* Write Recovery */ + debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs)); mmdc0->mdscr = MR(val, 0, 3, cs); /* ZQ calibration */ val = (1 << 10); @@ -535,10 +539,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mdpdc = (tcke & 0x7) << 16 | 5 << 12 | /* PWDT_1: 256 cycles */ 5 << 8 | /* PWDT_0: 256 cycles */ - 1 << 7 | /* SLOW_PD */ 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7); + if (!sysinfo->pd_fast_exit) + mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */ mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 8b6e108c42..7524ef90e4 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -7,7 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S deleted file mode 100644 index b4d0627871..0000000000 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation <www.altera.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: - - /* Remap */ -#ifdef CONFIG_SPL_BUILD - /* - * SPL : configure the remap (L3 NIC-301 GPV) - * so the on-chip RAM at lower memory instead ROM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x19 - str r1, [r0] -#else - /* - * U-Boot : configure the remap (L3 NIC-301 GPV) - * so the SDRAM at lower memory instead on-chip RAM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x2 - str r1, [r0] - - /* Private components security */ - - /* - * U-Boot : configure private timer, global timer and cpu - * component access as non secure for kernel stage (as required - * by kernel) - */ - mrc p15,4,r0,c15,c0,0 - add r1, r0, #0x54 - ldr r2, [r1] - orr r2, r2, #0xff - orr r2, r2, #0xf00 - str r2, [r1] -#endif /* #ifdef CONFIG_SPL_BUILD */ - mov pc, lr diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 25921e76c4..45b352bdfc 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -113,3 +113,27 @@ void socfpga_spim_enable(void) clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } + +/* Bring UART0 out of reset. */ +void socfpga_uart0_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB); +} + +/* Bring SDRAM controller out of reset. */ +void socfpga_sdram_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB); +} + +/* Bring OSC1 timer out of reset. */ +void socfpga_osc1timer_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB); +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 6a8c15d91f..f994658452 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/pl310.h> #include <asm/u-boot.h> #include <asm/utils.h> #include <image.h> @@ -15,9 +16,13 @@ #include <asm/arch/freeze_controller.h> #include <asm/arch/clock_manager.h> #include <asm/arch/scan_manager.h> +#include <asm/arch/sdram.h> DECLARE_GLOBAL_DATA_PTR; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + #define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ @@ -43,6 +48,31 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ ) +void board_init_f(ulong dummy) +{ + struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + unsigned long reg; + /* + * First C code to run. Clear fake OCRAM ECC first as SBE + * and DBE might triggered during power on + */ + reg = readl(&sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_SERR) + writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_DERR) + writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Remap SDRAM to 0x0 */ + writel(0x1, &pl310->pl310_addr_filter_start); + + board_init_r(NULL, 0); +} + u32 spl_boot_device(void) { return BOOT_DEVICE_RAM; @@ -53,6 +83,7 @@ u32 spl_boot_device(void) */ void spl_board_init(void) { + unsigned long sdram_size; #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET cm_config_t cm_default_cfg = { /* main group */ @@ -144,10 +175,19 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + socfpga_sdram_enable(); + socfpga_uart0_enable(); + socfpga_osc1timer_enable(); + + timer_init(); + debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); + /* Enable bootrom to configure IOs. */ + sysmgr_enable_warmrstcfgio(); + /* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr()) hang(); @@ -165,4 +205,25 @@ void spl_board_init(void) /* enable console uart printing */ preloader_console_init(); + + if (sdram_mmr_init_full(0xffffffff) != 0) { + puts("SDRAM init failed.\n"); + hang(); + } + + debug("SDRAM: Calibrating PHY\n"); + /* SDRAM calibration */ + if (sdram_calibration_full() == 0) { + puts("SDRAM calibration failed.\n"); + hang(); + } + + sdram_size = sdram_calculate_size(); + debug("SDRAM: %ld MiB\n", sdram_size >> 20); + + /* Sanity check ensure correct SDRAM size specified */ + if (get_ram_size(0, sdram_size) != sdram_size) { + puts("SDRAM size check failed!\n"); + hang(); + } } diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c index 11f7badbf2..8126e0d43c 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -66,3 +66,12 @@ void sysmgr_pinmux_init(void) populate_sysmgr_fpgaintf_module(); } + +/* + * This bit allows the bootrom to configure the IOs after a warm reset. + */ +void sysmgr_enable_warmrstcfgio(void) +{ + setbits_le32(&sysmgr_regs->romcodegrp_ctrl, + SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); +} diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a15c3..1b86897872 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; }; regulator_3_3v: 3-3-v-regulator { @@ -72,3 +76,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 8e1f88c2c7..0b300b92be 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; }; regulator_3_3v: 3-3-v-regulator { @@ -77,3 +81,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 8e0d7d15c1..c49aa6290c 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -250,6 +250,7 @@ struct mx6_ddr_sysinfo { u8 mif3_mode; /* Command prediction working mode */ u8 rst_to_cke; /* Time from SDE enable to CKE rise */ u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ + u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ }; /* diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 034135bff4..d63a285091 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -15,6 +15,9 @@ void socfpga_bridges_reset(int enable); void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); void socfpga_spim_enable(void); +void socfpga_uart0_enable(void); +void socfpga_sdram_enable(void); +void socfpga_osc1timer_enable(void); struct socfpga_reset_manager { u32 status; @@ -36,7 +39,10 @@ struct socfpga_reset_manager { #define RSTMGR_PERMODRST_EMAC0_LSB 0 #define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 +#define RSTMGR_PERMODRST_UART0_LSB 16 #define RSTMGR_PERMODRST_SPIM0_LSB 18 #define RSTMGR_PERMODRST_SPIM1_LSB 19 +#define RSTMGR_PERMODRST_SDR_LSB 29 #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h new file mode 100644 index 0000000000..4f6489dff6 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/sdram.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * FIXME: This file contains temporary stub functions and is here + * only until these functions are properly merged into + * mainline. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_SDRAM_H__ +#define __ARCH_SDRAM_H__ + +/* function declaration */ +inline unsigned long sdram_calculate_size(void) { return 0; } +inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; } +inline int sdram_calibration_full(void) { return 0; } + +#endif /* __ARCH_SDRAM_H__ */ diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 071ec4f266..51d9815778 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -10,6 +10,7 @@ #ifndef __ASSEMBLY__ void sysmgr_pinmux_init(void); +void sysmgr_enable_warmrstcfgio(void); /* declaration for handoff table type */ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c index 61cdc73fa3..7e7a18484f 100644 --- a/board/altera/socfpga/pinmux_config.c +++ b/board/altera/socfpga/pinmux_config.c @@ -54,8 +54,8 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { 2, /* GENERALIO14 */ 0, /* GENERALIO15 */ 0, /* GENERALIO16 */ - 0, /* GENERALIO17 */ - 0, /* GENERALIO18 */ + 2, /* GENERALIO17 */ + 2, /* GENERALIO18 */ 0, /* GENERALIO19 */ 0, /* GENERALIO20 */ 0, /* GENERALIO21 */ diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h index 8130fa4744..7cd25df614 100644 --- a/board/altera/socfpga/pll_config.h +++ b/board/altera/socfpga/pll_config.h @@ -36,7 +36,7 @@ /* Peripheral PLL */ #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) /* * To tell where is the VCOs source: * 0 = EOSC1 diff --git a/board/altera/socfpga/socfpga.c b/board/altera/socfpga/socfpga.c index 20d221641b..a1dbc492c9 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/socfpga/socfpga.c @@ -18,6 +18,8 @@ DECLARE_GLOBAL_DATA_PTR; +void s_init(void) {} + /* * Miscellaneous platform dependent initialisations */ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 7181cac291..87d05780fe 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -74,8 +74,7 @@ obj-$(CONFIG_P5040DS) += p_corenet/ obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o ifdef CONFIG_SECURE_BOOT -obj-y += fsl_validate.o -obj-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o +obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index bb2dd9624b..23f8f6b76f 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -753,10 +753,11 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = { .p1_mpwrdlctl = 0x48254A36, }; +/* MT41K128M16JT-125 */ static struct mx6_ddr3_cfg mem_ddr = { .mem_speed = 1600, - .density = 4, - .width = 64, + .density = 2, + .width = 16, .banks = 8, .rowaddr = 14, .coladdr = 10, @@ -798,18 +799,14 @@ static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ - .dsize = mem_ddr.width/32, + .dsize = 2, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */ .ncs = 1, .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ -#ifdef RTT_NOM_120OHM - .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ -#else .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ -#endif .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ @@ -818,7 +815,7 @@ static void spl_dram_init(void) .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ }; - mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); } diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index ab3bab847a..ba159696b4 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -81,8 +81,14 @@ read_eeprom(int bus, struct ventana_board_info *info) type = GW54xx; break; case '5': - type = GW552x; - break; + if (info->model[4] == '1') { + type = GW551x; + break; + } else if (info->model[4] == '2') { + type = GW552x; + break; + } + /* fall through */ default: printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); type = GW_UNKNOWN; diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index a34a9a84c8..718e1651d0 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -13,8 +13,6 @@ #include "gsc.h" -#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100) - /* * The Gateworks System Controller will fail to ACK a master transaction if * it is busy, which can occur during its 1HZ timer tick while reading ADC's. @@ -61,9 +59,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) return ret; } -#ifdef CONFIG_CMD_GSC -static void read_hwmon(const char *name, uint reg, uint size, uint low, - uint high) +static void read_hwmon(const char *name, uint reg, uint size) { unsigned char buf[3]; uint ui; @@ -75,59 +71,121 @@ static void read_hwmon(const char *name, uint reg, uint size, uint low, } else { ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); if (ui == 0xffffff) - printf("invalid"); - else if (ui < low) - printf("%d Failed - Low", ui); - else if (ui > high) - printf("%d Failed - High", ui); + puts("invalid\n"); else - printf("%d", ui); + printf("%d\n", ui); } - puts("\n"); } -int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int gsc_info(int verbose) { const char *model = getenv("model"); + unsigned char buf[16]; i2c_set_bus_num(0); - read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000); - read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000); - read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500); - read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10)); - read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10)); - read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10)); - read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10)); - read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10)); - read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10)); + if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16)) + return CMD_RET_FAILURE; + + printf("GSC: v%d", buf[GSC_SC_FWVER]); + printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8); + printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN)) + ? "en" : "dis"); + if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) { + buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG); + puts(" WDT_RESET"); + gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, + &buf[GSC_SC_STATUS], 1); + } + puts("\n"); + if (!verbose) + return CMD_RET_SUCCESS; + read_hwmon("Temp", GSC_HWMON_TEMP, 2); + read_hwmon("VIN", GSC_HWMON_VIN, 3); + read_hwmon("VBATT", GSC_HWMON_VBATT, 3); + read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); + read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); + read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); + read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); + read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); + read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); + read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); + read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); switch (model[3]) { case '1': /* GW51xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ break; case '2': /* GW52xx */ + break; case '3': /* GW53xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); - read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */ + read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); break; case '4': /* GW54xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10)); - read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ + read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); break; case '5': /* GW55xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); break; } return 0; } -U_BOOT_CMD(gsc, 1, 1, do_gsc, - "GSC test", - "" -); +#ifdef CONFIG_CMD_GSC +static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned char reg; + + if (argc < 2) + return CMD_RET_USAGE; + + if (strcasecmp(argv[1], "enable") == 0) { + int timeout = 0; + + if (argc > 2) + timeout = simple_strtoul(argv[2], NULL, 10); + i2c_set_bus_num(0); + if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); + if (timeout == 60) + reg |= (1 << GSC_SC_CTRL1_WDTIME); + else + timeout = 30; + reg |= (1 << GSC_SC_CTRL1_WDEN); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + printf("GSC Watchdog enabled with timeout=%d seconds\n", + timeout); + } else if (strcasecmp(argv[1], "disable") == 0) { + i2c_set_bus_num(0); + if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + printf("GSC Watchdog disabled\n"); + } else { + return CMD_RET_USAGE; + } + return CMD_RET_SUCCESS; +} + +static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2) + return gsc_info(1); + + if (strcasecmp(argv[1], "wd") == 0) + return do_gsc_wd(cmdtp, flag, --argc, ++argv); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + gsc, 4, 1, do_gsc, "GSC configuration", + "[wd enable [30|60]]|[wd disable]\n" + ); #endif /* CONFIG_CMD_GSC */ diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h index da970c39d6..2d4969ecdd 100644 --- a/board/gateworks/gw_ventana/gsc.h +++ b/board/gateworks/gw_ventana/gsc.h @@ -19,12 +19,15 @@ enum { GSC_SC_CTRL0 = 0x00, GSC_SC_CTRL1 = 0x01, GSC_SC_STATUS = 0x0a, + GSC_SC_FWCRC = 0x0c, GSC_SC_FWVER = 0x0e, }; /* System Controller Control1 bits */ enum { - GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */ + GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */ + GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */ + GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */ }; /* System Controller Interrupt bits */ @@ -50,8 +53,10 @@ enum { GSC_HWMON_VDD_DDR = 0x17, GSC_HWMON_VDD_SOC = 0x11, GSC_HWMON_VDD_1P8 = 0x1d, + GSC_HWMON_VDD_IO2 = 0x20, GSC_HWMON_VDD_2P5 = 0x23, - GSC_HWMON_VDD_1P0 = 0x20, + GSC_HWMON_VDD_IO3 = 0x26, + GSC_HWMON_VDD_IO4 = 0x29, }; /* @@ -60,5 +65,6 @@ enum { */ int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); +int gsc_info(int verbose); #endif diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index bb08cd272e..1e54912a01 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -89,16 +89,16 @@ DECLARE_GLOBAL_DATA_PTR; */ struct ventana_board_info ventana_info; -int board_type; +static int board_type; /* UART1: Function varies per baseboard */ -iomux_v3_cfg_t const uart1_pads[] = { +static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; /* UART2: Serial Console */ -iomux_v3_cfg_t const uart2_pads[] = { +static iomux_v3_cfg_t const uart2_pads[] = { IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; @@ -106,7 +106,7 @@ iomux_v3_cfg_t const uart2_pads[] = { #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1: GSC */ -struct i2c_pads_info mx6q_i2c_pad_info0 = { +static struct i2c_pads_info mx6q_i2c_pad_info0 = { .scl = { .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, @@ -118,7 +118,7 @@ struct i2c_pads_info mx6q_i2c_pad_info0 = { .gp = IMX_GPIO_NR(3, 28) } }; -struct i2c_pads_info mx6dl_i2c_pad_info0 = { +static struct i2c_pads_info mx6dl_i2c_pad_info0 = { .scl = { .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, @@ -132,7 +132,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info0 = { }; /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ -struct i2c_pads_info mx6q_i2c_pad_info1 = { +static struct i2c_pads_info mx6q_i2c_pad_info1 = { .scl = { .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, @@ -144,7 +144,7 @@ struct i2c_pads_info mx6q_i2c_pad_info1 = { .gp = IMX_GPIO_NR(4, 13) } }; -struct i2c_pads_info mx6dl_i2c_pad_info1 = { +static struct i2c_pads_info mx6dl_i2c_pad_info1 = { .scl = { .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, @@ -158,7 +158,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info1 = { }; /* I2C3: Misc/Expansion */ -struct i2c_pads_info mx6q_i2c_pad_info2 = { +static struct i2c_pads_info mx6q_i2c_pad_info2 = { .scl = { .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, @@ -170,7 +170,7 @@ struct i2c_pads_info mx6q_i2c_pad_info2 = { .gp = IMX_GPIO_NR(1, 6) } }; -struct i2c_pads_info mx6dl_i2c_pad_info2 = { +static struct i2c_pads_info mx6dl_i2c_pad_info2 = { .scl = { .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, @@ -184,7 +184,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info2 = { }; /* MMC */ -iomux_v3_cfg_t const usdhc3_pads[] = { +static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -196,7 +196,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { }; /* ENET */ -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), @@ -220,7 +220,7 @@ iomux_v3_cfg_t const enet_pads[] = { }; /* NAND */ -iomux_v3_cfg_t const nfc_pads[] = { +static iomux_v3_cfg_t const nfc_pads[] = { IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -285,7 +285,7 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_USB_EHCI_MX6 -iomux_v3_cfg_t const usb_pads[] = { +static iomux_v3_cfg_t const usb_pads[] = { IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), /* OTG PWR */ @@ -328,7 +328,7 @@ int board_ehci_power(int port, int on) #endif /* CONFIG_USB_EHCI_MX6 */ #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; int board_mmc_getcd(struct mmc *mmc) { @@ -397,11 +397,15 @@ int board_phy_config(struct phy_device *phydev) int board_eth_init(bd_t *bis) { - setup_iomux_enet(); - #ifdef CONFIG_FEC_MXC - if (board_type != GW552x) + if (board_type != GW551x && board_type != GW552x) { + setup_iomux_enet(); cpu_eth_init(bis); + } +#endif + +#ifdef CONFIG_E1000 + e1000_initialize(bis); #endif #ifdef CONFIG_CI_UDC @@ -409,6 +413,15 @@ int board_eth_init(bd_t *bis) usb_eth_initialize(bis); #endif + /* default to the first detected enet dev */ + if (!getenv("ethprime")) { + struct eth_device *dev = eth_get_dev_by_index(0); + if (dev) { + setenv("ethprime", dev->name); + printf("set ethprime to %s\n", getenv("ethprime")); + } + } + return 0; } @@ -482,6 +495,48 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + /* DLC700JMG-T-4 */ + .bus = 0, + .addr = 0, + .detect = NULL, + .enable = enable_lvds, + .pixfmt = IPU_PIX_FMT_LVDS666, + .mode = { + .name = "DLC700JMGT4", + .refresh = 60, + .xres = 1024, /* 1024x600active pixels */ + .yres = 600, + .pixclock = 15385, /* 64MHz */ + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + /* DLC800FIG-T-3 */ + .bus = 0, + .addr = 0, + .detect = NULL, + .enable = enable_lvds, + .pixfmt = IPU_PIX_FMT_LVDS666, + .mode = { + .name = "DLC800FIGT3", + .refresh = 60, + .xres = 1024, /* 1024x768 active pixels */ + .yres = 768, + .pixclock = 15385, /* 64MHz */ + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } } }; size_t display_count = ARRAY_SIZE(displays); @@ -614,6 +669,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCI_RST# (GW522x) */ + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; @@ -658,8 +715,6 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCICK_SSON */ - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* VID_EN */ @@ -668,6 +723,15 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), }; +static iomux_v3_cfg_t const gw551x_gpio_pads[] = { + /* PANLED# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + static iomux_v3_cfg_t const gw552x_gpio_pads[] = { /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), @@ -709,6 +773,7 @@ struct ventana { int num_pads; /* DIO pinmux/val */ struct dio_cfg dio_cfg[4]; + int num_gpios; /* various gpios (0 if non-existent) */ int leds[3]; int pcie_rst; @@ -723,7 +788,7 @@ struct ventana { int wdis; }; -struct ventana gpio_cfg[] = { +static struct ventana gpio_cfg[] = { /* GW5400proto */ { .gpio_pads = gw54xx_gpio_pads, @@ -754,6 +819,7 @@ struct ventana gpio_cfg[] = { 4 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 10), @@ -797,6 +863,7 @@ struct ventana gpio_cfg[] = { 4 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 10), @@ -839,6 +906,7 @@ struct ventana gpio_cfg[] = { 0 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -883,6 +951,7 @@ struct ventana gpio_cfg[] = { 0 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -926,6 +995,7 @@ struct ventana gpio_cfg[] = { 4 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -941,10 +1011,10 @@ struct ventana gpio_cfg[] = { .wdis = IMX_GPIO_NR(5, 17), }, - /* GW552x */ + /* GW551x */ { - .gpio_pads = gw552x_gpio_pads, - .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .gpio_pads = gw551x_gpio_pads, + .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, .dio_cfg = { { { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, @@ -965,18 +1035,46 @@ struct ventana gpio_cfg[] = { 3 }, { - { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(2, 10), - { 0, 0 }, - 0 + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 2, + .leds = { + IMX_GPIO_NR(4, 7), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW552x */ + { + .gpio_pads = gw552x_gpio_pads, + .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), IMX_GPIO_NR(4, 15), }, .pcie_rst = IMX_GPIO_NR(1, 29), + .wdis = IMX_GPIO_NR(7, 12), }, }; @@ -1014,22 +1112,32 @@ int power_init_board(void) p = pmic_get("LTC3676_PMIC"); if (p && !pmic_probe(p)) { puts("PMIC: LTC3676\n"); - /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ - if (is_cpu_type(MXC_CPU_MX6Q)) { - /* mask PGOOD during SW1 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB1B, reg); - /* set SW1 (VDD_SOC) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB1A, reg); - - /* mask PGOOD during SW3 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB3B, reg); - /*set SW3 (VDD_ARM) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB3A, reg); - } + /* + * set board-specific scalar for max CPU frequency + * per CPU based on the LDO enabled Operating Ranges + * defined in the respective IMX6DQ and IMX6SDL + * datasheets. The voltage resulting from the R1/R2 + * feedback inputs on Ventana is 1308mV. Note that this + * is a bit shy of the Vmin of 1350mV in the datasheet + * for LDO enabled mode but is as high as we can go. + * + * We will rely on an OS kernel driver to properly + * regulate these per CPU operating point and use LDO + * bypass mode when using the higher frequency + * operating points to compensate as LDO bypass mode + * allows the rails be 125mV lower. + */ + /* mask PGOOD during SW1 transition */ + pmic_reg_write(p, LTC3676_DVB1B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW1 (VDD_SOC) */ + pmic_reg_write(p, LTC3676_DVB1A, 0x1f); + + /* mask PGOOD during SW3 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); } } @@ -1062,6 +1170,10 @@ static void setup_board_gpio(int board) } #if !defined(CONFIG_CMD_PCI) + /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ + if (board_type == GW52xx && info->model[4] == '2') + gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); + /* assert PCI_RST# (released by OS when clock is valid) */ gpio_direction_output(gpio_cfg[board].pcie_rst, 0); #endif @@ -1100,7 +1212,9 @@ static void setup_board_gpio(int board) /* USBOTG Select (PCISKT or FrontPanel) */ if (gpio_cfg[board].usb_sel) - gpio_direction_output(gpio_cfg[board].usb_sel, 0); + gpio_direction_output(gpio_cfg[board].usb_sel, + (hwconfig("usb_pcisel")) ? 1 : 0); + /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ if (gpio_cfg[board].wdis) @@ -1115,6 +1229,8 @@ static void setup_board_gpio(int board) iomux_v3_cfg_t ctrl = DIO_PAD_CFG; unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; + if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) + continue; sprintf(arg, "dio%d", i); if (!hwconfig(arg)) continue; @@ -1320,15 +1436,8 @@ int checkboard(void) return 0; /* Display GSC firmware revision/CRC/status */ - i2c_set_bus_num(CONFIG_I2C_GSC); - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { - printf("GSC: v%d", buf[0]); - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { - printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ - printf(" 0x%02x", buf[0]); /* irq status */ - } - puts("\n"); - } + gsc_info(0); + /* Display RTC */ if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { printf("RTC: %d\n", @@ -1407,7 +1516,7 @@ int misc_init_r(void) sprintf(fdt, "%s-%s.dtb", cputype, str); setenv("fdt_file1", fdt); } - if (board_type != GW552x) + if (board_type != GW551x && board_type != GW552x) str[4] = 'x'; str[5] = 'x'; str[6] = 0; @@ -1430,6 +1539,10 @@ int misc_init_r(void) /* board serial-number */ sprintf(str, "%6d", info->serial); setenv("serial#", str); + + /* memory MB */ + sprintf(str, "%d", (int) (gd->ram_size >> 20)); + setenv("mem_mb", str); } @@ -1461,19 +1574,48 @@ int misc_init_r(void) } else { puts("Error: could not disable GSC Watchdog\n"); } - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { - if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ - puts("GSC boot watchdog timeout detected\n"); - reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ - gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); - } - } return 0; } #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +static int ft_sethdmiinfmt(void *blob, char *mode) +{ + int off; + + if (!mode) + return -EINVAL; + + off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x"); + if (off < 0) + return off; + + if (0 == strcasecmp(mode, "yuv422bt656")) { + u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00, + 0x00, 0x00, 0x00 }; + mode = "422_ccir"; + fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); + fdt_setprop_u32(blob, off, "vidout_trc", 1); + fdt_setprop_u32(blob, off, "vidout_blc", 1); + fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); + printf(" set HDMI input mode to %s\n", mode); + } else if (0 == strcasecmp(mode, "yuv422smp")) { + u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00, + 0x82, 0x81, 0x00 }; + mode = "422_smp"; + fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); + fdt_setprop_u32(blob, off, "vidout_trc", 0); + fdt_setprop_u32(blob, off, "vidout_blc", 0); + fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); + printf(" set HDMI input mode to %s\n", mode); + } else { + return -EINVAL; + } + + return 0; +} + /* * called prior to booting kernel or by 'fdt boardsetup' command * @@ -1492,6 +1634,17 @@ int ft_board_setup(void *blob, bd_t *bd) { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ }; const char *model = getenv("model"); + const char *display = getenv("display"); + int i; + char rev = 0; + + /* determine board revision */ + for (i = sizeof(ventana_info.model) - 1; i > 0; i--) { + if (ventana_info.model[i] >= 'A') { + rev = ventana_info.model[i]; + break; + } + } if (getenv("fdt_noauto")) { puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); @@ -1502,6 +1655,13 @@ int ft_board_setup(void *blob, bd_t *bd) puts(" Updating MTD partitions...\n"); fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + /* Update display timings from display env var */ + if (display) { + if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"), + display) >= 0) + printf(" Set display timings for %s...\n", display); + } + if (!model) { puts("invalid board info: Leaving FDT fully enabled\n"); return 0; @@ -1516,6 +1676,91 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_setprop(blob, 0, "board", info->model, strlen((const char *)info->model) + 1); + /* set desired digital video capture format */ + ft_sethdmiinfmt(blob, getenv("hdmiinfmt")); + + /* + * disable serial2 node for GW54xx for compatibility with older + * 3.10.x kernel that improperly had this node enabled in the DT + */ + if (board_type == GW54xx) { + i = fdt_path_offset(blob, + "/soc/aips-bus@02100000/serial@021ec000"); + if (i) + fdt_del_node(blob, i); + } + + /* + * disable wdog1/wdog2 nodes for GW51xx below revC to work around + * errata causing wdog timer to be unreliable. + */ + if (board_type == GW51xx && rev >= 'A' && rev < 'C') { + i = fdt_path_offset(blob, + "/soc/aips-bus@02000000/wdog@020bc000"); + if (i) + fdt_status_disabled(blob, i); + } + + /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ + else if (board_type == GW52xx && info->model[4] == '2') { + u32 handle = 0; + u32 *range = NULL; + + i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie"); + if (i) + range = (u32 *)fdt_getprop(blob, i, "reset-gpio", + NULL); + + if (range) { + i = fdt_path_offset(blob, + "/soc/aips-bus@02000000/gpio@020a4000"); + if (i) + handle = fdt_get_phandle(blob, i); + if (handle) { + range[0] = cpu_to_fdt32(handle); + range[1] = cpu_to_fdt32(23); + } + } + } + + /* + * isolate CSI0_DATA_EN for GW551x below revB to work around + * errata causing non functional digital video in (it is not hooked up) + */ + else if (board_type == GW551x && rev == 'A') { + u32 *range = NULL; + int len; + const u32 *handle = NULL; + + i = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx-tda1997x-video"); + if (i) + handle = fdt_getprop(blob, i, "pinctrl-0", NULL); + if (handle) + i = fdt_node_offset_by_phandle(blob, + fdt32_to_cpu(*handle)); + if (i) + range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len); + if (range) { + len /= sizeof(u32); + for (i = 0; i < len; i += 6) { + u32 mux_reg = fdt32_to_cpu(range[i+0]); + u32 conf_reg = fdt32_to_cpu(range[i+1]); + /* mux PAD_CSI0_DATA_EN to GPIO */ + if (is_cpu_type(MXC_CPU_MX6Q) && + mux_reg == 0x260 && conf_reg == 0x630) + range[i+3] = cpu_to_fdt32(0x5); + else if (!is_cpu_type(MXC_CPU_MX6Q) && + mux_reg == 0x08c && conf_reg == 0x3a0) + range[i+3] = cpu_to_fdt32(0x5); + } + fdt_setprop_inplace(blob, i, "fsl,pins", range, len); + } + + /* set BT656 video format */ + ft_sethdmiinfmt(blob, "yuv422bt656"); + } + /* * Peripheral Config: * remove nodes by alias path if EEPROM config tells us the diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 97128127fb..0c0fee3196 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -188,7 +188,21 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_b7ds = 0x00000030, }; -/* MT41K128M16JT-125 */ +/* MT41K64M16JT-125 (1Gb density) */ +static struct mx6_ddr3_cfg mt41k64m16jt_125 = { + .mem_speed = 1600, + .density = 1, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* MT41K128M16JT-125 (2Gb density) */ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { .mem_speed = 1600, .density = 2, @@ -202,7 +216,7 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { .trasmin = 3500, }; -/* MT41K256M16HA-125 */ +/* MT41K256M16HA-125 (4Gb density) */ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { .mem_speed = 1600, .density = 4, @@ -219,6 +233,44 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { /* * calibration - these are the various CPU/DDR3 combinations we support */ +static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x004C004E, + .p0_mpwldectrl1 = 0x00440044, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42440247, + .p0_mpdgctrl1 = 0x02310232, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x45424746, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x33382C31, +}; + +static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001B0016, + .p0_mpwldectrl1 = 0x000C000E, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x4324033A, + .p0_mpdgctrl1 = 0x00000000, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x40403438, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x40403D36, +}; + +static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00420043, + .p0_mpwldectrl1 = 0x0016001A, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x4238023B, + .p0_mpdgctrl1 = 0x00000000, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x40404849, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x40402E2F, +}; static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { /* write leveling calibration determine */ @@ -297,6 +349,19 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { .p0_mpwrdlctl = 0x32363934, }; +static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0X00480047, + .p0_mpwldectrl1 = 0X003D003F, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0X423E0241, + .p0_mpdgctrl1 = 0X022B022C, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0X49454A4A, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0X2E372C32, +}; + static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0X00220021, @@ -340,6 +405,7 @@ static void spl_dram_init(int width, int size_mb, int board_model) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ }; /* @@ -349,25 +415,60 @@ static void spl_dram_init(int width, int size_mb, int board_model) * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) * mx6_ddr_cfg - chip specific timing/layout details */ - if (width == 32 && size_mb == 512) { + if (width == 16 && size_mb == 128) { + mem = &mt41k64m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + ; + else + calib = &mx6sdl_64x16_mmdc_calib; + debug("1gB density\n"); + } else if (width == 16 && size_mb == 256) { + /* 1x 2Gb density chip - same calib as 2x 2Gb */ mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_128x32_mmdc_calib; else calib = &mx6sdl_128x32_mmdc_calib; debug("2gB density\n"); - } else if (width == 64 && size_mb == 1024) { + } else if (width == 16 && size_mb == 512) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x16_mmdc_calib; + else + calib = &mx6sdl_256x16_mmdc_calib; + debug("4gB density\n"); + } else if (width == 32 && size_mb == 256) { + /* Same calib as width==16, size==128 */ + mem = &mt41k64m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + ; + else + calib = &mx6sdl_64x16_mmdc_calib; + debug("1gB density\n"); + } else if (width == 32 && size_mb == 512) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_128x64_mmdc_calib; + calib = &mx6dq_128x32_mmdc_calib; else - calib = &mx6sdl_128x64_mmdc_calib; + calib = &mx6sdl_128x32_mmdc_calib; debug("2gB density\n"); - } else if (width == 32 && size_mb == 1024) { + } else if (width == 32 && size_mb == 1024) { mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_256x32_mmdc_calib; + else + calib = &mx6sdl_256x32_mmdc_calib; debug("4gB density\n"); + } else if (width == 64 && size_mb == 512) { + mem = &mt41k64m16jt_125; + debug("1gB density\n"); + } else if (width == 64 && size_mb == 1024) { + mem = &mt41k128m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_128x64_mmdc_calib; + else + calib = &mx6sdl_128x64_mmdc_calib; + debug("2gB density\n"); } else if (width == 64 && size_mb == 2048) { mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q)) @@ -375,12 +476,14 @@ static void spl_dram_init(int width, int size_mb, int board_model) debug("4gB density\n"); } - if (!mem) { - puts("Error: Invalid Memory Configuration\n"); - hang(); - } - if (!calib) { - puts("Error: Invalid Board Calibration Configuration\n"); + if (!(mem && calib)) { + puts("Error: Invalid Calibration/Board Configuration\n"); + printf("MEM : %s\n", mem ? "OKAY" : "NULL"); + printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); + printf("CPUTYPE: %s\n", + is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); + printf("SIZE_MB: %d\n", size_mb); + printf("WIDTH : %d\n", width); hang(); } diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index af12711ac2..daff375e40 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -109,6 +109,7 @@ enum { GW52xx, GW53xx, GW54xx, + GW551x, GW552x, GW_UNKNOWN, GW_BADCRC, diff --git a/board/solidrun/mx6cuboxi/Kconfig b/board/solidrun/mx6cuboxi/Kconfig new file mode 100644 index 0000000000..31d88b2dd4 --- /dev/null +++ b/board/solidrun/mx6cuboxi/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX6CUBOXI + +config SYS_BOARD + default "mx6cuboxi" + +config SYS_VENDOR + default "solidrun" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "mx6cuboxi" + +endif diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS new file mode 100644 index 0000000000..a3506c2f8f --- /dev/null +++ b/board/solidrun/mx6cuboxi/MAINTAINERS @@ -0,0 +1,6 @@ +MX6CUBOXI BOARD +M: Fabio Estevam <fabio.estevam@freescale.com> +S: Maintained +F: board/solidrun/mx6cuboxi/ +F: include/configs/mx6cuboxi.h +F: configs/mx6cuboxi_defconfig diff --git a/board/solidrun/mx6cuboxi/Makefile b/board/solidrun/mx6cuboxi/Makefile new file mode 100644 index 0000000000..df425ac93e --- /dev/null +++ b/board/solidrun/mx6cuboxi/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6cuboxi.o diff --git a/board/solidrun/mx6cuboxi/README b/board/solidrun/mx6cuboxi/README new file mode 100644 index 0000000000..3050c48840 --- /dev/null +++ b/board/solidrun/mx6cuboxi/README @@ -0,0 +1,21 @@ +How to use U-boot on Solid-run mx6 hummingboard +----------------------------------------------- + +- Build U-boot for hummingboard: + +$ make mrproper +$ make mx6cuboxi_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot.img image into the SD card: + +sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Insert the SD card in the hummingboard, power it up and U-boot messages +should come up. diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c new file mode 100644 index 0000000000..d3a32c1663 --- /dev/null +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -0,0 +1,510 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> + * + * Based on SPL code from Solidrun tree, which is: + * Author: Tungyi Lin <tungyilin1127@gmail.com> + * + * Derived from EDM_CF_IMX6 code by TechNexion,Inc + * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ETH_PHY_RESET IMX_GPIO_NR(4, 15) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const hb_cbi_sense[] = { + /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ + IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* uSDHC2 is always present */ +} + +int board_mmc_init(bd_t *bis) +{ + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +static iomux_v3_cfg_t const enet_pads[] = { + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* AR8035 reset */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), + /* AR8035 interrupt */ + IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* GPIO16 -> AR8035 25MHz */ + IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), +}; + +static void setup_iomux_enet(void) +{ + SETUP_IOMUX_PADS(enet_pads); + + gpio_direction_output(ETH_PHY_RESET, 0); + mdelay(2); + gpio_set_value(ETH_PHY_RESET, 1); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + int ret = enable_fec_anatop_clock(ENET_25MHZ); + if (ret) + return ret; + + /* set gpr1[ENET_CLK_SEL] */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +static bool is_hummingboard(void) +{ + int val1, val2; + + SETUP_IOMUX_PADS(hb_cbi_sense); + + gpio_direction_input(IMX_GPIO_NR(4, 9)); + gpio_direction_input(IMX_GPIO_NR(3, 4)); + + val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); + val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); + + /* + * Machine selection - + * Machine val1, val2 + * ------------------------- + * HB rev 3.x x 0 + * CBi 0 1 + * HB 1 1 + */ + + if (val2 == 0) + return true; + else if (val1 == 0) + return false; + else + return true; +} + +int checkboard(void) +{ + if (is_hummingboard()) + puts("Board: MX6 Hummingboard\n"); + else + puts("Board: MX6 Cubox-i\n"); + + return 0; +} + +static bool is_mx6q(void) +{ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + return true; + else + return false; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (is_hummingboard()) + setenv("board_name", "HUMMINGBOARD"); + else + setenv("board_name", "CUBOXI"); + + if (is_mx6q()) + setenv("board_rev", "MX6Q"); + else + setenv("board_rev", "MX6DL"); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <asm/arch/mx6-ddr.h> +static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { + .dram_sdclk_0 = 0x00000028, + .dram_sdclk_1 = 0x00000028, + .dram_cas = 0x00000028, + .dram_ras = 0x00000028, + .dram_reset = 0x000c0028, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_sdqs4 = 0x00000028, + .dram_sdqs5 = 0x00000028, + .dram_sdqs6 = 0x00000028, + .dram_sdqs7 = 0x00000028, + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_dqm4 = 0x00000028, + .dram_dqm5 = 0x00000028, + .dram_dqm6 = 0x00000028, + .dram_dqm7 = 0x00000028, +}; + +static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000028, + .grp_ctlds = 0x00000028, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_b4ds = 0x00000028, + .grp_b5ds = 0x00000028, + .grp_b6ds = 0x00000028, + .grp_b7ds = 0x00000028, +}; + +/* microSOM with Dual processor and 1GB memory */ +static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpwldectrl1 = 0x00000000, + .p1_mpwldectrl0 = 0x00000000, + .p1_mpwldectrl1 = 0x00000000, + .p0_mpdgctrl0 = 0x0314031c, + .p0_mpdgctrl1 = 0x023e0304, + .p1_mpdgctrl0 = 0x03240330, + .p1_mpdgctrl1 = 0x03180260, + .p0_mprddlctl = 0x3630323c, + .p1_mprddlctl = 0x3436283a, + .p0_mpwrdlctl = 0x36344038, + .p1_mpwrdlctl = 0x422a423c, +}; + +/* microSOM with Quad processor and 2GB memory */ +static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpwldectrl1 = 0x00000000, + .p1_mpwldectrl0 = 0x00000000, + .p1_mpwldectrl1 = 0x00000000, + .p0_mpdgctrl0 = 0x0314031c, + .p0_mpdgctrl1 = 0x023e0304, + .p1_mpdgctrl0 = 0x03240330, + .p1_mpdgctrl1 = 0x03180260, + .p0_mprddlctl = 0x3630323c, + .p1_mprddlctl = 0x3436283a, + .p0_mpwrdlctl = 0x36344038, + .p1_mpwrdlctl = 0x422a423c, +}; + +/* microSOM with Solo processor and 512MB memory */ +static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = { + .p0_mpwldectrl0 = 0x0045004D, + .p0_mpwldectrl1 = 0x003A0047, + .p0_mpdgctrl0 = 0x023C0224, + .p0_mpdgctrl1 = 0x02000220, + .p0_mprddlctl = 0x44444846, + .p0_mpwrdlctl = 0x32343032, +}; + +/* microSOM with Dual lite processor and 1GB memory */ +static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = { + .p0_mpwldectrl0 = 0x0045004D, + .p0_mpwldectrl1 = 0x003A0047, + .p1_mpwldectrl0 = 0x001F001F, + .p1_mpwldectrl1 = 0x00210035, + .p0_mpdgctrl0 = 0x023C0224, + .p0_mpdgctrl1 = 0x02000220, + .p1_mpdgctrl0 = 0x02200220, + .p1_mpdgctrl1 = 0x02000220, + .p0_mprddlctl = 0x44444846, + .p1_mprddlctl = 0x4042463C, + .p0_mpwrdlctl = 0x32343032, + .p1_mpwrdlctl = 0x36363430, +}; + +static struct mx6_ddr3_cfg mem_ddr_2g = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, +}; + +static struct mx6_ddr3_cfg mem_ddr_4g = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +/* + * This section requires the differentiation between Solidrun mx6 boards, but + * for now, it will configure only for the mx6dual hummingboard version. + */ +static void spl_dram_init(int width) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus: 0=16, 1=32, 2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + .ncs = 1, /* single chip select */ + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) + mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); + else + mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); + + if (is_cpu_type(MXC_CPU_MX6D)) + mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); + else if (is_cpu_type(MXC_CPU_MX6Q)) + mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); + else if (is_cpu_type(MXC_CPU_MX6DL)) + mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); + else if (is_cpu_type(MXC_CPU_MX6SOLO)) + mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + if (is_cpu_type(MXC_CPU_MX6SOLO)) + spl_dram_init(32); + else + spl_dram_init(64); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 3110405a1b..375cd0b6fe 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -109,7 +109,7 @@ int board_eth_init(bd_t *bis) XILINX_AXIDMA_BASEADDR); #endif -#ifdef CONFIG_XILINX_EMACLITE +#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) u32 txpp = 0; u32 rxpp = 0; # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG diff --git a/common/fdt_support.c b/common/fdt_support.c index 8266bca7d6..c5ed5ad89e 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1560,3 +1560,32 @@ int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, return 0; } + +/* + * Update native-mode in display-timings from display environment variable. + * The node to update are specified by path. + */ +int fdt_fixup_display(void *blob, const char *path, const char *display) +{ + int off, toff; + + if (!display || !path) + return -FDT_ERR_NOTFOUND; + + toff = fdt_path_offset(blob, path); + if (toff >= 0) + toff = fdt_subnode_offset(blob, toff, "display-timings"); + if (toff < 0) + return toff; + + for (off = fdt_first_subnode(blob, toff); + off >= 0; + off = fdt_next_subnode(blob, off)) { + uint32_t h = fdt_get_phandle(blob, off); + debug("%s:0x%x\n", fdt_get_name(blob, off, NULL), + fdt32_to_cpu(h)); + if (strcasecmp(fdt_get_name(blob, off, NULL), display) == 0) + return fdt_setprop_u32(blob, toff, "native-mode", h); + } + return toff; +} diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig new file mode 100644 index 0000000000..4c2f0e0e4e --- /dev/null +++ b/configs/mx6cuboxi_defconfig @@ -0,0 +1,6 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" +CONFIG_ARM=y +CONFIG_TARGET_MX6CUBOXI=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/drivers/core/device.c b/drivers/core/device.c index 3b77d231d3..85fd1fc735 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -135,7 +135,7 @@ int device_bind(struct udevice *parent, const struct driver *drv, return 0; fail_child_post_bind: - if (IS_ENABLED(DM_DEVICE_REMOVE)) { + if (IS_ENABLED(CONFIG_DM_DEVICE_REMOVE)) { if (drv->unbind && drv->unbind(dev)) { dm_warn("unbind() method failed on dev '%s' on error path\n", dev->name); @@ -143,14 +143,14 @@ fail_child_post_bind: } fail_bind: - if (IS_ENABLED(DM_DEVICE_REMOVE)) { + if (IS_ENABLED(CONFIG_DM_DEVICE_REMOVE)) { if (uclass_unbind_device(dev)) { dm_warn("Failed to unbind dev '%s' on error path\n", dev->name); } } fail_uclass_bind: - if (IS_ENABLED(DM_DEVICE_REMOVE)) { + if (IS_ENABLED(CONFIG_DM_DEVICE_REMOVE)) { list_del(&dev->sibling_node); if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) { free(dev->parent_platdata); diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 04e939d6c1..7de817324b 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -277,6 +277,7 @@ int uclass_get_device_tail(struct udevice *dev, int ret, if (ret) return ret; + assert(dev); ret = device_probe(dev); if (ret) return ret; @@ -342,6 +343,8 @@ int uclass_first_device(enum uclass_id id, struct udevice **devp) *devp = NULL; ret = uclass_find_first_device(id, &dev); + if (!dev) + return 0; return uclass_get_device_tail(dev, ret, devp); } @@ -352,6 +355,8 @@ int uclass_next_device(struct udevice **devp) *devp = NULL; ret = uclass_find_next_device(&dev); + if (!dev) + return 0; return uclass_get_device_tail(dev, ret, devp); } diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index fd110b3ddc..3d376d7580 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -255,7 +255,6 @@ void debug_uart_init(void) */ baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); - baud_divisor = 13; serial_out_shift(&com_port->ier, CONFIG_DEBUG_UART_SHIFT, CONFIG_SYS_NS16550_IER); serial_out_shift(&com_port->mcr, CONFIG_DEBUG_UART_SHIFT, UART_MCRVAL); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c4c112c5ae..357a33511f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -35,3 +35,19 @@ config SANDBOX_SPI sandbox,filename = "spi.bin"; }; }; + +config DESIGNWARE_SPI + bool "Designware SPI driver" + depends on DM_SPI + help + Enable the Designware SPI driver. This driver can be used to + access the SPI NOR flash on platforms embedding this Designware + IP core. + +config CADENCE_QSPI + bool "Cadence QSPI driver" + depends on DM_SPI + help + Enable the Cadence Quad-SPI (QSPI) driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Cadence IP core. diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 9bc325003a..fcfc1b3603 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -99,6 +99,7 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 #define CONFIG_I2C_PMIC 1 +#define CONFIG_I2C_EDID /* MMC Configs */ #define CONFIG_FSL_ESDHC @@ -112,15 +113,12 @@ /* Filesystem support */ #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_UBIFS #define CONFIG_DOS_PARTITION -/* Network config - Allow larger/faster download for TFTP/NFS */ -#define CONFIG_IP_DEFRAG -#define CONFIG_TFTP_BLOCKSIZE 4096 -#define CONFIG_NFS_READ_SIZE 4096 - /* * SATA Configs */ @@ -180,10 +178,10 @@ /* Ethernet support */ #define CONFIG_FEC_MXC +#define CONFIG_E1000 #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_PHYLIB #define CONFIG_ARP_TIMEOUT 200UL @@ -209,6 +207,18 @@ #define CONFIG_NETCONSOLE #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +/* USB Mass Storage Gadget */ +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* Netchip IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Gateworks" + /* Framebuffer and LCD */ #define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 @@ -317,6 +327,7 @@ "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \ #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ "bootdevs=usb mmc sata flash\0" \ HWCONFIG_DEFAULT \ @@ -327,28 +338,30 @@ \ "fdt_high=0xffffffff\0" \ "fdt_addr=0x18000000\0" \ + "initrd_high=0xffffffff\0" \ + "bootdir=boot\0" \ "loadfdt=" \ - "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ - "echo Loaded DTB from boot/${fdt_file}; " \ - "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \ - "echo Loaded DTB from boot/${fdt_file1}; " \ - "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \ - "echo Loaded DTB from boot/${fdt_file2}; " \ + "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ "fi\0" \ \ - "script=boot/6x_bootscript-ventana\0" \ + "script=6x_bootscript-ventana\0" \ "loadscript=" \ - "if ${fsload} ${loadaddr} ${script}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ "source; " \ "fi\0" \ \ - "uimage=boot/uImage\0" \ + "uimage=uImage\0" \ "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \ "mmc_boot=" \ "setenv fsload 'ext2load mmc 0:1'; " \ "mmc dev 0 && mmc rescan && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/mmcblk0p1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -362,7 +375,7 @@ "sata_boot=" \ "setenv fsload 'ext2load sata 0:1'; sata init && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -375,7 +388,7 @@ "usb_boot=" \ "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -418,8 +431,8 @@ #else #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ "tftp ${loadaddr} ${image_rootfs} && " \ "nand erase.part rootfs && " \ @@ -427,12 +440,21 @@ \ "flash_boot=" \ "setenv fsload 'ubifsload'; " \ - "ubi part rootfs && ubifsmount ubi0:rootfs; " \ + "ubi part rootfs; " \ + "if ubi check boot; then " \ + "ubifsmount ubi0:boot; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=squashfs,ubifs; " \ + "setenv bootdir; " \ + "elif ubi check rootfs; then " \ + "ubifsmount ubi0:rootfs; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=ubifs; " \ + "fi; " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ - "root=ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs ${video} ${extra}; " \ + "root=${root} ${video} ${extra}; " \ "if run loadfdt && fdt addr ${fdt_addr}; then " \ "ubifsumount; " \ "bootm ${loadaddr} - ${fdt_addr}; " \ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h new file mode 100644 index 0000000000..b569f344eb --- /dev/null +++ b/include/configs/mx6cuboxi.h @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the SolidRun mx6 based boards + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6CUBOXI_CONFIG_H +#define __MX6CUBOXI_CONFIG_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include "mx6_common.h" + +#define CONFIG_MX6 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_IMX6_THERMAL +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_UART +#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_NO_FLASH + +/* Command definition */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONSOLE_DEV "ttymxc0" +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "fdtfile=undefined\0" \ + "fdt_addr_r=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "findfdt="\ + "if test $board_name = HUMMINGBOARD && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-hummingboard.dtb; fi; " \ + "if test $board_name = HUMMINGBOARD && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-hummingboard.dtb; fi; " \ + "if test $board_name = CUBOXI && test $board_rev = MX6Q ; then " \ + "setenv fdtfile imx6q-cubox-i.dtb; fi; " \ + "if test $board_name = CUBOXI && test $board_rev = MX6DL ; then " \ + "setenv fdtfile imx6dl-cubox-i.dtb; fi; " \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * 64 * 1024) + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_CACHE + +#endif /* __MX6CUBOXI_CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 883d8a771a..eaa2c2cd36 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -143,6 +143,9 @@ #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) #define CONFIG_BMP_16BPP #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_CMD_HDMIDETECT diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 1ecd56f42a..41bb52bc8c 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -40,7 +40,7 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) @@ -292,6 +292,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) +#define CONFIG_SPL_MAX_SIZE (64 * 1024) #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ #define CONFIG_CRC32_VERIFY @@ -304,6 +305,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +/* + * Stack setup + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + #ifdef CONFIG_SPL_BUILD #undef CONFIG_PARTITIONS #endif diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 99c5f82aa0..012fa1c242 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -35,16 +35,6 @@ #define PHYS_SDRAM_SIZE (1024u * SZ_1M) #endif -#if defined(CONFIG_MBA6) - -#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) -#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" -#endif - -#endif - #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_GENERIC_BOARD @@ -86,11 +76,6 @@ /* I2C SYSMON (LM75) */ #define CONFIG_DTT_LM75 -#if defined(CONFIG_MBA6) -#define CONFIG_DTT_SENSORS { 0, 1 } -#else -#define CONFIG_DTT_SENSORS { 0 } -#endif #define CONFIG_DTT_MAX_TEMP 70 #define CONFIG_DTT_MIN_TEMP -30 #define CONFIG_DTT_HYSTERESIS 3 @@ -148,38 +133,12 @@ #define CONFIG_PHYLIB #define CONFIG_MII -#if defined(CONFIG_MBA6) - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_FEC_MXC_PHYADDR 0x03 -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_KSZ9031 - -#else - -#error "define PHY to use for your baseboard" - -#endif - #define CONFIG_ARP_TIMEOUT 200UL /* Network config - Allow larger/faster download for TFTP/NFS */ #define CONFIG_IP_DEFRAG #define CONFIG_TFTP_BLOCKSIZE 4096 #define CONFIG_NFS_READ_SIZE 4096 -#if defined(CONFIG_MBA6) - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_CONSOLE_DEV "ttymxc1" - -#else - -#error "define baseboard specific things (uart, number of SD-card slots)" - -#endif - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -493,4 +452,20 @@ #define CONFIG_CMD_CACHE #endif +/* + * All the defines above are for the TQMa6 SoM + * + * Now include the baseboard specific configuration + */ +#ifdef CONFIG_MBA6 +#include "tqma6_mba6.h" +#else +#error "No baseboard for the TQMa6 defined!" +#endif + +/* Support at least the sensor on TQMa6 SOM */ +#if !defined(CONFIG_DTT_SENSORS) +#define CONFIG_DTT_SENSORS { 0 } +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h new file mode 100644 index 0000000000..88c00679b6 --- /dev/null +++ b/include/configs/tqma6_mba6.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com> + * + * Configuration settings for the TQ Systems TQMa6<Q,S> module. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_TQMA6_MBA6_H +#define __CONFIG_TQMA6_MBA6_H + +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-mba6x.dtb" +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q) +#define CONFIG_DEFAULT_FDT_FILE "imx6q-mba6x.dtb" +#endif + +#define CONFIG_DTT_SENSORS { 0, 1 } + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC_PHYADDR 0x03 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_KSZ9031 + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" + +#endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/fdt_support.h b/include/fdt_support.h index ae5e8a3ef6..5d4f28dc78 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -47,6 +47,19 @@ int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, const void *val, int len, int create); void fdt_fixup_qe_firmware(void *fdt); +/** + * Update native-mode property of display-timings node to the phandle + * of the timings matching a display by name (case insensitive). + * + * see kernel Documentation/devicetree/bindings/video/display-timing.txt + * + * @param blob FDT blob to update + * @param path path within dt + * @param display name of display timing to match + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_fixup_display(void *blob, const char *path, const char *display); + #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) void fdt_fixup_dr_usb(void *blob, bd_t *bd); #else diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 07199b4f89..8e7a22d020 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -180,7 +180,7 @@ enum { #define LDOB_3_30V 15 #define LDO_VOL_MASK 0xf -#define LDO_EN 4 +#define LDO_EN (1 << 4) /* * Boost Regulator |