diff options
56 files changed, 1796 insertions, 363 deletions
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index f3eadb4db3..7fcb5d2094 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board" +config TARGET_ODROID_XU3 + bool "Exynos5422 Odroid board" + select OF_CONTROL + config TARGET_ARNDALE bool "Exynos5250 Arndale board" select CPU_V7_HAS_NONSEC diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135beb..b31c13b14b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index) if (sel == 0x3) sclk = get_pll_clk(MPLL); + else if (sel == 0x4) + sclk = get_pll_clk(SPLL); else if (sel == 0x6) sclk = get_pll_clk(EPLL); else diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 93a02adcec..b6983e60d7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -746,10 +746,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_SATA_CLK: return get_ahb_clk(); default: + printf("Unsupported MXC CLK: %d\n", clk); break; } - return -1; + return 0; } /* diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 73cffd3a8d..7873c38e2b 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -9,6 +9,7 @@ #include <altera.h> #include <miiphy.h> #include <netdev.h> +#include <watchdog.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <asm/arch/dwmmc.h> @@ -150,14 +151,23 @@ static inline void socfpga_fpga_add(void) {} int arch_cpu_init(void) { +#ifdef CONFIG_HW_WATCHDOG + /* + * In case the watchdog is enabled, make sure to (re-)configure it + * so that the defined timeout is valid. Otherwise the SPL (Perloader) + * timeout value is still active which might too short for Linux + * booting. + */ + hw_watchdog_init(); +#else /* * If the HW watchdog is NOT enabled, make sure it is not running, * for example because it was enabled in the preloader. This might * trigger a watchdog-triggered reboot of Linux kernel later. */ -#ifndef CONFIG_HW_WATCHDOG socfpga_watchdog_reset(); #endif + return 0; } diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 97602990aa..0556e4b350 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -65,6 +65,13 @@ config DRAM_INIT bool default SPL_BUILD +config CMD_DDRPHY_DUMP + bool "Enable dump command of DDR PHY parameters" + depends on !SPL_BUILD + help + The command "ddrphy" shows the resulting parameters of DDR PHY + training; it is useful for the evaluation of DDR PHY training. + choice prompt "DDR3 Frequency select" depends on DRAM_INIT diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile index 4a7b8a9d08..05462320b5 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -10,11 +10,13 @@ obj-y += reset.o obj-y += cache_uniphier.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o obj-y += dram_init.o +obj-$(CONFIG_DRAM_INIT) += ddrphy_training.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-$(CONFIG_UNIPHIER_SMP) += smp.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o +obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o obj-y += board_common.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o diff --git a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c b/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c new file mode 100644 index 0000000000..431d9010f1 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ddrphy-regs.h> + +/* Select either decimal or hexadecimal */ +#if 1 +#define PRINTF_FORMAT "%2d" +#else +#define PRINTF_FORMAT "%02x" +#endif +/* field separator */ +#define FS " " + +static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index) +{ + return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f; +} + +static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *)) +{ + int ch, p, dx; + struct ddrphy __iomem *phy; + + for (ch = 0; ch < NR_DDRCH; ch++) { + for (p = 0; p < NR_DDRPHY_PER_CH; p++) { + phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p); + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + printf("CH%dP%dDX%d:", ch, p, dx); + (*callback)(&phy->dx[dx]); + printf("\n"); + } + } + } +} + +static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + + for (i = 0; i < 10; i++) + printf(FS PRINTF_FORMAT, read_bdl(dx, i)); + + printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff); +} + +void wbdl_dump(void) +{ + printf("\n--- Write Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); + + dump_loop(&__wbdl_dump); +} + +static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + + for (i = 15; i < 24; i++) + printf(FS PRINTF_FORMAT, read_bdl(dx, i)); + + printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff); +} + +void rbdl_dump(void) +{ + printf("\n--- Read Bit Delay Line ---\n"); + printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); + + dump_loop(&__rbdl_dump); +} + +static void __wld_dump(struct ddrphy_datx8 __iomem *dx) +{ + int rank; + u32 lcdlr0 = readl(&dx->lcdlr[0]); + u32 gtr = readl(&dx->gtr); + + for (rank = 0; rank < 4; rank++) { + u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ + u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ + + printf(FS PRINTF_FORMAT "%sT", wld, + wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1"); + } +} + +void wld_dump(void) +{ + printf("\n--- Write Leveling Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__wld_dump); +} + +static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx) +{ + int rank; + u32 lcdlr2 = readl(&dx->lcdlr[2]); + u32 gtr = readl(&dx->gtr); + + for (rank = 0; rank < 4; rank++) { + u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ + u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ + + printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl); + } +} + +void dqsgd_dump(void) +{ + printf("\n--- DQS Gating Delay ---\n"); + printf(" Rank0 Rank1 Rank2 Rank3\n"); + + dump_loop(&__dqsgd_dump); +} + +static void __mdl_dump(struct ddrphy_datx8 __iomem *dx) +{ + int i; + u32 mdl = readl(&dx->mdlr); + for (i = 0; i < 3; i++) + printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); +} + +void mdl_dump(void) +{ + printf("\n--- Master Delay Line ---\n"); + printf(" IPRD TPRD MDLD\n"); + + dump_loop(&__mdl_dump); +} + +#define REG_DUMP(x) \ + { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \ + p - (u32 *)phy, #x, p, readl(p)); } + +void reg_dump(void) +{ + int ch, p; + struct ddrphy __iomem *phy; + + printf("\n--- DDR PHY registers ---\n"); + + for (ch = 0; ch < NR_DDRCH; ch++) { + for (p = 0; p < NR_DDRPHY_PER_CH; p++) { + printf("== Ch%d, PHY%d ==\n", ch, p); + printf(" No: Name : Address : Data\n"); + + phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p); + + REG_DUMP(ridr); + REG_DUMP(pir); + REG_DUMP(pgcr[0]); + REG_DUMP(pgcr[1]); + REG_DUMP(pgsr[0]); + REG_DUMP(pgsr[1]); + REG_DUMP(pllcr); + REG_DUMP(ptr[0]); + REG_DUMP(ptr[1]); + REG_DUMP(ptr[2]); + REG_DUMP(ptr[3]); + REG_DUMP(ptr[4]); + REG_DUMP(acmdlr); + REG_DUMP(acbdlr); + REG_DUMP(dxccr); + REG_DUMP(dsgcr); + REG_DUMP(dcr); + REG_DUMP(dtpr[0]); + REG_DUMP(dtpr[1]); + REG_DUMP(dtpr[2]); + REG_DUMP(mr0); + REG_DUMP(mr1); + REG_DUMP(mr2); + REG_DUMP(mr3); + REG_DUMP(dx[0].gcr); + REG_DUMP(dx[0].gtr); + REG_DUMP(dx[1].gcr); + REG_DUMP(dx[1].gtr); + } + } +} + +static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd = argv[1]; + + if (argc == 1) + cmd = "all"; + + if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) + wbdl_dump(); + + if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) + rbdl_dump(); + + if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) + wld_dump(); + + if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) + dqsgd_dump(); + + if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) + mdl_dump(); + + if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) + reg_dump(); + + return 0; +} + +U_BOOT_CMD( + ddr, 2, 1, do_ddr, + "UniPhier DDR PHY parameters dumper", + "- dump all of the followings\n" + "ddr wbdl - dump Write Bit Delay\n" + "ddr rbdl - dump Read Bit Delay\n" + "ddr wld - dump Write Leveling\n" + "ddr dqsgd - dump DQS Gating Delay\n" + "ddr mdl - dump Master Delay Line\n" + "ddr reg - dump registers\n" +); diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c index eef9f39840..3561b40a33 100644 --- a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c +++ b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/arch/boot-device.h> +#include <asm/arch/sbc-regs.h> static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -15,6 +16,8 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) mode_sel = get_boot_mode_sel(); + printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); + puts("Boot Mode Pin:\n"); for (table = boot_device_table; strlen(table->info); table++) { diff --git a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c b/arch/arm/cpu/armv7/uniphier/ddrphy_training.c new file mode 100644 index 0000000000..cc8b8ad648 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ddrphy_training.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ddrphy-regs.h> + +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) +{ + int dx; + u32 __iomem tmp, *p; + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + p = &phy->dx[dx].gcr; + + tmp = readl(p); + /* Specify the rank that should be write leveled */ + tmp &= ~DXGCR_WLRKEN_MASK; + tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK; + writel(tmp, p); + } + + p = &phy->dtcr; + + tmp = readl(p); + /* Specify the rank used during data bit deskew and eye centering */ + tmp &= ~DTCR_DTRANK_MASK; + tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK; + /* Use Multi-Purpose Register for DQS gate training */ + tmp |= DTCR_DTMPR; + /* Specify the rank enabled for data-training */ + tmp &= ~DTCR_RNKEN_MASK; + tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + writel(tmp, p); +} + +struct ddrphy_init_sequence { + char *description; + u32 init_flag; + u32 done_flag; + u32 err_flag; +}; + +static struct ddrphy_init_sequence init_sequence[] = { + { + "DRAM Initialization", + PIR_DRAMRST | PIR_DRAMINIT, + PGSR0_DIDONE, + PGSR0_DIERR + }, + { + "Write Leveling", + PIR_WL, + PGSR0_WLDONE, + PGSR0_WLERR + }, + { + "Read DQS Gate Training", + PIR_QSGATE, + PGSR0_QSGDONE, + PGSR0_QSGERR + }, + { + "Write Leveling Adjustment", + PIR_WLADJ, + PGSR0_WLADONE, + PGSR0_WLAERR + }, + { + "Read Bit Deskew", + PIR_RDDSKW, + PGSR0_RDDONE, + PGSR0_RDERR + }, + { + "Write Bit Deskew", + PIR_WRDSKW, + PGSR0_WDDONE, + PGSR0_WDERR + }, + { + "Read Eye Training", + PIR_RDEYE, + PGSR0_REDONE, + PGSR0_REERR + }, + { + "Write Eye Training", + PIR_WREYE, + PGSR0_WEDONE, + PGSR0_WEERR + } +}; + +int ddrphy_training(struct ddrphy __iomem *phy) +{ + int i; + u32 pgsr0; + u32 init_flag = PIR_INIT; + u32 done_flag = PGSR0_IDONE; + int timeout = 50000; /* 50 msec is long enough */ +#ifdef DISPLAY_ELAPSED_TIME + ulong start = get_timer(0); +#endif + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + init_flag |= init_sequence[i].init_flag; + done_flag |= init_sequence[i].done_flag; + } + + writel(init_flag, &phy->pir); + + do { + if (--timeout < 0) { +#ifndef CONFIG_SPL_BUILD + printf("%s: error: timeout during DDR training\n", + __func__); +#endif + return -1; + } + udelay(1); + pgsr0 = readl(&phy->pgsr[0]); + } while ((pgsr0 & done_flag) != done_flag); + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + if (pgsr0 & init_sequence[i].err_flag) { +#ifndef CONFIG_SPL_BUILD + printf("%s: error: %s failed\n", __func__, + init_sequence[i].description); +#endif + return -1; + } + } + +#ifdef DISPLAY_ELAPSED_TIME + printf("%s: info: elapsed time %ld msec\n", get_timer(start)); +#endif + + return 0; +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index 5d682d3ca3..8794629b2a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -8,4 +8,4 @@ obj-y += boot-mode.o obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ clkrst_init.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o -obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c new file mode 100644 index 0000000000..60fc5ad6ea --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/ddrphy-regs.h> + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8253c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a82dbc0, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000800, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c index ebcbaabf65..87889160a7 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/umc-regs.h> +#include <asm/arch/ddrphy-regs.h> static inline void umc_start_ssif(void __iomem *ssif_base) { @@ -125,6 +126,8 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); umc_dram_init_start(dramcont0); umc_dram_init_start(dramcont1); @@ -133,8 +136,18 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index fd1c432f4f..cee78781f6 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -7,4 +7,4 @@ obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o obj-y += boot-mode.o obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o -obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c new file mode 100644 index 0000000000..c5d1f606cf --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/ddrphy-regs.h> + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000000, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c index 328b2f4d9a..1973ab04c2 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/umc-regs.h> +#include <asm/arch/ddrphy-regs.h> static inline void umc_start_ssif(void __iomem *ssif_base) { @@ -94,6 +95,10 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); umc_dram_init_start(dramcont0); umc_dram_init_start(dramcont1); @@ -102,12 +107,32 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + writel(0x00000103, dramcont0 + UMC_DIOCTLA); + ddrphy_init(phy0_1, freq, size_ch0); + + ddrphy_prepare_training(phy0_1, 1); + ddrphy_training(phy0_1); + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 0); + ddrphy_training(phy1_0); + writel(0x00000103, dramcont1 + UMC_DIOCTLA); + ddrphy_init(phy1_1, freq, size_ch1); + + ddrphy_prepare_training(phy1_1, 1); + ddrphy_training(phy1_1); + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index 5d682d3ca3..8794629b2a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -8,4 +8,4 @@ obj-y += boot-mode.o obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ clkrst_init.o obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o -obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c new file mode 100644 index 0000000000..a5eafef9a8 --- /dev/null +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/ddrphy-regs.h> + +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, &phy->mr3); +#else + writel(0x00000800, &phy->mr3); +#endif + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); +} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c index a44f999fbf..2e0f9aeaa5 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/umc-regs.h> +#include <asm/arch/ddrphy-regs.h> static inline void umc_start_ssif(void __iomem *ssif_base) { @@ -105,6 +106,8 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); umc_dram_init_start(dramcont0); umc_dram_init_start(dramcont1); @@ -113,8 +116,18 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); + ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e6a495cb0d..fac16cc384 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \ - exynos5800-peach-pi.dtb + exynos5800-peach-pi.dtb \ + exynos5422-odroidxu3.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000000..79a7acd7df --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,49 @@ +/* + * Odroid XU3 device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Odroid XU3 based on EXYNOS5422"; + compatible = "samsung,odroidxu3", "samsung,exynos5"; + + aliases { + serial0 = "/serial@12C00000"; + console = "/serial@12C20000"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000 + 0x80000000 0x10000000 + 0x90000000 0x10000000 + 0xa0000000 0x10000000 + 0xb0000000 0xea00000>; + }; + + ehci@12110000 { + samsung,vbus-gpio = <&gpio 0x66 0>; /* X26 */ + }; + + serial@12C20000 { + status="okay"; + }; + + mmc@12200000 { + fifoth_val = <0x201f0020>; + }; + + mmc@12220000 { + fifoth_val = <0x201f0020>; + }; +}; diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 8aedf8e707..2f9d2dbd54 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -63,11 +63,6 @@ reg = <0x20>; compatible = "maxim,max98090-codec"; }; - - edp-lvds-bridge@48 { - compatible = "parade,ps8625"; - reg = <0x48>; - }; }; sound@3830000 { diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c index 34f53872e8..1a632e7203 100644 --- a/arch/arm/imx-common/i2c-mxv7.c +++ b/arch/arm/imx-common/i2c-mxv7.c @@ -73,26 +73,21 @@ static void * const i2c_bases[] = { int setup_i2c(unsigned i2c_index, int speed, int slave_addr, struct i2c_pads_info *p) { - char *name1, *name2; + char name[9]; int ret; if (i2c_index >= ARRAY_SIZE(i2c_bases)) return -EINVAL; - name1 = malloc(9); - name2 = malloc(9); - if (!name1 || !name2) - return -ENOMEM; - - sprintf(name1, "i2c_sda%d", i2c_index); - sprintf(name2, "i2c_scl%d", i2c_index); - ret = gpio_request(p->sda.gp, name1); + snprintf(name, sizeof(name), "i2c_sda%01d", i2c_index); + ret = gpio_request(p->sda.gp, name); if (ret) - goto err_req1; + return ret; - ret = gpio_request(p->scl.gp, name2); + snprintf(name, sizeof(name), "i2c_scl%01d", i2c_index); + ret = gpio_request(p->scl.gp, name); if (ret) - goto err_req2; + goto err_req; /* Enable i2c clock */ ret = enable_i2c_clk(1, i2c_index); @@ -112,11 +107,8 @@ int setup_i2c(unsigned i2c_index, int speed, int slave_addr, err_idle: err_clk: gpio_free(p->scl.gp); -err_req2: +err_req: gpio_free(p->sda.gp); -err_req1: - free(name1); - free(name2); return ret; } diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c index 477c38c1e2..ac6e40e83b 100644 --- a/arch/arm/imx-common/spl.c +++ b/arch/arm/imx-common/spl.c @@ -68,8 +68,10 @@ u32 spl_boot_mode(void) /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: -#ifdef CONFIG_SPL_FAT_SUPPORT +#if defined(CONFIG_SPL_FAT_SUPPORT) return MMCSD_MODE_FS; +#elif defined(CONFIG_SUPPORT_EMMC_BOOT) + return MMCSD_MODE_EMMCBOOT; #else return MMCSD_MODE_RAW; #endif diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 320763fd8c..4968d3dd2e 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -41,7 +41,4 @@ void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); int exynos_lcd_early_init(const void *blob); -/* Initialize the Parade dP<->LVDS bridge if present */ -int parade_init(const void *blob); - #endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h new file mode 100644 index 0000000000..484559c6cd --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h @@ -0,0 +1,172 @@ +/* + * UniPhier DDR PHY registers + * + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_DDRPHY_REGS_H +#define ARCH_DDRPHY_REGS_H + +#include <linux/compiler.h> + +#ifndef __ASSEMBLY__ + +struct ddrphy { + u32 ridr; /* Revision Identification Register */ + u32 pir; /* PHY Initialixation Register */ + u32 pgcr[2]; /* PHY General Configuration Register */ + u32 pgsr[2]; /* PHY General Status Register */ + u32 pllcr; /* PLL Control Register */ + u32 ptr[5]; /* PHY Timing Register */ + u32 acmdlr; /* AC Master Delay Line Register */ + u32 acbdlr; /* AC Bit Delay Line Register */ + u32 aciocr; /* AC I/O Configuration Register */ + u32 dxccr; /* DATX8 Common Configuration Register */ + u32 dsgcr; /* DDR System General Configuration Register */ + u32 dcr; /* DRAM Configuration Register */ + u32 dtpr[3]; /* DRAM Timing Parameters Register */ + u32 mr0; /* Mode Register 0 */ + u32 mr1; /* Mode Register 1 */ + u32 mr2; /* Mode Register 2 */ + u32 mr3; /* Mode Register 3 */ + u32 odtcr; /* ODT Configuration Register */ + u32 dtcr; /* Data Training Configuration Register */ + u32 dtar[4]; /* Data Training Address Register */ + u32 dtdr[2]; /* Data Training Data Register */ + u32 dtedr[2]; /* Data Training Eye Data Register */ + u32 rsv0[13]; /* Reserved */ + u32 dcuar; /* DCU Address Register */ + u32 dcudr; /* DCU Data Register */ + u32 dcurr; /* DCU Run Register */ + u32 dculr; /* DCU Loop Register */ + u32 dcugcr; /* DCU General Configuration Register */ + u32 dcutpr; /* DCU Timing Parameters Register */ + u32 dcusr[2]; /* DCU Status Register */ + u32 rsv1[8]; /* Reserved */ + u32 bistrr; /* BIST Run Register */ + u32 bistwcr; /* BIST Word Count Register */ + u32 bistmskr[3]; /* BIST Mask Register */ + u32 bistlsr; /* BIST LFSR Sed Register */ + u32 bistar[3]; /* BIST Address Register */ + u32 bistudpr; /* BIST User Data Pattern Register */ + u32 bistgsr; /* BIST General Status Register */ + u32 bistwer; /* BIST Word Error Register */ + u32 bistber[4]; /* BIST Bit Error Register */ + u32 bistwcsr; /* BIST Word Count Status Register */ + u32 bistfwr[3]; /* BIST Fail Word Register */ + u32 rsv2[10]; /* Reserved */ + u32 gpr[2]; /* General Purpose Register */ + struct ddrphy_zq { /* ZQ */ + u32 cr[2]; /* Impedance Control Register */ + u32 sr[2]; /* Impedance Status Register */ + } zq[4]; + struct ddrphy_datx8 { /* DATX8 */ + u32 gcr; /* General Configuration Register */ + u32 gsr[2]; /* General Status Register */ + u32 bdlr[5]; /* Bit Delay Line Register */ + u32 lcdlr[3]; /* Local Calibrated Delay Line Register */ + u32 mdlr; /* Master Delay Line Register */ + u32 gtr; /* General Timing Register */ + u32 rsv[3]; /* Reserved */ + } dx[9]; +} __packed; + +#endif /* __ASSEMBLY__ */ + +#define PIR_INIT (1 << 0) /* Initialization Trigger */ +#define PIR_ZCAL (1 << 1) /* Impedance Calibration */ +#define PIR_PLLINIT (1 << 4) /* PLL Initialization */ +#define PIR_DCAL (1 << 5) /* DDL Calibration */ +#define PIR_PHYRST (1 << 6) /* PHY Reset */ +#define PIR_DRAMRST (1 << 7) /* DRAM Reset */ +#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ +#define PIR_WL (1 << 9) /* Write Leveling */ +#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ +#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ +#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ +#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ +#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ +#define PIR_WREYE (1 << 15) /* Write Data Eye Training */ +#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ +#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ +#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ +#define PIR_INITBYP (1 << 31) /* Initialization Bypass */ + +#define PGSR0_IDONE (1 << 0) /* Initialization Done */ +#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ +#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */ +#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */ +#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */ +#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */ +#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */ +#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ +#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ +#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ +#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ +#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ +#define PGSR0_IERR (1 << 16) /* Initialization Error */ +#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ +#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ +#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ +#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ +#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ +#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ +#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ +#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ +#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ +#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ +#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ +#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ +#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) +#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ + +#define DXCCR_DQSRES_OPEN (0 << 5) +#define DXCCR_DQSRES_688_OHM (1 << 5) +#define DXCCR_DQSRES_611_OHM (2 << 5) +#define DXCCR_DQSRES_550_OHM (3 << 5) +#define DXCCR_DQSRES_500_OHM (4 << 5) +#define DXCCR_DQSRES_458_OHM (5 << 5) +#define DXCCR_DQSRES_393_OHM (6 << 5) +#define DXCCR_DQSRES_344_OHM (7 << 5) + +#define DXCCR_DQSNRES_OPEN (0 << 9) +#define DXCCR_DQSNRES_688_OHM (1 << 9) +#define DXCCR_DQSNRES_611_OHM (2 << 9) +#define DXCCR_DQSNRES_550_OHM (3 << 9) +#define DXCCR_DQSNRES_500_OHM (4 << 9) +#define DXCCR_DQSNRES_458_OHM (5 << 9) +#define DXCCR_DQSNRES_393_OHM (6 << 9) +#define DXCCR_DQSNRES_344_OHM (7 << 9) + +#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ +#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) +#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ +#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ +#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) + +#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ +#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) + +/* SoC-specific parameters */ +#define NR_DATX8_PER_DDRPHY 2 + +#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#define NR_DDRPHY_PER_CH 1 +#else +#define NR_DDRPHY_PER_CH 2 +#endif + +#define NR_DDRCH 2 + +#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) + +#ifndef __ASSEMBLY__ +void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); +int ddrphy_training(struct ddrphy __iomem *phy); +#endif + +#endif /* ARCH_DDRPHY_REGS_H */ diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index f1e5eb433a..c7c21f392b 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -112,7 +112,7 @@ static void setup_iomux_spi(void) #ifdef CONFIG_USB_EHCI_MX5 #define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7) #define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27) -#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 2) +#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1) #define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5) static void setup_usb_h1(void) diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 3a5b26dde7..98ccdb785b 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -16,6 +16,7 @@ #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> +#include <usb.h> DECLARE_GLOBAL_DATA_PTR; @@ -213,6 +214,43 @@ int board_eth_init(bd_t *bis) return 0; } +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 1); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 0) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -226,6 +264,10 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index ac3757f074..2f7198d3bf 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -29,6 +29,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <asm/arch/mx6-ddr.h> +#include <usb.h> DECLARE_GLOBAL_DATA_PTR; @@ -537,6 +538,69 @@ int board_eth_init(bd_t *bis) return cpu_eth_init(bis); } +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usb_hc1_pads[] = { + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + + imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, + ARRAY_SIZE(usb_hc1_pads)); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + if (on) + gpio_direction_output(IMX_GPIO_NR(1, 29), 1); + else + gpio_direction_output(IMX_GPIO_NR(1, 29), 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -557,6 +621,10 @@ int board_init(void) #endif setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 3834eec60e..838ea6c0f0 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -308,11 +308,6 @@ int board_init(void) return 0; } -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int checkboard(void) { puts("Board: MX6SLEVK\n"); diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index d6a584745b..97128127fb 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -401,7 +401,7 @@ static void ccgr_init(void) writel(0x0030FC03, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); writel(0x3FF00000, &ccm->CCGR3); - writel(0x00FFF300, &ccm->CCGR4); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ writel(0x0F0000C3, &ccm->CCGR5); writel(0x000003FF, &ccm->CCGR6); } diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile index 6fba17718b..6893b6311d 100644 --- a/board/kosagi/novena/Makefile +++ b/board/kosagi/novena/Makefile @@ -8,4 +8,5 @@ ifdef CONFIG_SPL_BUILD obj-y := novena_spl.o else obj-y := novena.o +obj-$(CONFIG_VIDEO_IPUV3) += video.o endif diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 6add9e5265..69f5be3b9c 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -36,11 +36,9 @@ #include <power/pfuze100_pmic.h> #include <stdio_dev.h> -DECLARE_GLOBAL_DATA_PTR; +#include "novena.h" -#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14) -#define NOVENA_SD_WP IMX_GPIO_NR(1, 2) -#define NOVENA_SD_CD IMX_GPIO_NR(1, 4) +DECLARE_GLOBAL_DATA_PTR; /* * GPIO button @@ -154,87 +152,10 @@ int board_mmc_init(bd_t *bis) } #endif -/* - * Video over HDMI - */ -#if defined(CONFIG_VIDEO_IPUV3) -static void enable_hdmi(struct display_info_t const *dev) -{ - imx_enable_hdmi_phy(); -} - -struct display_info_t const displays[] = { - { - /* HDMI Output */ - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, - .enable = enable_hdmi, - .mode = { - .name = "HDMI", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15385, - .left_margin = 220, - .right_margin = 40, - .upper_margin = 21, - .lower_margin = 7, - .hsync_len = 60, - .vsync_len = 10, - .sync = FB_SYNC_EXT, - .vmode = FB_VMODE_NONINTERLACED - } - } -}; - -size_t display_count = ARRAY_SIZE(displays); - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - enable_ipu_clock(); - imx_setup_hdmi(); - - /* Turn on LDB0,IPU,IPU DI0 clocks */ - setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); - - /* set LDB0, LDB1 clk select to 011/011 */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | - MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK, - (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | - (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); - - setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); - - setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << - MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - - writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | - IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | - IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | - IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | - IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | - IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | - IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | - IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, - &iomux->gpr[2]); - - clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, - IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << - IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); -} -#endif - int board_early_init_f(void) { #if defined(CONFIG_VIDEO_IPUV3) - setup_display(); + setup_display_clock(); #endif return 0; @@ -252,6 +173,14 @@ int board_init(void) return 0; } +int board_late_init(void) +{ +#if defined(CONFIG_VIDEO_IPUV3) + setup_display_lvds(); +#endif + return 0; +} + int checkboard(void) { puts("Board: Novena 4x\n"); diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h new file mode 100644 index 0000000000..8f11583c2d --- /dev/null +++ b/board/kosagi/novena/novena.h @@ -0,0 +1,33 @@ +/* + * Novena board support + * + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__ +#define __BOARD_KOSAGI_NOVENA_NOVENA_H__ + +#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) +#define NOVENA_BACKLIGHT_PWM_GPIO IMX_GPIO_NR(4, 29) +#define NOVENA_BACKLIGHT_PWR_GPIO IMX_GPIO_NR(4, 15) +#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14) +#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) +#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) +#define NOVENA_ITE6251_PWR_GPIO IMX_GPIO_NR(5, 28) +#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) +#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) +#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) +#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) +#define NOVENA_SD_CD IMX_GPIO_NR(1, 4) +#define NOVENA_SD_WP IMX_GPIO_NR(1, 2) + +#define NOVENA_IT6251_I2C_BUS 2 +#define NOVENA_IT6251_CHIPADDR 0x5c +#define NOVENA_IT6251_LVDSADDR 0x5e + +void setup_display_clock(void); +void setup_display_lvds(void); + +#endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */ diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index c07735ad03..b1688e0295 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -25,6 +25,8 @@ #include <asm/arch/mx6-ddr.h> +#include "novena.h" + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL \ @@ -68,14 +70,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17) -#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7) -#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4) -#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29) -#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12) -#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22) -#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16) - /* * Audio */ @@ -392,6 +386,13 @@ static void novena_spl_setup_iomux_uart(void) static iomux_v3_cfg_t hdmi_pads[] = { /* "Ghost HPD" pin */ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* LCD_PWR_CTL */ + MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LCD_BL_ON */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPIO_PWM1 */ + MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void novena_spl_setup_iomux_video(void) diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c new file mode 100644 index 0000000000..3bb1b7180b --- /dev/null +++ b/board/kosagi/novena/video.c @@ -0,0 +1,456 @@ +/* + * Novena video output support + * + * IT6251 code based on code Copyright (C) 2014 Sean Cross + * from https://github.com/xobs/novena-linux.git commit + * 3d85836ee1377d445531928361809612aa0a18db + * + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/video.h> +#include <i2c.h> +#include <input.h> +#include <ipu_pixfmt.h> +#include <linux/fb.h> +#include <linux/input.h> +#include <malloc.h> +#include <stdio_dev.h> + +#include "novena.h" + +#define IT6251_VENDOR_ID_LOW 0x00 +#define IT6251_VENDOR_ID_HIGH 0x01 +#define IT6251_DEVICE_ID_LOW 0x02 +#define IT6251_DEVICE_ID_HIGH 0x03 +#define IT6251_SYSTEM_STATUS 0x0d +#define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0) +#define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1) +#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2) +#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3) +#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4) +#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5) +#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6) +#define IT6251_REF_STATE 0x0e +#define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0) +#define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1) +#define IT6251_REF_STATE_CR_PATTERN (1 << 2) +#define IT6251_REF_STATE_EQ_PATTERN (1 << 3) +#define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4) +#define IT6251_REF_STATE_MUTED (1 << 5) + +#define IT6251_REG_PCLK_CNT_LOW 0x57 +#define IT6251_REG_PCLK_CNT_HIGH 0x58 + +#define IT6521_RETRY_MAX 20 + +static int it6251_is_stable(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + const unsigned int laddr = NOVENA_IT6251_LVDSADDR; + int status; + int clkcnt; + int rpclkcnt; + int refstate; + + rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) | + ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00); + debug("RPCLKCnt: %d\n", rpclkcnt); + + status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS); + debug("System status: 0x%02x\n", status); + + clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) | + ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) & + 0x0f00); + debug("Clock: 0x%02x\n", clkcnt); + + refstate = i2c_reg_read(laddr, IT6251_REF_STATE); + debug("Ref Link State: 0x%02x\n", refstate); + + if ((refstate & 0x1f) != 0) + return 0; + + /* If video is muted, that's a failure */ + if (refstate & IT6251_REF_STATE_MUTED) + return 0; + + if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE)) + return 0; + + return 1; +} + +static int it6251_ready(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + + /* Test if the IT6251 came out of reset by reading ID regs. */ + if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15) + return 0; + if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca) + return 0; + if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51) + return 0; + if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62) + return 0; + + return 1; +} + +static void it6251_program_regs(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + const unsigned int laddr = NOVENA_IT6251_LVDSADDR; + + i2c_reg_write(caddr, 0x05, 0x00); + mdelay(1); + + /* set LVDSRX address, and enable */ + i2c_reg_write(caddr, 0xfd, 0xbc); + i2c_reg_write(caddr, 0xfe, 0x01); + + /* + * LVDSRX + */ + /* This write always fails, because the chip goes into reset */ + /* reset LVDSRX */ + i2c_reg_write(laddr, 0x05, 0xff); + i2c_reg_write(laddr, 0x05, 0x00); + + /* reset LVDSRX PLL */ + i2c_reg_write(laddr, 0x3b, 0x42); + i2c_reg_write(laddr, 0x3b, 0x43); + + /* something with SSC PLL */ + i2c_reg_write(laddr, 0x3c, 0x08); + /* don't swap links, but writing reserved registers */ + i2c_reg_write(laddr, 0x0b, 0x88); + + /* JEIDA, 8-bit depth 0x11, orig 0x42 */ + i2c_reg_write(laddr, 0x2c, 0x01); + /* "reserved" */ + i2c_reg_write(laddr, 0x32, 0x04); + /* "reserved" */ + i2c_reg_write(laddr, 0x35, 0xe0); + /* "reserved" + clock delay */ + i2c_reg_write(laddr, 0x2b, 0x24); + + /* reset LVDSRX pix clock */ + i2c_reg_write(laddr, 0x05, 0x02); + i2c_reg_write(laddr, 0x05, 0x00); + + /* + * DPTX + */ + /* set for two lane mode, normal op, no swapping, no downspread */ + i2c_reg_write(caddr, 0x16, 0x02); + + /* some AUX channel EDID magic */ + i2c_reg_write(caddr, 0x23, 0x40); + + /* power down lanes 3-0 */ + i2c_reg_write(caddr, 0x5c, 0xf3); + + /* enable DP scrambling, change EQ CR phase */ + i2c_reg_write(caddr, 0x5f, 0x06); + + /* color mode RGB, pclk/2 */ + i2c_reg_write(caddr, 0x60, 0x02); + /* dual pixel input mode, no EO swap, no RGB swap */ + i2c_reg_write(caddr, 0x61, 0x04); + /* M444B24 video format */ + i2c_reg_write(caddr, 0x62, 0x01); + + /* vesa range / not interlace / vsync high / hsync high */ + i2c_reg_write(caddr, 0xa0, 0x0F); + + /* hpd event timer set to 1.6-ish ms */ + i2c_reg_write(caddr, 0xc9, 0xf5); + + /* more reserved magic */ + i2c_reg_write(caddr, 0xca, 0x4d); + i2c_reg_write(caddr, 0xcb, 0x37); + + /* enhanced framing mode, auto video fifo reset, video mute disable */ + i2c_reg_write(caddr, 0xd3, 0x03); + + /* "vidstmp" and some reserved stuff */ + i2c_reg_write(caddr, 0xd4, 0x45); + + /* queue number -- reserved */ + i2c_reg_write(caddr, 0xe7, 0xa0); + /* info frame packets and reserved */ + i2c_reg_write(caddr, 0xe8, 0x33); + /* more AVI stuff */ + i2c_reg_write(caddr, 0xec, 0x00); + + /* select PC master reg for aux channel? */ + i2c_reg_write(caddr, 0x23, 0x42); + + /* send PC request commands */ + i2c_reg_write(caddr, 0x24, 0x00); + i2c_reg_write(caddr, 0x25, 0x00); + i2c_reg_write(caddr, 0x26, 0x00); + + /* native aux read */ + i2c_reg_write(caddr, 0x2b, 0x00); + /* back to internal */ + i2c_reg_write(caddr, 0x23, 0x40); + + /* voltage swing level 3 */ + i2c_reg_write(caddr, 0x19, 0xff); + /* pre-emphasis level 3 */ + i2c_reg_write(caddr, 0x1a, 0xff); + + /* start link training */ + i2c_reg_write(caddr, 0x17, 0x01); +} + +static int it6251_init(void) +{ + const unsigned int caddr = NOVENA_IT6251_CHIPADDR; + int reg; + int tries, retries = 0; + + for (retries = 0; retries < IT6521_RETRY_MAX; retries++) { + /* Program the chip. */ + it6251_program_regs(); + + /* Wait for video stable. */ + for (tries = 0; tries < 100; tries++) { + reg = i2c_reg_read(caddr, 0x17); + /* Test Link CFG, STS, LCS read done. */ + if ((reg & 0xe0) != 0xe0) { + /* Not yet, wait a bit more. */ + mdelay(2); + continue; + } + + /* Test if the video input is stable. */ + if (it6251_is_stable()) + return 0; + } + /* + * If we couldn't stabilize, requeue and try again, + * because it means that the LVDS channel isn't + * stable yet. + */ + printf("Display didn't stabilize.\n"); + printf("This may be because the LVDS port is still in powersave mode.\n"); + mdelay(50); + } + + return -EINVAL; +} + +static void enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +static int lvds_enabled; + +static void enable_lvds(struct display_info_t const *dev) +{ + if (lvds_enabled) + return; + + /* ITE IT6251 power enable. */ + gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0); + mdelay(10); + gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1); + mdelay(20); + lvds_enabled = 1; +} + +static int detect_lvds(struct display_info_t const *dev) +{ + int ret, loops = 250; + + enable_lvds(dev); + + ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); + if (ret) { + puts("Cannot select IT6251 I2C bus.\n"); + return 0; + } + + /* Wait up-to ~250 mS for the LVDS to come up. */ + while (--loops) { + ret = it6251_ready(); + if (ret) + return ret; + + mdelay(1); + } + + return 0; +} + +struct display_info_t const displays[] = { + { + /* HDMI Output */ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15384, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED + }, + }, { + /* LVDS Output: N133HSE-EA1 Rev. C1 */ + .bus = -1, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_lvds, + .enable = enable_lvds, + .mode = { + .name = "Chimei-FHD", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 15384, + .left_margin = 148, + .right_margin = 88, + .upper_margin = 36, + .lower_margin = 4, + .hsync_len = 44, + .vsync_len = 5, + .sync = FB_SYNC_HOR_HIGH_ACT | + FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, + }, + }, +}; + +size_t display_count = ARRAY_SIZE(displays); + +static void enable_vpll(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int timeout = 100000; + + setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_DIV_SELECT | + BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT, + BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) | + BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1)); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); + + clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + clrsetbits_le32(&ccm->analog_pll_video, + BM_ANADIG_PLL_VIDEO_BYPASS, + BM_ANADIG_PLL_VIDEO_ENABLE); +} + +void setup_display_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + enable_ipu_clock(); + enable_vpll(); + imx_setup_hdmi(); + + /* Turn on IPU LDB DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); + + /* Switch LDB DI0 to PLL5 (Video PLL) */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK, + (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); + + /* LDB clock div by 3.5 */ + clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + + /* DI0 clock derived from ldb_di0_clk */ + clrsetbits_le32(&mxc_ccm->chsccdr, + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK, + (CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) + ); + + /* Enable both LVDS channels, both connected to DI0. */ + writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH | + IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA | + IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT | + IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA | + IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT | + IOMUXC_GPR2_SPLIT_MODE_EN_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 | + IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0, + &iomux->gpr[2]); + + clrsetbits_le32(&iomux->gpr[3], + IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | + IOMUXC_GPR3_LVDS1_MUX_CTL_MASK, + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) + ); +} + +void setup_display_lvds(void) +{ + int ret; + + ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); + if (ret) { + puts("Cannot select LVDS-to-eDP I2C bus.\n"); + return; + } + + /* The IT6251 should be ready now, if it's not, it's not connected. */ + ret = it6251_ready(); + if (!ret) + return; + + /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */ + ret = it6251_init(); + if (!ret) { + /* Backlight power enable. */ + gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1); + /* PWM backlight pin, always on for full brightness. */ + gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1); + } +} diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c index 313ab20e26..65cbbf15b7 100644 --- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c +++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c @@ -78,33 +78,3 @@ int board_init(void) return 0; } - -/* Fine-tune the DRAM configuration. */ -void mxs_adjust_memory_params(uint32_t *dram_vals) -{ - /* Enable Auto Precharge. */ - dram_vals[3] |= 1 << 8; - /* Enable Fast Writes. */ - dram_vals[5] |= 1 << 8; - /* tEMRS = 3*tCK */ - dram_vals[10] &= ~(0x3 << 8); - dram_vals[10] |= (0x3 << 8); - /* CASLAT = 3*tCK */ - dram_vals[11] &= ~(0x3 << 0); - dram_vals[11] |= (0x3 << 0); - /* tCKE = 1*tCK */ - dram_vals[12] &= ~(0x7 << 0); - dram_vals[12] |= (0x1 << 0); - /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ - dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0)); - dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0); - /* tDAL = 6*tCK */ - dram_vals[15] &= ~(0xf << 16); - dram_vals[15] |= (0x6 << 16); - /* tREF = 1040*tCK */ - dram_vals[26] &= ~0xffff; - dram_vals[26] |= 0x0410; - /* tRAS_MAX = 9334*tCK */ - dram_vals[32] &= ~0xffff; - dram_vals[32] |= 0x2475; -} diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c index 5272dfa4e6..de3b0e4c8b 100644 --- a/board/olimex/mx23_olinuxino/spl_boot.c +++ b/board/olimex/mx23_olinuxino/spl_boot.c @@ -89,3 +89,33 @@ void board_init_ll(const uint32_t arg, const uint32_t *resptr) { mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); } + +/* Fine-tune the DRAM configuration. */ +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* Enable Auto Precharge. */ + dram_vals[3] |= 1 << 8; + /* Enable Fast Writes. */ + dram_vals[5] |= 1 << 8; + /* tEMRS = 3*tCK */ + dram_vals[10] &= ~(0x3 << 8); + dram_vals[10] |= (0x3 << 8); + /* CASLAT = 3*tCK */ + dram_vals[11] &= ~(0x3 << 0); + dram_vals[11] |= (0x3 << 0); + /* tCKE = 1*tCK */ + dram_vals[12] &= ~(0x7 << 0); + dram_vals[12] |= (0x1 << 0); + /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */ + dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0)); + dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0); + /* tDAL = 6*tCK */ + dram_vals[15] &= ~(0xf << 16); + dram_vals[15] |= (0x6 << 16); + /* tREF = 1040*tCK */ + dram_vals[26] &= ~0xffff; + dram_vals[26] |= 0x0410; + /* tRAS_MAX = 9334*tCK */ + dram_vals[32] &= ~0xffff; + dram_vals[32] |= 0x2475; +} diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index e7aafe5beb..ff28b1df7e 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -1,3 +1,16 @@ +if TARGET_ODROID_XU3 + +config SYS_BOARD + default "smdk5420" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid_xu3" + +endif + if TARGET_PEACH_PI config SYS_BOARD diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index a691222b8b..1aca9fabd9 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <i2c.h> #include <lcd.h> +#include <parade.h> #include <spi.h> #include <errno.h> #include <asm/gpio.h> @@ -21,24 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_USB_EHCI_EXYNOS -static int board_usb_vbus_init(void) -{ - /* Enable VBUS power switch */ - gpio_direction_output(EXYNOS5420_GPIO_X26, 1); - - /* VBUS turn ON time */ - mdelay(3); - - return 0; -} -#endif - int exynos_init(void) { -#ifdef CONFIG_USB_EHCI_EXYNOS - board_usb_vbus_init(); -#endif return 0; } diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000000..74aa0cf672 --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/doc/README.odroid b/doc/README.odroid index 25b962b9f1..8a004ca6ba 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -1,28 +1,39 @@ - U-boot for Odroid X2/U3 + U-boot for Odroid X2/U3/XU3 ======================== 1. Summary ========== -This is a quick instruction for setup Odroid boards based on Exynos4412. -Board config: odroid_config +This is a quick instruction for setup Odroid boards. +Board config: odroid_config for X2/U3 +Board config: odroid-xu3_config for XU3 2. Supported devices ==================== -This U-BOOT config can be used on two boards: +This U-BOOT config can be used on three boards: - Odroid U3 - Odroid X2 with CPU Exynos 4412 rev 2.0 and 2GB of RAM +- Odroid XU3 +with CPU Exynos5422 and 2GB of RAM 3. Boot sequence ================ iROM->BL1->(BL2 + TrustZone)->U-BOOT -This version of U-BOOT doesn't implement SPL but it is required(BL2) -and can be found in "boot.tar.gz" from here: +This version of U-BOOT doesn't implement SPL. So, BL1, BL2, and TrustZone +binaries are needed to boot up. + +<< X2/U3 >> +It can be found in "boot.tar.gz" from here: http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&value=boot.tar.gz or here: http://odroid.in/guides/ubuntu-lfs/boot.tar.gz +<< XU3 >> +It can be downloaded from: +https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel + + 4. Boot media layout ==================== The table below shows SD/eMMC cards layout for U-boot. @@ -35,18 +46,20 @@ The block offset is starting from 0 and the block size is 512B. | Bl2 | 31 | 30 | 1 (boot) | | U-boot | 63 | 62 | 1 (boot) | | Tzsw | 2111 | 2110 | 1 (boot) | -| Uboot Env | 2500 | 2500 | 0 (user) | +| Uboot Env | 2560 | 2560 | 0 (user) | ------------------------------------- 5. Prepare the SD boot card - with SD card reader ================================================= To prepare bootable media you need boot binaries provided by hardkernel. -File "boot.tar.gz" (link in point 3.) contains: -- E4412_S.bl1.HardKernel.bin -- E4412_S.tzsw.signed.bin -- bl2.signed.bin +From the downloaded files, You can find: +- bl1.bin +- tzsw.bin +- bl2.bin - sd_fusing.sh - u-boot.bin +(The file names can be slightly different, but you can distinguish what they are +without problem) This is all you need to boot this board. But if you want to use your custom u-boot then you need to change u-boot.bin with your own u-boot binary* @@ -56,7 +69,7 @@ and run the script "sd_fusing.sh" - this script is valid only for SD card. The proper binary file of current U-boot is u-boot-dtb.bin. quick steps for Linux: -- extract boot.tar.gz +- Download all files from the link at point 3 and extract it if needed. - put any SD card into the SD reader - check the device with "dmesg" - run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) @@ -66,7 +79,7 @@ Check if Hardkernel U-boot is booting, and next do the same with your U-boot. with a eMMC card reader (boot from eMMC card slot) ===================================================== To boot the device from the eMMC slot you should use a special card reader -which supports eMMC partiion switch. All of the boot binaries are stored +which supports eMMC partition switch. All of the boot binaries are stored on the eMMC boot partition which is normally hidden. The "sd_fusing.sh" script can be used after updating offsets of binaries @@ -81,8 +94,8 @@ But then the device can boot only from the SD card slot. 8. Prepare the boot media using Hardkernel U-boot ================================================= -You can update the U-boot to the custom one if you have an working bootloader -delivered with the board on a eMMC/SD card. Then follow the steps: +You can update the U-boot to the custom one if you have a working bootloader +delivered with the board on the eMMC/SD card. Then follow the steps: - install the android fastboot tool - connect a micro usb cable to the board - on the U-boot prompt, run command: fastboot (as a root) @@ -91,7 +104,7 @@ delivered with the board on a eMMC/SD card. Then follow the steps: 9. Partition layout ==================== -Default U-boot environment is setup for fixed partiion layout. +Default U-boot environment is setup for fixed partition layout. Partition table: MSDOS. Disk layout and files as listed in the table below. ----- ------ ------ ------ -------- --------------------------------- @@ -106,6 +119,7 @@ Partition table: MSDOS. Disk layout and files as listed in the table below. Supported fdt files are: - exynos4412-odroidx2.dtb - exynos4412-odroidu3.dtb +- exynos5422-odroidxu3.dtb Supported kernel files are: - Image.itb @@ -144,6 +158,7 @@ And the boot sequence is: 11. USB host support ==================== +NOTE: This section is only for Odroid X2/U3. The ethernet can be accessed after starting the USB subsystem in U-Boot. The adapter does not come with a preconfigured MAC address, and hence it needs diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 185edbe7fe..b4b3ae842f 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -78,14 +78,7 @@ #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION - -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET + #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR @@ -114,151 +107,19 @@ /* Command definition */ #include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA #define CONFIG_CMD_BMODE -#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_SETEXPR #undef CONFIG_CMD_IMLS -#define CONFIG_BOOTDELAY 1 - #define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 -#ifdef CONFIG_SUPPORT_EMMC_BOOT -#define EMMC_ENV \ - "emmcdev=2\0" \ - "update_emmc_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "if mmc dev ${emmcdev}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" -#else -#define EMMC_ENV "" -#endif - -#ifdef CONFIG_CMD_SF -#define SF_ENV \ - "update_spi_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_spi_firmware_filename}; then " \ - "if sf probe; then " \ - "sf erase 0 0xc0000; " \ - "sf write ${loadaddr} 0x400 ${filesize}; " \ - "fi; " \ - "fi\0" -#else -#define SF_ENV "" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONFIG_CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - EMMC_ENV \ - SF_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - #define CONFIG_ARP_TIMEOUT 200UL /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Print Buffer Size */ @@ -272,7 +133,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_CMDLINE_EDITING #define CONFIG_STACKSIZE (128 * 1024) /* Physical Memory Map */ @@ -295,14 +155,14 @@ #if defined(CONFIG_ENV_IS_IN_MMC) /* RiOTboard */ -#define CONFIG_DEFAULT_FDT_FILE "imx6dl-riotboard.dtb" +#define CONFIG_FDTFILE "imx6dl-riotboard.dtb" #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) /* MarSBoard */ -#define CONFIG_DEFAULT_FDT_FILE "imx6q-marsboard.dtb" +#define CONFIG_FDTFILE "imx6q-marsboard.dtb" #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_ENV_OFFSET (768 * 1024) #define CONFIG_ENV_SECT_SIZE (8 * 1024) @@ -312,8 +172,6 @@ #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #endif -#define CONFIG_OF_LIBFDT - #ifndef CONFIG_SYS_DCACHE_OFF #define CONFIG_CMD_CACHE #endif @@ -335,4 +193,43 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#include <config_distro_defaults.h> + +/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, + * 1M script, 1M pxe and the ramdisk at the end */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x12000000\0" \ + "fdt_addr_r=0x13000000\0" \ + "scriptaddr=0x13100000\0" \ + "pxefile_addr_r=0x13200000\0" \ + "ramdisk_addr_r=0x13300000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" + +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_FDTFILE "\0" \ + BOOTENV + #endif /* __RIOTBOARD_CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 8f9b780003..ad63f3c549 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -174,6 +174,16 @@ #define CONFIG_CMD_GPIO +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX + /* USB boot mode */ #define CONFIG_USB_BOOTING #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index a0107e8b4d..671431397f 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -22,11 +22,6 @@ #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) -/* USB */ -#define CONFIG_CMD_USB -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE - #define CONFIG_SPL_TEXT_BASE 0x02023400 #define CONFIG_IRAM_STACK 0x02050000 diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index ef6e1551ab..fe72bd0d3b 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -13,13 +13,6 @@ /* A variant of Exynos5420 (Exynos5 Family) */ #define CONFIG_EXYNOS5800 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) -#define CONFIG_SPI_BOOTING - #include <configs/exynos5-common.h> #define CONFIG_ARCH_EARLY_INIT_R @@ -29,8 +22,6 @@ #define CONFIG_VAR_SIZE_SPL -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_TEXT_BASE 0x23E00000 #ifdef CONFIG_VAR_SIZE_SPL #define CONFIG_SPL_TEXT_BASE 0x02024410 #else @@ -47,15 +38,4 @@ #define CONFIG_BOARD_REV_GPIO_COUNT 2 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 - -/* - * Put the initial stack pointer 1KB below this to allow room for the - * SPL marker. This value is arbitrary, but gd_t is placed starting here. - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* Miscellaneous configurable options */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 620f9501d2..4f137fc96b 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -39,6 +39,7 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* Init Functions */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 6e01fa0435..76cfef123c 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -189,4 +189,18 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index a346542130..99d9d4d7cf 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -60,4 +60,18 @@ #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ +#endif + #endif /* __MX6QSABRESD_CONFIG_H */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 879141a7ca..ea75d2c2b9 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -12,6 +12,7 @@ /* System configurations */ #define CONFIG_MX6 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_CPUINFO @@ -115,6 +116,7 @@ #define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* SPL */ #define CONFIG_SPL_FAT_SUPPORT @@ -225,7 +227,6 @@ /* Video output */ #ifdef CONFIG_VIDEO -#define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000000..9fa86603f6 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Hyungwon Hwang <human.hwang@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H + +#include "exynos5420-common.h" + +#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3" + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */ + +#define TZPC_BASE_OFFSET 0x10000 + +#define CONFIG_CMD_MMC + +/* + * FIXME: The number of bank is actually 8. But there is no way to reserve the + * last 16 Mib in the last bank now. So I just excluded the last bank + * temporally. + */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_ENV_IS_IN_MMC + +#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS + +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT + +#endif /* __CONFIG_H */ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 9512b1e150..255c933baa 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -85,6 +85,7 @@ /* USB Configs */ #define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_MX6 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) @@ -197,6 +198,8 @@ #define CONFIG_CMD_EXT4 #define CONFIG_DOS_PARTITION #define CONFIG_CMD_FS_GENERIC +#define CONFIG_LIB_UUID +#define CONFIG_CMD_FS_UUID #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTFILE diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index 8a82402ec1..a1c980d320 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -14,14 +14,20 @@ #define CONFIG_ENV_SPI_BASE 0x12D30000 #define FLASH_SIZE (0x4 << 20) #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING #include <configs/exynos5420-common.h> #include <configs/exynos5-dt-common.h> #define CONFIG_BOARD_COMMON +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #define CONFIG_SYS_PROMPT "Peach-Pi # " #define CONFIG_IDENT_STRING " for Peach-Pi" diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index ad5db57f5f..6516a72764 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -14,14 +14,20 @@ #define CONFIG_ENV_SPI_BASE 0x12D30000 #define FLASH_SIZE (0x4 << 20) #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING #include <configs/exynos5420-common.h> #include <configs/exynos5-dt-common.h> #define CONFIG_BOARD_COMMON +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) + /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #define CONFIG_SYS_PROMPT "Peach-Pit # " #define CONFIG_IDENT_STRING " for Peach-Pit" diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 5c9a3c0b21..61f582f375 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,20 +9,35 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + #include <configs/exynos5420-common.h> #define CONFIG_BOARD_COMMON #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_TEXT_BASE 0x23E00000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #define CONFIG_SYS_PROMPT "SMDK5420 # " #define CONFIG_IDENT_STRING " for SMDK5420" #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +/* USB */ +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + /* DRAM Memory Banks */ #define CONFIG_NR_DRAM_BANKS 7 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6bb9473c82..6b1f967c44 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -139,7 +139,7 @@ #define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 #endif /* diff --git a/include/parade.h b/include/parade.h new file mode 100644 index 0000000000..887f56dcf2 --- /dev/null +++ b/include/parade.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PARADE_H__ +#define __PARADE_H__ + +/* Initialize the Parade dP<->LVDS bridge if present */ +#ifdef CONFIG_VIDEO_PARADE +int parade_init(const void *blob); +#else +static inline int parade_init(const void *blob) { return -1; } +#endif + +#endif /* __PARADE_H__ */ |