diff options
152 files changed, 1407 insertions, 402 deletions
diff --git a/.travis.yml b/.travis.yml index 8bd49ef1a5..e4e7e653f6 100644 --- a/.travis.yml +++ b/.travis.yml @@ -183,6 +183,9 @@ matrix: - name: "buildman NXP AArch64 LS101x" env: - BUILDMAN="freescale&aarch64&ls101" + - name: "buildman NXP AArch64 LS102x" + env: + - BUILDMAN="freescale&aarch64&ls102" - name: "buildman NXP AArch64 LS104x" env: - BUILDMAN="freescale&aarch64&ls104" @@ -192,6 +195,9 @@ matrix: - name: "buildman NXP AArch64 LS20xx" env: - BUILDMAN="freescale&aarch64&&ls20" + - name: "buildman NXP AArch64 LX216x" + env: + - BUILDMAN="freescale&aarch64&lx216" - name: "buildman i.MX6 (non-NXP)" env: - BUILDMAN="mx6 -x freescale,toradex,boundary,engicam" diff --git a/MAINTAINERS b/MAINTAINERS index 8e26eda2c8..bea3122f2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -55,7 +55,7 @@ M: Alexey Brodkin <alexey.brodkin@synopsys.com> M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> S: Maintained L: uboot-snps-arc@synopsys.com -T: git git://git.denx.de/u-boot-arc.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-arc.git F: arch/arc/ F: board/synopsys/ @@ -84,7 +84,7 @@ F: drivers/mmc/snps_dw_mmc.c ARM M: Albert Aribaud <albert.u.boot@aribaud.net> S: Maintained -T: git git://git.denx.de/u-boot-arm.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-arm.git F: arch/arm/ F: cmd/arm/ @@ -92,14 +92,14 @@ ARM ALTERA SOCFPGA M: Marek Vasut <marex@denx.de> M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> S: Maintainted -T: git git://git.denx.de/u-boot-socfpga.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git F: arch/arm/mach-socfpga/ ARM AMLOGIC SOC SUPPORT M: Neil Armstrong <narmstrong@baylibre.com> S: Maintained L: u-boot-amlogic@groups.io -T: git git://git.denx.de/u-boot-amlogic.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git F: arch/arm/mach-meson/ F: arch/arm/include/asm/arch-meson/ F: drivers/clk/meson/ @@ -153,7 +153,7 @@ M: Stefano Babic <sbabic@denx.de> M: Fabio Estevam <festevam@gmail.com> R: NXP i.MX U-Boot Team <uboot-imx@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-imx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git F: arch/arm/cpu/arm1136/mx*/ F: arch/arm/cpu/arm926ejs/mx*/ F: arch/arm/cpu/armv7/vf610/ @@ -174,7 +174,7 @@ F: arch/arm/include/asm/arch-hi6220/ ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese <sr@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-marvell.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-marvell.git F: arch/arm/mach-kirkwood/ F: arch/arm/mach-mvebu/ F: drivers/ata/ahci_mvebu.c @@ -188,7 +188,7 @@ F: drivers/watchdog/orion_wdt.c ARM MARVELL PXA M: Marek Vasut <marex@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-pxa.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ @@ -217,7 +217,7 @@ N: mediatek ARM MICROCHIP/ATMEL AT91 M: Eugen Hristev <eugen.hristev@microchip.com> S: Maintained -T: git git://git.denx.de/u-boot-atmel.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git F: arch/arm/mach-at91/ F: board/atmel/ @@ -234,7 +234,7 @@ ARM RENESAS RMOBILE/R-CAR M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> M: Marek Vasut <marek.vasut+renesas@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-sh.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git F: arch/arm/mach-rmobile/ ARM ROCKCHIP @@ -242,7 +242,7 @@ M: Simon Glass <sjg@chromium.org> M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> M: Kever Yang <kever.yang@rock-chips.com> S: Maintained -T: git git://git.denx.de/u-boot-rockchip.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git F: arch/arm/include/asm/arch-rockchip/ F: arch/arm/mach-rockchip/ F: board/rockchip/ @@ -264,7 +264,7 @@ F: tools/rkspi.c ARM SAMSUNG M: Minkyu Kang <mk7.kang@samsung.com> S: Maintained -T: git git://git.denx.de/u-boot-samsung.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.git F: arch/arm/mach-exynos/ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ @@ -289,13 +289,12 @@ F: arch/arm/include/asm/arch-sti*/ ARM STM SPEAR #M: Vipin Kumar <vipin.kumar@st.com> S: Orphaned (Since 2016-02) -T: git git://git.denx.de/u-boot-stm.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git F: arch/arm/cpu/arm926ejs/spear/ F: arch/arm/include/asm/arch-spear/ ARM STM STM32MP M: Patrick Delaunay <patrick.delaunay@st.com> -M: Christophe Kerello <christophe.kerello@st.com> M: Patrice Chotard <patrice.chotard@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) S: Maintained @@ -326,7 +325,7 @@ ARM SUNXI M: Jagan Teki <jagan@amarulasolutions.com> M: Maxime Ripard <maxime.ripard@bootlin.com> S: Maintained -T: git git://git.denx.de/u-boot-sunxi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git F: arch/arm/cpu/armv7/sunxi/ F: arch/arm/include/asm/arch-sunxi/ F: arch/arm/mach-sunxi/ @@ -335,14 +334,14 @@ F: board/sunxi/ ARM TEGRA M: Tom Warren <twarren@nvidia.com> S: Maintained -T: git git://git.denx.de/u-boot-tegra.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-tegra.git F: arch/arm/mach-tegra/ F: arch/arm/include/asm/arch-tegra*/ ARM TI M: Tom Rini <trini@konsulko.com> S: Maintained -T: git git://git.denx.de/u-boot-ti.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git F: arch/arm/mach-davinci/ F: arch/arm/mach-k3/ F: arch/arm/mach-keystone/ @@ -352,7 +351,7 @@ F: arch/arm/include/asm/ti-common/ ARM UNIPHIER M: Masahiro Yamada <yamada.masahiro@socionext.com> S: Maintained -T: git git://git.denx.de/u-boot-uniphier.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier.git F: arch/arm/mach-uniphier/ F: configs/uniphier_*_defconfig N: uniphier @@ -360,7 +359,7 @@ N: uniphier ARM VERSAL M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ ARM VERSATILE EXPRESS DRIVERS @@ -373,7 +372,7 @@ N: vexpress ARM ZYNQ M: Michal Simek <monstr@monstr.eu> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynq/ F: drivers/clk/clk_zynq.c F: drivers/fpga/zynqpl.c @@ -397,7 +396,7 @@ N: zynq ARM ZYNQMP M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp/ F: drivers/clk/clk_zynqmp.c F: drivers/fpga/zynqpl.c @@ -423,7 +422,7 @@ N: zynqmp ARM ZYNQMP R5 M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp-r5/ BINMAN @@ -439,7 +438,7 @@ F: tools/buildman/ CFI FLASH M: Stefan Roese <sr@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-cfi-flash.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash.git F: drivers/mtd/cfi_flash.c F: drivers/mtd/jedec_flash.c @@ -447,13 +446,13 @@ COLDFIRE M: Huan Wang <alison.wang@nxp.com> M: Angelo Dureghello <angelo@sysam.it> S: Maintained -T: git git://git.denx.de/u-boot-coldfire.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-coldfire.git F: arch/m68k/ DFU M: Lukasz Majewski <lukma@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-dfu.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-dfu.git F: cmd/dfu.c F: cmd/usb_*.c F: common/dfu.c @@ -465,7 +464,7 @@ F: drivers/usb/gadget/ DRIVER MODEL M: Simon Glass <sjg@chromium.org> S: Maintained -T: git git://git.denx.de/u-boot-dm.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-dm.git F: drivers/core/ F: include/dm/ F: test/dm/ @@ -474,10 +473,10 @@ EFI PAYLOAD M: Heinrich Schuchardt <xypron.glpk@gmx.de> R: Alexander Graf <agraf@csgraf.de> S: Maintained -T: git git://git.denx.de/u-boot-efi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git F: doc/README.uefi F: doc/README.iscsi -F: Documentation/efi.rst +F: doc/efi.rst F: include/capitalization.h F: include/charset.h F: include/cp1250.h @@ -497,7 +496,7 @@ F: tools/file2include.c FPGA M: Michal Simek <michal.simek@xilinx.com> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: drivers/fpga/ F: cmd/fpga.c F: include/fpga.h @@ -505,7 +504,7 @@ F: include/fpga.h FLATTENED DEVICE TREE M: Simon Glass <sjg@chromium.org> S: Maintained -T: git git://git.denx.de/u-boot-fdt.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fdt.git F: lib/fdtdec* F: lib/libfdt/ F: include/fdt* @@ -516,24 +515,24 @@ F: common/fdt_support.c FREEBSD M: Rafal Jaworowski <raj@semihalf.com> S: Maintained -T: git git://git.denx.de/u-boot-freebsd.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-freebsd.git FREESCALE QORIQ M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-fsl-qoriq.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git F: drivers/watchdog/sp805_wdt.c I2C M: Heiko Schocher <hs@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-i2c.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-i2c.git F: drivers/i2c/ LOGGING M: Simon Glass <sjg@chromium.org> S: Maintained -T: git git://git.denx.de/u-boot.git +T: git https://gitlab.denx.de/u-boot/u-boot.git F: common/log.c F: cmd/log.c F: test/log/log_test.c @@ -549,7 +548,7 @@ F: drivers/i2c/i2c-versatile.c MICROBLAZE M: Michal Simek <monstr@monstr.eu> S: Maintained -T: git git://git.denx.de/u-boot-microblaze.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/microblaze/ F: cmd/mfsl.c F: drivers/gpio/xilinx_gpio.c @@ -564,7 +563,7 @@ N: xilinx MIPS M: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-mips.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git F: arch/mips/ MIPS MSCC @@ -595,38 +594,38 @@ F: arch/mips/mach-jz47xx/ MMC M: Peng Fan <peng.fan@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-mmc.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git F: drivers/mmc/ NAND FLASH #M: Scott Wood <oss@buserror.net> S: Orphaned (Since 2018-07) -T: git git://git.denx.de/u-boot-nand-flash.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash.git F: drivers/mtd/nand/raw/ NDS32 M: Macpaul Lin <macpaul@andestech.com> S: Maintained -T: git git://git.denx.de/u-boot-nds32.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nds32.git F: arch/nds32/ NETWORK M: Joe Hershberger <joe.hershberger@ni.com> S: Maintained -T: git git://git.denx.de/u-boot-net.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-net.git F: drivers/net/ F: net/ NIOS M: Thomas Chou <thomas@wytron.com.tw> S: Maintained -T: git git://git.denx.de/u-boot-nios.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nios.git F: arch/nios2/ ONENAND #M: Lukasz Majewski <l.majewski@majess.pl> S: Orphaned (Since 2017-01) -T: git git://git.denx.de/u-boot-onenand.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-onenand.git F: drivers/mtd/onenand/ PATMAN @@ -637,7 +636,7 @@ F: tools/patman/ POWER M: Jaehoon Chung <jh80.chung@samsung.com> S: Maintained -T: git git://git.denx.de/u-boot-pmic.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-pmic.git F: drivers/power/ POWERPC @@ -648,13 +647,13 @@ F: arch/powerpc/ POWERPC MPC8XX M: Christophe Leroy <christophe.leroy@c-s.fr> S: Maintained -T: git git://git.denx.de/u-boot-mpc8xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc8xx.git F: arch/powerpc/cpu/mpc8xx/ POWERPC MPC83XX M: Mario Six <mario.six@gdsys.cc> S: Maintained -T: git git://git.denx.de/u-boot-mpc83xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx.git F: drivers/ram/mpc83xx_sdram.c F: include/dt-bindings/memory/mpc83xx-sdram.h F: drivers/sysreset/sysreset_mpc83xx.c @@ -672,19 +671,19 @@ F: arch/powerpc/include/asm/arch-mpc83xx/ POWERPC MPC85XX M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-mpc85xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx.git F: arch/powerpc/cpu/mpc85xx/ POWERPC MPC86XX M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained -T: git git://git.denx.de/u-boot-mpc86xx.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc86xx.git F: arch/powerpc/cpu/mpc86xx/ RISC-V M: Rick Chen <rick@andestech.com> S: Maintained -T: git git://git.denx.de/u-boot-riscv.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git F: arch/riscv/ F: cmd/riscv/ F: tools/prelink-riscv.c @@ -702,15 +701,16 @@ S: Maintained F: arch/sandbox/ SH +M: Marek Vasut <marek.vasut+renesas@gmail.com> M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> S: Maintained -T: git git://git.denx.de/u-boot-sh.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git F: arch/sh/ SPI M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained -T: git git://git.denx.de/u-boot-spi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-spi.git F: drivers/spi/ F: include/spi* @@ -772,25 +772,25 @@ UBI M: Kyungmin Park <kmpark@infradead.org> M: Heiko Schocher <hs@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-ubi.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ USB M: Marek Vasut <marex@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-usb.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git F: drivers/usb/ USB xHCI M: Bin Meng <bmeng.cn@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-usb.git topic-xhci +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci F: drivers/usb/host/xhci* VIDEO M: Anatolij Gustschin <agust@denx.de> S: Maintained -T: git git://git.denx.de/u-boot-video.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-video.git F: drivers/video/ F: common/lcd*.c F: include/lcd*.h @@ -800,7 +800,7 @@ X86 M: Simon Glass <sjg@chromium.org> M: Bin Meng <bmeng.cn@gmail.com> S: Maintained -T: git git://git.denx.de/u-boot-x86.git +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git F: arch/x86/ F: cmd/x86/ @@ -814,7 +814,7 @@ M: Tom Rini <trini@konsulko.com> L: u-boot@lists.denx.de Q: http://patchwork.ozlabs.org/project/uboot/list/ S: Maintained -T: git git://git.denx.de/u-boot.git +T: git https://gitlab.denx.de/u-boot/u-boot.git F: configs/tools-only_defconfig F: * F: */ @@ -168,7 +168,7 @@ MAKEFLAGS += --no-print-directory # Use 'make C=2' to enable checking of *all* source files, regardless # of whether they are re-compiled or not. # -# See the file "Documentation/sparse.txt" for more details, including +# See the file "doc/sparse.txt" for more details, including # where to get the "sparse" utility. ifeq ("$(origin C)", "command line") @@ -1916,7 +1916,7 @@ help: @echo ' coccicheck - Execute static code analysis with Coccinelle' @echo '' @echo 'Documentation targets:' - @$(MAKE) -f $(srctree)/Documentation/Makefile dochelp + @$(MAKE) -f $(srctree)/doc/Makefile dochelp @echo '' @echo ' make V=0|1 [targets] 0 => quiet build (default), 1 => verbose build' @echo ' make V=2 [targets] 2 => give reason for rebuild of target' @@ -1945,7 +1945,7 @@ DOC_TARGETS := xmldocs latexdocs pdfdocs htmldocs epubdocs cleandocs \ linkcheckdocs dochelp refcheckdocs PHONY += $(DOC_TARGETS) $(DOC_TARGETS): scripts_basic FORCE - $(Q)$(MAKE) $(build)=Documentation $@ + $(Q)$(MAKE) $(build)=doc $@ endif #ifeq ($(config-targets),1) endif #ifeq ($(mixed-targets),1) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index fe52166e28..99d126660d 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -18,7 +18,7 @@ .globl _start _start: -#if defined(LINUX_KERNEL_IMAGE_HEADER) +#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER) #include <asm/boot0-linux-kernel-header.h> #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) /* diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 5b19e44d2f..994092a195 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -56,10 +56,6 @@ }; }; -&usbotg_hs { - g-tx-fifo-size = <576>; -}; - &v3v3 { regulator-always-on; }; diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index aebf168a89..7572404625 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -533,6 +533,7 @@ config ARCH_BSC9132 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_ERRATUM_IFC_A002769 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -551,6 +552,7 @@ config ARCH_C29X select SYS_FSL_DDR_VER_46 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -566,6 +568,7 @@ config ARCH_MPC8536 select FSL_LAW select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -594,6 +597,7 @@ config ARCH_MPC8544 bool select FSL_LAW select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -609,6 +613,7 @@ config ARCH_MPC8548 select SYS_FSL_ERRATUM_NMG_LBC103 select SYS_FSL_ERRATUM_NMG_ETSEC129 select SYS_FSL_ERRATUM_I2C_A004447 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_SEC @@ -633,6 +638,7 @@ config ARCH_MPC8560 config ARCH_MPC8568 bool select FSL_LAW + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -643,6 +649,7 @@ config ARCH_MPC8569 select FSL_LAW select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -657,6 +664,7 @@ config ARCH_MPC8572 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_DDR_115 select SYS_FSL_ERRATUM_DDR111_DDR134 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC @@ -681,6 +689,7 @@ config ARCH_P1010 select SYS_FSL_ERRATUM_P1010_A003549 select SYS_FSL_ERRATUM_SEC_A003571 select SYS_FSL_ERRATUM_IFC_A003399 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -702,6 +711,7 @@ config ARCH_P1011 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -716,6 +726,8 @@ config ARCH_P1020 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -735,6 +747,8 @@ config ARCH_P1021 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -756,6 +770,7 @@ config ARCH_P1022 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_SATA_A001 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -769,6 +784,7 @@ config ARCH_P1023 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_I2C_A004447 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -782,6 +798,8 @@ config ARCH_P1024 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -802,6 +820,8 @@ config ARCH_P1025 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_DISABLE_ASPM + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -819,6 +839,7 @@ config ARCH_P2020 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC_A001 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_BE @@ -1074,6 +1095,7 @@ config ARCH_T2080 select SYS_FSL_ERRATUM_A007907 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 @@ -1096,6 +1118,7 @@ config ARCH_T2081 select SYS_FSL_ERRATUM_A007212 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_ESDHC111 + select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 @@ -1429,6 +1452,12 @@ config SYS_P4080_ERRATUM_SERDES_A001 config SYS_P4080_ERRATUM_SERDES_A005 bool +config FSL_PCIE_DISABLE_ASPM + bool + +config FSL_PCIE_RESET + bool + config SYS_FSL_QORIQ_CHASSIS1 bool diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c index 90ccc3427c..1d0213a513 100644 --- a/arch/powerpc/cpu/mpc85xx/pci.c +++ b/arch/powerpc/cpu/mpc85xx/pci.c @@ -12,7 +12,7 @@ #include <asm/cpm_85xx.h> #include <pci.h> -#if !defined(CONFIG_FSL_PCI_INIT) +#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI) #ifndef CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index d2bebb08b6..999fa8cec4 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -104,4 +104,52 @@ sata-fpdma = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t2080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; }; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7c963cdc35..946e74a93b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -61,19 +61,16 @@ /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_ARCH_P1020) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif #elif defined(CONFIG_ARCH_P1021) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -95,14 +92,12 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_TSECV2 -#define CONFIG_FSL_PCIE_DISABLE_ASPM #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/board/Arcturus/ucp1020/cmd_arc.c b/board/Arcturus/ucp1020/cmd_arc.c index 9579d52ffd..7a510c61fb 100644 --- a/board/Arcturus/ucp1020/cmd_arc.c +++ b/board/Arcturus/ucp1020/cmd_arc.c @@ -2,8 +2,8 @@ /* * Command for accessing Arcturus factory environment. * - * Copyright 2013-2015 Arcturus Networks Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks Inc. + * https://www.arcturusnetworks.com/products/ * by Oleksandr G Zhadan et al. * */ @@ -12,19 +12,13 @@ #include <div64.h> #include <malloc.h> #include <spi_flash.h> - +#include <mmc.h> +#include <version.h> +#include <environment.h> #include <asm/io.h> -#define MAX_SERIAL_SIZE 15 -#define MAX_HWADDR_SIZE 17 - -#define FIRM_ADDR1 (0x200 - sizeof(smac)) -#define FIRM_ADDR2 (0x400 - sizeof(smac)) -#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) -#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) - -static struct spi_flash *flash; -char smac[4][18]; +static ulong fwenv_addr[MAX_FWENV_ADDR]; +const char mystrerr[] = "ERROR: Failed to save factory info"; static int ishwaddr(char *hwaddr) { @@ -38,156 +32,349 @@ static int ishwaddr(char *hwaddr) return -1; } -static int set_arc_product(int argc, char *const argv[]) +#if (FWENV_TYPE == FWENV_MMC) + +static char smac[29][18] __attribute__ ((aligned(0x200))); /* 1 MMC block is 512 bytes */ + +int set_mmc_arc_product(int argc, char *const argv[]) { - int err = 0; - char *mystrerr = "ERROR: Failed to save factory info in spi location"; + struct mmc *mmc; + u32 blk, cnt, n; + int i, err = 1; + void *addr; + const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + + mmc = find_mmc_device(mmc_dev_num); + if (!mmc) { + printf("No SD/MMC/eMMC card found\n"); + return 0; + } + if (mmc_init(mmc)) { + printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", + mmc_dev_num); + return 0; + } + if (mmc_getwp(mmc) == 1) { + printf("Error: card is write protected!\n"); + return CMD_RET_FAILURE; + } - if (argc != 5) - return -1; + /* Save factory defaults */ + addr = (void *)smac; + cnt = 1; /* One 512 bytes block */ + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + blk = fwenv_addr[i] / 512; + n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); + if (n != cnt) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + } + if (err) + return -2; - /* Check serial number */ - if (strlen(argv[1]) != MAX_SERIAL_SIZE) - return -1; + return err; +} - /* Check HWaddrs */ - if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) - return -1; +static int read_mmc_arc_info(void) +{ + struct mmc *mmc; + u32 blk, cnt, n; + int i; + void *addr; + const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + + mmc = find_mmc_device(mmc_dev_num); + if (!mmc) { + printf("No SD/MMC/eMMC card found\n"); + return 0; + } + if (mmc_init(mmc)) { + printf("%s(%d) init failed\n", IS_SD(mmc) ? "SD" : "MMC", + mmc_dev_num); + return 0; + } - strcpy(smac[3], argv[1]); - strcpy(smac[2], argv[2]); - strcpy(smac[1], argv[3]); - strcpy(smac[0], argv[4]); + addr = (void *)smac; + cnt = 1; /* One 512 bytes block */ - flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, - CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + blk = fwenv_addr[i] / 512; + n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); + flush_cache((ulong) addr, 512); + if (n == cnt) + return (i + 1); + } + return 0; +} +#endif - /* - * Save factory defaults - */ +#if (FWENV_TYPE == FWENV_SPI_FLASH) - if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) { - printf("%s: %s [1]\n", __func__, mystrerr); - err++; - } - if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) { - printf("%s: %s [2]\n", __func__, mystrerr); - err++; - } +static struct spi_flash *flash; +static char smac[4][18]; - if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) { - printf("%s: %s [3]\n", __func__, mystrerr); - err++; - } +int set_spi_arc_product(int argc, char *const argv[]) +{ + int i, err = 1; - if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) { - printf("%s: %s [4]\n", __func__, mystrerr); - err++; + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", + CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); + return -1; } - if (err == 4) { - printf("%s: %s [ALL]\n", __func__, mystrerr); + /* Save factory defaults */ + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + if (spi_flash_write + (flash, fwenv_addr[i], sizeof(smac), smac)) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + if (err) return -2; - } - return 0; + return err; } -int get_arc_info(void) +static int read_spi_arc_info(void) { - int location = 1; - char *myerr = "ERROR: Failed to read all 4 factory info spi locations"; + int i; flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); + if (!flash) { + printf("Failed to initialize SPI flash at %u:%u\n", + CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS); + return 0; + } + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + if (!spi_flash_read + (flash, fwenv_addr[i], sizeof(smac), smac)) + return (i + 1); + return 0; +} +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) - if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac), - smac)) { - location++; - if (spi_flash_read(flash, FIRM_ADDR4, - sizeof(smac), smac)) { - printf("%s: %s\n", __func__, myerr); - return -2; - } - } +static char smac[4][18]; + +int set_nor_arc_product(int argc, char *const argv[]) +{ + int i, err = 1; + + /* Save factory defaults */ + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + ulong fwenv_end = fwenv_addr[i] + 4; + + flash_sect_roundb(&fwenv_end); + flash_sect_protect(0, fwenv_addr[i], fwenv_end); + if (flash_write + ((char *)smac, fwenv_addr[i], sizeof(smac))) + printf("%s: %s [%d]\n", __func__, mystrerr, i); + else + err = 0; + flash_sect_protect(1, fwenv_addr[i], fwenv_end); } - } - if (smac[3][0] != 0) { - if (location > 1) - printf("Using region %d\n", location); - printf("SERIAL: "); - if (smac[3][0] == 0xFF) { - printf("\t<not found>\n"); - } else { - printf("\t%s\n", smac[3]); - env_set("SERIAL", smac[3]); + if (err) + return -2; + + return err; +} + +static int read_nor_arc_info(void) +{ + int i; + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) { + memcpy(smac, (void *)fwenv_addr[i], sizeof(smac)); + return (i + 1); } + + return 0; +} +#endif + +int set_arc_product(int argc, char *const argv[]) +{ + if (argc != 5) + return -1; + + /* Check serial number */ + if (strlen(argv[1]) != MAX_SERIAL_SIZE) + return -1; + + /* Check HWaddrs */ + if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4])) + return -1; + + strcpy(smac[0], argv[1]); + strcpy(smac[1], argv[2]); + strcpy(smac[2], argv[3]); + strcpy(smac[3], argv[4]); + +#if (FWENV_TYPE == FWENV_NOR_FLASH) + return set_nor_arc_product(argc, argv); +#endif +#if (FWENV_TYPE == FWENV_SPI_FLASH) + return set_spi_arc_product(argc, argv); +#endif +#if (FWENV_TYPE == FWENV_MMC) + return set_mmc_arc_product(argc, argv); +#endif + return -2; +} + +static int read_arc_info(void) +{ +#if (FWENV_TYPE == FWENV_NOR_FLASH) + return read_nor_arc_info(); +#endif +#if (FWENV_TYPE == FWENV_SPI_FLASH) + return read_spi_arc_info(); +#endif +#if (FWENV_TYPE == FWENV_MMC) + return read_mmc_arc_info(); +#endif + return 0; +} + +static int do_get_arc_info(void) +{ + int l = read_arc_info(); + char *oldserial = env_get("SERIAL"); + char *oldversion = env_get("VERSION"); + + if (oldversion != NULL) + if (strcmp(oldversion, U_BOOT_VERSION) != 0) + oldversion = NULL; + + if (l == 0) { + printf("%s: failed to read factory info\n", __func__); + return -2; } - if (strcmp(smac[2], "00:00:00:00:00:00") == 0) - return 0; + printf("\rSERIAL: "); + if (smac[0][0] == EMPY_CHAR) { + printf("<not found>\n"); + } else { + printf("%s\n", smac[0]); + env_set("SERIAL", smac[0]); + } - printf("HWADDR0:"); - if (smac[2][0] == 0xFF) { - printf("\t<not found>\n"); + if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { + env_set("ethaddr", NULL); + env_set("eth1addr", NULL); + env_set("eth2addr", NULL); + goto done; + } + + printf("HWADDR0: "); + if (smac[1][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("ethaddr"); - if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { - env_set("ethaddr", smac[2]); - printf("\t%s (factory)\n", smac[2]); + if (ret == NULL) { + env_set("ethaddr", smac[1]); + printf("%s\n", smac[1]); + } else if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) { + env_set("ethaddr", smac[1]); + printf("%s (factory)\n", smac[1]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } - if (strcmp(smac[1], "00:00:00:00:00:00") == 0) { - env_set("eth1addr", smac[2]); - env_set("eth2addr", smac[2]); - return 0; + if (strcmp(smac[2], "00:00:00:00:00:00") == 0) { + env_set("eth1addr", NULL); + env_set("eth2addr", NULL); + goto done; } - printf("HWADDR1:"); - if (smac[1][0] == 0xFF) { - printf("\t<not found>\n"); + printf("HWADDR1: "); + if (smac[2][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("eth1addr"); - if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { - env_set("eth1addr", smac[1]); - printf("\t%s (factory)\n", smac[1]); + if (ret == NULL) { + env_set("ethaddr", smac[2]); + printf("%s\n", smac[2]); + } else if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) { + env_set("eth1addr", smac[2]); + printf("%s (factory)\n", smac[2]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } - if (strcmp(smac[0], "00:00:00:00:00:00") == 0) { - env_set("eth2addr", smac[1]); - return 0; + if (strcmp(smac[3], "00:00:00:00:00:00") == 0) { + env_set("eth2addr", NULL); + goto done; } - printf("HWADDR2:"); - if (smac[0][0] == 0xFF) { - printf("\t<not found>\n"); + printf("HWADDR2: "); + if (smac[3][0] == EMPY_CHAR) { + printf("<not found>\n"); } else { char *ret = env_get("eth2addr"); - if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { - env_set("eth2addr", smac[0]); - printf("\t%s (factory)\n", smac[0]); + if (ret == NULL) { + env_set("ethaddr", smac[3]); + printf("%s\n", smac[3]); + } else if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) { + env_set("eth2addr", smac[3]); + printf("%s (factory)\n", smac[3]); } else { - printf("\t%s\n", ret); + printf("%s\n", ret); } } +done: + if (oldserial == NULL || oldversion == NULL) { + if (oldversion == NULL) + env_set("VERSION", U_BOOT_VERSION); + env_save(); + } return 0; } -static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +static int init_fwenv(void) +{ + int i, ret = -1; + + fwenv_addr[0] = FWENV_ADDR1; + fwenv_addr[1] = FWENV_ADDR2; + fwenv_addr[2] = FWENV_ADDR3; + fwenv_addr[3] = FWENV_ADDR4; + + for (i = 0; i < MAX_FWENV_ADDR; i++) + if (fwenv_addr[i] != -1) + ret = 0; + if (ret) + printf("%s: No firmfare info storage address is defined\n", + __func__); + return ret; +} + +void get_arc_info(void) +{ + if (!init_fwenv()) + do_get_arc_info(); +} + +static int do_arc_cmd(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]) { const char *cmd; int ret = -1; @@ -196,15 +383,14 @@ static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) --argc; ++argv; - if (strcmp(cmd, "product") == 0) { + if (init_fwenv()) + return ret; + + if (strcmp(cmd, "product") == 0) ret = set_arc_product(argc, argv); - goto done; - } - if (strcmp(cmd, "info") == 0) { - ret = get_arc_info(); - goto done; - } -done: + else if (strcmp(cmd, "info") == 0) + ret = do_get_arc_info(); + if (ret == -1) return CMD_RET_USAGE; diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c index 1a1fcb9be9..54fd1782cb 100644 --- a/board/Arcturus/ucp1020/ucp1020.c +++ b/board/Arcturus/ucp1020/ucp1020.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * by Oleksandr G Zhadan et al. * based on board/freescale/p1_p2_rdb_pc/spl.c * original copyright follows: @@ -108,7 +108,9 @@ int checkboard(void) { printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL); board_gpio_init(); +#ifdef CONFIG_MMC printf("SD/MMC: 4-bit Mode\n"); +#endif return 0; } @@ -193,7 +195,9 @@ int last_stage_init(void) static char newkernelargs[256]; static u8 id1[16]; static u8 id2; +#ifdef CONFIG_MMC struct mmc *mmc; +#endif char *sval, *kval; if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) { @@ -215,6 +219,7 @@ int last_stage_init(void) kval = env_get("kernelargs"); +#ifdef CONFIG_MMC mmc = find_mmc_device(0); if (mmc) if (!mmc_init(mmc)) { @@ -234,6 +239,7 @@ int last_stage_init(void) env_set("kernelargs", mmckargs); } } +#endif get_arc_info(); if (kval) { diff --git a/board/Arcturus/ucp1020/ucp1020.h b/board/Arcturus/ucp1020/ucp1020.h index cf1ddd718b..1b527cdb1c 100644 --- a/board/Arcturus/ucp1020/ucp1020.h +++ b/board/Arcturus/ucp1020/ucp1020.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * by Oleksandr G Zhadan et al. */ @@ -35,8 +35,10 @@ #define GPIO_WD GPIO15 +#ifdef CONFIG_MMC static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro"; static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw"; +#endif int get_arc_info(void); diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 0608a5a88b..21156a4ca9 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) ARM Ltd 2015 * * Author: Liviu Dudau <Liviu.Dudau@arm.com> - * - * SPDX-Licence-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/board/bosch/guardian/MAINTAINERS b/board/bosch/guardian/MAINTAINERS index 8d16ec0202..2f674d7f83 100644 --- a/board/bosch/guardian/MAINTAINERS +++ b/board/bosch/guardian/MAINTAINERS @@ -1,5 +1,7 @@ Guardian BOARD M: Sjoerd Simons <sjoerd.simons@collabora.co.uk> +M: Govindaraji Sivanantham <Govindaraji.Sivanantham@in.bosch.com> +M: Moses Christopher Bollavarapu <BollavarapuMoses.Christopher@in.bosch.com> S: Maintained F: board/bosch/guardian/ F: include/configs/am335x_guardian.h diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c index c761aea0ac..ef26f14c46 100644 --- a/board/freescale/t208xqds/pci.c +++ b/board/freescale/t208xqds/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h> +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index e6fed25152..efc1d356d6 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -2,6 +2,7 @@ XILINX_ZYNQMP BOARDS M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: arch/arm/dts/zynqmp-* +F: arch/arm/dts/avnet-ultra96* F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp* F: configs/xilinx_zynqmp* @@ -137,6 +137,6 @@ U_BOOT_CMD( led, 4, 1, do_led, "manage LEDs", "<led_label> on|off|toggle" BLINK "\tChange LED state\n" - "led [<led_label>]\tGet LED state\n" + "led <led_label>\tGet LED state\n" "led list\t\tshow a list of LEDs" ); diff --git a/common/image-sig.c b/common/image-sig.c index 4f6b4ec412..004fbc525b 100644 --- a/common/image-sig.c +++ b/common/image-sig.c @@ -211,7 +211,7 @@ static int fit_image_setup_verify(struct image_sign_info *info, info->required_keynode = required_keynode; printf("%s:%s", algo_name, info->keyname); - if (!info->checksum || !info->crypto) { + if (!info->checksum || !info->crypto || !info->padding) { *err_msgp = "Unknown signature algorithm"; return -1; } diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index 9c2182e8ba..ee2de0ad68 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -112,5 +112,4 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y -CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index 9cd3daab35..a446bb9f2c 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -102,5 +102,4 @@ CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_SPI=y -CONFIG_MPC8XXX_SPI=y CONFIG_OF_LIBFDT=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index f7dfb94768..0db930f733 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -66,6 +66,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index a89c410c12..f5cca80a6d 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -63,6 +63,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 6996f856a7..dea8479253 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -50,6 +50,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 101e23d250..60539f4380 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -64,6 +64,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 1346d5eaac..f4bebee147 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -43,6 +43,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index bcbd276b02..e22542fd8c 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -50,6 +50,9 @@ CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_SCSI=y CONFIG_DM_SCSI=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index 0a676d48c9..128f10fa5d 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -19,12 +19,9 @@ CONFIG_AUTOBOOT_STOP_STR="\x1b" CONFIG_CMD_IMLS=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y # CONFIG_CMD_NAND is not set -CONFIG_CMD_MMC_SPI=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y +# CONFIG_CMD_PCI is not set +# CONFIG_CMD_SATA is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -35,26 +32,18 @@ CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_FSL_ESDHC=y +# CONFIG_SATA_SIL is not set +# CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y CONFIG_FS_CRAMFS=y CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index 05077c5b73..a0a4abab4e 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -17,7 +17,6 @@ CONFIG_BOOTDELAY=1 CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" @@ -50,5 +49,6 @@ CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_TPS65910=y CONFIG_CONS_INDEX=4 +# CONFIG_OMAP_WATCHDOG is not set # CONFIG_USE_TINY_PRINTF is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig index 584e54d535..7f6ccc9f54 100644 --- a/configs/apalis-imx8qm_defconfig +++ b/configs/apalis-imx8qm_defconfig @@ -54,5 +54,4 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y # CONFIG_EFI_LOADER is not set diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 6f36f7b82e..248922cd56 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index b14786ed3d..5292ef96ee 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 8baac6fc70..3cbc949a01 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -15,7 +15,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 4ce6a09483..67526e87c0 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -34,7 +34,6 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 8d63c874cc..c3c29d38e5 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 91d9fdf961..522e60bbb5 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -28,7 +28,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_PART=y CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 40f6bb9830..3b2cbdcd44 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_PART=y CONFIG_CMD_SATA=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index 0b0198151b..a42d726b71 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -18,7 +18,6 @@ CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 5c89439f7b..1c027299b6 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_COLIBRI_IMX6ULL=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig index d808bd7608..8d6c0788f1 100644 --- a/configs/colibri-imx8qxp_defconfig +++ b/configs/colibri-imx8qxp_defconfig @@ -3,8 +3,8 @@ CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_TARGET_COLIBRI_IMX8X=y -CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=3 +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx8x/colibri-imx8qxp-imximage.cfg" CONFIG_LOG=y @@ -52,5 +52,4 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y # CONFIG_EFI_LOADER is not set diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index a60d6951c9..56e512d529 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -85,7 +84,7 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_HOST_ETHER=y CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index efbf5f55a3..e5e4168285 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SECURE_BOOT=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_NR_DRAM_BANKS=1 @@ -66,8 +65,8 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y -CONFIG_DM_USB=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 89f43e5fb9..06902b6311 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SECURE_BOOT=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_TARGET_COLIBRI_IMX7_EMMC=y @@ -45,6 +44,12 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_FSL_CAAM=y CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y @@ -59,22 +64,13 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DM_VIDEO=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_USB=y -CONFIG_FASTBOOT=y -CONFIG_FASTBOOT_USB_DEV=0 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x82000000 -CONFIG_FASTBOOT_BUF_SIZE=0x10000000 diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index d6a20ca642..170a1b0b27 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -67,4 +67,3 @@ CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 8bce6b75ef..338317203e 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index b3cf9704d7..4fdee998be 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index c11d5f2147..b05da76ef1 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 092ab42941..e575040a47 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -20,7 +20,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index d8b900f964..111011c854 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 70f0277040..d71bbced01 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -10,8 +10,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 -CONFIG_DM_GPIO=y -CONFIG_DM_MMC=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_AHCI=y @@ -46,6 +44,8 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/efi-x86_app_defconfig b/configs/efi-x86_app_defconfig index b4e8921f8c..ea3743dd12 100644 --- a/configs/efi-x86_app_defconfig +++ b/configs/efi-x86_app_defconfig @@ -14,7 +14,6 @@ CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTM is not set CONFIG_CMD_PART=y -# CONFIG_CMD_SF_TEST is not set # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index db088c0e97..ba5a501963 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index f282064fc7..3db70827a1 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 5ad49b38ec..c27c5ccf69 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SECURE_BOOT=y CONFIG_TARGET_MX6DL_MAMOJ=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index d39fd957a3..ad4b930a39 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index 8704006ae7..f6fc59ff5e 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index b65979967a..5ab932d0ae 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index 83b926b699..4b8998177b 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6Q_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index 318628b1a0..d5fdc43f48 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6UL_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 00c9bbd859..88b9b49781 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6UL_ENGICAM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index bc84a66b5f..f02b5e2084 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -3,7 +3,6 @@ CONFIG_SPL_SYS_ICACHE_OFF=y CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_IMX8MQ_EVK=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 1c67b98c5d..6db0669ef4 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -6,7 +6,6 @@ CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_IMX8QM_MEK=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index a375546a75..1f37729063 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -1,8 +1,8 @@ CONFIG_RISCV=y +CONFIG_TARGET_MICROCHIP_ICICLE=y CONFIG_ARCH_RV64I=y CONFIG_NR_CPUS=5 -CONFIG_TARGET_MICROCHIP_ICICLE=y +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_FIT=y CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 16df6ef137..446c2f2c03 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 89d542fef7..0739c581a7 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -82,16 +82,15 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_MII=y +CONFIG_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y -CONFIG_PCI=y CONFIG_DM_REGULATOR=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y -# CONFIG_SPL_DM_USB is not set CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index 97a94cbc36..5799ab39f4 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -6,16 +6,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -26,7 +27,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index e649ebb549..2a7807d360 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_MX6_DDRCAL=y CONFIG_TARGET_KOSAGI_NOVENA=y CONFIG_SPL_MMC_SUPPORT=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index badc4b0236..b0ec1208f5 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_OPOS6ULDEV=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 2a21ff1dd0..4bd8cd29f3 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -4,8 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=2 CONFIG_TEGRA210=y CONFIG_TARGET_P2371_2180=y -CONFIG_OF_SYSTEM_SETUP=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P2371-2180) # " diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 4ac810db35..808577167e 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -3,8 +3,8 @@ CONFIG_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=1026 CONFIG_TEGRA186=y -CONFIG_OF_SYSTEM_SETUP=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-000) # " diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 3ca85272a8..b222bfa446 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -3,8 +3,8 @@ CONFIG_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 CONFIG_NR_DRAM_BANKS=1026 CONFIG_TEGRA186=y -CONFIG_OF_SYSTEM_SETUP=y CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra186 (P2771-0000-500) # " diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 75408a8344..5c07b954b6 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -6,10 +6,9 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_PCL063_ULL=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_NR_DRAM_BANKS=8 CONFIG_SPL=y -# CONFIG_CMD_DEKBLOB is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_NR_DRAM_BANKS=8 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index b1cd5b4f44..d89cd44144 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 2a36f405f4..898d656ac3 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -21,7 +21,6 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 32da77aa39..be670df23f 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -6,16 +6,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -26,7 +27,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index 90bcaedbd2..e8fc7ae141 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -6,16 +6,17 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xFF1A0000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y @@ -26,7 +27,6 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_TPL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index bfb1eaf0e7..29a9df8ab0 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 4cffa2c604..6894262b89 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -44,7 +44,6 @@ CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_AXI=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index dda6832f83..af335285c9 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index ec8726b798..da9229fc79 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -37,7 +37,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 3e0bf5d3b5..d355cc3f3b 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -45,7 +45,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 0287314469..fe1aa8236b 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 66361c8715..5fe9477823 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -73,7 +73,7 @@ CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y -CONFIG_ETH_DESIGNWARE=y +CONFIG_DWC_ETH_QOS=y CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y CONFIG_PINCONF=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index f01e53055c..2653f71f78 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index a0586145d5..ee9189aeae 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 2f8eaa4402..7da1beaa99 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -24,7 +24,6 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y -CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 0e8cf73fe9..27a5fc0dfb 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -3,10 +3,10 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y -CONFIG_SPL_SIZE_LIMIT=30720 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_SIZE_LIMIT=30720 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEBUG_UART_BASE=0xff690000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/u200_defconfig b/configs/u200_defconfig index 2c0999c707..ced6ca84b6 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -15,6 +15,8 @@ CONFIG_MISC_INIT_R=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y @@ -27,6 +29,7 @@ CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ADDR=8 CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_G12A=y CONFIG_DM_REGULATOR=y @@ -36,21 +39,16 @@ CONFIG_DEBUG_UART_MESON=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_USB=y -CONFIG_USB_HOST=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_PHY=y -CONFIG_MESON_G12A_USB_PHY=y CONFIG_DM_USB=y -CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MESON_G12A=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/disk/part.c b/disk/part.c index 862078f3e7..f14bc22b6d 100644 --- a/disk/part.c +++ b/disk/part.c @@ -414,11 +414,10 @@ int blk_get_device_by_str(const char *ifname, const char *dev_hwpart_str, #ifdef CONFIG_HAVE_BLOCK_DEVICE /* * Updates the partition table for the specified hw partition. - * Does not need to be done for hwpart 0 since it is default and - * already loaded. + * Always should be done, otherwise hw partition 0 will return stale + * data after displaying a non-zero hw partition. */ - if(hwpart != 0) - part_init(*dev_desc); + part_init(*dev_desc); #endif cleanup: diff --git a/Documentation/Makefile b/doc/Makefile index 2ca77ad0f2..5135a96e88 100644 --- a/Documentation/Makefile +++ b/doc/Makefile @@ -8,7 +8,7 @@ subdir-y := SPHINXBUILD = sphinx-build SPHINXOPTS = SPHINXDIRS = . -_SPHINXDIRS = $(patsubst $(srctree)/Documentation/%/conf.py,%,$(wildcard $(srctree)/Documentation/*/conf.py)) +_SPHINXDIRS = $(patsubst $(srctree)/doc/%/conf.py,%,$(wildcard $(srctree)/doc/*/conf.py)) SPHINX_CONF = conf.py PAPER = BUILDDIR = $(obj)/output @@ -49,10 +49,10 @@ loop_cmd = $(echo-cmd) $(cmd_$(1)) || exit; # * cache folder relative to $(BUILDDIR)/.doctrees # $4 dest subfolder e.g. "man" for man pages at media/man # $5 reST source folder relative to $(srctree)/$(src), -# e.g. "media" for the linux-tv book-set at ./Documentation/media +# e.g. "media" for the linux-tv book-set at ./doc/media quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4) - cmd_sphinx = $(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/media $2 && \ + cmd_sphinx = $(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=doc/media $2 && \ PYTHONDONTWRITEBYTECODE=1 \ BUILDDIR=$(abspath $(BUILDDIR)) SPHINX_CONF=$(abspath $(srctree)/$(src)/$5/$(SPHINX_CONF)) \ $(SPHINXBUILD) \ @@ -102,7 +102,7 @@ refcheckdocs: cleandocs: $(Q)rm -rf $(BUILDDIR) - $(Q)$(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/media clean + $(Q)$(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=doc/media clean dochelp: @echo ' Linux kernel internal documentation in different formats from ReST:' @@ -121,4 +121,4 @@ dochelp: @echo ' make SPHINX_CONF={conf-file} [target] use *additional* sphinx-build' @echo ' configuration. This is e.g. useful to build with nit-picking config.' @echo - @echo ' Default location for the generated documents is Documentation/output' + @echo ' Default location for the generated documents is doc/output' diff --git a/Documentation/conf.py b/doc/conf.py index 168c31346b..168c31346b 100644 --- a/Documentation/conf.py +++ b/doc/conf.py diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/doc/device-tree-bindings/arm/l2c2x0.txt index fbe6cb21f4..fbe6cb21f4 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/doc/device-tree-bindings/arm/l2c2x0.txt diff --git a/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt b/doc/device-tree-bindings/axi/gdsys,ihs_axi.txt index 110788fa91..110788fa91 100644 --- a/Documentation/devicetree/bindings/axi/gdsys,ihs_axi.txt +++ b/doc/device-tree-bindings/axi/gdsys,ihs_axi.txt diff --git a/Documentation/devicetree/bindings/board/gdsys,board_gazerbeam.txt b/doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt index 28c1080d90..28c1080d90 100644 --- a/Documentation/devicetree/bindings/board/gdsys,board_gazerbeam.txt +++ b/doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt diff --git a/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt index 8313da8507..8313da8507 100644 --- a/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt +++ b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt diff --git a/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt index ac563d906a..ac563d906a 100644 --- a/Documentation/devicetree/bindings/cpu/fsl,mpc83xx.txt +++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt diff --git a/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt b/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt index 64a9b5b154..64a9b5b154 100644 --- a/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt +++ b/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt b/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt index db2ff8ca12..db2ff8ca12 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt b/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt index acd466fdc6..acd466fdc6 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt b/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt index 819db22bf7..819db22bf7 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt b/doc/device-tree-bindings/misc/misc/gdsys,soc.txt index 278e935b16..278e935b16 100644 --- a/Documentation/devicetree/bindings/misc/gdsys,soc.txt +++ b/doc/device-tree-bindings/misc/misc/gdsys,soc.txt diff --git a/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt b/doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt index da01fe908d..da01fe908d 100644 --- a/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt +++ b/doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/doc/device-tree-bindings/reserved-memory/reserved-memory.txt index bac4afa3b1..bac4afa3b1 100644 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +++ b/doc/device-tree-bindings/reserved-memory/reserved-memory.txt diff --git a/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt b/doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt index 608d24110b..608d24110b 100644 --- a/Documentation/devicetree/bindings/timer/fsl,mpc83xx-timer.txt +++ b/doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt diff --git a/Documentation/efi.rst b/doc/efi.rst index 5337a55c3b..5337a55c3b 100644 --- a/Documentation/efi.rst +++ b/doc/efi.rst diff --git a/Documentation/index.rst b/doc/index.rst index 0353c10a4b..0353c10a4b 100644 --- a/Documentation/index.rst +++ b/doc/index.rst diff --git a/Documentation/linker_lists.rst b/doc/linker_lists.rst index 72f514e0ac..72f514e0ac 100644 --- a/Documentation/linker_lists.rst +++ b/doc/linker_lists.rst diff --git a/Documentation/media/Makefile b/doc/media/Makefile index 0efd18ab4d..b9b43a34c3 100644 --- a/Documentation/media/Makefile +++ b/doc/media/Makefile @@ -1,7 +1,7 @@ # Rules to convert a .h file to inline RST documentation -SRC_DIR=$(srctree)/Documentation/media -PARSER = $(srctree)/Documentation/sphinx/parse-headers.pl +SRC_DIR=$(srctree)/doc/media +PARSER = $(srctree)/doc/sphinx/parse-headers.pl API = $(srctree)/include FILES = linker_lists.h.rst diff --git a/Documentation/media/linker_lists.h.rst.exceptions b/doc/media/linker_lists.h.rst.exceptions index e69de29bb2..e69de29bb2 100644 --- a/Documentation/media/linker_lists.h.rst.exceptions +++ b/doc/media/linker_lists.h.rst.exceptions diff --git a/Documentation/serial.rst b/doc/serial.rst index ed34e592a4..ed34e592a4 100644 --- a/Documentation/serial.rst +++ b/doc/serial.rst diff --git a/Documentation/sphinx-static/theme_overrides.css b/doc/sphinx-static/theme_overrides.css index 522b6d4c49..522b6d4c49 100644 --- a/Documentation/sphinx-static/theme_overrides.css +++ b/doc/sphinx-static/theme_overrides.css diff --git a/Documentation/sphinx/cdomain.py b/doc/sphinx/cdomain.py index cf13ff3a65..cf13ff3a65 100644 --- a/Documentation/sphinx/cdomain.py +++ b/doc/sphinx/cdomain.py diff --git a/Documentation/sphinx/kernel_include.py b/doc/sphinx/kernel_include.py index f523aa68a3..f523aa68a3 100755 --- a/Documentation/sphinx/kernel_include.py +++ b/doc/sphinx/kernel_include.py diff --git a/Documentation/sphinx/kerneldoc.py b/doc/sphinx/kerneldoc.py index fbedcc3946..fbedcc3946 100644 --- a/Documentation/sphinx/kerneldoc.py +++ b/doc/sphinx/kerneldoc.py diff --git a/Documentation/sphinx/kfigure.py b/doc/sphinx/kfigure.py index b97228d2cc..b97228d2cc 100644 --- a/Documentation/sphinx/kfigure.py +++ b/doc/sphinx/kfigure.py diff --git a/Documentation/sphinx/load_config.py b/doc/sphinx/load_config.py index 301a21aa4f..301a21aa4f 100644 --- a/Documentation/sphinx/load_config.py +++ b/doc/sphinx/load_config.py diff --git a/Documentation/sphinx/parse-headers.pl b/doc/sphinx/parse-headers.pl index d410f47567..d4f38262eb 100755 --- a/Documentation/sphinx/parse-headers.pl +++ b/doc/sphinx/parse-headers.pl @@ -382,7 +382,7 @@ ioctl. The EXCEPTIONS_FILE contain two rules to allow ignoring a symbol or to replace the default references by a custom one. -Please read Documentation/doc-guide/parse-headers.rst at the Kernel's +Please read doc/doc-guide/parse-headers.rst at the Kernel's tree for more details. =head1 BUGS diff --git a/Documentation/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 742be3e126..742be3e126 100644 --- a/Documentation/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt diff --git a/Documentation/sphinx/rstFlatTable.py b/doc/sphinx/rstFlatTable.py index 25feb0d35e..f9a4b46dbe 100755 --- a/Documentation/sphinx/rstFlatTable.py +++ b/doc/sphinx/rstFlatTable.py @@ -54,7 +54,7 @@ from docutils.utils import SystemMessagePropagation # ============================================================================== # The version numbering follows numbering of the specification -# (Documentation/books/kernel-doc-HOWTO). +# (doc/books/kernel-doc-HOWTO). __version__ = '1.0' PY3 = sys.version_info[0] == 3 diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 456c1b4cc9..71b52c6cf2 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -905,14 +905,14 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } -#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) +#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num) { int forbidden = 0; bool change = false; if (part_num & PART_ACCESS_MASK) - forbidden = MMC_CAP(MMC_HS_200); + forbidden = MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400); if (MMC_CAP(mmc->selected_mode) & forbidden) { pr_debug("selected mode (%s) is forbidden for part %d\n", diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 429bb836a8..3fe38f7315 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,6 +60,14 @@ config PCIE_DW_MVEBU Armada-8K SoCs. The PCIe controller on Armada-8K is based on DesignWare hardware. +config PCIE_FSL + bool "FSL PowerPC PCIe support" + depends on DM_PCI + help + Say Y here if you want to enable PCIe controller support on FSL + PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. + This driver does not support SRIO_PCIE_BOOT feature. + config PCI_RCAR_GEN2 bool "Renesas RCar Gen2 PCIe driver" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index bd392edba1..b5ebd50c85 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o +obj-$(CONFIG_PCIE_FSL) += pcie_fsl.o pcie_fsl_fixup.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ diff --git a/drivers/pci/pci_auto_common.c b/drivers/pci/pci_auto_common.c index 183787333e..84908e6154 100644 --- a/drivers/pci/pci_auto_common.c +++ b/drivers/pci/pci_auto_common.c @@ -21,9 +21,10 @@ void pciauto_region_init(struct pci_region *res) /* * Avoid allocating PCI resources from address 0 -- this is illegal * according to PCI 2.1 and moreover, this is known to cause Linux IDE - * drivers to fail. Use a reasonable starting value of 0x1000 instead. + * drivers to fail. Use a reasonable starting value of 0x1000 instead + * if the bus start address is below 0x1000. */ - res->bus_lower = res->bus_start ? res->bus_start : 0x1000; + res->bus_lower = res->bus_start < 0x1000 ? 0x1000 : res->bus_start; } void pciauto_region_align(struct pci_region *res, pci_size_t size) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c new file mode 100644 index 0000000000..4d61a46cef --- /dev/null +++ b/drivers/pci/pcie_fsl.c @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 NXP + * + * PCIe DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + */ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <mapmem.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_serdes.h> +#include <asm/io.h> +#include "pcie_fsl.h" + +LIST_HEAD(fsl_pcie_list); + +static int fsl_pcie_link_up(struct fsl_pcie *pcie); + +static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf) +{ + struct udevice *bus = pcie->bus; + + if (!pcie->enabled) + return -ENXIO; + + if (PCI_BUS(bdf) < bus->seq) + return -EINVAL; + + if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode)) + return -EINVAL; + + if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0)) + return -EINVAL; + + if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0)) + return -EINVAL; + + return 0; +} + +static int fsl_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + struct fsl_pcie *pcie = dev_get_priv(bus); + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + + if (fsl_pcie_addr_valid(pcie, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + + bdf = bdf - PCI_BDF(bus->seq, 0, 0); + val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + out_be32(®s->cfg_addr, val); + + sync(); + + switch (size) { + case PCI_SIZE_8: + *valuep = in_8((u8 *)®s->cfg_data + (offset & 3)); + break; + case PCI_SIZE_16: + *valuep = in_le16((u16 *)((u8 *)®s->cfg_data + + (offset & 2))); + break; + case PCI_SIZE_32: + *valuep = in_le32(®s->cfg_data); + break; + } + + return 0; +} + +static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + struct fsl_pcie *pcie = dev_get_priv(bus); + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + u8 val_8; + u16 val_16; + u32 val_32; + + if (fsl_pcie_addr_valid(pcie, bdf)) + return 0; + + bdf = bdf - PCI_BDF(bus->seq, 0, 0); + val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; + out_be32(®s->cfg_addr, val); + + sync(); + + switch (size) { + case PCI_SIZE_8: + val_8 = value; + out_8((u8 *)®s->cfg_data + (offset & 3), val_8); + break; + case PCI_SIZE_16: + val_16 = value; + out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16); + break; + case PCI_SIZE_32: + val_32 = value; + out_le32(®s->cfg_data, val_32); + break; + } + + return 0; +} + +static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset, + ulong *valuep, enum pci_size_t size) +{ + int ret; + struct udevice *bus = pcie->bus; + + ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0), + offset, valuep, size); + + return ret; +} + +static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset, + ulong value, enum pci_size_t size) +{ + struct udevice *bus = pcie->bus; + + return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0), + offset, value, size); +} + +static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset, + u8 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset, + u16 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset, + u32 *valuep) +{ + ulong val; + int ret; + + ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32); + *valuep = val; + + return ret; +} + +static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset, + u8 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8); +} + +static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset, + u16 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16); +} + +static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset, + u32 value) +{ + return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32); +} + +static int fsl_pcie_link_up(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u16 ltssm; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + ltssm = (in_be32(®s->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + return ltssm == LTSSM_L0_REV3; + } + + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + + return ltssm == LTSSM_L0; +} + +static bool fsl_pcie_is_agent(struct fsl_pcie *pcie) +{ + u8 header_type; + + fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type); + + return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL; +} + +static int fsl_pcie_setup_law(struct fsl_pcie *pcie) +{ + struct pci_region *io, *mem, *pref; + + pci_get_regions(pcie->bus, &io, &mem, &pref); + + if (mem) + set_next_law(mem->phys_start, + law_size_bits(mem->size), + pcie->law_trgt_if); + + if (io) + set_next_law(io->phys_start, + law_size_bits(io->size), + pcie->law_trgt_if); + + return 0; +} + +static void fsl_pcie_config_ready(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY); + return; + } + + fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1); +} + +static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx, + int type, u64 phys, u64 bus_addr, + pci_size_t size) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + pot_t *po = ®s->pot[idx]; + u32 war, sz; + + if (idx < 0) + return -EINVAL; + + out_be32(&po->powbar, phys >> 12); + out_be32(&po->potar, bus_addr >> 12); +#ifdef CONFIG_SYS_PCI_64BIT + out_be32(&po->potear, bus_addr >> 44); +#else + out_be32(&po->potear, 0); +#endif + + sz = (__ilog2_u64((u64)size) - 1); + war = POWAR_EN | sz; + + if (type == PCI_REGION_IO) + war |= POWAR_IO_READ | POWAR_IO_WRITE; + else + war |= POWAR_MEM_READ | POWAR_MEM_WRITE; + + out_be32(&po->powar, war); + + return 0; +} + +static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx, + bool pf, u64 phys, u64 bus_addr, + pci_size_t size) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + pit_t *pi = ®s->pit[idx]; + u32 sz = (__ilog2_u64(size) - 1); + u32 flag = PIWAR_LOCAL; + + if (idx < 0) + return -EINVAL; + + out_be32(&pi->pitar, phys >> 12); + out_be32(&pi->piwbar, bus_addr >> 12); + +#ifdef CONFIG_SYS_PCI_64BIT + out_be32(&pi->piwbear, bus_addr >> 44); +#else + out_be32(&pi->piwbear, 0); +#endif + + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434)) + flag = 0; + + flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; + if (pf) + flag |= PIWAR_PF; + out_be32(&pi->piwar, flag | sz); + + return 0; +} + +static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie) +{ + struct pci_region *io, *mem, *pref; + int idx = 1; /* skip 0 */ + + pci_get_regions(pcie->bus, &io, &mem, &pref); + + if (io) + /* ATU : OUTBOUND : IO */ + fsl_pcie_setup_outbound_win(pcie, idx++, + PCI_REGION_IO, + io->phys_start, + io->bus_start, + io->size); + + if (mem) + /* ATU : OUTBOUND : MEM */ + fsl_pcie_setup_outbound_win(pcie, idx++, + PCI_REGION_MEM, + mem->phys_start, + mem->bus_start, + mem->size); + return 0; +} + +static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) +{ + phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; + pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; + u64 sz = min((u64)gd->ram_size, (1ull << 32)); + pci_size_t pci_sz; + int idx; + + if (pcie->block_rev >= PEX_IP_BLK_REV_2_2) + idx = 2; + else + idx = 3; + + pci_sz = 1ull << __ilog2_u64(sz); + + dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)bus_start, (u64)phys_start, (u64)sz); + + /* if we aren't an exact power of two match, pci_sz is smaller + * round it up to the next power of two. We report the actual + * size to pci region tracking. + */ + if (pci_sz != sz) + sz = 2ull << __ilog2_u64(sz); + + fsl_pcie_setup_inbound_win(pcie, idx--, true, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_BUS, sz); +#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) + /* + * On 64-bit capable systems, set up a mapping for all of DRAM + * in high pci address space. + */ + pci_sz = 1ull << __ilog2_u64(gd->ram_size); + /* round up to the next largest power of two */ + if (gd->ram_size > pci_sz) + pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); + + dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n", + (u64)CONFIG_SYS_PCI64_MEMORY_BUS, + (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); + + fsl_pcie_setup_inbound_win(pcie, idx--, true, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz); +#endif + + return 0; +} + +static int fsl_pcie_init_atmu(struct fsl_pcie *pcie) +{ + fsl_pcie_setup_outbound_wins(pcie); + fsl_pcie_setup_inbound_wins(pcie); + + return 0; +} + +static int fsl_pcie_init_port(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val_32; + u16 val_16; + + fsl_pcie_init_atmu(pcie); + + if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) { + val_32 = 0; + fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); + val_32 &= ~0x03; + fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); + udelay(1); + } + + if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) { + u16 ltssm; + int i; + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } else { + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + if (ltssm == 1) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(100); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && + !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } + } + } + + if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) && + !fsl_pcie_link_up(pcie)) { + serdes_corenet_t *srds_regs; + + srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + val_32 = in_be32(&srds_regs->srdspccr0); + + if ((val_32 >> 28) == 3) { + int i; + + out_be32(&srds_regs->srdspccr0, 2 << 28); + setbits_be32(®s->pdb_stat, 0x08000000); + in_be32(®s->pdb_stat); + udelay(100); + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } + } + + /* + * The Read-Only Write Enable bit defaults to 1 instead of 0. + * Set to 0 to protect the read-only registers. + */ + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815)) + clrbits_be32(®s->dbi_ro_wr_en, 0x01); + + /* + * Enable All Error Interrupts except + * - Master abort (pci) + * - Master PERR (pci) + * - ICCA (PCIe) + */ + out_be32(®s->peer, ~0x20140); + + /* set URR, FER, NFER (but not CER) */ + fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32); + val_32 |= 0xf000e; + fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32); + + /* Clear all error indications */ + out_be32(®s->pme_msg_det, 0xffffffff); + out_be32(®s->pme_msg_int_en, 0xffffffff); + out_be32(®s->pedr, 0xffffffff); + + fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16); + if (val_16) + fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff); + + fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16); + if (val_16) + fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff); + + return 0; +} + +static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) +{ + ccsr_fsl_pci_t *regs = pcie->regs; + u32 val; + + setbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + val &= 0xff; + val |= PCI_CLASS_BRIDGE_PCI << 16; + fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); + clrbits_be32(®s->dbi_ro_wr_en, 0x01); + + return 0; +} + +static int fsl_pcie_init_rc(struct fsl_pcie *pcie) +{ + return fsl_pcie_fixup_classcode(pcie); +} + +static int fsl_pcie_init_ep(struct fsl_pcie *pcie) +{ + fsl_pcie_config_ready(pcie); + + return 0; +} + +static int fsl_pcie_probe(struct udevice *dev) +{ + struct fsl_pcie *pcie = dev_get_priv(dev); + ccsr_fsl_pci_t *regs = pcie->regs; + u16 val_16; + + pcie->bus = dev; + pcie->block_rev = in_be32(®s->block_rev1); + + list_add(&pcie->list, &fsl_pcie_list); + pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx); + if (!pcie->enabled) { + printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); + return 0; + } + + fsl_pcie_setup_law(pcie); + + pcie->mode = fsl_pcie_is_agent(pcie); + + fsl_pcie_init_port(pcie); + + printf("PCIe%d: %s ", pcie->idx, dev->name); + + if (pcie->mode) { + printf("Endpoint"); + fsl_pcie_init_ep(pcie); + } else { + printf("Root Complex"); + fsl_pcie_init_rc(pcie); + } + + if (!fsl_pcie_link_up(pcie)) { + printf(": %s\n", pcie->mode ? "undetermined link" : "no link"); + return 0; + } + + fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16); + printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf)); + + return 0; +} + +static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) +{ + struct fsl_pcie *pcie = dev_get_priv(dev); + int ret; + + pcie->regs = dev_remap_addr(dev); + if (!pcie->regs) { + pr_err("\"reg\" resource not found\n"); + return -EINVAL; + } + + ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if); + if (ret < 0) { + pr_err("\"law_trgt_if\" not found\n"); + return ret; + } + + pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + + return 0; +} + +static const struct dm_pci_ops fsl_pcie_ops = { + .read_config = fsl_pcie_read_config, + .write_config = fsl_pcie_write_config, +}; + +static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-t2080" }, + { } +}; + +U_BOOT_DRIVER(fsl_pcie) = { + .name = "fsl_pcie", + .id = UCLASS_PCI, + .of_match = fsl_pcie_ids, + .ops = &fsl_pcie_ops, + .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata, + .probe = fsl_pcie_probe, + .priv_auto_alloc_size = sizeof(struct fsl_pcie), +}; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h new file mode 100644 index 0000000000..5eefc31fa9 --- /dev/null +++ b/drivers/pci/pcie_fsl.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * + * PCIe DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + */ + +#ifndef _PCIE_FSL_H_ +#define _PCIE_FSL_H_ + +#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +#define FSL_PCIE_CAP_ID 0x70 +#else +#define FSL_PCIE_CAP_ID 0x4c +#endif +/* PCIe Device Control Register */ +#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08) +/* PCIe Device Status Register */ +#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a) +/* PCIe Link Control Register */ +#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10) +/* PCIe Link Status Register */ +#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12) + +#ifndef CONFIG_SYS_PCI_MEMORY_BUS +#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#endif + +#ifndef CONFIG_SYS_PCI_MEMORY_PHYS +#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#endif + +#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) +#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#endif + +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define LTSSM_L0_REV3 0x11 +#define LTSSM_L0 0x16 + +struct fsl_pcie { + int idx; + struct udevice *bus; + void __iomem *regs; + u32 law_trgt_if; /* LAW target ID */ + u32 block_rev; /* IP block revision */ + bool mode; /* RC&EP mode flag */ + bool enabled; /* Enable status */ + struct list_head list; +}; + +extern struct list_head fsl_pcie_list; + +#endif /* _PCIE_FSL_H_ */ diff --git a/drivers/pci/pcie_fsl_fixup.c b/drivers/pci/pcie_fsl_fixup.c new file mode 100644 index 0000000000..cbdc0ef291 --- /dev/null +++ b/drivers/pci/pcie_fsl_fixup.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 NXP + * + * PCIe Kernel DT fixup of DM U-Boot driver for Freescale PowerPC SoCs + * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + */ + +#include <common.h> +#ifdef CONFIG_OF_BOARD_SETUP +#include <dm.h> +#include <fdt_support.h> +#include <asm/fsl_pci.h> +#include <linux/libfdt.h> +#include "pcie_fsl.h" + +static void ft_fsl_pcie_setup(void *blob, struct fsl_pcie *pcie) +{ + struct pci_controller *hose = dev_get_uclass_priv(pcie->bus); + fdt_addr_t regs_addr; + int off; + + regs_addr = dev_read_addr(pcie->bus); + off = fdt_node_offset_by_compat_reg(blob, FSL_PCIE_COMPAT, regs_addr); + if (off < 0) { + printf("%s: Fail to find PCIe node@0x%pa\n", + FSL_PCIE_COMPAT, ®s_addr); + return; + } + + if (!hose || !pcie->enabled) + fdt_del_node(blob, off); + else + fdt_pci_dma_ranges(blob, off, hose); +} + +/* Fixup Kernel DT for PCIe */ +void pci_of_setup(void *blob, bd_t *bd) +{ + struct fsl_pcie *pcie; + + list_for_each_entry(pcie, &fsl_pcie_list, list) + ft_fsl_pcie_setup(blob, pcie); +} + +#else +void pci_of_setup(void *blob, bd_t *bd) +{ +} +#endif diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index 494ab533cc..35f4147840 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -1039,8 +1039,10 @@ static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) int node = dev_of_offset(dev); ulong drvdata; void (*set_params)(struct dwc2_plat_otg_data *data); + int ret; - if (usb_get_dr_mode(node) != USB_DR_MODE_PERIPHERAL) { + if (usb_get_dr_mode(node) != USB_DR_MODE_PERIPHERAL && + usb_get_dr_mode(node) != USB_DR_MODE_OTG) { dev_dbg(dev, "Invalid mode\n"); return -ENODEV; } @@ -1050,7 +1052,18 @@ static int dwc2_udc_otg_ofdata_to_platdata(struct udevice *dev) platdata->rx_fifo_sz = dev_read_u32_default(dev, "g-rx-fifo-size", 0); platdata->np_tx_fifo_sz = dev_read_u32_default(dev, "g-np-tx-fifo-size", 0); - platdata->tx_fifo_sz = dev_read_u32_default(dev, "g-tx-fifo-size", 0); + + platdata->tx_fifo_sz_nb = + dev_read_size(dev, "g-tx-fifo-size") / sizeof(u32); + if (platdata->tx_fifo_sz_nb > DWC2_MAX_HW_ENDPOINTS) + platdata->tx_fifo_sz_nb = DWC2_MAX_HW_ENDPOINTS; + if (platdata->tx_fifo_sz_nb) { + ret = dev_read_u32_array(dev, "g-tx-fifo-size", + platdata->tx_fifo_sz_array, + platdata->tx_fifo_sz_nb); + if (ret) + return ret; + } platdata->force_b_session_valid = dev_read_bool(dev, "u-boot,force-b-session-valid"); diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c index 523484b1ff..d344d54aee 100644 --- a/drivers/watchdog/ast_wdt.c +++ b/drivers/watchdog/ast_wdt.c @@ -23,6 +23,12 @@ static int ast_wdt_start(struct udevice *dev, u64 timeout, ulong flags) ulong driver_data = dev_get_driver_data(dev); u32 reset_mode = ast_reset_mode_from_flags(flags); + /* 32 bits at 1MHz is 4294967ms */ + timeout = min_t(u64, timeout, 4294967); + + /* WDT counts in ticks of 1MHz clock. 1ms / 1e3 * 1e6 */ + timeout *= 1000; + clrsetbits_le32(&priv->regs->ctrl, WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT, reset_mode << WDT_CTRL_RESET_MODE_SHIFT); diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 0b501733f2..a7d4c7a3b8 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -70,18 +70,30 @@ static int mtk_wdt_expire_now(struct udevice *dev, ulong flags) return 0; } -static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout) +static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout_ms) { struct mtk_wdt_priv *priv = dev_get_priv(dev); /* - * One bit is the value of 512 ticks - * The clock has 32 KHz + * One WDT_LENGTH count is 512 ticks of the wdt clock + * Clock runs at 32768 Hz + * e.g. 15.625 ms per count (nominal) + * We want the ceiling after dividing timeout_ms by 15.625 ms + * We add 15624 prior to the divide to implement the ceiling + * We prevent over-flow by clamping the timeout_ms value here + * as the maximum WDT_LENGTH counts is 1023 -> 15.984375 sec + * We also enforce a minimum of 1 count + * Many watchdog peripherals have a self-imposed count of 1 + * that is added to the register counts. + * The MediaTek docs lack details to know if this is the case here. + * So we enforce a minimum of 1 to guarantee operation. */ - timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY; - writel(timeout, priv->base + MTK_WDT_LENGTH); - - mtk_wdt_reset(dev); + if(timeout_ms > 15984) timeout_ms = 15984; + u64 timeout_us = timeout_ms * 1000; + u32 timeout_cc = (u32) ( (15624 + timeout_us) / 15625 ); + if(timeout_cc == 0) timeout_cc = 1; + u32 length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY; + writel(length, priv->base + MTK_WDT_LENGTH); } static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags) @@ -90,6 +102,8 @@ static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags) mtk_wdt_set_timeout(dev, timeout); + mtk_wdt_reset(dev); + /* Enable watchdog reset signal */ setbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 4993303f4d..26e61ef196 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -229,10 +229,23 @@ #endif #ifdef CONFIG_IDE -#define BOOTENV_SHARED_IDE BOOTENV_SHARED_BLKDEV(ide) +#define BOOTENV_RUN_IDE_INIT "run ide_init; " +#define BOOTENV_SET_IDE_NEED_INIT "setenv ide_need_init; " +#define BOOTENV_SHARED_IDE \ + "ide_init=" \ + "if ${ide_need_init}; then " \ + "setenv ide_need_init false; " \ + "ide reset; " \ + "fi\0" \ + \ + "ide_boot=" \ + BOOTENV_RUN_IDE_INIT \ + BOOTENV_SHARED_BLKDEV_BODY(ide) #define BOOTENV_DEV_IDE BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_IDE BOOTENV_DEV_NAME_BLKDEV #else +#define BOOTENV_RUN_IDE_INIT +#define BOOTENV_SET_IDE_NEED_INIT #define BOOTENV_SHARED_IDE #define BOOTENV_DEV_IDE \ BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE @@ -451,6 +464,7 @@ \ "distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT \ BOOTENV_SET_NVME_NEED_INIT \ + BOOTENV_SET_IDE_NEED_INIT \ "for target in ${boot_targets}; do " \ "run bootcmd_${target}; " \ "done\0" diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 1537b45cc1..1c615acb3b 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -57,7 +57,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index e9371a025b..5a1a29bd9e 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -66,7 +66,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 819129033f..7697e8d3e0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -36,7 +36,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 280b873aee..2cbe855235 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -16,7 +16,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index be600becfe..b37601c794 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -20,7 +20,6 @@ #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 5515b9232c..01ee69c013 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -16,7 +16,6 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3c6661fc83..de187bf9a4 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -15,7 +15,6 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 13fbbb3044..e3952f423b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,7 +27,6 @@ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 025aa33083..1152bca03b 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -115,7 +115,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 62943a3b0c..4b2eb6525b 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -81,7 +81,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 7fe34c332e..9535a7bbb2 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -24,7 +24,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #ifndef __ASSEMBLY__ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb3342b9..54ec1abd66 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -491,50 +491,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4b53e19fd4..ab92ca3b68 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -476,7 +476,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index b518c222d4..268a41c82c 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2013-2015 Arcturus Networks, Inc. - * http://www.arcturusnetworks.com/products/ucp1020/ + * Copyright 2013-2019 Arcturus Networks, Inc. + * https://www.arcturusnetworks.com/products/ucp1020/ * based on include/configs/p1_p2_rdb_pc.h * original copyright follows: * Copyright 2009-2011 Freescale Semiconductor, Inc. @@ -13,11 +13,66 @@ #ifndef __CONFIG_H #define __CONFIG_H +/*** Arcturus FirmWare Environment */ + +#define MAX_SERIAL_SIZE 15 +#define MAX_HWADDR_SIZE 17 + +#define MAX_FWENV_ADDR 4 + +#define FWENV_MMC 1 +#define FWENV_SPI_FLASH 2 +#define FWENV_NOR_FLASH 3 +/* + #define FWENV_TYPE FWENV_MMC + #define FWENV_TYPE FWENV_SPI_FLASH +*/ +#define FWENV_TYPE FWENV_NOR_FLASH + +#if (FWENV_TYPE == FWENV_MMC) +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV 1 +#endif +#define FWENV_ADDR1 -1 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0 +#endif + +#if (FWENV_TYPE == FWENV_SPI_FLASH) +#ifndef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#endif +#ifndef CONFIG_SF_DEFAULT_MODE +#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 +#endif +#ifndef CONFIG_SF_DEFAULT_CS +#define CONFIG_SF_DEFAULT_CS 0 +#endif +#ifndef CONFIG_SF_DEFAULT_BUS +#define CONFIG_SF_DEFAULT_BUS 0 +#endif +#define FWENV_ADDR1 (0x200 - sizeof(smac)) +#define FWENV_ADDR2 (0x400 - sizeof(smac)) +#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) +#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) +#define EMPY_CHAR 0xff +#endif + +#if (FWENV_TYPE == FWENV_NOR_FLASH) +#define FWENV_ADDR1 0xEC080000 +#define FWENV_ADDR2 -1 +#define FWENV_ADDR3 -1 +#define FWENV_ADDR4 -1 +#define EMPY_CHAR 0xff +#endif +/***********************************/ + #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #if defined(CONFIG_TARTGET_UCP1020T1) @@ -38,8 +93,6 @@ #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_ETHPRIME "eTSEC3" -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -52,7 +105,6 @@ #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" #define CONFIG_TSEC1 -#define CONFIG_TSEC2 #define CONFIG_TSEC3 #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 @@ -68,7 +120,7 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_ETHPRIME "eTSEC1" -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#undef CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SYS_L2_SIZE (256 << 10) diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index f1c3522c68..19223e2947 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -204,7 +204,6 @@ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d9312bd149..e07d2a178f 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -209,7 +209,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index e42b9b0cb9..1e0708a71b 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -34,7 +34,6 @@ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 9df8604af7..ba613672eb 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif #ifdef CONFIG_PCIE1 -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #endif #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 22dd3c036e..0a87f226f8 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -22,7 +22,6 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ /* * Multicore config diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index a7c8dc4e33..0389874609 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -22,7 +22,6 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ /* * Multicore config diff --git a/lib/Makefile b/lib/Makefile index 09c45b8122..2fffd68f94 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -88,7 +88,7 @@ obj-y += crc32.o obj-$(CONFIG_CRC32C) += crc32c.o obj-y += ctype.o obj-y += div64.o -obj-$(CONFIG_OF_LIBFDT) += fdtdec.o +obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdtdec.o fdtdec_common.o obj-y += hang.o obj-y += linux_compat.o obj-y += linux_string.o diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 22de7a4b6c..d252045d80 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,6 +1,5 @@ CONFIG_16BIT CONFIG_33 -CONFIG_400MHZ_MODE CONFIG_64BIT_PHYS_ADDR CONFIG_66 CONFIG_8349_CLKIN @@ -238,9 +237,7 @@ CONFIG_CONS_ON_SCC CONFIG_CONS_SCIF0 CONFIG_CONS_SCIF1 CONFIG_CONS_SCIF2 -CONFIG_CONS_SCIF3 CONFIG_CONS_SCIF4 -CONFIG_CONS_SCIF5 CONFIG_CONTROL CONFIG_CONTROLCENTERD CONFIG_CON_ROT @@ -268,9 +265,6 @@ CONFIG_CPU_PXA27X CONFIG_CPU_PXA300 CONFIG_CPU_R8000 CONFIG_CPU_SH7722 -CONFIG_CPU_SH7723 -CONFIG_CPU_SH7734 -CONFIG_CPU_SH7750 CONFIG_CPU_SH7751 CONFIG_CPU_SH7752 CONFIG_CPU_SH7753 @@ -372,7 +366,6 @@ CONFIG_DRIVER_NE2000_BASE CONFIG_DRIVER_NE2000_CCR CONFIG_DRIVER_NE2000_VAL CONFIG_DRIVER_SMC911X_BASE -CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE CONFIG_DRIVER_TI_EMAC_USE_RMII CONFIG_DSP_CLUSTER_START CONFIG_DUOVERO @@ -614,8 +607,6 @@ CONFIG_FSL_LBC CONFIG_FSL_MC9SDZ60 CONFIG_FSL_MEMAC CONFIG_FSL_NGPIXIS -CONFIG_FSL_PCIE_DISABLE_ASPM -CONFIG_FSL_PCIE_RESET CONFIG_FSL_PCI_INIT CONFIG_FSL_PIXIS CONFIG_FSL_PMIC_BITLEN @@ -685,7 +676,6 @@ CONFIG_GICV2 CONFIG_GLOBAL_DATA_NOT_REG10 CONFIG_GLOBAL_TIMER CONFIG_GMII -CONFIG_GOOD_SESH4 CONFIG_GPCNTRL CONFIG_GPIO_ENABLE_SPI_FLASH CONFIG_GPIO_LED_INVERTED_TABLE @@ -923,9 +913,6 @@ CONFIG_IO_TRACE CONFIG_IPADDR CONFIG_IPADDR1 CONFIG_IPADDR2 -CONFIG_IPAM390_GPIO_BOOTMODE -CONFIG_IPAM390_GPIO_LED_GREEN -CONFIG_IPAM390_GPIO_LED_RED CONFIG_IPROC CONFIG_IRAM_BASE CONFIG_IRAM_END @@ -1072,7 +1059,6 @@ CONFIG_LCD_INFO_BELOW_LOGO CONFIG_LCD_IN_PSRAM CONFIG_LCD_LOGO CONFIG_LCD_MENU -CONFIG_LCD_ROTATION CONFIG_LD9040 CONFIG_LEGACY CONFIG_LEGACY_BOOTCMD_ENV @@ -1135,7 +1121,6 @@ CONFIG_MACRESET_TIMEOUT CONFIG_MALLOC_F_ADDR CONFIG_MALTA CONFIG_MARCO_MEMSET -CONFIG_MARUBUN_PCCARD CONFIG_MARVELL_GPIO CONFIG_MARVELL_MFP CONFIG_MASK_AER_AO @@ -1601,7 +1586,6 @@ CONFIG_SATA1 CONFIG_SATA2 CONFIG_SATA_ULI5288 CONFIG_SCF0403_LCD -CONFIG_SCIF CONFIG_SCIF_A CONFIG_SCIF_USE_EXT_CLK CONFIG_SCSI_AHCI_PLAT @@ -1701,7 +1685,6 @@ CONFIG_SMSTP7_ENA CONFIG_SMSTP8_ENA CONFIG_SMSTP9_ENA CONFIG_SOCRATES -CONFIG_SOC_DM644X CONFIG_SOC_K2E CONFIG_SOC_K2G CONFIG_SOC_K2HK @@ -1858,7 +1841,6 @@ CONFIG_STRIDER_CON_DP CONFIG_STRIDER_CPU CONFIG_STRIDER_CPU_DP CONFIG_STRIDER_FANS -CONFIG_STUART CONFIG_STV0991 CONFIG_STV0991_HZ CONFIG_STV0991_HZ_CLOCK @@ -2135,8 +2117,6 @@ CONFIG_SYS_CSPR6 CONFIG_SYS_CSPR6_EXT CONFIG_SYS_CSPR7 CONFIG_SYS_CSPR7_EXT -CONFIG_SYS_DA850_CS2CFG -CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_DDR2_DDRPHYCR CONFIG_SYS_DA850_DDR2_PBBPR CONFIG_SYS_DA850_DDR2_SDBCR @@ -3402,7 +3382,6 @@ CONFIG_SYS_NAND_MASK_CLE CONFIG_SYS_NAND_MAX_ECCPOS CONFIG_SYS_NAND_MAX_OOBFREE CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES -CONFIG_SYS_NAND_NO_SUBPAGE CONFIG_SYS_NAND_NO_SUBPAGE_WRITE CONFIG_SYS_NAND_ONFI_DETECTION CONFIG_SYS_NAND_OR_PRELIM @@ -4209,9 +4188,6 @@ CONFIG_SYS_VXWORKS_MAC_PTR CONFIG_SYS_WATCHDOG_FREQ CONFIG_SYS_WATCHDOG_VALUE CONFIG_SYS_WDTC_WDMR_VAL -CONFIG_SYS_WDTTIMERBASE -CONFIG_SYS_WDT_PERIOD_HIGH -CONFIG_SYS_WDT_PERIOD_LOW CONFIG_SYS_WINDOW1_BASE CONFIG_SYS_WRITE_SWAPPED_DATA CONFIG_SYS_XHCI_USB1_ADDR @@ -4222,7 +4198,6 @@ CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL CONFIG_TAM3517_SETTINGS -CONFIG_TAM3517_SW3_SETTINGS CONFIG_TCA642X CONFIG_TEGRA_BOARD_STRING CONFIG_TEGRA_CLOCK_SCALING @@ -4454,7 +4429,6 @@ CONFIG_X86_REFCODE_ADDR CONFIG_X86_REFCODE_RUN_ADDR CONFIG_XGI_XG22_BASE CONFIG_XILINX_SPI_IDLE_VAL -CONFIG_XR16L2751 CONFIG_XSENGINE CONFIG_XTFPGA CONFIG_YAFFSFS_PROVIDE_VALUES diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index cfada0ee11..eef12dd2b7 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1317,7 +1317,7 @@ static int flash_io_write(int fd_current) rc = -1; } - if (target_temp) { + if (rc >= 0 && target_temp) { int dir_fd; dir_fd = open(dname, O_DIRECTORY | O_RDONLY); |