diff options
315 files changed, 5709 insertions, 13473 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 194fb7bd8b..c598f5e4c1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -62,6 +62,12 @@ config SEMIHOSTING the hosted environment to call out to the emulator to retrieve files from the host machine. +config SYS_L2CACHE_OFF + bool "L2cache off" + help + If SoC does not support L2CACHE or one do not want to enable + L2CACHE, choose this option. + choice prompt "Target select" default ARCH_VERSATILE @@ -511,112 +517,6 @@ config TARGET_VISION2 bool "Support vision2" select CPU_V7 -config TARGET_UDOO - bool "Support udoo" - select CPU_V7 - -config TARGET_WANDBOARD - bool "Support wandboard" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_WARP - bool "Support WaRP" - select CPU_V7 - -config TARGET_TITANIUM - bool "Support titanium" - select CPU_V7 - -config TARGET_NITROGEN6X - bool "Support nitrogen6x" - select CPU_V7 - -config TARGET_CGTQMX6EVAL - bool "Support cgtqmx6eval" - select CPU_V7 - -config TARGET_EMBESTMX6BOARDS - bool "Support embestmx6boards" - select CPU_V7 - -config TARGET_ARISTAINETOS - bool "Support aristainetos" - select CPU_V7 - -config TARGET_ARISTAINETOS2 - bool "Support aristainetos2" - select CPU_V7 - -config TARGET_MX6QARM2 - bool "Support mx6qarm2" - select CPU_V7 - -config TARGET_MX6QSABREAUTO - bool "Support mx6qsabreauto" - select CPU_V7 - select DM - select DM_THERMAL - -config TARGET_MX6SABRESD - bool "Support mx6sabresd" - select CPU_V7 - select SUPPORT_SPL - select DM - select DM_THERMAL - -config TARGET_MX6CUBOXI - bool "Support Solid-run mx6 boards" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_MX6SLEVK - bool "Support mx6slevk" - select CPU_V7 - -config TARGET_MX6SXSABRESD - bool "Support mx6sxsabresd" - select CPU_V7 - select SUPPORT_SPL - select DM - select DM_THERMAL - -config TARGET_MX6UL_14X14_EVK - bool "Support mx6ul_14x14_evk" - select CPU_V7 - select DM - select DM_THERMAL - select SUPPORT_SPL - -config TARGET_GW_VENTANA - bool "Support gw_ventana" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_KOSAGI_NOVENA - bool "Support Kosagi Novena" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_TBS2910 - bool "Support tbs2910" - select CPU_V7 - -config TARGET_OT1200 - bool "Bachmann OT1200" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_PLATINUM_PICON - bool "Support platinum-picon" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_PLATINUM_TITANIUM - bool "Support platinum-titanium" - select CPU_V7 - select SUPPORT_SPL - config OMAP34XX bool "OMAP34XX SoC" select CPU_V7 @@ -666,6 +566,10 @@ config TARGET_SNOWBALL bool "Support snowball" select CPU_V7 +config TARGET_TS4800 + bool "Support TS4800" + select CPU_V7 + config TARGET_U8500_HREF bool "Support u8500_href" select CPU_V7 @@ -893,7 +797,6 @@ source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/imx-common/Kconfig" -source "board/aristainetos/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" @@ -904,26 +807,18 @@ source "board/Marvell/gplugd/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" -source "board/hisilicon/hikey/Kconfig" -source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" -source "board/barco/platinum/Kconfig" -source "board/barco/titanium/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" -source "board/boundary/nitrogen6x/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" source "board/cirrus/edb93xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" -source "board/compulab/cm_fx6/Kconfig" -source "board/congatec/cgtqmx6eval/Kconfig" source "board/creative/xfi3/Kconfig" source "board/davedenx/qong/Kconfig" source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" -source "board/embest/mx6boards/Kconfig" source "board/esg/ima3-mx53/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls2085aqds/Kconfig" @@ -941,24 +836,17 @@ source "board/freescale/mx53ard/Kconfig" source "board/freescale/mx53evk/Kconfig" source "board/freescale/mx53loco/Kconfig" source "board/freescale/mx53smd/Kconfig" -source "board/freescale/mx6qarm2/Kconfig" -source "board/freescale/mx6qsabreauto/Kconfig" -source "board/freescale/mx6sabresd/Kconfig" -source "board/freescale/mx6slevk/Kconfig" -source "board/freescale/mx6sxsabresd/Kconfig" -source "board/freescale/mx6ul_14x14_evk/Kconfig" source "board/freescale/vf610twr/Kconfig" -source "board/gateworks/gw_ventana/Kconfig" source "board/genesi/mx51_efikamx/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hale/tt01/Kconfig" +source "board/hisilicon/hikey/Kconfig" source "board/icpdas/lp8x4x/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" -source "board/kosagi/novena/Kconfig" source "board/logicpd/imx27lite/Kconfig" source "board/logicpd/imx31_litekit/Kconfig" source "board/maxbcm/Kconfig" @@ -978,7 +866,6 @@ source "board/siemens/draco/Kconfig" source "board/siemens/pxm2/Kconfig" source "board/siemens/rut/Kconfig" source "board/silica/pengwyn/Kconfig" -source "board/solidrun/mx6cuboxi/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" @@ -990,7 +877,6 @@ source "board/st/stm32f429-discovery/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" source "board/syteco/zmx25/Kconfig" -source "board/tbs/tbs2910/Kconfig" source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/birdland/bav335x/Kconfig" @@ -1000,12 +886,10 @@ source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" source "board/trizepsiv/Kconfig" +source "board/technologic/ts4800/Kconfig" source "board/ttcontrol/vision2/Kconfig" -source "board/udoo/Kconfig" source "board/vpac270/Kconfig" source "board/vscom/baltos/Kconfig" -source "board/wandboard/Kconfig" -source "board/warp/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 060d46b82c..fe966702fa 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -175,7 +175,7 @@ u32 get_cpu_rev(void) for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) if (srev == mx31_cpu_type[i].srev) - return mx31_cpu_type[i].v; + return mx31_cpu_type[i].v | (MXC_CPU_MX31 << 12); return srev | 0x8000; } diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index 5ee9f07d87..b713c84519 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -12,6 +12,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> +#include <asm/imx-common/sys_proto.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif @@ -159,6 +160,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk) } +u32 get_cpu_rev(void) +{ + return MXC_CPU_MX27 << 12; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 6c59494558..71c2c0e7b4 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -74,12 +74,10 @@ u-boot.csf: u-boot.ivt u-boot.bin board/$(VENDOR)/$(BOARD)/sign/u-boot.csf %.sig: %.csf $(call if_changed,mkcst_mxs) -quiet_cmd_mkimage_mxs = MKIMAGE $@ -cmd_mkimage_mxs = $(objtree)/tools/mkimage -n $< -T mxsimage $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) - +MKIMAGEFLAGS_u-boot.sb = -n $< -T mxsimage u-boot.sb: $(src)/$(MKIMAGE_TARGET-y) u-boot.bin spl/u-boot-spl.bin FORCE - $(call if_changed,mkimage_mxs) + $(call if_changed,mkimage) +MKIMAGEFLAGS_u-boot-signed.sb = -n $< -T mxsimage u-boot-signed.sb: $(src)/mxsimage-signed.cfg u-boot.ivt u-boot.sig spl/u-boot-spl.ivt spl/u-boot-spl.sig FORCE - $(call if_changed,mkimage_mxs) + $(call if_changed,mkimage) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index b1d8721213..a6af0fcb36 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -132,23 +132,7 @@ int arch_cpu_init(void) return 0; } -#if defined(CONFIG_DISPLAY_CPUINFO) -static const char *get_cpu_type(void) -{ - struct mxs_digctl_regs *digctl_regs = - (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; - - switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) { - case HW_DIGCTL_CHIPID_MX23: - return "23"; - case HW_DIGCTL_CHIPID_MX28: - return "28"; - default: - return "??"; - } -} - -static const char *get_cpu_rev(void) +u32 get_cpu_rev(void) { struct mxs_digctl_regs *digctl_regs = (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; @@ -158,38 +142,50 @@ static const char *get_cpu_rev(void) case HW_DIGCTL_CHIPID_MX23: switch (rev) { case 0x0: - return "1.0"; case 0x1: - return "1.1"; case 0x2: - return "1.2"; case 0x3: - return "1.3"; case 0x4: - return "1.4"; + return (MXC_CPU_MX23 << 12) | (rev + 0x10); default: - return "??"; + return 0; } case HW_DIGCTL_CHIPID_MX28: switch (rev) { case 0x1: - return "1.2"; + return (MXC_CPU_MX28 << 12) | 0x12; default: - return "??"; + return 0; } default: + return 0; + } +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_MX23: + return "23"; /* Quad-Plus version of the mx6 */ + case MXC_CPU_MX28: + return "28"; /* Dual-Plus version of the mx6 */ + default: return "??"; } } int print_cpuinfo(void) { + u32 cpurev; struct mxs_spl_data *data = (struct mxs_spl_data *) ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf); - printf("CPU: Freescale i.MX%s rev%s at %d MHz\n", - get_cpu_type(), - get_cpu_rev(), + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode); return 0; diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index dce7ffc022..8b0120fea5 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -33,25 +33,159 @@ choice prompt "MX6 board select" optional +config TARGET_ARISTAINETOS + bool "aristainetos" + select CPU_V7 + +config TARGET_ARISTAINETOS2 + bool "aristainetos2" + select CPU_V7 + +config TARGET_ARISTAINETOS2B + bool "Support aristainetos2-revB" + select CPU_V7 + +config TARGET_CGTQMX6EVAL + bool "cgtqmx6eval" + select CPU_V7 + config TARGET_CM_FX6 - bool "Support CM-FX6" + bool "CM-FX6" select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO +config TARGET_EMBESTMX6BOARDS + bool "embestmx6boards" + select CPU_V7 + +config TARGET_GW_VENTANA + bool "gw_ventana" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_KOSAGI_NOVENA + bool "Kosagi Novena" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_MX6CUBOXI + bool "Solid-run mx6 boards" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_MX6QARM2 + bool "mx6qarm2" + select CPU_V7 + +config TARGET_MX6QSABREAUTO + bool "mx6qsabreauto" + select CPU_V7 + select DM + select DM_THERMAL + +config TARGET_MX6SABRESD + bool "mx6sabresd" + select CPU_V7 + select SUPPORT_SPL + select DM + select DM_THERMAL + +config TARGET_MX6SLEVK + bool "mx6slevk" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_MX6SXSABRESD + bool "mx6sxsabresd" + select CPU_V7 + select SUPPORT_SPL + select DM + select DM_THERMAL + +config TARGET_MX6UL_14X14_EVK + bool "mx6ul_14x14_evk" + select MX6UL + select CPU_V7 + select DM + select DM_THERMAL + select SUPPORT_SPL + +config TARGET_NITROGEN6X + bool "nitrogen6x" + select CPU_V7 + +config TARGET_OT1200 + bool "Bachmann OT1200" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PLATINUM_PICON + bool "platinum-picon" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_PLATINUM_TITANIUM + bool "platinum-titanium" + select CPU_V7 + select SUPPORT_SPL + config TARGET_SECOMX6 - bool "Support secomx6 boards" + bool "secomx6 boards" + +config TARGET_TBS2910 + bool "TBS2910 Matrix ARM mini PC" + select CPU_V7 + +config TARGET_TITANIUM + bool "titanium" + select CPU_V7 config TARGET_TQMA6 bool "TQ Systems TQMa6 board" +config TARGET_UDOO + bool "udoo" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_WANDBOARD + bool "wandboard" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_WARP + bool "WaRP" + select CPU_V7 + endchoice config SYS_SOC default "mx6" +source "board/aristainetos/Kconfig" +source "board/bachmann/ot1200/Kconfig" +source "board/barco/platinum/Kconfig" +source "board/barco/titanium/Kconfig" +source "board/boundary/nitrogen6x/Kconfig" +source "board/compulab/cm_fx6/Kconfig" +source "board/congatec/cgtqmx6eval/Kconfig" +source "board/embest/mx6boards/Kconfig" +source "board/freescale/mx6qarm2/Kconfig" +source "board/freescale/mx6qsabreauto/Kconfig" +source "board/freescale/mx6sabresd/Kconfig" +source "board/freescale/mx6slevk/Kconfig" +source "board/freescale/mx6sxsabresd/Kconfig" +source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/gateworks/gw_ventana/Kconfig" +source "board/kosagi/novena/Kconfig" source "board/seco/Kconfig" +source "board/solidrun/mx6cuboxi/Kconfig" +source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" +source "board/udoo/Kconfig" +source "board/wandboard/Kconfig" +source "board/warp/Kconfig" endif diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 9cf4eece13..ba6cc75a7b 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num) #endif #ifdef CONFIG_FEC_MXC -int enable_fec_anatop_clock(enum enet_freq freq) +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) { u32 reg = 0; s32 timeout = 100000; @@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq) if (freq < ENET_25MHZ || freq > ENET_125MHZ) return -EINVAL; - reg = readl(&anatop->pll_enet); - reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; - reg |= freq; + if (fec_id == 0) { + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); + } else if (fec_id == 1) { + /* Only i.MX6SX/UL support ENET2 */ + if (!(is_cpu_type(MXC_CPU_MX6SX) || + is_cpu_type(MXC_CPU_MX6UL))) + return -EINVAL; + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); + } else { + return -EINVAL; + } if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq) } /* Enable FEC clock */ - reg |= BM_ANADIG_PLL_ENET_ENABLE; + if (fec_id == 0) + reg |= BM_ANADIG_PLL_ENET_ENABLE; + else + reg |= BM_ANADIG_PLL_ENET2_ENABLE; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet); diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index b808627a42..cf5587be54 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <linux/types.h> +#include <asm/arch/clock.h> #include <asm/arch/mx6-ddr.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -115,6 +116,61 @@ void mx6ul_dram_iocfg(unsigned width, } #endif +#if defined(CONFIG_MX6SL) +void mx6sl_dram_iocfg(unsigned width, + const struct mx6sl_iomux_ddr_regs *ddr, + const struct mx6sl_iomux_grp_regs *grp) +{ + struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux; + struct mx6sl_iomux_grp_regs *mx6_grp_iomux; + + mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE; + mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE; + + /* DDR IO TYPE */ + mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; + mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; + + /* CLOCK */ + mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; + + /* ADDRESS */ + mx6_ddr_iomux->dram_cas = ddr->dram_cas; + mx6_ddr_iomux->dram_ras = ddr->dram_ras; + mx6_grp_iomux->grp_addds = grp->grp_addds; + + /* Control */ + mx6_ddr_iomux->dram_reset = ddr->dram_reset; + mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; + mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; + + /* Data Strobes */ + mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; + mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; + mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; + if (width >= 32) { + mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; + mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; + } + + /* Data */ + mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; + mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; + mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; + if (width >= 32) { + mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; + mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; + } + + mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; + mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; + if (width >= 32) { + mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; + mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; + } +} +#endif + #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) /* Configure MX6DQ mmdc iomux */ void mx6dq_dram_iocfg(unsigned width, @@ -275,24 +331,314 @@ void mx6sdl_dram_iocfg(unsigned width, * Configure mx6 mmdc registers based on: * - board-specific memory configuration * - board-specific calibration data - * - ddr3 chip details + * - ddr3/lpddr2 chip details * * The various calculations here are derived from the Freescale - * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC - * configuration registers based on memory system and memory chip parameters. + * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate + * MMDC configuration registers based on memory system and memory chip + * parameters. + * + * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC + * configuration registers based on memory system and memory chip + * parameters. * * The defaults here are those which were specified in the spreadsheet. * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM - * section titled MMDC initialization + * and/or IMX6SLRM section titled MMDC initialization. */ #define MR(val, ba, cmd, cs1) \ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) #define MMDC1(entry, value) do { \ - if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \ + if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \ + !is_cpu_type(MXC_CPU_MX6SL)) \ mmdc1->entry = value; \ } while (0) -void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, +/* + * According JESD209-2B-LPDDR2: Table 103 + * WL: write latency + */ +static int lpddr2_wl(uint32_t mem_speed) +{ + switch (mem_speed) { + case 1066: + case 933: + return 4; + case 800: + return 3; + case 677: + case 533: + return 2; + case 400: + case 333: + return 1; + default: + puts("invalid memory speed\n"); + hang(); + } + + return 0; +} + +/* + * According JESD209-2B-LPDDR2: Table 103 + * RL: read latency + */ +static int lpddr2_rl(uint32_t mem_speed) +{ + switch (mem_speed) { + case 1066: + return 8; + case 933: + return 7; + case 800: + return 6; + case 677: + return 5; + case 533: + return 4; + case 400: + case 333: + return 3; + default: + puts("invalid memory speed\n"); + hang(); + } + + return 0; +} + +void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo, + const struct mx6_mmdc_calibration *calib, + const struct mx6_lpddr2_cfg *lpddr2_cfg) +{ + volatile struct mmdc_p_regs *mmdc0; + u32 val; + u8 tcke, tcksrx, tcksre, trrd; + u8 twl, txp, tfaw, tcl; + u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; + u16 trcd_lp, trppb_lp, trpab_lp, trc_lp; + u16 cs0_end; + u8 coladdr; + int clkper; /* clock period in picoseconds */ + int clock; /* clock freq in mHz */ + int cs; + + /* only support 16/32 bits */ + if (sysinfo->dsize > 1) + hang(); + + mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; + + clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U; + clkper = (1000 * 1000) / clock; /* pico seconds */ + + twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1; + + /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */ + switch (lpddr2_cfg->density) { + case 1: + case 2: + case 4: + trfc = DIV_ROUND_UP(130000, clkper) - 1; + txsr = DIV_ROUND_UP(140000, clkper) - 1; + break; + case 8: + trfc = DIV_ROUND_UP(210000, clkper) - 1; + txsr = DIV_ROUND_UP(220000, clkper) - 1; + break; + default: + /* + * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently. + */ + hang(); + break; + } + /* + * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode, + * set them to 0. */ + txp = DIV_ROUND_UP(7500, clkper) - 1; + tcke = 3; + if (lpddr2_cfg->mem_speed == 333) + tfaw = DIV_ROUND_UP(60000, clkper) - 1; + else + tfaw = DIV_ROUND_UP(50000, clkper) - 1; + trrd = DIV_ROUND_UP(10000, clkper) - 1; + + /* tckesr for LPDDR2 */ + tcksre = DIV_ROUND_UP(15000, clkper); + tcksrx = tcksre; + twr = DIV_ROUND_UP(15000, clkper) - 1; + /* + * tMRR: 2, tMRW: 5 + * tMRD should be set to max(tMRR, tMRW) + */ + tmrd = 5; + tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1; + /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */ + trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1; + trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp, + clkper / 10) - 1; + trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1; + trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1; + /* To LPDDR2, CL in MDCFG0 refers to RL */ + tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3; + twtr = DIV_ROUND_UP(7500, clkper) - 1; + trtp = DIV_ROUND_UP(7500, clkper) - 1; + + cs0_end = 4 * sysinfo->cs_density - 1; + + debug("density:%d Gb (%d Gb per chip)\n", + sysinfo->cs_density, lpddr2_cfg->density); + debug("clock: %dMHz (%d ps)\n", clock, clkper); + debug("memspd:%d\n", lpddr2_cfg->mem_speed); + debug("trcd_lp=%d\n", trcd_lp); + debug("trppb_lp=%d\n", trppb_lp); + debug("trpab_lp=%d\n", trpab_lp); + debug("trc_lp=%d\n", trc_lp); + debug("tcke=%d\n", tcke); + debug("tcksrx=%d\n", tcksrx); + debug("tcksre=%d\n", tcksre); + debug("trfc=%d\n", trfc); + debug("txsr=%d\n", txsr); + debug("txp=%d\n", txp); + debug("tfaw=%d\n", tfaw); + debug("tcl=%d\n", tcl); + debug("tras=%d\n", tras); + debug("twr=%d\n", twr); + debug("tmrd=%d\n", tmrd); + debug("twl=%d\n", twl); + debug("trtp=%d\n", trtp); + debug("twtr=%d\n", twtr); + debug("trrd=%d\n", trrd); + debug("cs0_end=%d\n", cs0_end); + debug("ncs=%d\n", sysinfo->ncs); + + /* + * board-specific configuration: + * These values are determined empirically and vary per board layout + */ + mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; + mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; + mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; + mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; + mmdc0->mprddlctl = calib->p0_mprddlctl; + mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; + mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl; + + /* Read data DQ Byte0-3 delay */ + mmdc0->mprddqby0dl = 0x33333333; + mmdc0->mprddqby1dl = 0x33333333; + if (sysinfo->dsize > 0) { + mmdc0->mprddqby2dl = 0x33333333; + mmdc0->mprddqby3dl = 0x33333333; + } + + /* Write data DQ Byte0-3 delay */ + mmdc0->mpwrdqby0dl = 0xf3333333; + mmdc0->mpwrdqby1dl = 0xf3333333; + if (sysinfo->dsize > 0) { + mmdc0->mpwrdqby2dl = 0xf3333333; + mmdc0->mpwrdqby3dl = 0xf3333333; + } + + /* + * In LPDDR2 mode this register should be cleared, + * so no termination will be activated. + */ + mmdc0->mpodtctrl = 0; + + /* complete calibration */ + val = (1 << 11); /* Force measurement on delay-lines */ + mmdc0->mpmur0 = val; + + /* Step 1: configuration request */ + mmdc0->mdscr = (u32)(1 << 15); /* config request */ + + /* Step 2: Timing configuration */ + mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) | + (tfaw << 4) | tcl; + mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; + mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd; + mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) | + (trppb_lp << 4) | trpab_lp; + mmdc0->mdotc = 0; + + mmdc0->mdasp = cs0_end; /* CS addressing */ + + /* Step 3: Configure DDR type */ + mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) | + (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) | + (sysinfo->ralat << 6) | (1 << 3); + + /* Step 4: Configure delay while leaving reset */ + mmdc0->mdor = (sysinfo->sde_to_rst << 8) | + (sysinfo->rst_to_cke << 0); + + /* Step 5: Configure DDR physical parameters (density and burst len) */ + coladdr = lpddr2_cfg->coladdr; + if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ + coladdr += 4; + else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ + coladdr += 1; + mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */ + (coladdr - 9) << 20 | /* COL */ + (0 << 19) | /* Burst Length = 4 for LPDDR2 */ + (sysinfo->dsize << 16); /* DDR data bus size */ + + /* Step 6: Perform ZQ calibration */ + val = 0xa1390003; /* one-time HW ZQ calib */ + mmdc0->mpzqhwctrl = val; + + /* Step 7: Enable MMDC with desired chip select */ + mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ + ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ + + /* Step 8: Write Mode Registers to Init LPDDR2 devices */ + for (cs = 0; cs < sysinfo->ncs; cs++) { + /* MR63: reset */ + mmdc0->mdscr = MR(63, 0, 3, cs); + /* MR10: calibration, + * 0xff is calibration command after intilization. + */ + val = 0xA | (0xff << 8); + mmdc0->mdscr = MR(val, 0, 3, cs); + /* MR1 */ + val = 0x1 | (0x82 << 8); + mmdc0->mdscr = MR(val, 0, 3, cs); + /* MR2 */ + val = 0x2 | (0x04 << 8); + mmdc0->mdscr = MR(val, 0, 3, cs); + /* MR3 */ + val = 0x3 | (0x02 << 8); + mmdc0->mdscr = MR(val, 0, 3, cs); + } + + /* Step 10: Power down control and self-refresh */ + mmdc0->mdpdc = (tcke & 0x7) << 16 | + 5 << 12 | /* PWDT_1: 256 cycles */ + 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 6 | /* BOTH_CS_PD */ + (tcksrx & 0x7) << 3 | + (tcksre & 0x7); + mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ + + /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ + val = 0xa1310003; + mmdc0->mpzqhwctrl = val; + + /* Step 12: Configure and activate periodic refresh */ + mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */ + (3 << 11); /* REFR: Refresh Rate - 4 refreshes */ + + /* Step 13: Deassert config request - init complete */ + mmdc0->mdscr = 0x00000000; + + /* wait for auto-ZQ calibration to complete */ + mdelay(1); +} + +void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, const struct mx6_mmdc_calibration *calib, const struct mx6_ddr3_cfg *ddr3_cfg) { @@ -312,7 +658,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, u16 mem_speed = ddr3_cfg->mem_speed; mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; - if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) + if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && + !is_cpu_type(MXC_CPU_MX6SL)) mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; /* Limit mem_speed for MX6D/MX6Q */ @@ -355,8 +702,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, txs = DIV_ROUND_UP(170000, clkper) - 1; break; case 4: /* 4Gb per chip */ - trfc = DIV_ROUND_UP(260000, clkper) - 1; - txs = DIV_ROUND_UP(270000, clkper) - 1; + trfc = DIV_ROUND_UP(300000, clkper) - 1; + txs = DIV_ROUND_UP(310000, clkper) - 1; break; case 8: /* 8Gb per chip */ trfc = DIV_ROUND_UP(350000, clkper) - 1; @@ -598,3 +945,17 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* wait for auto-ZQ calibration to complete */ mdelay(1); } + +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, + const struct mx6_mmdc_calibration *calib, + const void *ddr_cfg) +{ + if (sysinfo->ddr_type == DDR_TYPE_DDR3) { + mx6_ddr3_cfg(sysinfo, calib, ddr_cfg); + } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) { + mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg); + } else { + puts("Unsupported ddr type\n"); + hang(); + } +} diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index f4fb6cb486..cda38e1387 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -92,6 +92,9 @@ config TARGET_MCX config TARGET_OMAP3_LOGIC bool "OMAP3 Logic" + select DM + select DM_SERIAL + select DM_GPIO config TARGET_OMAP3_MVBLX bool "OMAP3 MVBLX" diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 05c401dc73..08b9ef42a1 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -9,6 +9,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> +#include <asm/imx-common/sys_proto.h> #include <netdev.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> @@ -266,6 +267,11 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif +u32 get_cpu_rev(void) +{ + return MXC_CPU_VF610 << 12; +} + #if defined(CONFIG_DISPLAY_CPUINFO) static char *get_reset_cause(void) { diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 835f6a6525..6bde1cf6a0 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,13 +12,22 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF -void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type) +inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, + u64 memory_type, u64 share) { u64 value; value = section | PMD_TYPE_SECT | PMD_SECT_AF; value |= PMD_ATTRINDX(memory_type); + value |= share; + page_table[index] = value; +} + +inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) +{ + u64 value; + + value = (u64)table_addr | PMD_TYPE_TABLE; page_table[index] = value; } @@ -32,7 +41,7 @@ static void mmu_setup(void) /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE); } /* Setup an identity-mapping for all RAM space */ @@ -42,7 +51,7 @@ static void mmu_setup(void) for (j = start >> SECTION_SHIFT; j < end >> SECTION_SHIFT; j++) { set_pgtable_section(page_table, j, j << SECTION_SHIFT, - MT_NORMAL); + MT_NORMAL, PMD_SECT_NON_SHARE); } } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 3c15479315..08da7e4d1d 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -171,3 +171,74 @@ nand write <u-boot image in memory> 80000 <size of u-boot image> Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image to match board NAND device with 4KB/page, block size 512KB. + +MMU Translation Tables +====================== + +(1) Early MMU Tables: + + Level 0 Level 1 Level 2 +------------------ ------------------ ------------------ +| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | +------------------ ------------------ ------------------ +| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | +------------------ | ------------------ ------------------ +| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | +------------------ | ------------------ ------------------ + | | 0x00_c000_0000 | | 0x00_0060_0000 | + | ------------------ ------------------ + | | 0x01_0000_0000 | | 0x00_0080_0000 | + | ------------------ ------------------ + | ... ... + | ------------------ + | | 0x05_8000_0000 | --| + | ------------------ | + | | 0x05_c000_0000 | | + | ------------------ | + | ... | + | ------------------ | ------------------ + |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 | + ------------------ ------------------ + | 0x80_4000_0000 | | 0x00_3020_0000 | + ------------------ ------------------ + | 0x80_8000_0000 | | 0x00_3040_0000 | + ------------------ ------------------ + | 0x80_c000_0000 | | 0x00_3060_0000 | + ------------------ ------------------ + | 0x81_0000_0000 | | 0x00_3080_0000 | + ------------------ ------------------ + ... ... + +(2) Final MMU Tables: + + Level 0 Level 1 Level 2 +------------------ ------------------ ------------------ +| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | +------------------ ------------------ ------------------ +| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | +------------------ | ------------------ ------------------ +| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | +------------------ | ------------------ ------------------ + | | 0x00_c000_0000 | | 0x00_0060_0000 | + | ------------------ ------------------ + | | 0x01_0000_0000 | | 0x00_0080_0000 | + | ------------------ ------------------ + | ... ... + | ------------------ + | | 0x08_0000_0000 | --| + | ------------------ | + | | 0x08_4000_0000 | | + | ------------------ | + | ... | + | ------------------ | ------------------ + |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 | + ------------------ ------------------ + | 0x80_4000_0000 | | 0x08_0020_0000 | + ------------------ ------------------ + | 0x80_8000_0000 | | 0x08_0040_0000 | + ------------------ ------------------ + | 0x80_c000_0000 | | 0x08_0060_0000 | + ------------------ ------------------ + | 0x81_0000_0000 | | 0x08_0080_0000 | + ------------------ ------------------ + ... ... diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index d02c0beef9..eb1213e9f0 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/errno.h> #include <asm/system.h> #include <asm/armv8/mmu.h> #include <asm/io.h> @@ -53,27 +54,16 @@ void cpu_name(char *name) } #ifndef CONFIG_SYS_DCACHE_OFF -/* - * To start MMU before DDR is available, we create MMU table in SRAM. - * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three - * levels of translation tables here to cover 40-bit address space. - * We use 4KB granule size, with 40 bits physical address, T0SZ=24 - * Level 0 IA[39], table address @0 - * Level 1 IA[31:30], table address @0x1000, 0x2000 - * Level 2 IA[29:21], table address @0x3000, 0x4000 - * Address above 0x5000 is free for other purpose. - */ -#define SECTION_SHIFT_L0 39UL -#define SECTION_SHIFT_L1 30UL -#define SECTION_SHIFT_L2 21UL -#define BLOCK_SIZE_L0 0x8000000000UL -#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) -#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) -#define CONFIG_SYS_IFC_BASE 0x30000000 -#define CONFIG_SYS_IFC_SIZE 0x10000000 -#define CONFIG_SYS_IFC_BASE2 0x500000000 -#define CONFIG_SYS_IFC_SIZE2 0x100000000 +#define SECTION_SHIFT_L0 39UL +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000 +#define BLOCK_SIZE_L1 0x40000000 +#define BLOCK_SIZE_L2 0x200000 + +#define NUM_OF_ENTRY 512 + #define TCR_EL2_PS_40BIT (2 << 16) #define LSCH3_VA_BITS (40) #define LSCH3_TCR (TCR_TG0_4K | \ @@ -89,95 +79,265 @@ void cpu_name(char *name) TCR_IRGN_WBWA | \ TCR_T0SZ(LSCH3_VA_BITS)) +#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 +#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 +#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 +#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 +#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 +#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 +#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 +#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 +#define CONFIG_SYS_FSL_NI_BASE 0x810000000 +#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 +#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 +#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 + +struct sys_mmu_table { + u64 virt_addr; + u64 phys_addr; + u64 size; + u64 memory_type; + u64 share; +}; + +static const struct sys_mmu_table lsch3_early_mmu_table[] = { + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +}; + +static const struct sys_mmu_table lsch3_final_mmu_table[] = { + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#ifdef CONFIG_LS2085A + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +}; + +struct table_info { + u64 *ptr; + u64 table_base; + u64 entry_size; +}; + /* - * Final MMU - * Let's start from the same layout as early MMU and modify as needed. - * IFC regions will be cache-inhibit. + * Set the block entries according to the information of the table. */ -#define FINAL_QBMAN_CACHED_MEM 0x818000000UL -#define FINAL_QBMAN_CACHED_SIZE 0x4000000 +static int set_block_entry(const struct sys_mmu_table *list, + struct table_info *table) +{ + u64 block_size = 0, block_shift = 0; + u64 block_addr, index; + int j; + + if (table->entry_size == BLOCK_SIZE_L1) { + block_size = BLOCK_SIZE_L1; + block_shift = SECTION_SHIFT_L1; + } else if (table->entry_size == BLOCK_SIZE_L2) { + block_size = BLOCK_SIZE_L2; + block_shift = SECTION_SHIFT_L2; + } else { + return -EINVAL; + } + block_addr = list->phys_addr; + index = (list->virt_addr - table->table_base) >> block_shift; + + for (j = 0; j < (list->size >> block_shift); j++) { + set_pgtable_section(table->ptr, + index, + block_addr, + list->memory_type, + list->share); + block_addr += block_size; + index++; + } -static inline void early_mmu_setup(void) + return 0; +} + +/* + * Find the corresponding table entry for the list. + */ +static int find_table(const struct sys_mmu_table *list, + struct table_info *table, u64 *level0_table) { - int el; - u64 i; - u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1; - u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; - u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); - u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); - u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); - u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); + u64 index = 0, level = 0; + u64 *level_table = level0_table; + u64 temp_base = 0, block_size = 0, block_shift = 0; + + while (level < 3) { + if (level == 0) { + block_size = BLOCK_SIZE_L0; + block_shift = SECTION_SHIFT_L0; + } else if (level == 1) { + block_size = BLOCK_SIZE_L1; + block_shift = SECTION_SHIFT_L1; + } else if (level == 2) { + block_size = BLOCK_SIZE_L2; + block_shift = SECTION_SHIFT_L2; + } - level0_table[0] = - (u64)level1_table_0 | PMD_TYPE_TABLE; - level0_table[1] = - (u64)level1_table_1 | PMD_TYPE_TABLE; + index = 0; + while (list->virt_addr >= temp_base) { + index++; + temp_base += block_size; + } - /* - * set level 1 table 0 to cache_inhibit, covering 0 to 512GB - * set level 1 table 1 to cache enabled, covering 512GB to 1TB - * set level 2 table to cache-inhibit, covering 0 to 1GB - */ - section_l1t0 = 0; - section_l1t1 = BLOCK_SIZE_L0; - section_l2t0 = 0; - section_l2t1 = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < 512; i++) { - set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); - set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); - set_pgtable_section(level2_table_0, i, section_l2t0, - MT_DEVICE_NGNRNE); - set_pgtable_section(level2_table_1, i, section_l2t1, - MT_DEVICE_NGNRNE); - section_l1t0 += BLOCK_SIZE_L1; - section_l1t1 += BLOCK_SIZE_L1; - section_l2t0 += BLOCK_SIZE_L2; - section_l2t1 += BLOCK_SIZE_L2; + temp_base -= block_size; + + if ((level_table[index - 1] & PMD_TYPE_MASK) == + PMD_TYPE_TABLE) { + level_table = (u64 *)(level_table[index - 1] & + ~PMD_TYPE_MASK); + level++; + continue; + } else { + if (level == 0) + return -EINVAL; + + if ((list->phys_addr + list->size) > + (temp_base + block_size * NUM_OF_ENTRY)) + return -EINVAL; + + /* + * Check the address and size of the list member is + * aligned with the block size. + */ + if (((list->phys_addr & (block_size - 1)) != 0) || + ((list->size & (block_size - 1)) != 0)) + return -EINVAL; + + table->ptr = level_table; + table->table_base = temp_base - + ((index - 1) << block_shift); + table->entry_size = block_size; + + return 0; + } } + return -EINVAL; +} - level1_table_0[0] = - (u64)level2_table_0 | PMD_TYPE_TABLE; - level1_table_0[1] = - 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_DEVICE_NGNRNE); - level1_table_0[2] = - 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); - level1_table_0[3] = - 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); - - /* Rewerite table to enable cache for OCRAM */ - set_pgtable_section(level2_table_0, - CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, - CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); - -#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY) - /* Rewrite table to enable cache for two entries (4MB) */ - section_l2t1 = CONFIG_SYS_IFC_BASE; - set_pgtable_section(level2_table_0, - section_l2t1 >> SECTION_SHIFT_L2, - section_l2t1, - MT_NORMAL); - section_l2t1 += BLOCK_SIZE_L2; - set_pgtable_section(level2_table_0, - section_l2t1 >> SECTION_SHIFT_L2, - section_l2t1, - MT_NORMAL); -#endif - - /* Create a mapping for 256MB IFC region to final flash location */ - level1_table_0[CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1] = - (u64)level2_table_1 | PMD_TYPE_TABLE; - section_l2t1 = CONFIG_SYS_IFC_BASE; - for (i = 0; i < 0x10000000 >> SECTION_SHIFT_L2; i++) { - set_pgtable_section(level2_table_1, i, - section_l2t1, MT_DEVICE_NGNRNE); - section_l2t1 += BLOCK_SIZE_L2; +/* + * To start MMU before DDR is available, we create MMU table in SRAM. + * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three + * levels of translation tables here to cover 40-bit address space. + * We use 4KB granule size, with 40 bits physical address, T0SZ=24 + * Level 0 IA[39], table address @0 + * Level 1 IA[38:30], table address @0x1000, 0x2000 + * Level 2 IA[29:21], table address @0x3000, 0x4000 + * Address above 0x5000 is free for other purpose. + */ +static inline void early_mmu_setup(void) +{ + unsigned int el, i; + u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; + u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); + u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); + u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); + u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + + /* Invalidate all table entries */ + memset(level0_table, 0, 0x5000); + + /* Fill in the table entries */ + set_pgtable_table(level0_table, 0, level1_table0); + set_pgtable_table(level0_table, 1, level1_table1); + set_pgtable_table(level1_table0, 0, level2_table0); + set_pgtable_table(level1_table0, + CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, + level2_table1); + + /* Find the table and fill in the block entries */ + for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) { + if (find_table(&lsch3_early_mmu_table[i], + &table, level0_table) == 0) { + /* + * If find_table() returns error, it cannot be dealt + * with here. Breakpoint can be added for debugging. + */ + set_block_entry(&lsch3_early_mmu_table[i], &table); + /* + * If set_block_entry() returns error, it cannot be + * dealt with here too. + */ + } } el = current_el(); @@ -186,89 +346,55 @@ static inline void early_mmu_setup(void) } /* - * This final tale looks similar to early table, but different in detail. - * These tables are in regular memory. Cache on IFC is disabled. One sub table - * is added to enable cache for QBMan. + * The final tables look similar to early tables, but different in detail. + * These tables are in DRAM. Sub tables are added to enable cache for + * QBMan and OCRAM. + * + * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. + * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. + * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. + * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. */ static inline void final_mmu_setup(void) { - int el; - u64 i, tbl_base, tbl_limit, section_base; - u64 section_l1t0, section_l1t1, section_l2; + unsigned int el, i; u64 *level0_table = (u64 *)gd->arch.tlb_addr; - u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000); - u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000); - u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000); - u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000); - - - level0_table[0] = - (u64)level1_table_0 | PMD_TYPE_TABLE; - level0_table[1] = - (u64)level1_table_1 | PMD_TYPE_TABLE; - - /* - * set level 1 table 0 to cache_inhibit, covering 0 to 512GB - * set level 1 table 1 to cache enabled, covering 512GB to 1TB - * set level 2 table 0 to cache-inhibit, covering 0 to 1GB - */ - section_l1t0 = 0; - section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE; - section_l2 = 0; - for (i = 0; i < 512; i++) { - set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); - set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); - set_pgtable_section(level2_table_0, i, section_l2, - MT_DEVICE_NGNRNE); - section_l1t0 += BLOCK_SIZE_L1; - section_l1t1 += BLOCK_SIZE_L1; - section_l2 += BLOCK_SIZE_L2; - } - - level1_table_0[0] = - (u64)level2_table_0 | PMD_TYPE_TABLE; - level1_table_0[2] = - 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); - level1_table_0[3] = - 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); - - /* Rewrite table to enable cache */ - set_pgtable_section(level2_table_0, - CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, - CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); + u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); + u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); + u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + + /* Invalidate all table entries */ + memset(level0_table, 0, PGTABLE_SIZE); + + /* Fill in the table entries */ + set_pgtable_table(level0_table, 0, level1_table0); + set_pgtable_table(level0_table, 1, level1_table1); + set_pgtable_table(level1_table0, 0, level2_table0); + set_pgtable_table(level1_table0, + CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, + level2_table1); + + /* Find the table and fill in the block entries */ + for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) { + if (find_table(&lsch3_final_mmu_table[i], + &table, level0_table) == 0) { + if (set_block_entry(&lsch3_final_mmu_table[i], + &table) != 0) { + printf("MMU error: could not set block entry for %p\n", + &lsch3_final_mmu_table[i]); + } - /* - * Fill in other part of tables if cache is needed - * If finer granularity than 1GB is needed, sub table - * should be created. - */ - section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1); - i = section_base >> SECTION_SHIFT_L1; - level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE; - section_l2 = section_base; - for (i = 0; i < 512; i++) { - set_pgtable_section(level2_table_1, i, section_l2, - MT_DEVICE_NGNRNE); - section_l2 += BLOCK_SIZE_L2; - } - tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); - tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) & - (BLOCK_SIZE_L1 - 1); - for (i = tbl_base >> SECTION_SHIFT_L2; - i < tbl_limit >> SECTION_SHIFT_L2; i++) { - section_l2 = section_base + (i << SECTION_SHIFT_L2); - set_pgtable_section(level2_table_1, i, - section_l2, MT_NORMAL); + } else { + printf("MMU error: could not find the table for %p\n", + &lsch3_final_mmu_table[i]); + } } /* flush new MMU table */ flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); + gd->arch.tlb_addr + gd->arch.tlb_size); /* point TTBR to the new table */ el = current_el(); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c index 02ca126ab8..ae0834365e 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c @@ -90,7 +90,38 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, else { serdes_prtcl_map[lane_prtcl] = 1; #ifdef CONFIG_FSL_MC_ENET - wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl); + switch (lane_prtcl) { + case QSGMII_A: + wriop_init_dpmac(sd, 5, (int)lane_prtcl); + wriop_init_dpmac(sd, 6, (int)lane_prtcl); + wriop_init_dpmac(sd, 7, (int)lane_prtcl); + wriop_init_dpmac(sd, 8, (int)lane_prtcl); + break; + case QSGMII_B: + wriop_init_dpmac(sd, 1, (int)lane_prtcl); + wriop_init_dpmac(sd, 2, (int)lane_prtcl); + wriop_init_dpmac(sd, 3, (int)lane_prtcl); + wriop_init_dpmac(sd, 4, (int)lane_prtcl); + break; + case QSGMII_C: + wriop_init_dpmac(sd, 13, (int)lane_prtcl); + wriop_init_dpmac(sd, 14, (int)lane_prtcl); + wriop_init_dpmac(sd, 15, (int)lane_prtcl); + wriop_init_dpmac(sd, 16, (int)lane_prtcl); + break; + case QSGMII_D: + wriop_init_dpmac(sd, 9, (int)lane_prtcl); + wriop_init_dpmac(sd, 10, (int)lane_prtcl); + wriop_init_dpmac(sd, 11, (int)lane_prtcl); + wriop_init_dpmac(sd, 12, (int)lane_prtcl); + break; + default: + if (lane_prtcl >= SGMII1 && + lane_prtcl <= SGMII16) + wriop_init_dpmac(sd, lane + 1, + (int)lane_prtcl); + break; + } #endif } } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 018c61742e..6b19d36f11 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -16,13 +16,71 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ /* Add fully-coherent masters to DVM domain */ - ldr x1, =CCI_MN_BASE - ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST] - str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] -1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] - mvn x0, x3 - tst x0, x3 /* Wait for domain addition to complete */ - b.ne 1b + ldr x0, =CCI_MN_BASE + ldr x1, =CCI_MN_RNF_NODEID_LIST + ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET + bl ccn504_add_masters_to_dvm + + /* Set all RN-I ports to QoS of 15 */ + ldr x0, =CCI_S0_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c index 098745bd74..0b79a501d9 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c @@ -32,9 +32,9 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, - {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, - QSGMII_A} }, - {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, + {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, + QSGMII_B} }, + {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, {} }; static struct serdes_config serdes2_cfg_tbl[] = { diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 7fb23dd027..b4f481fa53 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -41,6 +41,18 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) } #endif +#ifdef CONFIG_IOMUX_LPSR + u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT; + + if (lpsr == IOMUX_CONFIG_LPSR) { + base = (void *)IOMUXC_LPSR_BASE_ADDR; + mux_mode &= ~IOMUX_CONFIG_LPSR; + /* set daisy chain sel_input */ + if (sel_input_ofs) + sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; + } +#endif + if (mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); @@ -55,6 +67,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); #endif + +#ifdef CONFIG_IOMUX_LPSR + if (lpsr == IOMUX_CONFIG_LPSR) + base = (void *)IOMUXC_BASE_ADDR; +#endif + } /* configures a list of pads within declared with IOMUX_PADS macro */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index a4576ddce1..96d6c98cb8 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -19,6 +19,7 @@ #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) @@ -136,6 +137,17 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) +#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) +#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) +#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) +#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) +#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) + +#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) +#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) +#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) + /* Device Configuration */ #define DCFG_BASE 0x01e00000 #define DCFG_PORSR1 0x000 diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index c7f9fffacb..1c8d24e576 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -4,6 +4,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#define MXC_CPU_MX23 0x23 +#define MXC_CPU_MX25 0x25 +#define MXC_CPU_MX27 0x27 +#define MXC_CPU_MX28 0x28 +#define MXC_CPU_MX31 0x31 +#define MXC_CPU_MX35 0x35 #define MXC_CPU_MX51 0x51 #define MXC_CPU_MX53 0x53 #define MXC_CPU_MX6SL 0x60 @@ -15,6 +21,7 @@ #define MXC_CPU_MX6D 0x67 #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 +#define MXC_CPU_VF610 0xF6 /* dummy ID */ #define CS0_128 0 #define CS0_64M_CS1_64M 1 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index c55cdef4c7..bcaf7bf2e4 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -103,20 +103,6 @@ #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE -#define CONFIG_KEY_REVOCATION -#define CONFIG_FSL_ISBC_KEY_EXT - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_DM -#define CONFIG_RSA -#define CONFIG_RSA_FREESCALE_EXP -#ifndef CONFIG_FSL_CAAM -#define CONFIG_FSL_CAAM -#endif -#endif #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index d34044a5f7..60aa0d3b6f 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -143,7 +143,7 @@ struct ccsr_gur { u32 sdhcpcr; }; -#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f +#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h new file mode 100644 index 0000000000..3e9e9eab1c --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h @@ -0,0 +1,52 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_DEVDIS_H_ +#define __FSL_LS102XA_DEVDIS_H_ + +#include <fsl_devdis.h> + +const struct devdis_table devdis_tbl[] = { + { "pbl", 0x0, 0x80000000 }, /* PBL */ + { "esdhc", 0x0, 0x20000000 }, /* eSDHC */ + { "qdma", 0x0, 0x800000 }, /* qDMA */ + { "edma", 0x0, 0x400000 }, /* eDMA */ + { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/ + { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */ + { "sata", 0x0, 0x8000 }, /* SATA */ + { "sec", 0x0, 0x200 }, /* SEC */ + { "dcu", 0x0, 0x2 }, /* Display controller Unit */ + { "qe", 0x0, 0x1 }, /* QUICC Engine */ + { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */ + { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */ + { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */ + { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */ + { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */ + { "duart1", 0x3, 0x20000000 }, /* DUART1 */ + { "duart2", 0x3, 0x10000000 }, /* DUART2 */ + { "qspi", 0x3, 0x8000000 }, /* QSPI */ + { "ddr", 0x4, 0x80000000 }, /* DDR */ + { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */ + { "ifc", 0x4, 0x800000 }, /* IFC */ + { "gpio", 0x4, 0x400000 }, /* GPIO */ + { "dbg", 0x4, 0x200000 }, /* DBG */ + { "can1", 0x4, 0x80000 }, /* FlexCAN1 */ + { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */ + { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */ + { "secmon", 0x4, 0x4000 }, /* Security Monitor */ + { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */ + { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */ + { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */ + { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */ + { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */ + { "asrc", 0x4, 0x20 }, /* ASRC */ + { "spdif", 0x4, 0x10 }, /* SPDIF */ + { "i2c1", 0x4, 0x4 }, /* I2C1 */ + { "lpuart1", 0x4, 0x2 }, /* LPUART1 */ + { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */ +}; + +#endif diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h index b0dfcba586..674b25cff4 100644 --- a/arch/arm/include/asm/arch-mx31/sys_proto.h +++ b/arch/arm/include/asm/arch-mx31/sys_proto.h @@ -5,8 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ +#ifndef _MX31_SYS_PROTO_H_ +#define _MX31_SYS_PROTO_H_ + +#include <asm/imx-common/sys_proto.h> struct mxc_weimcs { u32 upper; @@ -16,5 +18,4 @@ struct mxc_weimcs { void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs); int mxc_mmc_init(bd_t *bis); -u32 get_cpu_rev(void); #endif diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h index 35c03520aa..0979fda487 100644 --- a/arch/arm/include/asm/arch-mx35/sys_proto.h +++ b/arch/arm/include/asm/arch-mx35/sys_proto.h @@ -5,12 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ +#ifndef _MX35_SYS_PROTO_H_ +#define _MX35_SYS_PROTO_H_ -u32 get_cpu_rev(void); -void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, - u32 row, u32 col, u32 dsize, u32 refresh); -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +#include <asm/imx-common/sys_proto.h> + +void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row, + u32 col, u32 dsize, u32 refresh); #endif diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h index 70aaa37f9d..b7b169505f 100644 --- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h +++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h @@ -184,8 +184,19 @@ enum { MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL), MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL), MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DI2_PIN2__FEC_MDC = IOMUX_PAD(0x74C, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5), MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL), MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP2_DAT6__FEC_TDAT1 = IOMUX_PAD(0x774, 0x36C, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT7__FEC_TDAT2 = IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT8__FEC_TDAT3 = IOMUX_PAD(0x77C, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT9__FEC_TX_EN = IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_DISP2_DAT10__FEC_COL = IOMUX_PAD(0x784, 0x37C, 2, 0x94c, 0x1, MX51_PAD_CTRL_2), + MX51_PAD_DISP2_DAT11__FEC_RXCLK = IOMUX_PAD(0x788, 0x380, 2, 0x968, 0x1, MX51_PAD_CTRL_2), + MX51_PAD_DISP2_DAT12__FEC_RX_DV = IOMUX_PAD(0x78C, 0x384, 2, 0x96c, 0x1, MX51_PAD_CTRL_4), + MX51_PAD_DISP2_DAT13__FEC_TX_CLK = IOMUX_PAD(0x790, 0x388, 2, 0x974, 0x1, MX51_PAD_CTRL_4), + MX51_PAD_DISP2_DAT14__FEC_RDAT0 = IOMUX_PAD(0x794, 0x38C, 2, 0x958, 0x1, MX51_PAD_CTRL_4), + MX51_PAD_DISP2_DAT15__FEC_TDAT0 = IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_PAD_CTRL_5), MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index b06c77f65c..16c9b766d9 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -5,24 +5,4 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include "../arch-imx/cpu.h" - -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) -u32 get_cpu_rev(void); -unsigned imx_ddr_size(void); -void sdelay(unsigned long); -void set_chipselect_size(int const); - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ - -int fecmxc_initialize(bd_t *bis); -u32 get_ahb_clk(void); -u32 get_periph_clk(void); - -#endif +#include <asm/imx-common/sys_proto.h> diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 7b3bbb8185..2b220d6f8f 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -64,7 +64,7 @@ int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); -int enable_fec_anatop_clock(enum enet_freq freq); +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index fe75da4c98..10306cd776 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1052,6 +1052,12 @@ struct mxc_ccm_reg { #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) +/* ENET2 for i.MX6SX/UL */ +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) + #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4d84a9b753..a685ed2c3b 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -630,9 +630,10 @@ struct ocotp_regs { u32 version; u32 rsvd7[0xdb]; + /* fuse banks */ struct fuse_bank { u32 fuse_regs[0x20]; - } bank[16]; + } bank[0]; }; struct fuse_bank0_regs { diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 7bfbdc3cf9..68d9bda2c5 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -19,13 +19,22 @@ #ifdef CONFIG_MX6UL #include "mx6ul-ddr.h" #else +#ifdef CONFIG_MX6SL +#include "mx6sl-ddr.h" +#else #error "Please select cpu" +#endif /* CONFIG_MX6SL */ #endif /* CONFIG_MX6UL */ #endif /* CONFIG_MX6SX */ #endif /* CONFIG_MX6DL or CONFIG_MX6S */ #endif /* CONFIG_MX6Q */ #else +enum { + DDR_TYPE_DDR3, + DDR_TYPE_LPDDR2, +}; + /* MMDC P0/P1 Registers */ struct mmdc_p_regs { u32 mdctl; @@ -40,30 +49,120 @@ struct mmdc_p_regs { u32 res1[2]; u32 mdrwd; u32 mdor; - u32 res2[3]; + u32 mdmrr; + u32 mdcfg3lp; + u32 mdmr4; u32 mdasp; - u32 res3[240]; + u32 res2[239]; + u32 maarcr; u32 mapsr; - u32 res4[254]; + u32 maexidr0; + u32 maexidr1; + u32 madpcr0; + u32 madpcr1; + u32 madpsr0; + u32 madpsr1; + u32 madpsr2; + u32 madpsr3; + u32 madpsr4; + u32 madpsr5; + u32 masbs0; + u32 masbs1; + u32 res3[2]; + u32 magenp; + u32 res4[239]; u32 mpzqhwctrl; - u32 res5[2]; + u32 mpzqswctrl; + u32 mpwlgcr; u32 mpwldectrl0; u32 mpwldectrl1; - u32 res6; + u32 mpwldlst; u32 mpodtctrl; u32 mprddqby0dl; u32 mprddqby1dl; u32 mprddqby2dl; u32 mprddqby3dl; - u32 res7[4]; + u32 mpwrdqby0dl; + u32 mpwrdqby1dl; + u32 mpwrdqby2dl; + u32 mpwrdqby3dl; u32 mpdgctrl0; u32 mpdgctrl1; - u32 res8; + u32 mpdgdlst0; u32 mprddlctl; - u32 res9; + u32 mprddlst; u32 mpwrdlctl; - u32 res10[25]; + u32 mpwrdlst; + u32 mpsdctrl; + u32 mpzqlp2ctl; + u32 mprddlhwctl; + u32 mpwrdlhwctl; + u32 mprddlhwst0; + u32 mprddlhwst1; + u32 mpwrdlhwst0; + u32 mpwrdlhwst1; + u32 mpwlhwerr; + u32 mpdghwst0; + u32 mpdghwst1; + u32 mpdghwst2; + u32 mpdghwst3; + u32 mppdcmpr1; + u32 mppdcmpr2; + u32 mpswdar0; + u32 mpswdrdr0; + u32 mpswdrdr1; + u32 mpswdrdr2; + u32 mpswdrdr3; + u32 mpswdrdr4; + u32 mpswdrdr5; + u32 mpswdrdr6; + u32 mpswdrdr7; u32 mpmur0; + u32 mpwrcadl; + u32 mpdccr; +}; + +#define MX6SL_IOM_DDR_BASE 0x020e0300 +struct mx6sl_iomux_ddr_regs { + u32 dram_cas; + u32 dram_cs0_b; + u32 dram_cs1_b; + u32 dram_dqm0; + u32 dram_dqm1; + u32 dram_dqm2; + u32 dram_dqm3; + u32 dram_ras; + u32 dram_reset; + u32 dram_sdba0; + u32 dram_sdba1; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdcke1; + u32 dram_sdclk_0; + u32 dram_odt0; + u32 dram_odt1; + u32 dram_sdqs0; + u32 dram_sdqs1; + u32 dram_sdqs2; + u32 dram_sdqs3; + u32 dram_sdwe_b; +}; + +#define MX6SL_IOM_GRP_BASE 0x020e0500 +struct mx6sl_iomux_grp_regs { + u32 res1[43]; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 grp_ddrpke; + u32 grp_ddrpk; + u32 grp_ddrhys; + u32 grp_ddrmode; + u32 grp_b0ds; + u32 grp_ctlds; + u32 grp_b1ds; + u32 grp_ddr_type; + u32 grp_b2ds; + u32 grp_b3ds; }; #define MX6UL_IOM_DDR_BASE 0x020e0200 @@ -278,6 +377,21 @@ struct mx6_ddr3_cfg { u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ }; +/* Device Information: Varies per LPDDR2 part number and speed grade */ +struct mx6_lpddr2_cfg { + u16 mem_speed; /* ie 800 for LPDDR2-800 */ + u8 density; /* chip density (Gb) (1,2,4,8) */ + u8 width; /* bus width (bits) (4,8,16) */ + u8 banks; /* number of banks */ + u8 rowaddr; /* row address bits (11-16)*/ + u8 coladdr; /* col address bits (9-12) */ + u16 trcd_lp; + u16 trppb_lp; + u16 trpab_lp; + u16 trcmin; /* tRC min (ns*100) */ + u16 trasmin; /* tRAS min (ns*100) */ +}; + /* System Information: Varies per board design, layout, and term choices */ struct mx6_ddr_sysinfo { u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ @@ -293,6 +407,7 @@ struct mx6_ddr_sysinfo { u8 rst_to_cke; /* Time from SDE enable to CKE rise */ u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ + u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */ }; /* @@ -320,6 +435,8 @@ struct mx6_mmdc_calibration { /* write delay */ u32 p0_mpwrdlctl; u32 p1_mpwrdlctl; + /* lpddr2 zq hw calibration */ + u32 mpzqlp2ctl; }; /* configure iomux (pinctl/padctl) */ @@ -335,11 +452,14 @@ void mx6sx_dram_iocfg(unsigned width, void mx6ul_dram_iocfg(unsigned width, const struct mx6ul_iomux_ddr_regs *, const struct mx6ul_iomux_grp_regs *); +void mx6sl_dram_iocfg(unsigned width, + const struct mx6sl_iomux_ddr_regs *, + const struct mx6sl_iomux_grp_regs *); /* configure mx6 mmdc registers */ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, const struct mx6_mmdc_calibration *, - const struct mx6_ddr3_cfg *); + const void *); #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h new file mode 100644 index 0000000000..c3c4d69818 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX6SL_DDR_H__ +#define __ASM_ARCH_MX6SL_DDR_H__ + +#ifndef CONFIG_MX6SL +#error "wrong CPU" +#endif + +#define MX6_IOM_DRAM_CAS_B 0x020e0300 +#define MX6_IOM_DRAM_CS0_B 0x020e0304 +#define MX6_IOM_DRAM_CS1_B 0x020e0308 + +#define MX6_IOM_DRAM_DQM0 0x020e030c +#define MX6_IOM_DRAM_DQM1 0x020e0310 +#define MX6_IOM_DRAM_DQM2 0x020e0314 +#define MX6_IOM_DRAM_DQM3 0x020e0318 + +#define MX6_IOM_DRAM_RAS_B 0x020e031c +#define MX6_IOM_DRAM_RESET 0x020e0320 + +#define MX6_IOM_DRAM_SDBA0 0x020e0324 +#define MX6_IOM_DRAM_SDBA1 0x020e0328 +#define MX6_IOM_DRAM_SDBA2 0x020e032c + +#define MX6_IOM_DRAM_SDCKE0 0x020e0330 +#define MX6_IOM_DRAM_SDCKE1 0x020e0334 + +#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338 + +#define MX6_IOM_DRAM_ODT0 0x020e033c +#define MX6_IOM_DRAM_ODT1 0x020e0340 + +#define MX6_IOM_DRAM_SDQS0_P 0x020e0344 +#define MX6_IOM_DRAM_SDQS1_P 0x020e0348 +#define MX6_IOM_DRAM_SDQS2_P 0x020e034c +#define MX6_IOM_DRAM_SDQS3_P 0x020e0350 + +#define MX6_IOM_DRAM_SDWE_B 0x020e0354 + +#endif /*__ASM_ARCH_MX6SL_DDR_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index eee8ca8af7..16c9b766d9 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -5,47 +5,4 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <asm/imx-common/regs-common.h> -#include "../arch-imx/cpu.h" - -#define soc_rev() (get_cpu_rev() & 0xFF) -#define is_soc_rev(rev) (soc_rev() == rev) - -u32 get_nr_cpus(void); -u32 get_cpu_rev(void); -u32 get_cpu_speed_grade_hz(void); -u32 get_cpu_temp_grade(int *minc, int *maxc); - -/* returns MXC_CPU_ value */ -#define cpu_type(rev) (((rev) >> 12) & 0xff) - -/* both macros return/take MXC_CPU_ constants */ -#define get_cpu_type() (cpu_type(get_cpu_rev())) -#define is_cpu_type(cpu) (get_cpu_type() == cpu) - -const char *get_imx_type(u32 imxtype); -unsigned imx_ddr_size(void); -void set_chipselect_size(int const); - -#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ - -int fecmxc_initialize(bd_t *bis); -u32 get_ahb_clk(void); -u32 get_periph_clk(void); - -int mxs_reset_block(struct mxs_register_32 *reg); -int mxs_wait_mask_set(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); -int mxs_wait_mask_clr(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); -#endif +#include <asm/imx-common/sys_proto.h> diff --git a/arch/arm/include/asm/arch-mx7/gpio.h b/arch/arm/include/asm/arch-mx7/gpio.h new file mode 100644 index 0000000000..b7890c2903 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/gpio.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MX7_GPIO_H +#define __ASM_ARCH_MX7_GPIO_H + +#include <asm/imx-common/gpio.h> + +#endif /* __ASM_ARCH_MX7_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx7/mx7-pins.h b/arch/arm/include/asm/arch-mx7/mx7-pins.h new file mode 100644 index 0000000000..164c2be8ac --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/mx7-pins.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_MX7_PINS_H__ +#define __ASM_ARCH_MX7_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +#if defined(CONFIG_MX7D) +#include "mx7d_pins.h" +#elif defined(CONFIG_MX7S) +#include "mx7s_pins.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX7D */ + +#endif /*__ASM_ARCH_MX7_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/mx7d_pins.h b/arch/arm/include/asm/arch-mx7/mx7d_pins.h new file mode 100644 index 0000000000..d8b4097262 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/mx7d_pins.h @@ -0,0 +1,1308 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX7D_PINS_H__ +#define __ASM_ARCH_IMX7D_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +enum { + MX7D_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO02__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0), + MX7D_PAD_GPIO1_IO02__SAI2_MCLK = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__CCM_CLKO1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO02__USB_OTG1_ID = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0), + + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__PWM3_OUT = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0), + MX7D_PAD_GPIO1_IO03__SAI3_MCLK = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__CCM_CLKO2 = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO03__USB_OTG2_ID = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0), + + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO04__USB_OTG1_OC = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0), + MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4 = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0), + MX7D_PAD_GPIO1_IO04__UART5_CTS_B = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0), + MX7D_PAD_GPIO1_IO04__I2C1_SCL = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0), + + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0), + MX7D_PAD_GPIO1_IO05__UART5_RTS_B = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0), + MX7D_PAD_GPIO1_IO05__I2C1_SDA = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0), + + MX7D_PAD_GPIO1_IO06__GPIO1_IO6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__USB_OTG2_OC = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0), + MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0), + MX7D_PAD_GPIO1_IO06__UART5_RX_DATA = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0), + MX7D_PAD_GPIO1_IO06__I2C2_SCL = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0), + MX7D_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO06__KPP_ROW4 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0), + + MX7D_PAD_GPIO1_IO07__GPIO1_IO7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0), + MX7D_PAD_GPIO1_IO07__UART5_TX_DATA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0), + MX7D_PAD_GPIO1_IO07__I2C2_SDA = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0), + MX7D_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO07__KPP_COL4 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0), +}; + +enum { + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__SD1_VSELECT = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DCE_RX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0), + MX7D_PAD_GPIO1_IO08__UART3_DTE_TX = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO08__I2C3_SCL = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0), + MX7D_PAD_GPIO1_IO08__KPP_COL5 = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0), + MX7D_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__SD1_LCTL = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DCE_TX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO09__UART3_DTE_RX = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0), + MX7D_PAD_GPIO1_IO09__I2C3_SDA = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0), + MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0), + MX7D_PAD_GPIO1_IO09__KPP_ROW5 = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0), + MX7D_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__SD2_LCTL = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0), + MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO10__I2C4_SCL = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0), + MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0), + MX7D_PAD_GPIO1_IO10__KPP_COL6 = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0), + MX7D_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__SD3_LCTL = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__ENET1_MDC = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0), + MX7D_PAD_GPIO1_IO11__I2C4_SDA = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0), + MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0), + MX7D_PAD_GPIO1_IO11__KPP_ROW6 = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0), + MX7D_PAD_GPIO1_IO11__PWM4_OUT = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0), + + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__SD2_VSELECT = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0), + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0), + MX7D_PAD_GPIO1_IO12__CM4_NMI = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0), + MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO12__USB_OTG1_ID = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0), + + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__SD3_VSELECT = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0), + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0), + MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0), + MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO13__USB_OTG2_ID = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0), + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__SD3_CD_B = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0), + MX7D_PAD_GPIO1_IO14__ENET2_MDIO = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0), + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0), + MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0), + MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0), + + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__SD3_WP = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0), + MX7D_PAD_GPIO1_IO15__ENET2_MDC = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0), + MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0), + MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0), + + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__KPP_ROW3 = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0), + MX7D_PAD_EPDC_DATA00__EIM_AD0 = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_DATA0 = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0), + MX7D_PAD_EPDC_DATA00__LCD_CLK = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__KPP_COL3 = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0), + MX7D_PAD_EPDC_DATA01__EIM_AD1 = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_DATA1 = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0), + MX7D_PAD_EPDC_DATA01__LCD_ENABLE = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__KPP_ROW2 = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0), + MX7D_PAD_EPDC_DATA02__EIM_AD2 = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_DATA2 = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0), + MX7D_PAD_EPDC_DATA02__LCD_VSYNC = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0), + + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__KPP_COL2 = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0), + MX7D_PAD_EPDC_DATA03__EIM_AD3 = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_DATA3 = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0), + MX7D_PAD_EPDC_DATA03__LCD_HSYNC = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__KPP_ROW1 = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0), + MX7D_PAD_EPDC_DATA04__EIM_AD4 = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA04__LCD_DATA4 = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0), + MX7D_PAD_EPDC_DATA04__JTAG_FAIL = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__KPP_COL1 = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0), + MX7D_PAD_EPDC_DATA05__EIM_AD5 = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA05__LCD_DATA5 = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0), + MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__KPP_ROW0 = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0), + MX7D_PAD_EPDC_DATA06__EIM_AD6 = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA06__LCD_DATA6 = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0), + MX7D_PAD_EPDC_DATA06__JTAG_DE_B = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__KPP_COL0 = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0), + MX7D_PAD_EPDC_DATA07__EIM_AD7 = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA07__LCD_DATA7 = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0), + MX7D_PAD_EPDC_DATA07__JTAG_DONE = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0), + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0), + MX7D_PAD_EPDC_DATA08__UART6_DTE_TX = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__EIM_OE = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_DATA8 = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0), + MX7D_PAD_EPDC_DATA08__LCD_BUSY = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0), + MX7D_PAD_EPDC_DATA08__EPDC_SDCLK = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__UART6_DTE_RX = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0), + MX7D_PAD_EPDC_DATA09__EIM_RW = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__GPIO2_IO9 = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA9 = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0), + MX7D_PAD_EPDC_DATA09__LCD_DATA0 = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0), + MX7D_PAD_EPDC_DATA09__EPDC_SDLE = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0), + MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__EIM_CS0_B = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA10 = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0), + MX7D_PAD_EPDC_DATA10__LCD_DATA9 = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0), + MX7D_PAD_EPDC_DATA10__EPDC_SDOE = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0), + MX7D_PAD_EPDC_DATA11__EIM_BCLK = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA11 = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0), + MX7D_PAD_EPDC_DATA11__LCD_DATA1 = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0), + MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0), + MX7D_PAD_EPDC_DATA12__UART7_DTE_TX = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__EIM_LBA_B = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__GPIO2_IO12 = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA12 = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0), + MX7D_PAD_EPDC_DATA12__LCD_DATA21 = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0), + MX7D_PAD_EPDC_DATA12__EPDC_GDCLK = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__UART7_DTE_RX = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0), + MX7D_PAD_EPDC_DATA13__EIM_WAIT = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_DATA13 = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0), + MX7D_PAD_EPDC_DATA13__LCD_CS = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA13__EPDC_GDOE = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0), + MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__EIM_EB_B0 = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__GPIO2_IO14 = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA14 = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0), + MX7D_PAD_EPDC_DATA14__LCD_DATA22 = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0), + MX7D_PAD_EPDC_DATA14__EPDC_GDSP = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0), + MX7D_PAD_EPDC_DATA15__EIM_CS1_B = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_DATA15 = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0), + MX7D_PAD_EPDC_DATA15__LCD_WR_RWN = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0), + MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0), + + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__KPP_ROW4 = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0), + MX7D_PAD_EPDC_SDCLK__EIM_AD10 = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_CLK = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCLK__LCD_DATA20 = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0), + + MX7D_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__KPP_COL4 = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0), + MX7D_PAD_EPDC_SDLE__EIM_AD11 = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__GPIO2_IO17 = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA16 = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0), + MX7D_PAD_EPDC_SDLE__LCD_DATA8 = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0), + + MX7D_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__KPP_COL5 = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0), + MX7D_PAD_EPDC_SDOE__EIM_AD12 = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__GPIO2_IO18 = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA17 = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0), + MX7D_PAD_EPDC_SDOE__LCD_DATA23 = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0), + + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__KPP_ROW5 = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0), + MX7D_PAD_EPDC_SDSHR__EIM_AD13 = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA18 = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0), + MX7D_PAD_EPDC_SDSHR__LCD_DATA10 = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0), + + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__EIM_AD14 = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA19 = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0), + MX7D_PAD_EPDC_SDCE0__LCD_DATA5 = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0), + + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0), + MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__EIM_AD15 = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA20 = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0), + MX7D_PAD_EPDC_SDCE1__LCD_DATA4 = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0), + + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__KPP_COL6 = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0), + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA21 = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0), + MX7D_PAD_EPDC_SDCE2__LCD_DATA3 = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0), + + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__KPP_ROW6 = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0), + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA22 = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0), + MX7D_PAD_EPDC_SDCE3__LCD_DATA2 = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0), + + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__KPP_COL7 = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0), + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA23 = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0), + MX7D_PAD_EPDC_GDCLK__LCD_DATA16 = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0), + + MX7D_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__KPP_ROW7 = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0), + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__GPIO2_IO25 = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_WR_RWN = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDOE__LCD_DATA18 = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0), + + MX7D_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__GPIO2_IO26 = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_RD_E = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDRL__LCD_DATA19 = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0), + + MX7D_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__ENET2_TX_ER = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__GPIO2_IO27 = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_GDSP__LCD_BUSY = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0), + MX7D_PAD_EPDC_GDSP__LCD_DATA17 = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0), + + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0), + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_CS = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR0__LCD_DATA7 = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0), + + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0), + MX7D_PAD_EPDC_BDR1__EIM_AD8 = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_ENABLE = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_BDR1__LCD_DATA6 = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0), + + MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0), + MX7D_PAD_EPDC_PWR_COM__ENET2_CRS = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0), + + MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__ENET2_COL = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0), + MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0), + + MX7D_PAD_LCD_CLK__LCD_CLK = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__ECSPI4_MISO = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0), + MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__CSI_DATA16 = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0), + MX7D_PAD_LCD_CLK__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_CLK__GPIO3_IO0 = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_ENABLE__LCD_ENABLE = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0), + MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__CSI_DATA17 = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DCE_TX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_ENABLE__UART2_DTE_RX = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0), + MX7D_PAD_LCD_ENABLE__GPIO3_IO1 = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_HSYNC__LCD_HSYNC = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0), + MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__CSI_DATA18 = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0), + MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_HSYNC__GPIO3_IO2 = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_VSYNC__LCD_VSYNC = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0), + MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0), + MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__CSI_DATA19 = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0), + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_RESET__LCD_RESET = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPT1_COMPARE1 = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__CSI_FIELD = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__EIM_DTACK_B = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_RESET__GPIO3_IO4 = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA00__LCD_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0), + MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__CSI_DATA20 = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__EIM_DATA0 = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__GPIO3_IO5 = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA01__LCD_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0), + MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__CSI_DATA21 = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__EIM_DATA1 = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__GPIO3_IO6 = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA02__LCD_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0), + MX7D_PAD_LCD_DATA02__GPT1_CLK = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__CSI_DATA22 = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__EIM_DATA2 = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__GPIO3_IO7 = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA03__LCD_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0), + MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__CSI_DATA23 = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__EIM_DATA3 = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__GPIO3_IO8 = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA04__LCD_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0), + MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__CSI_VSYNC = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0), + MX7D_PAD_LCD_DATA04__EIM_DATA4 = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__GPIO3_IO9 = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA05__LCD_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0), + MX7D_PAD_LCD_DATA05__CSI_HSYNC = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0), + MX7D_PAD_LCD_DATA05__EIM_DATA5 = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA06__LCD_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0), + MX7D_PAD_LCD_DATA06__CSI_PIXCLK = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0), + MX7D_PAD_LCD_DATA06__EIM_DATA6 = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA07__LCD_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0), + MX7D_PAD_LCD_DATA07__CSI_MCLK = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__EIM_DATA7 = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA08__LCD_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0), + MX7D_PAD_LCD_DATA08__CSI_DATA9 = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0), + MX7D_PAD_LCD_DATA08__EIM_DATA8 = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA09__LCD_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0), + MX7D_PAD_LCD_DATA09__CSI_DATA8 = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0), + MX7D_PAD_LCD_DATA09__EIM_DATA9 = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA10__LCD_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0), + MX7D_PAD_LCD_DATA10__CSI_DATA7 = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0), + MX7D_PAD_LCD_DATA10__EIM_DATA10 = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA11__LCD_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0), + MX7D_PAD_LCD_DATA11__CSI_DATA6 = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0), + MX7D_PAD_LCD_DATA11__EIM_DATA11 = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA12__LCD_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0), + MX7D_PAD_LCD_DATA12__CSI_DATA5 = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0), + MX7D_PAD_LCD_DATA12__EIM_DATA12 = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA13__LCD_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0), + MX7D_PAD_LCD_DATA13__CSI_DATA4 = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0), + MX7D_PAD_LCD_DATA13__EIM_DATA13 = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA14__LCD_DATA14 = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0), + MX7D_PAD_LCD_DATA14__CSI_DATA3 = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0), + MX7D_PAD_LCD_DATA14__EIM_DATA14 = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA15__LCD_DATA15 = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0), + MX7D_PAD_LCD_DATA15__CSI_DATA2 = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0), + MX7D_PAD_LCD_DATA15__EIM_DATA15 = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA16__LCD_DATA16 = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0), + MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0), + MX7D_PAD_LCD_DATA16__CSI_DATA1 = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__EIM_CRE = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA17__LCD_DATA17 = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0), + MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0), + MX7D_PAD_LCD_DATA17__CSI_DATA0 = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA18__LCD_DATA18 = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0), + MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0), + MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__CSI_DATA15 = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__EIM_CS2_B = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__EIM_CS3_B = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA19__LCD_DATA19 = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0), + MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0), + MX7D_PAD_LCD_DATA19__CSI_DATA14 = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__EIM_ADDR23 = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__I2C3_SCL = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0), + + MX7D_PAD_LCD_DATA20__LCD_DATA20 = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0), + MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0), + MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA20__CSI_DATA13 = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0), + + MX7D_PAD_LCD_DATA21__LCD_DATA21 = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0), + MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0), + MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__CSI_DATA12 = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__EIM_ADDR24 = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA21__I2C3_SDA = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0), + + MX7D_PAD_LCD_DATA22__LCD_DATA22 = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0), + MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0), + MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__CSI_DATA11 = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__EIM_ADDR25 = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA22__I2C4_SCL = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0), + + MX7D_PAD_LCD_DATA23__LCD_DATA23 = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0), + MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0), + MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__CSI_DATA10 = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__EIM_ADDR26 = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0), + MX7D_PAD_LCD_DATA23__I2C4_SDA = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), + + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__I2C1_SCL = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_RX_DATA__ENET1_MDIO = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0), + MX7D_PAD_UART1_TX_DATA__I2C1_SDA = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0), + MX7D_PAD_UART1_TX_DATA__SAI3_MCLK = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0), + MX7D_PAD_UART1_TX_DATA__ENET1_MDC = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), + + MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__I2C2_SCL = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_RX_DATA__ENET2_MDIO = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), + + MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__I2C2_SDA = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0), + MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0), + MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0), + MX7D_PAD_UART2_TX_DATA__ENET2_MDC = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0), + + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0), + MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0), + MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0), + MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RX_DATA__SD1_LCTL = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0), + MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0), + MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0), + MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_TX_DATA__SD2_LCTL = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__GPIO4_IO6 = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_RTS_B__SD3_LCTL = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0), + + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0), + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0), + MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0), + MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0), + MX7D_PAD_UART3_CTS_B__SD1_VSELECT = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0), + MX7D_PAD_I2C1_SCL__UART4_DCE_CTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__UART4_DTE_RTS = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0), + MX7D_PAD_I2C1_SCL__FLEXCAN1_RX = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0), + MX7D_PAD_I2C1_SCL__ECSPI3_MISO = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0), + MX7D_PAD_I2C1_SCL__GPIO4_IO8 = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SCL__SD2_VSELECT = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DCE_RTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0), + MX7D_PAD_I2C1_SDA__UART4_DTE_CTS = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__FLEXCAN1_TX = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__ECSPI3_MOSI = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0), + MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0), + MX7D_PAD_I2C1_SDA__GPIO4_IO9 = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C1_SDA__SD3_VSELECT = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0), + MX7D_PAD_I2C2_SCL__UART4_DCE_RX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0), + MX7D_PAD_I2C2_SCL__UART4_DTE_TX = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__ECSPI3_SCLK = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0), + MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0), + MX7D_PAD_I2C2_SCL__GPIO4_IO10 = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SCL__SD3_CD_B = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0), + + MX7D_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0), + MX7D_PAD_I2C2_SDA__UART4_DCE_TX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__UART4_DTE_RX = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0), + MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__ECSPI3_SS0 = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0), + MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__GPIO4_IO11 = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0), + MX7D_PAD_I2C2_SDA__SD3_WP = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0), + + MX7D_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0), + MX7D_PAD_I2C3_SCL__UART5_DCE_CTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__UART5_DTE_RTS = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0), + MX7D_PAD_I2C3_SCL__FLEXCAN2_RX = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0), + MX7D_PAD_I2C3_SCL__CSI_VSYNC = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0), + MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0), + MX7D_PAD_I2C3_SCL__GPIO4_IO12 = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SCL__EPDC_BDR0 = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0), + MX7D_PAD_I2C3_SDA__UART5_DCE_RTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0), + MX7D_PAD_I2C3_SDA__UART5_DTE_CTS = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__CSI_HSYNC = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0), + MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0), + MX7D_PAD_I2C3_SDA__GPIO4_IO13 = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0), + MX7D_PAD_I2C3_SDA__EPDC_BDR1 = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0), + MX7D_PAD_I2C4_SCL__UART5_DCE_RX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0), + MX7D_PAD_I2C4_SCL__UART5_DTE_TX = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__CSI_PIXCLK = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0), + MX7D_PAD_I2C4_SCL__USB_OTG1_ID = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0), + MX7D_PAD_I2C4_SCL__GPIO4_IO14 = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SCL__EPDC_VCOM0 = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0), + + MX7D_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0), + MX7D_PAD_I2C4_SDA__UART5_DCE_TX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__UART5_DTE_RX = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0), + MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__CSI_MCLK = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__USB_OTG2_ID = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0), + MX7D_PAD_I2C4_SDA__GPIO4_IO15 = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0), + MX7D_PAD_I2C4_SDA__EPDC_VCOM1 = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0), + MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0), + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0), + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0), + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0), + + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0), + MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__CSI_DATA4 = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0), + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0), + + MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0), + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__CSI_DATA5 = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0), + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0), + MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0), + MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0), + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0), + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0), + MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0), + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0), + + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0), + MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_MISO__CSI_DATA8 = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0), + MX7D_PAD_ECSPI2_MISO__LCD_DATA15 = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0), + + MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0), + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__CSI_DATA9 = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0), + MX7D_PAD_ECSPI2_SS0__LCD_RESET = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0), + MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_CD_B__SD1_CD_B = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__UART6_DCE_RX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0), + MX7D_PAD_SD1_CD_B__UART6_DTE_TX = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__ECSPI4_MISO = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0), + MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_CD_B__CCM_CLKO1 = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_WP__SD1_WP = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DCE_TX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__UART6_DTE_RX = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0), + MX7D_PAD_SD1_WP__ECSPI4_MOSI = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0), + MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0), + MX7D_PAD_SD1_WP__GPIO5_IO1 = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_WP__CCM_CLKO2 = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0), + + MX7D_PAD_SD1_RESET_B__SD1_RESET_B = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__SAI3_MCLK = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0), + MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0), + MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0), + MX7D_PAD_SD1_CLK__UART6_DCE_CTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_CLK__UART6_DTE_RTS = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0), + MX7D_PAD_SD1_CLK__ECSPI4_SS0 = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0), + MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0), + MX7D_PAD_SD1_CLK__GPIO5_IO3 = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0), + MX7D_PAD_SD1_CMD__ECSPI4_SS1 = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0), + MX7D_PAD_SD1_CMD__GPIO5_IO4 = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0), + + MX7D_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0), + MX7D_PAD_SD1_DATA0__UART7_DCE_RX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0), + MX7D_PAD_SD1_DATA0__UART7_DTE_TX = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__ECSPI4_SS2 = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0), + MX7D_PAD_SD1_DATA0__GPIO5_IO5 = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0), + + MX7D_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0), + MX7D_PAD_SD1_DATA1__UART7_DCE_TX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__UART7_DTE_RX = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0), + MX7D_PAD_SD1_DATA1__ECSPI4_SS3 = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0), + MX7D_PAD_SD1_DATA1__GPIO5_IO6 = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0), + + MX7D_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0), + MX7D_PAD_SD1_DATA2__UART7_DCE_CTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__UART7_DTE_RTS = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0), + MX7D_PAD_SD1_DATA2__ECSPI4_RDY = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0), + MX7D_PAD_SD1_DATA2__GPIO5_IO7 = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0), + + MX7D_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__UART7_DCE_RTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0), + MX7D_PAD_SD1_DATA3__UART7_DTE_CTS = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__ECSPI3_SS1 = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0), + MX7D_PAD_SD1_DATA3__GPIO5_IO8 = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0), + MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0), + + MX7D_PAD_SD2_CD_B__SD2_CD_B = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__ENET1_MDIO = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0), + MX7D_PAD_SD2_CD_B__ENET2_MDIO = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0), + MX7D_PAD_SD2_CD_B__ECSPI3_SS2 = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0), + MX7D_PAD_SD2_CD_B__GPIO5_IO9 = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0), + + MX7D_PAD_SD2_WP__SD2_WP = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET1_MDC = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ENET2_MDC = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__ECSPI3_SS3 = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__USB_OTG1_ID = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0), + MX7D_PAD_SD2_WP__GPIO5_IO10 = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0), + MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0), + + MX7D_PAD_SD2_RESET_B__SD2_RESET_B = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SAI2_MCLK = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__SD2_RESET = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__ECSPI3_RDY = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_RESET_B__USB_OTG2_ID = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0), + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__SAI2_RX_SYNC = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0), + MX7D_PAD_SD2_CLK__MQS_RIGHT = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPT4_CLK = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CLK__GPIO5_IO12 = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SAI2_RX_BCLK = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0), + MX7D_PAD_SD2_CMD__MQS_LEFT = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0), + MX7D_PAD_SD2_CMD__GPIO5_IO13 = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0), + MX7D_PAD_SD2_DATA0__UART4_DCE_RX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0), + MX7D_PAD_SD2_DATA0__UART4_DTE_TX = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA0__GPIO5_IO14 = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DCE_TX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__UART4_DTE_RX = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0), + MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA1__GPIO5_IO15 = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DCE_CTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__UART4_DTE_RTS = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0), + MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA2__GPIO5_IO16 = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__UART4_DCE_RTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0), + MX7D_PAD_SD2_DATA3__UART4_DTE_CTS = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0), + MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0), + MX7D_PAD_SD2_DATA3__GPIO5_IO17 = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CLK__SD3_CLK = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__NAND_CLE = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__ECSPI4_MISO = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0), + MX7D_PAD_SD3_CLK__SAI3_RX_SYNC = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0), + MX7D_PAD_SD3_CLK__GPT3_CLK = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CLK__GPIO6_IO0 = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_CMD__SD3_CMD = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__NAND_ALE = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__ECSPI4_MOSI = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0), + MX7D_PAD_SD3_CMD__SAI3_RX_BCLK = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0), + MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_CMD__GPIO6_IO1 = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA0__SD3_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__NAND_DATA00 = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__ECSPI4_SS0 = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0), + MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0), + MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA0__GPIO6_IO2 = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA1__SD3_DATA1 = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__NAND_DATA01 = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0), + MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0), + MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA1__GPIO6_IO3 = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA2__SD3_DATA2 = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__NAND_DATA02 = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__I2C3_SDA = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0), + MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0), + MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA2__GPIO6_IO4 = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA3__SD3_DATA3 = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__NAND_DATA03 = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__I2C3_SCL = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0), + MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA3__GPIO6_IO5 = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA4__SD3_DATA4 = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__NAND_DATA04 = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__UART3_DCE_RX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0), + MX7D_PAD_SD3_DATA4__UART3_DTE_TX = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA4__FLEXCAN2_RX = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0), + MX7D_PAD_SD3_DATA4__GPIO6_IO6 = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA5__SD3_DATA5 = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__NAND_DATA05 = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DCE_TX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__UART3_DTE_RX = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0), + MX7D_PAD_SD3_DATA5__FLEXCAN1_TX = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA5__GPIO6_IO7 = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA6__SD3_DATA6 = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__NAND_DATA06 = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__SD3_WP = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0), + MX7D_PAD_SD3_DATA6__UART3_DCE_RTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0), + MX7D_PAD_SD3_DATA6__UART3_DTE_CTS = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__FLEXCAN2_TX = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA6__GPIO6_IO8 = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_DATA7__SD3_DATA7 = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__NAND_DATA07 = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__SD3_CD_B = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0), + MX7D_PAD_SD3_DATA7__UART3_DCE_CTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_DATA7__UART3_DTE_RTS = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0), + MX7D_PAD_SD3_DATA7__FLEXCAN1_RX = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0), + MX7D_PAD_SD3_DATA7__GPIO6_IO9 = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_STROBE__SD3_STROBE = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__NAND_RE_B = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_STROBE__GPIO6_IO10 = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0), + + MX7D_PAD_SD3_RESET_B__SD3_RESET_B = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__NAND_WE_B = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SD3_RESET = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__SAI3_MCLK = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0), + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0), + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0), + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0), + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0), + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0), + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0), + MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0), + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0), + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0), + MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0), + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0), + MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI1_MCLK__SAI1_MCLK = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__NAND_WP_B = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SAI2_MCLK = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0), + MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0), + MX7D_PAD_SAI1_MCLK__GPIO6_IO18 = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0), + MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0), + MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0), + MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0), + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0), + MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0), + + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0), + MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0), + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_RX_DATA__KPP_COL7 = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0), + + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0), + MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0), + MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0), + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0), + MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0), + MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0), + MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0), + MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0), + MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0), + + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0), + MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0), + + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0), + + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0), + + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0), + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0), + MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0), + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0), + MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0), + + MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0), + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0), + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0), + MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0), + MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0), + MX7D_PAD_ENET1_RX_CLK__GPT2_CLK = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0), + MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_CRS__ENET1_CRS = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0), + MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__GPIO7_IO14 = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0), + MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0), + + MX7D_PAD_ENET1_COL__ENET1_COL = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__GPIO7_IO15 = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0), + MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0), + MX7D_PAD_ENET1_COL__CSU_INT_DEB = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX7D_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 4678723754..20ff101a2b 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -7,18 +7,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __SYS_PROTO_H__ -#define __SYS_PROTO_H__ +#ifndef __MXS_SYS_PROTO_H__ +#define __MXS_SYS_PROTO_H__ -#include <asm/imx-common/regs-common.h> - -int mxs_reset_block(struct mxs_register_32 *reg); -int mxs_wait_mask_set(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); -int mxs_wait_mask_clr(struct mxs_register_32 *reg, - uint32_t mask, - unsigned int timeout); +#include <asm/imx-common/sys_proto.h> int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 04fa0be64c..0c928d40e7 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -65,6 +65,7 @@ /* * Section */ +#define PMD_SECT_NON_SHARE (0 << 8) #define PMD_SECT_OUTER_SHARE (2 << 8) #define PMD_SECT_INNER_SHARE (3 << 8) #define PMD_SECT_AF (1 << 10) @@ -110,8 +111,13 @@ TCR_T0SZ(VA_BITS)) #ifndef __ASSEMBLY__ + void set_pgtable_section(u64 *page_table, u64 index, - u64 section, u64 memory_type); + u64 section, u64 memory_type, + u64 share); +void set_pgtable_table(u64 *page_table, u64 index, + u64 *table_addr); + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index f097c81a92..f2d4c3c5f9 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,6 +8,28 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_ESBC_VALIDATE +#define CONFIG_FSL_SEC_MON +#define CONFIG_SHA_PROG_HW_ACCEL +#define CONFIG_DM +#define CONFIG_RSA +#define CONFIG_RSA_FREESCALE_EXP +#ifndef CONFIG_FSL_CAAM +#define CONFIG_FSL_CAAM +#endif + +#define CONFIG_KEY_REVOCATION +#ifndef CONFIG_SYS_RAMBOOT +/* The key used for verification of next level images + * is picked up from an Extension Table which has + * been verified by the ISBC (Internal Secure boot Code) + * in boot ROM of the SoC. + * The feature is only applicable in case of NOR boot and is + * not applicable in case of RAMBOOT (NAND, SD, SPI). + */ +#define CONFIG_FSL_ISBC_KEY_EXT +#endif + #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_EXTRA_ENV \ diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 42098a3f49..1a80a962c7 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -85,6 +85,36 @@ typedef u64 iomux_v3_cfg_t; #define NO_PAD_CTRL (1 << 17) +#ifdef CONFIG_MX7 + +#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 +#define IOMUX_CONFIG_LPSR 0x8 +#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ + MUX_MODE_SHIFT) + +#define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) +#define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) +#define PAD_CTL_DSE_1P8V_70OHM (0x2<<0) +#define PAD_CTL_DSE_1P8V_23OHM (0x3<<0) + +#define PAD_CTL_DSE_3P3V_196OHM (0x0<<0) +#define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) +#define PAD_CTL_DSE_3P3V_98OHM (0x2<<0) +#define PAD_CTL_DSE_3P3V_32OHM (0x3<<0) + +#define PAD_CTL_SRE_FAST (0 << 2) +#define PAD_CTL_SRE_SLOW (0x1 << 2) + +#define PAD_CTL_HYS (0x1 << 3) +#define PAD_CTL_PUE (0x1 << 4) + +#define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE) +#define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE) + +#else + #ifdef CONFIG_MX6 #define PAD_CTL_HYS (1 << 16) @@ -173,6 +203,8 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_SRE_SLOW (0 << 0) #define PAD_CTL_SRE_FAST (1 << 0) +#endif + #define IOMUX_CONFIG_SION 0x10 #define GPIO_PIN_MASK 0x1f diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h new file mode 100644 index 0000000000..6954ee918e --- /dev/null +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include <asm/imx-common/regs-common.h> +#include <common.h> +#include "../arch-imx/cpu.h" + +#define soc_rev() (get_cpu_rev() & 0xFF) +#define is_soc_rev(rev) (soc_rev() == rev) + +/* returns MXC_CPU_ value */ +#define cpu_type(rev) (((rev) >> 12) & 0xff) +/* both macros return/take MXC_CPU_ constants */ +#define get_cpu_type() (cpu_type(get_cpu_rev())) +#define is_cpu_type(cpu) (get_cpu_type() == cpu) + +#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) + +u32 get_nr_cpus(void); +u32 get_cpu_rev(void); +u32 get_cpu_speed_grade_hz(void); +u32 get_cpu_temp_grade(int *minc, int *maxc); +const char *get_imx_type(u32 imxtype); +u32 imx_ddr_size(void); +void sdelay(unsigned long); +void set_chipselect_size(int const); + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int fecmxc_initialize(bd_t *bis); +u32 get_ahb_clk(void); +u32 get_periph_clk(void); + +int mxs_reset_block(struct mxs_register_32 *reg); +int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); +int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); +#endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 15e74bd484..f717103526 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -42,6 +42,7 @@ obj-y += stack.o ifdef CONFIG_CPU_V7M obj-y += interrupts_m.o else ifdef CONFIG_ARM64 +obj-y += ccn504.o obj-y += gic_64.o obj-y += interrupts_64.o else diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S new file mode 100644 index 0000000000..7570c7b231 --- /dev/null +++ b/arch/arm/lib/ccn504.S @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Extracted from gic_64.S + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> + +/************************************************************************* + * + * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST, + * CCI_MN_DVM_DOMAIN_CTL_SET); + * + * Add fully-coherent masters to DVM domain + * + *************************************************************************/ +ENTRY(ccn504_add_masters_to_dvm) + /* + * x0: CCI_MN_BASE + * x1: CCI_MN_RNF_NODEID_LIST + * x2: CCI_MN_DVM_DOMAIN_CTL_SET + */ + + /* Add fully-coherent masters to DVM domain */ + ldr x9, [x0, x1] + str x9, [x0, x2] +1: ldr x10, [x0, x2] + mvn x11, x10 + tst x11, x10 /* Wait for domain addition to complete */ + b.ne 1b + + ret +ENDPROC(ccn504_add_masters_to_dvm) + +/************************************************************************* + * + * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value); + * + * Initialize QoS settings for AR/AW override. + * Right now, this function sets the same QoS value for all RN-I ports + * + *************************************************************************/ +ENTRY(ccn504_set_qos) + /* + * x0: CCI_Sx_QOS_CONTROL_BASE + * x1: QoS Value + */ + + /* Set all RN-I ports to QoS value denoted by x1 */ + ldr x9, [x0] + mov x10, x1 + orr x9, x9, x10 + str x9, [x0] + + ret +ENDPROC(ccn504_set_qos) + diff --git a/arch/powerpc/cpu/mpc5xx/Kconfig b/arch/powerpc/cpu/mpc5xx/Kconfig index 5275447cf6..d81bfd2a50 100644 --- a/arch/powerpc/cpu/mpc5xx/Kconfig +++ b/arch/powerpc/cpu/mpc5xx/Kconfig @@ -8,15 +8,11 @@ choice prompt "Target select" optional -config TARGET_CMI_MPC5XX - bool "Support cmi_mpc5xx" - config TARGET_PATI bool "Support PATI" endchoice -source "board/cmi/Kconfig" source "board/mpl/pati/Kconfig" endmenu diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 3e8d0b1bad..ae0823af65 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -137,12 +137,6 @@ config TARGET_CONTROLCENTERD config TARGET_KMP204X bool "Support kmp204x" -config TARGET_STXGP3 - bool "Support stxgp3" - -config TARGET_STXSSA - bool "Support stxssa" - config TARGET_XPEDITE520X bool "Support xpedite520x" @@ -191,8 +185,6 @@ source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" source "board/socrates/Kconfig" -source "board/stx/stxgp3/Kconfig" -source "board/stx/stxssa/Kconfig" source "board/xes/xpedite520x/Kconfig" source "board/xes/xpedite537x/Kconfig" source "board/xes/xpedite550x/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index fd7f5fa7e1..85eba0b22d 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -74,7 +74,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 7a2d4be42c..7a4465fefc 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -57,6 +57,23 @@ static void set_liodn(struct liodn_id_table *tbl, int size) } } +#ifdef CONFIG_SYS_DPAA_FMAN +static void set_fman_liodn(struct fman_liodn_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) { + u32 liodn; + if (tbl[i].num_ids == 2) + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + else + liodn = tbl[i].id[0]; + + out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); + } +} +#endif + static void setup_sec_liodn_base(void) { ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; @@ -76,7 +93,7 @@ static void setup_sec_liodn_base(void) #ifdef CONFIG_SYS_DPAA_FMAN static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, - struct liodn_id_table *tbl, int size) + struct fman_liodn_id_table *tbl, int size) { int i; ccsr_fman_t *fm; @@ -180,12 +197,12 @@ void set_liodns(void) /* setup FMAN block(s) liodn bases & offsets if we have one */ #ifdef CONFIG_SYS_DPAA_FMAN - set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); + set_fman_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz); #if (CONFIG_SYS_NUM_FMAN == 2) - set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); + set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif @@ -315,6 +332,43 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) } } +#ifdef CONFIG_SYS_DPAA_FMAN +static void fdt_fixup_liodn_tbl_fman(void *blob, + struct fman_liodn_id_table *tbl, + int sz) +{ + int i; + + for (i = 0; i < sz; i++) { + int off; + + if (tbl[i].compat == NULL) + continue; + + /* Try the new compatible first. + * If the node is missing, try the old. + */ + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat[0], tbl[i].compat_offset); + if (off < 0) + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat[1], tbl[i].compat_offset); + + if (off >= 0) { + off = fdt_setprop(blob, off, "fsl,liodn", + &tbl[i].id[0], + sizeof(u32) * tbl[i].num_ids); + if (off > 0) + printf("WARNING unable to set fsl,liodn for FMan Port: %s\n", + fdt_strerror(off)); + } else { + debug("WARNING: could not set fsl,liodn for FMan Portport: %s.\n", + fdt_strerror(off)); + } + } +} +#endif + void fdt_fixup_liodn(void *blob) { #ifdef CONFIG_SYS_SRIO @@ -323,9 +377,9 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_liodn_tbl(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); + fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); #if (CONFIG_SYS_NUM_FMAN == 2) - fdt_fixup_liodn_tbl(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); + fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 6e3cdddaed..8b6d27452e 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -61,7 +61,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 10), SET_FMAN_RX_1G_LIODN(1, 1, 11), SET_FMAN_RX_1G_LIODN(1, 2, 12), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 2b57703b2e..ff8216bf52 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 10), SET_FMAN_RX_1G_LIODN(1, 1, 11), SET_FMAN_RX_1G_LIODN(1, 2, 12), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 94a51439a0..174eb04d7a 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -54,7 +54,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 11), SET_FMAN_RX_1G_LIODN(1, 1, 12), SET_FMAN_RX_1G_LIODN(1, 2, 13), @@ -64,7 +64,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) -struct liodn_id_table fman2_liodn_tbl[] = { +struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 16), SET_FMAN_RX_1G_LIODN(2, 1, 17), SET_FMAN_RX_1G_LIODN(2, 2, 18), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 0f292cf5a8..99e3e91e45 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 10), SET_FMAN_RX_1G_LIODN(1, 1, 11), SET_FMAN_RX_1G_LIODN(1, 2, 12), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 98a568fb10..1c99f9ffe3 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -48,7 +48,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 11), SET_FMAN_RX_1G_LIODN(1, 1, 12), SET_FMAN_RX_1G_LIODN(1, 2, 13), @@ -59,7 +59,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) -struct liodn_id_table fman2_liodn_tbl[] = { +struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 17), SET_FMAN_RX_1G_LIODN(2, 1, 18), SET_FMAN_RX_1G_LIODN(2, 2, 19), diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index a70fb711c7..d867e2a767 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1116,7 +1116,11 @@ switch_as: li r0,0 1: dcbz r0,r3 - dcbtls 0,r0,r3 +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ + dcbtls 2, r0, r3 +#else + dcbtls 0, r0, r3 +#endif addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b @@ -1727,7 +1731,11 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 +#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ + dcblc 2, r0, r3 +#else dcblc r0,r3 +#endif addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index 8a1092ea65..8f95e335d8 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -50,7 +50,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_10G_TYPE2_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 80917224b9..b98c7bcd61 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -55,7 +55,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index eda7f59da0..868f2d5ca1 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -83,7 +83,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 470b0800bf..14ada9e690 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -112,7 +112,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), @@ -124,7 +124,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) -struct liodn_id_table fman2_liodn_tbl[] = { +struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 88), SET_FMAN_RX_1G_LIODN(2, 1, 89), SET_FMAN_RX_1G_LIODN(2, 2, 90), diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 10b86e058a..23ecc895fb 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -8,28 +8,9 @@ choice prompt "Target select" optional -config TARGET_CSB272 - bool "Support csb272" - -config TARGET_CSB472 - bool "Support csb472" - -config TARGET_LWMON5 - bool "Support lwmon5" - select SUPPORT_SPL - -config TARGET_PCS440EP - bool "Support pcs440ep" - -config TARGET_SBC405 - bool "Support sbc405" - config TARGET_T3CORP bool "Support t3corp" -config TARGET_ZEUS - bool "Support zeus" - config TARGET_ACADIA bool "Support acadia" @@ -140,12 +121,6 @@ config TARGET_MIP405 config TARGET_PIP405 bool "Support PIP405" -config TARGET_ALPR - bool "Support alpr" - -config TARGET_P3P440 - bool "Support p3p440" - config TARGET_XPEDITE1000 bool "Support xpedite1000" @@ -179,8 +154,6 @@ source "board/amcc/yosemite/Kconfig" source "board/amcc/yucca/Kconfig" source "board/avnet/fx12mm/Kconfig" source "board/avnet/v5fx30teval/Kconfig" -source "board/csb272/Kconfig" -source "board/csb472/Kconfig" source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci405/Kconfig" source "board/esd/plu405/Kconfig" @@ -192,19 +165,13 @@ source "board/gdsys/405ex/Kconfig" source "board/gdsys/dlvision/Kconfig" source "board/gdsys/gdppc440etx/Kconfig" source "board/gdsys/intip/Kconfig" -source "board/lwmon5/Kconfig" source "board/mosaixtech/icon/Kconfig" source "board/mpl/mip405/Kconfig" source "board/mpl/pip405/Kconfig" -source "board/pcs440ep/Kconfig" -source "board/prodrive/alpr/Kconfig" -source "board/prodrive/p3p440/Kconfig" -source "board/sbc405/Kconfig" source "board/t3corp/Kconfig" source "board/xes/xpedite1000/Kconfig" source "board/xilinx/ml507/Kconfig" source "board/xilinx/ppc405-generic/Kconfig" source "board/xilinx/ppc440-generic/Kconfig" -source "board/zeus/Kconfig" endmenu diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 7a0f0d25d1..77d4040727 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1805,21 +1805,6 @@ ppc405ep_init: bne _pci_66mhz #endif /* CONFIG_TAIHU */ -#if defined(CONFIG_ZEUS) - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - lis r3,0x0000 - addi r3,r3,0x3030 - lis r4,0x8042 - addi r4,r4,0x223e - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 - b 1f -#endif - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ ori r3,r3,PLLMR0_DEFAULT@l /* */ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 6206bee5d3..8c91e722f4 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -44,6 +44,18 @@ struct liodn_id_table { unsigned long reg_offset; }; +struct fman_liodn_id_table { + /* Freescale FMan Device Tree binding was updated for FMan. + * We need to support both new and old compatibles in order not to + * break backward compatibility. + */ + const char *compat[2]; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid); extern void set_liodns(void); extern void fdt_fixup_liodn(void *blob); @@ -54,6 +66,14 @@ extern void fdt_fixup_liodn(void *blob); #define SET_LIODN_BASE_2(idA, idB) \ { .id = { idA, idB }, .num_ids = 2 } +#define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\ + { .compat[0] = name1, \ + .compat[1] = name2, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ { .compat = name, \ .id = { idA }, .num_ids = 1, \ @@ -133,24 +153,37 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) +#ifdef CONFIG_SYS_FMAN_V3 /* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \ - FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ - FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) /* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ - FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) +#else +/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) +/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) +#endif /* * handle both old and new versioned SEC properties: * "fsl,secX.Y" became "fsl,sec-vX.Y" during development @@ -199,7 +232,7 @@ extern void fdt_fixup_liodn(void *blob); extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; extern struct liodn_id_table raide_liodn_tbl[]; -extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; +extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; #ifdef CONFIG_SYS_SRIO extern struct srio_liodn_id_table srio_liodn_tbl[]; extern int srio_liodn_tbl_sz; diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index d57bb55692..87415b123f 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -65,11 +65,13 @@ #define CONFIG_FSL_TRUST_ARCH_v1 #endif -#if defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) /* The key used for verification of next level images * is picked up from an Extension Table which has * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC + * in boot ROM of the SoC. + * The feature is only applicable in case of NOR boot and is + * not applicable in case of RAMBOOT (NAND, SD, SPI). */ #define CONFIG_FSL_ISBC_KEY_EXT #endif diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 4090975bf5..2527ef88de 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -106,12 +106,6 @@ struct arch_global_data { #ifdef CONFIG_SYS_FPGA_COUNT unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; #endif -#if defined(CONFIG_WD_MAX_RATE) - unsigned long long wdt_last; /* trace watch-dog triggering rate */ -#endif -#if defined(CONFIG_LWMON5) - unsigned long kbd_status; -#endif }; #include <asm-generic/global_data.h> diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 500b665cb9..e987f38e3a 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -23,3 +23,16 @@ config SYS_CONFIG_NAME default "aristainetos2" endif + +if TARGET_ARISTAINETOS2B + +config SYS_BOARD + default "aristainetos" + +config SYS_SOC + default "mx6" + +config SYS_CONFIG_NAME + default "aristainetos2b" + +endif diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c index d6a761430d..b8fed2e3fd 100644 --- a/board/aristainetos/aristainetos-v1.c +++ b/board/aristainetos/aristainetos-v1.c @@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(ENET_50MHZ); + ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c index 7a44031043..49dbd2e497 100644 --- a/board/aristainetos/aristainetos-v2.c +++ b/board/aristainetos/aristainetos-v2.c @@ -42,8 +42,16 @@ #define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define ECSPI1_CS0 IMX_GPIO_NR(4, 9) /* 4.3 display controller */ -#define ECSPI4_CS0 IMX_GPIO_NR(3, 29) +#if (CONFIG_SYS_BOARD_VERSION == 2) + /* 4.3 display controller */ + #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) + #define ECSPI4_CS0 IMX_GPIO_NR(3, 29) +#elif (CONFIG_SYS_BOARD_VERSION == 3) + #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */ + /* 4.3 display controller */ + #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) +#endif + #define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) #define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) @@ -103,7 +111,11 @@ iomux_v3_cfg_t const gpio_pads[] = { /* LED yellow */ MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* LED red */ +#if (CONFIG_SYS_BOARD_VERSION == 2) MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +#elif (CONFIG_SYS_BOARD_VERSION == 3) + MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +#endif /* LED green */ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* LED blue */ @@ -170,7 +182,12 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), +#if (CONFIG_SYS_BOARD_VERSION == 2) MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), +#elif (CONFIG_SYS_BOARD_VERSION == 3) + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +#endif }; static void setup_iomux_enet(void) @@ -178,6 +195,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); } +#if (CONFIG_SYS_BOARD_VERSION == 2) iomux_v3_cfg_t const ecspi4_pads[] = { MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -185,13 +203,13 @@ iomux_v3_cfg_t const ecspi4_pads[] = { MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#endif static iomux_v3_cfg_t const display_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DI0_PIN4__GPIO4_IO20, MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, @@ -221,11 +239,17 @@ static iomux_v3_cfg_t const display_pads[] = { int board_spi_cs_gpio(unsigned bus, unsigned cs) { if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) +#if (CONFIG_SYS_BOARD_VERSION == 2) return IMX_GPIO_NR(5, 2); if (bus == 0 && cs == 0) return IMX_GPIO_NR(4, 9); +#elif (CONFIG_SYS_BOARD_VERSION == 3) + return ECSPI1_CS0; + if (bus == 0 && cs == 1) + return ECSPI1_CS1; +#endif return -1; } @@ -234,15 +258,22 @@ static void setup_spi(void) int i; imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + +#if (CONFIG_SYS_BOARD_VERSION == 2) imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); +#endif + for (i = 0; i < 4; i++) enable_spi_clk(true, i); gpio_direction_output(ECSPI1_CS0, 1); +#if (CONFIG_SYS_BOARD_VERSION == 2) gpio_direction_output(ECSPI4_CS1, 0); - /* set cs0 to high (second device on spi bus #4) */ gpio_direction_output(ECSPI4_CS0, 1); +#elif (CONFIG_SYS_BOARD_VERSION == 3) + gpio_direction_output(ECSPI1_CS1, 1); +#endif } static void setup_iomux_uart(void) @@ -573,6 +604,7 @@ static void setup_board_gpio(void) gpio_direction_output(IMX_GPIO_NR(1, 25), 0); /* switch off Status LEDs */ +#if (CONFIG_SYS_BOARD_VERSION == 2) gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ gpio_direction_output(IMX_GPIO_NR(6, 16), 1); gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ @@ -581,11 +613,21 @@ static void setup_board_gpio(void) gpio_direction_output(IMX_GPIO_NR(5, 4), 1); gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ gpio_direction_output(IMX_GPIO_NR(2, 29), 1); +#elif (CONFIG_SYS_BOARD_VERSION == 3) + gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ + gpio_direction_output(IMX_GPIO_NR(6, 16), 0); + gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */ + gpio_direction_output(IMX_GPIO_NR(5, 0), 0); + gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ + gpio_direction_output(IMX_GPIO_NR(2, 29), 0); +#endif } static void setup_board_spi(void) { - /* enable spi bus #2 SS drivers */ + /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ gpio_direction_output(IMX_GPIO_NR(6, 6), 1); } @@ -620,8 +662,9 @@ int board_late_init(void) /* if we have the lg panel, we can initialze it now */ if (panel) if (!strcmp(panel, displays[1].mode.name)) - lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0); + lg4573_spi_startup(CONFIG_LG4573_BUS, + CONFIG_LG4573_CS, + 10000000, SPI_MODE_0); return 0; } - diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 0c39ee6cf1..e95ec81760 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -60,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR; #if (CONFIG_SYS_BOARD_VERSION == 1) #include "./aristainetos-v1.c" -#elif (CONFIG_SYS_BOARD_VERSION == 2) +#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) #include "./aristainetos-v2.c" #endif @@ -163,18 +163,18 @@ struct display_info_t const displays[] = { .refresh = 60, .xres = 800, .yres = 480, - .pixclock = 33246, + .pixclock = 30066, .left_margin = 88, .right_margin = 88, - .upper_margin = 10, - .lower_margin = 10, + .upper_margin = 20, + .lower_margin = 20, .hsync_len = 80, - .vsync_len = 25, - .sync = 0, + .vsync_len = 5, + .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED } } -#if (CONFIG_SYS_BOARD_VERSION == 2) +#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) , { .bus = -1, .addr = 0, @@ -183,7 +183,7 @@ struct display_info_t const displays[] = { .enable = enable_spi_display, .mode = { .name = "lg4573", - .refresh = 60, + .refresh = 57, .xres = 480, .yres = 800, .pixclock = 37037, @@ -214,9 +214,6 @@ iomux_v3_cfg_t nfc_pads[] = { MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c index b2eab766c5..0384a26e92 100644 --- a/board/barco/platinum/platinum_picon.c +++ b/board/barco/platinum/platinum_picon.c @@ -148,7 +148,7 @@ int platinum_setup_enet(void) /* set GPIO_16 as ENET_REF_CLK_OUT */ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } int platinum_setup_i2c(void) diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c index f421c2108c..098542fbd2 100644 --- a/board/barco/platinum/spl_picon.c +++ b/board/barco/platinum/spl_picon.c @@ -137,6 +137,7 @@ static void spl_dram_init(int width) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c index 26fe26ba2b..a3a42551b0 100644 --- a/board/barco/platinum/spl_titanium.c +++ b/board/barco/platinum/spl_titanium.c @@ -140,6 +140,7 @@ static void spl_dram_init(int width) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); diff --git a/board/boundary/nitrogen6x/MAINTAINERS b/board/boundary/nitrogen6x/MAINTAINERS index cb06c03691..1602d650e3 100644 --- a/board/boundary/nitrogen6x/MAINTAINERS +++ b/board/boundary/nitrogen6x/MAINTAINERS @@ -1,5 +1,5 @@ NITROGEN6X BOARD -M: Eric Nelson <eric.nelson@boundarydevices.com> +M: Troy Kisky <troy.kisky@boundarydevices.com> S: Maintained F: board/boundary/nitrogen6x/ F: include/configs/nitrogen6x.h diff --git a/board/cmi/Kconfig b/board/cmi/Kconfig deleted file mode 100644 index 6efe6b1cb7..0000000000 --- a/board/cmi/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CMI_MPC5XX - -config SYS_BOARD - default "cmi" - -config SYS_CONFIG_NAME - default "cmi_mpc5xx" - -endif diff --git a/board/cmi/MAINTAINERS b/board/cmi/MAINTAINERS deleted file mode 100644 index 60701bfd99..0000000000 --- a/board/cmi/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CMI BOARD -#M: - -S: Maintained -F: board/cmi/ -F: include/configs/cmi_mpc5xx.h -F: configs/cmi_mpc5xx_defconfig diff --git a/board/cmi/Makefile b/board/cmi/Makefile deleted file mode 100644 index cd3bb0db21..0000000000 --- a/board/cmi/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := flash.o cmi.o diff --git a/board/cmi/README b/board/cmi/README deleted file mode 100644 index 0edd50ad22..0000000000 --- a/board/cmi/README +++ /dev/null @@ -1,84 +0,0 @@ - -Summary: -======== - -This file contains information about the cmi board configuration. -Please see cmi_mpc5xx_config for further details. The cmi board is -a customer specific board but should work with small modifications -on every board which has a MPC5xx and either a 28F128J3A, -28F320J3A or 28F640J3A Intel flash mounted. - -Board Discription: -================== - -* Motorola MPC555 -* RS232 connection -* Intel flash 28F640J3A -* Micron SRAM 1M -* Altera PLD - -Bootstrap: -========== - -In contrast to the usual boot sequence used in U-Boot, on the -cmi board we don't boot from the external flash directly. -Because of we use a 16-bit flash and don't sample a RCW -from the data bus to set the startup buswidth to 16-bit. -Unfortunatly the default width, sampled from the default RCW -is 32-bit. For this reason we burn the proper RCW into the -internal flash shadow location and boot after power-on or -reset from the internal flash and then branch to 0x02000100 -where the U-Boot reset vector handler is located. - -Memory Map: -=========== - -Memory Map after relocation: - - 0x0000 0000 CONFIG_SYS_SDRAM_BASE - : - 0x000F 9FFF - : - : - 0x0100 0000 CONFIG_SYS_IMMR (Internal memory map base adress) - : - 0x0130 7FFF - : - : - 0x0200 0000 CONFIG_SYS_FLASH_BASE - : - 0x027C FFFF - : - : - 0x0300 0000 PLD_BASE - -Flash Partition: - - 0x0200 0000 Block 0 and 1 contain U-Boot except - : environment - : - 0x0201 FFFF - 0x0202 0000 Block 2 contains environment (.ppcenv) - : - 0x0202 FFFF - -See README file for futher information about U-Boot relocation -and partitioning. - -Tested Features: -================ - -* U-Boot commands: go, loads, loadb, all memory features, printenv, - setenv, saveenv, protect, erase, fli, bdi, mtest, reset, version, - coninfo, help (see configuration file for available commands) - -* Blinking led to indicate boot process - -Added or Changed Files: -======================= - -u-boot-0.2.0/board/cmi/* -u-boot-0.2.0/include/configs/cmi_mpc5xx.h - -Regards, -Martin diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c deleted file mode 100644 index 37028c31eb..0000000000 --- a/board/cmi/cmi.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cmi.c - * - * Discription: For generic board specific functions - * - */ - - -#include <common.h> -#include <mpc5xx.h> - -#define SRAM_SIZE 1024000L /* 1M RAM available*/ - -#if defined(__APPLE__) -/* Leading underscore on symbols */ -# define SYM_CHAR "_" -#else /* No leading character on symbols */ -# define SYM_CHAR -#endif - -/* - * Macros to generate global absolutes. - */ -#define GEN_SYMNAME(str) SYM_CHAR #str -#define GEN_VALUE(str) #str -#define GEN_ABS(name, value) \ - asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) - -/* - * Check the board - */ -int checkboard(void) -{ - puts ("Board: ### No HW ID - assuming CMI board\n"); - return (0); -} - -/* - * Get RAM size. - */ -phys_size_t initdram(int board_type) -{ - return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */ -} - -/* - * Absolute environment address for linker file. - */ -GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE); diff --git a/board/cmi/flash.c b/board/cmi/flash.c deleted file mode 100644 index d9986f99cc..0000000000 --- a/board/cmi/flash.c +++ /dev/null @@ -1,501 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: flash.c - * - * Discription: This Driver is for 28F320J3A, 28F640J3A and - * 28F128J3A Intel flashs working in 16 Bit mode. - * They are single bank flashs. - * - * Most of this code is taken from existing u-boot - * source code. - */ - - -#include <common.h> -#include <mpc5xx.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#define FLASH_ID_MASK 0xFFFF -#define FLASH_BLOCK_SIZE 0x00010000 -#define FLASH_CMD_READ_ID 0x0090 -#define FLASH_CMD_RESET 0x00ff -#define FLASH_CMD_BLOCK_ERASE 0x0020 -#define FLASH_CMD_ERASE_CONFIRM 0x00D0 -#define FLASH_CMD_CLEAR_STATUS 0x0050 -#define FLASH_CMD_SUSPEND_ERASE 0x00B0 -#define FLASH_CMD_WRITE 0x0040 -#define FLASH_CMD_PROTECT 0x0060 -#define FLASH_CMD_PROTECT_SET 0x0001 -#define FLASH_CMD_PROTECT_CLEAR 0x00D0 -#define FLASH_STATUS_DONE 0x0080 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* - * Local function prototypes - */ -static ulong flash_get_size (vu_short *addr, flash_info_t *info); -static int write_short (flash_info_t *info, ulong dest, ushort data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/* - * Initialize flash - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ -#if 1 - debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM); -#endif - size_b0 = flash_get_size((vu_short *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0: " - "ID 0x%lx, Size = 0x%08lx = %ld MB\n", - flash_info[0].flash_id, - size_b0, size_b0<<20); - } - - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - flash_info[0].size = size_b0; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - return size_b0; -} - -/* - * Compute start adress of each sector (block) - */ - -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * FLASH_BLOCK_SIZE; - } - return; - - default: - printf ("Don't know sector offsets for flash type 0x%lx\n", - info->flash_id); - return; - } -} - -/* - * Print flash information - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("Fujitsu "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_MT: printf ("MT "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: printf ("28F320J3A (32Mbit) 16-Bit\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64Mbit) 16-Bit\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128Mbit) 16-Bit\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size >= (1 << 20)) { - i = 20; - } else { - i = 10; - } - printf (" Size: %ld %cB in %d Sectors\n", - info->size >> i, - (i == 20) ? 'M' : 'k', - info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * Get size of flash in bytes. - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - vu_short value; - - /* Read Manufacturer ID */ - addr[0] = FLASH_CMD_READ_ID; - value = addr[0]; - - switch (value) { - case (AMD_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_FUJ; - break; - case (SST_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_SST; - break; - case (STM_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_STM; - break; - case (INTEL_MANUFACT & FLASH_ID_MASK): - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (INTEL_ID_28F320J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 32 MBit */ - - case (INTEL_ID_28F640J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 64 MBit */ - - case (INTEL_ID_28F128J3A & FLASH_ID_MASK): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 128 MBit */ - - default: - info->flash_id = FLASH_UNKNOWN; - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = FLASH_CMD_RESET; /* restore read mode */ - - return (info->size); -} - - -/* - * Erase unprotected sectors - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) { - printf ("Can erase only Intel flash types - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *)(info->start[sect]); - unsigned long status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - -#ifdef DEBUG - printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]); -#endif - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_BLOCK_ERASE; - *addr = FLASH_CMD_ERASE_CONFIRM; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Flash erase timeout at address %lx\n", info->start[sect]); - *addr = FLASH_CMD_SUSPEND_ERASE; - *addr = FLASH_CMD_RESET; - return 1; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - *addr = FLASH_CMD_RESET; - } - } - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int i, rc; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start byte - */ - - if (addr - wp) { - data = 0; - data = (data << 8) | *src++; - --cnt; - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - - while (cnt >= 2) { - data = 0; - for (i=0; i<2; ++i) { - data = (data << 8) | *src++; - } - - if ((rc = write_short(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_short(info, wp, data)); - -} - -/* - * Write 16 bit (short) to flash - */ - -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if (!(info->flash_id & FLASH_VENDMASK)) { - return 4; - } - *addr = FLASH_CMD_ERASE_CONFIRM; - *addr = FLASH_CMD_WRITE; - - *((vu_short *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - } - - /* data polling for D7 */ - start = get_timer (0); - - /* wait for error or finish */ - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - - *addr = FLASH_CMD_RESET; - return (0); -} - -/* - * Protects a flash sector - */ - -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - vu_short *addr = (vu_short*)(info->start[sector]); - ulong start; - - *addr = FLASH_CMD_CLEAR_STATUS; - *addr = FLASH_CMD_PROTECT; - - if(prot) { - *addr = FLASH_CMD_PROTECT_SET; - } else { - *addr = FLASH_CMD_PROTECT_CLEAR; - } - - /* wait for error or finish */ - start = get_timer (0); - while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Flash protect timeout at address %lx\n", info->start[sector]); - addr[0] = FLASH_CMD_RESET; - return (1); - } - } - /* Set software protect flag */ - info->protect[sector] = prot; - *addr = FLASH_CMD_RESET; - return (0); -} diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index e85c8aba45..e3db9d5b9b 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -14,6 +14,7 @@ #include <miiphy.h> #include <netdev.h> #include <errno.h> +#include <usb.h> #include <fdt_support.h> #include <sata.h> #include <splash.h> @@ -330,6 +331,11 @@ static int cm_fx6_setup_usb_otg(void) return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0); } +int board_usb_phy_mode(int port) +{ + return USB_INIT_HOST; +} + int board_ehci_hcd_init(int port) { int ret; @@ -620,6 +626,13 @@ int checkboard(void) return 0; } +int misc_init_r(void) +{ + cl_print_pcb_info(); + + return 0; +} + void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 7de6460ca0..574891e5ec 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -27,6 +27,10 @@ #include <power/pfuze100_pmic.h> #include <linux/fb.h> #include <ipu_pixfmt.h> +#include <malloc.h> +#include <miiphy.h> +#include <netdev.h> +#include <micrel.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +47,11 @@ DECLARE_GLOBAL_DATA_PTR; #define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9) + +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -98,6 +107,51 @@ static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static iomux_v3_cfg_t enet_pads_ksz9031[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t enet_pads_final_ksz9031[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t enet_pads_ar8035[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) struct i2c_pads_info i2c_pad_info1 = { .scl = { @@ -169,6 +223,159 @@ int power_init_board(void) return 0; } + +int board_eth_init(bd_t *bis) +{ + struct phy_device *phydev; + struct mii_dev *bus; + unsigned short id1, id2; + int ret; + + iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 | + MUX_PAD_CTRL(NO_PAD_CTRL); + + /* check whether KSZ9031 or AR8035 has to be configured */ + imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035, + ARRAY_SIZE(enet_pads_ar8035)); + imx_iomux_v3_setup_pad(enet_reset); + + /* phy reset */ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + udelay(2000); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + udelay(500); + + bus = fec_get_miibus(IMX_FEC_BASE, -1); + if (!bus) + return -EINVAL; + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("Error: phy device not found.\n"); + ret = -ENODEV; + goto free_bus; + } + + /* get the PHY id */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* re-configure for Micrel KSZ9031 */ + printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n", + phydev->addr); + + /* phy reset: gpio3-23 */ + gpio_set_value(IMX_GPIO_NR(3, 23), 0); + gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2)); + gpio_set_value(IMX_GPIO_NR(6, 25), 1); + gpio_set_value(IMX_GPIO_NR(6, 27), 1); + gpio_set_value(IMX_GPIO_NR(6, 28), 1); + gpio_set_value(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031, + ARRAY_SIZE(enet_pads_ksz9031)); + gpio_set_value(IMX_GPIO_NR(6, 24), 1); + udelay(500); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031, + ARRAY_SIZE(enet_pads_final_ksz9031)); + } else if ((id1 == 0x004d) && (id2 == 0xd072)) { + /* configure Atheros AR8035 - actually nothing to do */ + printf("configure Atheros AR8035 Ethernet Phy at address %d\n", + phydev->addr); + } else { + printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2); + ret = -EINVAL; + goto free_phydev; + } + + ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); + if (ret) + goto free_phydev; + + return 0; + +free_phydev: + free(phydev); +free_bus: + free(bus); + return ret; +} + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short id1, id2; + unsigned short val; + + /* check whether KSZ9031 or AR8035 has to be configured */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* finalize phy configuration for Micrel KSZ9031 */ + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); + + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG); + + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF); + + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF); + + /* fix KSZ9031 link up issue */ + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80); + } + + if ((id1 == 0x004d) && (id2 == 0xd072)) { + /* enable AR8035 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16); + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7); + val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA); + val &= 0xfe63; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + /* disable hibernation */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40); + } + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} static void setup_iomux_uart(void) { diff --git a/board/csb272/Kconfig b/board/csb272/Kconfig deleted file mode 100644 index eed04f0431..0000000000 --- a/board/csb272/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CSB272 - -config SYS_BOARD - default "csb272" - -config SYS_CONFIG_NAME - default "csb272" - -endif diff --git a/board/csb272/MAINTAINERS b/board/csb272/MAINTAINERS deleted file mode 100644 index 4bc95eaeb8..0000000000 --- a/board/csb272/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CSB272 BOARD -M: Tolunay Orkun <torkun@nextio.com> -S: Maintained -F: board/csb272/ -F: include/configs/csb272.h -F: configs/csb272_defconfig diff --git a/board/csb272/Makefile b/board/csb272/Makefile deleted file mode 100644 index 36ec9b6f4d..0000000000 --- a/board/csb272/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = csb272.o -obj-y += init.o diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c deleted file mode 100644 index dc2c9503e6..0000000000 --- a/board/csb272/csb272.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <i2c.h> -#include <miiphy.h> -#include <asm/ppc4xx-emac.h> - -void sdram_init(void); - -/* - * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator - * - * CLKA output => Epson LCD Controller - * CLKB output => Not Connected - * CLKC output => Ethernet - * CLKD output => UART external clock - * - * Note: these values are obtained from device after init by micromonitor -*/ -uchar pll_fs6377_regs[16] = { - 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80, - 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 }; - -/* - * pll_init: Initialize AMIS IC FS6377-01 PLL - * - * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock - * - */ -int pll_init(void) -{ - i2c_set_bus_num(0); - - return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1, - (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs)); -} - -/* - * board_early_init_f: do early board initialization - * - */ -int board_early_init_f(void) -{ - /* initialize PLL so UART, LCD, Ethernet clocked at correctly */ - (void) get_clocks(); - pll_init(); - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ - - return 0; /* success */ -} - -/* - * checkboard: identify/verify the board we are running - * - * Remark: we just assume it is correct board here! - * - */ -int checkboard(void) -{ - printf("BOARD: Cogent CSB272\n"); - - return 0; /* success */ -} - -/* - * initram: Determine the size of mounted DRAM - * - * Size is determined by reading SDRAM configuration registers as - * configured by initialization code - * - */ -phys_size_t initdram (int board_type) -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in arch/powerpc/cpu/ppc4xx - */ - sdram_init(); - - tot_size = 0; - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} - -/* - * last_stage_init: final configurations (such as PHY etc) - * - */ -int last_stage_init(void) -{ - /* initialize the PHY */ - miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); - - /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); - - /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); - - - return 0; /* success */ -} diff --git a/board/csb272/init.S b/board/csb272/init.S deleted file mode 100644 index bf1d98680d..0000000000 --- a/board/csb272/init.S +++ /dev/null @@ -1,196 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -#include <config.h> -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#define LI32(reg,val) \ - addis reg,0,val@h;\ - ori reg,reg,val@l - -#define WDCR_EBC(reg,val) \ - addi r4,0,reg;\ - mtdcr EBC0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr EBC0_CFGDATA,r4 - -#define WDCR_SDRAM(reg,val) \ - addi r4,0,reg;\ - mtdcr SDRAM0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr SDRAM0_CFGDATA,r4 - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * SETUP CPC0_CR0 - *******************************************************************/ - LI32(r4, 0x007000c0) - mtdcr CPC0_CR0, r4 - - /******************************************************************** - * Setup CPC0_CR1: Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, CPC0_CR1 - ori r4, r4, 0x4000 - mtdcr CPC0_CR1, r4 - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - WDCR_EBC(EBC0_CFG, 0xd84c0000) - /******************************************************************** - * Memory Bank 0 (Intel 28F128J3 Flash) initialization - *******************************************************************/ - /*WDCR_EBC(PB1AP, 0x02869200)*/ - WDCR_EBC(PB1AP, 0x07869200) - WDCR_EBC(PB0CR, 0xfe0bc000) - /******************************************************************** - * Memory Bank 1 (Holtek HT6542B PS/2) initialization - *******************************************************************/ - WDCR_EBC(PB1AP, 0x1f869200) - WDCR_EBC(PB1CR, 0xf0818000) - /******************************************************************** - * Memory Bank 2 (Epson S1D13506) initialization - *******************************************************************/ - WDCR_EBC(PB2AP, 0x05860300) - WDCR_EBC(PB2CR, 0xf045a000) - /******************************************************************** - * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization - *******************************************************************/ - WDCR_EBC(PB3AP, 0x0387d200) - WDCR_EBC(PB3CR, 0xf021c000) - /******************************************************************** - * Memory Bank 4-7 (Unused) initialization - *******************************************************************/ - WDCR_EBC(PB4AP, 0) - WDCR_EBC(PB4CR, 0) - WDCR_EBC(PB5AP, 0) - WDCR_EBC(PB5CR, 0) - WDCR_EBC(PB6AP, 0) - WDCR_EBC(PB6CR, 0) - WDCR_EBC(PB7AP, 0) - WDCR_EBC(PB7CR, 0) - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - - /* - * Disable memory controller to allow - * values to be changed. - */ - WDCR_SDRAM(SDRAM0_CFG, 0x00000000) - - /* - * Configure Memory Banks - */ - WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) - WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) - - /* - * Set up SDTR1 (SDRAM Timing Register) - */ - WDCR_SDRAM(SDRAM0_TR, 0x00854009) - - /* - * Set RTR (Refresh Timing Register) - */ - WDCR_SDRAM(SDRAM0_RTR, 0x10000000) - /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait >200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - WDCR_SDRAM(SDRAM0_CFG,0x80800000) - -..sdri_done: - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/board/csb472/Kconfig b/board/csb472/Kconfig deleted file mode 100644 index 53b1e7ad9a..0000000000 --- a/board/csb472/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CSB472 - -config SYS_BOARD - default "csb472" - -config SYS_CONFIG_NAME - default "csb472" - -endif diff --git a/board/csb472/MAINTAINERS b/board/csb472/MAINTAINERS deleted file mode 100644 index 25041ed824..0000000000 --- a/board/csb472/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CSB472 BOARD -M: Tolunay Orkun <torkun@nextio.com> -S: Maintained -F: board/csb472/ -F: include/configs/csb472.h -F: configs/csb472_defconfig diff --git a/board/csb472/Makefile b/board/csb472/Makefile deleted file mode 100644 index 5f7e8b533e..0000000000 --- a/board/csb472/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = csb472.o -obj-y += init.o diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c deleted file mode 100644 index b1de18ce51..0000000000 --- a/board/csb472/csb472.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <i2c.h> -#include <miiphy.h> -#include <asm/ppc4xx-emac.h> - -void sdram_init(void); - -/* - * board_early_init_f: do early board initialization - * - */ -int board_early_init_f(void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ - - return 0; /* success */ -} - -/* - * checkboard: identify/verify the board we are running - * - * Remark: we just assume it is correct board here! - * - */ -int checkboard(void) -{ - printf("BOARD: Cogent CSB472\n"); - - return 0; /* success */ -} - -/* - * initram: Determine the size of mounted DRAM - * - * Size is determined by reading SDRAM configuration registers as - * configured by initialization code - * - */ -phys_size_t initdram (int board_type) -{ - ulong tot_size; - ulong bank_size; - ulong tmp; - - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in arch/powerpc/cpu/ppc4xx - */ - sdram_init(); - - tot_size = 0; - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - tmp = mfdcr (SDRAM0_CFGDATA); - if (tmp & 0x00000001) { - bank_size = 0x00400000 << ((tmp >> 17) & 0x7); - tot_size += bank_size; - } - - return tot_size; -} - -/* - * last_stage_init: final configurations (such as PHY etc) - * - */ -int last_stage_init(void) -{ - /* initialize the PHY */ - miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); - - /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); - - /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); - - return 0; /* success */ -} diff --git a/board/csb472/init.S b/board/csb472/init.S deleted file mode 100644 index 7383a708b0..0000000000 --- a/board/csb472/init.S +++ /dev/null @@ -1,192 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -#include <config.h> -#include <asm/ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - -#define LI32(reg,val) \ - addis reg,0,val@h;\ - ori reg,reg,val@l - -#define WDCR_EBC(reg,val) \ - addi r4,0,reg;\ - mtdcr EBC0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr EBC0_CFGDATA,r4 - -#define WDCR_SDRAM(reg,val) \ - addi r4,0,reg;\ - mtdcr SDRAM0_CFGADDR,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr SDRAM0_CFGDATA,r4 - -/****************************************************************************** - * Function: ext_bus_cntlr_init - * - * Description: Configures EBC Controller and a few basic chip selects. - * - * CS0 is setup to get the Boot Flash out of the addresss range - * so that we may setup a stack. CS7 is setup so that we can - * access and reset the hardware watchdog. - * - * IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl ext_bus_cntlr_init - .type ext_bus_cntlr_init, @function -ext_bus_cntlr_init: - mflr r0 - /******************************************************************** - * Prefetch entire ext_bus_cntrl_init function into the icache. - * This is necessary because we are going to change the same CS we - * are executing from. Otherwise a CPU lockup may occur. - *******************************************************************/ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - - /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) - mtctr r4 -..ebcloop: - icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ - bdnz ..ebcloop /* continue for $CTR cache lines */ - - /******************************************************************** - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. - *******************************************************************/ - addis r3, 0, 0x0 - ori r3, r3, 0xA000 /* wait 200us from reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /******************************************************************** - * SETUP CPC0_CR0 - *******************************************************************/ - LI32(r4, 0x00c01030) - mtdcr CPC0_CR0, r4 - - /******************************************************************** - * Setup CPC0_CR1: Change PCIINT signal to PerWE - *******************************************************************/ - mfdcr r4, CPC0_CR1 - ori r4, r4, 0x4000 - mtdcr CPC0_CR1, r4 - - /******************************************************************** - * Setup External Bus Controller (EBC). - *******************************************************************/ - WDCR_EBC(EBC0_CFG, 0xd84c0000) - /******************************************************************** - * Memory Bank 0 (Intel 28F640J3 Flash) initialization - *******************************************************************/ - /*WDCR_EBC(PB1AP, 0x03055200)*/ - /*WDCR_EBC(PB1AP, 0x04055200)*/ - WDCR_EBC(PB1AP, 0x08055200) - WDCR_EBC(PB0CR, 0xff87a000) - /******************************************************************** - * Memory Bank 3 (Xilinx XC95144 CPLD) initialization - *******************************************************************/ - /*WDCR_EBC(PB3AP, 0x07869200)*/ - WDCR_EBC(PB3AP, 0x04055200) - WDCR_EBC(PB3CR, 0xf081c000) - /******************************************************************** - * Memory Bank 1,2,4-7 (Unused) initialization - *******************************************************************/ - WDCR_EBC(PB1AP, 0) - WDCR_EBC(PB1CR, 0) - WDCR_EBC(PB2AP, 0) - WDCR_EBC(PB2CR, 0) - WDCR_EBC(PB4AP, 0) - WDCR_EBC(PB4CR, 0) - WDCR_EBC(PB5AP, 0) - WDCR_EBC(PB5CR, 0) - WDCR_EBC(PB6AP, 0) - WDCR_EBC(PB6CR, 0) - WDCR_EBC(PB7AP, 0) - WDCR_EBC(PB7CR, 0) - - /* We are all done */ - mtlr r0 /* Restore link register */ - blr /* Return to calling function */ -.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init -/* end ext_bus_cntlr_init() */ - -/****************************************************************************** - * Function: sdram_init - * - * Description: Configures SDRAM memory banks. - * - * Notes: Does NOT use the stack. - *****************************************************************************/ - .section ".text" - .align 2 - .globl sdram_init - .type sdram_init, @function -sdram_init: - - /* - * Disable memory controller to allow - * values to be changed. - */ - WDCR_SDRAM(SDRAM0_CFG, 0x00000000) - - /* - * Configure Memory Banks - */ - WDCR_SDRAM(SDRAM0_B0CR, 0x00062001) - WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) - WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) - - /* - * Set up SDTR1 (SDRAM Timing Register) - */ - WDCR_SDRAM(SDRAM0_TR, 0x00854009) - - /* - * Set RTR (Refresh Timing Register) - */ - WDCR_SDRAM(SDRAM0_RTR, 0x10000000) - /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ - - /******************************************************************** - * Delay to ensure 200usec have elapsed since reset. Assume worst - * case that the core is running 200Mhz: - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *******************************************************************/ - addis r3, 0, 0x0000 - ori r3, r3, 0xA000 /* Wait >200us from reset */ - mtctr r3 -..spinlp2: - bdnz ..spinlp2 /* spin loop */ - - /******************************************************************** - * Set memory controller options reg, MCOPT1. - *******************************************************************/ - WDCR_SDRAM(SDRAM0_CFG,0x80800000) - -..sdri_done: - blr /* Return to calling function */ -.Lfe1: .size sdram_init,.Lfe1-sdram_init -/* end sdram_init() */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d6ef6ba10d..655fc644fe 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -12,12 +12,14 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_sec.h> #include <spl.h> +#include <fsl_devdis.h> #include "../common/sleep.h" #include "../common/qixis.h" @@ -280,7 +282,8 @@ int board_early_init_f(void) unsigned int major; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); #endif #ifdef CONFIG_FSL_IFC @@ -530,6 +533,9 @@ int misc_init_r(void) else if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif #ifdef CONFIG_FSL_CAAM return sec_init(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b7458a9e99..228dbf81bb 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> #include <fsl_esdhc.h> @@ -21,6 +22,7 @@ #include <fsl_mdio.h> #include <tsec.h> #include <fsl_sec.h> +#include <fsl_devdis.h> #include <spl.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE @@ -481,7 +483,8 @@ int board_early_init_f(void) unsigned int major; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif @@ -651,6 +654,9 @@ int board_init(void) #if defined(CONFIG_MISC_INIT_R) int misc_init_r(void) { +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif #ifndef CONFIG_QSPI_BOOT config_board_mux(); #endif diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS index 572c4b8446..90b4e4715d 100644 --- a/board/freescale/ls2085a/MAINTAINERS +++ b/board/freescale/ls2085a/MAINTAINERS @@ -4,6 +4,5 @@ S: Maintained F: board/freescale/ls2085a/ F: include/configs/ls2085a_emu.h F: configs/ls2085a_emu_defconfig -F: configs/ls2085a_emu_D4_defconfig F: include/configs/ls2085a_simu.h F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README index 11b2e79945..e4a6f69bfc 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2085aqds/README @@ -146,3 +146,84 @@ below: earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m hugepages=16 mem=2048M' + +X-QSGMII-16PORT riser card +---------------------------- +The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes +interfaces implemented in PCIe form factor board. +It supports followings + - Card can operate with up to 4 QSGMII lane simultaneously + - Card can operate with up to 8 SGMII lane simultaneously + +Supported card configuration + - CSEL : ON ON ON ON + - MSEL1 : ON ON ON ON OFF OFF OFF OFF + - MSEL2 : OFF OFF OFF OFF ON ON ON ON + +To enable this card: modify hwconfig to add "xqsgmii" variable. + +Supported PHY addresses during SGMII: +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe + +Mapping DPMACx to PHY during QSGMII +DPMAC1 -> PHY1-P0 +DPMAC2 -> PHY2-P0 +DPMAC3 -> PHY3-P0 +DPMAC4 -> PHY4-P0 +DPMAC5 -> PHY3-P2 +DPMAC6 -> PHY1-P2 +DPMAC7 -> PHY4-P1 +DPMAC8 -> PHY2-P2 +DPMAC9 -> PHY1-P0 +DPMAC10 -> PHY2-P0 +DPMAC11 -> PHY3-P0 +DPMAC12 -> PHY4-P0 +DPMAC13 -> PHY3-P2 +DPMAC14 -> PHY1-P2 +DPMAC15 -> PHY4-P1 +DPMAC16 -> PHY2-P2 + + +Supported PHY address during QSGMII +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + +Mapping DPMACx to PHY during QSGMII +DPMAC1 -> PHY1-P3 +DPMAC2 -> PHY1-P2 +DPMAC3 -> PHY1-P1 +DPMAC4 -> PHY1-P0 +DPMAC5 -> PHY2-P3 +DPMAC6 -> PHY2-P2 +DPMAC7 -> PHY2-P1 +DPMAC8 -> PHY2-P0 +DPMAC9 -> PHY3-P0 +DPMAC10 -> PHY3-P1 +DPMAC11 -> PHY3-P2 +DPMAC12 -> PHY3-P3 +DPMAC13 -> PHY4-P0 +DPMAC14 -> PHY4-P1 +DPMAC15 -> PHY4-P2 +DPMAC16 -> PHY4-P3 + diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c index 1f8a31ff00..007b433d81 100644 --- a/board/freescale/ls2085aqds/eth.c +++ b/board/freescale/ls2085aqds/eth.c @@ -9,9 +9,12 @@ #include <asm/io.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <hwconfig.h> #include <fsl_mdio.h> #include <malloc.h> #include <fm_eth.h> +#include <i2c.h> +#include <miiphy.h> #include <fsl-mc/ldpaa_wriop.h> #include "../common/qixis.h" @@ -30,6 +33,10 @@ * maps to something other than a board slot. */ +static u8 lane_to_slot_fsm1[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + static u8 lane_to_slot_fsm2[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; @@ -37,7 +44,19 @@ static u8 lane_to_slot_fsm2[] = { /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs * housed. */ -static int riser_phy_addr[] = { + +static int xqsgii_riser_phy_addr[] = { + XQSGMII_CARD_PHY1_PORT0_ADDR, + XQSGMII_CARD_PHY2_PORT0_ADDR, + XQSGMII_CARD_PHY3_PORT0_ADDR, + XQSGMII_CARD_PHY4_PORT0_ADDR, + XQSGMII_CARD_PHY3_PORT2_ADDR, + XQSGMII_CARD_PHY1_PORT2_ADDR, + XQSGMII_CARD_PHY4_PORT2_ADDR, + XQSGMII_CARD_PHY2_PORT2_ADDR, +}; + +static int sgmii_riser_phy_addr[] = { SGMII_CARD_PORT1_PHY_ADDR, SGMII_CARD_PORT2_PHY_ADDR, SGMII_CARD_PORT3_PHY_ADDR, @@ -70,6 +89,236 @@ struct ls2085a_qds_mdio { struct mii_dev *realbus; }; +static void sgmii_configure_repeater(int serdes_port) +{ + struct mii_dev *bus; + uint8_t a = 0xf; + int i, j, ret; + int dpmac_id = 0, dpmac, mii_bus = 0; + unsigned short value; + char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"}; + uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60}; + + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + + int *riser_phy_addr = &xqsgii_riser_phy_addr[0]; + + /* Set I2c to Slot 1 */ + i2c_write(0x77, 0, 0, &a, 1); + + for (dpmac = 0; dpmac < 8; dpmac++) { + /* Check the PHY status */ + switch (serdes_port) { + case 1: + mii_bus = 0; + dpmac_id = dpmac + 1; + break; + case 2: + mii_bus = 1; + dpmac_id = dpmac + 9; + a = 0xb; + i2c_write(0x76, 0, 0, &a, 1); + break; + } + + ret = miiphy_set_current_dev(dev[mii_bus]); + if (ret > 0) + goto error; + + bus = mdio_get_current_dev(); + debug("Reading from bus %s\n", bus->name); + + ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, + 3); + if (ret > 0) + goto error; + + mdelay(10); + ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11, + &value); + if (ret > 0) + goto error; + + mdelay(10); + + if ((value & 0xfff) == 0x40f) { + printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id); + continue; + } + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + a = 0x18; + i2c_write(i2c_addr[dpmac], 6, 1, &a, 1); + a = 0x38; + i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + a = 0x4; + i2c_write(i2c_addr[dpmac], 8, 1, &a, 1); + + i2c_write(i2c_addr[dpmac], 0xf, 1, + &ch_a_eq[i], 1); + i2c_write(i2c_addr[dpmac], 0x11, 1, + &ch_a_ctl2[j], 1); + + i2c_write(i2c_addr[dpmac], 0x16, 1, + &ch_b_eq[i], 1); + i2c_write(i2c_addr[dpmac], 0x18, 1, + &ch_b_ctl2[j], 1); + + a = 0x14; + i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1); + a = 0xb5; + i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1); + a = 0x20; + i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + mdelay(100); + ret = miiphy_read(dev[mii_bus], + riser_phy_addr[dpmac], + 0x11, &value); + if (ret > 0) + goto error; + + mdelay(1); + ret = miiphy_read(dev[mii_bus], + riser_phy_addr[dpmac], + 0x11, &value); + if (ret > 0) + goto error; + mdelay(10); + + if ((value & 0xfff) == 0x40f) { + printf("DPMAC %d :PHY is configured ", + dpmac_id); + printf("after setting repeater 0x%x\n", + value); + i = 5; + j = 5; + } else + printf("DPMAC %d :PHY is failed to ", + dpmac_id); + printf("configure the repeater 0x%x\n", + value); + } + } + } +error: + if (ret) + printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id); + return; +} + +static void qsgmii_configure_repeater(int dpmac) +{ + uint8_t a = 0xf; + int i, j; + int i2c_phy_addr = 0; + int phy_addr = 0; + int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; + + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + + const char *dev = "LS2085A_QDS_MDIO0"; + int ret = 0; + unsigned short value; + + /* Set I2c to Slot 1 */ + i2c_write(0x77, 0, 0, &a, 1); + + switch (dpmac) { + case 1: + case 2: + case 3: + case 4: + i2c_phy_addr = i2c_addr[0]; + phy_addr = 0; + break; + + case 5: + case 6: + case 7: + case 8: + i2c_phy_addr = i2c_addr[1]; + phy_addr = 4; + break; + + case 9: + case 10: + case 11: + case 12: + i2c_phy_addr = i2c_addr[2]; + phy_addr = 8; + break; + + case 13: + case 14: + case 15: + case 16: + i2c_phy_addr = i2c_addr[3]; + phy_addr = 0xc; + break; + } + + /* Check the PHY status */ + ret = miiphy_set_current_dev(dev); + ret = miiphy_write(dev, phy_addr, 0x1f, 3); + mdelay(10); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + mdelay(10); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + mdelay(10); + if ((value & 0xf) == 0xf) { + printf("DPMAC %d :PHY is ..... Configured\n", dpmac); + return; + } + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + a = 0x18; + i2c_write(i2c_phy_addr, 6, 1, &a, 1); + a = 0x38; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + a = 0x4; + i2c_write(i2c_phy_addr, 8, 1, &a, 1); + + i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); + i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); + + i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); + i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); + + a = 0x14; + i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); + a = 0xb5; + i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); + a = 0x20; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + mdelay(100); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + mdelay(1); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + mdelay(10); + if ((value & 0xf) == 0xf) { + printf("DPMAC %d :PHY is ..... Configured\n", + dpmac); + return; + } + } + } +error: + printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac); + return; +} + static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) { return mdio_names[muxval]; @@ -195,14 +444,38 @@ static void initialize_dpmac_to_slot(void) FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + char *env_hwconfig; + env_hwconfig = getenv("hwconfig"); switch (serdes1_prtcl) { + case 0x07: + case 0x09: + case 0x33: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + lane_to_slot_fsm1[0] = EMI1_SLOT1; + lane_to_slot_fsm1[1] = EMI1_SLOT1; + lane_to_slot_fsm1[2] = EMI1_SLOT1; + lane_to_slot_fsm1[3] = EMI1_SLOT1; + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm1[4] = EMI1_SLOT1; + lane_to_slot_fsm1[5] = EMI1_SLOT1; + lane_to_slot_fsm1[6] = EMI1_SLOT1; + lane_to_slot_fsm1[7] = EMI1_SLOT1; + } else { + lane_to_slot_fsm1[4] = EMI1_SLOT2; + lane_to_slot_fsm1[5] = EMI1_SLOT2; + lane_to_slot_fsm1[6] = EMI1_SLOT2; + lane_to_slot_fsm1[7] = EMI1_SLOT2; + } + break; + case 0x2A: - printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; } @@ -210,21 +483,30 @@ static void initialize_dpmac_to_slot(void) switch (serdes2_prtcl) { case 0x07: case 0x08: + case 0x09: case 0x49: - printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); lane_to_slot_fsm2[0] = EMI1_SLOT4; lane_to_slot_fsm2[1] = EMI1_SLOT4; lane_to_slot_fsm2[2] = EMI1_SLOT4; lane_to_slot_fsm2[3] = EMI1_SLOT4; - /* No MDIO physical connection */ - lane_to_slot_fsm2[4] = EMI1_SLOT6; - lane_to_slot_fsm2[5] = EMI1_SLOT6; - lane_to_slot_fsm2[6] = EMI1_SLOT6; - lane_to_slot_fsm2[7] = EMI1_SLOT6; + + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm2[4] = EMI1_SLOT4; + lane_to_slot_fsm2[5] = EMI1_SLOT4; + lane_to_slot_fsm2[6] = EMI1_SLOT4; + lane_to_slot_fsm2[7] = EMI1_SLOT4; + } else { + /* No MDIO physical connection */ + lane_to_slot_fsm2[4] = EMI1_SLOT6; + lane_to_slot_fsm2[5] = EMI1_SLOT6; + lane_to_slot_fsm2[6] = EMI1_SLOT6; + lane_to_slot_fsm2[7] = EMI1_SLOT6; + } break; default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); break; } @@ -242,9 +524,69 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id) FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + int *riser_phy_addr; + char *env_hwconfig = getenv("hwconfig"); + + if (hwconfig_f("xqsgmii", env_hwconfig)) + riser_phy_addr = &xqsgii_riser_phy_addr[0]; + else + riser_phy_addr = &sgmii_riser_phy_addr[0]; + + if (dpmac_id > WRIOP1_DPMAC9) + goto serdes2; + switch (serdes1_prtcl) { + case 0x07: + + lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id); + slot = lane_to_slot_fsm1[lane]; + + switch (++slot) { + case 1: + /* Slot housing a SGMII riser card? */ + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 1]); + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; + bus = mii_dev_for_muxval(EMI1_SLOT1); + wriop_set_mdio(dpmac_id, bus); + dpmac_info[dpmac_id].phydev = phy_connect( + dpmac_info[dpmac_id].bus, + dpmac_info[dpmac_id].phy_addr, + NULL, + dpmac_info[dpmac_id].enet_if); + phy_config(dpmac_info[dpmac_id].phydev); + break; + case 2: + /* Slot housing a SGMII riser card? */ + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 1]); + dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; + bus = mii_dev_for_muxval(EMI1_SLOT2); + wriop_set_mdio(dpmac_id, bus); + dpmac_info[dpmac_id].phydev = phy_connect( + dpmac_info[dpmac_id].bus, + dpmac_info[dpmac_id].phy_addr, + NULL, + dpmac_info[dpmac_id].enet_if); + phy_config(dpmac_info[dpmac_id].phydev); + break; + case 3: + break; + case 4: + break; + case 5: + break; + case 6: + break; + } + break; + default: + printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + break; } +serdes2: switch (serdes2_prtcl) { case 0x07: case 0x08: @@ -285,11 +627,86 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id) } break; default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); break; } } + +void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) +{ + int lane = 0, slot; + struct mii_dev *bus; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) + >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + switch (serdes1_prtcl) { + case 0x33: + switch (dpmac_id) { + case 1: + case 2: + case 3: + case 4: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A); + break; + case 5: + case 6: + case 7: + case 8: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B); + break; + case 9: + case 10: + case 11: + case 12: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C); + break; + case 13: + case 14: + case 15: + case 16: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D); + break; + } + + slot = lane_to_slot_fsm1[lane]; + + switch (++slot) { + case 1: + /* Slot housing a QSGMII riser card? */ + wriop_set_phy_address(dpmac_id, dpmac_id - 1); + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; + bus = mii_dev_for_muxval(EMI1_SLOT1); + wriop_set_mdio(dpmac_id, bus); + dpmac_info[dpmac_id].phydev = phy_connect( + dpmac_info[dpmac_id].bus, + dpmac_info[dpmac_id].phy_addr, + NULL, + dpmac_info[dpmac_id].enet_if); + + phy_config(dpmac_info[dpmac_id].phydev); + break; + case 3: + break; + case 4: + break; + case 5: + break; + case 6: + break; + } + break; + default: + printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } + + qsgmii_configure_repeater(dpmac_id); +} + void ls2085a_handle_phy_interface_xsgmii(int i) { struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; @@ -324,9 +741,20 @@ int board_eth_init(bd_t *bis) { int error; #ifdef CONFIG_FSL_MC_ENET + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) + >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) + >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + struct memac_mdio_info *memac_mdio0_info; struct memac_mdio_info *memac_mdio1_info; unsigned int i; + char *env_hwconfig; + + env_hwconfig = getenv("hwconfig"); initialize_dpmac_to_slot(); @@ -363,6 +791,7 @@ int board_eth_init(bd_t *bis) for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { switch (wriop_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: + ls2085a_handle_phy_interface_qsgmii(i); break; case PHY_INTERFACE_MODE_SGMII: ls2085a_handle_phy_interface_sgmii(i); @@ -372,11 +801,26 @@ int board_eth_init(bd_t *bis) break; default: break; + + if (i == 16) + i = NUM_WRIOP_PORTS; } } error = cpu_eth_init(bis); + + if (hwconfig_f("xqsgmii", env_hwconfig)) { + if (serdes1_prtcl == 0x7) + sgmii_configure_repeater(1); + if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 || + serdes2_prtcl == 0x49) + sgmii_configure_repeater(2); + } #endif error = pci_eth_init(bis); return error; } + +#ifdef CONFIG_FSL_MC_ENET + +#endif diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c index 08906a6255..2315bdb130 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2085aqds/ls2085aqds.c @@ -16,6 +16,7 @@ #include <fsl-mc/fsl_mc.h> #include <environment.h> #include <i2c.h> +#include <rtc.h> #include <asm/arch-fsl-lsch3/soc.h> #include <hwconfig.h> @@ -209,6 +210,7 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + rtc_enable_32khz_output(); return 0; } diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 98602f889e..7c0e90ad0b 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -361,7 +361,7 @@ static void setup_fec(void) * select ENET MAC0 TX clock from PLL */ imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(ENET_125MHZ); + enable_fec_anatop_clock(0, ENET_125MHZ); } setup_iomux_enet(); diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index eb8a8b3826..5644167008 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -824,6 +824,7 @@ static void spl_dram_init(void) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 7c18c90bce..6ba604e707 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -8,7 +8,9 @@ #include <asm/arch/clock.h> #include <asm/arch/iomux.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> @@ -190,6 +192,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { +#ifndef CONFIG_SPL_BUILD int i, ret; /* @@ -234,6 +237,44 @@ int board_mmc_init(bd_t *bis) } return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + /* Boot from USDHC */ + port = (val >> 11) & 0x3; + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif } #ifdef CONFIG_SYS_I2C_MXC @@ -279,7 +320,7 @@ static int setup_fec(void) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } #endif @@ -361,3 +402,126 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdqs0 = 0x00003030, + .dram_sdqs1 = 0x00003030, + .dram_sdqs2 = 0x00003030, + .dram_sdqs3 = 0x00003030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_sdclk_0 = 0x00000028, + .dram_reset = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_odt0 = 0x00000008, + .dram_odt1 = 0x00000008, +}; + +const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = { + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x00080000, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpdgctrl0 = 0x20000000, + .p0_mpdgctrl1 = 0x00000000, + .p0_mprddlctl = 0x4241444a, + .p0_mpwrdlctl = 0x3030312b, + .mpzqlp2ctl = 0x1b4700c7, +}; + +static struct mx6_lpddr2_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .trcd_lp = 2000, + .trppb_lp = 2000, + .trpab_lp = 2250, + .trasmin = 4200, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + + writel(0x00260324, &ccm->cbcmr); +} + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = mem_ddr.width / 32, + .cs_density = 20, + .ncs = 2, + .cs1_mirror = 0, + .walat = 0, + .ralat = 2, + .mif3_mode = 3, + .bi_on = 1, + .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ + .rtt_nom = 0, + .sde_to_rst = 0, /* LPDDR2 does not need this field */ + .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ + .ddr_type = DDR_TYPE_LPDDR2, + }; + mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index d58a79a6b8..b9af7e7b95 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -170,7 +170,7 @@ static int setup_fec(void) reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - return enable_fec_anatop_clock(ENET_125MHZ); + return enable_fec_anatop_clock(0, ENET_125MHZ); } int board_eth_init(bd_t *bis) @@ -566,6 +566,7 @@ static void spl_dram_init(void) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 8f712cb058..c09d84e540 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -19,8 +19,10 @@ #include <common.h> #include <fsl_esdhc.h> #include <i2c.h> +#include <miiphy.h> #include <linux/sizes.h> #include <mmc.h> +#include <netdev.h> #include <usb.h> #include <usb/ehci-fsl.h> @@ -43,6 +45,18 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + #define IOX_SDI IMX_GPIO_NR(5, 10) #define IOX_STCP IMX_GPIO_NR(5, 7) #define IOX_SHCP IMX_GPIO_NR(5, 11) @@ -457,6 +471,98 @@ int board_ehci_hcd_init(int port) } #endif +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, + ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, + ARRAY_SIZE(fec2_pads)); +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); +} + +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -477,6 +583,10 @@ int board_init(void) setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + #ifdef CONFIG_USB_EHCI_MX6 setup_usb(); #endif @@ -598,6 +708,7 @@ static void spl_dram_init(void) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS index 1ffccc4fd3..23480e2d71 100644 --- a/board/freescale/t102xqds/MAINTAINERS +++ b/board/freescale/t102xqds/MAINTAINERS @@ -7,6 +7,6 @@ F: configs/T1024QDS_defconfig F: configs/T1024QDS_NAND_defconfig F: configs/T1024QDS_SDCARD_defconfig F: configs/T1024QDS_SPIFLASH_defconfig -F: configs/T1024QDS_D4_defconfig +F: configs/T1024QDS_DDR4_defconfig F: configs/T1024QDS_SECURE_BOOT_defconfig -F: configs/T1024QDS_D4_SECURE_BOOT_defconfig +F: configs/T1024QDS_DDR4_SECURE_BOOT_defconfig diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg index 1d11a2eed7..f8f72826b1 100644 --- a/board/freescale/t102xrdb/t1023_rcw.cfg +++ b/board/freescale/t102xrdb/t1023_rcw.cfg @@ -1,8 +1,8 @@ #PBL preamble and RCW header for T1023RDB aa55aa55 010e0100 #SerDes Protocol: 0x77 -#Core/DDR: 1400Mhz/1600MT/s with single source clock -0810000e 00000000 00000000 00000000 +#Default Core=1200MHz, DDR=1600MT/s with single source clock +0810000c 00000000 00000000 00000000 3b800003 00000012 e8104000 21000000 00000000 00000000 00000000 00022800 00000130 04020200 00000000 00000006 diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS index 83f6b3ce3a..640538ff61 100644 --- a/board/freescale/t1040qds/MAINTAINERS +++ b/board/freescale/t1040qds/MAINTAINERS @@ -4,7 +4,7 @@ S: Maintained F: board/freescale/t1040qds/ F: include/configs/T1040QDS.h F: configs/T1040QDS_defconfig -F: configs/T1040QDS_D4_defconfig +F: configs/T1040QDS_DDR4_defconfig T1040QDS_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal@freescale.com> diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index d4418e554c..d28eb14f87 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -365,6 +365,7 @@ static void spl_dram_init(int width, int size_mb, int board_model) .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .pd_fast_exit = 1, /* enable precharge power-down fast exit */ + .ddr_type = DDR_TYPE_DDR3, }; /* diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 609edf1e5c..babb0dc0fe 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -12,6 +12,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> +#include <ns16550.h> #include <netdev.h> #include <flash.h> #include <nand.h> @@ -33,6 +35,18 @@ DECLARE_GLOBAL_DATA_PTR; * machine IDs; row it selected based on CPU column is slected based * on hsusb0_data5 pin having a pulldown resistor */ + +static const struct ns16550_platdata omap3logic_serial = { + OMAP34XX_UART1, + 2, + V_NS16550_CLK +}; + +U_BOOT_DEVICE(omap3logic_uart) = { + "serial_omap", + &omap3logic_serial +}; + static struct board_id { char *name; int machine_id; diff --git a/board/lwmon5/Kconfig b/board/lwmon5/Kconfig deleted file mode 100644 index 90566d825b..0000000000 --- a/board/lwmon5/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_LWMON5 - -config SYS_BOARD - default "lwmon5" - -config SYS_CONFIG_NAME - default "lwmon5" - -endif diff --git a/board/lwmon5/MAINTAINERS b/board/lwmon5/MAINTAINERS deleted file mode 100644 index 7402ab6758..0000000000 --- a/board/lwmon5/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -LWMON5 BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/lwmon5/ -F: include/configs/lwmon5.h -F: configs/lcd4_lwmon5_defconfig -F: configs/lwmon5_defconfig diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile deleted file mode 100644 index 02478ca0c8..0000000000 --- a/board/lwmon5/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = lwmon5.o kbd.o sdram.o -extra-y += init.o diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk deleted file mode 100644 index d0348e8024..0000000000 --- a/board/lwmon5/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# lwmon5 (440EPx) -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S deleted file mode 100644 index e5207c2b40..0000000000 --- a/board/lwmon5/init.S +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG) - - /* TLB-entry for the FPGA Chip select 2 */ - tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G) - - /* TLB-entry for the FPGA Chip select 3 */ - tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G) - - /* TLB-entry for the LIME Controller */ - tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G) - tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G) - tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G) - tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I) - - /*TLB-entry PCI registers*/ - tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG) - - /* TLB-entry for peripherals */ - tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c deleted file mode 100644 index 97962daf93..0000000000 --- a/board/lwmon5/kbd.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2001, 2002 - * DENX Software Engineering - * Wolfgang Denk, wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <i2c.h> -#include <command.h> -#include <post.h> -#include <serial.h> -#include <malloc.h> - -#include <linux/types.h> -#include <linux/string.h> /* for strdup */ - -DECLARE_GLOBAL_DATA_PTR; - -static void kbd_init (void); -static int compare_magic (uchar *kbd_data, uchar *str); - -/*--------------------- Local macros and constants --------------------*/ -#define _NOT_USED_ 0xFFFFFFFF - -/*------------------------- dspic io expander -----------------------*/ -#define DSPIC_PON_STATUS_REG 0x80A -#define DSPIC_PON_INV_STATUS_REG 0x80C -#define DSPIC_PON_KEY_REG 0x810 -/*------------------------- Keyboard controller -----------------------*/ -/* command codes */ -#define KEYBD_CMD_READ_KEYS 0x01 -#define KEYBD_CMD_READ_VERSION 0x02 -#define KEYBD_CMD_READ_STATUS 0x03 -#define KEYBD_CMD_RESET_ERRORS 0x10 - -/* status codes */ -#define KEYBD_STATUS_MASK 0x3F -#define KEYBD_STATUS_H_RESET 0x20 -#define KEYBD_STATUS_BROWNOUT 0x10 -#define KEYBD_STATUS_WD_RESET 0x08 -#define KEYBD_STATUS_OVERLOAD 0x04 -#define KEYBD_STATUS_ILLEGAL_WR 0x02 -#define KEYBD_STATUS_ILLEGAL_RD 0x01 - -/* Number of bytes returned from Keyboard Controller */ -#define KEYBD_VERSIONLEN 2 /* version information */ - -/* - * This is different from the "old" lwmon dsPIC kbd controller - * implementation. Now the controller still answers with 9 bytes, - * but the last 3 bytes are always "0x06 0x07 0x08". So we just - * set the length to compare to 6 instead of 9. - */ -#define KEYBD_DATALEN 6 /* normal key scan data */ - -/* maximum number of "magic" key codes that can be assigned */ - -static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; -static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR; - -static uchar *key_match (uchar *); - -#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ - -/*********************************************************************** -F* Function: int board_postclk_init (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: This function is the board_postclk_init() method implementation -Z* for the lwmon board. - * - ***********************************************************************/ -int board_postclk_init (void) -{ - kbd_init(); - - return (0); -} - -static void kbd_init (void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar tmp_data[KEYBD_DATALEN]; - uchar val, errcd; - int i; - - i2c_set_bus_num(0); - - gd->arch.kbd_status = 0; - - /* Forced by PIC. Delays <= 175us loose */ - udelay(1000); - - /* Read initial keyboard error code */ - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &errcd, 1); - /* clear unused bits */ - errcd &= KEYBD_STATUS_MASK; - /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ - errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); - if (errcd) { - gd->arch.kbd_status |= errcd << 8; - } - /* Reset error code and verify */ - val = KEYBD_CMD_RESET_ERRORS; - i2c_write (kbd_addr, 0, 0, &val, 1); - udelay(1000); /* delay NEEDED by keyboard PIC !!! */ - - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &val, 1); - - val &= KEYBD_STATUS_MASK; /* clear unused bits */ - if (val) { /* permanent error, report it */ - gd->arch.kbd_status |= val; - return; - } - - /* - * Read current keyboard state. - * - * After the error reset it may take some time before the - * keyboard PIC picks up a valid keyboard scan - the total - * scan time is approx. 1.6 ms (information by Martin Rajek, - * 28 Sep 2002). We read a couple of times for the keyboard - * to stabilize, using a big enough delay. - * 10 times should be enough. If the data is still changing, - * we use what we get :-( - */ - - memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ - for (i=0; i<10; ++i) { - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { - /* consistent state, done */ - break; - } - /* remeber last state, delay, and retry */ - memcpy (tmp_data, kbd_data, KEYBD_DATALEN); - udelay (5000); - } -} - - -/* Read a register from the dsPIC. */ -int _dspic_read(ushort reg, ushort *data) -{ - uchar buf[sizeof(*data)]; - int rval; - - if (i2c_read(dspic_addr, reg, 2, buf, 2)) - return -1; - - rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data)); - *data = (buf[0] << 8) | buf[1]; - - return rval; -} - - -/*********************************************************************** -F* Function: int misc_init_r (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned, even in the case of a keyboard -P* error. - * -Z* Intention: This function is the misc_init_r() method implementation -Z* for the lwmon board. -Z* The keyboard controller is initialized and the result -Z* of a read copied to the environment variable "keybd". -Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for -Z* this key, and if found display to the LCD will be enabled. -Z* The keys in "keybd" are checked against the magic -Z* keycommands defined in the environment. -Z* See also key_match(). - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int misc_init_r_kbd (void) -{ - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar kbd_init_status = gd->arch.kbd_status >> 8; - uchar kbd_status = gd->arch.kbd_status; - uchar val; - ushort data, inv_data; - char *str; - int i; - - if (kbd_init_status) { - printf ("KEYBD: Error %02X\n", kbd_init_status); - } - if (kbd_status) { /* permanent error, report it */ - printf ("*** Keyboard error code %02X ***\n", kbd_status); - sprintf (keybd_env, "%02X", kbd_status); - setenv ("keybd", keybd_env); - return 0; - } - - /* - * Now we know that we have a working keyboard, so disable - * all output to the LCD except when a key press is detected. - */ - - if ((console_assign (stdout, "serial") < 0) || - (console_assign (stderr, "serial") < 0)) { - printf ("Can't assign serial port as output device\n"); - } - - /* Read Version */ - val = KEYBD_CMD_READ_VERSION; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); - printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); - - /* Read current keyboard state */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - /* read out start key from bse01 received via can */ - _dspic_read(DSPIC_PON_STATUS_REG, &data); - /* check highbyte from status register */ - if (data > 0xFF) { - _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data); - - /* check inverse data */ - if ((data+inv_data) == 0xFFFF) { - /* don't overwrite local key */ - if (kbd_data[1] == 0) { - /* read key value */ - _dspic_read(DSPIC_PON_KEY_REG, &data); - str = (char *)&data; - /* swap bytes */ - kbd_data[1] = str[1]; - kbd_data[2] = str[0]; - printf("CAN received startkey: 0x%X\n", data); - } - } - } - - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - } - - setenv ("keybd", keybd_env); - - str = strdup ((char *)key_match (kbd_data)); /* decode keys */ -#ifdef KEYBD_SET_DEBUGMODE - if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ - if ((console_assign (stdout, "lcd") < 0) || - (console_assign (stderr, "lcd") < 0)) { - printf ("Can't assign LCD display as output device\n"); - } - } -#endif /* KEYBD_SET_DEBUGMODE */ -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - return (0); -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static int compare_magic (uchar *kbd_data, uchar *str) -{ - uchar compare[KEYBD_DATALEN-1]; - char *nxt; - int i; - - /* Don't include modifier byte */ - memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); - - for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { - uchar c; - int k; - - c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); - - if (str == (uchar *)nxt) { /* invalid character */ - break; - } - - /* - * Check if this key matches the input. - * Set matches to zero, so they match only once - * and we can find duplicates or extra keys - */ - for (k = 0; k < sizeof(compare); ++k) { - if (compare[k] == '\0') /* only non-zero entries */ - continue; - if (c == compare[k]) { /* found matching key */ - compare[k] = '\0'; - break; - } - } - if (k == sizeof(compare)) { - return -1; /* unmatched key */ - } - } - - /* - * A full match leaves no keys in the `compare' array, - */ - for (i = 0; i < sizeof(compare); ++i) { - if (compare[i]) - { - return -1; - } - } - - return 0; -} - -/*********************************************************************** -F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* - * -P* Parameters: uchar *kbd_data -P* - The keys to match against our magic definitions -P* -P* Returnvalue: uchar * -P* - != NULL: Pointer to the corresponding command(s) -P* NULL: No magic is about to happen - * -Z* Intention: Check if pressed key(s) match magic sequence, -Z* and return the command string associated with that key(s). -Z* -Z* If no key press was decoded, NULL is returned. -Z* -Z* Note: the first character of the argument will be -Z* overwritten with the "magic charcter code" of the -Z* decoded key(s), or '\0'. -Z* -Z* Note: the string points to static environment data -Z* and must be saved before you call any function that -Z* modifies the environment. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -static uchar *key_match (uchar *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - uchar *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - debug ("### Check magic \"%s\"\n", magic); - if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - - cmd = getenv (cmd_name); - debug ("### Set PREBOOT to $(%s): \"%s\"\n", - cmd_name, cmd ? cmd : "<<NULL>>"); - *kbd_data = *suffix; - return ((uchar *)cmd); - } - } - debug ("### Delete PREBOOT\n"); - *kbd_data = '\0'; - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -/*********************************************************************** -F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, -F* int argc, char * const argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char * const argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: Implement the "kbd" command. -Z* The keyboard status is read. The result is printed on -Z* the console and written into the "keybd" environment -Z* variable. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar val; - int i; - -#if 0 /* Done in kbd_init */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - puts ("Keys:"); - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - printf (" %02x", kbd_data[i]); - } - putc ('\n'); - setenv ("keybd", keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "read keyboard status", - "" -); - -/*----------------------------- Utilities -----------------------------*/ - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar val; - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); -} -#endif diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c deleted file mode 100644 index e9aa0b77de..0000000000 --- a/board/lwmon5/lwmon5.c +++ /dev/null @@ -1,558 +0,0 @@ -/* - * (C) Copyright 2007-2013 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/ppc440.h> -#include <asm/processor.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/io.h> -#include <post.h> -#include <flash.h> -#include <mtd/cfi_flash.h> - -DECLARE_GLOBAL_DATA_PTR; - -static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST; - -ulong flash_get_size(ulong base, int banknum); -int misc_init_r_kbd(void); - -int board_early_init_f(void) -{ - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - /* PLB Write pipelining disabled. Denali Core workaround */ - mtdcr(PLB4A0_ACR, 0xDE000000); - mtdcr(PLB4A1_ACR, 0xDE000000); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ - mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ - mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ - mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ - mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* Trace Pins are disabled. SDR0_PFC0 Register */ - mtsdr(SDR0_PFC0, 0x0); - - /* select Ethernet pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - /* SMII via ZMII */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_6; - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_6; - - /* enable SPI (SCP) */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; - - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - mtsdr(SDR0_PFC4, 0x80000000); - - /* PCI arbiter disabled */ - /* PCI Host Configuration disbaled */ - mfsdr(SDR0_PCI0, reg); - reg = 0; - mtsdr(SDR0_PCI0, 0x00000000 | reg); - - gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); - -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 - /* enable the LSB transmitter */ - gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); - /* enable the CAN transmitter */ - gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); - - reg = 0; /* reuse as counter */ - out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, - in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) - & ~CONFIG_SYS_DSPIC_TEST_MASK); - while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { - udelay(1000); - } - if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { - /* set "boot error" flag */ - out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, - in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | - CONFIG_SYS_DSPIC_TEST_MASK); - } -#endif - - /* - * Reset PHY's: - * The PHY's need a 2nd reset pulse, since the MDIO address is latched - * upon reset, and with the first reset upon powerup, the addresses are - * not latched reliable, since the IRQ line is multiplexed with an - * MDIO address. A 2nd reset at this time will make sure, that the - * correct address is latched. - */ - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); - udelay(1000); - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); - udelay(1000); - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); - - return 0; -} - -/* - * Override weak default with board specific version - */ -phys_addr_t cfi_flash_bank_addr(int bank) -{ - return lwmon5_cfi_flash_bank_addr[bank]; -} - -/* - * Override the weak default mapping function with a board specific one - */ -u32 flash_get_bank_size(int cs, int idx) -{ - return flash_info[idx].size; -} - -int board_early_init_r(void) -{ - u32 val0, val1; - - /* - * lwmon5 is manufactured in 2 different board versions: - * The lwmon5a board has 64MiB NOR flash instead of the - * 128MiB of the original lwmon5. Unfortunately the CFI driver - * will report 2 banks of 64MiB even for the smaller flash - * chip, since the bank is mirrored. To fix this, we bring - * one bank into CFI query mode and read its response. This - * enables us to detect the real number of flash devices/ - * banks which will be used later on by the common CFI driver. - */ - - /* Put bank 0 into CFI command mode and read */ - out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098); - val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP); - val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP); - - /* Reset flash again out of query mode */ - out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0); - - /* When not identical, we have 2 different flash devices/banks */ - if (val0 != val1) - return 0; - - /* - * Now we're sure that we're running on a LWMON5a board with - * only 64MiB NOR flash in one bank: - * - * Set flash base address and bank count for CFI driver probing. - */ - cfi_flash_num_flash_banks = 1; - lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0; - - return 0; -} - -int misc_init_r(void) -{ - u32 pbcr; - int size_val = 0; - u32 reg; -#ifndef CONFIG_LCD4_LWMON5 - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1, sdr0_srst; -#endif - - /* - * FLASH stuff... - */ - - /* Re-do sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - mfebc(PB0CR, pbcr); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(PB0CR, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, - &flash_info[cfi_flash_num_flash_banks - 1]); - - /* Env protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, - &flash_info[cfi_flash_num_flash_banks - 1]); - -#ifndef CONFIG_LCD4_LWMON5 - /* - * USB suff... - */ - - /* Reset USB */ - /* Reset of USB2PHY0 must be active at least 10 us */ - mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); - udelay(2000); - - mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | - SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | - SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); - udelay(2000); - - /* Errata CHIP_6 */ - - /* 1. Set internal PHY configuration */ - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB0, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB0, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /* 2. De-assert internal PHY reset */ - mfsdr(SDR0_SRST1, sdr0_srst); - sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; - mtsdr(SDR0_SRST1, sdr0_srst); - - /* 3. Wait for more than 1 ms */ - udelay(2000); - - /* 4. De-assert USB 2.0 Host main reset */ - mfsdr(SDR0_SRST0, sdr0_srst); - sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; - mtsdr(SDR0_SRST0, sdr0_srst); - udelay(1000); - - /* 5. De-assert reset of OPB2 cores */ - mfsdr(SDR0_SRST1, sdr0_srst); - sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; - sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; - sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; - mtsdr(SDR0_SRST1, sdr0_srst); - udelay(1000); - - /* 6. Set EHCI Configure FLAG */ - - /* 7. Reassert internal PHY reset: */ - mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); - udelay(1000); -#endif - - /* - * Clear resets - */ - mtsdr(SDR0_SRST1, 0x00000000); - mtsdr(SDR0_SRST0, 0x00000000); - -#ifndef CONFIG_LCD4_LWMON5 - printf("USB: Host(int phy) Device(ext phy)\n"); -#endif - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - -#ifndef CONFIG_LCD4_LWMON5 - /* - * Init matrix keyboard - */ - misc_init_r_kbd(); -#endif - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: %s", __stringify(CONFIG_HOSTNAME)); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -void hw_watchdog_reset(void) -{ - int val; -#if defined(CONFIG_WD_MAX_RATE) - unsigned long long ct = get_ticks(); - - /* - * Don't allow watch-dog triggering more frequently than - * the predefined value CONFIG_WD_MAX_RATE [ticks]. - */ - if (ct >= gd->arch.wdt_last) { - if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE) - return; - } else { - /* Time base counter had been reset */ - if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) < - CONFIG_WD_MAX_RATE) - return; - } - gd->arch.wdt_last = get_ticks(); -#endif - - /* - * Toggle watchdog output - */ - val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0; - gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val); -} - -int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - if ((strcmp(argv[1], "on") == 0)) - gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1); - else if ((strcmp(argv[1], "off") == 0)) - gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0); - else - return cmd_usage(cmdtp); - - return 0; -} - -U_BOOT_CMD( - eepromwp, 2, 0, do_eeprom_wp, - "eeprom write protect off/on", - "<on|off> - enable (on) or disable (off) I2C EEPROM write protect" -); - -#if defined(CONFIG_VIDEO) -#include <video_fb.h> -#include <mb862xx.h> - -extern GraphicDevice mb862xx; - -static const gdc_regs init_regs [] = { - { 0x0100, 0x00000f00 }, - { 0x0020, 0x801401df }, - { 0x0024, 0x00000000 }, - { 0x0028, 0x00000000 }, - { 0x002c, 0x00000000 }, - { 0x0110, 0x00000000 }, - { 0x0114, 0x00000000 }, - { 0x0118, 0x01df0280 }, - { 0x0004, 0x031f0000 }, - { 0x0008, 0x027f027f }, - { 0x000c, 0x015f028f }, - { 0x0010, 0x020c0000 }, - { 0x0014, 0x01df01ea }, - { 0x0018, 0x00000000 }, - { 0x001c, 0x01e00280 }, - { 0x0100, 0x80010f00 }, - { 0x0, 0x0 } -}; - -const gdc_regs *board_get_regs(void) -{ - return init_regs; -} - -/* Returns Lime base address */ -unsigned int board_video_init(void) -{ - /* - * Reset Lime controller - */ - gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); - udelay(500); - gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); - - mb862xx.winSizeX = 640; - mb862xx.winSizeY = 480; - mb862xx.gdfBytesPP = 2; - mb862xx.gdfIndex = GDF_15BIT_555RGB; - - return CONFIG_SYS_LIME_BASE_0; -} - -#define DEFAULT_BRIGHTNESS 0x64 - -static void board_backlight_brightness(int brightness) -{ - if (brightness > 0) { - /* pwm duty, lamp on */ - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness); - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701); - } else { - /* lamp off */ - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00); - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00); - } -} - -void board_backlight_switch(int flag) -{ - char * param; - int rc; - - if (flag) { - param = getenv("brightness"); - rc = param ? simple_strtol(param, NULL, 10) : -1; - if (rc < 0) - rc = DEFAULT_BRIGHTNESS; - } else { - rc = 0; - } - board_backlight_brightness(rc); -} - -#if defined(CONFIG_CONSOLE_EXTRA_INFO) -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str(int line_number, char *info) -{ - if (line_number == 1) - strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); - else - info [0] = '\0'; -} -#endif /* CONFIG_CONSOLE_EXTRA_INFO */ -#endif /* CONFIG_VIDEO */ - -void board_reset(void) -{ - gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); -} - -#ifdef CONFIG_SPL_OS_BOOT -/* - * lwmon5 specific implementation of spl_start_uboot() - * - * RETURN - * 0 if booting into OS is selected (default) - * 1 if booting into U-Boot is selected - */ -int spl_start_uboot(void) -{ - char s[8]; - - env_init(); - getenv_f("boot_os", s, sizeof(s)); - if ((s != NULL) && (strcmp(s, "yes") == 0)) - return 0; - - return 1; -} - -/* - * This function is called from the SPL U-Boot version for - * early init stuff, that needs to be done for OS (e.g. Linux) - * booting. Doing it later in the real U-Boot would not work - * in case that the SPL U-Boot boots Linux directly. - */ -void spl_board_init(void) -{ - const gdc_regs *regs = board_get_regs(); - - /* - * Setup PFC registers, mainly for ethernet support - * later on in Linux - */ - board_early_init_f(); - - /* enable the LSB transmitter */ - gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); - - /* - * Clear resets - */ - mtsdr(SDR0_SRST1, 0x00000000); - mtsdr(SDR0_SRST0, 0x00000000); - - /* - * Reset Lime controller - */ - gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); - udelay(500); - gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); - - out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF); - udelay(300); - out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR); - - while (regs->index) { - out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) + - regs->index, regs->value); - regs++; - } - - board_backlight_brightness(DEFAULT_BRIGHTNESS); -} -#endif diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c deleted file mode 100644 index 5dfbb0bc25..0000000000 --- a/board/lwmon5/sdram.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2007-2013 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <asm/cache.h> -#include <asm/ppc440.h> -#include <watchdog.h> - -/* - * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory - * region. Right now the cache should still be disabled in U-Boot because of the - * EMAC driver, that need it's buffer descriptor to be located in non cached - * memory. - * - * If at some time this restriction doesn't apply anymore, just define - * CONFIG_4xx_DCACHE in the board config file and this code should setup - * everything correctly. - */ -#ifdef CONFIG_4xx_DCACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -#endif - -/*-----------------------------------------------------------------------------+ - * Prototypes - *-----------------------------------------------------------------------------*/ -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); -extern void dcbz_area(u32 start_address, u32 num_bytes); - -static u32 is_ecc_enabled(void) -{ - u32 val; - - mfsdram(DDR0_22, val); - val &= DDR0_22_CTRL_RAW_MASK; - if (val) - return 1; - else - return 0; -} - -void board_add_ram_info(int use_default) -{ - PPC4xx_SYS_INFO board_cfg; - u32 val; - - if (is_ecc_enabled()) - puts(" (ECC"); - else - puts(" (ECC not"); - - get_sys_info(&board_cfg); - printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000); - - mfsdram(DDR0_03, val); - val = DDR0_03_CASLAT_DECODE(val); - printf(", CL%d)", val); -} - -#ifdef CONFIG_DDR_ECC -static void wait_ddr_idle(void) -{ - /* - * Controller idle status cannot be determined for Denali - * DDR2 code. Just return here. - */ -} - -static void program_ecc(u32 start_address, - u32 num_bytes, - u32 tlb_word2_i_value) -{ - u32 val; - u32 current_addr = start_address; - u32 size; - int bytes_remaining; - - sync(); - wait_ddr_idle(); - - /* - * Because of 440EPx errata CHIP 11, we don't touch the last 256 - * bytes of SDRAM. - */ - bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE; - - /* - * We have to write the ECC bytes by zeroing and flushing in smaller - * steps, since the whole 256MByte takes too long for the external - * watchdog. - */ - while (bytes_remaining > 0) { - size = min((64 << 20), bytes_remaining); - - /* Write zero's to SDRAM */ - dcbz_area(current_addr, size); - - /* Write modified dcache lines back to memory */ - clean_dcache_range(current_addr, current_addr + size); - - current_addr += 64 << 20; - bytes_remaining -= 64 << 20; - WATCHDOG_RESET(); - } - - sync(); - wait_ddr_idle(); - - /* Clear error status */ - mfsdram(DDR0_00, val); - mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); - - /* Set 'int_mask' parameter to functionnal value */ - mfsdram(DDR0_01, val); - mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); - - sync(); - wait_ddr_idle(); -} -#endif - -/************************************************************************* - * - * initdram -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -phys_size_t initdram (int board_type) -{ -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5) - /* CL=4 */ - mtsdram(DDR0_02, 0x00000000); - - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ - - mtsdram(DDR0_04, 0x0B030300); - mtsdram(DDR0_05, 0x02020308); - mtsdram(DDR0_06, 0x0003C812); - mtsdram(DDR0_07, 0x00090100); - mtsdram(DDR0_08, 0x03c80001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_11, 0x000CC800); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x1e000000); - mtsdram(DDR0_18, 0x1e1e1e1e); - mtsdram(DDR0_19, 0x1e1e1e1e); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); -#ifdef CONFIG_DDR_ECC - mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ -#else - mtsdram(DDR0_22, 0x00267F0B); -#endif - - mtsdram(DDR0_23, 0x01000000); - mtsdram(DDR0_24, 0x01010001); - - mtsdram(DDR0_26, 0x2D93028A); - mtsdram(DDR0_27, 0x0784682B); - - mtsdram(DDR0_28, 0x00000080); - mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000008); - - mtsdram(DDR0_43, 0x050A0200); - mtsdram(DDR0_44, 0x00000005); - mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ - - denali_wait_for_dlllock(); - -#if defined(CONFIG_DDR_DATA_EYE) - /* -----------------------------------------------------------+ - * Perform data eye search if requested. - * ----------------------------------------------------------*/ - program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, - TLB_WORD2_I_ENABLE); - denali_core_search_data_eye(); - remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); -#endif - - /* - * Program tlb entries for this size (dynamic) - */ - program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, - MY_TLB_WORD2_I_ENABLE); - -#if defined(CONFIG_DDR_ECC) -#if defined(CONFIG_4xx_DCACHE) - /* - * If ECC is enabled, initialize the parity bits. - */ - program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0); -#else /* CONFIG_4xx_DCACHE */ - /* - * Setup 2nd TLB with same physical address but different virtual address - * with cache enabled. This is done for fast ECC generation. - */ - program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); - - /* - * If ECC is enabled, initialize the parity bits. - */ - program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); - - /* - * Now after initialization (auto-calibration and ECC generation) - * remove the TLB entries with caches enabled and program again with - * desired cache functionality - */ - remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20); -#endif /* CONFIG_4xx_DCACHE */ -#endif /* CONFIG_DDR_ECC */ - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); -#endif /* CONFIG_SPL_BUILD */ - - return (CONFIG_SYS_MBYTES_SDRAM << 20); -} diff --git a/board/pcs440ep/Kconfig b/board/pcs440ep/Kconfig deleted file mode 100644 index 5b280f6e77..0000000000 --- a/board/pcs440ep/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PCS440EP - -config SYS_BOARD - default "pcs440ep" - -config SYS_CONFIG_NAME - default "pcs440ep" - -endif diff --git a/board/pcs440ep/MAINTAINERS b/board/pcs440ep/MAINTAINERS deleted file mode 100644 index 6eccc854f9..0000000000 --- a/board/pcs440ep/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PCS440EP BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/pcs440ep/ -F: include/configs/pcs440ep.h -F: configs/pcs440ep_defconfig diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile deleted file mode 100644 index 4fc24d6c5d..0000000000 --- a/board/pcs440ep/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pcs440ep.o flash.o -extra-y += init.o diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk deleted file mode 100644 index b90d5d0ec1..0000000000 --- a/board/pcs440ep/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# PCS440EP board -# - -# Check the U-Boot Image with a SHA1 checksum -ALL-y += u-boot.sha1 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c deleted file mode 100644 index 8c5e94fbf5..0000000000 --- a/board/pcs440ep/flash.c +++ /dev/null @@ -1,607 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> - -#ifndef CONFIG_SYS_FLASH_READ0 -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Functions - */ -static int write_word(flash_info_t *info, ulong dest, ulong data); -static ulong flash_get_size(vu_long *addr, flash_info_t *info); - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1; - int i; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - return (size_b0 + size_b1); -} - -void flash_print_info(flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("ST Micro"); break; - case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; - case FLASH_MAN_MX: printf ("MXIC "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM040: printf ("AM29LV040B (4 Mbit, uniform sector size)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n"); - break; - case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); - break; - case STM_ID_M29W040B: printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - short n; - volatile CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - - value = addr2[CONFIG_SYS_FLASH_READ0]; - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: - info->flash_id = FLASH_MAN_EXCEL; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 0.5 MB */ - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 0,5 MB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020: - info->flash_id += FLASH_SST020; - info->sector_count = 64; - info->size = 0x00040000; - break; /* => 256 kB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040: - info->flash_id += FLASH_SST040; - info->sector_count = 128; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00001000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) - info->protect[i] = 0; - else - info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) - if (info->protect[sect]) - prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - flag = 0; - } - - /* data polling for D7 */ - start = get_timer (0); - while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } else { - if (sect == s_first) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - } - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) - data = (data << 8) | *src++; - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S deleted file mode 100644 index c0e83de257..0000000000 --- a/board/pcs440ep/init.S +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR detection - * routine. - */ - - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) - - /* PCI */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) - - /* USB 2.0 Device */ - tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) - - tlbtab_end diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c deleted file mode 100644 index 267c001435..0000000000 --- a/board/pcs440ep/pcs440ep.c +++ /dev/null @@ -1,755 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <malloc.h> -#include <command.h> -#include <crc.h> -#include <asm/processor.h> -#include <spd_sdram.h> -#include <status_led.h> -#include <u-boot/sha1.h> -#include <asm/io.h> -#include <net.h> -#include <ata.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -unsigned char sha1_checksum[SHA1_SUM_LEN]; - -/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */ -unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, - 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; - -static void set_leds (int val) -{ - out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27)); -} - -#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27) - -void __led_init (led_id_t mask, int state) -{ - int val = GET_LEDS; - - if (state == STATUS_LED_ON) - val |= mask; - else - val &= ~mask; - set_leds (val); -} - -void __led_set (led_id_t mask, int state) -{ - int val = GET_LEDS; - - if (state == STATUS_LED_ON) - val |= mask; - else if (state == STATUS_LED_OFF) - val &= ~mask; - set_leds (val); -} - -void __led_toggle (led_id_t mask) -{ - int val = GET_LEDS; - - val ^= mask; - set_leds (val); -} - -static void status_led_blink (void) -{ - int i; - int val = GET_LEDS; - - /* set all LED which are on, to state BLINKING */ - for (i = 0; i < 4; i++) { - if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING); - else status_led_set (3 - i, STATUS_LED_OFF); - val = val >> 1; - } -} - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress (int val) -{ - /* find all valid Codes for val in README */ - if (val == -BOOTSTAGE_ID_NEED_RESET) - return; - if (val < 0) { - /* smthing goes wrong */ - status_led_blink (); - return; - } - switch (val) { - case BOOTSTAGE_ID_CHECK_MAGIC: - /* validating Image */ - status_led_set(0, STATUS_LED_OFF); - status_led_set(1, STATUS_LED_ON); - status_led_set(2, STATUS_LED_ON); - break; - case BOOTSTAGE_ID_RUN_OS: - status_led_set(0, STATUS_LED_ON); - status_led_set(1, STATUS_LED_ON); - status_led_set(2, STATUS_LED_ON); - break; -#if 0 - case BOOTSTAGE_ID_NET_ETH_START: - /* starting Ethernet configuration */ - status_led_set(0, STATUS_LED_OFF); - status_led_set(1, STATUS_LED_OFF); - status_led_set(2, STATUS_LED_ON); - break; -#endif - case BOOTSTAGE_ID_NET_START: - /* loading Image */ - status_led_set(0, STATUS_LED_ON); - status_led_set(1, STATUS_LED_OFF); - status_led_set(2, STATUS_LED_ON); - break; - } -} -#endif - -int board_early_init_f(void) -{ - register uint reg; - - set_leds(0); /* display boot info counter */ - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - /*-------------------------------------------------------------------- - * GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c - * via define from board config file. - *-------------------------------------------------------------------*/ - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ - mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup other serial configuration - *-------------------------------------------------------------------*/ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(SDR0_PFC0, 0x00000000); /* Pin function: enable GPIO49-63 */ - mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ - - return 0; -} - -#define EEPROM_LEN 256 -static void load_ethaddr(void) -{ - int ok_ethaddr, ok_eth1addr; - int ret; - uchar buf[EEPROM_LEN]; - char *use_eeprom; - u16 checksumcrc16 = 0; - - /* If the env is sane, then nothing for us to do */ - ok_ethaddr = eth_getenv_enetaddr("ethaddr", buf); - ok_eth1addr = eth_getenv_enetaddr("eth1addr", buf); - if (ok_ethaddr && ok_eth1addr) - return; - - /* read the MACs from EEprom */ - status_led_set (0, STATUS_LED_ON); - status_led_set (1, STATUS_LED_ON); - ret = eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 0, buf, EEPROM_LEN); - if (ret == 0) { - checksumcrc16 = cyg_crc16 (buf, EEPROM_LEN - 2); - /* check, if the EEprom is programmed: - * - The Prefix(Byte 0,1,2) is equal to "ATR" - * - The checksum, stored in the last 2 Bytes, is correct - */ - if ((strncmp ((char *)buf,"ATR",3) != 0) || - ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) || - ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) { - /* EEprom is not programmed */ - printf("%s: EEPROM Checksum not OK\n", __FUNCTION__); - } else { - /* get the MACs */ - if (!ok_ethaddr) - eth_setenv_enetaddr("ethaddr", &buf[3]); - if (!ok_eth1addr) - eth_setenv_enetaddr("eth1addr", &buf[9]); - return; - } - } - - /* some error reading the EEprom */ - if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) { - /* dont use bootcmd */ - setenv("bootdelay", "-1"); - return; - } - /* == default ? use standard */ - if (strncmp (use_eeprom, "default", 7) == 0) { - return; - } - /* Env doesnt exist -> hang */ - status_led_blink (); - /* here we do this "handy" because we have no interrupts - at this time */ - puts ("### EEPROM ERROR ### Please RESET the board ###\n"); - for (;;) { - __led_toggle (12); - udelay (100000); - } - return; -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -struct kbd_data_t { - char s1; - char s2; -}; - -struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) -{ - char *val; - unsigned long tmp; - - /* use the DIPs for some bootoptions */ - val = getenv (ENV_NAME_DIP); - tmp = simple_strtoul (val, NULL, 16); - - kbd_data->s2 = (tmp & 0x0f); - kbd_data->s1 = (tmp & 0xf0) >> 4; - return kbd_data; -} - -static int compare_magic (const struct kbd_data_t *kbd_data, char *str) -{ - char s1 = str[0]; - - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (s1 != kbd_data->s1) return -1; - - s1 = str[1]; - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (s1 != kbd_data->s2) return -1; - return 0; -} - -static char *key_match (const struct kbd_data_t *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can be appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; *suffix || - suffix == kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - if (compare_magic (kbd_data, getenv (magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv (cmd_name); - - return (cmd); - } - } - return (NULL); -} - -#endif /* CONFIG_PREBOOT */ - -static int pcs440ep_readinputs (void) -{ - int i; - char value[20]; - - /* read the inputs and set the Envvars */ - /* Revision Level Bit 26 - 29 */ - i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2); - i = swapbits[i]; - sprintf (value, "%02x", i); - setenv (ENV_NAME_REVLEV, value); - /* Solder Switch Bit 30 - 33 */ - i = (in32 (GPIO0_IR) & 0x00000003) << 2; - i += (in32 (GPIO1_IR) & 0xc0000000) >> 30; - i = swapbits[i]; - sprintf (value, "%02x", i); - setenv (ENV_NAME_SOLDER, value); - /* DIP Switch Bit 49 - 56 */ - i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7); - i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4]; - sprintf (value, "%02x", i); - setenv (ENV_NAME_DIP, value); - return 0; -} - - -#if defined(CONFIG_SHA1_CHECK_UB_IMG) -/************************************************************************* - * calculate a SHA1 sum for the U-Boot image in Flash. - * - ************************************************************************/ -static int pcs440ep_sha1 (int docheck) -{ - unsigned char *data; - unsigned char *ptroff; - unsigned char output[20]; - unsigned char org[20]; - int i, len = CONFIG_SHA1_LEN; - - memcpy ((char *)CONFIG_SYS_LOAD_ADDR, (char *)CONFIG_SHA1_START, len); - data = (unsigned char *)CONFIG_SYS_LOAD_ADDR; - ptroff = &data[len + SHA1_SUM_POS]; - - for (i = 0; i < SHA1_SUM_LEN; i++) { - org[i] = ptroff[i]; - ptroff[i] = 0; - } - - sha1_csum ((unsigned char *) data, len, (unsigned char *)output); - - if (docheck == 2) { - for (i = 0; i < 20 ; i++) { - printf("%02X ", output[i]); - } - printf("\n"); - } - if (docheck == 1) { - for (i = 0; i < 20 ; i++) { - if (org[i] != output[i]) return 1; - } - } - return 0; -} - -/************************************************************************* - * do some checks after the SHA1 checksum from the U-Boot Image was - * calculated. - * - ************************************************************************/ -static void pcs440ep_checksha1 (void) -{ - int ret; - char *cs_test; - - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_OFF); - status_led_set (2, STATUS_LED_ON); - ret = pcs440ep_sha1 (1); - if (ret == 0) return; - - if ((cs_test = getenv ("cs_test")) == NULL) { - /* Env doesnt exist -> hang */ - status_led_blink (); - /* here we do this "handy" because we have no interrupts - at this time */ - puts ("### SHA1 ERROR ### Please RESET the board ###\n"); - for (;;) { - __led_toggle (2); - udelay (100000); - } - } - - if (strncmp (cs_test, "off", 3) == 0) { - printf ("SHA1 U-Boot sum NOT ok!\n"); - setenv ("bootdelay", "-1"); - } -} -#else -static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);} -#endif - -int misc_init_r (void) -{ - uint pbcr; - int size_val = 0; - - load_ethaddr(); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[1]); - - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[1]); - - pcs440ep_readinputs (); - pcs440ep_checksha1 (); -#ifdef CONFIG_PREBOOT - { - struct kbd_data_t kbd_data; - /* Decode keys */ - char *str = strdup (key_match (get_keys (&kbd_data))); - /* Set or delete definition */ - setenv ("preboot", str); - free (str); - } -#endif /* CONFIG_PREBOOT */ - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: PCS440EP"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -void spd_ddr_init_hang (void) -{ - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_ON); - /* we cannot use hang() because we are still running from - Flash, and so the status_led driver is not initialized */ - puts ("### SDRAM ERROR ### Please RESET the board ###\n"); - for (;;) { - __led_toggle (4); - udelay (100000); - } -} - -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - - status_led_set (0, STATUS_LED_ON); - status_led_set (1, STATUS_LED_OFF); - dram_size = spd_sdram(); - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_ON); - if (dram_size == 0) { - hang(); - } - - return dram_size; -} - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ - -} -#endif - -/************************************************************************* - * "led" Commando for the U-Boot shell - * - ************************************************************************/ -int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = 0, i; - ulong pattern = 0; - - pattern = simple_strtoul (argv[1], NULL, 16); - if (pattern > 0x400) { - int val = GET_LEDS; - printf ("led: %x\n", val); - return rcode; - } - if (pattern > 0x200) { - status_led_blink (); - hang (); - return rcode; - } - if (pattern > 0x100) { - status_led_blink (); - return rcode; - } - pattern &= 0x0f; - for (i = 0; i < 4; i++) { - if (pattern & 0x01) status_led_set (i, STATUS_LED_ON); - else status_led_set (i, STATUS_LED_OFF); - pattern = pattern >> 1; - } - return rcode; -} - -U_BOOT_CMD( - led, 2, 1, do_led, - "set the DIAG-LED", - "[bitmask] 0x01 = DIAG 1 on\n" - " 0x02 = DIAG 2 on\n" - " 0x04 = DIAG 3 on\n" - " 0x08 = DIAG 4 on\n" - " > 0x100 set the LED, who are on, to state blinking" -); - -#if defined(CONFIG_SHA1_CHECK_UB_IMG) -/************************************************************************* - * "sha1" Commando for the U-Boot shell - * - ************************************************************************/ -int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = -1; - - if (argc < 2) { -usage: - return cmd_usage(cmdtp); - } - - if (argc >= 3) { - unsigned char *data; - unsigned char output[20]; - int len; - int i; - - data = (unsigned char *)simple_strtoul (argv[1], NULL, 16); - len = simple_strtoul (argv[2], NULL, 16); - sha1_csum (data, len, (unsigned char *)output); - printf ("U-Boot sum:\n"); - for (i = 0; i < 20 ; i++) { - printf ("%02X ", output[i]); - } - printf ("\n"); - if (argc == 4) { - data = (unsigned char *)simple_strtoul (argv[3], NULL, 16); - memcpy (data, output, 20); - } - return 0; - } - if (argc == 2) { - char *ptr = argv[1]; - if (*ptr != '-') goto usage; - ptr++; - if ((*ptr == 'c') || (*ptr == 'C')) { - rcode = pcs440ep_sha1 (1); - printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : ""); - } else if ((*ptr == 'p') || (*ptr == 'P')) { - rcode = pcs440ep_sha1 (2); - } else { - rcode = pcs440ep_sha1 (0); - } - return rcode; - } - return rcode; -} - -U_BOOT_CMD( - sha1, 4, 1, do_sha1, - "calculate the SHA1 Sum", - "address len [addr] calculate the SHA1 sum [save at addr]\n" - " -p calculate the SHA1 sum from the U-Boot image in flash and print\n" - " -c check the U-Boot image in flash" -); -#endif - -#if defined (CONFIG_CMD_IDE) -/* These addresses need to be shifted one place to the left - * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) - * These values are shifted - */ -void inline ide_outb(int dev, int port, unsigned char val) -{ - debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", - dev, port, val, (ATA_CURR_BASE(dev)+port)); - - out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val); -} -unsigned char inline ide_inb(int dev, int port) -{ - uchar val; - val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1))); - debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", - dev, port, (ATA_CURR_BASE(dev)+port), val); - return (val); -} -#endif - -#ifdef CONFIG_IDE_PREINIT -int ide_preinit (void) -{ - /* Set True IDE Mode */ - out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000)); - out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); - out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040)); - udelay (100000); - return 0; -} -#endif - -#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - if (idereset == 0) { - out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); - } else { - out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000)); - } - udelay (10000); -} -#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - - -/* this is motly the same as it should, causing a little code duplication */ -#if defined(CONFIG_CMD_IDE) -#define EIEIO __asm__ volatile ("eieio") - -void ide_input_swap_data(int dev, ulong *sect_buf, int words) -{ - volatile ushort *pbuf = - (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); - ushort *dbuf = (ushort *) sect_buf; - - debug("in input swap data base for read is %lx\n", - (unsigned long) pbuf); - - while (words--) { - *dbuf++ = *pbuf; - *dbuf++ = *pbuf; - } -} - -void ide_output_data(int dev, const ulong *sect_buf, int words) -{ - ushort *dbuf; - volatile ushort *pbuf; - - pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); - dbuf = (ushort *) sect_buf; - while (words--) { - EIEIO; - *pbuf = ld_le16(dbuf++); - EIEIO; - *pbuf = ld_le16(dbuf++); - } -} - -void ide_input_data(int dev, ulong *sect_buf, int words) -{ - ushort *dbuf; - volatile ushort *pbuf; - - pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG); - dbuf = (ushort *) sect_buf; - - debug("in input data base for read is %lx\n", (unsigned long) pbuf); - - while (words--) { - EIEIO; - *dbuf++ = ld_le16(pbuf); - EIEIO; - *dbuf++ = ld_le16(pbuf); - } -} - -#endif diff --git a/board/prodrive/alpr/Kconfig b/board/prodrive/alpr/Kconfig deleted file mode 100644 index 543b4557ee..0000000000 --- a/board/prodrive/alpr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ALPR - -config SYS_BOARD - default "alpr" - -config SYS_VENDOR - default "prodrive" - -config SYS_CONFIG_NAME - default "alpr" - -endif diff --git a/board/prodrive/alpr/MAINTAINERS b/board/prodrive/alpr/MAINTAINERS deleted file mode 100644 index 31baabb67e..0000000000 --- a/board/prodrive/alpr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ALPR BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/prodrive/alpr/ -F: include/configs/alpr.h -F: configs/alpr_defconfig diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile deleted file mode 100644 index 812d041ef2..0000000000 --- a/board/prodrive/alpr/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = alpr.o fpga.o nand.o -extra-y += init.o diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c deleted file mode 100644 index 31c1ab5d0f..0000000000 --- a/board/prodrive/alpr/alpr.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <spd_sdram.h> -#include <asm/ppc4xx-emac.h> -#include <miiphy.h> -#include <asm/processor.h> -#include <asm/4xx_pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern int alpr_fpga_init(void); - -int board_early_init_f (void) -{ - /*------------------------------------------------------------------------- - * Initialize EBC CONFIG - *-------------------------------------------------------------------------*/ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (UIC1PR, 0xfffffe03); /* per manual */ - mtdcr (UIC1TR, 0x01c00000); /* per manual */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); /* */ - mtdcr (UIC0TR, 0x00000000); /* */ - mtdcr (UIC0VR, 0x00000001); /* */ - - /* Setup shutdown/SSD empty interrupt as inputs */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); - - /* Setup GPIO/IRQ multiplexing */ - mtsdr(SDR0_PFC0, 0x01a33e00); - - return 0; -} - -int last_stage_init(void) -{ - unsigned short reg; - - /* - * Configure LED's of both Marvell 88E1111 PHY's - * - * This has to be done after the 4xx ethernet driver is loaded, - * so "last_stage_init()" is the right place. - */ - miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); - reg |= 0x0001; - miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); - miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); - reg |= 0x0001; - miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); - - return 0; -} - -static int board_rev(void) -{ - /* Setup as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); - - return (in32(GPIO0_IR) >> 16) & 0x3; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf ("Board: ALPR"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - printf(" (Rev. %d)\n", board_rev()); - - return (0); -} - -#if defined(CONFIG_PCI) -/* - * Override weak pci_pre_init() - */ -int pci_pre_init(struct pci_controller *hose) -{ - if (__pci_pre_init(hose) == 0) - return 0; - - /* FPGA Init */ - alpr_fpga_init(); - - return 1; -} - -/************************************************************************* - * Override weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -static void wait_for_pci_ready(void) -{ - /* - * Configure EREADY as input - */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY); - udelay(1000); - - for (;;) { - if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY) - return; - } - -} - -int is_pci_host(struct pci_controller *hose) -{ - wait_for_pci_ready(); - return 1; /* return 1 for host controller */ -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - | PowerPC440 PCI Master configuration. - | Map PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r( PCIL0_POM0SA, 0 ); /* disable */ - out32r( PCIL0_POM1SA, 0 ); /* disable */ - out32r( PCIL0_POM2SA, 0 ); /* disable */ - - out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ - - out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk deleted file mode 100644 index 0ccb2e669c..0000000000 --- a/board/prodrive/alpr/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c deleted file mode 100644 index 3133f94273..0000000000 --- a/board/prodrive/alpr/fpga.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Altera FPGA configuration support for the ALPR computer from prodrive - */ - -#include <common.h> -#include <altera.h> -#include <ACEX1K.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/ppc440.h> -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_FPGA) - -#ifdef FPGA_DEBUG -#define PRINTF(fmt, args...) printf(fmt , ##args) -#else -#define PRINTF(fmt, args...) -#endif - -static unsigned long regval; - -#define SET_GPIO_REG_0(reg, bit) do { \ - regval = in32(reg); \ - regval &= ~(0x80000000 >> bit); \ - out32(reg, regval); \ - } while (0) - -#define SET_GPIO_REG_1(reg, bit) do { \ - regval = in32(reg); \ - regval |= (0x80000000 >> bit); \ - out32(reg, regval); \ - } while (0) - -#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) -#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) - -#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN) -#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG) -#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA) -#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK) -#define OLD_VAL (FPGA_PRG | FPGA_CONFIG) - -#define SET_FPGA(data) out32(GPIO0_OR, data) - -#define FPGA_WRITE_1 do { \ - SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA); /* set data to 1 */ \ -} while (0) - -#define FPGA_WRITE_0 do { \ - SET_FPGA(OLD_VAL | 0 | 0); /* set data to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_CLK | 0); /* set data to 1 */ \ -} while (0) - -/* Plattforminitializations */ -/* Here we have to set the FPGA Chain */ -/* PROGRAM_PROG_EN = HIGH */ -/* PROGRAM_SEL_DPR = LOW */ -int fpga_pre_fn(int cookie) -{ - /* Enable the FPGA Chain */ - SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN); - SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN); - SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR); - SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR)); - - /* initialize the GPIO Pins */ - /* output */ - SET_GPIO_0(CONFIG_SYS_GPIO_CLK); - SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK); - - /* output */ - SET_GPIO_0(CONFIG_SYS_GPIO_DATA); - SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA); - - /* First we set STATUS to 0 then as an input */ - SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS); - SET_GPIO_0(CONFIG_SYS_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS); - - /* output */ - SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG); - SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); - - /* input */ - SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON); - SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON); - SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON); - - /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ - SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); - return FPGA_SUCCESS; -} - -/* Set the state of CONFIG Pin */ -int fpga_config_fn(int assert_config, int flush, int cookie) -{ - if (assert_config) - SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG); - else - SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); - - return FPGA_SUCCESS; -} - -/* Returns the state of STATUS Pin */ -int fpga_status_fn(int cookie) -{ - unsigned long reg; - - reg = in32(GPIO0_IR); - if (reg & (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) { - PRINTF("STATUS = HIGH\n"); - return FPGA_FAIL; - } - PRINTF("STATUS = LOW\n"); - return FPGA_SUCCESS; -} - -/* Returns the state of CONF_DONE Pin */ -int fpga_done_fn(int cookie) -{ - unsigned long reg; - reg = in32(GPIO0_IR); - if (reg & (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) { - PRINTF("CONF_DON = HIGH\n"); - return FPGA_FAIL; - } - PRINTF("CONF_DON = LOW\n"); - return FPGA_SUCCESS; -} - -/* writes the complete buffer to the FPGA - writing the complete buffer in one function is much faster, - then calling it for every bit */ -int fpga_write_fn(const void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - unsigned char *data = (unsigned char *) buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - while (bytecount < len) { - val = data[bytecount++]; - i = 8; - do { - if (val & 0x01) - FPGA_WRITE_1; - else - FPGA_WRITE_0; - - val >>= 1; - i--; - } while (i > 0); - -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % len_40 == 0) { - putc('.'); /* let them know we are alive */ -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } -#endif - } - return FPGA_SUCCESS; -} - -/* called, when programming is aborted */ -int fpga_abort_fn(int cookie) -{ - SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR)); - return FPGA_SUCCESS; -} - -/* called, when programming was succesful */ -int fpga_post_fn(int cookie) -{ - return fpga_abort_fn(cookie); -} - -/* Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - */ -Altera_CYC2_Passive_Serial_fns fpga_fns = { - fpga_pre_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_write_fn, - fpga_abort_fn, - fpga_post_fn -}; - -Altera_desc fpga[CONFIG_FPGA_COUNT] = { - {Altera_CYC2, - passive_serial, - Altera_EP2C35_SIZE, - (void *) &fpga_fns, - NULL, - 0} -}; - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -int alpr_fpga_init(void) -{ - int i; - - PRINTF("%s:%d: Initialize FPGA interface\n", __func__, __LINE__); - fpga_init(); - - for (i = 0; i < CONFIG_FPGA_COUNT; i++) { - PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i); - fpga_add(fpga_altera, &fpga[i]); - } - return 1; -} - -#endif diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S deleted file mode 100644 index 7ff7a59170..0000000000 --- a/board/prodrive/alpr/init.S +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG ) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) -#ifdef CONFIG_4xx_DCACHE - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G) -#else - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG) -#endif - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) -#endif - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) - - /* PCI */ - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG) - - /* NAND */ - tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG) - tlbtab_end diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c deleted file mode 100644 index ca40cea9ad..0000000000 --- a/board/prodrive/alpr/nand.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2006 - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_CMD_NAND) - -#include <asm/processor.h> -#include <nand.h> - -struct alpr_ndfc_regs { - u8 cmd[4]; - u8 addr_wait; - u8 term; - u8 dummy; - u8 dummy2; - u8 data; -}; - -static u8 hwctl; -static struct alpr_ndfc_regs *alpr_ndfc = NULL; - -#define readb(addr) (u8)(*(volatile u8 *)(addr)) -#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) - -/* - * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to - * the NAND devices. The NDFC has command, address and data registers that - * when accessed will set up the NAND flash pins appropriately. We'll use the - * hwcontrol function to save the configuration in a global variable. - * We can then use this information in the read and write functions to - * determine which NDFC register to access. - * - * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). - */ -static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - if ( (ctrl & NAND_NCE) != NAND_NCE) - writeb(0x00, &(alpr_ndfc->term)); - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static u_char alpr_nand_read_byte(struct mtd_info *mtd) -{ - return readb(&(alpr_ndfc->data)); -} - -static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *nand = mtd->priv; - int i; - - for (i = 0; i < len; i++) { - if (hwctl & 0x1) - /* - * IO_ADDR_W used as CMD[i] reg to support multiple NAND - * chips. - */ - writeb(buf[i], nand->IO_ADDR_W); - else if (hwctl & 0x2) - writeb(buf[i], &(alpr_ndfc->addr_wait)); - else - writeb(buf[i], &(alpr_ndfc->data)); - } -} - -static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - buf[i] = readb(&(alpr_ndfc->data)); - } -} - -static int alpr_nand_dev_ready(struct mtd_info *mtd) -{ - /* - * Blocking read to wait for NAND to be ready - */ - (void)readb(&(alpr_ndfc->addr_wait)); - - /* - * Return always true - */ - return 1; -} - -int board_nand_init(struct nand_chip *nand) -{ - alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE; - - nand->ecc.mode = NAND_ECC_SOFT; - - /* Reference hardware control function */ - nand->cmd_ctrl = alpr_nand_hwcontrol; - nand->read_byte = alpr_nand_read_byte; - nand->write_buf = alpr_nand_write_buf; - nand->read_buf = alpr_nand_read_buf; - nand->dev_ready = alpr_nand_dev_ready; - - return 0; -} -#endif diff --git a/board/prodrive/p3p440/Kconfig b/board/prodrive/p3p440/Kconfig deleted file mode 100644 index cf53aac57b..0000000000 --- a/board/prodrive/p3p440/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P3P440 - -config SYS_BOARD - default "p3p440" - -config SYS_VENDOR - default "prodrive" - -config SYS_CONFIG_NAME - default "p3p440" - -endif diff --git a/board/prodrive/p3p440/MAINTAINERS b/board/prodrive/p3p440/MAINTAINERS deleted file mode 100644 index 68fd1a98a0..0000000000 --- a/board/prodrive/p3p440/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -P3P440 BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/prodrive/p3p440/ -F: include/configs/p3p440.h -F: configs/p3p440_defconfig diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile deleted file mode 100644 index d62f75d3e7..0000000000 --- a/board/prodrive/p3p440/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = p3p440.o -extra-y += init.o diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk deleted file mode 100644 index f18b09710d..0000000000 --- a/board/prodrive/p3p440/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S deleted file mode 100644 index 35b1afab85..0000000000 --- a/board/prodrive/p3p440/init.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX ) - tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX ) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c deleted file mode 100644 index 929e8eb1a5..0000000000 --- a/board/prodrive/p3p440/p3p440.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> - -#include "p3p440.h" - -DECLARE_GLOBAL_DATA_PTR; - -void set_led(int color) -{ - switch (color) { - case LED_OFF: - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED); - break; - - case LED_GREEN: - out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED); - break; - - case LED_RED: - out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN); - break; - - case LED_ORANGE: - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED); - break; - } -} - -static int is_monarch(void) -{ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY); - udelay(1000); - - if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO) - return 0; - else - return 1; -} - -static void wait_for_pci_ready(void) -{ - /* - * Configure EREADY_IO as input - */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO); - udelay(1000); - - for (;;) { - if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO) - return; - } - -} - -int board_early_init_f(void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - /*-------------------------------------------------------------------- - * Setup pin multiplexing (GPIO/IRQ...) - *-------------------------------------------------------------------*/ - mtdcr(CPC0_GPIO, 0x03F01F80); - - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); - out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: P3P440"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - - if (is_monarch()) { - puts(", Monarch"); - } else { - puts(", None-Monarch"); - } - - putc('\n'); - - return (0); -} - -int misc_init_r (void) -{ - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if only one FLASH bank is available - */ - if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - mtebc(PB1CR, 0); /* disable cs */ - mtebc(PB1AP, 0); - mtebc(PB2CR, 0); /* disable cs */ - mtebc(PB2AP, 0); - mtebc(PB3CR, 0); /* disable cs */ - mtebc(PB3AP, 0); - } - - return 0; -} - -/************************************************************************* - * Override weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - if (is_monarch()) { - wait_for_pci_ready(); - return 1; /* return 1 for host controller */ - } else { - return 0; /* return 0 for adapter controller */ - } -} -#endif /* defined(CONFIG_PCI) */ diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h deleted file mode 100644 index a164f95feb..0000000000 --- a/board/prodrive/p3p440/p3p440.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __P3P440_H__ -#define __P3P440_H__ - -#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11) -#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18) -#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20) -#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21) -#define CONFIG_SYS_LED_RED (0x80000000 >> 22) - -#define LED_OFF 1 -#define LED_GREEN 2 -#define LED_RED 3 -#define LED_ORANGE 4 - -long int fixed_sdram(void); - -#endif /* __P3P440_H__ */ diff --git a/board/sbc405/Kconfig b/board/sbc405/Kconfig deleted file mode 100644 index 4e7e843f46..0000000000 --- a/board/sbc405/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SBC405 - -config SYS_BOARD - default "sbc405" - -config SYS_CONFIG_NAME - default "sbc405" - -endif diff --git a/board/sbc405/MAINTAINERS b/board/sbc405/MAINTAINERS deleted file mode 100644 index 2abad25997..0000000000 --- a/board/sbc405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -SBC405 BOARD -#M: - -S: Maintained -F: board/sbc405/ -F: include/configs/sbc405.h -F: configs/sbc405_defconfig diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile deleted file mode 100644 index 3f2b0e24ca..0000000000 --- a/board/sbc405/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sbc405.o strataflash.o diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c deleted file mode 100644 index cafc844a22..0000000000 --- a/board/sbc405/sbc405.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2001 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> -#include <malloc.h> -#include <spd_sdram.h> - - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - -int misc_init_r (void) -{ - return (0); -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming sbc405"); - } else { - puts(str); - } - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 64 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c deleted file mode 100644 index 7ddc97c5ea..0000000000 --- a/board/sbc405/strataflash.c +++ /dev/null @@ -1,774 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CONFIG_SYS_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CONFIG_SYS_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CONFIG_SYS_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t cptr; - int flag; - - cptr.cp = (uchar *)dest; - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 9b1ecf0457..fc37f1eef0 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis) struct mii_dev *bus; struct phy_device *phydev; - int ret = enable_fec_anatop_clock(ENET_25MHZ); + int ret = enable_fec_anatop_clock(0, ENET_25MHZ); if (ret) return ret; @@ -615,6 +615,7 @@ static void spl_dram_init(int width) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, }; if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) diff --git a/board/stx/stxgp3/Kconfig b/board/stx/stxgp3/Kconfig deleted file mode 100644 index 910b31b24f..0000000000 --- a/board/stx/stxgp3/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_STXGP3 - -config SYS_BOARD - default "stxgp3" - -config SYS_VENDOR - default "stx" - -config SYS_CONFIG_NAME - default "stxgp3" - -endif diff --git a/board/stx/stxgp3/MAINTAINERS b/board/stx/stxgp3/MAINTAINERS deleted file mode 100644 index bd5743c7de..0000000000 --- a/board/stx/stxgp3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -STXGP3 BOARD -#M: Dan Malek <dan@embeddedalley.com> -S: Orphan (since 2014-06) -F: board/stx/stxgp3/ -F: include/configs/stxgp3.h -F: configs/stxgp3_defconfig diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile deleted file mode 100644 index 78e2d6c96f..0000000000 --- a/board/stx/stxgp3/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += stxgp3.o -obj-y += law.o -obj-y += tlb.o -obj-y += flash.o -obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c deleted file mode 100644 index 41d4cfe738..0000000000 --- a/board/stx/stxgp3/ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/stx/stxgp3/flash.c b/board/stx/stxgp3/flash.c deleted file mode 100644 index 61066a430f..0000000000 --- a/board/stx/stxgp3/flash.c +++ /dev/null @@ -1,499 +0,0 @@ -/* - * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. <dan@embeddededge.com> - * Copied from ADS85xx. - * Updated to support the Silicon Tx GP3 8560. We should only find - * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash), - * but I left other code here in case people order custom boards. - * - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if !defined(CONFIG_SYS_NO_FLASH) - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -#undef DEBUG - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* set the default sector offset */ - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - } - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - - value = addr[0] & 0x00FF00FF; - -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)value); -#endif - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - - case (INTEL_ID_28F640C3T): - info->flash_id += FLASH_28F640C3T; - info->sector_count = 135; - info->size = 0x01000000; - sector_offset = 0x20000; - break; /* => 2x8 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table - * The first 127 blocks are large, the last 8 are small. - */ - for (i = 0; i < 127; i++) { - info->start[i] = base; - base += sector_offset; - /* Sectors are locked upon reset */ - info->protect[i] = 0; - } - for (i = 127; i < 135; i++) { - info->start[i] = base; - base += 0x4000; - /* Sectors are locked upon reset */ - info->protect[i] = 0; - } - - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - asm("sync"); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x00800080) != 0x00800080) { - if(*addr & 0x00200020){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - } - } - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - start = get_timer (0); - while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CONFIG_SYS_NO_FLASH */ diff --git a/board/stx/stxgp3/law.c b/board/stx/stxgp3/law.c deleted file mode 100644 index 611fa4bcf9..0000000000 --- a/board/stx/stxgp3/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xfc00_0000 0xfc00_ffff Config Latch 64K - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c deleted file mode 100644 index c80d5259ce..0000000000 --- a/board/stx/stxgp3/stxgp3.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * (C) Copyright 2003, Embedded Edge, LLC - * Dan Malek, <dan@embeddededge.com> - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560 - * - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <miiphy.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -static uint64_t next_led_update; -static uint led_bit; - -int -board_early_init_f(void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xfffffffdf; /* disable master abort */ -#endif - return 0; -} - -void -reset_phy(void) -{ - volatile uint *blatch; - - blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; - - /* reset Giga bit Ethernet port if needed here */ - - *blatch &= ~0x000000c0; - udelay(100); - *blatch = 0x000000c1; /* Light one led, too */ - udelay(1000); - -#if 0 /* This is the port we really want to use for debugging. */ - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -#endif -} - -int -checkboard(void) -{ - printf ("Board: Silicon Tx GPPP 8560 Board\n"); - return (0); -} - -/* Blinkin' LEDS for Robert. -*/ -void -show_activity(int flag) -{ - volatile uint *blatch; - - if (next_led_update > get_ticks()) - return; - - blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; - - led_bit >>= 1; - if (led_bit == 0) - led_bit = 0x08; - *blatch = (0xc0 | led_bit); - eieio(); - next_led_update += (get_tbclk() / 4); -} - - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_stxgp3_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_stxgp3_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} diff --git a/board/stx/stxgp3/tlb.c b/board/stx/stxgp3/tlb.c deleted file mode 100644 index 7c877b24d2..0000000000 --- a/board/stx/stxgp3/tlb.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xfc000000 16K Configuration Latch register - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stx/stxssa/Kconfig b/board/stx/stxssa/Kconfig deleted file mode 100644 index bd47b04444..0000000000 --- a/board/stx/stxssa/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_STXSSA - -config SYS_BOARD - default "stxssa" - -config SYS_VENDOR - default "stx" - -config SYS_CONFIG_NAME - default "stxssa" - -endif diff --git a/board/stx/stxssa/MAINTAINERS b/board/stx/stxssa/MAINTAINERS deleted file mode 100644 index b7cc89bf73..0000000000 --- a/board/stx/stxssa/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -STXSSA BOARD -#M: Dan Malek <dan@embeddedalley.com> -S: Orphan (since 2014-06) -F: board/stx/stxssa/ -F: include/configs/stxssa.h -F: configs/stxssa_defconfig -F: configs/stxssa_4M_defconfig diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile deleted file mode 100644 index b1d4b0a270..0000000000 --- a/board/stx/stxssa/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += stxssa.o -obj-y += law.o -obj-y += tlb.o -obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c deleted file mode 100644 index 1ccd4c5183..0000000000 --- a/board/stx/stxssa/ddr.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <i2c.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/stx/stxssa/law.c b/board/stx/stxssa/law.c deleted file mode 100644 index 72373f5d74..0000000000 --- a/board/stx/stxssa/law.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xfaff_ffff Local bus 128M - * 0xfb00_0000 0xfb00_ffff Config Latch 64K - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - /* Map the whole localbus, including flash and reset latch. */ - SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c deleted file mode 100644 index 6e4eed86a5..0000000000 --- a/board/stx/stxssa/stxssa.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * (C) Copyright 2005, Embedded Alley Solutions, Inc. - * Dan Malek, <dan@embeddedalley.com> - * Copied from STx GP3. - * Updates for Silicon Tx GP3 SSA - * - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_pci.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <miiphy.h> -#include <netdev.h> - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -static uint64_t next_led_update; -static uint led_bit; - -void -reset_phy(void) -{ - volatile uint *blatch; -#if 0 - int i; -#endif - blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE; - - /* reset Giga bit Ethernet port if needed here */ - -#if 1 - *blatch &= ~0x000000c0; - udelay(100); -#else - *blatch = 0; - asm("eieio"); - for (i=0; i<1000; i++) - udelay(1000); -#endif - *blatch = 0x000000c1; /* Light one led, too */ - udelay(1000); - -#if 0 /* This is the port we really want to use for debugging. */ - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -#endif -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup (blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -int -board_early_init_f(void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xffffffdf; /* disable master abort */ -#endif - - /* Why is the phy reset done _after_ the ethernet - * initialization in arch/powerpc/lib/board.c? - * Do it here so it's done before the TSECs are used. - */ - reset_phy(); - - return 0; -} - -int -checkboard(void) -{ - printf ("Board: Silicon Tx GPPP SSA Board\n"); - return (0); -} - -/* Blinkin' LEDS for Robert. -*/ -void -show_activity(int flag) -{ - volatile uint *blatch; - - if (next_led_update > get_ticks()) - return; - - blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE; - - led_bit >>= 1; - if (led_bit == 0) - led_bit = 0x08; - *blatch = (0xc0 | led_bit); - eieio(); - next_led_update += (get_tbclk() / 4); -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_stxgp3_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose[] = { -#ifndef CONFIG_PCI_PNP - { config_table: pci_stxgp3_config_table,}, -#else - {}, -#endif -#ifdef CONFIG_MPC85XX_PCI2 - {}, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); - - pci_mpc85xx_init(hose); -#endif /* CONFIG_PCI */ -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Initialize TSECs first */ - return pci_eth_init(bis); -} diff --git a/board/stx/stxssa/tlb.c b/board/stx/stxssa/tlb.c deleted file mode 100644 index 49c630c20e..0000000000 --- a/board/stx/stxssa/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 6M4 FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 256M Non-cacheable, guarded - * 0xf0000000 Local bus expansion option. - * 0xfb000000 Configuration Latch register (one word) - * 0xfc000000 Up to 64M flash - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig index 84b243e352..55c475c59a 100644 --- a/board/tbs/tbs2910/Kconfig +++ b/board/tbs/tbs2910/Kconfig @@ -6,10 +6,13 @@ config SYS_BOARD config SYS_VENDOR default "tbs" -config SYS_SOC - default "mx6" - config SYS_CONFIG_NAME default "tbs2910" +config MX6Q + default y + +config IMX_CONFIG + default "board/boundary/nitrogen6x/nitrogen6q2g.cfg" + endif diff --git a/board/technologic/ts4800/Kconfig b/board/technologic/ts4800/Kconfig new file mode 100644 index 0000000000..a28d5e41bd --- /dev/null +++ b/board/technologic/ts4800/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TS4800 + +config SYS_BOARD + default "ts4800" + +config SYS_VENDOR + default "technologic" + +config SYS_SOC + default "mx5" + +config SYS_CONFIG_NAME + default "ts4800" + +endif diff --git a/board/technologic/ts4800/MAINTAINERS b/board/technologic/ts4800/MAINTAINERS new file mode 100644 index 0000000000..e013ee42f8 --- /dev/null +++ b/board/technologic/ts4800/MAINTAINERS @@ -0,0 +1,6 @@ +TS4800 BOARD +M: Lucile Quirion <lucile.quirion@savoirfairelinux.com> +S: Maintained +F: board/ts/ts4800/ +F: include/configs/ts4800.h +F: configs/ts4800_defconfig diff --git a/board/technologic/ts4800/Makefile b/board/technologic/ts4800/Makefile new file mode 100644 index 0000000000..e9f1a37238 --- /dev/null +++ b/board/technologic/ts4800/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Savoir-faire Linux +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ts4800.o diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c new file mode 100644 index 0000000000..6ef15e10bf --- /dev/null +++ b/board/technologic/ts4800/ts4800.c @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2015 Savoir-faire Linux Inc. + * + * Derived from MX51EVK code by + * Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx51.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/imx-common/mx5_video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <mc13892.h> + +#include <malloc.h> +#include <netdev.h> +#include <phy.h> +#include "ts4800.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC2_BASE_ADDR}, +}; +#endif + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +u32 get_board_rev(void) +{ + u32 rev = get_cpu_rev(); + if (!gpio_get_value(IMX_GPIO_NR(1, 22))) + rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET; + return rev; +} + +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH) + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL), + NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +static void setup_iomux_fec(void) +{ + static const iomux_v3_cfg_t fec_pads[] = { + NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, + PAD_CTL_HYS | + PAD_CTL_PUS_22K_UP | + PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST), + MX51_PAD_EIM_EB3__FEC_RDATA1, + NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, PAD_CTL_HYS), + MX51_PAD_EIM_CS3__FEC_RDATA3, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_EIM_CS4__FEC_RX_ER, + /* PAD used on TS4800 */ + MX51_PAD_DI2_PIN2__FEC_MDC, + MX51_PAD_DISP2_DAT14__FEC_RDAT0, + MX51_PAD_DISP2_DAT10__FEC_COL, + MX51_PAD_DISP2_DAT11__FEC_RXCLK, + MX51_PAD_DISP2_DAT15__FEC_TDAT0, + MX51_PAD_DISP2_DAT6__FEC_TDAT1, + MX51_PAD_DISP2_DAT7__FEC_TDAT2, + MX51_PAD_DISP2_DAT8__FEC_TDAT3, + MX51_PAD_DISP2_DAT9__FEC_TX_EN, + MX51_PAD_DISP2_DAT13__FEC_TX_CLK, + MX51_PAD_DISP2_DAT12__FEC_RX_DV, + }; + + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0, + NO_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(1, 0)); + imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, + NO_PAD_CTRL)); + gpio_direction_input(IMX_GPIO_NR(1, 6)); + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + ret = !gpio_get_value(IMX_GPIO_NR(1, 0)); + else + ret = !gpio_get_value(IMX_GPIO_NR(1, 6)); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + static const iomux_v3_cfg_t sd1_pads[] = { + NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX | + PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX | + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST), + NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS), + NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS), + }; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_fec(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +/* + * Read the MAC address from FEC's registers PALR PAUR. + * User is supposed to configure these registers when MAC address is known + * from another source (fuse), but on TS4800, MAC address is not fused and + * the bootrom configure these registers on startup. + */ +static int fec_get_mac_from_register(uint32_t base_addr) +{ + unsigned char ethaddr[6]; + u32 reg_mac[2]; + int i; + + reg_mac[0] = in_be32(base_addr + 0xE4); + reg_mac[1] = in_be32(base_addr + 0xE8); + + for(i = 0; i < 6; i++) + ethaddr[i] = (reg_mac[i / 4] >> ((i % 4) * 8)) & 0xFF; + + if (is_valid_ethaddr(ethaddr)) { + eth_setenv_enetaddr("ethaddr", ethaddr); + return 0; + } + + return -1; +} + +#define TS4800_GPIO_FEC_PHY_RES IMX_GPIO_NR(2, 14) +int board_eth_init(bd_t *bd) +{ + int dev_id = -1; + int phy_id = 0xFF; + uint32_t addr = IMX_FEC_BASE; + + uint32_t base_mii; + struct mii_dev *bus = NULL; + struct phy_device *phydev = NULL; + int ret; + + /* reset FEC phy */ + imx_iomux_v3_setup_pad(MX51_PAD_EIM_A20__GPIO2_14); + gpio_direction_output(TS4800_GPIO_FEC_PHY_RES, 0); + mdelay(1); + gpio_set_value(TS4800_GPIO_FEC_PHY_RES, 1); + mdelay(1); + + base_mii = addr; + debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); + bus = fec_get_miibus(base_mii, dev_id); + if (!bus) + return -ENOMEM; + + phydev = phy_find_by_mask(bus, phy_id, PHY_INTERFACE_MODE_MII); + if (!phydev) { + free(bus); + return -ENOMEM; + } + + if (fec_get_mac_from_register(addr)) + printf("eth_init: failed to get MAC address\n"); + + ret = fec_probe(bd, dev_id, addr, bus, phydev); + if (ret) { + free(phydev); + free(bus); + } + + return ret; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int checkboard(void) +{ + puts("Board: TS4800\n"); + + return 0; +} + +void hw_watchdog_reset(void) +{ + struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE); + /* feed the watchdog for another 10s */ + writew(0x2, &wtd->feed); +} + +void hw_watchdog_init(void) +{ + return; +} diff --git a/board/technologic/ts4800/ts4800.h b/board/technologic/ts4800/ts4800.h new file mode 100644 index 0000000000..6856b0596a --- /dev/null +++ b/board/technologic/ts4800/ts4800.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2015 Savoir-faire Linux Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TS4800_H +#define _TS4800_H + +#define TS4800_SYSCON_BASE 0xb0010000 + +struct ts4800_wtd_regs { + u16 feed; +}; + +#endif diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index 29db838490..8656782d86 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -25,6 +25,7 @@ #include <mmc.h> #include <power/pfuze100_pmic.h> #include <power/pmic.h> +#include <spi_flash.h> #include "tqma6_bb.h" diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg deleted file mode 100644 index 1ac0aec773..0000000000 --- a/board/udoo/1066mhz_4x256mx16.cfg +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 - -DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB - -DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 - -DATA 4, MX6_MMDC_P0_MDOR, 0x00591023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 -DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 - -DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 - -DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 - -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266 - -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141 -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45 - -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035 -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001 -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001 - -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 - -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - diff --git a/board/udoo/MAINTAINERS b/board/udoo/MAINTAINERS index ee8b61e37e..789e98ff85 100644 --- a/board/udoo/MAINTAINERS +++ b/board/udoo/MAINTAINERS @@ -3,4 +3,4 @@ M: Fabio Estevam <fabio.estevam@freescale.com> S: Maintained F: board/udoo/ F: include/configs/udoo.h -F: configs/udoo_quad_defconfig +F: configs/udoo_defconfig diff --git a/board/udoo/Makefile b/board/udoo/Makefile index 80efadaf0d..1d6d9f891f 100644 --- a/board/udoo/Makefile +++ b/board/udoo/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := udoo.o +obj-y := udoo.o udoo_spl.o diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg deleted file mode 100644 index 9cd1af128f..0000000000 --- a/board/udoo/clocks.cfg +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0x00FFF300 -DATA 4, CCM_CCGR5, 0x0F0000C3 -DATA 4, CCM_CCGR6, 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF - -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4, MX6_IOMUXC_GPR6, 0x007F007F -DATA 4, MX6_IOMUXC_GPR7, 0x007F007F - diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg deleted file mode 100644 index 78cbe17db4..0000000000 --- a/board/udoo/ddr-setup.cfg +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* - * DDR3 settings - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), - * memory bus width: 64 bits x16/x32/x64 - * MX6DL ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 64 bits x16/x32/x64 - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 32 bits x16/x32 - */ -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 - -DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 - -DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 - -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 - -/* (differential input) */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -/* (differential input) */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -/* disable ddr pullups */ -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 - -/* Read data DQ Byte0-3 delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 - diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c index e9236d444c..a8bd90a42a 100644 --- a/board/udoo/udoo.c +++ b/board/udoo/udoo.c @@ -42,28 +42,28 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; static iomux_v3_cfg_t const usdhc3_pads[] = { - MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; static iomux_v3_cfg_t const wdog_pads[] = { - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D19__GPIO3_IO19, + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19), }; int mx6_rgmii_rework(struct phy_device *phydev) @@ -96,43 +96,43 @@ int mx6_rgmii_rework(struct phy_device *phydev) } static iomux_v3_cfg_t const enet_pads1[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), /* RGMII reset */ - MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* Ethernet power supply */ - MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; static iomux_v3_cfg_t const enet_pads2[] = { - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), + IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), }; static void setup_iomux_enet(void) { - imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + SETUP_IOMUX_PADS(enet_pads1); udelay(20); gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */ @@ -156,17 +156,17 @@ static void setup_iomux_enet(void) gpio_free(IMX_GPIO_NR(6, 28)); gpio_free(IMX_GPIO_NR(6, 29)); - imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + SETUP_IOMUX_PADS(enet_pads2); } static void setup_iomux_uart(void) { - imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + SETUP_IOMUX_PADS(uart2_pads); } static void setup_iomux_wdog(void) { - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + SETUP_IOMUX_PADS(wdog_pads); gpio_direction_output(WDT_TRG, 0); gpio_direction_output(WDT_EN, 1); gpio_direction_input(WDT_TRG); @@ -212,7 +212,7 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); usdhc_cfg.max_bus_width = 4; @@ -242,14 +242,29 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_CMD_SATA - setup_sata(); + if (is_cpu_type(MXC_CPU_MX6Q)) + setup_sata(); +#endif + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (is_cpu_type(MXC_CPU_MX6Q)) + setenv("board_rev", "MX6Q"); + else + setenv("board_rev", "MX6DL"); #endif return 0; } int checkboard(void) { - puts("Board: Udoo\n"); + if (is_cpu_type(MXC_CPU_MX6Q)) + puts("Board: Udoo Quad\n"); + else + puts("Board: Udoo DualLite\n"); return 0; } diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg deleted file mode 100644 index 8d7ff25f7f..0000000000 --- a/board/udoo/udoo.cfg +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) - */ -BOOT_FROM sd - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" -#include "1066mhz_4x256mx16.cfg" -#include "clocks.cfg" diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c new file mode 100644 index 0000000000..a1154edf69 --- /dev/null +++ b/board/udoo/udoo_spl.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2015 Udoo + * Author: Tungyi Lin <tungyilin1127@gmail.com> + * Richard Hu <hakahu@gmail.com> + * Based on board/wandboard/spl.c + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_SPL_BUILD) +#include <asm/arch/mx6-ddr.h> + +/* + * Driving strength: + * 0x30 == 40 Ohm + * 0x28 == 48 Ohm + */ +#define IMX6DQ_DRIVE_STRENGTH 0x30 +#define IMX6SDL_DRIVE_STRENGTH 0x28 + +/* configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH, + .dram_cas = IMX6DQ_DRIVE_STRENGTH, + .dram_ras = IMX6DQ_DRIVE_STRENGTH, + .dram_reset = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH, + .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6DQ_DRIVE_STRENGTH, + .grp_ctlds = IMX6DQ_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b1ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b2ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b3ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b4ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b5ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b6ds = IMX6DQ_DRIVE_STRENGTH, + .grp_b7ds = IMX6DQ_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, + .dram_cas = IMX6SDL_DRIVE_STRENGTH, + .dram_ras = IMX6SDL_DRIVE_STRENGTH, + .dram_reset = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, + .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, + .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6SDL_DRIVE_STRENGTH, + .grp_ctlds = IMX6SDL_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b1ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b2ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b3ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b4ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b5ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b6ds = IMX6SDL_DRIVE_STRENGTH, + .grp_b7ds = IMX6SDL_DRIVE_STRENGTH, +}; + +/* MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg mt41k128m16jt_125 = { + /* quad = 1066, duallite = 800 */ + .mem_speed = 1066, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + +static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = { + .p0_mpwldectrl0 = 0x00350035, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00010001, + .p1_mpwldectrl1 = 0x00010001, + .p0_mpdgctrl0 = 0x43510360, + .p0_mpdgctrl1 = 0x0342033F, + .p1_mpdgctrl0 = 0x033F033F, + .p1_mpdgctrl1 = 0x03290266, + .p0_mprddlctl = 0x4B3E4141, + .p1_mprddlctl = 0x47413B4A, + .p0_mpwrdlctl = 0x42404843, + .p1_mpwrdlctl = 0x4C3F4C45, +}; + +static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { + .p0_mpwldectrl0 = 0x002F0038, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x001F001F, + .p1_mpwldectrl1 = 0x001F001F, + .p0_mpdgctrl0 = 0x425C0251, + .p0_mpdgctrl1 = 0x021B021E, + .p1_mpdgctrl0 = 0x021B021E, + .p1_mpdgctrl1 = 0x01730200, + .p0_mprddlctl = 0x45474C45, + .p1_mprddlctl = 0x44464744, + .p0_mpwrdlctl = 0x3F3F3336, + .p1_mpwrdlctl = 0x32383630, +}; + +/* DDR 64bit 1GB */ +static struct mx6_ddr_sysinfo mem_qdl = { + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + /* quad = 2, duallite = 1 */ + .rtt_nom = 2, + /* quad = 2, duallite = 1 */ + .rtt_wr = 2, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* set the default clock gate to save power */ + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000FF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void spl_dram_init(void) +{ + if (is_cpu_type(MXC_CPU_MX6DL)) { + mt41k128m16jt_125.mem_speed = 800; + mem_qdl.rtt_nom = 1; + mem_qdl.rtt_wr = 1; + + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125); + } else if (is_cpu_type(MXC_CPU_MX6Q)) { + mt41k128m16jt_125.mem_speed = 1066; + mem_qdl.rtt_nom = 2; + mem_qdl.rtt_wr = 2; + + mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125); + } + + udelay(100); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + gpr_init(); + + /* iomux */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/zeus/Kconfig b/board/zeus/Kconfig deleted file mode 100644 index 67796508f3..0000000000 --- a/board/zeus/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_ZEUS - -config SYS_BOARD - default "zeus" - -config SYS_CONFIG_NAME - default "zeus" - -endif diff --git a/board/zeus/MAINTAINERS b/board/zeus/MAINTAINERS deleted file mode 100644 index 3118710cd4..0000000000 --- a/board/zeus/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ZEUS BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/zeus/ -F: include/configs/zeus.h -F: configs/zeus_defconfig diff --git a/board/zeus/Makefile b/board/zeus/Makefile deleted file mode 100644 index aa3658a370..0000000000 --- a/board/zeus/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = zeus.o update.o diff --git a/board/zeus/README b/board/zeus/README deleted file mode 100644 index 1848d8cd38..0000000000 --- a/board/zeus/README +++ /dev/null @@ -1,73 +0,0 @@ - -Storage of the board specific values (ethaddr...) -------------------------------------------------- - -The board specific environment variables that should be unique -for each individual board, can be stored in the I2C EEPROM. This -will be done from offset 0x80 with the length of 0x80 bytes. The -following command can be used to store the values here: - -=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001 - - ethaddr eth1addr serial# - -Now those 3 values are stored into the I2C EEPROM. A CRC is added -to make sure that the values get not corrupted. - - -SW-Reset Pushbutton handling: ------------------------------ - -The SW-reset push button is connected to a GPIO input too. This -way U-Boot can "see" how long the SW-reset was pressed, and a -specific action can be taken. Two different actions are supported: - -a) Release after more than 5 seconds and less then 10 seconds: - -> Run POST - - Please note, that the POST test will take a while (approx. 1 min - on the 128MByte board). This is mainly due to the system memory - test. - -b) Release after more than 10 seconds: - -> Restore factory default settings - - The factory default values are restored. The default environment - variables are restored (ipaddr, serverip...) and the board - specific values (ethaddr, eth1addr and serial#) are restored - to the environment from the I2C EEPROM. Also a bootline parameter - is added to the Linux bootline to signal the Linux kernel upon - the next startup, that the factory defaults should be restored. - -The command to check this sw-reset status and act accordingly is - -=> chkreset - -This command is added to the default "bootcmd", so that it is called -automatically upon startup. - -Also, the 2 LED's are used to indicate the current status of this -command (time passed since pushing the button). When the POST test -will be run, the green LED will be switched off, and when the -factory restore will be initiated, the reg LED will be switched off. - - -Loggin of POST results: ------------------------ - -The results of the POST tests are logged in a logbuffer located at the end -of the onboard memory. It can be accessed with the U-Boot command "log": - -=> log show -<4>POST memory PASSED -<4>POST cache PASSED -<4>POST cpu PASSED -<4>POST uart PASSED -<4>POST ethernet PASSED - -The DENX Linux kernel tree has support for this log buffer included. Exactly -this buffer is used for logging of all kernel messages too. By enabling the -compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you -can access the U-Boot log messages from Linux too. - -2007-08-10, Stefan Roese <sr@denx.de> diff --git a/board/zeus/update.c b/board/zeus/update.c deleted file mode 100644 index ac738ef2ab..0000000000 --- a/board/zeus/update.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <i2c.h> - -#if defined(CONFIG_ZEUS) - -u8 buf_zeus_ce[] = { -/*00 01 02 03 04 05 06 07 */ - 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*08 09 0a 0b 0c 0d 0e 0f */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*10 11 12 13 14 15 16 17 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*18 19 1a 1b 1c 1d 1e 1f */ - 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 }; - -u8 buf_zeus_pe[] = { - -/* CPU_CLOCK_DIV 1 = 00 - CPU_PLB_FREQ_DIV 3 = 10 - OPB_PLB_FREQ_DIV 2 = 01 - EBC_PLB_FREQ_DIV 2 = 00 - MAL_PLB_FREQ_DIV 1 = 00 - PCI_PLB_FRQ_DIV 3 = 10 - PLL_PLLOUTA = IS SET - PLL_OPERATING = IS NOT SET - PLL_FDB_MUL 10 = 1010 - PLL_FWD_DIV_A 3 = 101 - PLL_FWD_DIV_B 3 = 101 - TUNE = 0x2be */ -/*00 01 02 03 04 05 06 07 */ - 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*08 09 0a 0b 0c 0d 0e 0f */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*10 11 12 13 14 15 16 17 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -/*18 19 1a 1b 1c 1d 1e 1f */ - 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 }; - -static int update_boot_eeprom(void) -{ - u32 len = 0x20; - u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR; - u8 *pbuf; - u8 base; - int i; - - if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) { - pbuf = buf_zeus_pe; - base = 0x40; - } else { - pbuf = buf_zeus_ce; - base = 0x00; - } - - for (i = 0; i < len; i++, base++) { - if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) { - printf("i2c_write fail\n"); - return 1; - } - udelay(11000); - } - - return 0; -} - -int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[]) -{ - return update_boot_eeprom(); -} - -U_BOOT_CMD ( - update_boot_eeprom, 1, 1, do_update_boot_eeprom, - "update boot eeprom content", - "" -); - -#endif diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c deleted file mode 100644 index e2b12f677e..0000000000 --- a/board/zeus/zeus.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <environment.h> -#include <logbuff.h> -#include <post.h> - -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define REBOOT_MAGIC 0x07081967 -#define REBOOT_NOP 0x00000000 -#define REBOOT_DO_POST 0x00000001 - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -ulong flash_get_size(ulong base, int banknum); -void env_crc_update(void); - -static u32 start_time; - -int board_early_init_f(void) -{ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); - mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - - /* - * Configure CPC0_PCI to enable PerWE as output - */ - mtdcr(CPC0_PCI, CPC0_PCI_SPE); - - return 0; -} - -int misc_init_r(void) -{ - u32 pbcr; - int size_val = 0; - u32 post_magic; - u32 post_val; - - post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC); - post_val = in_be32((void *)CONFIG_SYS_POST_VAL); - if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) { - /* - * Set special bootline bootparameter to pass this POST boot - * mode to Linux to reset the username/password - */ - setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes"); - - /* - * Normally don't run POST tests, only when enabled - * via the sw-reset button. So disable further tests - * upon next bootup here. - */ - out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP); - } else { - /* - * Only run POST when initiated via the sw-reset button mechanism - */ - post_word_store(0); - } - - /* - * Get current time - */ - start_time = get_timer(0); - - /* - * FLASH stuff... - */ - - /* Re-do sizing to get full correct info */ - - /* adjust flash start and offset */ - mfebc(PB0CR, pbcr); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(PB0CR, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Zeus-"); - - if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) - puts("PE"); - else - puts("CE"); - - puts(" of BulletEndPoint"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - /* both LED's off */ - gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0); - gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0); - udelay(10000); - /* and on again */ - gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 1); - gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 1); - - return (0); -} - -static int default_env_var(char *buf, char *var) -{ - char *ptr; - char *val; - - /* - * Find env variable - */ - ptr = strstr(buf + 4, var); - if (ptr == NULL) { - printf("ERROR: %s not found!\n", var); - return -1; - } - ptr += strlen(var) + 1; - - /* - * Now the ethaddr needs to be updated in the "normal" - * environment storage -> redundant flash. - */ - val = ptr; - setenv(var, val); - printf("Updated %s from eeprom to %s!\n", var, val); - - return 0; -} - -static int restore_default(void) -{ - char *buf; - char *buf_save; - u32 crc; - - set_default_env(""); - - gd->env_valid = 1; - - /* - * Read board specific values from I2C EEPROM - * and set env variables accordingly - * -> ethaddr, eth1addr, serial# - */ - buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); - if (buf == NULL) { - printf("ERROR: malloc() failed\n"); - return -1; - } - if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, - (u8 *)buf, FACTORY_RESET_ENV_SIZE)) { - puts("\nError reading EEPROM!\n"); - } else { - crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4); - if (crc != *(u32 *)buf) { - printf("ERROR: crc mismatch %08x %08x\n", crc, *(u32 *)buf); - return -1; - } - - default_env_var(buf, "ethaddr"); - buf += 8 + 18; - default_env_var(buf, "eth1addr"); - buf += 9 + 18; - default_env_var(buf, "serial#"); - } - - /* - * Finally save updated env variables back to flash - */ - saveenv(); - - free(buf_save); - - return 0; -} - -int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *buf; - char *buf_save; - char str[32]; - u32 crc; - char var[32]; - - if (argc < 4) { - puts("ERROR!\n"); - return -1; - } - - buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); - memset(buf, 0, FACTORY_RESET_ENV_SIZE); - - strcpy(var, "ethaddr"); - printf("Setting %s to %s\n", var, argv[1]); - sprintf(str, "%s=%s", var, argv[1]); - strcpy(buf + 4, str); - buf += strlen(str) + 1; - - strcpy(var, "eth1addr"); - printf("Setting %s to %s\n", var, argv[2]); - sprintf(str, "%s=%s", var, argv[2]); - strcpy(buf + 4, str); - buf += strlen(str) + 1; - - strcpy(var, "serial#"); - printf("Setting %s to %s\n", var, argv[3]); - sprintf(str, "%s=%s", var, argv[3]); - strcpy(buf + 4, str); - - crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4); - *(u32 *)buf_save = crc; - - if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, - (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) { - puts("\nError writing EEPROM!\n"); - return -1; - } - - free(buf_save); - - return 0; -} - -U_BOOT_CMD( - setdef, 4, 1, do_set_default, - "write board-specific values to EEPROM (ethaddr...)", - "ethaddr eth1addr serial#\n - write board-specific values to EEPROM" - ); - -static inline int sw_reset_pressed(void) -{ - return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET)); -} - -int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[]) -{ - int delta; - int count = 0; - int post = 0; - int factory_reset = 0; - - if (!sw_reset_pressed()) { - printf("SW-Reset already high (Button released)\n"); - printf("-> No action taken!\n"); - return 0; - } - - printf("Waiting for SW-Reset button to be released."); - - while (1) { - delta = get_timer(start_time); - if (!sw_reset_pressed()) - break; - - if ((delta > CONFIG_SYS_TIME_POST) && !post) { - printf("\nWhen released now, POST tests will be started."); - gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0); - post = 1; - } - - if ((delta > CONFIG_SYS_TIME_FACTORY_RESET) && !factory_reset) { - printf("\nWhen released now, factory default values" - " will be restored."); - gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0); - factory_reset = 1; - } - - udelay(1000); - if (!(count++ % 1000)) - printf("."); - } - - - printf("\nSW-Reset Button released after %d milli-seconds!\n", delta); - - if (delta > CONFIG_SYS_TIME_FACTORY_RESET) { - printf("Starting factory reset value restoration...\n"); - - /* - * Restore default setting - */ - restore_default(); - - /* - * Reset the board for default to become valid - */ - do_reset(NULL, 0, 0, NULL); - - return 0; - } - - if (delta > CONFIG_SYS_TIME_POST) { - printf("Starting POST configuration...\n"); - - /* - * Enable POST upon next bootup - */ - out_be32((void *)CONFIG_SYS_POST_MAGIC, REBOOT_MAGIC); - out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_DO_POST); - post_bootmode_init(); - - /* - * Reset the logbuffer for a clean start - */ - logbuff_reset(); - - do_reset(NULL, 0, 0, NULL); - - return 0; - } - - return 0; -} - -U_BOOT_CMD ( - chkreset, 1, 1, do_chkreset, - "Check for status of SW-reset button and act accordingly", - "" -); - -#if defined(CONFIG_POST) -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - u32 post_magic; - u32 post_val; - - post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC); - post_val = in_be32((void *)CONFIG_SYS_POST_VAL); - - if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) - return 1; - else - return 0; -} -#endif /* CONFIG_POST */ diff --git a/configs/T1024QDS_D4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig index f69c49d241..f69c49d241 100644 --- a/configs/T1024QDS_D4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig new file mode 100644 index 0000000000..174fbcab97 --- /dev/null +++ b/configs/T1024QDS_DDR4_defconfig @@ -0,0 +1,5 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4" +CONFIG_SPI_FLASH=y diff --git a/configs/T1040QDS_D4_defconfig b/configs/T1040QDS_DDR4_defconfig index 8c4320bf58..8c4320bf58 100644 --- a/configs/T1040QDS_D4_defconfig +++ b/configs/T1040QDS_DDR4_defconfig diff --git a/configs/alpr_defconfig b/configs/alpr_defconfig deleted file mode 100644 index b7cd74da3a..0000000000 --- a/configs/alpr_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_ALPR=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index e676f0ec0d..e43f6eb2a5 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_ARISTAINETOS2=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" # CONFIG_CMD_IMLS is not set diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig new file mode 100644 index 0000000000..af2dbc6ab8 --- /dev/null +++ b/configs/aristainetos2b_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_ARISTAINETOS2B=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_SPI_FLASH=y diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig index f5b0b6bf5a..e6affedb9c 100644 --- a/configs/aristainetos_defconfig +++ b/configs/aristainetos_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_ARISTAINETOS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL" # CONFIG_CMD_IMLS is not set diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig index 74f95277e8..0289a3fd4d 100644 --- a/configs/cgtqmx6qeval_defconfig +++ b/configs/cgtqmx6qeval_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_CGTQMX6EVAL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" # CONFIG_CMD_IMLS is not set diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 21c35e3d94..b50ababa03 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -28,5 +28,5 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y -CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y CONFIG_SYS_PROMPT="CM-FX6 # " +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/configs/cmi_mpc5xx_defconfig b/configs/cmi_mpc5xx_defconfig deleted file mode 100644 index abebfab999..0000000000 --- a/configs/cmi_mpc5xx_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_PPC=y -CONFIG_5xx=y -CONFIG_TARGET_CMI_MPC5XX=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -# CONFIG_CMD_NFS is not set diff --git a/configs/csb272_defconfig b/configs/csb272_defconfig deleted file mode 100644 index c9cc680951..0000000000 --- a/configs/csb272_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CSB272=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/csb472_defconfig b/configs/csb472_defconfig deleted file mode 100644 index e46b965517..0000000000 --- a/configs/csb472_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_CSB472=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index e294cac0b2..e45b077e3a 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_GW_VENTANA=y CONFIG_SPL=y CONFIG_SPL_STACK_R=y diff --git a/configs/lcd4_lwmon5_defconfig b/configs/lcd4_lwmon5_defconfig deleted file mode 100644 index b911dbd67d..0000000000 --- a/configs/lcd4_lwmon5_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_LWMON5=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5" -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/ls2085a_emu_D4_defconfig b/configs/ls2085a_emu_D4_defconfig deleted file mode 100644 index 9c82e17d64..0000000000 --- a/configs/ls2085a_emu_D4_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS2085A_EMU=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_FPGA is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_CMD_MISC is not set diff --git a/configs/ls2085a_emu_defconfig b/configs/ls2085a_emu_defconfig index fa4a44e856..9c82e17d64 100644 --- a/configs/ls2085a_emu_defconfig +++ b/configs/ls2085a_emu_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_LS2085A_EMU=y -CONFIG_SYS_EXTRA_OPTIONS="EMU" +CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4" # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig deleted file mode 100644 index 0a6da688cb..0000000000 --- a/configs/lwmon5_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_LWMON5=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 5ea278fee4..0707f0d298 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_EMBESTMX6BOARDS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 27fe22eb01..59362c661b 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6CUBOXI=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig index 6c1ba3361d..e1bdaafe9b 100644 --- a/configs/mx6dlarm2_defconfig +++ b/configs/mx6dlarm2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QARM2=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig index 4624a09dfe..a37c254a7d 100644 --- a/configs/mx6dlarm2_lpddr2_defconfig +++ b/configs/mx6dlarm2_lpddr2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QARM2=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index 756e5dbff4..17d1b96751 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index de9999851b..6610a0c93f 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SABRESD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig index 42dbded343..5cd78cd300 100644 --- a/configs/mx6qarm2_defconfig +++ b/configs/mx6qarm2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QARM2=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig index 5f9105fd9a..89c42b8510 100644 --- a/configs/mx6qarm2_lpddr2_defconfig +++ b/configs/mx6qarm2_lpddr2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QARM2=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig index 293e3f27a5..2cbbc32b0a 100644 --- a/configs/mx6qpsabreauto_defconfig +++ b/configs/mx6qpsabreauto_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q" CONFIG_SPI_FLASH=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index 9343bcce5a..11ded404ad 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index 427fbee322..1a2bb221d3 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 732c1dce61..6cbe1cfbb6 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SABRESD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig index d93a40dbe3..bfd371a322 100644 --- a/configs/mx6sabresd_spl_defconfig +++ b/configs/mx6sabresd_spl_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SABRESD=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index dcc3296a3b..ae9912b2a6 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SLEVK=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 964a147cac..39046164ef 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SLEVK=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig new file mode 100644 index 0000000000..1fbd0d1d3e --- /dev/null +++ b/configs/mx6slevk_spl_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6SL" +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index e6e4db5c48..a582905327 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SXSABRESD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX" # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig index df3489409c..3f196590c4 100644 --- a/configs/mx6sxsabresd_spl_defconfig +++ b/configs/mx6sxsabresd_spl_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_MX6SXSABRESD=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 29159a1bf7..57dbad2250 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -1,4 +1,8 @@ CONFIG_ARM=y -CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_ARCH_MX6=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" +CONFIG_TARGET_MX6UL_14X14_EVK=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 6cbc0e3089..2044fc9d15 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048" # CONFIG_CMD_IMLS is not set diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 055266ca36..c90c8c9762 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024" # CONFIG_CMD_IMLS is not set diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 7b5ccc7ab9..90ef17eeeb 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048" # CONFIG_CMD_IMLS is not set diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index 5cc245ed01..798467ece0 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024" # CONFIG_CMD_IMLS is not set diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index b613a491c2..e8eca1b016 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024" # CONFIG_CMD_IMLS is not set diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index b7cd09abcc..d142ebc116 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_NITROGEN6X=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512" # CONFIG_CMD_IMLS is not set diff --git a/configs/novena_defconfig b/configs/novena_defconfig index aca98b7245..60d6658217 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_KOSAGI_NOVENA=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index ea789345ff..17022a43de 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_OT1200=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q" # CONFIG_CMD_IMLS is not set diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index 3c7346b5ce..dbbea35cf0 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_OT1200=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" diff --git a/configs/p3p440_defconfig b/configs/p3p440_defconfig deleted file mode 100644 index 84e683b083..0000000000 --- a/configs/p3p440_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_P3P440=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/pcs440ep_defconfig b/configs/pcs440ep_defconfig deleted file mode 100644 index b01f63a7be..0000000000 --- a/configs/pcs440ep_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_PCS440EP=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig index 64da7c449b..2e4e879b74 100644 --- a/configs/platinum_picon_defconfig +++ b/configs/platinum_picon_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_PLATINUM_PICON=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6DL" diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig index 67957c3830..0c8e32f577 100644 --- a/configs/platinum_titanium_defconfig +++ b/configs/platinum_titanium_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_PLATINUM_TITANIUM=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q" diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index fd18e2de95..859b14323e 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_EMBESTMX6BOARDS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC" # CONFIG_CMD_IMLS is not set diff --git a/configs/sbc405_defconfig b/configs/sbc405_defconfig deleted file mode 100644 index 0bc0ab229d..0000000000 --- a/configs/sbc405_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_SBC405=y -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/stxgp3_defconfig b/configs/stxgp3_defconfig deleted file mode 100644 index 816092d8c9..0000000000 --- a/configs/stxgp3_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_STXGP3=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="GPPP=> " diff --git a/configs/stxssa_4M_defconfig b/configs/stxssa_4M_defconfig deleted file mode 100644 index 75479060e1..0000000000 --- a/configs/stxssa_4M_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_STXSSA=y -CONFIG_SYS_EXTRA_OPTIONS="STXSSA_4M" -# CONFIG_CMD_SETEXPR is not set diff --git a/configs/stxssa_defconfig b/configs/stxssa_defconfig deleted file mode 100644 index ec812c1c8e..0000000000 --- a/configs/stxssa_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_STXSSA=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_SYS_PROMPT="SSA=> " diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 745d32edd5..822aec37ed 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_TBS2910=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_DM=y diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig index d286fd61fe..de3c78dc38 100644 --- a/configs/titanium_defconfig +++ b/configs/titanium_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_TITANIUM=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg" # CONFIG_CMD_IMLS is not set diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index c9a304d8c0..e30b130c14 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -7,5 +7,4 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n" CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068" -CONFIG_SPI_FLASH=y CONFIG_PCA9551_LED=y diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig new file mode 100644 index 0000000000..a2fa541c79 --- /dev/null +++ b/configs/ts4800_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_TARGET_TS4800=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig new file mode 100644 index 0000000000..e4f1d8d3de --- /dev/null +++ b/configs/udoo_defconfig @@ -0,0 +1,7 @@ +CONFIG_SPL=y +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y +CONFIG_TARGET_UDOO=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" diff --git a/configs/udoo_quad_defconfig b/configs/udoo_quad_defconfig deleted file mode 100644 index 42c21c69d4..0000000000 --- a/configs/udoo_quad_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_UDOO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 62666ffca7..595e4be53d 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_WANDBOARD=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" diff --git a/configs/warp_defconfig b/configs/warp_defconfig index dacb4320da..423f82037a 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARCH_MX6=y CONFIG_TARGET_WARP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL" # CONFIG_CMD_IMLS is not set diff --git a/configs/zeus_defconfig b/configs/zeus_defconfig deleted file mode 100644 index da2ff3c6ad..0000000000 --- a/configs/zeus_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_PPC=y -CONFIG_4xx=y -CONFIG_TARGET_ZEUS=y -# CONFIG_CMD_SETEXPR is not set diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index 72a1d595f5..30e05da574 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -1,7 +1,8 @@ U-boot config options used in fec_mxc.c CONFIG_FEC_MXC - Selects fec_mxc.c to be compiled into u-boot. + Selects fec_mxc.c to be compiled into u-boot. Can read out the + ethaddr from the SoC eFuses (see below). CONFIG_MII Must be defined if CONFIG_FEC_MXC is defined. @@ -25,3 +26,9 @@ CONFIG_FEC_MXC_NO_ANEG CONFIG_FEC_MXC_PHYADDR Optional, selects the exact phy address that should be connected and function fecmxc_initialize will try to initialize it. + + +Reading the ethaddr from the SoC eFuses: +if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the +ethaddr variable, then its value gets read from the corresponding eFuses in +the SoC. See the README files of the specific SoC for details. diff --git a/doc/README.imx5 b/doc/README.imx5 index c5312b69d3..ea0e144ced 100644 --- a/doc/README.imx5 +++ b/doc/README.imx5 @@ -26,3 +26,15 @@ i.MX5x SoCs. 2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the natural MAC byte order (i.e. MSB first). + + This is an example how to program an example MAC address 01:23:45:67:89:ab + into the eFuses. Assure that the programming voltage is available and then + execute: + + => fuse prog -y 1 9 01 23 45 67 89 ab + + After programming a MAC address, consider locking the MAC fuses. This is + done by programming the MAC_ADDR_LOCK fuse, which is bit 4 of word 0 in + bank 1: + + => fuse prog -y 1 0 10 diff --git a/doc/README.scrapyard b/doc/README.scrapyard index fb1ed42320..9cda0bdedc 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,7 +12,17 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -cam_enc_4xx arm arm926ejs - - Heiko Schocher <hs@denx.de> +stxgp3 powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com> +stxssa powerpc mpc85xx - - Dan Malek <dan@embeddedalley.com> +cmi_mpc5xx powerpc mpc5xx - - +zeus powerpc ppc4xx - - Stefan Roese <sr@denx.de> +sbc405 powerpc ppc4xx - - +pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de> +p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de> +lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de> +csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com> +alpr powerpc ppc4xx - - Stefan Roese <sr@denx.de> +cam_enc_4xx arm arm926ejs 8d775763 2015-08-20 Heiko Schocher <hs@denx.de> atstk1003 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> atstk1004 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> atstk1006 avr32 - e5354b8a 2015-06-10 Haavard Skinnemoen <haavard.skinnemoen@atmel.com> diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 0c48320966..70fe5b6a4e 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -40,16 +40,18 @@ static unsigned long gpio_ports[] = { [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ - defined(CONFIG_MX53) || defined(CONFIG_MX6) + defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_MX7) [3] = GPIO4_BASE_ADDR, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ + defined(CONFIG_MX7) [4] = GPIO5_BASE_ADDR, #ifndef CONFIG_MX6UL [5] = GPIO6_BASE_ADDR, #endif #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) #ifndef CONFIG_MX6UL [6] = GPIO7_BASE_ADDR, #endif diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 5218b91c0b..8d0fc3c5cb 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -35,3 +35,4 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_RESET) += reset-uclass.o +obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c index 44cd9b9fd4..a592891f26 100644 --- a/drivers/misc/fsl_debug_server.c +++ b/drivers/misc/fsl_debug_server.c @@ -60,29 +60,29 @@ int debug_server_parse_firmware_fit_image(const void **raw_image_addr, /* Check if Image is in FIT format */ format = genimg_get_format(fit_hdr); if (format != IMAGE_FORMAT_FIT) { - printf("Error! Not a FIT image\n"); + printf("Debug Server FW: Not a FIT image\n"); goto out_error; } if (!fit_check_format(fit_hdr)) { - printf("Error! Bad FIT image format\n"); + printf("Debug Server FW: Bad FIT image format\n"); goto out_error; } node_offset = fit_image_get_node(fit_hdr, uname); if (node_offset < 0) { - printf("Error! Can not find %s subimage\n", uname); + printf("Debug Server FW:Can not find %s subimage\n", uname); goto out_error; } /* Verify Debug Server firmware image */ if (!fit_image_verify(fit_hdr, node_offset)) { - printf("Error! Bad Debug Server firmware hash"); + printf("Debug Server FW: Bad Debug Server firmware hash"); goto out_error; } if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) { - printf("Error! Failed to get Debug Server fw description"); + printf("Debug Server FW: Failed to get FW description"); goto out_error; } diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c new file mode 100644 index 0000000000..996f45c281 --- /dev/null +++ b/drivers/misc/fsl_devdis.c @@ -0,0 +1,29 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Author: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch-ls102xa/immap_ls102xa.h> +#include <asm/arch-ls102xa/config.h> +#include <linux/compiler.h> +#include <hwconfig.h> +#include <fsl_devdis.h> + +void device_disable(const struct devdis_table *tbl, uint32_t num) +{ + int i; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + /* + * Extract hwconfig from environment and disable unused device. + */ + for (i = 0; i < num; i++) { + if (hwconfig_sub("devdis", tbl[i].name)) + setbits_be32(&gur->devdisr + tbl[i].offset, + tbl[i].mask); + } +} + diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index d92044eeda..65ff8158e5 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -25,8 +25,21 @@ #define BM_CTRL_ERROR 0x00000200 #define BM_CTRL_BUSY 0x00000100 #define BO_CTRL_ADDR 0 +#ifdef CONFIG_MX7 +#define BM_CTRL_ADDR 0x0000000f +#define BM_CTRL_RELOAD 0x00000400 +#else #define BM_CTRL_ADDR 0x0000007f - +#endif + +#ifdef CONFIG_MX7 +#define BO_TIMING_FSOURCE 12 +#define BM_TIMING_FSOURCE 0x0007f000 +#define BV_TIMING_FSOURCE_NS 1001 +#define BO_TIMING_PROG 0 +#define BM_TIMING_PROG 0x00000fff +#define BV_TIMING_PROG_US 10 +#else #define BO_TIMING_STROBE_READ 16 #define BM_TIMING_STROBE_READ 0x003f0000 #define BV_TIMING_STROBE_READ_NS 37 @@ -36,6 +49,7 @@ #define BO_TIMING_STROBE_PROG 0 #define BM_TIMING_STROBE_PROG 0x00000fff #define BV_TIMING_STROBE_PROG_US 10 +#endif #define BM_READ_CTRL_READ_FUSE 0x00000001 @@ -43,6 +57,68 @@ #define WRITE_POSTAMBLE_US 2 +#if defined(CONFIG_MX6) || defined(CONFIG_VF610) +#define FUSE_BANK_SIZE 0x80 +#ifdef CONFIG_MX6SL +#define FUSE_BANKS 8 +#else +#define FUSE_BANKS 16 +#endif +#elif defined CONFIG_MX7 +#define FUSE_BANK_SIZE 0x40 +#define FUSE_BANKS 16 +#else +#error "Unsupported architecture\n" +#endif + +#if defined(CONFIG_MX6) +#include <asm/arch/sys_proto.h> + +/* + * There is a hole in shadow registers address map of size 0x100 + * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. + * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, + * we should account for this hole in address space. + * + * Similar hole exists between bank 14 and bank 15 of size + * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. + * Note: iMX6SL has only 0-7 banks and there is no hole. + * Note: iMX6UL doesn't have this one. + * + * This function is to covert user input to physical bank index. + * Only needed when read fuse, because we use register offset, so + * need to calculate real register offset. + * When write, no need to consider hole, always use the bank/word + * index from fuse map. + */ +u32 fuse_bank_physical(int index) +{ + u32 phy_index; + + if (is_cpu_type(MXC_CPU_MX6SL)) { + phy_index = index; + } else if (is_cpu_type(MXC_CPU_MX6UL)) { + if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } else { + if (index >= 15) + phy_index = fuse_bank_physical(14) + (index - 15) + 2; + else if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } + return phy_index; +} +#else +u32 fuse_bank_physical(int index) +{ + return index; +} +#endif + static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) { while (readl(®s->ctrl) & BM_CTRL_BUSY) @@ -59,9 +135,9 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, { *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; - if (bank >= ARRAY_SIZE((*regs)->bank) || - word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || - !assert) { + if (bank >= FUSE_BANKS || + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || + !assert) { printf("mxc_ocotp %s(): Invalid argument\n", caller); return -EINVAL; } @@ -99,16 +175,38 @@ int fuse_read(u32 bank, u32 word, u32 *val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; ret = prepare_read(®s, bank, word, val, __func__); if (ret) return ret; - *val = readl(®s->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + + *val = readl(®s->bank[phy_bank].fuse_regs[word << 2]); return finish_access(regs, __func__); } +#ifdef CONFIG_MX7 +static void set_timing(struct ocotp_regs *regs) +{ + u32 ipg_clk; + u32 fsource, prog; + u32 timing; + + ipg_clk = mxc_get_clock(MXC_IPG_CLK); + + fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS, + + 1000000) + 1; + prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1; + + timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG); + + clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, + timing); +} +#else static void set_timing(struct ocotp_regs *regs) { u32 ipg_clk; @@ -130,12 +228,17 @@ static void set_timing(struct ocotp_regs *regs) clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | BM_TIMING_STROBE_PROG, timing); } +#endif static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, int write) { u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; +#ifdef CONFIG_MX7 + u32 addr = bank; +#else u32 addr = bank << 3 | word; +#endif set_timing(regs); clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR, @@ -155,7 +258,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val) setup_direct_access(regs, bank, word, false); writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl); wait_busy(regs, 1); +#ifdef CONFIG_MX7 + *val = readl((®s->read_fuse_data0) + (word << 2)); +#else *val = readl(®s->read_fuse_data); +#endif return finish_access(regs, __func__); } @@ -176,8 +283,38 @@ int fuse_prog(u32 bank, u32 word, u32 val) return ret; setup_direct_access(regs, bank, word, true); +#ifdef CONFIG_MX7 + switch (word) { + case 0: + writel(0, ®s->data1); + writel(0, ®s->data2); + writel(0, ®s->data3); + writel(val, ®s->data0); + break; + case 1: + writel(val, ®s->data1); + writel(0, ®s->data2); + writel(0, ®s->data3); + writel(0, ®s->data0); + break; + case 2: + writel(0, ®s->data1); + writel(val, ®s->data2); + writel(0, ®s->data3); + writel(0, ®s->data0); + break; + case 3: + writel(0, ®s->data1); + writel(0, ®s->data2); + writel(val, ®s->data3); + writel(0, ®s->data0); + break; + } + wait_busy(regs, BV_TIMING_PROG_US); +#else writel(val, ®s->data); wait_busy(regs, BV_TIMING_STROBE_PROG_US); +#endif udelay(WRITE_POSTAMBLE_US); return finish_access(regs, __func__); @@ -187,12 +324,15 @@ int fuse_override(u32 bank, u32 word, u32 val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; ret = prepare_write(®s, bank, word, __func__); if (ret) return ret; - writel(val, ®s->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + + writel(val, ®s->bank[phy_bank].fuse_regs[word << 2]); return finish_access(regs, __func__); } diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c index 6f0a1d3e6d..6c0d247ed2 100644 --- a/drivers/misc/mxs_ocotp.c +++ b/drivers/misc/mxs_ocotp.c @@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val) /* Return the original HCLK clock speed. */ *val = readl(&clkctrl_regs->hw_clkctrl_hbus); *val &= CLKCTRL_HBUS_DIV_MASK; + *val >>= CLKCTRL_HBUS_DIV_OFFSET; /* Scale the HCLK to 454/19 = 23.9 MHz . */ scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index c5dcbbbced..bff5fd1119 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -17,6 +17,7 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/imx-common/sys_proto.h> #include <asm/io.h> #include <asm/errno.h> #include <linux/compiler.h> @@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd) writel(0x00000000, &fec->eth->gaddr2); - /* clear MIB RAM */ - for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) - writel(0, i); + /* Do not access reserved register for i.MX6UL */ + if (!is_cpu_type(MXC_CPU_MX6UL)) { + /* clear MIB RAM */ + for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) + writel(0, i); - /* FIFO receive start register */ - writel(0x520, &fec->eth->r_fstart); + /* FIFO receive start register */ + writel(0x520, &fec->eth->r_fstart); + } /* size and address of each buffer */ writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 9a8a007861..b3ff4c50db 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ +#include <errno.h> #include <common.h> #include <asm/io.h> #include <asm/fsl_serdes.h> @@ -230,7 +231,7 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) __attribute__((weak, alias("__def_board_ft_fman_fixup_port"))); -static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) +int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) { int off; uint32_t ph; @@ -239,11 +240,13 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; off = fdt_node_offset_by_compat_reg(blob, prop, paddr); + if (off == -FDT_ERR_NOTFOUND) + return -EINVAL; if (info->enabled) { fdt_fixup_phy_connection(blob, off, info->enet_if); board_ft_fman_fixup_port(blob, prop, paddr, info->port, off); - return ; + return 0; } #ifdef CONFIG_SYS_FMAN_V3 @@ -281,7 +284,7 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4))) #endif ) - return; + return 0; #endif /* board code might have caused offset to change */ off = fdt_node_offset_by_compat_reg(blob, prop, paddr); @@ -294,6 +297,8 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ph = fdt_get_phandle(blob, off); do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph), "status", "disabled", strlen("disabled") + 1, 1); + + return 0; } void fdt_fixup_fman_ethernet(void *blob) @@ -305,10 +310,18 @@ void fdt_fixup_fman_ethernet(void *blob) ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac"); #else for (i = 0; i < ARRAY_SIZE(fm_info); i++) { - if (fm_info[i].type == FM_ETH_1G_E) - ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac"); - else - ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac"); + /* Try the new compatible first. + * If the node is missing, try the old. + */ + if (fm_info[i].type == FM_ETH_1G_E) { + if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec")) + ft_fixup_port(blob, &fm_info[i], + "fsl,fman-1g-mac"); + } else { + if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec")) + ft_fixup_port(blob, &fm_info[i], + "fsl,fman-10g-mac"); + } } #endif } diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 20a67466a7..941d0760b5 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -347,6 +347,16 @@ static struct phy_driver VSC8514_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8584_driver = { + .name = "Vitesse VSC8584", + .uid = 0x707c0, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8574_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + static struct phy_driver VSC8601_driver = { .name = "Vitesse VSC8601", .uid = 0x70420, @@ -417,6 +427,7 @@ int phy_vitesse_init(void) phy_register(&VSC8211_driver); phy_register(&VSC8221_driver); phy_register(&VSC8574_driver); + phy_register(&VSC8584_driver); phy_register(&VSC8514_driver); phy_register(&VSC8662_driver); phy_register(&VSC8664_driver); diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 42d037471f..4bdc188c8f 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -271,9 +271,6 @@ void redundant_init(struct eth_device *dev) out_be32(®s->tstat, TSTAT_CLEAR_THALT); out_be32(®s->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); -#ifdef CONFIG_LS102XA - setbits_be32(®s->dmactrl, DMACTRL_LE); -#endif do { uint16_t status; @@ -370,9 +367,6 @@ static void startup_tsec(struct eth_device *dev) out_be32(®s->tstat, TSTAT_CLEAR_THALT); out_be32(®s->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); -#ifdef CONFIG_LS102XA - setbits_be32(®s->dmactrl, DMACTRL_LE); -#endif } /* This returns the status bits of the device. The return value diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 95cfe8c16f..2f24a6a39b 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -689,6 +689,7 @@ void fdt_fixup_smmu_pcie(void *blob) { int count; u32 stream_ids[MAX_STREAM_IDS]; + u32 ctlr_streamid = 0x300; #ifdef CONFIG_PCIE1 /* PEX1 stream ID fixup */ @@ -696,6 +697,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE2 @@ -704,6 +707,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE3 @@ -712,6 +717,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE4 @@ -720,6 +727,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000", + &ctlr_streamid, 1); #endif } #endif diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 8f6463e127..00fde71b2c 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o +obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c new file mode 100644 index 0000000000..ac807a801f --- /dev/null +++ b/drivers/power/pmic/pmic_pfuze3000.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Peng Fan <Peng.Fan@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> + +int power_pfuze3000_init(unsigned char bus) +{ + static const char name[] = "PFUZE3000"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = PMIC_NUM_OF_REGS; + p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index c84bbc647f..e5e1be134c 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -49,6 +49,8 @@ #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ +#define RTC_STAT_BIT_BB32KHZ 0x40 /* Battery backed 32KHz Output */ +#define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz Output */ static uchar rtc_read (uchar reg); @@ -141,6 +143,14 @@ void rtc_reset (void) rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2); } +/* + * Enable 32KHz output + */ +void rtc_enable_32khz_output(void) +{ + rtc_write(RTC_STAT_REG_ADDR, + RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ); +} /* * Helper functions diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 7ddda9f205..ccb80d2d1d 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -120,7 +120,7 @@ config ROCKCHIP_SERIAL config SANDBOX_SERIAL bool "Sandbox UART support" - depends on SANDBOX && DM + depends on SANDBOX help Select this to enable a seral UART for sandbox. This is required to operate correctly, otherwise you will see no serial output from @@ -140,7 +140,7 @@ config SANDBOX_SERIAL config UNIPHIER_SERIAL bool "Support for UniPhier on-chip UART" - depends on ARCH_UNIPHIER && DM_SERIAL + depends on ARCH_UNIPHIER help If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N. diff --git a/drivers/video/lg4573.c b/drivers/video/lg4573.c index 43670fc320..11fef279a9 100644 --- a/drivers/video/lg4573.c +++ b/drivers/video/lg4573.c @@ -220,7 +220,8 @@ err_claim_bus: static int do_lgset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0); + lg4573_spi_startup(CONFIG_LG4573_BUS, CONFIG_LG4573_CS, 10000000, + SPI_MODE_0); return 0; } diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 1c74e97c5e..868c51254d 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -419,8 +419,7 @@ void *video_hw_init (void) board_disp_init (); #endif -#if (defined(CONFIG_LWMON5) || \ - defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) +#if defined(CONFIG_SOCRATES) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) /* Lamp on */ board_backlight_switch (1); #endif diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index ad3f52ac92..1e458f44f6 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -460,13 +460,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 931816bf36..a42c93690d 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -18,6 +18,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index d24d1ca522..8942aae3ef 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d7aa5011f4..67fac70294 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -11,6 +11,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index eef1b1e506..842afe1421 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 675ca874f6..2e8db5a67b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 5a481d5207..fabe6bf0cf 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -18,6 +18,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 05e5a3d08e..7a2131bb41 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ad8082950b..9e38724710 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index de56c489cd..9a487e0a23 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 2f78e05c57..92f51f6fd6 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -475,13 +475,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 386d0e6e82..324f7108d5 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -476,13 +476,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS #endif diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a0390a845b..1f4616011a 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -380,7 +380,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 39273377da..cd5b3e2ada 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -432,7 +432,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 19f07f8697..23ca0cfceb 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -430,7 +430,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index b0d8399fdd..ef42b88854 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -390,7 +390,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index edc03c3414..d43f6b7ea4 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -179,7 +179,7 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ diff --git a/include/configs/alpr.h b/include/configs/alpr.h deleted file mode 100644 index f113ebd74b..0000000000 --- a/include/configs/alpr.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_ALPR 1 /* Board is ebony */ -#define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 - - -#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000) -#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_TEMP_STACK_OCM 1 -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ -#undef CONFIG_SDRAM_ECC /* enable ECC support */ -#define CONFIG_SYS_SDRAM_TABLE { \ - {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ - {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (PCF8594C) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ - /* 8 byte page write mode using */ - /* last 3 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run kernelx\" to boot the system;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth3\0" \ - "hostname=alpr\0" \ - "fdt_file=alpr/alpr.dtb\0" \ - "fdt_addr=400000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} ${init}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ - "mem=193M\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "net_nfs_fdt=tftp 200000 ${bootfile};" \ - "tftp ${fdt_addr} ${fdt_file};" \ - "run nfsargs addip addtty;" \ - "bootm 200000 - ${fdt_addr}\0" \ - "rootpath=/opt/projects/alpr/nfs_root\0" \ - "bootfile=/alpr/uImage\0" \ - "kernel_addr=fff00000\0" \ - "ramdisk_addr=fff10000\0" \ - "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "ethprime=ppc_4xx_eth3\0" \ - "ethact=ppc_4xx_eth3\0" \ - "autoload=no\0" \ - "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \ - "load_fpga=fpga load 0 ffe00000 10dd9a\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \ - "rootfstype=jffs2 init=/sbin/init\0" \ - "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\ - ";bootm 200000\0" \ - "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \ - "addtty;bootm 200000\0" \ - "kernel1=setenv actkernel 'kernel1';run load_fpga " \ - "kernel1_mtd\0" \ - "kernel2=setenv actkernel 'kernel2';run load_fpga " \ - "kernel2_mtd\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run kernel2" - -#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ -#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ -#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ -#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FPGA_LOADMK -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PCI - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ -#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ -#define CONFIG_SYS_PCI_MASTER_INIT - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/*----------------------------------------------------------------------- - * FPGA stuff - *-----------------------------------------------------------------------*/ -#define CONFIG_FPGA -#define CONFIG_FPGA_ALTERA -#define CONFIG_FPGA_CYCLON2 -#define CONFIG_SYS_FPGA_CHECK_CTRLC -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in - Reihe geschaltet -> sollte gehen, - aufpassen mit Datasize ist jetzt - halt doppelt so gross ... Seite 306 - ist das mit den multiple Device in PS - Mode erklaert ...*/ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ -#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */ -#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ -#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ -#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ - -#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */ -#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */ -#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */ - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup - *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6) -#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9) -#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26) -#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14) -#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15) - -/*----------------------------------------------------------------------- - * NAND-FLASH stuff - *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ - CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } -#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */ -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 4a5d4fb080..20afdd6bc0 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -45,7 +45,6 @@ #define CONFIG_SPI_FLASH_MTD #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MXC_SPI -#define CONFIG_SF_DEFAULT_BUS 3 #define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN @@ -106,9 +105,6 @@ "ubiboot=echo Booting from ubi ...; " \ "run ubiargs addmtd addmisc set_fit_default;" \ "bootm ${fit_addr_r}\0" \ - "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " \ "rescueargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/ram rw\0 " \ "rescueboot=echo Booting rescue system from NOR ...; " \ diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h index 258866a473..be93debfa1 100644 --- a/include/configs/aristainetos.h +++ b/include/configs/aristainetos.h @@ -22,6 +22,7 @@ #define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_SF_DEFAULT_BUS 3 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ @@ -32,7 +33,10 @@ "addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " + "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \ + "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \ + "ubifsload ${fit_addr_r} /boot/system.itb; " \ + "imi ${fit_addr_r}\0 " #define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) #define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index faeafe2dda..152f5e919a 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -24,6 +24,7 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_PHY_MICREL_KSZ9031 +#define CONFIG_SF_DEFAULT_BUS 3 #define CONFIG_SF_DEFAULT_CS 1 #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ @@ -34,7 +35,10 @@ "-(rescue-system);gpmi-nand:-(ubi)\0" \ "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " + "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ + "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ + "ubifsload ${fit_addr_r} /boot/system.itb; " \ + "imi ${fit_addr_r}\0 " #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ @@ -45,6 +49,8 @@ /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 33246000 #define CONFIG_LG4573 +#define CONFIG_LG4573_BUS 0 +#define CONFIG_LG4573_CS 0 #define CONFIG_CMD_BMP diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h new file mode 100644 index 0000000000..78791db9a9 --- /dev/null +++ b/include/configs/aristainetos2b.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2015 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6DL aristainetos2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ARISTAINETOS2B_CONFIG_H +#define __ARISTAINETOS2B_CONFIG_H + +#define CONFIG_SYS_BOARD_VERSION 3 +#define CONFIG_HOSTNAME aristainetos2 +#define CONFIG_BOARDNAME "aristainetos2-revB" + +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_PHY_MICREL_KSZ9031 + +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 + +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "board_type=aristainetos2_7@1\0" \ + "nor_bootdelay=-2\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(rescue-system);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ + "ubiargs=setenv bootargs console=${console},${baudrate} " \ + "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ + "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ + "ubifsload ${fit_addr_r} /boot/system.itb; " \ + "imi ${fit_addr_r}\0 " \ + +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ + +#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) +#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) +#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) + +/* Framebuffer */ +#define CONFIG_SYS_LDB_CLOCK 33246000 +#define CONFIG_LG4573 +#define CONFIG_LG4573_BUS 0 +#define CONFIG_LG4573_CS 1 + +#define CONFIG_CMD_BMP + +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#include "aristainetos-common.h" + +#endif /* __ARISTAINETOS2B_CONFIG_H */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index fb5b82ee33..92930c8f72 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -97,6 +97,19 @@ #define CONFIG_LBA48 #define CONFIG_LIBATA +/* Ethernet */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + /* Command definition */ #define CONFIG_MXC_UART_BASE UART2_BASE diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index ddf6b5f131..12734a10bf 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -224,6 +224,7 @@ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ #define CONFIG_OF_BOARD_SETUP +#define CONFIG_MISC_INIT_R /* SPL */ #include "imx6_spl.h" diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h deleted file mode 100644 index d081865749..0000000000 --- a/include/configs/cmi_mpc5xx.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: cmi_mpc5xx.h - * - * Discription: Config header file for cmi - * board using an MPC5xx CPU - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_CMI 1 /* Using the customized cmi board */ - -#define CONFIG_SYS_TEXT_BASE 0x02000000 /* Boot from flash at location 0x00000000 */ - -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -#define CONFIG_BAUDRATE 57600 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_ASKENV - - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -#define CONFIG_STATUS_LED 1 /* Enable status led */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CONFIG_SYS_IMMR 0x01000000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ - -/* - * Start addresses for the final memory configuration - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CONFIG_SYS_FLASH_BASE 0x02000000 /* External flash */ -#define PLD_BASE 0x03000000 /* PLD */ -#define ANYBUS_BASE 0x03010000 /* Anybus Module */ - -#define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Physically section protection on */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CONFIG_ENV_SIZE 0x00010000 /* Set whole sector as env */ -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ -#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16) -#define CONFIG_SYS_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3) -#define CONFIG_SYS_BR1_PRELIM (ANYBUS_BASE) -#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR) -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32) -#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) -#define CONFIG_SYS_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) -#define CONFIG_SYS_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ - OR_ACS_10 | OR_ETHR | OR_CSNT) - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CONFIG_SYS_DER 0x00000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h deleted file mode 100644 index 71cb5dff36..0000000000 --- a/include/configs/csb272.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * OS Bootstrap configuration - * - */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#if 1 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm fe000000 fe100000" -#endif - -#if 0 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ -#undef CONFIG_SYS_BASE_BAUD -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CONFIG_ENV_IS_IN_NVRAM -#undef CONFIG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMSTART -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) -#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Miscellaneous board specific definitions - * - */ -#define CONFIG_SYS_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h deleted file mode 100644 index 5bd3867908..0000000000 --- a/include/configs/csb472.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * (C) Copyright 2004 - * Tolunay Orkun, Nextio Inc., torkun@nextio.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ -#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ -#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ -#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -/* - * OS Bootstrap configuration - * - */ - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ -#endif - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ - -#if 1 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/ram rw ramdisk_size=4096 " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm ff800000 ff900000" -#endif - -#if 0 -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs console=ttyS0,38400 debug " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -/* - * Serial download configuration - * - */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * KGDB Configuration - * - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - * - */ -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * watchdog configuration - * - */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * UART configuration - * - */ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */ -#define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 38400 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * I2C configuration - * - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F /* I2C slave address */ - -/* - * MII PHY configuration - * - */ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ - /* 32usec min. for LXT971A */ -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * RTC configuration - * - * Note that DS1307 RTC is limited to 100Khz I2C bus. - * - */ -#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ - -/* - * PCI stuff - * - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/* - * IDE stuff - * - */ -#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -/* - * Environment configuration - * - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ -#undef CONFIG_ENV_IS_IN_NVRAM -#undef CONFIG_ENV_IS_IN_EEPROM - -/* - * General Memory organization - * - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 0x00800000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_RAMSTART -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) -#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ -#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ -#endif - -/* - * FLASH Device configuration - * - */ -#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max # of sectors on one chip */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * On Chip Memory location/size - * - */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -/* - * Global info and initial stack - * - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Miscellaneous board specific definitions - * - */ -#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 9a70aaecbf..2d1f1b3db9 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -24,6 +24,8 @@ #define CONFIG_VIDEO #define CONFIG_PREBOOT +#define CONFIG_SYS_GENERIC_BOARD + /* * SoC Configuration */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 0a585b700b..1744f2c74c 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -61,7 +61,7 @@ #define CONFIG_SPL_LIBDISK_SUPPORT #endif -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) +#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6SL) #define CONFIG_SPL_BSS_START_ADDR 0x88200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START 0x88300000 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index dfaffa13d3..b44f3264e3 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -566,7 +566,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3299a9f593..7dcb719b01 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -414,7 +414,9 @@ #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 39fb464593..2dbb5f70a9 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -218,6 +218,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV +#define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_PING @@ -250,8 +251,8 @@ unsigned long long get_qixis_addr(void); "kernel_size=0x2800000\0" \ "console=ttyAMA0,38400n8\0" -#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0600,115200 " \ +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ + "earlycon=uart8250,mmio,0x21c0500,115200 " \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h index d0d2eedb6d..bd15b3d624 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2085a_simu.h @@ -127,6 +127,17 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +/* MMC */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index f818570e55..f7f3870032 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -355,6 +355,23 @@ unsigned long get_board_ddr_clk(void); #define SGMII_CARD_PORT3_PHY_ADDR 0x1E #define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "DPNI1" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index aee1216257..a190bc7c70 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -321,6 +321,12 @@ unsigned long get_board_sys_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ + "earlycon=uart8250,mmio,0x21c0600,115200 " \ + "ramdisk_size=0x2000000 default_hugepagesz=2m" \ + " hugepagesz=2m hugepages=16" + /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET #define CONFIG_PHYLIB_10G diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h deleted file mode 100644 index 513167e2ef..0000000000 --- a/include/configs/lwmon5.h +++ /dev/null @@ -1,692 +0,0 @@ -/* - * (C) Copyright 2007-2013 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * lwmon5.h - configuration for lwmon5 board - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Liebherr extra version info - */ -#define CONFIG_IDENT_STRING " - v2.0" - -/* - * High Level Configuration Options - */ -#define CONFIG_LWMON5 1 /* Board is lwmon5 */ -#define CONFIG_440EPX 1 /* Specific PPC440EPx */ -#define CONFIG_440 1 /* ... PPC440 family */ - -#ifdef CONFIG_LCD4_LWMON5 -#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ -#define CONFIG_HOSTNAME lcd4_lwmon5 -#else -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 -#define CONFIG_HOSTNAME lwmon5 -#endif - -#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ - -#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */ - -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ -#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ -#define CONFIG_MISC_INIT_R /* Call misc_init_r */ -#define CONFIG_BOARD_RESET /* Call board_reset */ - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ - -#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ -#define CONFIG_SYS_LIME_BASE_0 0xc0000000 -#define CONFIG_SYS_LIME_BASE_1 0xc1000000 -#define CONFIG_SYS_LIME_BASE_2 0xc2000000 -#define CONFIG_SYS_LIME_BASE_3 0xc3000000 -#define CONFIG_SYS_FPGA_BASE_0 0xc4000000 -#define CONFIG_SYS_FPGA_BASE_1 0xc4200000 -#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) -#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) -#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) - -#ifndef CONFIG_LCD4_LWMON5 -#define CONFIG_SYS_USB2D0_BASE 0xe0000100 -#define CONFIG_SYS_USB_DEVICE 0xe0000000 -#define CONFIG_SYS_USB_HOST 0xe0000400 -#endif - -/* - * Initial RAM & stack pointer - * - * On LWMON5 we use D-cache as init-ram and stack pointer. We also move - * the POST_WORD from OCM to a 440EPx register that preserves it's - * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) - * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) - */ -#ifndef CONFIG_LCD4_LWMON5 -#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#else -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) -#endif -/* unused GPT0 COMP reg */ -#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) -#define CONFIG_SYS_OCM_SIZE (16 << 10) -/* 440EPx errata CHIP 11: don't use last 4kbytes */ -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) - -/* Additional registers for watchdog timer post test */ -#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) -#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) -#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR -#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR -#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000 -#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000 -#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001 -#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 -#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 -#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 2 /* Use UART1 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ - -/* - * FLASH related - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH0 0xFC000000 -#define CONFIG_SYS_FLASH1 0xF8000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } - -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * DDR SDRAM - */ -#define CONFIG_SYS_MBYTES_SDRAM 256 -#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ -#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ -#ifndef CONFIG_LCD4_LWMON5 -#define CONFIG_DDR_ECC /* enable ECC */ -#endif - -#ifndef CONFIG_LCD4_LWMON5 -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_ECC | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_OCM | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_SPR | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_SYSMON | \ - CONFIG_SYS_POST_WATCHDOG | \ - CONFIG_SYS_POST_DSP | \ - CONFIG_SYS_POST_BSPEC1 | \ - CONFIG_SYS_POST_BSPEC2 | \ - CONFIG_SYS_POST_BSPEC3 | \ - CONFIG_SYS_POST_BSPEC4 | \ - CONFIG_SYS_POST_BSPEC5) - -/* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ - CONFIG_SYS_NS16550_COM2 } - -#define CONFIG_POST_UART { \ - "UART test", \ - "uart", \ - "This test verifies the UART operation.", \ - POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ - &uart_post_test, \ - NULL, \ - NULL, \ - CONFIG_SYS_POST_UART \ - } - -#define CONFIG_POST_WATCHDOG { \ - "Watchdog timer test", \ - "watchdog", \ - "This test checks the watchdog timer.", \ - POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ - &lwmon5_watchdog_post_test, \ - NULL, \ - NULL, \ - CONFIG_SYS_POST_WATCHDOG \ - } - -#define CONFIG_POST_BSPEC1 { \ - "dsPIC init test", \ - "dspic_init", \ - "This test returns result of dsPIC READY test run earlier.", \ - POST_RAM | POST_ALWAYS, \ - &dspic_init_post_test, \ - NULL, \ - NULL, \ - CONFIG_SYS_POST_BSPEC1 \ - } - -#define CONFIG_POST_BSPEC2 { \ - "dsPIC test", \ - "dspic", \ - "This test gets result of dsPIC POST and dsPIC version.", \ - POST_RAM | POST_ALWAYS, \ - &dspic_post_test, \ - NULL, \ - NULL, \ - CONFIG_SYS_POST_BSPEC2 \ - } - -#define CONFIG_POST_BSPEC3 { \ - "FPGA test", \ - "fpga", \ - "This test checks FPGA registers and memory.", \ - POST_RAM | POST_ALWAYS | POST_MANUAL, \ - &fpga_post_test, \ - NULL, \ - NULL, \ - CONFIG_SYS_POST_BSPEC3 \ - } - -#define CONFIG_POST_BSPEC4 { \ - "GDC test", \ - "gdc", \ - "This test checks GDC registers and memory.", \ - POST_RAM | POST_ALWAYS | POST_MANUAL,\ - &gdc_post_test, \ - NULL, \ - NULL, \ - CONFIG_SYS_POST_BSPEC4 \ - } - -#define CONFIG_POST_BSPEC5 { \ - "SYSMON1 test", \ - "sysmon1", \ - "This test checks GPIO_62_EPX pin indicating power failure.", \ - POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ - &sysmon1_post_test, \ - NULL, \ - NULL, \ - CONFIG_SYS_POST_BSPEC5 \ - } - -#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ -#define CONFIG_LOGBUFFER -/* Reserve GPT0_COMP1-COMP5 for logbuffer header */ -#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) -#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ -#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ -#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ -#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ -#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ -#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ -#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ - /* 64 byte page write mode using*/ - /* last 6 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE - -#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ -#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ -#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ - -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \ - CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\ - CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ - CONFIG_SYS_I2C_DSPIC_ADDR, \ - CONFIG_SYS_I2C_DSPIC_2_ADDR, \ - CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\ - CONFIG_SYS_I2C_DSPIC_IO_ADDR } - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -/* Update size in "reg" property of NOR FLASH device tree nodes */ -#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE - -#define CONFIG_FIT /* enable FIT image support */ - -#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ - -#define CONFIG_PREBOOT "setenv bootdelay 15" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=lwmon5\0" \ - "netdev=eth0\0" \ - "unlock=yes\0" \ - "logversion=2\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addtty addmisc;bootm\0" \ - "rootpath=/opt/eldk/ppc_4xxFP\0" \ - "bootfile=/tftpboot/lwmon5/uImage\0" \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC180000\0" \ - "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ - "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ - "cp.b 200000 FFF80000 80000\0" \ - "upd=run load update\0" \ - "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ - "autoscr 200000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ - -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_RESET_DELAY 300 - -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY1_ADDR 1 - -/* Video console */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define VIDEO_FB_16BPP_PIXEL_SWAP -#define VIDEO_FB_16BPP_WORD_SWAP - -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN - -#ifndef CONFIG_LCD4_LWMON5 -/* - * USB/EHCI - */ -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ -#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ -#define CONFIG_USB_STORAGE - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM - -#ifdef CONFIG_VIDEO -#define CONFIG_CMD_BMP -#endif - -#ifndef CONFIG_LCD4_LWMON5 -#ifdef CONFIG_440EPX -#define CONFIG_CMD_USB -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SUPPORT_VFAT - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ - -#ifndef CONFIG_LCD4_LWMON5 -#ifndef DEBUG -#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ -#endif -#define CONFIG_WD_PERIOD 40000 /* in usec */ -#define CONFIG_WD_MAX_RATE 66600 /* in ticks */ -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the 40x Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -/* - * External Bus Controller (EBC) Setup - */ -#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE - -/* Memory Bank 0 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x03000280 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) - -/* Memory Bank 1 (Lime) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01004380 -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) - -/* Memory Bank 2 (FPGA) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x01004400 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000) - -/* Memory Bank 3 (FPGA2) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x01004400 -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000) - -#define CONFIG_SYS_EBC_CFG 0xb8400000 - -/* - * Graphics (Fujitsu Lime) - */ -/* SDRAM Clock frequency adjustment register */ -#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 -#if 1 /* 133MHz is not tested enough, use 100MHz for now */ -/* Lime Clock frequency is to set 100MHz */ -#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 -#else -/* Lime Clock frequency for 133MHz */ -#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 -#endif - -/* SDRAM Parameter register */ -#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC -/* - * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars - * and pixel flare on display when 133MHz was configured. According to - * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed - * Grade - */ -#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ -#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 -#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ -#else -#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 -#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ -#endif - -/* - * GPIO Setup - */ -#define CONFIG_SYS_GPIO_PHY1_RST 12 -#define CONFIG_SYS_GPIO_FLASH_WP 14 -#define CONFIG_SYS_GPIO_PHY0_RST 22 -#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 -#define CONFIG_SYS_GPIO_DSPIC_READY 51 -#define CONFIG_SYS_GPIO_CAN_ENABLE 53 -#define CONFIG_SYS_GPIO_LSB_ENABLE 54 -#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 -#define CONFIG_SYS_GPIO_HIGHSIDE 56 -#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 -#define CONFIG_SYS_GPIO_BOARD_RESET 58 -#define CONFIG_SYS_GPIO_LIME_S 59 -#define CONFIG_SYS_GPIO_LIME_RST 60 -#define CONFIG_SYS_GPIO_SYSMON_STATUS 62 -#define CONFIG_SYS_GPIO_WATCHDOG 63 - -/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */ -#ifdef CONFIG_LCD4_LWMON5 -#define GPIO49_VAL 0 -#else -#define GPIO49_VAL 1 -#endif - -/* - * PPC440 GPIO Configuration - */ -#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ -{ \ -/* GPIO Core 0 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ -}, \ -{ \ -/* GPIO Core 1 */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ -} \ -} - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * SPL related defines - */ -#ifdef CONFIG_LCD4_LWMON5 -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_NOR_SUPPORT -#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ -#define CONFIG_SYS_SPL_MAX_LEN (64 << 10) -#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ -#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ -#define CONFIG_SPL_SERIAL_SUPPORT - -/* Place BSS for SPL near end of SDRAM */ -#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20) -#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) - -#define CONFIG_SPL_OS_BOOT -/* Place patched DT blob (fdt) at this address */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 - -#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin" - -/* Settings for real U-Boot to be loaded from NOR flash */ -#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_UBOOT_START 0x01002100 - -#define CONFIG_SYS_OS_BASE 0xf8000000 -#define CONFIG_SYS_FDT_BASE 0xf87c0000 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3cecd94039..04d53a7f08 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -11,6 +11,13 @@ #include "mx6_common.h" +#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#include "imx6_spl.h" +#endif + #define MACH_TYPE_MX6SLEVK 4307 #define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 848bdcd674..74d04a088f 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -15,6 +15,7 @@ #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 6ae736f154..4a2280bc18 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -20,7 +20,6 @@ #define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" -#define CONFIG_MX6 #define CONFIG_ROM_UNIFIED_SECTIONS #define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO @@ -221,6 +220,27 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE RMII +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#endif +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_FEC_DMA_MINALIGN 64 +#endif + #define CONFIG_IMX6_THERMAL #endif diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index e09e617f73..8bd36340e7 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -14,25 +14,16 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON -/* Common ARM Erratas */ -#define CONFIG_ARM_ERRATA_454179 -#define CONFIG_ARM_ERRATA_430973 -#define CONFIG_ARM_ERRATA_621766 +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define CONFIG_SYS_TEXT_BASE 0x80400000 -#define CONFIG_SDRC /* The chip has SDRC controller */ - -#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap.h> - +#include <configs/ti_omap3_common.h> +#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ /* * Display CPU and Board information */ + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -55,25 +46,14 @@ */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* * Hardware drivers */ /* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* * select serial console configuration */ +#undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 #define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */ @@ -92,7 +72,6 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=omap2-nand.0" @@ -120,32 +99,24 @@ /* * TWL4030 */ -#define CONFIG_TWL4030_POWER + /* * Board NAND Info. */ +#define CONFIG_SYS_NAND_BASE NAND_BASE #define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ #define CONFIG_SYS_NAND_BUSWIDTH_16BIT -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ + /* Environment information */ -#define CONFIG_BOOTDELAY 2 /* * PREBOOT assumes the 4.3" display is attached. User can interrupt @@ -239,17 +210,13 @@ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - /* * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). @@ -292,12 +259,8 @@ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) /* * SMSC922x Ethernet diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h deleted file mode 100644 index eb1400337d..0000000000 --- a/include/configs/p3p440.h +++ /dev/null @@ -1,302 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * board/config_p3p440.h - configuration for Prodrive P3P440 - ***********************************************************************/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_P3P440 1 /* Board is P3P440 */ -#define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_440 1 /* ... PPC440 family */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ - -#define CONFIG_SYS_USB_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000) - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in internal SRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ -#define CONFIG_SDRAM_ECC /* enable ECC support */ -#define CONFIG_SYS_SDRAM_TABLE { \ - {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ - {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ - -/*----------------------------------------------------------------------- - * I2C RTC - *----------------------------------------------------------------------*/ -#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */ - -/*----------------------------------------------------------------------- - * I2C EEPROM (PCF8594C) for environment - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ - /* 8 byte page write mode using */ - /* last 3 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ - -/*----------------------------------------------------------------------- - * Default configuration (environment varibles...) - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=p3p440\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/p3p440/uImage\0" \ - "kernel_addr=ff800000\0" \ - "ramdisk_addr=ff810000\0" \ - "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "unlock=yes\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0x1c /* PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */ -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_SNTP - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------*/ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ - -#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH0 0xFF800000 -#define CONFIG_SYS_FLASH1 0xFF000000 -#define CONFIG_SYS_FLASH2 0xFE800000 -#define CONFIG_SYS_FLASH3 0xFE000000 -#define CONFIG_SYS_USB 0xF0000000 - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x03050200 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x03050200 -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x03050200 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x03050200 -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */ - -/* Memory Bank 7 (USB controller) initialization */ -#define CONFIG_SYS_EBC_PB7AP 0x02015000 -#define CONFIG_SYS_EBC_PB7CR (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } - -#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif -#endif /* __CONFIG_H */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h deleted file mode 100644 index 77e20cf8da..0000000000 --- a/include/configs/pcs440ep.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * pcs440ep.h - configuration for PCS440EP board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - - -/* new uImage format support */ -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_PCS440EP 1 /* Board is PCS440EP */ -#define CONFIG_440EP 1 /* Specific PPC440EP support */ -#define CONFIG_440 1 /* ... PPC440 family */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000 - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -/*----------------------------------------------------------------------- - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 - -/*Don't change either of these*/ -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ -/*Don't change either of these*/ - -#define CONFIG_SYS_USB_DEVICE 0x50000000 -#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 - -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -#define CONFIG_ENV_OVERWRITE 1 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -#define ENV_NAME_REVLEV "revision_level" -#define ENV_NAME_SOLDER "solder_switch" -#define ENV_NAME_DIP "dip" - -/*----------------------------------------------------------------------- - * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#undef CONFIG_DDR_ECC /* don't use ECC */ -#define SPD_EEPROM_ADDRESS {0x50} -#define CONFIG_PROG_SDRAM_TLB 1 - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1) -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=pcs440ep\0" \ - "use_eeprom_ethaddr=default\0" \ - "cs_test=off\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/pcs440ep/uImage\0" \ - "kernel_addr=FFF00000\0" \ - "ramdisk_addr=FFF00000\0" \ - "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 100000 FFFA0000 60000\0" \ - "upd=run load update\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -/* check U-Boot image with SHA1 sum */ -#define CONFIG_SHA1_CHECK_UB_IMG 1 -#define CONFIG_SHA1_START CONFIG_SYS_MONITOR_BASE -#define CONFIG_SHA1_LEN CONFIG_SYS_MONITOR_LEN - -/*----------------------------------------------------------------------- - * Definitions for status LED - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 - -#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ -#define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ -#define STATUS_LED_PERIOD1 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE1 STATUS_LED_ON -#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ -#define STATUS_LED_PERIOD2 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ -#define STATUS_LED_PERIOD3 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE3 STATUS_LED_OFF - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ -#define CONFIG_PHY1_ADDR 2 - -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef CONFIG_440EP -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/*Comment this out to enable USB 1.1 device*/ -#define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ - -#ifdef DEBUG -#define CONFIG_PANIC_HANG -#else -#define CONFIG_HW_WATCHDOG /* watchdog */ -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_USB - -#define CONFIG_SUPPORT_VFAT - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT -#define CONFIG_SYS_PCI_MASTER_INIT - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ -#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */ - -#define CONFIG_SYS_FLASH FLASH_BASE0_PRELIM -#define CONFIG_SYS_SRAM 0xF1000000 -#define CONFIG_SYS_FPGA 0xF2000000 -#define CONFIG_SYS_CF1 0xF0000000 -#define CONFIG_SYS_CF2 0xF0100000 - -/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */ -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ - -/* Memory Bank 1 (SRAM) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */ -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 2 (FPGA) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */ -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */ - -/* Memory Bank 3 (CompactFlash) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x080BD400 -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ - -/* Memory Bank 4 (CompactFlash) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x080BD400 -#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * PPC440 GPIO Configuration - */ -#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ -{ \ -/* GPIO Core 0 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ -}, \ -{ \ -/* GPIO Core 1 */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ -{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \ -} \ -} - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 -#define CONFIG_IDE_RESET 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF1 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0000) - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h deleted file mode 100644 index b2adea976a..0000000000 --- a/include/configs/sbc405.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * (C) Copyright 2001 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405GP 1 /* This is a PPC405 CPU */ -#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo" - -#define CONFIG_RAMBOOT \ - "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOT \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */ - - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \ - "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \ - "f=0x08 tn=sbc405 o=emac \0" \ - "env_startaddr=FF000000\0" \ - "env_endaddr=FF03FFFF\0" \ - "loadfile=vxWorks.st\0" \ - "loadaddr=0x01000000\0" \ - "net_load=tftpboot ${loadaddr} ${loadfile}\0" \ - "uboot_startaddr=FFFC0000\0" \ - "uboot_endaddr=FFFFFFFF\0" \ - "update=tftp ${loadaddr} u-boot.bin;" \ - "protect off ${uboot_startaddr} ${uboot_endaddr};" \ - "era ${uboot_startaddr} ${uboot_endaddr};" \ - "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \ - "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \ - "zapenv=protect off ${env_startaddr} ${env_endaddr};" \ - "era ${env_startaddr} ${env_endaddr};" \ - "protect on ${env_startaddr} ${env_endaddr}\0" - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_ENV_OVERWRITE - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ - -#define CONFIG_IPADDR 192.168.193.102 -#define CONFIG_NETMASK 255.255.255.224 -#define CONFIG_SERVERIP 192.168.193.119 -#define CONFIG_GATEWAYIP 192.168.193.97 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_BASE_BAUD 691200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ - -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 -#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * Environment Variable setup - */ -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ -#define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ - -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Definitions for Serial Presence Detect EEPROM address - * (to get SDRAM settings) - */ -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h deleted file mode 100644 index 25b7d5f6a6..0000000000 --- a/include/configs/stxgp3.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * (C) Copyright 2003 Embedded Edge, LLC - * Dan Malek <dan@embeddededge.com> - * Copied from ADS85xx. - * Updates for Silicon Tx GP3 8560 board. - * - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ -#define CONFIG_MPC8560 1 - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support*/ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* sysclk for MPC85xx - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ - -/* Blinkin' LEDs for Robert :-) -*/ -#define CONFIG_SHOW_ACTIVITY 1 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - - -/* Localbus SDRAM is an option, not all boards have it. - * This address, however, is used to configure a 256M local bus - * window that includes the Config latch below. - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -/* The configuration latch is Chip Select 1. - * It's an 8-bit latch in the lower 8 bits of the word. - */ -#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */ -#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ -#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#endif -#define CONFIG_SYS_CCSRBAR 0xfdf00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#undef CONFIG_FSL_DDR_INTERACTIVE - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -/* local bus definitions */ -#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#if 0 -#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ -#else -/* I did the 'if 0' so we could keep the syntax above if ever needed. */ -#undef CONFIG_SYS_I2C_NOPROBES -#endif - -/* RapdIO Map configuration, mapped 1:1. -*/ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ - -/* Standard 8560 PCI addressing, mapped 1:1. -*/ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ - -#if defined(CONFIG_PCI) /* PCI Ethernet card */ - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII 1 /* MII PHY management */ - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - -#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#if 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) -#else - #define CONFIG_SYS_FCC_PSMR 0 -#endif - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* MDIO is done through the TSEC0 control. -*/ -#define CONFIG_MII /* MII PHY management */ -#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#endif - -/* Environment */ -/* We use the top boot sector flash, so we have some 16K sectors for env - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) - #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" -#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_CMD_ELF -#endif - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_SERVERIP 192.168.85.1 -#define CONFIG_IPADDR 192.168.85.60 -#define CONFIG_GATEWAYIP 192.168.85.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME STX_GP3 -#define CONFIG_ROOTPATH "/gppproot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x1000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h deleted file mode 100644 index ee16fea3ae..0000000000 --- a/include/configs/stxssa.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * (C) Copyright 2005 Embedded Alley Solutions, Inc. - * Dan Malek <dan@embeddedalley.com> - * Copied from STx GP3. - * Updates for Silicon Tx GP3 SSA board. - * - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao <X.Xiao@motorola.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ -#define CONFIG_MPC8560 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF80000 - -#define CONFIG_PCI /* PCI ethernet support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support*/ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* sysclk for MPC85xx - */ - -#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ - -/* Blinkin' LEDs for Robert :-) -*/ -#define CONFIG_SHOW_ACTIVITY 1 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - - -/* Localbus connector. There are many options that can be - * connected here, including sdram or lots of flash. - * This address, however, is used to configure a 256M local bus - * window that includes the Config latch below. - */ -#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */ -#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */ - -/* There are various flash options used, we configure for the largest, - * which is 64Mbytes. The CFI works fine and will discover the proper - * sizes. - */ -#ifdef CONFIG_STXSSA_4M -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */ -#else -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */ -#endif -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */ -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7) - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_FLASH_PROTECTION - -/* The configuration latch is Chip Select 1. - * It's an 8-bit latch in the lower 8 bits of the word. - */ -#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */ -#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ -#endif - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SYS_FSL_DDR1 -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#undef CONFIG_FSL_DDR_INTERACTIVE - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -/* local bus definitions */ -#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 2 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#undef CONFIG_SYS_I2C_NOPROBES - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* I2C EEPROM. AT24C32, we keep our environment in here. -*/ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Standard 8555 PCI mapping. - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ - -#if defined(CONFIG_PCI) /* PCI Ethernet card */ -#define CONFIG_MPC85XX_PCI2 1 -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#define CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII 1 /* MII PHY management */ - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define CONFIG_ETHPRIME "TSEC0" - -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ - -#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#if 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) -#else - #define CONFIG_SYS_FCC_PSMR 0 -#endif - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* MDIO is done through the TSEC0 control. -*/ -#define CONFIG_MII /* MII PHY management */ -#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -#endif - -/* Environment - default config is in flash, see below */ -#if 0 /* in EEPROM */ -# define CONFIG_ENV_IS_IN_EEPROM 1 -# define CONFIG_ENV_OFFSET 0 -# define CONFIG_ENV_SIZE 2048 -#else /* in flash */ -# define CONFIG_ENV_IS_IN_FLASH 1 -# ifdef CONFIG_STXSSA_4M -# define CONFIG_ENV_SECT_SIZE 0x20000 -# else /* default configuration - 64 MiB flash */ -# define CONFIG_ENV_SECT_SIZE 0x40000 -# endif -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE 0x4000 -# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#if !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_CMD_ELF -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -/* - * Environment in EEPROM is compatible with different flash sector sizes, - * but only little space is available, so we use a very simple setup. - * With environment in flash, we use a more powerful default configuration. - */ -#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */ - -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ -#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate" -#define CONFIG_SERVERIP 192.168.85.1 -#define CONFIG_IPADDR 192.168.85.60 -#define CONFIG_GATEWAYIP 192.168.85.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_HOSTNAME STX_SSA -#define CONFIG_ROOTPATH "/gppproot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x1000000 - -#else /* ENV IS IN FLASH -- use a full-blown envionment */ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=gp3ssa\0" \ - "bootfile=/tftpboot/gp3ssa/uImage\0" \ - "loadaddr=400000\0" \ - "netdev=eth0\0" \ - "consdev=ttyS1\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ - "rootpath=/opt/eldk/ppc_85xx\0" \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC200000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* CONFIG_ENV_IS_IN_EEPROM */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 356220edb4..d3138feb70 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -123,7 +123,7 @@ #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 1c86bc0701..1330a0a591 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -68,4 +68,12 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_BOOTCOUNT_BE +/* + * Remove all unused interfaces / commands that are defined in + * the common header tqms6.h + */ +#undef CONFIG_CMD_SF +#undef CONFIG_CMD_SPI +#undef CONFIG_MXC_SPI + #endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h new file mode 100644 index 0000000000..21f1555eb7 --- /dev/null +++ b/include/configs/ts4800.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2015, Savoir-faire Linux Inc. + * + * Derived from MX51EVK code by + * Guennadi Liakhovetski <lg@denx.de> + * Freescale Semiconductor, Inc. + * + * Configuration settings for the TS4800 Board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MX51 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_NO_FLASH /* No NOR Flash */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-boot is a 2nd stage bootloader */ + +#define CONFIG_HW_WATCHDOG + +#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX + +/* text base address used when linking */ +#define CONFIG_SYS_TEXT_BASE 0x90008000 + +#include <asm/arch/imx-regs.h> + +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* use common/board_f.c instead of arch/<arch>/lib/<board>.c */ +#define CONFIG_SYS_GENERIC_BOARD + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +/* + * Hardware drivers + */ + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_MXC_GPIO + +/* + * SPI Configs + * */ +#define CONFIG_HARD_SPI /* puts SPI: ready */ +#define CONFIG_MXC_SPI /* driver for the SPI controllers*/ +#define CONFIG_CMD_SPI /* SPI serial bus support */ + +/* + * MMC Configs + * */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR + +#define CONFIG_MMC + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* + * Eth Configs + */ +#define CONFIG_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ +#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */ +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ + +#define CONFIG_CMD_BOOTZ +#undef CONFIG_CMD_IMLS + +/* Environment variables */ + +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=uImage\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \ + "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs addtty; " \ + "bootm; " + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Low level init */ +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 +#define CONFIG_SYS_MAIN_PWR_ON + +/*----------------------------------------------------------------------- + * Environment organization + */ + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#endif diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 910bf01688..8ec073d343 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -11,6 +11,10 @@ #include "mx6_common.h" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" + #define MACH_TYPE_UDOO 4800 #define CONFIG_MACH_TYPE MACH_TYPE_UDOO @@ -18,6 +22,7 @@ #define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE @@ -58,7 +63,7 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb" +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ @@ -67,7 +72,7 @@ "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x18000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ @@ -134,9 +139,17 @@ "fi; " \ "else " \ "bootz; " \ - "fi;\0" + "fi;\0" \ + "findfdt=" \ + "if test $board_rev = MX6Q ; then " \ + "setenv fdt_file imx6q-udoo.dtb; fi; " \ + "if test $board_rev = MX6DL ; then " \ + "setenv fdt_file imx6dl-udoo.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ diff --git a/include/configs/zeus.h b/include/configs/zeus.h deleted file mode 100644 index 2bc4e1a9fe..0000000000 --- a/include/configs/zeus.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************************************ - * zeus.h - configuration for Zeus board - ***********************************************************************/ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*----------------------------------------------------------------------- - * High Level Configuration Options - *----------------------------------------------------------------------*/ -#define CONFIG_ZEUS 1 /* Board is Zeus */ -#define CONFIG_405EP 1 /* Specifc 405EP support*/ - -#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 - -#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - -#define PLLMR0_DEFAULT PLLMR0_333_111_55_111 -#define PLLMR1_DEFAULT PLLMR1_333_111_55_111 - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 - -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0x01 /* PHY address */ -#define CONFIG_HAS_ETH1 1 -#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ -#define CONFIG_PHY_RESET 1 -#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_ETHER) - -#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ - -/* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } - -#define CONFIG_LOGBUFFER -#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/*----------------------------------------------------------------------- - * SDRAM - *----------------------------------------------------------------------*/ -/* - * SDRAM configuration (please see cpu/ppc/sdram.[ch]) - */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ -#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ - -/* SDRAM timings used in datasheet */ -#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ -#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ -#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ -#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ -#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ - -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PPC4XX -#define CONFIG_SYS_I2C_PPC4XX_CH0 -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F - -/* these are for the ST M24C02 2kbit serial i2c eeprom */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * The layout of the I2C EEPROM, used for bootstrap setup and for board- - * specific values, like ethaddr... that can be restored via the sw-reset - * button - */ -#define FACTORY_RESET_I2C_EEPROM 0x50 -#define FACTORY_RESET_ENV_OFFS 0x80 -#define FACTORY_RESET_ENV_SIZE 0x80 - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory (OCM) for temperary stack until sdram is tested */ -#define CONFIG_SYS_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 -#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* reserve some memory for POST and BOOT limit info */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16) - -/* extra data in OCM */ -#define CONFIG_SYS_POST_MAGIC \ - (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8) -#define CONFIG_SYS_POST_VAL \ - (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12) - -/*----------------------------------------------------------------------- - * External Bus Controller (EBC) Setup - */ - -/* Memory Bank 0 (Flash 16M) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x05815600 -#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ - -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */ -#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */ -#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 -#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ -#define CONFIG_SYS_GPIO0_ODR 0x00000000 - -#define CONFIG_SYS_GPIO_SW_RESET 1 -#define CONFIG_SYS_GPIO_ZEUS_PE 12 -#define CONFIG_SYS_GPIO_LED_RED 22 -#define CONFIG_SYS_GPIO_LED_GREEN 23 - -/* Time in milli-seconds */ -#define CONFIG_SYS_TIME_POST 5000 -#define CONFIG_SYS_TIME_FACTORY_RESET 10000 - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP - -/* ENVIRONMENT VARS */ - -#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo" -#define CONFIG_IPADDR 192.168.1.10 -#define CONFIG_SERVERIP 192.168.1.100 -#define CONFIG_GATEWAYIP 192.168.1.100 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "logversion=2\0" \ - "hostname=zeus\0" \ - "netdev=eth0\0" \ - "ethact=ppc_4xx_eth0\0" \ - "netmask=255.255.255.0\0" \ - "ramdisk_size=50000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw" \ - " nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw" \ - " ramdisk_size=${ramdisk_size}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0," \ - "${baudrate}\0" \ - "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \ - "run nfsargs addip addtty;bootm\0" \ - "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \ - "tftp ${ramdisk_mem_addr} ${file_fs};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \ - "rootpath=/target_fs/zeus\0" \ - "kernel_fl_addr=ff000000\0" \ - "kernel_mem_addr=200000\0" \ - "ramdisk_fl_addr=ff300000\0" \ - "ramdisk_mem_addr=4000000\0" \ - "uboot_fl_addr=fffc0000\0" \ - "uboot_mem_addr=100000\0" \ - "file_uboot=/zeus/u-boot.bin\0" \ - "tftp_uboot=tftp 100000 ${file_uboot}\0" \ - "update_uboot=protect off fffc0000 ffffffff;" \ - "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \ - "protect on fffc0000 ffffffff\0" \ - "upd_uboot=run tftp_uboot;run update_uboot\0" \ - "file_kernel=/zeus/uImage_ba\0" \ - "tftp_kernel=tftp 100000 ${file_kernel}\0" \ - "update_kernel=protect off ff000000 ff17ffff;" \ - "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \ - "upd_kernel=run tftp_kernel;run update_kernel\0" \ - "file_fs=/zeus/rootfs_ba.img\0" \ - "tftp_fs=tftp 100000 ${file_fs}\0" \ - "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\ - "cp.b 100000 ff300000 580000\0" \ - "upd_fs=run tftp_fs;run update_fs\0" \ - "bootcmd=chkreset;run ramargs addip addtty addmisc;" \ - "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \ - "" - -#endif /* __CONFIG_H */ diff --git a/include/fsl_devdis.h b/include/fsl_devdis.h new file mode 100644 index 0000000000..02415feed8 --- /dev/null +++ b/include/fsl_devdis.h @@ -0,0 +1,18 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DEVDIS_H_ +#define __FSL_DEVDIS_H_ + +struct devdis_table { + char name[32]; + u32 offset; + u32 mask; +}; + +void device_disable(const struct devdis_table *tbl, uint32_t num); + +#endif diff --git a/include/micrel.h b/include/micrel.h index 04c9ecf3bf..e6d145d4b2 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -20,6 +20,10 @@ #define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6 #define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8 +/* Registers */ +#define MMD_ACCESS_CONTROL 0xd +#define MMD_ACCESS_REG_DATA 0xe + struct phy_device; int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val); int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum); diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h new file mode 100644 index 0000000000..e8b892ba88 --- /dev/null +++ b/include/power/pfuze3000_pmic.h @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc + * Peng Fan <Peng.Fan@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __PFUZE3000_PMIC_H_ +#define __PFUZE3000_PMIC_H_ + +/* PFUZE3000 registers */ +enum { + PFUZE3000_DEVICEID = 0x00, + + PFUZE3000_REVID = 0x03, + PFUZE3000_FABID = 0x04, + PFUZE3000_INTSTAT0 = 0x05, + PFUZE3000_INTMASK0 = 0x06, + PFUZE3000_INTSENSE0 = 0x07, + PFUZE3000_INTSTAT1 = 0x08, + PFUZE3000_INTMASK1 = 0x09, + PFUZE3000_INTSENSE1 = 0x0A, + + PFUZE3000_INTSTAT3 = 0x0E, + PFUZE3000_INTMASK3 = 0x0F, + PFUZE3000_INTSENSE3 = 0x10, + PFUZE3000_INTSTAT4 = 0x11, + PFUZE3000_INTMASK4 = 0x12, + PFUZE3000_INTSENSE4 = 0x13, + + PFUZE3000_COINCTL = 0x1A, + PFUZE3000_PWRCTL = 0x1B, + PFUZE3000_MEMA = 0x1C, + PFUZE3000_MEMB = 0x1D, + PFUZE3000_MEMC = 0x1E, + PFUZE3000_MEMD = 0x1F, + + PFUZE3000_SW1AVOLT = 0x20, + PFUZE3000_SW1ASTBY = 0x21, + PFUZE3000_SW1AOFF = 0x22, + PFUZE3000_SW1AMODE = 0x23, + PFUZE3000_SW1ACONF = 0x24, + + PFUZE3000_SW1BVOLT = 0x2E, + PFUZE3000_SW1BSTBY = 0x2F, + PFUZE3000_SW1BOFF = 0x30, + PFUZE3000_SW1BMODE = 0x31, + PFUZE3000_SW1BCONF = 0x32, + + PFUZE3000_SW2VOLT = 0x35, + PFUZE3000_SW2STBY = 0x36, + PFUZE3000_SW2OFF = 0x37, + PFUZE3000_SW2MODE = 0x38, + PFUZE3000_SW2CONF = 0x39, + + PFUZE3000_SW3VOLT = 0x3C, + PFUZE3000_SW3STBY = 0x3D, + PFUZE3000_SW3OFF = 0x3E, + PFUZE3000_SW3MODE = 0x3F, + PFUZE3000_SW3CONF = 0x40, + + PFUZE3000_SWBSTCTL = 0x66, + + PFUZE3000_LDOGCTL = 0x69, + PFUZE3000_VREFDDRCTL = 0x6A, + PFUZE3000_VSNVSCTL = 0x6B, + PFUZE3000_VLDO1CTL = 0x6C, + PFUZE3000_VLDO2CTL = 0x6D, + PFUZE3000_VCC_SDCTL = 0x6E, + PFUZE3000_V33CTL = 0x6F, + PFUZE3000_VLDO3CTL = 0x70, + PFUZE3000_VLD4CTL = 0x71, + + PMIC_NUM_OF_REGS = 0x7F, +}; + +int power_pfuze3000_init(unsigned char bus); + +#endif diff --git a/include/rtc.h b/include/rtc.h index bd8621d60b..69fe8d4db0 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -151,6 +151,7 @@ int rtc_write32(struct udevice *dev, unsigned int reg, u32 value); int rtc_get (struct rtc_time *); int rtc_set (struct rtc_time *); void rtc_reset (void); +void rtc_enable_32khz_output(void); /** * rtc_read8() - Read an 8-bit register diff --git a/include/status_led.h b/include/status_led.h index a5e35df80a..f6be18146b 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -64,19 +64,6 @@ void status_led_set (int led, int state); * filling this file up with lots of custom board stuff. */ -/***** CMI ********************************************************/ -#elif defined(CONFIG_CMI) -# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr -# define STATUS_LED_DAT im_mios.mios_mpiosm32dr - -# define STATUS_LED_BIT 0x2000 /* Select one of the 16 possible*/ - /* MIOS outputs */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Blinking periode is 500 ms */ -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */ -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - #elif defined(CONFIG_V38B) # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ diff --git a/tools/imximage.c b/tools/imximage.c index 909efaba2d..0da48a733d 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -288,7 +288,11 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len, hdr_base = entry_point - imximage_init_loadsize + flash_offset; fhdr_v2->self = hdr_base; - fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table); + if (dcd_len > 0) + fhdr_v2->dcd_ptr = hdr_base + + offsetof(imx_header_v2_t, dcd_table); + else + fhdr_v2->dcd_ptr = 0; fhdr_v2->boot_data_ptr = hdr_base + offsetof(imx_header_v2_t, boot_data); hdr_v2->boot_data.start = entry_point - imximage_init_loadsize; diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 185b327920..15eec9179d 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -271,23 +271,10 @@ static struct mx28_nand_fcb *mx28_nand_get_fcb(uint32_t size) fcb->ecc_block_0_size = 512; fcb->ecc_block_n_size = 512; fcb->metadata_bytes = 10; - - if (nand_writesize == 2048) { - fcb->ecc_block_n_ecc_type = 4; - fcb->ecc_block_0_ecc_type = 4; - } else if (nand_writesize == 4096) { - if (nand_oobsize == 128) { - fcb->ecc_block_n_ecc_type = 4; - fcb->ecc_block_0_ecc_type = 4; - } else if (nand_oobsize == 218) { - fcb->ecc_block_n_ecc_type = 8; - fcb->ecc_block_0_ecc_type = 8; - } else if (nand_oobsize == 224) { - fcb->ecc_block_n_ecc_type = 8; - fcb->ecc_block_0_ecc_type = 8; - } - } - + fcb->ecc_block_n_ecc_type = mx28_nand_get_ecc_strength( + nand_writesize, nand_oobsize) >> 1; + fcb->ecc_block_0_ecc_type = mx28_nand_get_ecc_strength( + nand_writesize, nand_oobsize) >> 1; if (fcb->ecc_block_n_ecc_type == 0) { printf("MX28 NAND: Unsupported NAND geometry\n"); goto err; |