diff options
119 files changed, 1200 insertions, 5954 deletions
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi index ba0fd4d2cd..aeeecd6283 100644 --- a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi +++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi @@ -7,8 +7,6 @@ /{ pinctrl_0: pinctrl@11400000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "samsung,exynos4210-pinctrl"; }; @@ -21,8 +19,6 @@ }; pinctrl_2: pinctrl@03860000 { - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index 59ea5a633e..610a8ad2e7 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -25,8 +25,6 @@ gpio-mosi = <&gpy3 3 0>; gpio-miso = <&gpy3 0 0>; spi-delay-us = <1>; - #address-cells = <1>; - #size-cells = <0>; cs@0 { }; }; diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi index 7409e76a59..955e14ef8f 100644 --- a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi +++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi @@ -32,13 +32,9 @@ }; pinctrl_2: pinctrl@03860000 { - #address-cells = <1>; - #size-cells = <1>; }; pinctrl_3: pinctrl@106E0000 { - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi index 6102978aa4..cdc965d90d 100644 --- a/arch/arm/dts/exynos5.dtsi +++ b/arch/arm/dts/exynos5.dtsi @@ -147,8 +147,6 @@ dp: dp@145b0000 { compatible = "samsung,exynos5-dp"; reg = <0x145b0000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; }; xhci0: xhci@12000000 { diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi index f19ce47b41..b414805319 100644 --- a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi +++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi @@ -18,8 +18,6 @@ }; pinctrl_1: pinctrl@13400000 { - #address-cells = <1>; - #size-cells = <1>; }; pinctrl_2: pinctrl@10d10000 { @@ -34,8 +32,6 @@ }; pinctrl_3: pinctrl@03860000 { - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts index b73b572e62..7633d36874 100644 --- a/arch/arm/dts/exynos5250-spring.dts +++ b/arch/arm/dts/exynos5250-spring.dts @@ -31,7 +31,7 @@ spi2 = "/spi@12d40000"; spi3 = "/spi@131a0000"; spi4 = "/spi@131b0000"; - mmc0 = "/mmc@12000000"; + mmc0 = "/mmc@12200000"; serial0 = "/serial@12C30000"; console = "/serial@12C30000"; i2s = "/sound@3830000"; diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi index 7265387639..4fcbe71fe5 100644 --- a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi +++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi @@ -12,8 +12,6 @@ * numbers are not needed in U-Boot for exynos. */ pinctrl@14010000 { - #address-cells = <1>; - #size-cells = <1>; }; pinctrl@13400000 { #address-cells = <1>; @@ -26,16 +24,10 @@ }; }; pinctrl@13410000 { - #address-cells = <1>; - #size-cells = <1>; }; pinctrl@14000000 { - #address-cells = <1>; - #size-cells = <1>; }; pinctrl@03860000 { - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31b622ff51..6e5e0ffe65 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -52,25 +52,6 @@ config TARGET_VCT select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD -config TARGET_DBAU1X00 - bool "Support dbau1x00" - select MIPS_TUNE_4KC - select ROM_EXCEPTION_VECTORS - select SUPPORTS_BIG_ENDIAN - select SUPPORTS_CPU_MIPS32_R1 - select SUPPORTS_CPU_MIPS32_R2 - select SUPPORTS_LITTLE_ENDIAN - select SYS_MIPS_CACHE_INIT_RAM_LOAD - -config TARGET_PB1X00 - bool "Support pb1x00" - select MIPS_TUNE_4KC - select ROM_EXCEPTION_VECTORS - select SUPPORTS_CPU_MIPS32_R1 - select SUPPORTS_CPU_MIPS32_R2 - select SUPPORTS_LITTLE_ENDIAN - select SYS_MIPS_CACHE_INIT_RAM_LOAD - config ARCH_ATH79 bool "Support QCA/Atheros ath79" select DM @@ -131,12 +112,10 @@ config TARGET_XILFPGA endchoice -source "board/dbau1x00/Kconfig" source "board/imgtec/boston/Kconfig" source "board/imgtec/malta/Kconfig" source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" -source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-bmips/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5deec9a202..a36f5f1fb6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -11,7 +11,6 @@ endif libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ -machine-$(CONFIG_SOC_AU1X00) += au1x00 machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi new file mode 100644 index 0000000000..d365d0f2ce --- /dev/null +++ b/arch/mips/dts/brcm,bcm6838.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6838"; + + cpus { + reg = <0x14e00000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6838-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6838-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + memory: memory-controller@12000000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x12000000 0x1000>; + u-boot,dm-pre-reloc; + }; + + uart0: serial@14e00500 { + compatible = "brcm,bcm6345-uart"; + reg = <0x14e00500 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + leds: led-controller@14e00f00 { + compatible = "brcm,bcm6328-leds"; + reg = <0x14e00f00 0x28>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/mips/dts/brcm,bcm968380gerg.dts b/arch/mips/dts/brcm,bcm968380gerg.dts new file mode 100644 index 0000000000..513045ee05 --- /dev/null +++ b/arch/mips/dts/brcm,bcm968380gerg.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +/dts-v1/; + +#include "brcm,bcm6838.dtsi" + +/ { + model = "Broadcom bcm68380gerg"; + compatible = "broadcom,bcm68380gerg", "brcm,bcm6838"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&memory { + force-size = <0x10000000>; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&leds { + status = "okay"; + + led@0 { + reg = <0>; + active-low; + label = "bcm968380gerg:green:usb"; + }; +}; diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 7deb516d45..b6d387677e 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -130,13 +130,13 @@ * Returns the uncached address of a sdram address */ #ifndef __ASSEMBLY__ -#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) +#if defined(CONFIG_TB0229) /* We use a 36 bit physical address map here and cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_SOC_AU1X00 */ +#else /* !CONFIG_TB0229 */ #define UNCACHED_SDRAM(a) CKSEG1ADDR(a) -#endif /* CONFIG_SOC_AU1X00 */ +#endif /* CONFIG_TB0229 */ #endif /* __ASSEMBLY__ */ /* diff --git a/arch/mips/mach-au1x00/Makefile b/arch/mips/mach-au1x00/Makefile deleted file mode 100644 index 4301b9c6d7..0000000000 --- a/arch/mips/mach-au1x00/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c deleted file mode 100644 index 84a1f59ba0..0000000000 --- a/arch/mips/mach-au1x00/au1x00_eth.c +++ /dev/null @@ -1,312 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Only eth0 supported for now - * - * (C) Copyright 2003 - * Thomas.Lange@corelatus.se - */ -#include <config.h> - -#if defined(CONFIG_SYS_DISCOVER_PHY) -#error "PHY not supported yet" -/* We just assume that we are running 100FD for now */ -/* We all use switches, right? ;-) */ -#endif - -/* I assume ethernet behaves like au1000 */ - -#ifdef CONFIG_SOC_AU1000 -/* Base address differ between cpu:s */ -#define ETH0_BASE AU1000_ETH0_BASE -#define MAC0_ENABLE AU1000_MAC0_ENABLE -#else -#ifdef CONFIG_SOC_AU1100 -#define ETH0_BASE AU1100_ETH0_BASE -#define MAC0_ENABLE AU1100_MAC0_ENABLE -#else -#ifdef CONFIG_SOC_AU1500 -#define ETH0_BASE AU1500_ETH0_BASE -#define MAC0_ENABLE AU1500_MAC0_ENABLE -#else -#ifdef CONFIG_SOC_AU1550 -#define ETH0_BASE AU1550_ETH0_BASE -#define MAC0_ENABLE AU1550_MAC0_ENABLE -#else -#error "No valid cpu set" -#endif -#endif -#endif -#endif - -#include <common.h> -#include <malloc.h> -#include <net.h> -#include <command.h> -#include <asm/io.h> -#include <mach/au1x00.h> - -#if defined(CONFIG_CMD_MII) -#include <miiphy.h> -#endif - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 -#define PKT_MAXBUF_SIZE 1518 - -static char txbuf[DBUF_LENGTH]; - -static int next_tx; -static int next_rx; - -/* 4 rx and 4 tx fifos */ -#define NO_OF_FIFOS 4 - -typedef struct{ - u32 status; - u32 addr; - u32 len; /* Only used for tx */ - u32 not_used; -} mac_fifo_t; - -mac_fifo_t mac_fifo[NO_OF_FIFOS]; - -#define MAX_WAIT 1000 - -#if defined(CONFIG_CMD_MII) -int au1x00_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) -{ - unsigned short value = 0; - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; - - *mii_control_reg = mii_control; - - timedout = 20; - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - value = *mii_data_reg; - return value; -} - -int au1x00_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value) -{ - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_write busy timeout!!\n"); - return -1; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; - - *mii_data_reg = value; - *mii_control_reg = mii_control; - return 0; -} -#endif - -static int au1x00_send(struct eth_device *dev, void *packet, int length) -{ - volatile mac_fifo_t *fifo_tx = - (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); - int i; - int res; - - /* tx fifo should always be idle */ - fifo_tx[next_tx].len = length; - fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE; - au_sync(); - - udelay(1); - i=0; - while(!(fifo_tx[next_tx].addr&TX_T_DONE)){ - if(i>MAX_WAIT){ - printf("TX timeout\n"); - break; - } - udelay(1); - i++; - } - - /* Clear done bit */ - fifo_tx[next_tx].addr = 0; - fifo_tx[next_tx].len = 0; - au_sync(); - - res = fifo_tx[next_tx].status; - - next_tx++; - if(next_tx>=NO_OF_FIFOS){ - next_tx=0; - } - return(res); -} - -static int au1x00_recv(struct eth_device* dev){ - volatile mac_fifo_t *fifo_rx = - (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); - - int length; - u32 status; - - for(;;){ - if(!(fifo_rx[next_rx].addr&RX_T_DONE)){ - /* Nothing has been received */ - return(-1); - } - - status = fifo_rx[next_rx].status; - - length = status&0x3FFF; - - if(status&RX_ERROR){ - printf("Rx error 0x%x\n", status); - } else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[next_rx], - length - 4); - } - - fifo_rx[next_rx].addr = - (virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE; - - next_rx++; - if(next_rx>=NO_OF_FIFOS){ - next_rx=0; - } - } /* for */ - - return(0); /* Does anyone use this? */ -} - -static int au1x00_init(struct eth_device* dev, bd_t * bd){ - - volatile u32 *macen = (volatile u32*)MAC0_ENABLE; - volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL); - volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH); - volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW); - volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH); - volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW); - volatile mac_fifo_t *fifo_tx = - (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); - volatile mac_fifo_t *fifo_rx = - (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS); - int i; - - next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr); - next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr); - - /* We have to enable clocks before releasing reset */ - *macen = MAC_EN_CLOCK_ENABLE; - udelay(10); - - /* Enable MAC0 */ - /* We have to release reset before accessing registers */ - *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0| - MAC_EN_RESET1|MAC_EN_RESET2; - udelay(10); - - for(i=0;i<NO_OF_FIFOS;i++){ - fifo_tx[i].len = 0; - fifo_tx[i].addr = virt_to_phys(&txbuf[0]); - fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) | - RX_DMA_ENABLE; - } - - /* Put mac addr in little endian */ -#define ea eth_get_ethaddr() - *mac_addr_high = (ea[5] << 8) | (ea[4] ) ; - *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) | - (ea[1] << 8) | (ea[0] ) ; -#undef ea - *mac_mcast_low = 0; - *mac_mcast_high = 0; - - /* Make sure the MAC buffer is in the correct endian mode */ -#ifdef __LITTLE_ENDIAN - *mac_ctrl = MAC_FULL_DUPLEX; - udelay(1); - *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; -#else - *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX; - udelay(1); - *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE; -#endif - - return(1); -} - -static void au1x00_halt(struct eth_device* dev){ - volatile u32 *macen = (volatile u32*)MAC0_ENABLE; - - /* Put MAC0 in reset */ - *macen = 0; -} - -int au1x00_enet_initialize(bd_t *bis){ - struct eth_device* dev; - - if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) { - puts ("malloc failed\n"); - return -1; - } - - memset(dev, 0, sizeof *dev); - - strcpy(dev->name, "Au1X00 ethernet"); - dev->iobase = 0; - dev->priv = 0; - dev->init = au1x00_init; - dev->halt = au1x00_halt; - dev->send = au1x00_send; - dev->recv = au1x00_recv; - - eth_register(dev); - -#if defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = au1x00_miiphy_read; - mdiodev->write = au1x00_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - return 1; -} - -int cpu_eth_init(bd_t *bis) -{ - au1x00_enet_initialize(bis); - return 0; -} diff --git a/arch/mips/mach-au1x00/au1x00_ide.c b/arch/mips/mach-au1x00/au1x00_ide.c deleted file mode 100644 index ab52b9964e..0000000000 --- a/arch/mips/mach-au1x00/au1x00_ide.c +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <ide.h> - -/* AU1X00 swaps data in big-endian mode, enforce little-endian function */ -void ide_input_swap_data(int dev, ulong *sect_buf, int words) -{ - ide_input_data(dev, sect_buf, words); -} diff --git a/arch/mips/mach-au1x00/au1x00_serial.c b/arch/mips/mach-au1x00/au1x00_serial.c deleted file mode 100644 index 4bcbc2d3ae..0000000000 --- a/arch/mips/mach-au1x00/au1x00_serial.c +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * AU1X00 UART support - * - * Hardcoded to UART 0 for now - * Speed and options also hardcoded to 115200 8N1 - * - * Copyright (c) 2003 Thomas.Lange@corelatus.se - */ - -#include <config.h> -#include <common.h> -#include <mach/au1x00.h> -#include <serial.h> -#include <linux/compiler.h> - -/****************************************************************************** -* -* serial_init - initialize a channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -static int au1x00_serial_init(void) -{ - volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR); - volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE); - - /* Enable clocks first */ - *uart_enable = UART_EN_CE; - - /* Then release reset */ - /* Must release reset before setting other regs */ - *uart_enable = UART_EN_CE|UART_EN_E; - - /* Activate fifos, reset tx and rx */ - /* Set tx trigger level to 12 */ - *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR| - UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12; - - serial_setbrg(); - - return 0; -} - - -static void au1x00_serial_setbrg(void) -{ - volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK); - volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR); - volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL; - int sd; - int divisorx2; - - /* sd is system clock divisor */ - /* see section 10.4.5 in au1550 datasheet */ - sd = (*sys_powerctrl & 0x03) + 2; - - /* calulate 2x baudrate and round */ - divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); - - if (divisorx2 & 0x01) - divisorx2 = divisorx2 + 1; - - *uart_clk = divisorx2 / 2; - - /* Set parity, stop bits and word length to 8N1 */ - *uart_lcr = UART_LCR_WLEN8; -} - -static void au1x00_serial_putc(const char c) -{ - volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); - volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX); - - if (c == '\n') - au1x00_serial_putc('\r'); - - /* Wait for fifo to shift out some bytes */ - while((*uart_lsr&UART_LSR_THRE)==0); - - *uart_tx = (u32)c; -} - -static int au1x00_serial_getc(void) -{ - volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX); - char c; - - while (!serial_tstc()); - - c = (*uart_rx&0xFF); - return c; -} - -static int au1x00_serial_tstc(void) -{ - volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); - - if(*uart_lsr&UART_LSR_DR){ - /* Data in rfifo */ - return(1); - } - return 0; -} - -static struct serial_device au1x00_serial_drv = { - .name = "au1x00_serial", - .start = au1x00_serial_init, - .stop = NULL, - .setbrg = au1x00_serial_setbrg, - .putc = au1x00_serial_putc, - .puts = default_serial_puts, - .getc = au1x00_serial_getc, - .tstc = au1x00_serial_tstc, -}; - -void au1x00_serial_initialize(void) -{ - serial_register(&au1x00_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &au1x00_serial_drv; -} diff --git a/arch/mips/mach-au1x00/au1x00_usb_ohci.c b/arch/mips/mach-au1x00/au1x00_usb_ohci.c deleted file mode 100644 index 999b15ae83..0000000000 --- a/arch/mips/mach-au1x00/au1x00_usb_ohci.c +++ /dev/null @@ -1,1609 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00. - * - * (C) Copyright 2003 - * Gary Jennejohn, DENX Software Engineering <garyj@denx.de> - * Note: Part of this code has been derived from linux - * - */ -/* - * IMPORTANT NOTES - * 1 - this driver is intended for use with USB Mass Storage Devices - * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! - */ - -#include <config.h> - -#ifdef CONFIG_USB_OHCI - -/* #include <pci.h> no PCI on the AU1x00 */ - -#include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <mach/au1x00.h> -#include <usb.h> -#include "au1x00_usb_ohci.h" - -#define OHCI_USE_NPS /* force NoPowerSwitching mode */ -#define OHCI_VERBOSE_DEBUG /* not always helpful */ -#define OHCI_FILL_TRACE - -#define USBH_ENABLE_BE (1<<0) -#define USBH_ENABLE_C (1<<1) -#define USBH_ENABLE_E (1<<2) -#define USBH_ENABLE_CE (1<<3) -#define USBH_ENABLE_RD (1<<4) - -#ifdef __LITTLE_ENDIAN -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) -#else -#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) -#endif - - -/* For initializing controller (mask in an HCFS mode too) */ -#define OHCI_CONTROL_INIT \ - (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE - -#undef readl -#undef writel - -#define readl(a) au_readl((long)(a)) -#define writel(v,a) au_writel((v),(int)(a)) - -#define DEBUG -#ifdef DEBUG -#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) -#else -#define dbg(format, arg...) do {} while(0) -#endif /* DEBUG */ -#define err(format, arg...) printf("ERROR: " format "\n", ## arg) -#define SHOW_INFO -#ifdef SHOW_INFO -#define info(format, arg...) printf("INFO: " format "\n", ## arg) -#else -#define info(format, arg...) do {} while(0) -#endif - -#define m16_swap(x) swap_16(x) -#define m32_swap(x) swap_32(x) - -/* global ohci_t */ -static ohci_t gohci; -/* this must be aligned to a 256 byte boundary */ -struct ohci_hcca ghcca[1]; -/* a pointer to the aligned storage */ -struct ohci_hcca *phcca; -/* this allocates EDs for all possible endpoints */ -struct ohci_device ohci_dev; -/* urb_priv */ -urb_priv_t urb_priv; -/* RHSC flag */ -int got_rhsc; -/* device which was disconnected */ -struct usb_device *devgone; - -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } -static inline u32 roothub_b (struct ohci *hc) - { return readl (&hc->regs->roothub.b); } -static inline u32 roothub_status (struct ohci *hc) - { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } - - -/* forward declaration */ -static int hc_interrupt (void); -static void -td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); - -/*-------------------------------------------------------------------------* - * URB support functions - *-------------------------------------------------------------------------*/ - -/* free HCD-private data associated with this URB */ - -static void urb_free_priv (urb_priv_t * urb) -{ - int i; - int last; - struct td * td; - - last = urb->length - 1; - if (last >= 0) { - for (i = 0; i <= last; i++) { - td = urb->td[i]; - if (td) { - td->usb_dev = NULL; - urb->td[i] = NULL; - } - } - } -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -static int sohci_get_current_frame_number (struct usb_device * dev); - -/* debug| print the main components of an URB - * small: 0) header + data packets 1) just header */ - -static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, - int transfer_len, struct devrequest * setup, char * str, int small) -{ - urb_priv_t * purb = &urb_priv; - - dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", - str, - sohci_get_current_frame_number (dev), - usb_pipedevice (pipe), - usb_pipeendpoint (pipe), - usb_pipeout (pipe)? 'O': 'I', - usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): - (usb_pipecontrol (pipe)? "CTRL": "BULK"), - purb->actual_length, - transfer_len, dev->status); -#ifdef OHCI_VERBOSE_DEBUG - if (!small) { - int i, len; - - if (usb_pipecontrol (pipe)) { - printf (__FILE__ ": cmd(8):"); - for (i = 0; i < 8 ; i++) - printf (" %02x", ((__u8 *) setup) [i]); - printf ("\n"); - } - if (transfer_len > 0 && buffer) { - printf (__FILE__ ": data(%d/%d):", - purb->actual_length, - transfer_len); - len = usb_pipeout (pipe)? - transfer_len: purb->actual_length; - for (i = 0; i < 16 && i < len; i++) - printf (" %02x", ((__u8 *) buffer) [i]); - printf ("%s\n", i < len? "...": ""); - } - } -#endif -} - -/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ -void ep_print_int_eds (ohci_t *ohci, char * str) { - int i, j; - __u32 * ed_p; - for (i= 0; i < 32; i++) { - j = 5; - ed_p = &(ohci->hcca->int_table [i]); - if (*ed_p == 0) - continue; - printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); - while (*ed_p != 0 && j--) { - ed_t *ed = (ed_t *)m32_swap(ed_p); - printf (" ed: %4x;", ed->hwINFO); - ed_p = &ed->hwNextED; - } - printf ("\n"); - } -} - -static void ohci_dump_intr_mask (char *label, __u32 mask) -{ - dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", - label, - mask, - (mask & OHCI_INTR_MIE) ? " MIE" : "", - (mask & OHCI_INTR_OC) ? " OC" : "", - (mask & OHCI_INTR_RHSC) ? " RHSC" : "", - (mask & OHCI_INTR_FNO) ? " FNO" : "", - (mask & OHCI_INTR_UE) ? " UE" : "", - (mask & OHCI_INTR_RD) ? " RD" : "", - (mask & OHCI_INTR_SF) ? " SF" : "", - (mask & OHCI_INTR_WDH) ? " WDH" : "", - (mask & OHCI_INTR_SO) ? " SO" : "" - ); -} - -static void maybe_print_eds (char *label, __u32 value) -{ - ed_t *edp = (ed_t *)value; - - if (value) { - dbg ("%s %08x", label, value); - dbg ("%08x", edp->hwINFO); - dbg ("%08x", edp->hwTailP); - dbg ("%08x", edp->hwHeadP); - dbg ("%08x", edp->hwNextED); - } -} - -static char * hcfs2string (int state) -{ - switch (state) { - case OHCI_USB_RESET: return "reset"; - case OHCI_USB_RESUME: return "resume"; - case OHCI_USB_OPER: return "operational"; - case OHCI_USB_SUSPEND: return "suspend"; - } - return "?"; -} - -/* dump control and status registers */ -static void ohci_dump_status (ohci_t *controller) -{ - struct ohci_regs *regs = controller->regs; - __u32 temp; - - temp = readl (®s->revision) & 0xff; - if (temp != 0x10) - dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); - - temp = readl (®s->control); - dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, - (temp & OHCI_CTRL_RWE) ? " RWE" : "", - (temp & OHCI_CTRL_RWC) ? " RWC" : "", - (temp & OHCI_CTRL_IR) ? " IR" : "", - hcfs2string (temp & OHCI_CTRL_HCFS), - (temp & OHCI_CTRL_BLE) ? " BLE" : "", - (temp & OHCI_CTRL_CLE) ? " CLE" : "", - (temp & OHCI_CTRL_IE) ? " IE" : "", - (temp & OHCI_CTRL_PLE) ? " PLE" : "", - temp & OHCI_CTRL_CBSR - ); - - temp = readl (®s->cmdstatus); - dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, - (temp & OHCI_SOC) >> 16, - (temp & OHCI_OCR) ? " OCR" : "", - (temp & OHCI_BLF) ? " BLF" : "", - (temp & OHCI_CLF) ? " CLF" : "", - (temp & OHCI_HCR) ? " HCR" : "" - ); - - ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); - ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); - - maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); - - maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); - maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); - - maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); - maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); - - maybe_print_eds ("donehead", readl (®s->donehead)); -} - -static void ohci_dump_roothub (ohci_t *controller, int verbose) -{ - __u32 temp, ndp, i; - - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - - if (verbose) { - dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, - ((temp & RH_A_POTPGT) >> 24) & 0xff, - (temp & RH_A_NOCP) ? " NOCP" : "", - (temp & RH_A_OCPM) ? " OCPM" : "", - (temp & RH_A_DT) ? " DT" : "", - (temp & RH_A_NPS) ? " NPS" : "", - (temp & RH_A_PSM) ? " PSM" : "", - ndp - ); - temp = roothub_b (controller); - dbg ("roothub.b: %08x PPCM=%04x DR=%04x", - temp, - (temp & RH_B_PPCM) >> 16, - (temp & RH_B_DR) - ); - temp = roothub_status (controller); - dbg ("roothub.status: %08x%s%s%s%s%s%s", - temp, - (temp & RH_HS_CRWE) ? " CRWE" : "", - (temp & RH_HS_OCIC) ? " OCIC" : "", - (temp & RH_HS_LPSC) ? " LPSC" : "", - (temp & RH_HS_DRWE) ? " DRWE" : "", - (temp & RH_HS_OCI) ? " OCI" : "", - (temp & RH_HS_LPS) ? " LPS" : "" - ); - } - - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", - i, - temp, - (temp & RH_PS_PRSC) ? " PRSC" : "", - (temp & RH_PS_OCIC) ? " OCIC" : "", - (temp & RH_PS_PSSC) ? " PSSC" : "", - (temp & RH_PS_PESC) ? " PESC" : "", - (temp & RH_PS_CSC) ? " CSC" : "", - - (temp & RH_PS_LSDA) ? " LSDA" : "", - (temp & RH_PS_PPS) ? " PPS" : "", - (temp & RH_PS_PRS) ? " PRS" : "", - (temp & RH_PS_POCI) ? " POCI" : "", - (temp & RH_PS_PSS) ? " PSS" : "", - - (temp & RH_PS_PES) ? " PES" : "", - (temp & RH_PS_CCS) ? " CCS" : "" - ); - } -} - -static void ohci_dump (ohci_t *controller, int verbose) -{ - dbg ("OHCI controller usb-%s state", controller->slot_name); - - /* dumps some of the state we know about */ - ohci_dump_status (controller); - if (verbose) - ep_print_int_eds (controller, "hcca"); - dbg ("hcca frame #%04x", controller->hcca->frame_no); - ohci_dump_roothub (controller, 1); -} - - -#endif /* DEBUG */ - -/*-------------------------------------------------------------------------* - * Interface functions (URB) - *-------------------------------------------------------------------------*/ - -/* get a transfer request */ - -int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - ohci_t *ohci; - ed_t * ed; - urb_priv_t *purb_priv; - int i, size = 0; - - ohci = &gohci; - - /* when controller's hung, permit only roothub cleanup attempts - * such as powering down ports */ - if (ohci->disabled) { - err("sohci_submit_job: EPIPE"); - return -1; - } - - /* every endpoint has a ed, locate and fill it */ - if (!(ed = ep_add_ed (dev, pipe))) { - err("sohci_submit_job: ENOMEM"); - return -1; - } - - /* for the private part of the URB we need the number of TDs (size) */ - switch (usb_pipetype (pipe)) { - case PIPE_BULK: /* one TD for every 4096 Byte */ - size = (transfer_len - 1) / 4096 + 1; - break; - case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ - size = (transfer_len == 0)? 2: - (transfer_len - 1) / 4096 + 3; - break; - } - - if (size >= (N_URB_TD - 1)) { - err("need %d TDs, only have %d", size, N_URB_TD); - return -1; - } - purb_priv = &urb_priv; - purb_priv->pipe = pipe; - - /* fill the private part of the URB */ - purb_priv->length = size; - purb_priv->ed = ed; - purb_priv->actual_length = 0; - - /* allocate the TDs */ - /* note that td[0] was allocated in ep_add_ed */ - for (i = 0; i < size; i++) { - purb_priv->td[i] = td_alloc (dev); - if (!purb_priv->td[i]) { - purb_priv->length = i; - urb_free_priv (purb_priv); - err("sohci_submit_job: ENOMEM"); - return -1; - } - } - - if (ed->state == ED_NEW || (ed->state & ED_DEL)) { - urb_free_priv (purb_priv); - err("sohci_submit_job: EINVAL"); - return -1; - } - - /* link the ed into a chain if is not already */ - if (ed->state != ED_OPER) - ep_link (ohci, ed); - - /* fill the TDs and link it to the ed */ - td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -#ifdef DEBUG -/* tell us the current USB frame number */ - -static int sohci_get_current_frame_number (struct usb_device *usb_dev) -{ - ohci_t *ohci = &gohci; - - return m16_swap (ohci->hcca->frame_no); -} -#endif - -/*-------------------------------------------------------------------------* - * ED handling functions - *-------------------------------------------------------------------------*/ - -/* link an ed into one of the HC chains */ - -static int ep_link (ohci_t *ohci, ed_t *edi) -{ - volatile ed_t *ed = edi; - - ed->state = ED_OPER; - - switch (ed->type) { - case PIPE_CONTROL: - ed->hwNextED = 0; - if (ohci->ed_controltail == NULL) { - writel ((long)ed, &ohci->regs->ed_controlhead); - } else { - ohci->ed_controltail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_controltail; - if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_controltail = edi; - break; - - case PIPE_BULK: - ed->hwNextED = 0; - if (ohci->ed_bulktail == NULL) { - writel ((long)ed, &ohci->regs->ed_bulkhead); - } else { - ohci->ed_bulktail->hwNextED = m32_swap (ed); - } - ed->ed_prev = ohci->ed_bulktail; - if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && - !ohci->ed_rm_list[1] && !ohci->sleeping) { - ohci->hc_control |= OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - ohci->ed_bulktail = edi; - break; - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* unlink an ed from one of the HC chains. - * just the link to the ed is unlinked. - * the link from the ed still points to another operational ed or 0 - * so the HC can eventually finish the processing of the unlinked ed */ - -static int ep_unlink (ohci_t *ohci, ed_t *ed) -{ - ed->hwINFO |= m32_swap (OHCI_ED_SKIP); - - switch (ed->type) { - case PIPE_CONTROL: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_CLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_controltail == ed) { - ohci->ed_controltail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - - case PIPE_BULK: - if (ed->ed_prev == NULL) { - if (!ed->hwNextED) { - ohci->hc_control &= ~OHCI_CTRL_BLE; - writel (ohci->hc_control, &ohci->regs->control); - } - writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); - } else { - ed->ed_prev->hwNextED = ed->hwNextED; - } - if (ohci->ed_bulktail == ed) { - ohci->ed_bulktail = ed->ed_prev; - } else { - ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; - } - break; - } - ed->state = ED_UNLINK; - return 0; -} - - -/*-------------------------------------------------------------------------*/ - -/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, - * but the USB stack is a little bit stateless so we do it at every transaction - * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK - * in all other cases the state is left unchanged - * the ed info fields are setted anyway even though most of them should not change */ - -static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) -{ - td_t *td; - ed_t *ed_ret; - volatile ed_t *ed; - - ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | - (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; - - if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { - err("ep_add_ed: pending delete"); - /* pending delete request */ - return NULL; - } - - if (ed->state == ED_NEW) { - ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ - /* dummy td; end of td list for ed */ - td = td_alloc (usb_dev); - ed->hwTailP = m32_swap (td); - ed->hwHeadP = ed->hwTailP; - ed->state = ED_UNLINK; - ed->type = usb_pipetype (pipe); - ohci_dev.ed_cnt++; - } - - ed->hwINFO = m32_swap (usb_pipedevice (pipe) - | usb_pipeendpoint (pipe) << 7 - | (usb_pipeisoc (pipe)? 0x8000: 0) - | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) - | (usb_dev->speed == USB_SPEED_LOW) << 13 - | usb_maxpacket (usb_dev, pipe) << 16); - - return ed_ret; -} - -/*-------------------------------------------------------------------------* - * TD handling functions - *-------------------------------------------------------------------------*/ - -/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ - -static void td_fill (ohci_t *ohci, unsigned int info, - void *data, int len, - struct usb_device *dev, int index, urb_priv_t *urb_priv) -{ - volatile td_t *td, *td_pt; -#ifdef OHCI_FILL_TRACE - int i; -#endif - - if (index > urb_priv->length) { - err("index > length"); - return; - } - /* use this td as the next dummy */ - td_pt = urb_priv->td [index]; - td_pt->hwNextTD = 0; - - /* fill the old dummy TD */ - td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); - - td->ed = urb_priv->ed; - td->next_dl_td = NULL; - td->index = index; - td->data = (__u32)data; -#ifdef OHCI_FILL_TRACE - if (1 || (usb_pipebulk(urb_priv->pipe) && - usb_pipeout(urb_priv->pipe))) { - for (i = 0; i < len; i++) - printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]); - } -#endif - if (!len) - data = 0; - - td->hwINFO = m32_swap (info); - td->hwCBP = m32_swap (data); - if (data) - td->hwBE = m32_swap (data + len - 1); - else - td->hwBE = 0; - td->hwNextTD = m32_swap (td_pt); - td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); - - /* append to queue */ - td->ed->hwTailP = td->hwNextTD; -} - -/*-------------------------------------------------------------------------*/ - -/* prepare all TDs of a transfer */ - -#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000)) - -static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) -{ - ohci_t *ohci = &gohci; - int data_len = transfer_len; - void *data; - int cnt = 0; - __u32 info = 0; - unsigned int toggle = 0; - - /* OHCI handles the DATA-toggles itself, we just use the - USB-toggle bits for resetting */ - if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { - toggle = TD_T_TOGGLE; - } else { - toggle = TD_T_DATA0; - usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); - } - urb->td_cnt = 0; - if (data_len) - data = kseg_to_phys(buffer); - else - data = 0; - - switch (usb_pipetype (pipe)) { - case PIPE_BULK: - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; - while(data_len > 4096) { - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); - data += 4096; data_len -= 4096; cnt++; - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; - td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); - cnt++; - - if (!ohci->sleeping) - writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ - break; - - case PIPE_CONTROL: - info = TD_CC | TD_DP_SETUP | TD_T_DATA0; - td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb); - if (data_len > 0) { - info = usb_pipeout (pipe)? - TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; - /* NOTE: mishandles transfers >8K, some >4K */ - td_fill (ohci, info, data, data_len, dev, cnt++, urb); - } - info = usb_pipeout (pipe)? - TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; - td_fill (ohci, info, data, 0, dev, cnt++, urb); - if (!ohci->sleeping) - writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ - break; - } - if (urb->length != cnt) - dbg("TD LENGTH %d != CNT %d", urb->length, cnt); -} - -/*-------------------------------------------------------------------------* - * Done List handling functions - *-------------------------------------------------------------------------*/ - - -/* calculate the transfer length and update the urb */ - -static void dl_transfer_length(td_t * td) -{ - __u32 tdINFO, tdBE, tdCBP; - urb_priv_t *lurb_priv = &urb_priv; - - tdINFO = m32_swap (td->hwINFO); - tdBE = m32_swap (td->hwBE); - tdCBP = m32_swap (td->hwCBP); - - - if (!(usb_pipecontrol(lurb_priv->pipe) && - ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { - if (tdBE != 0) { - if (td->hwCBP == 0) - lurb_priv->actual_length += tdBE - td->data + 1; - else - lurb_priv->actual_length += tdCBP - td->data; - } - } -} - -/*-------------------------------------------------------------------------*/ - -/* replies to the request have to be on a FIFO basis so - * we reverse the reversed done-list */ - -static td_t * dl_reverse_done_list (ohci_t *ohci) -{ - __u32 td_list_hc; - td_t *td_rev = NULL; - td_t *td_list = NULL; - urb_priv_t *lurb_priv = NULL; - - td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; - ohci->hcca->done_head = 0; - - while (td_list_hc) { - td_list = (td_t *)td_list_hc; - - if (TD_CC_GET (m32_swap (td_list->hwINFO))) { - lurb_priv = &urb_priv; - dbg(" USB-error/status: %x : %p", - TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); - if (td_list->ed->hwHeadP & m32_swap (0x1)) { - if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { - td_list->ed->hwHeadP = - (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | - (td_list->ed->hwHeadP & m32_swap (0x2)); - lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; - } else - td_list->ed->hwHeadP &= m32_swap (0xfffffff2); - } - } - - td_list->next_dl_td = td_rev; - td_rev = td_list; - td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; - } - return td_list; -} - -/*-------------------------------------------------------------------------*/ - -/* td done list */ -static int dl_done_list (ohci_t *ohci, td_t *td_list) -{ - td_t *td_list_next = NULL; - ed_t *ed; - int cc = 0; - int stat = 0; - /* urb_t *urb; */ - urb_priv_t *lurb_priv; - __u32 tdINFO, edHeadP, edTailP; - - while (td_list) { - td_list_next = td_list->next_dl_td; - - lurb_priv = &urb_priv; - tdINFO = m32_swap (td_list->hwINFO); - - ed = td_list->ed; - - dl_transfer_length(td_list); - - /* error code of transfer */ - cc = TD_CC_GET (tdINFO); - if (cc != 0) { - dbg("ConditionCode %#x", cc); - stat = cc_to_error[cc]; - } - - if (ed->state != ED_NEW) { - edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; - edTailP = m32_swap (ed->hwTailP); - - /* unlink eds if they are not busy */ - if ((edHeadP == edTailP) && (ed->state == ED_OPER)) - ep_unlink (ohci, ed); - } - - td_list = td_list_next; - } - return stat; -} - -/*-------------------------------------------------------------------------* - * Virtual Root Hub - *-------------------------------------------------------------------------*/ - -#include <usbroothubdes.h> - -/* Hub class-specific descriptor is constructed dynamically */ - - -/*-------------------------------------------------------------------------*/ - -#define OK(x) len = (x); break -#ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} -#else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) -#endif -#define RD_RH_STAT roothub_status(&gohci) -#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) - -/* request to virtual root hub */ - -int rh_check_port_status(ohci_t *controller) -{ - __u32 temp, ndp, i; - int res; - - res = -1; - temp = roothub_a (controller); - ndp = (temp & RH_A_NDP); - for (i = 0; i < ndp; i++) { - temp = roothub_portstatus (controller, i); - /* check for a device disconnect */ - if (((temp & (RH_PS_PESC | RH_PS_CSC)) == - (RH_PS_PESC | RH_PS_CSC)) && - ((temp & RH_PS_CCS) == 0)) { - res = i; - break; - } - } - return res; -} - -static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len, struct devrequest *cmd) -{ - void * data = buffer; - int leni = transfer_len; - int len = 0; - int stat = 0; - __u32 datab[4]; - __u8 *data_buf = (__u8 *)datab; - __u16 bmRType_bReq; - __u16 wValue; - __u16 wIndex; - __u16 wLength; - -#ifdef DEBUG -urb_priv.actual_length = 0; -pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (usb_pipeint(pipe)) { - info("Root-Hub submit IRQ: NOT implemented"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - wValue = m16_swap (cmd->value); - wIndex = m16_swap (cmd->index); - wLength = m16_swap (cmd->length); - - info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", - dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(__u16 *) data_buf = m16_swap (1); OK (2); - case RH_GET_STATUS | RH_INTERFACE: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_ENDPOINT: - *(__u16 *) data_buf = m16_swap (0); OK (2); - case RH_GET_STATUS | RH_CLASS: - *(__u32 *) data_buf = m32_swap ( - RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); - OK (4); - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); - - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case RH_C_HUB_LOCAL_POWER: - OK(0); - case (RH_C_HUB_OVER_CURRENT): - WR_RH_STAT(RH_HS_OCIC); OK (0); - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_POCI); OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); - case (RH_C_PORT_CONNECTION): - WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); - case (RH_C_PORT_ENABLE): - WR_RH_PORTSTAT (RH_PS_PESC); OK (0); - case (RH_C_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); - case (RH_C_PORT_OVER_CURRENT): - WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); - case (RH_C_PORT_RESET): - WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); - } - break; - - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - switch (wValue) { - case (RH_PORT_SUSPEND): - WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); - case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PRS); - OK (0); - case (RH_PORT_POWER): - WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); - case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ - if (RD_RH_PORTSTAT & RH_PS_CCS) - WR_RH_PORTSTAT (RH_PS_PES ); - OK (0); - } - break; - - case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_dev_des), - wLength)); - data_buf = root_hub_dev_des; OK(len); - case (0x02): /* configuration descriptor */ - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_config_des), - wLength)); - data_buf = root_hub_config_des; OK(len); - case (0x03): /* string descriptors */ - if(wValue==0x0300) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index0), - wLength)); - data_buf = root_hub_str_index0; - OK(len); - } - if(wValue==0x0301) { - len = min_t(unsigned int, - leni, - min_t(unsigned int, - sizeof (root_hub_str_index1), - wLength)); - data_buf = root_hub_str_index1; - OK(len); - } - default: - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - { - __u32 temp = roothub_a (&gohci); - - data_buf [0] = 9; /* min length; */ - data_buf [1] = 0x29; - data_buf [2] = temp & RH_A_NDP; - data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ - data_buf [3] |= 0x1; - if (temp & RH_A_NOCP) /* no overcurrent reporting? */ - data_buf [3] |= 0x10; - else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ - data_buf [3] |= 0x8; - - /* corresponds to data_buf[4-7] */ - datab [1] = 0; - data_buf [5] = (temp & RH_A_POTPGT) >> 24; - temp = roothub_b (&gohci); - data_buf [7] = temp & RH_B_DR; - if (data_buf [2] < 7) { - data_buf [8] = 0xff; - } else { - data_buf [0] += 2; - data_buf [8] = (temp & RH_B_DR) >> 8; - data_buf [10] = data_buf [9] = 0xff; - } - - len = min_t(unsigned int, leni, - min_t(unsigned int, data_buf [0], wLength)); - OK (len); - } - - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); - - default: - dbg ("unsupported root hub command"); - stat = USB_ST_STALLED; - } - -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#else - mdelay(1); -#endif - - len = min_t(int, len, leni); - if (data != data_buf) - memcpy (data, data_buf, len); - dev->act_len = len; - dev->status = stat; - -#ifdef DEBUG - if (transfer_len) - urb_priv.actual_length = transfer_len; - pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); -#else - mdelay(1); -#endif - - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/* common code for handling submit messages - used for all but root hub */ -/* accesses. */ -int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup, int interval) -{ - int stat = 0; - int maxsize = usb_maxpacket(dev, pipe); - int timeout; - - /* device pulled? Shortcut the action. */ - if (devgone == dev) { - dev->status = USB_ST_CRC_ERR; - return 0; - } - -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (!maxsize) { - err("submit_common_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - - if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { - err("sohci_submit_job failed"); - return -1; - } - - mdelay(10); - /* ohci_dump_status(&gohci); */ - - /* allow more time for a BULK device to react - some are slow */ -#define BULK_TO 5000 /* timeout in milliseconds */ - if (usb_pipebulk(pipe)) - timeout = BULK_TO; - else - timeout = 100; - - timeout *= 4; - /* wait for it to complete */ - for (;;) { - /* check whether the controller is done */ - stat = hc_interrupt(); - if (stat < 0) { - stat = USB_ST_CRC_ERR; - break; - } - if (stat >= 0 && stat != 0xff) { - /* 0xff is returned for an SF-interrupt */ - break; - } - if (--timeout) { - udelay(250); /* mdelay(1); */ - } else { - err("CTL:TIMEOUT "); - stat = USB_ST_CRC_ERR; - break; - } - } - /* we got an Root Hub Status Change interrupt */ - if (got_rhsc) { -#ifdef DEBUG - ohci_dump_roothub (&gohci, 1); -#endif - got_rhsc = 0; - /* abuse timeout */ - timeout = rh_check_port_status(&gohci); - if (timeout >= 0) { -#if 0 /* this does nothing useful, but leave it here in case that changes */ - /* the called routine adds 1 to the passed value */ - usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); -#endif - /* - * XXX - * This is potentially dangerous because it assumes - * that only one device is ever plugged in! - */ - devgone = dev; - } - } - - dev->status = stat; - dev->act_len = transfer_len; - -#ifdef DEBUG - pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); -#else - mdelay(1); -#endif - - /* free TDs in urb_priv */ - urb_free_priv (&urb_priv); - return 0; -} - -/* submit routines called from usb.c */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len) -{ - info("submit_bulk_msg"); - return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, struct devrequest *setup) -{ - int maxsize = usb_maxpacket(dev, pipe); - - info("submit_control_msg"); -#ifdef DEBUG - urb_priv.actual_length = 0; - pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); -#else - mdelay(1); -#endif - if (!maxsize) { - err("submit_control_message: pipesize for pipe %lx is zero", - pipe); - return -1; - } - if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { - gohci.rh.dev = dev; - /* root hub - redirect */ - return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, - setup); - } - - return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len, int interval) -{ - info("submit_int_msg"); - return -1; -} - -/*-------------------------------------------------------------------------* - * HC functions - *-------------------------------------------------------------------------*/ - -/* reset the HC and BUS */ - -static int hc_reset (ohci_t *ohci) -{ - int timeout = 30; - int smm_timeout = 50; /* 0,5 sec */ - - if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ - writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ - info("USB HC TakeOver from SMM"); - while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { - mdelay (10); - if (--smm_timeout == 0) { - err("USB HC TakeOver failed!"); - return -1; - } - } - } - - /* Disable HC interrupts */ - writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); - - dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", - ohci->slot_name, - readl (&ohci->regs->control)); - - /* Reset USB (needed by some controllers) */ - writel (0, &ohci->regs->control); - - /* HC Reset requires max 10 us delay */ - writel (OHCI_HCR, &ohci->regs->cmdstatus); - while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { - if (--timeout == 0) { - err("USB HC reset timed out!"); - return -1; - } - udelay (1); - } - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* Start an OHCI controller, set the BUS operational - * enable interrupts - * connect the virtual root hub */ - -static int hc_start (ohci_t * ohci) -{ - __u32 mask; - unsigned int fminterval; - - ohci->disabled = 1; - - /* Tell the controller where the control and bulk lists are - * The lists are empty now. */ - - writel (0, &ohci->regs->ed_controlhead); - writel (0, &ohci->regs->ed_bulkhead); - - writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ - - fminterval = 0x2edf; - writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); - fminterval |= ((((fminterval - 210) * 6) / 7) << 16); - writel (fminterval, &ohci->regs->fminterval); - writel (0x628, &ohci->regs->lsthresh); - - /* start controller operations */ - ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; - ohci->disabled = 0; - writel (ohci->hc_control, &ohci->regs->control); - - /* disable all interrupts */ - mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | - OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | - OHCI_INTR_OC | OHCI_INTR_MIE); - writel (mask, &ohci->regs->intrdisable); - /* clear all interrupts */ - mask &= ~OHCI_INTR_MIE; - writel (mask, &ohci->regs->intrstatus); - /* Choose the interrupts we care about now - but w/o MIE */ - mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; - writel (mask, &ohci->regs->intrenable); - -#ifdef OHCI_USE_NPS - /* required for AMD-756 and some Mac platforms */ - writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, - &ohci->regs->roothub.a); - writel (RH_HS_LPSC, &ohci->regs->roothub.status); -#endif /* OHCI_USE_NPS */ - - /* POTPGT delay is bits 24-31, in 2 ms units. */ - mdelay ((roothub_a (ohci) >> 23) & 0x1fe); - - /* connect the virtual root hub */ - ohci->rh.devnum = 0; - - return 0; -} - -/*-------------------------------------------------------------------------*/ - -/* an interrupt happens */ - -static int -hc_interrupt (void) -{ - ohci_t *ohci = &gohci; - struct ohci_regs *regs = ohci->regs; - int ints; - int stat = -1; - - if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { - ints = OHCI_INTR_WDH; - } else { - ints = readl (®s->intrstatus); - } - - /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ - - if (ints & OHCI_INTR_RHSC) { - got_rhsc = 1; - } - - if (ints & OHCI_INTR_UE) { - ohci->disabled++; - err ("OHCI Unrecoverable Error, controller usb-%s disabled", - ohci->slot_name); - /* e.g. due to PCI Master/Target Abort */ - -#ifdef DEBUG - ohci_dump (ohci, 1); -#else - mdelay(1); -#endif - /* FIXME: be optimistic, hope that bug won't repeat often. */ - /* Make some non-interrupt context restart the controller. */ - /* Count and limit the retries though; either hardware or */ - /* software errors can go forever... */ - hc_reset (ohci); - return -1; - } - - if (ints & OHCI_INTR_WDH) { - mdelay(1); - writel (OHCI_INTR_WDH, ®s->intrdisable); - stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); - writel (OHCI_INTR_WDH, ®s->intrenable); - } - - if (ints & OHCI_INTR_SO) { - dbg("USB Schedule overrun\n"); - writel (OHCI_INTR_SO, ®s->intrenable); - stat = -1; - } - - /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ - if (ints & OHCI_INTR_SF) { - unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; - mdelay(1); - writel (OHCI_INTR_SF, ®s->intrdisable); - if (ohci->ed_rm_list[frame] != NULL) - writel (OHCI_INTR_SF, ®s->intrenable); - stat = 0xff; - } - - writel (ints, ®s->intrstatus); - return stat; -} - -/*-------------------------------------------------------------------------*/ - -/*-------------------------------------------------------------------------*/ - -/* De-allocate all resources.. */ - -static void hc_release_ohci (ohci_t *ohci) -{ - dbg ("USB HC release ohci usb-%s", ohci->slot_name); - - if (!ohci->disabled) - hc_reset (ohci); -} - -/*-------------------------------------------------------------------------*/ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -/* - * low level initalisation routine, called from usb.c - */ -static char ohci_inited = 0; - -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - u32 pin_func; - u32 sys_freqctrl, sys_clksrc; - u32 prid = read_c0_prid(); - - dbg("in usb_lowlevel_init\n"); - - /* zero and disable FREQ2 */ - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* zero and disable USBH/USBD clocks */ - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~0x00007FE0; - au_writel(sys_clksrc, SYS_CLKSRC); - - sys_freqctrl = au_readl(SYS_FREQCTRL0); - sys_freqctrl &= ~0xFFF00000; - - sys_clksrc = au_readl(SYS_CLKSRC); - sys_clksrc &= ~0x00007FE0; - - switch (prid & 0x000000FF) { - case 0x00: /* DA */ - case 0x01: /* HA */ - case 0x02: /* HB */ - /* CPU core freq to 48MHz to slow it way down... */ - au_writel(4, SYS_CPUPLL); - - /* - * Setup 48MHz FREQ2 from CPUPLL for USB Host - */ - /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ - sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); - au_writel(sys_freqctrl, SYS_FREQCTRL0); - - /* CPU core freq to 384MHz */ - au_writel(0x20, SYS_CPUPLL); - - printf("Au1000: 48MHz OHCI workaround enabled\n"); - break; - - default: /* HC and newer */ - /* FREQ2 = aux/2 = 48 MHz */ - sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); - au_writel(sys_freqctrl, SYS_FREQCTRL0); - break; - } - - /* - * Route 48MHz FREQ2 into USB Host and/or Device - */ - sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); - au_writel(sys_clksrc, SYS_CLKSRC); - - /* configure pins GPIO[14:9] as GPIO */ - pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); - - au_writel(pin_func, SYS_PINFUNC); - au_writel(0x2800, SYS_TRIOUTCLR); - au_writel(0x0030, SYS_OUTPUTCLR); - - dbg("OHCI board setup complete\n"); - - /* enable host controller */ - au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG); - udelay(1000); - au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG); - udelay(1000); - - /* wait for reset complete (read register twice; see au1500 errata) */ - while (au_readl(USB_HOST_CONFIG), - !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD)) - udelay(1000); - - dbg("OHCI clock running\n"); - - memset (&gohci, 0, sizeof (ohci_t)); - memset (&urb_priv, 0, sizeof (urb_priv_t)); - - /* align the storage */ - if ((__u32)&ghcca[0] & 0xff) { - err("HCCA not aligned!!"); - return -1; - } - phcca = &ghcca[0]; - info("aligned ghcca %p", phcca); - memset(&ohci_dev, 0, sizeof(struct ohci_device)); - if ((__u32)&ohci_dev.ed[0] & 0x7) { - err("EDs not aligned!!"); - return -1; - } - memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); - if ((__u32)gtd & 0x7) { - err("TDs not aligned!!"); - return -1; - } - ptd = gtd; - gohci.hcca = phcca; - memset (phcca, 0, sizeof (struct ohci_hcca)); - - gohci.disabled = 1; - gohci.sleeping = 0; - gohci.irq = -1; - gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000); - - gohci.flags = 0; - gohci.slot_name = "au1x00"; - - dbg("OHCI revision: 0x%08x\n" - " RH: a: 0x%08x b: 0x%08x\n", - readl(&gohci.regs->revision), - readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b)); - - if (hc_reset (&gohci) < 0) - goto errout; - - /* FIXME this is a second HC reset; why?? */ - writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); - mdelay (10); - - if (hc_start (&gohci) < 0) - goto errout; - -#ifdef DEBUG - ohci_dump (&gohci, 1); -#else - mdelay(1); -#endif - ohci_inited = 1; - return 0; - - errout: - err("OHCI initialization error\n"); - hc_release_ohci (&gohci); - /* Initialization failed */ - au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); - return -1; -} - -int usb_lowlevel_stop(int index) -{ - /* this gets called really early - before the controller has */ - /* even been initialized! */ - if (!ohci_inited) - return 0; - /* TODO release any interrupts, etc. */ - /* call hc_release_ohci() here ? */ - hc_reset (&gohci); - /* may not want to do this */ - /* Disable clock */ - au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG); - return 0; -} - -#endif /* CONFIG_USB_OHCI */ diff --git a/arch/mips/mach-au1x00/au1x00_usb_ohci.h b/arch/mips/mach-au1x00/au1x00_usb_ohci.h deleted file mode 100644 index bb9f351099..0000000000 --- a/arch/mips/mach-au1x00/au1x00_usb_ohci.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * URB OHCI HCD (Host Controller Driver) for USB. - * - * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> - * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> - * - * usb-ohci.h - */ - - -static int cc_to_error[16] = { - -/* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 -}; - -/* ED States */ - -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 -#define ED_OPER 0x02 -#define ED_DEL 0x04 -#define ED_URB_DEL 0x08 - -/* usb_ohci_ed */ -struct ed { - __u32 hwINFO; - __u32 hwTailP; - __u32 hwHeadP; - __u32 hwNextED; - - struct ed *ed_prev; - __u8 int_period; - __u8 int_branch; - __u8 int_load; - __u8 int_interval; - __u8 state; - __u8 type; - __u16 last_iso; - struct ed *ed_rm_list; - - struct usb_device *usb_dev; - __u32 unused[3]; -} __attribute__((aligned(16))); -typedef struct ed ed_t; - - -/* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 - -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 - -/* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F - - -#define MAXPSW 1 - -struct td { - __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ - - __u16 hwPSW[MAXPSW]; - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; - struct usb_device *usb_dev; - int transfer_len; - __u32 data; - - __u32 unused2[2]; -} __attribute__((aligned(32))); -typedef struct td td_t; - -#define OHCI_ED_SKIP (1 << 14) - -/* - * The HCCA (Host Controller Communications Area) is a 256 byte - * structure defined in the OHCI spec. that the host controller is - * told the base address of. It must be 256-byte aligned. - */ - -#define NUM_INTS 32 /* part of the OHCI standard */ -struct ohci_hcca { - __u32 int_table[NUM_INTS]; /* Interrupt ED table */ - __u16 frame_no; /* current frame number */ - __u16 pad1; /* set to 0 on each frame_no change */ - __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; -} __attribute__((aligned(256))); - - -/* - * Maximum number of root hub ports. - */ -#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ - -/* - * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and - * writel() macros defined in asm/io.h to access these!! - */ -struct ohci_regs { - /* control and status registers */ - __u32 revision; - __u32 control; - __u32 cmdstatus; - __u32 intrstatus; - __u32 intrenable; - __u32 intrdisable; - /* memory pointers */ - __u32 hcca; - __u32 ed_periodcurrent; - __u32 ed_controlhead; - __u32 ed_controlcurrent; - __u32 ed_bulkhead; - __u32 ed_bulkcurrent; - __u32 donehead; - /* frame counters */ - __u32 fminterval; - __u32 fmremaining; - __u32 fmnumber; - __u32 periodicstart; - __u32 lsthresh; - /* Root hub ports */ - struct ohci_roothub_regs { - __u32 a; - __u32 b; - __u32 status; - __u32 portstatus[MAX_ROOT_PORTS]; - } roothub; -} __attribute__((aligned(32))); - - -/* OHCI CONTROL AND STATUS REGISTER MASKS */ - -/* - * HcControl (control) register masks - */ -#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ -#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ -#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ -#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ -#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ -#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ -#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ -#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ -#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ - -/* pre-shifted values for HCFS */ -# define OHCI_USB_RESET (0 << 6) -# define OHCI_USB_RESUME (1 << 6) -# define OHCI_USB_OPER (2 << 6) -# define OHCI_USB_SUSPEND (3 << 6) - -/* - * HcCommandStatus (cmdstatus) register masks - */ -#define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ - -/* - * masks used with interrupt registers: - * HcInterruptStatus (intrstatus) - * HcInterruptEnable (intrenable) - * HcInterruptDisable (intrdisable) - */ -#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ -#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ -#define OHCI_INTR_SF (1 << 2) /* start frame */ -#define OHCI_INTR_RD (1 << 3) /* resume detect */ -#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ -#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ -#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ -#define OHCI_INTR_OC (1 << 30) /* ownership change */ -#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ - - -/* Virtual Root HUB */ -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - void *dev; /* was urb */ - void *int_addr; - int send; - int interval; -}; - -/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ - -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 - -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* OHCI ROOT HUB REGISTER MASKS */ - -/* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ - -/* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ - -/* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ - -/* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ - -/* urb */ -#define N_URB_TD 48 -typedef struct -{ - ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ - int state; - unsigned long pipe; - int actual_length; - td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ -} urb_priv_t; -#define URB_DEL 1 - -/* - * This is the full ohci controller description - * - * Note how the "proper" USB information is just - * a subset of what the full implementation needs. (Linus) - */ - - -typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma;*/ - - int irq; - int disabled; /* e.g. got a UE, we're hung */ - int sleeping; - unsigned long flags; /* for HC bugs */ - - struct ohci_regs *regs; /* OHCI controller's memory */ - - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ - int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ - struct usb_device *dev[32]; - struct virt_root_hub rh; - - const char *slot_name; -} ohci_t; - -#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ - -struct ohci_device { - ed_t ed[NUM_EDS]; - int ed_cnt; -}; - -/* hcd */ -/* endpoint */ -static int ep_link(ohci_t * ohci, ed_t * ed); -static int ep_unlink(ohci_t * ohci, ed_t * ed); -static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); - -/*-------------------------------------------------------------------------*/ - -/* we need more TDs than EDs */ -#define NUM_TD 64 - -/* +1 so we can align the storage */ -td_t gtd[NUM_TD+1]; -/* pointers to aligned storage */ -td_t *ptd; - -/* TDs ... */ -static inline struct td * -td_alloc (struct usb_device *usb_dev) -{ - int i; - struct td *td; - - td = NULL; - for (i = 0; i < NUM_TD; i++) { - if (ptd[i].usb_dev == NULL) { - td = &ptd[i]; - td->usb_dev = usb_dev; - break; - } - } - return td; -} - -static inline void -ed_free (struct ed *ed) -{ - ed->usb_dev = NULL; -} diff --git a/arch/mips/mach-au1x00/include/mach/au1x00.h b/arch/mips/mach-au1x00/include/mach/au1x00.h deleted file mode 100644 index e242489978..0000000000 --- a/arch/mips/mach-au1x00/include/mach/au1x00.h +++ /dev/null @@ -1,1071 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * BRIEF MODULE DESCRIPTION - * Include file for Alchemy Semiconductor's Au1k CPU. - * - * Copyright 2000,2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - */ - - /* - * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp - */ - -#ifndef _AU1X00_H_ -#define _AU1X00_H_ - -#ifndef __ASSEMBLY__ -/* cpu pipeline flush */ -void static inline au_sync(void) -{ - __asm__ volatile ("sync"); -} - -void static inline au_sync_udelay(int us) -{ - __asm__ volatile ("sync"); - udelay(us); -} - -void static inline au_writeb(u8 val, int reg) -{ - *(volatile u8 *)(reg) = val; -} - -void static inline au_writew(u16 val, int reg) -{ - *(volatile u16 *)(reg) = val; -} - -void static inline au_writel(u32 val, int reg) -{ - *(volatile u32 *)(reg) = val; -} - -static inline u8 au_readb(unsigned long port) -{ - return (*(volatile u8 *)port); -} - -static inline u16 au_readw(unsigned long port) -{ - return (*(volatile u16 *)port); -} - -static inline u32 au_readl(unsigned long port) -{ - return (*(volatile u32 *)port); -} - -/* These next three functions should be a generic part of the MIPS - * kernel (with the 'au_' removed from the name) and selected for - * processors that support the instructions. - * Taken from PPC tree. -- Dan - */ -/* Return the bit position of the most significant 1 bit in a word */ -static __inline__ int __ilog2(unsigned int x) -{ - int lz; - - asm volatile ( - ".set\tnoreorder\n\t" - ".set\tnoat\n\t" - ".set\tmips32\n\t" - "clz\t%0,%1\n\t" - ".set\tmips0\n\t" - ".set\tat\n\t" - ".set\treorder" - : "=r" (lz) - : "r" (x)); - - return 31 - lz; -} - -static __inline__ int au_ffz(unsigned int x) -{ - if ((x = ~x) == 0) - return 32; - return __ilog2(x & -x); -} - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -static __inline__ int au_ffs(int x) -{ - return __ilog2(x & -x) + 1; -} - -#define gpio_set(Value) outl(Value, SYS_OUTPUTSET) -#define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR) -#define gpio_read() inl(SYS_PINSTATERD) -#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR) - -#endif /* !ASSEMBLY */ - -#ifdef CONFIG_PM -/* no CP0 timer irq */ -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) -#else -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) -#endif - -#define CP0_IWATCHLO $18,1 -#define CP0_DEBUG $23 - -/* SDRAM Controller */ -#ifdef CONFIG_SOC_AU1550 - -#define MEM_SDMODE0 0xB4000800 -#define MEM_SDMODE1 0xB4000808 -#define MEM_SDMODE2 0xB4000810 - -#define MEM_SDADDR0 0xB4000820 -#define MEM_SDADDR1 0xB4000828 -#define MEM_SDADDR2 0xB4000830 - -#define MEM_SDCONFIGA 0xB4000840 -#define MEM_SDCONFIGB 0xB4000848 -#define MEM_SDPRECMD 0xB40008c0 -#define MEM_SDAUTOREF 0xB40008c8 - -#define MEM_SDWRMD0 0xB4000880 -#define MEM_SDWRMD1 0xB4000888 -#define MEM_SDWRMD2 0xB4000890 - -#else /* CONFIG_SOC_AU1550 */ - -#define MEM_SDMODE0 0xB4000000 -#define MEM_SDMODE1 0xB4000004 -#define MEM_SDMODE2 0xB4000008 - -#define MEM_SDADDR0 0xB400000C -#define MEM_SDADDR1 0xB4000010 -#define MEM_SDADDR2 0xB4000014 - -#define MEM_SDREFCFG 0xB4000018 -#define MEM_SDPRECMD 0xB400001C -#define MEM_SDAUTOREF 0xB4000020 - -#define MEM_SDWRMD0 0xB4000024 -#define MEM_SDWRMD1 0xB4000028 -#define MEM_SDWRMD2 0xB400002C - -#endif /* CONFIG_SOC_AU1550 */ - -#define MEM_SDSLEEP 0xB4000030 -#define MEM_SDSMCKE 0xB4000034 - -/* Static Bus Controller */ -#define MEM_STCFG0 0xB4001000 -#define MEM_STTIME0 0xB4001004 -#define MEM_STADDR0 0xB4001008 - -#define MEM_STCFG1 0xB4001010 -#define MEM_STTIME1 0xB4001014 -#define MEM_STADDR1 0xB4001018 - -#define MEM_STCFG2 0xB4001020 -#define MEM_STTIME2 0xB4001024 -#define MEM_STADDR2 0xB4001028 - -#define MEM_STCFG3 0xB4001030 -#define MEM_STTIME3 0xB4001034 -#define MEM_STADDR3 0xB4001038 - -/* Interrupt Controller 0 */ -#define IC0_CFG0RD 0xB0400040 -#define IC0_CFG0SET 0xB0400040 -#define IC0_CFG0CLR 0xB0400044 - -#define IC0_CFG1RD 0xB0400048 -#define IC0_CFG1SET 0xB0400048 -#define IC0_CFG1CLR 0xB040004C - -#define IC0_CFG2RD 0xB0400050 -#define IC0_CFG2SET 0xB0400050 -#define IC0_CFG2CLR 0xB0400054 - -#define IC0_REQ0INT 0xB0400054 -#define IC0_SRCRD 0xB0400058 -#define IC0_SRCSET 0xB0400058 -#define IC0_SRCCLR 0xB040005C -#define IC0_REQ1INT 0xB040005C - -#define IC0_ASSIGNRD 0xB0400060 -#define IC0_ASSIGNSET 0xB0400060 -#define IC0_ASSIGNCLR 0xB0400064 - -#define IC0_WAKERD 0xB0400068 -#define IC0_WAKESET 0xB0400068 -#define IC0_WAKECLR 0xB040006C - -#define IC0_MASKRD 0xB0400070 -#define IC0_MASKSET 0xB0400070 -#define IC0_MASKCLR 0xB0400074 - -#define IC0_RISINGRD 0xB0400078 -#define IC0_RISINGCLR 0xB0400078 -#define IC0_FALLINGRD 0xB040007C -#define IC0_FALLINGCLR 0xB040007C - -#define IC0_TESTBIT 0xB0400080 - -/* Interrupt Controller 1 */ -#define IC1_CFG0RD 0xB1800040 -#define IC1_CFG0SET 0xB1800040 -#define IC1_CFG0CLR 0xB1800044 - -#define IC1_CFG1RD 0xB1800048 -#define IC1_CFG1SET 0xB1800048 -#define IC1_CFG1CLR 0xB180004C - -#define IC1_CFG2RD 0xB1800050 -#define IC1_CFG2SET 0xB1800050 -#define IC1_CFG2CLR 0xB1800054 - -#define IC1_REQ0INT 0xB1800054 -#define IC1_SRCRD 0xB1800058 -#define IC1_SRCSET 0xB1800058 -#define IC1_SRCCLR 0xB180005C -#define IC1_REQ1INT 0xB180005C - -#define IC1_ASSIGNRD 0xB1800060 -#define IC1_ASSIGNSET 0xB1800060 -#define IC1_ASSIGNCLR 0xB1800064 - -#define IC1_WAKERD 0xB1800068 -#define IC1_WAKESET 0xB1800068 -#define IC1_WAKECLR 0xB180006C - -#define IC1_MASKRD 0xB1800070 -#define IC1_MASKSET 0xB1800070 -#define IC1_MASKCLR 0xB1800074 - -#define IC1_RISINGRD 0xB1800078 -#define IC1_RISINGCLR 0xB1800078 -#define IC1_FALLINGRD 0xB180007C -#define IC1_FALLINGCLR 0xB180007C - -#define IC1_TESTBIT 0xB1800080 - -/* Interrupt Configuration Modes */ -#define INTC_INT_DISABLED 0 -#define INTC_INT_RISE_EDGE 0x1 -#define INTC_INT_FALL_EDGE 0x2 -#define INTC_INT_RISE_AND_FALL_EDGE 0x3 -#define INTC_INT_HIGH_LEVEL 0x5 -#define INTC_INT_LOW_LEVEL 0x6 -#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 - -/* Interrupt Numbers */ -#define AU1X00_UART0_INT 0 -#define AU1000_UART1_INT 1 /* au1000 */ -#define AU1000_UART2_INT 2 /* au1000 */ - -#define AU1500_PCI_INTA 1 /* au1500 */ -#define AU1500_PCI_INTB 2 /* au1500 */ - -#define AU1X00_UART3_INT 3 - -#define AU1000_SSI0_INT 4 /* au1000 */ -#define AU1000_SSI1_INT 5 /* au1000 */ - -#define AU1500_PCI_INTC 4 /* au1500 */ -#define AU1500_PCI_INTD 5 /* au1500 */ - -#define AU1X00_DMA_INT_BASE 6 -#define AU1X00_TOY_INT 14 -#define AU1X00_TOY_MATCH0_INT 15 -#define AU1X00_TOY_MATCH1_INT 16 -#define AU1X00_TOY_MATCH2_INT 17 -#define AU1X00_RTC_INT 18 -#define AU1X00_RTC_MATCH0_INT 19 -#define AU1X00_RTC_MATCH1_INT 20 -#define AU1X00_RTC_MATCH2_INT 21 -#define AU1000_IRDA_TX_INT 22 /* au1000 */ -#define AU1000_IRDA_RX_INT 23 /* au1000 */ -#define AU1X00_USB_DEV_REQ_INT 24 -#define AU1X00_USB_DEV_SUS_INT 25 -#define AU1X00_USB_HOST_INT 26 -#define AU1X00_ACSYNC_INT 27 -#define AU1X00_MAC0_DMA_INT 28 -#define AU1X00_MAC1_DMA_INT 29 -#define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT -#define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT -#define AU1000_I2S_UO_INT 30 /* au1000 */ -#define AU1X00_AC97C_INT 31 -#define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT -#define AU1X00_GPIO_0 32 -#define AU1X00_GPIO_1 33 -#define AU1X00_GPIO_2 34 -#define AU1X00_GPIO_3 35 -#define AU1X00_GPIO_4 36 -#define AU1X00_GPIO_5 37 -#define AU1X00_GPIO_6 38 -#define AU1X00_GPIO_7 39 -#define AU1X00_GPIO_8 40 -#define AU1X00_GPIO_9 41 -#define AU1X00_GPIO_10 42 -#define AU1X00_GPIO_11 43 -#define AU1X00_GPIO_12 44 -#define AU1X00_GPIO_13 45 -#define AU1X00_GPIO_14 46 -#define AU1X00_GPIO_15 47 - -/* Au1000 only */ -#define AU1000_GPIO_16 48 -#define AU1000_GPIO_17 49 -#define AU1000_GPIO_18 50 -#define AU1000_GPIO_19 51 -#define AU1000_GPIO_20 52 -#define AU1000_GPIO_21 53 -#define AU1000_GPIO_22 54 -#define AU1000_GPIO_23 55 -#define AU1000_GPIO_24 56 -#define AU1000_GPIO_25 57 -#define AU1000_GPIO_26 58 -#define AU1000_GPIO_27 59 -#define AU1000_GPIO_28 60 -#define AU1000_GPIO_29 61 -#define AU1000_GPIO_30 62 -#define AU1000_GPIO_31 63 - -/* Au1500 only */ -#define AU1500_GPIO_200 48 -#define AU1500_GPIO_201 49 -#define AU1500_GPIO_202 50 -#define AU1500_GPIO_203 51 -#define AU1500_GPIO_20 52 -#define AU1500_GPIO_204 53 -#define AU1500_GPIO_205 54 -#define AU1500_GPIO_23 55 -#define AU1500_GPIO_24 56 -#define AU1500_GPIO_25 57 -#define AU1500_GPIO_26 58 -#define AU1500_GPIO_27 59 -#define AU1500_GPIO_28 60 -#define AU1500_GPIO_206 61 -#define AU1500_GPIO_207 62 -#define AU1500_GPIO_208_215 63 - -#define AU1X00_MAX_INTR 63 - -#define AU1100_SD 2 -#define AU1100_GPIO_208_215 29 -/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */ - -/* Programmable Counters 0 and 1 */ -#define SYS_BASE 0xB1900000 -#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) -#define SYS_CNTRL_E1S (1<<23) -#define SYS_CNTRL_T1S (1<<20) -#define SYS_CNTRL_M21 (1<<19) -#define SYS_CNTRL_M11 (1<<18) -#define SYS_CNTRL_M01 (1<<17) -#define SYS_CNTRL_C1S (1<<16) -#define SYS_CNTRL_BP (1<<14) -#define SYS_CNTRL_EN1 (1<<13) -#define SYS_CNTRL_BT1 (1<<12) -#define SYS_CNTRL_EN0 (1<<11) -#define SYS_CNTRL_BT0 (1<<10) -#define SYS_CNTRL_E0 (1<<8) -#define SYS_CNTRL_E0S (1<<7) -#define SYS_CNTRL_32S (1<<5) -#define SYS_CNTRL_T0S (1<<4) -#define SYS_CNTRL_M20 (1<<3) -#define SYS_CNTRL_M10 (1<<2) -#define SYS_CNTRL_M00 (1<<1) -#define SYS_CNTRL_C0S (1<<0) - -/* Programmable Counter 0 Registers */ -#define SYS_TOYTRIM (SYS_BASE + 0) -#define SYS_TOYWRITE (SYS_BASE + 4) -#define SYS_TOYMATCH0 (SYS_BASE + 8) -#define SYS_TOYMATCH1 (SYS_BASE + 0xC) -#define SYS_TOYMATCH2 (SYS_BASE + 0x10) -#define SYS_TOYREAD (SYS_BASE + 0x40) - -/* Programmable Counter 1 Registers */ -#define SYS_RTCTRIM (SYS_BASE + 0x44) -#define SYS_RTCWRITE (SYS_BASE + 0x48) -#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) -#define SYS_RTCMATCH1 (SYS_BASE + 0x50) -#define SYS_RTCMATCH2 (SYS_BASE + 0x54) -#define SYS_RTCREAD (SYS_BASE + 0x58) - -/* I2S Controller */ -#define I2S_DATA 0xB1000000 -#define I2S_DATA_MASK (0xffffff) -#define I2S_CONFIG 0xB1000004 -#define I2S_CONFIG_XU (1<<25) -#define I2S_CONFIG_XO (1<<24) -#define I2S_CONFIG_RU (1<<23) -#define I2S_CONFIG_RO (1<<22) -#define I2S_CONFIG_TR (1<<21) -#define I2S_CONFIG_TE (1<<20) -#define I2S_CONFIG_TF (1<<19) -#define I2S_CONFIG_RR (1<<18) -#define I2S_CONFIG_RE (1<<17) -#define I2S_CONFIG_RF (1<<16) -#define I2S_CONFIG_PD (1<<11) -#define I2S_CONFIG_LB (1<<10) -#define I2S_CONFIG_IC (1<<9) -#define I2S_CONFIG_FM_BIT 7 -#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) -#define I2S_CONFIG_TN (1<<6) -#define I2S_CONFIG_RN (1<<5) -#define I2S_CONFIG_SZ_BIT 0 -#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) - -#define I2S_CONTROL 0xB1000008 -#define I2S_CONTROL_D (1<<1) -#define I2S_CONTROL_CE (1<<0) - -/* USB Host Controller */ -/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */ -#define USB_OHCI_BASE 0x10100000 -#define USB_OHCI_LEN 0x00100000 -#define USB_HOST_CONFIG 0xB017fffc - -/* USB Device Controller */ -#define USBD_EP0RD 0xB0200000 -#define USBD_EP0WR 0xB0200004 -#define USBD_EP2WR 0xB0200008 -#define USBD_EP3WR 0xB020000C -#define USBD_EP4RD 0xB0200010 -#define USBD_EP5RD 0xB0200014 -#define USBD_INTEN 0xB0200018 -#define USBD_INTSTAT 0xB020001C -#define USBDEV_INT_SOF (1<<12) -#define USBDEV_INT_HF_BIT 6 -#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) -#define USBDEV_INT_CMPLT_BIT 0 -#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) -#define USBD_CONFIG 0xB0200020 -#define USBD_EP0CS 0xB0200024 -#define USBD_EP2CS 0xB0200028 -#define USBD_EP3CS 0xB020002C -#define USBD_EP4CS 0xB0200030 -#define USBD_EP5CS 0xB0200034 -#define USBDEV_CS_SU (1<<14) -#define USBDEV_CS_NAK (1<<13) -#define USBDEV_CS_ACK (1<<12) -#define USBDEV_CS_BUSY (1<<11) -#define USBDEV_CS_TSIZE_BIT 1 -#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) -#define USBDEV_CS_STALL (1<<0) -#define USBD_EP0RDSTAT 0xB0200040 -#define USBD_EP0WRSTAT 0xB0200044 -#define USBD_EP2WRSTAT 0xB0200048 -#define USBD_EP3WRSTAT 0xB020004C -#define USBD_EP4RDSTAT 0xB0200050 -#define USBD_EP5RDSTAT 0xB0200054 -#define USBDEV_FSTAT_FLUSH (1<<6) -#define USBDEV_FSTAT_UF (1<<5) -#define USBDEV_FSTAT_OF (1<<4) -#define USBDEV_FSTAT_FCNT_BIT 0 -#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) -#define USBD_ENABLE 0xB0200058 -#define USBDEV_ENABLE (1<<1) -#define USBDEV_CE (1<<0) - -/* Ethernet Controllers */ -#define AU1000_ETH0_BASE 0xB0500000 -#define AU1000_ETH1_BASE 0xB0510000 -#define AU1500_ETH0_BASE 0xB1500000 -#define AU1500_ETH1_BASE 0xB1510000 -#define AU1100_ETH0_BASE 0xB0500000 -#define AU1550_ETH0_BASE 0xB0500000 -#define AU1550_ETH1_BASE 0xB0510000 - -/* 4 byte offsets from AU1000_ETH_BASE */ -#define MAC_CONTROL 0x0 -#define MAC_RX_ENABLE (1<<2) -#define MAC_TX_ENABLE (1<<3) -#define MAC_DEF_CHECK (1<<5) -#define MAC_SET_BL(X) (((X)&0x3)<<6) -#define MAC_AUTO_PAD (1<<8) -#define MAC_DISABLE_RETRY (1<<10) -#define MAC_DISABLE_BCAST (1<<11) -#define MAC_LATE_COL (1<<12) -#define MAC_HASH_MODE (1<<13) -#define MAC_HASH_ONLY (1<<15) -#define MAC_PASS_ALL (1<<16) -#define MAC_INVERSE_FILTER (1<<17) -#define MAC_PROMISCUOUS (1<<18) -#define MAC_PASS_ALL_MULTI (1<<19) -#define MAC_FULL_DUPLEX (1<<20) -#define MAC_NORMAL_MODE 0 -#define MAC_INT_LOOPBACK (1<<21) -#define MAC_EXT_LOOPBACK (1<<22) -#define MAC_DISABLE_RX_OWN (1<<23) -#define MAC_BIG_ENDIAN (1<<30) -#define MAC_RX_ALL (1<<31) -#define MAC_ADDRESS_HIGH 0x4 -#define MAC_ADDRESS_LOW 0x8 -#define MAC_MCAST_HIGH 0xC -#define MAC_MCAST_LOW 0x10 -#define MAC_MII_CNTRL 0x14 -#define MAC_MII_BUSY (1<<0) -#define MAC_MII_READ 0 -#define MAC_MII_WRITE (1<<1) -#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) -#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) -#define MAC_MII_DATA 0x18 -#define MAC_FLOW_CNTRL 0x1C -#define MAC_FLOW_CNTRL_BUSY (1<<0) -#define MAC_FLOW_CNTRL_ENABLE (1<<1) -#define MAC_PASS_CONTROL (1<<2) -#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) -#define MAC_VLAN1_TAG 0x20 -#define MAC_VLAN2_TAG 0x24 - -/* Ethernet Controller Enable */ -#define AU1000_MAC0_ENABLE 0xB0520000 -#define AU1000_MAC1_ENABLE 0xB0520004 -#define AU1500_MAC0_ENABLE 0xB1520000 -#define AU1500_MAC1_ENABLE 0xB1520004 -#define AU1100_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC0_ENABLE 0xB0520000 -#define AU1550_MAC1_ENABLE 0xB0520004 - -#define MAC_EN_CLOCK_ENABLE (1<<0) -#define MAC_EN_RESET0 (1<<1) -#define MAC_EN_TOSS (0<<2) -#define MAC_EN_CACHEABLE (1<<3) -#define MAC_EN_RESET1 (1<<4) -#define MAC_EN_RESET2 (1<<5) -#define MAC_DMA_RESET (1<<6) - -/* Ethernet Controller DMA Channels */ - -#define MAC0_TX_DMA_ADDR 0xB4004000 -#define MAC1_TX_DMA_ADDR 0xB4004200 -/* offsets from MAC_TX_RING_ADDR address */ -#define MAC_TX_BUFF0_STATUS 0x0 -#define TX_FRAME_ABORTED (1<<0) -#define TX_JAB_TIMEOUT (1<<1) -#define TX_NO_CARRIER (1<<2) -#define TX_LOSS_CARRIER (1<<3) -#define TX_EXC_DEF (1<<4) -#define TX_LATE_COLL_ABORT (1<<5) -#define TX_EXC_COLL (1<<6) -#define TX_UNDERRUN (1<<7) -#define TX_DEFERRED (1<<8) -#define TX_LATE_COLL (1<<9) -#define TX_COLL_CNT_MASK (0xF<<10) -#define TX_PKT_RETRY (1<<31) -#define MAC_TX_BUFF0_ADDR 0x4 -#define TX_DMA_ENABLE (1<<0) -#define TX_T_DONE (1<<1) -#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) -#define MAC_TX_BUFF0_LEN 0x8 -#define MAC_TX_BUFF1_STATUS 0x10 -#define MAC_TX_BUFF1_ADDR 0x14 -#define MAC_TX_BUFF1_LEN 0x18 -#define MAC_TX_BUFF2_STATUS 0x20 -#define MAC_TX_BUFF2_ADDR 0x24 -#define MAC_TX_BUFF2_LEN 0x28 -#define MAC_TX_BUFF3_STATUS 0x30 -#define MAC_TX_BUFF3_ADDR 0x34 -#define MAC_TX_BUFF3_LEN 0x38 - -#define MAC0_RX_DMA_ADDR 0xB4004100 -#define MAC1_RX_DMA_ADDR 0xB4004300 -/* offsets from MAC_RX_RING_ADDR */ -#define MAC_RX_BUFF0_STATUS 0x0 -#define RX_FRAME_LEN_MASK 0x3fff -#define RX_WDOG_TIMER (1<<14) -#define RX_RUNT (1<<15) -#define RX_OVERLEN (1<<16) -#define RX_COLL (1<<17) -#define RX_ETHER (1<<18) -#define RX_MII_ERROR (1<<19) -#define RX_DRIBBLING (1<<20) -#define RX_CRC_ERROR (1<<21) -#define RX_VLAN1 (1<<22) -#define RX_VLAN2 (1<<23) -#define RX_LEN_ERROR (1<<24) -#define RX_CNTRL_FRAME (1<<25) -#define RX_U_CNTRL_FRAME (1<<26) -#define RX_MCAST_FRAME (1<<27) -#define RX_BCAST_FRAME (1<<28) -#define RX_FILTER_FAIL (1<<29) -#define RX_PACKET_FILTER (1<<30) -#define RX_MISSED_FRAME (1<<31) - -#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ - RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ - RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) -#define MAC_RX_BUFF0_ADDR 0x4 -#define RX_DMA_ENABLE (1<<0) -#define RX_T_DONE (1<<1) -#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) -#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) -#define MAC_RX_BUFF1_STATUS 0x10 -#define MAC_RX_BUFF1_ADDR 0x14 -#define MAC_RX_BUFF2_STATUS 0x20 -#define MAC_RX_BUFF2_ADDR 0x24 -#define MAC_RX_BUFF3_STATUS 0x30 -#define MAC_RX_BUFF3_ADDR 0x34 - - -/* UARTS 0-3 */ -#define UART0_ADDR 0xB1100000 -#define UART1_ADDR 0xB1200000 -#define UART2_ADDR 0xB1300000 -#define UART3_ADDR 0xB1400000 -#define UART_BASE UART0_ADDR -#define UART_DEBUG_BASE UART2_ADDR - -#define UART_RX 0 /* Receive buffer */ -#define UART_TX 4 /* Transmit buffer */ -#define UART_IER 8 /* Interrupt Enable Register */ -#define UART_IIR 0xC /* Interrupt ID Register */ -#define UART_FCR 0x10 /* FIFO Control Register */ -#define UART_LCR 0x14 /* Line Control Register */ -#define UART_MCR 0x18 /* Modem Control Register */ -#define UART_LSR 0x1C /* Line Status Register */ -#define UART_MSR 0x20 /* Modem Status Register */ -#define UART_CLK 0x28 /* Baud Rate Clock Divider */ -#define UART_ENABLE 0x100 /* Uart enable */ - -#define UART_EN_CE 1 /* Clock enable */ -#define UART_EN_E 2 /* Enable */ - -#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ -#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ -#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ -#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ -#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ -#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ -#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ -#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ -#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ - -/* - * These are the definitions for the Line Control Register - */ -#define UART_LCR_SBC 0x40 /* Set break control */ -#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ -#define UART_LCR_EPAR 0x10 /* Even parity select */ -#define UART_LCR_PARITY 0x08 /* Parity Enable */ -#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ -#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ -#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ -#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ -#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ - -/* - * These are the definitions for the Line Status Register - */ -#define UART_LSR_TEMT 0x40 /* Transmitter empty */ -#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ -#define UART_LSR_BI 0x10 /* Break interrupt indicator */ -#define UART_LSR_FE 0x08 /* Frame error indicator */ -#define UART_LSR_PE 0x04 /* Parity error indicator */ -#define UART_LSR_OE 0x02 /* Overrun error indicator */ -#define UART_LSR_DR 0x01 /* Receiver data ready */ - -/* - * These are the definitions for the Interrupt Identification Register - */ -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -/* - * These are the definitions for the Interrupt Enable Register - */ -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -/* - * These are the definitions for the Modem Control Register - */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_OUT2 0x08 /* Out2 complement */ -#define UART_MCR_OUT1 0x04 /* Out1 complement */ -#define UART_MCR_RTS 0x02 /* RTS complement */ -#define UART_MCR_DTR 0x01 /* DTR complement */ - -/* - * These are the definitions for the Modem Status Register - */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ -#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ - - -/* SSIO */ -#define SSI0_STATUS 0xB1600000 -#define SSI_STATUS_BF (1<<4) -#define SSI_STATUS_OF (1<<3) -#define SSI_STATUS_UF (1<<2) -#define SSI_STATUS_D (1<<1) -#define SSI_STATUS_B (1<<0) -#define SSI0_INT 0xB1600004 -#define SSI_INT_OI (1<<3) -#define SSI_INT_UI (1<<2) -#define SSI_INT_DI (1<<1) -#define SSI0_INT_ENABLE 0xB1600008 -#define SSI_INTE_OIE (1<<3) -#define SSI_INTE_UIE (1<<2) -#define SSI_INTE_DIE (1<<1) -#define SSI0_CONFIG 0xB1600020 -#define SSI_CONFIG_AO (1<<24) -#define SSI_CONFIG_DO (1<<23) -#define SSI_CONFIG_ALEN_BIT 20 -#define SSI_CONFIG_ALEN_MASK (0x7<<20) -#define SSI_CONFIG_DLEN_BIT 16 -#define SSI_CONFIG_DLEN_MASK (0x7<<16) -#define SSI_CONFIG_DD (1<<11) -#define SSI_CONFIG_AD (1<<10) -#define SSI_CONFIG_BM_BIT 8 -#define SSI_CONFIG_BM_MASK (0x3<<8) -#define SSI_CONFIG_CE (1<<7) -#define SSI_CONFIG_DP (1<<6) -#define SSI_CONFIG_DL (1<<5) -#define SSI_CONFIG_EP (1<<4) -#define SSI0_ADATA 0xB1600024 -#define SSI_AD_D (1<<24) -#define SSI_AD_ADDR_BIT 16 -#define SSI_AD_ADDR_MASK (0xff<<16) -#define SSI_AD_DATA_BIT 0 -#define SSI_AD_DATA_MASK (0xfff<<0) -#define SSI0_CLKDIV 0xB1600028 -#define SSI0_CONTROL 0xB1600100 -#define SSI_CONTROL_CD (1<<1) -#define SSI_CONTROL_E (1<<0) - -/* SSI1 */ -#define SSI1_STATUS 0xB1680000 -#define SSI1_INT 0xB1680004 -#define SSI1_INT_ENABLE 0xB1680008 -#define SSI1_CONFIG 0xB1680020 -#define SSI1_ADATA 0xB1680024 -#define SSI1_CLKDIV 0xB1680028 -#define SSI1_ENABLE 0xB1680100 - -/* - * Register content definitions - */ -#define SSI_STATUS_BF (1<<4) -#define SSI_STATUS_OF (1<<3) -#define SSI_STATUS_UF (1<<2) -#define SSI_STATUS_D (1<<1) -#define SSI_STATUS_B (1<<0) - -/* SSI_INT */ -#define SSI_INT_OI (1<<3) -#define SSI_INT_UI (1<<2) -#define SSI_INT_DI (1<<1) - -/* SSI_INTEN */ -#define SSI_INTEN_OIE (1<<3) -#define SSI_INTEN_UIE (1<<2) -#define SSI_INTEN_DIE (1<<1) - -#define SSI_CONFIG_AO (1<<24) -#define SSI_CONFIG_DO (1<<23) -#define SSI_CONFIG_ALEN (7<<20) -#define SSI_CONFIG_DLEN (15<<16) -#define SSI_CONFIG_DD (1<<11) -#define SSI_CONFIG_AD (1<<10) -#define SSI_CONFIG_BM (3<<8) -#define SSI_CONFIG_CE (1<<7) -#define SSI_CONFIG_DP (1<<6) -#define SSI_CONFIG_DL (1<<5) -#define SSI_CONFIG_EP (1<<4) -#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) -#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) -#define SSI_CONFIG_BM_HI (0<<8) -#define SSI_CONFIG_BM_LO (1<<8) -#define SSI_CONFIG_BM_CY (2<<8) - -#define SSI_ADATA_D (1<<24) -#define SSI_ADATA_ADDR (0xFF<<16) -#define SSI_ADATA_DATA (0x0FFF) -#define SSI_ADATA_ADDR_N(N) (N<<16) - -#define SSI_ENABLE_CD (1<<1) -#define SSI_ENABLE_E (1<<0) - - -/* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) -#define IR_RING_SIZE (IRDA_BASE+0x0C) -#define IR_RING_PROMPT (IRDA_BASE+0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) -#define IR_INT_CLEAR (IRDA_BASE+0x18) -#define IR_CONFIG_1 (IRDA_BASE+0x20) -#define IR_RX_INVERT_LED (1<<0) -#define IR_TX_INVERT_LED (1<<1) -#define IR_ST (1<<2) -#define IR_SF (1<<3) -#define IR_SIR (1<<4) -#define IR_MIR (1<<5) -#define IR_FIR (1<<6) -#define IR_16CRC (1<<7) -#define IR_TD (1<<8) -#define IR_RX_ALL (1<<9) -#define IR_DMA_ENABLE (1<<10) -#define IR_RX_ENABLE (1<<11) -#define IR_TX_ENABLE (1<<12) -#define IR_LOOPBACK (1<<14) -#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE+0x24) -#define IR_ENABLE (IRDA_BASE+0x28) -#define IR_RX_STATUS (1<<9) -#define IR_TX_STATUS (1<<10) -#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) -#define IR_CONFIG_2 (IRDA_BASE+0x3C) -#define IR_MODE_INV (1<<0) -#define IR_ONE_PIN (1<<1) -#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) - -/* GPIO */ -#define SYS_PINFUNC 0xB190002C -#define SYS_PF_USB (1<<15) /* 2nd USB device/host */ -#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ -#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ -#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ -#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ -#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ -#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ -#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ -#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ -#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ -#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ -#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ -#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ -#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ -#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ -#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ -#define SYS_TRIOUTRD 0xB1900100 -#define SYS_TRIOUTCLR 0xB1900100 -#define SYS_OUTPUTRD 0xB1900108 -#define SYS_OUTPUTSET 0xB1900108 -#define SYS_OUTPUTCLR 0xB190010C -#define SYS_PINSTATERD 0xB1900110 -#define SYS_PININPUTEN 0xB1900110 - -/* GPIO2, Au1500 only */ -#define GPIO2_BASE 0xB1700000 -#define GPIO2_DIR (GPIO2_BASE + 0) -#define GPIO2_DATA_EN (GPIO2_BASE + 8) -#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) -#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10) -#define GPIO2_ENABLE (GPIO2_BASE + 0x14) - -/* Power Management */ -#define SYS_SCRATCH0 0xB1900018 -#define SYS_SCRATCH1 0xB190001C -#define SYS_WAKEMSK 0xB1900034 -#define SYS_ENDIAN 0xB1900038 -#define SYS_POWERCTRL 0xB190003C -#define SYS_WAKESRC 0xB190005C -#define SYS_SLPPWR 0xB1900078 -#define SYS_SLEEP 0xB190007C - -/* Clock Controller */ -#define SYS_FREQCTRL0 0xB1900020 -#define SYS_FC_FRDIV2_BIT 22 -#define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) -#define SYS_FC_FE2 (1<<21) -#define SYS_FC_FS2 (1<<20) -#define SYS_FC_FRDIV1_BIT 12 -#define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) -#define SYS_FC_FE1 (1<<11) -#define SYS_FC_FS1 (1<<10) -#define SYS_FC_FRDIV0_BIT 2 -#define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) -#define SYS_FC_FE0 (1<<1) -#define SYS_FC_FS0 (1<<0) -#define SYS_FREQCTRL1 0xB1900024 -#define SYS_FC_FRDIV5_BIT 22 -#define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) -#define SYS_FC_FE5 (1<<21) -#define SYS_FC_FS5 (1<<20) -#define SYS_FC_FRDIV4_BIT 12 -#define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) -#define SYS_FC_FE4 (1<<11) -#define SYS_FC_FS4 (1<<10) -#define SYS_FC_FRDIV3_BIT 2 -#define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) -#define SYS_FC_FE3 (1<<1) -#define SYS_FC_FS3 (1<<0) -#define SYS_CLKSRC 0xB1900028 -#define SYS_CS_ME1_BIT 27 -#define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT) -#define SYS_CS_DE1 (1<<26) -#define SYS_CS_CE1 (1<<25) -#define SYS_CS_ME0_BIT 22 -#define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT) -#define SYS_CS_DE0 (1<<21) -#define SYS_CS_CE0 (1<<20) -#define SYS_CS_MI2_BIT 17 -#define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT) -#define SYS_CS_DI2 (1<<16) -#define SYS_CS_CI2 (1<<15) -#define SYS_CS_MUH_BIT 12 -#define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT) -#define SYS_CS_DUH (1<<11) -#define SYS_CS_CUH (1<<10) -#define SYS_CS_MUD_BIT 7 -#define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT) -#define SYS_CS_DUD (1<<6) -#define SYS_CS_CUD (1<<5) -#define SYS_CS_MIR_BIT 2 -#define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT) -#define SYS_CS_DIR (1<<1) -#define SYS_CS_CIR (1<<0) - -#define SYS_CS_MUX_AUX 0x1 -#define SYS_CS_MUX_FQ0 0x2 -#define SYS_CS_MUX_FQ1 0x3 -#define SYS_CS_MUX_FQ2 0x4 -#define SYS_CS_MUX_FQ3 0x5 -#define SYS_CS_MUX_FQ4 0x6 -#define SYS_CS_MUX_FQ5 0x7 -#define SYS_CPUPLL 0xB1900060 -#define SYS_AUXPLL 0xB1900064 - -/* AC97 Controller */ -#define AC97C_CONFIG 0xB0000000 -#define AC97C_RECV_SLOTS_BIT 13 -#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) -#define AC97C_XMIT_SLOTS_BIT 3 -#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) -#define AC97C_SG (1<<2) -#define AC97C_SYNC (1<<1) -#define AC97C_RESET (1<<0) -#define AC97C_STATUS 0xB0000004 -#define AC97C_XU (1<<11) -#define AC97C_XO (1<<10) -#define AC97C_RU (1<<9) -#define AC97C_RO (1<<8) -#define AC97C_READY (1<<7) -#define AC97C_CP (1<<6) -#define AC97C_TR (1<<5) -#define AC97C_TE (1<<4) -#define AC97C_TF (1<<3) -#define AC97C_RR (1<<2) -#define AC97C_RE (1<<1) -#define AC97C_RF (1<<0) -#define AC97C_DATA 0xB0000008 -#define AC97C_CMD 0xB000000C -#define AC97C_WD_BIT 16 -#define AC97C_READ (1<<7) -#define AC97C_INDEX_MASK 0x7f -#define AC97C_CNTRL 0xB0000010 -#define AC97C_RS (1<<1) -#define AC97C_CE (1<<0) - -#define DB1000_BCSR_ADDR 0xAE000000 -#define DB1550_BCSR_ADDR 0xAF000000 - -#ifdef CONFIG_DBAU1550 -#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR -#else -#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR -#endif - -#ifdef CONFIG_SOC_AU1500 -/* Au1500 PCI Controller */ -#define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */ -#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) -#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) -#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) -#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) -#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) -#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) -#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) -#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) -#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) -#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) -#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) -#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) -#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) -#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) -#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) - -#define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */ - -/* All of our structures, like pci resource, have 32 bit members. - * Drivers are expected to do an ioremap on the PCI MEM resource, but it's - * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch - * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and - * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM - * addresses. For PCI IO, it's simpler because we get to do the ioremap - * ourselves and then adjust the device's resources. - */ -#define Au1500_EXT_CFG 0x600000000 -#define Au1500_EXT_CFG_TYPE1 0x680000000 -#define Au1500_PCI_IO_START 0x500000000 -#define Au1500_PCI_IO_END 0x5000FFFFF -#define Au1500_PCI_MEM_START 0x440000000 -#define Au1500_PCI_MEM_END 0x443FFFFFF - -#define PCI_IO_START (Au1500_PCI_IO_START + 0x300) -#define PCI_IO_END (Au1500_PCI_IO_END) -#define PCI_MEM_START (Au1500_PCI_MEM_START) -#define PCI_MEM_END (Au1500_PCI_MEM_END) -#define PCI_FIRST_DEVFN (0<<3) -#define PCI_LAST_DEVFN (19<<3) - -#endif - -#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000)) -/* no PCI bus controller */ -#define PCI_IO_START 0 -#define PCI_IO_END 0 -#define PCI_MEM_START 0 -#define PCI_MEM_END 0 -#define PCI_FIRST_DEVFN 0 -#define PCI_LAST_DEVFN 0 -#endif -#define AU1X_SOCK0_IO 0xF00000000 -#define AU1X_SOCK0_PHYS_ATTR 0xF40000000 -#define AU1X_SOCK0_PHYS_MEM 0xF80000000 - -/* pcmcia socket 1 needs external glue logic so the memory map - * differs from board to board. - */ - -/* Only for db board, not older pb */ -#define AU1X_SOCK1_IO 0xF04000000 -#define AU1X_SOCK1_PHYS_ATTR 0xF44000000 -#define AU1X_SOCK1_PHYS_MEM 0xF84000000 - -#endif diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 5968d5345e..521996599e 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -14,6 +14,7 @@ config SYS_SOC default "bcm6368" if SOC_BMIPS_BCM6368 default "bcm6362" if SOC_BMIPS_BCM6362 default "bcm63268" if SOC_BMIPS_BCM63268 + default "bcm6838" if SOC_BMIPS_BCM6838 choice prompt "Broadcom MIPS SoC select" @@ -118,11 +119,34 @@ config SOC_BMIPS_BCM63268 This supports BMIPS BCM63268 family including BCM63168, BCM63169, BCM63268 and BCM63269. +config SOC_BMIPS_BCM6838 + bool "BMIPS BCM6838 family" + select MIPS_L1_CACHE_SHIFT_4 + select MIPS_TUNE_4KC + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6838 family including BCM68380, BCM68381, + and BCM68385. + endchoice choice prompt "Board select" +config BOARD_BROADCOM_BCM968380GERG + bool "Broadcom bcm968380gerg" + depends on SOC_BMIPS_BCM6838 + select BMIPS_SUPPORTS_BOOT_RAM + help + Broadcom BCM968380GERG reference board with BCM68380 SoC with 512 MB + of RAM and 128 MB of flash (nand). + Between its different peripherals there's an integrated switch with 4 + ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and + a BCM43217 (PCIe). + config BOARD_COMTREND_AR5315U bool "Comtrend AR-5315u" depends on SOC_BMIPS_BCM6318 @@ -251,6 +275,7 @@ endchoice config BMIPS_SUPPORTS_BOOT_RAM bool +source "board/broadcom/bcm968380gerg/Kconfig" source "board/comtrend/ar5315u/Kconfig" source "board/comtrend/ar5387un/Kconfig" source "board/comtrend/ct5361/Kconfig" diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 137679abea..7035646195 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -14,7 +14,9 @@ i2c0 = "/i2c@0"; mmc0 = "/mmc0"; mmc1 = "/mmc1"; - pci0 = &pci; + pci0 = &pci0; + pci1 = &pci1; + pci2 = &pci2; remoteproc1 = &rproc_1; remoteproc2 = &rproc_2; rtc0 = &rtc_0; @@ -295,13 +297,48 @@ compatible = "sandbox,mmc"; }; - pci: pci-controller { + pci0: pci-controller0 { compatible = "sandbox,pci"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000 0x01000000 0 0x20000000 0x20000000 0 0x2000>; + pci@0,0 { + compatible = "pci-generic"; + reg = <0x0000 0 0 0 0>; + emul@0,0 { + compatible = "sandbox,swap-case"; + }; + }; + pci@1f,0 { + compatible = "pci-generic"; + reg = <0xf800 0 0 0 0>; + emul@1f,0 { + compatible = "sandbox,swap-case"; + }; + }; + }; + + pci1: pci-controller1 { + compatible = "sandbox,pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 + 0x01000000 0 0x40000000 0x40000000 0 0x2000>; + sandbox,dev-info = <0x08 0x00 0x1234 0x5678 + 0x0c 0x00 0x1234 0x5678>; + }; + + pci2: pci-controller2 { + compatible = "sandbox,pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000 + 0x01000000 0 0x60000000 0x60000000 0 0x2000>; + sandbox,dev-info = <0x08 0x00 0x1234 0x5678>; pci@1f,0 { compatible = "pci-generic"; reg = <0xf800 0 0 0 0>; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 08863bf3a9..c8ae52b248 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -16,6 +16,18 @@ #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL +#define PCI_CAP_ID_PM_OFFSET 0x50 +#define PCI_CAP_ID_EXP_OFFSET 0x60 +#define PCI_CAP_ID_MSIX_OFFSET 0x70 + +#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100 +#define PCI_EXT_CAP_ID_VC_OFFSET 0x200 +#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300 + +/* Useful for PCI_VDEVICE() macro */ +#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID +#define SWAP_CASE_DRV_DATA 0x55aa + #define SANDBOX_CLK_RATE 32768 /* System controller driver data */ diff --git a/board/broadcom/bcm968380gerg/Kconfig b/board/broadcom/bcm968380gerg/Kconfig new file mode 100644 index 0000000000..c33e25d1a1 --- /dev/null +++ b/board/broadcom/bcm968380gerg/Kconfig @@ -0,0 +1,12 @@ +if BOARD_BROADCOM_BCM968380GERG + +config SYS_BOARD + default "bcm968380gerg" + +config SYS_VENDOR + default "broadcom" + +config SYS_CONFIG_NAME + default "broadcom_bcm968380gerg" + +endif diff --git a/board/broadcom/bcm968380gerg/MAINTAINERS b/board/broadcom/bcm968380gerg/MAINTAINERS new file mode 100644 index 0000000000..52747cd9ea --- /dev/null +++ b/board/broadcom/bcm968380gerg/MAINTAINERS @@ -0,0 +1,6 @@ +BCM968380GERG BOARD +M: Philippe Reynes <philippe.reynes@softathome.com> +S: Maintained +F: board/broadcom/bcm968380gerg/ +F: include/configs/broadcom_bcm968380gerg.h +F: configs/bcm968380gerg_ram_defconfig diff --git a/board/broadcom/bcm968380gerg/Makefile b/board/broadcom/bcm968380gerg/Makefile new file mode 100644 index 0000000000..a525b7b9b3 --- /dev/null +++ b/board/broadcom/bcm968380gerg/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += bcm968380gerg.o diff --git a/board/broadcom/bcm968380gerg/bcm968380gerg.c b/board/broadcom/bcm968380gerg/bcm968380gerg.c new file mode 100644 index 0000000000..044b3554ba --- /dev/null +++ b/board/broadcom/bcm968380gerg/bcm968380gerg.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include <common.h> diff --git a/board/broadcom/bcm968380gerg/board.c b/board/broadcom/bcm968380gerg/board.c new file mode 100644 index 0000000000..044b3554ba --- /dev/null +++ b/board/broadcom/bcm968380gerg/board.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include <common.h> diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig deleted file mode 100644 index 448176d8ba..0000000000 --- a/board/dbau1x00/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -if TARGET_DBAU1X00 - -config SYS_BOARD - default "dbau1x00" - -config SYS_SOC - default "au1x00" - -config SYS_CONFIG_NAME - default "dbau1x00" - -config SYS_TEXT_BASE - default 0xbfc00000 - -config SYS_DCACHE_SIZE - default 16384 - -config SYS_DCACHE_LINE_SIZE - default 32 - -config SYS_ICACHE_SIZE - default 16384 - -config SYS_ICACHE_LINE_SIZE - default 32 - -menu "dbau1x00 board options" - -choice - prompt "Select au1x00 SoC type" - optional - -config DBAU1100 - bool "Select AU1100" - -config DBAU1500 - bool "Select AU1500" - -config DBAU1550 - bool "Select AU1550" - -endchoice - -endmenu - -endif diff --git a/board/dbau1x00/MAINTAINERS b/board/dbau1x00/MAINTAINERS deleted file mode 100644 index 21853ed2fe..0000000000 --- a/board/dbau1x00/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -DBAU1X00 BOARD -#M: - -S: Orphan (since 2016-06) -F: board/dbau1x00/ -F: include/configs/dbau1x00.h -F: configs/dbau1000_defconfig -F: configs/dbau1100_defconfig -F: configs/dbau1500_defconfig -F: configs/dbau1550_defconfig -F: configs/dbau1550_el_defconfig diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile deleted file mode 100644 index 0ea56ef59c..0000000000 --- a/board/dbau1x00/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = dbau1x00.o -obj-y += lowlevel_init.o diff --git a/board/dbau1x00/README b/board/dbau1x00/README deleted file mode 100644 index b1e9494118..0000000000 --- a/board/dbau1x00/README +++ /dev/null @@ -1,63 +0,0 @@ -By Thomas.Lange@corelatus.se 2004-Oct-05 ----------------------------------------- -DbAu1xx0 are development boards from AMD containing -an Alchemy AU1xx0 series cpu with mips32 core. -Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 - -Limitations & comments ----------------------- -Support was originally big endian only. -I have not tested, but several u-boot users report working -configurations in little endian mode. - -I named the board dbau1x00, to allow -support for all three development boards -( dbau1000, dbau1100 and dbau1500 ). -Now there is a new board called dbau1550 also, which -should be supported RSN. - -I only have a dbau1000, so my testing is limited -to this board. - -The board has two different flash banks, that can -be selected via dip switch. This makes it possible -to test new bootloaders without thrashing the YAMON -boot loader delivered with board. - -NOTE! When you switch between the two boot flashes, the -base addresses will be swapped. -Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has -to match the address where u-boot is located when you -actually launch. - -Ethernet only supported for mac0. - -PCMCIA only supported for slot 0, only 3.3V. - -PCMCIA IDE tested with Sandisk Compact Flash and -IBM microdrive. - -################################### -######## NOTE!!!!!! ######### -################################### -If you partition a disk on another system (e.g. laptop), -all bytes will be swapped on 16bit level when using -PCMCIA and running cpu in big endian mode!!!! - -This is probably due to an error in Au1000 chip. - -Solution: - -a) Boot via network and partition disk directly from -dbau1x00. The endian will then be correct. - -b) Partition disk on "laptop" and fill it with all files -you need. Then write a simple program that endian swaps -whole disk, - -Example: -Original "laptop" byte order: -B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... - -Dbau1000 byte order will then be: -B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c deleted file mode 100644 index 1e62753b30..0000000000 --- a/board/dbau1x00/dbau1x00.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Thomas.Lange@corelatus.se - */ - -#include <common.h> -#include <command.h> -#include <mach/au1x00.h> -#include <asm/mipsregs.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - gd->ram_size = MEM_SIZE * 1024 * 1024; - - return 0; -} - -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 - -/* In arch/mips/cpu/cpu.c */ -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); - -int checkboard (void) -{ -#ifdef CONFIG_IDE_PCMCIA - u16 status; - volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10); -#endif /* CONFIG_IDE_PCMCIA */ - volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC); - volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; - u32 proc_id; - - *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - - proc_id = read_c0_prid(); - - switch (proc_id >> 24) { - case 0: - puts ("Board: Merlot (DbAu1000)\n"); - printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 1: - puts ("Board: DbAu1500\n"); - printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 2: - puts ("Board: DbAu1100\n"); - printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 3: - puts ("Board: DbAu1550\n"); - printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - default: - printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); - } - - set_io_port_base(0); - -#ifdef CONFIG_IDE_PCMCIA - /* Enable 3.3 V on slot 0 ( VCC ) - No 5V */ - status = 4; - *pcmcia_bcsr = status; - - status |= BCSR_PCMCIA_PC0DRVEN; - *pcmcia_bcsr = status; - au_sync(); - - udelay(300*1000); - - status |= BCSR_PCMCIA_PC0RST; - *pcmcia_bcsr = status; - au_sync(); - - udelay(100*1000); - - /* PCMCIA is on a 36 bit physical address. - We need to map it into a 32 bit addresses */ - -#if 0 - /* We dont need theese unless we run whole pcmcia package */ - write_one_tlb(20, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ - 0x3C000017, /* Lo0 */ - 0x3C200017); /* Lo1 */ - - write_one_tlb(21, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ - 0x3D000017, /* Lo0 */ - 0x3D200017); /* Lo1 */ -#endif /* 0 */ - write_one_tlb(22, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ - 0x3E000017, /* Lo0 */ - 0x3E200017); /* Lo1 */ -#endif /* CONFIG_IDE_PCMCIA */ - - /* Release reset of ethernet PHY chips */ - /* Always do this, because linux does not know about it */ - *phy = 3; - - return 0; -} diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S deleted file mode 100644 index 409f8ee477..0000000000 --- a/board/dbau1x00/lowlevel_init.S +++ /dev/null @@ -1,589 +0,0 @@ -/* Memory sub-system initialization code */ - -#include <config.h> -#include <mach/au1x00.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> - -#define AU1500_SYS_ADDR 0xB1900000 -#define sys_endian 0x0038 -#define CP0_Config0 $16 -#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ -#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000) - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - /* - * Step 1) Establish CPU endian mode. - * Db1500-specific: - * Switch S1.1 Off(bit7 reads 1) is Little Endian - * Switch S1.1 On (bit7 reads 0) is Big Endian - */ -#ifdef CONFIG_DBAU1550 - li t0, MEM_STCFG2 - li t1, 0x00000040 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x10c03f00 - sw t1, 0(t0) -#else - li t0, MEM_STCFG1 - li t1, 0x00000080 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x10c03f00 - sw t1, 0(t0) -#endif - - li t0, DB1XX0_BCSR_ADDR - lw t1,8(t0) - andi t1,t1,0x80 - beq zero,t1,big_endian - nop -little_endian: - - /* Change Au1 core to little endian */ - li t0, AU1500_SYS_ADDR - li t1, 1 - sw t1, sys_endian(t0) - mfc0 t2, CP0_CONFIG - mtc0 t2, CP0_CONFIG - nop - nop - - /* Big Endian is default so nothing to do but fall through */ - -big_endian: - - /* - * Step 2) Establish Status Register - * (set BEV, clear ERL, clear EXL, clear IE) - */ - li t1, 0x00400000 - mtc0 t1, CP0_STATUS - - /* - * Step 3) Establish CP0 Config0 - * (set OD, set K0=3) - */ - li t1, 0x00080003 - mtc0 t1, CP0_CONFIG - - /* - * Step 4) Disable Watchpoint facilities - */ - li t1, 0x00000000 - mtc0 t1, CP0_WATCHLO - mtc0 t1, CP0_IWATCHLO - /* - * Step 5) Disable the performance counters - */ - mtc0 zero, CP0_PERFORMANCE - nop - - /* - * Step 6) Establish EJTAG Debug register - */ - mtc0 zero, CP0_DEBUG - nop - - /* - * Step 7) Establish Cause - * (set IV bit) - */ - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* Establish Wired (and Random) */ - mtc0 zero, CP0_WIRED - nop - -#ifdef CONFIG_DBAU1550 - /* No workaround if running from ram */ - lui t0, 0xffc0 - lui t3, 0xbfc0 - and t1, ra, t0 - bne t1, t3, noCacheJump - nop - - /*** From AMD YAMON ***/ - /* - * Step 8) Initialize the caches - */ - li t0, (16*1024) - li t1, 32 - li t2, 0x80000000 - addu t3, t0, t2 -cacheloop: - cache 0, 0(t2) - cache 1, 0(t2) - addu t2, t1 - bne t2, t3, cacheloop - nop - - /* Save return address */ - move t3, ra - - /* Run from cacheable space now */ - bal cachehere - nop -cachehere: - li t1, ~0x20000000 /* convert to KSEG0 */ - and t0, ra, t1 - addi t0, 5*4 /* 5 insns beyond cachehere */ - jr t0 - nop - - /* Restore return address */ - move ra, t3 - - /* - * Step 9) Initialize the TLB - */ - li t0, 0 # index value - li t1, 0x00000000 # entryhi value - li t2, 32 # 32 entries - -tlbloop: - /* Probe TLB for matching EntryHi */ - mtc0 t1, CP0_ENTRYHI - tlbp - nop - - /* Examine Index[P], 1=no matching entry */ - mfc0 t3, CP0_INDEX - li t4, 0x80000000 - and t3, t4, t3 - addiu t1, t1, 1 # increment t1 (asid) - beq zero, t3, tlbloop - nop - - /* Initialize the TLB entry */ - mtc0 t0, CP0_INDEX - mtc0 zero, CP0_ENTRYLO0 - mtc0 zero, CP0_ENTRYLO1 - mtc0 zero, CP0_PAGEMASK - tlbwi - - /* Do it again */ - addiu t0, t0, 1 - bne t0, t2, tlbloop - nop - -#endif /* CONFIG_DBAU1550 */ - - /* First setup pll:s to make serial work ok */ - /* We have a 12 MHz crystal */ - li t0, SYS_CPUPLL - li t1, CPU_SCALE /* CPU clock */ - sw t1, 0(t0) - sync - nop - nop - - /* wait 1mS for clocks to settle */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - /* Setup AUX PLL */ - li t0, SYS_AUXPLL - li t1, 0x20 /* 96 MHz */ - sw t1, 0(t0) /* aux pll */ - sync - -#ifdef CONFIG_DBAU1550 - /* Static memory controller */ - /* RCE0 - can not change while fetching, do so from icache */ - move t2, ra /* Store return address */ - bal getAddr - nop - -getAddr: - move t1, ra - move ra, t2 /* Move return addess back */ - - cache 0x14,0(t1) - cache 0x14,32(t1) - /*** /From YAMON ***/ - -noCacheJump: -#endif /* CONFIG_DBAU1550 */ - -#ifdef CONFIG_DBAU1550 - li t0, MEM_STTIME0 - li t1, 0x040181D7 - sw t1, 0(t0) - - /* RCE0 AMD MirrorBit Flash (?) */ - li t0, MEM_STCFG0 - li t1, 0x00000003 - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11803E00 - sw t1, 0(t0) -#else /* CONFIG_DBAU1550 */ - li t0, MEM_STTIME0 - li t1, 0x040181D7 - sw t1, 0(t0) - - /* RCE0 AMD 29LV640M MirrorBit Flash */ - li t0, MEM_STCFG0 - li t1, 0x00000013 - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11E03F80 - sw t1, 0(t0) -#endif /* CONFIG_DBAU1550 */ - - /* RCE1 CPLD Board Logic */ - li t0, MEM_STCFG1 - li t1, 0x00000080 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x10c03f00 - sw t1, 0(t0) - -#ifdef CONFIG_DBAU1550 - /* RCE2 CPLD Board Logic */ - li t0, MEM_STCFG2 - li t1, 0x00000040 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x22080a20 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x10c03f00 - sw t1, 0(t0) -#else - li t0, MEM_STCFG2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x00000000 - sw t1, 0(t0) -#endif - - /* RCE3 PCMCIA 250ns */ - li t0, MEM_STCFG3 - li t1, 0x00000002 - sw t1, 0(t0) - - li t0, MEM_STTIME3 - li t1, 0x280E3E07 - sw t1, 0(t0) - - li t0, MEM_STADDR3 - li t1, 0x10000000 - sw t1, 0(t0) - - sync - - /* Set peripherals to a known state */ - li t0, IC0_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC0_CFG0CLR - sw t1, 0(t0) - - li t0, IC0_CFG1CLR - sw t1, 0(t0) - - li t0, IC0_CFG2CLR - sw t1, 0(t0) - - li t0, IC0_SRCSET - sw t1, 0(t0) - - li t0, IC0_ASSIGNSET - sw t1, 0(t0) - - li t0, IC0_WAKECLR - sw t1, 0(t0) - - li t0, IC0_RISINGCLR - sw t1, 0(t0) - - li t0, IC0_FALLINGCLR - sw t1, 0(t0) - - li t0, IC0_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, IC1_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC1_CFG0CLR - sw t1, 0(t0) - - li t0, IC1_CFG1CLR - sw t1, 0(t0) - - li t0, IC1_CFG2CLR - sw t1, 0(t0) - - li t0, IC1_SRCSET - sw t1, 0(t0) - - li t0, IC1_ASSIGNSET - sw t1, 0(t0) - - li t0, IC1_WAKECLR - sw t1, 0(t0) - - li t0, IC1_RISINGCLR - sw t1, 0(t0) - - li t0, IC1_FALLINGCLR - sw t1, 0(t0) - - li t0, IC1_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, SYS_FREQCTRL0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_FREQCTRL1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_CLKSRC - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_PININPUTEN - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, 0xB1100100 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, 0xB1400100 - li t1, 0x00000000 - sw t1, 0(t0) - - - li t0, SYS_WAKEMSK - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_WAKESRC - li t1, 0x00000000 - sw t1, 0(t0) - - /* wait 1mS before setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - -#ifdef CONFIG_DBAU1550 -/* SDCS 0,1,2 DDR SDRAM */ - li t0, MEM_SDMODE0 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x04276221 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0xe21003f0 - sw t1, 0(t0) - - li t0, MEM_SDADDR1 - li t1, 0xe21043f0 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0xe21083f0 - sw t1, 0(t0) - - sync - - li t0, MEM_SDCONFIGA - li t1, 0x9030060a /* Program refresh - disabled */ - sw t1, 0(t0) - sync - - li t0, MEM_SDCONFIGB - li t1, 0x00028000 - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD /* Precharge all */ - li t1, 0 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x40000000 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x00000063 - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD /* Precharge all */ - sw zero, 0(t0) - sync - - /* Issue 2 autoref */ - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - - /* Enable refresh */ - li t0, MEM_SDCONFIGA - li t1, 0x9830060a /* Program refresh - enabled */ - sw t1, 0(t0) - sync - -#else /* CONFIG_DBAU1550 */ -/* SDCS 0,1 SDRAM */ - li t0, MEM_SDMODE0 - li t1, 0x005522AA - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x005522AA - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0x001003F8 - sw t1, 0(t0) - - - li t0, MEM_SDADDR1 - li t1, 0x001023F8 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0x00000000 - sw t1, 0(t0) - - sync - - li t0, MEM_SDREFCFG - li t1, 0x64000C24 /* Disable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - sw zero, 0(t0) - sync - - li t0, MEM_SDREFCFG - li t1, 0x66000C24 /* Enable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000033 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000033 - sw t1, 0(t0) - sync - -#endif /* CONFIG_DBAU1550 */ - /* wait 1mS after setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - li t0, SYS_PINFUNC - li t1, 0x00008080 - sw t1, 0(t0) - - li t0, SYS_TRIOUTCLR - li t1, 0x00001FFF - sw t1, 0(t0) - - li t0, SYS_OUTPUTCLR - li t1, 0x00008000 - sw t1, 0(t0) - sync - - jr ra - nop diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig deleted file mode 100644 index ef8905d46a..0000000000 --- a/board/pb1x00/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -if TARGET_PB1X00 - -config SYS_BOARD - default "pb1x00" - -config SYS_SOC - default "au1x00" - -config SYS_CONFIG_NAME - default "pb1x00" - -config SYS_TEXT_BASE - default 0x83800000 - -config SYS_DCACHE_SIZE - default 16384 - -config SYS_DCACHE_LINE_SIZE - default 32 - -config SYS_ICACHE_SIZE - default 16384 - -config SYS_ICACHE_LINE_SIZE - default 32 - -endif diff --git a/board/pb1x00/MAINTAINERS b/board/pb1x00/MAINTAINERS deleted file mode 100644 index 8326cc78cc..0000000000 --- a/board/pb1x00/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PB1X00 BOARD -#M: - -S: Maintained -F: board/pb1x00/ -F: include/configs/pb1x00.h -F: configs/pb1000_defconfig diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile deleted file mode 100644 index 5ef9b7f43b..0000000000 --- a/board/pb1x00/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = pb1x00.o flash.o -obj-y += lowlevel_init.o diff --git a/board/pb1x00/README b/board/pb1x00/README deleted file mode 100644 index b1e9494118..0000000000 --- a/board/pb1x00/README +++ /dev/null @@ -1,63 +0,0 @@ -By Thomas.Lange@corelatus.se 2004-Oct-05 ----------------------------------------- -DbAu1xx0 are development boards from AMD containing -an Alchemy AU1xx0 series cpu with mips32 core. -Existing cpu:s are Au1000, Au1100, Au1500 and Au1550 - -Limitations & comments ----------------------- -Support was originally big endian only. -I have not tested, but several u-boot users report working -configurations in little endian mode. - -I named the board dbau1x00, to allow -support for all three development boards -( dbau1000, dbau1100 and dbau1500 ). -Now there is a new board called dbau1550 also, which -should be supported RSN. - -I only have a dbau1000, so my testing is limited -to this board. - -The board has two different flash banks, that can -be selected via dip switch. This makes it possible -to test new bootloaders without thrashing the YAMON -boot loader delivered with board. - -NOTE! When you switch between the two boot flashes, the -base addresses will be swapped. -Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has -to match the address where u-boot is located when you -actually launch. - -Ethernet only supported for mac0. - -PCMCIA only supported for slot 0, only 3.3V. - -PCMCIA IDE tested with Sandisk Compact Flash and -IBM microdrive. - -################################### -######## NOTE!!!!!! ######### -################################### -If you partition a disk on another system (e.g. laptop), -all bytes will be swapped on 16bit level when using -PCMCIA and running cpu in big endian mode!!!! - -This is probably due to an error in Au1000 chip. - -Solution: - -a) Boot via network and partition disk directly from -dbau1x00. The endian will then be correct. - -b) Partition disk on "laptop" and fill it with all files -you need. Then write a simple program that endian swaps -whole disk, - -Example: -Original "laptop" byte order: -B0 B1 B2 B3 B4 B5 B6 B7 B8 B9... - -Dbau1000 byte order will then be: -B1 B0 B3 B2 B5 B4 B7 B6 B9 B8... diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c deleted file mode 100644 index c7daf5a0ef..0000000000 --- a/board/pb1x00/flash.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - printf ("Skipping flash_init\n"); - return (0); -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - printf ("write_buff not implemented\n"); - return (-1); -} diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S deleted file mode 100644 index 98d9536a7d..0000000000 --- a/board/pb1x00/lowlevel_init.S +++ /dev/null @@ -1,391 +0,0 @@ -/* Memory sub-system initialization code */ - -#include <config.h> -#include <mach/au1x00.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> - -#define AU1500_SYS_ADDR 0xB1900000 -#define sys_endian 0x0038 -#define CP0_Config0 $16 -#define MEM_1MS ((396000000/1000000) * 1000) - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - /* - * Step 1) Establish CPU endian mode. - * NOTE: A fair amount of code is necessary on the Pb1000 to - * obtain the value of Switch S8.1 which is used to determine - * endian at run-time. - */ - - /* RCE1 */ - li t0, MEM_STCFG1 - li t1, 0x00000083 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x33030A10 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x11803E40 - sw t1, 0(t0) - - /* Set DSTRB bits so switch will read correctly */ - li t1, 0xBE00000C - lw t2, 0(t1) - or t2, t2, 0x00000300 - sw t2, 0(t1) - - /* Check switch setting */ - li t1, 0xBE000014 - lw t2, 0(t1) - and t2, t2, 0x00000100 - bne t2, zero, big_endian - nop - -little_endian: - - /* Change Au1 core to little endian */ - li t0, AU1500_SYS_ADDR - li t1, 1 - sw t1, sys_endian(t0) - mfc0 t2, CP0_CONFIG - mtc0 t2, CP0_CONFIG - nop - nop - - /* Big Endian is default so nothing to do but fall through */ - -big_endian: - - /* - * Step 2) Establish Status Register - * (set BEV, clear ERL, clear EXL, clear IE) - */ - li t1, 0x00400000 - mtc0 t1, CP0_STATUS - - /* - * Step 3) Establish CP0 Config0 - * (set OD, set K0=3) - */ - li t1, 0x00080003 - mtc0 t1, CP0_CONFIG - - /* - * Step 4) Disable Watchpoint facilities - */ - li t1, 0x00000000 - mtc0 t1, CP0_WATCHLO - mtc0 t1, CP0_IWATCHLO - /* - * Step 5) Disable the performance counters - */ - mtc0 zero, CP0_PERFORMANCE - nop - - /* - * Step 6) Establish EJTAG Debug register - */ - mtc0 zero, CP0_DEBUG - nop - - /* - * Step 7) Establish Cause - * (set IV bit) - */ - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* Establish Wired (and Random) */ - mtc0 zero, CP0_WIRED - nop - - /* First setup pll:s to make serial work ok */ - /* We have a 12 MHz crystal */ - li t0, SYS_CPUPLL - li t1, 0x21 /* 396 MHz */ - sw t1, 0(t0) - sync - nop - nop - - /* wait 1mS for clocks to settle */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - /* Setup AUX PLL */ - li t0, SYS_AUXPLL - li t1, 8 /* 96 MHz */ - sw t1, 0(t0) /* aux pll */ - sync - - /* Static memory controller */ - - /* RCE0 8MB AMD29D323 Flash */ - li t0, MEM_STCFG0 - li t1, 0x00001403 - sw t1, 0(t0) - - li t0, MEM_STTIME0 - li t1, 0xFFFFFFDD - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11F83FE0 - sw t1, 0(t0) - - /* RCE1 CPLD Board Logic */ - li t0, MEM_STCFG1 - li t1, 0x00000083 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x33030A10 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x11803E40 - sw t1, 0(t0) - - /* RCE2 CPLD Board Logic */ - li t0, MEM_STCFG2 - li t1, 0x00000004 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x08061908 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x12A03FC0 - sw t1, 0(t0) - - /* RCE3 PCMCIA 250ns */ - li t0, MEM_STCFG3 - li t1, 0x00000002 - sw t1, 0(t0) - - li t0, MEM_STTIME3 - li t1, 0x280E3E07 - sw t1, 0(t0) - - li t0, MEM_STADDR3 - li t1, 0x10000000 - sw t1, 0(t0) - - sync - - /* Set peripherals to a known state */ - li t0, IC0_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC0_CFG0CLR - sw t1, 0(t0) - - li t0, IC0_CFG1CLR - sw t1, 0(t0) - - li t0, IC0_CFG2CLR - sw t1, 0(t0) - - li t0, IC0_SRCSET - sw t1, 0(t0) - - li t0, IC0_ASSIGNSET - sw t1, 0(t0) - - li t0, IC0_WAKECLR - sw t1, 0(t0) - - li t0, IC0_RISINGCLR - sw t1, 0(t0) - - li t0, IC0_FALLINGCLR - sw t1, 0(t0) - - li t0, IC0_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, IC1_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC1_CFG0CLR - sw t1, 0(t0) - - li t0, IC1_CFG1CLR - sw t1, 0(t0) - - li t0, IC1_CFG2CLR - sw t1, 0(t0) - - li t0, IC1_SRCSET - sw t1, 0(t0) - - li t0, IC1_ASSIGNSET - sw t1, 0(t0) - - li t0, IC1_WAKECLR - sw t1, 0(t0) - - li t0, IC1_RISINGCLR - sw t1, 0(t0) - - li t0, IC1_FALLINGCLR - sw t1, 0(t0) - - li t0, IC1_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, SYS_FREQCTRL0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_FREQCTRL1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_CLKSRC - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_PININPUTEN - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, 0xB1100100 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, 0xB1400100 - li t1, 0x00000000 - sw t1, 0(t0) - - - li t0, SYS_WAKEMSK - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_WAKESRC - li t1, 0x00000000 - sw t1, 0(t0) - - /* wait 1mS before setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - /* - * Skip memory setup if we are running from memory - */ - li t0, 0x90000000 - sub t0, ra, t0 - bltz t0, skip_memsetup - nop - - /* - * SDCS0 - Not used, for SMROM - * SDCS1 - 32MB Micron 48LCBM16A2 - * SDCS2 - 32MB Micron 48LCBM16A2 - */ - li t0, MEM_SDMODE0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x00552229 - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x00552229 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDADDR1 - li t1, 0x001003F8 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0x001023F8 - sw t1, 0(t0) - - sync - - li t0, MEM_SDREFCFG - li t1, 0x74000c30 /* Disable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - sw zero, 0(t0) - sync - - li t0, MEM_SDREFCFG - li t1, 0x76000c30 /* Enable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - /* wait 1mS after setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - -skip_memsetup: - - li t0, SYS_PINFUNC - li t1, 0/*0x00008080*/ - sw t1, 0(t0) - - /* - li t0, SYS_TRIOUTCLR - li t1, 0x00001FFF - sw t1, 0(t0) - - li t0, SYS_OUTPUTCLR - li t1, 0x00008000 - sw t1, 0(t0) - */ - sync - - jr ra - nop diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c deleted file mode 100644 index f3e6110077..0000000000 --- a/board/pb1x00/pb1x00.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Thomas.Lange@corelatus.se - */ - -#include <common.h> -#include <command.h> -#include <mach/au1x00.h> -#include <asm/mipsregs.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* Sdram is setup by assembler code */ - /* If memory could be changed, we should return the true value here */ - gd->ram_size = 64 * 1024 * 1024; - - return 0; -} - -#define BCSR_PCMCIA_PC0DRVEN 0x0010 -#define BCSR_PCMCIA_PC0RST 0x0080 - -/* In arch/mips/cpu/cpu.c */ -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); - -int checkboard (void) -{ -#if defined(CONFIG_IDE_PCMCIA) && 0 - u16 status; -#endif - /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */ - volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; - u32 proc_id; - - *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - - proc_id = read_c0_prid(); - - switch (proc_id >> 24) { - case 0: - puts ("Board: Pb1000\n"); - printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 1: - puts ("Board: Pb1500\n"); - printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - case 2: - puts ("Board: Pb1100\n"); - printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", - (proc_id >> 8) & 0xFF, proc_id & 0xFF); - break; - default: - printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); - } - - set_io_port_base(0); - -#if defined(CONFIG_IDE_PCMCIA) && 0 - /* Enable 3.3 V on slot 0 ( VCC ) - No 5V */ - status = 4; - *pcmcia_bcsr = status; - - status |= BCSR_PCMCIA_PC0DRVEN; - *pcmcia_bcsr = status; - au_sync(); - - udelay(300*1000); - - status |= BCSR_PCMCIA_PC0RST; - *pcmcia_bcsr = status; - au_sync(); - - udelay(100*1000); - - /* PCMCIA is on a 36 bit physical address. - We need to map it into a 32 bit addresses */ - -#if 0 - /* We dont need theese unless we run whole pcmcia package */ - write_one_tlb(20, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ - 0x3C000017, /* Lo0 */ - 0x3C200017); /* Lo1 */ - - write_one_tlb(21, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ - 0x3D000017, /* Lo0 */ - 0x3D200017); /* Lo1 */ -#endif /* 0 */ - write_one_tlb(22, /* index */ - 0x01ffe000, /* Pagemask, 16 MB pages */ - CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ - 0x3E000017, /* Lo0 */ - 0x3E200017); /* Lo1 */ -#endif /* CONFIG_IDE_PCMCIA */ - - return 0; -} diff --git a/board/samsung/common/bootscripts/autoboot.cmd b/board/samsung/common/bootscripts/autoboot.cmd index 1faed8ba0c..11c724c4e0 100644 --- a/board/samsung/common/bootscripts/autoboot.cmd +++ b/board/samsung/common/bootscripts/autoboot.cmd @@ -74,15 +74,15 @@ setenv boot_img " #### Routine: autoboot - choose proper boot path setenv autoboot " -if test -e mmc 0:${mmcbootpart} Image.itb; then +if test -e mmc ${mmcbootdev}:${mmcbootpart} Image.itb; then echo Found kernel image: Image.itb; run setboot_fit; run boot_img; -elif test -e mmc 0:${mmcbootpart} zImage; then +elif test -e mmc ${mmcbootdev}:${mmcbootpart} zImage; then echo Found kernel image: zImage; run setboot_zimg; run boot_img; -elif test -e mmc 0:${mmcbootpart} uImage; then +elif test -e mmc ${mmcbootdev}:${mmcbootpart} uImage; then echo Found kernel image: uImage; run setboot_uimg; run boot_img; diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index 590a1140b0..31c00360f2 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -11,6 +11,7 @@ F: configs/peach-pi_defconfig ODROID-XU3 BOARD M: Jaehoon Chung <jh80.chung@samsung.com> +M: Lukasz Majewski <lukma@denx.de> S: Maintained F: board/samsung/smdk5420/ F: include/configs/odroid_xu3.h diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index edcbb16cf6..6bc33fc94f 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 CONFIG_DRAM_ZQ=3881979 CONFIG_DRAM_ODT_EN=y +CONFIG_MACPWR="PA17" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" @@ -13,11 +14,9 @@ CONFIG_AHCI=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_SCSI_AHCI=y +CONFIG_RGMII=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO4_VOLT=2500 -CONFIG_AXP_ALDO2_VOLT=2500 CONFIG_AXP_ELDO3_VOLT=1200 CONFIG_SCSI=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -CONFIG_SUN8I_EMAC=y -CONFIG_RGMII=y -CONFIG_MACPWR="PA17" diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 89921a5c0d..05a1c18eae 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -39,6 +39,5 @@ CONFIG_MV88E61XX_SWITCH=y CONFIG_MV88E61XX_CPU_PORT=10 CONFIG_MV88E61XX_PHY_PORTS=0x003 CONFIG_MV88E61XX_FIXED_PORTS=0x300 -CONFIG_MV88E61XX_RGMII_DELAY=y CONFIG_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 38d21c890b..33a3e6847d 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -38,9 +38,9 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD_PARTITIONS=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_MTD_PARTITIONS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index ac07bcb9e5..cab5f7d143 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -38,8 +38,8 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y -CONFIG_NAND_ATMEL=y CONFIG_MTD_PARTITIONS=y +CONFIG_NAND_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 5e04424c97..61308e6bb2 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -38,9 +38,9 @@ CONFIG_DM_GPIO=y CONFIG_AT91_GPIO=y CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD_PARTITIONS=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_MTD_PARTITIONS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 46dea17563..8b4247882f 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -1,27 +1,20 @@ CONFIG_ARM=y CONFIG_ARCH_BCMSTB=y +CONFIG_SYS_TEXT_BASE=0x80100000 CONFIG_TARGET_BCM7445=y -CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_OF_CONTROL=y -CONFIG_OF_PRIOR_STAGE=y -CONFIG_DM=y -CONFIG_DM_SPI=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI=y -CONFIG_SPI_FLASH=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_BCMSTB_SPI=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -CONFIG_RSA=y -CONFIG_BLK=n -CONFIG_SDHCI=y +CONFIG_BOOTDELAY=1 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot>" +CONFIG_OF_PRIOR_STAGE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCMSTB=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y CONFIG_CONS_INDEX=3 -CONFIG_BOOTDELAY=1 -CONFIG_SYS_PROMPT="U-Boot>" -CONFIG_HUSH_PARSER=y -CONFIG_SYS_TEXT_BASE=0x80100000 -CONFIG_SYS_NS16550_COM3=0xf040ab00 -CONFIG_EFI_LOADER=n +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_BCMSTB_SPI=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig new file mode 100644 index 0000000000..3354a5e034 --- /dev/null +++ b/configs/bcm968380gerg_ram_defconfig @@ -0,0 +1,48 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ARCH_BMIPS=y +CONFIG_SOC_BMIPS_BCM6838=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="bcm968380gerg # " +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y +# CONFIG_NET is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_DM_GPIO=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY=y +CONFIG_BCM6368_USBH_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_DM_RESET=y +CONFIG_RESET_BCM6345=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y +CONFIG_LZO=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 3a83ecf1ac..8931cbd73a 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -8,7 +8,6 @@ CONFIG_AM33XX=y CONFIG_TARGET_BRPPT1=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-mmc" CONFIG_TPL_SYS_MALLOC_F_LEN=0x0 @@ -28,6 +27,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 3651bab31a..13104f05ef 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -80,8 +80,8 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y -CONFIG_DM_SPI_FLASH=y CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index a2bd7e80e2..81e4fbcd0d 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -1,17 +1,17 @@ CONFIG_ARM=y +CONFIG_ARM_SMCCC=y CONFIG_ARCH_OWL=y -CONFIG_TARGET_BUBBLEGUM_96=y CONFIG_SYS_TEXT_BASE=0x11000000 +CONFIG_TARGET_BUBBLEGUM_96=y CONFIG_IDENT_STRING="\nBubblegum-96" CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y -CONFIG_ARM_SMCCC=y CONFIG_BOOTARGS="console=ttyOWL5,115200n8" -CONFIG_BOOTDELAY=5 -CONFIG_SYS_PROMPT="U-Boot => " # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="U-Boot => " CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_CACHE=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index b5b52c798b..83564dbe89 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -40,9 +40,9 @@ CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set +CONFIG_MTD_PARTITIONS=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_MTD_PARTITIONS=y CONFIG_PHYLIB=y CONFIG_ATMEL_USART=y CONFIG_USB=y diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig deleted file mode 100644 index 4161262bc9..0000000000 --- a/configs/dbau1000_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_SYS_EXTRA_OPTIONS="DBAU1000" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_MAC_PARTITION=y -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig deleted file mode 100644 index 96305e40f8..0000000000 --- a/configs/dbau1100_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1100=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_MAC_PARTITION=y -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig deleted file mode 100644 index eb83a3dbbb..0000000000 --- a/configs/dbau1500_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1500=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_MAC_PARTITION=y -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig deleted file mode 100644 index 619874a98f..0000000000 --- a/configs/dbau1550_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1550=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig deleted file mode 100644 index b1e448073b..0000000000 --- a/configs/dbau1550_el_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -CONFIG_MIPS=y -CONFIG_SYS_TEXT_BASE=0xBFC00000 -CONFIG_TARGET_DBAU1X00=y -CONFIG_DBAU1550=y -CONFIG_SYS_LITTLE_ENDIAN=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="DbAu1xx0 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NFS is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index f1eddaff5d..def682c76b 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -11,7 +11,6 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 -CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4" CONFIG_DEBUG_UART=y CONFIG_AHCI=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index ebab2956fc..7d921cde05 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -55,7 +55,6 @@ CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_FSL_ESDHC=y -CONFIG_MTD_PARTITIONS=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 0309c5f5ff..911618c17a 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -38,7 +38,6 @@ CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_NAND_DAVINCI=y -CONFIG_MTD_DEVICE=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index c99e92a3b4..174af79960 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -31,7 +31,6 @@ CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_NAND_DAVINCI=y -CONFIG_MTD_DEVICE=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 1bcbed46d5..49384d68eb 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -20,10 +20,9 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y -CONFIG_ADC=y -CONFIG_SARADC_MESON=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y CONFIG_DM_GPIO=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y @@ -36,7 +35,6 @@ CONFIG_PHY=y CONFIG_MESON_GXL_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXL=y -CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_MESON=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 3b0b42f37e..5128d1c4a5 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -29,7 +30,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -CONFIG_BLK=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -37,6 +38,7 @@ CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -45,7 +47,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -CONFIG_DM_SCSI=y -CONFIG_SATA_CEVA=y -CONFIG_SCSI=y -CONFIG_AHCI=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 09c301b201..fdd131bcbe 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -34,7 +35,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y -CONFIG_BLK=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -48,6 +49,7 @@ CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -57,8 +59,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -CONFIG_DM_SCSI=y -CONFIG_SATA_CEVA=y -CONFIG_SCSI_AHCI=y -CONFIG_SCSI=y -CONFIG_AHCI=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index c444127f17..fcfaa501bf 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -5,6 +5,7 @@ CONFIG_SECURE_BOOT=y CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -31,7 +32,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -CONFIG_BLK=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -43,6 +44,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -54,8 +56,3 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_DM_SCSI=y -CONFIG_SATA_CEVA=y -CONFIG_SCSI_AHCI=y -CONFIG_SCSI=y -CONFIG_AHCI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index ee9f606ed9..b803f54140 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_FSL_LS_PPA=y CONFIG_QSPI_AHB_INIT=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y @@ -30,7 +31,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y -CONFIG_BLK=y +CONFIG_SATA_CEVA=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y @@ -43,6 +44,7 @@ CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -52,8 +54,3 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y -CONFIG_DM_SCSI=y -CONFIG_SATA_CEVA=y -CONFIG_SCSI_AHCI=y -CONFIG_SCSI=y -CONFIG_AHCI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 5c1ab6eeb1..7fbce1cf3b 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -20,12 +20,12 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110 +CONFIG_SPL_CRYPTO_SUPPORT=y +CONFIG_SPL_HASH_SUPPORT=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_CRYPTO_SUPPORT=y -CONFIG_SPL_HASH_SUPPORT=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 9a9c33a173..cc88c887d5 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -26,10 +26,10 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_PHYLIB=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y CONFIG_NETDEVICES=y CONFIG_PHY_GIGE=y CONFIG_E1000=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 1384768ddf..b2ca618af8 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -30,10 +30,10 @@ CONFIG_DM=y CONFIG_FSL_CAAM=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y -CONFIG_PHYLIB=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y CONFIG_NETDEVICES=y CONFIG_PHY_GIGE=y CONFIG_E1000=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 148aff85d6..8870da5583 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -6,7 +6,6 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" # CONFIG_CONSOLE_MUX is not set diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index 8a0dbf02e7..c1d14cbcdd 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -24,15 +24,15 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_RESET=y CONFIG_DM_MMC=y CONFIG_MMC_MESON_GX=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXBB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y CONFIG_DEBUG_UART_MESON=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 5943c19cf9..632542d984 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -29,9 +29,8 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ADC=y CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y +CONFIG_DM_MMC=y CONFIG_MMC_DW=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_S5P=y CONFIG_NETDEVICES=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x5000000 diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 48bc6e54ee..3d456eb16e 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -1,14 +1,12 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-one-plus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y # CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig deleted file mode 100644 index 68f714cba9..0000000000 --- a/configs/pb1000_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -CONFIG_MIPS=y -CONFIG_TARGET_PB1X00=y -CONFIG_SYS_EXTRA_OPTIONS="PB1000" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="Pb1x00 # " -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_RUN is not set -CONFIG_CMD_IMLS=y -# CONFIG_CMD_SAVEENV is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_ISO_PARTITION is not set -CONFIG_MTD_NOR_FLASH=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index 67d3ddd4ea..0a03854e70 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -40,7 +40,6 @@ CONFIG_CMD_UBI=y CONFIG_DM=y CONFIG_FSL_ESDHC=y CONFIG_MTD=y -CONFIG_MTD_DEVICE=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_SPI_FLASH=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index e9596c0284..878770a2c4 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PF6" @@ -7,9 +8,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_SPL=y # CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set # CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 1fa85a819c..5bd5927b41 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -68,7 +68,6 @@ CONFIG_CMD_CBFS=y CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_LOG=y CONFIG_MAC_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_OF_CONTROL=y @@ -165,6 +164,8 @@ CONFIG_DM_RESET=y CONFIG_SANDBOX_RESET=y CONFIG_DM_RTC=y CONFIG_SANDBOX_SERIAL=y +CONFIG_SMEM=y +CONFIG_SANDBOX_SMEM=y CONFIG_SOUND=y CONFIG_SOUND_SANDBOX=y CONFIG_SANDBOX_SPI=y @@ -174,7 +175,6 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_TIMER_EARLY=y CONFIG_SANDBOX_TIMER=y -CONFIG_TPM_TIS_SANDBOX=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y @@ -199,5 +199,3 @@ CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y CONFIG_UT_OVERLAY=y -CONFIG_SMEM=y -CONFIG_SANDBOX_SMEM=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 6130290919..afc34298ed 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -68,7 +68,6 @@ CONFIG_CMD_CBFS=y CONFIG_CMD_CRAMFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_LOG=y CONFIG_MAC_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_OF_CONTROL=y @@ -166,6 +165,8 @@ CONFIG_DM_RESET=y CONFIG_SANDBOX_RESET=y CONFIG_DM_RTC=y CONFIG_SANDBOX_SERIAL=y +CONFIG_SMEM=y +CONFIG_SANDBOX_SMEM=y CONFIG_SOUND=y CONFIG_SOUND_SANDBOX=y CONFIG_SANDBOX_SPI=y @@ -175,8 +176,6 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_TIMER_EARLY=y CONFIG_SANDBOX_TIMER=y -CONFIG_TPM_TIS_SANDBOX=y -CONFIG_TPM2_TIS_SANDBOX=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y @@ -193,8 +192,6 @@ CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y -CONFIG_TPM_V1=y -CONFIG_TPM_V2=y CONFIG_LZ4=y CONFIG_ERRNO_STR=y CONFIG_OF_LIBFDT_OVERLAY=y @@ -203,5 +200,3 @@ CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y CONFIG_UT_OVERLAY=y -CONFIG_SMEM=y -CONFIG_SANDBOX_SMEM=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index e922c4b38f..84b0756a4d 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -156,7 +156,6 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_TIMER_EARLY=y CONFIG_SANDBOX_TIMER=y -CONFIG_TPM_TIS_SANDBOX=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig index 8bdd4edcda..d1ca61bff2 100644 --- a/configs/sandbox_noblk_defconfig +++ b/configs/sandbox_noblk_defconfig @@ -155,7 +155,6 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_TIMER_EARLY=y CONFIG_SANDBOX_TIMER=y -CONFIG_TPM_TIS_SANDBOX=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index fb6bb4baa2..c00672f6cc 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -174,7 +174,6 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_TIMER_EARLY=y CONFIG_SANDBOX_TIMER=y -CONFIG_TPM_TIS_SANDBOX=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 2c93a5b34b..f6ec130ce2 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -43,9 +43,9 @@ CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set +CONFIG_MTD_PARTITIONS=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_MTD_PARTITIONS=y CONFIG_PHYLIB=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 7a9a83e3ae..ad21bdbab4 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -38,7 +38,6 @@ CONFIG_STM32_SDMMC2=y CONFIG_DM_PMIC=y # CONFIG_SPL_PMIC_CHILDREN is not set CONFIG_PMIC_STPMU1=y -CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STM32_VREFBUF=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 366d16f985..3c6b8866a7 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -47,9 +47,9 @@ CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set +CONFIG_MTD_PARTITIONS=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_MTD_PARTITIONS=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 7dfc88fdbb..fc5bc00d18 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -12,25 +12,18 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld4-ref" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_CONFIG=y -CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y # CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)" diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index ccd80c00f8..ce7bcfc97d 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -11,25 +11,18 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka" CONFIG_LOGLEVEL=6 CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NOR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_CONFIG=y -CONFIG_CMD_BOOTZ=y CONFIG_CMD_IMLS=y # CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)" diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 67ebde7a10..4a96c70103 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -8,24 +8,18 @@ CONFIG_MICRO_SUPPORT_CARD=y CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_LOGLEVEL=6 -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set CONFIG_CMD_CONFIG=y CONFIG_CMD_IMLS=y # CONFIG_CMD_XIMG is not set -# CONFIG_CMD_ENV_EXISTS is not set CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y # CONFIG_CMD_MISC is not set -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=uniphier-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=uniphier-nand.0:1m(firmware),-(UBI)" CONFIG_CMD_UBI=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 9fd0bec2c8..2e0f7b767b 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -7,7 +7,6 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -# CONFIG_CMD_BMODE is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig index eb6a921301..f8c8ddbbd1 100644 --- a/configs/wb45n_defconfig +++ b/configs/wb45n_defconfig @@ -23,9 +23,9 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_NAND=y -CONFIG_NAND_ATMEL=y CONFIG_MTD_DEVICE=y CONFIG_MTD_PARTITIONS=y +CONFIG_NAND=y +CONFIG_NAND_ATMEL=y CONFIG_LZMA=y CONFIG_OF_LIBFDT=y diff --git a/doc/driver-model/pci-info.txt b/doc/driver-model/pci-info.txt index 52b4389d2c..e1701d1fbc 100644 --- a/doc/driver-model/pci-info.txt +++ b/doc/driver-model/pci-info.txt @@ -133,3 +133,31 @@ When this bus is scanned we will end up with something like this: When accesses go to the pci@1f,0 device they are forwarded to its child, the emulator. + +The sandbox PCI drivers also support dynamic driver binding, allowing device +driver to declare the driver binding information via U_BOOT_PCI_DEVICE(), +eliminating the need to provide any device tree node under the host controller +node. It is required a "sandbox,dev-info" property must be provided in the +host controller node for this functionality to work. + + pci1: pci-controller1 { + compatible = "sandbox,pci"; + ... + sandbox,dev-info = <0x08 0x00 0x1234 0x5678 + 0x0c 0x00 0x1234 0x5678>; + }; + +The "sandbox,dev-info" property specifies all dynamic PCI devices on this bus. +Each dynamic PCI device is encoded as 4 cells a group. The first and second +cells are PCI device number and function number respectively. The third and +fourth cells are PCI vendor ID and device ID respectively. + +When this bus is scanned we will end up with something like this: + + pci [ + ] pci_sandbo |-- pci-controller1 + pci_emul [ ] sandbox_sw | |-- sandbox_swap_case_emul + pci_emul [ ] sandbox_sw | `-- sandbox_swap_case_emul + +Note the difference from the statically declared device nodes is that the +device is directly attached to the host controller, instead of via a container +device like pci@1f,0. diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 29375397e0..0cfb0fbabb 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -623,6 +623,42 @@ fail: return ret; } +int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device) +{ + const char *list, *end; + int len; + + list = ofnode_get_property(node, "compatible", &len); + if (!list) + return -ENOENT; + + end = list + len; + while (list < end) { + len = strlen(list); + if (len >= strlen("pciVVVV,DDDD")) { + char *s = strstr(list, "pci"); + + /* + * check if the string is something like pciVVVV,DDDD.RR + * or just pciVVVV,DDDD + */ + if (s && s[7] == ',' && + (s[12] == '.' || s[12] == 0)) { + s += 3; + *vendor = simple_strtol(s, NULL, 16); + + s += 5; + *device = simple_strtol(s, NULL, 16); + + return 0; + } + } + list += (len + 1); + } + + return -ENOENT; +} + int ofnode_read_addr_cells(ofnode node) { if (ofnode_is_np(node)) diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c index 78560b0fb4..fc047473f5 100644 --- a/drivers/cpu/bmips_cpu.c +++ b/drivers/cpu/bmips_cpu.c @@ -66,6 +66,10 @@ #define STRAPBUS_63268_FCVO_SHIFT 21 #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) +#define REG_BCM6838_OTP_BRCMBITS0 0x440 +#define VIPER_6838_FREQ_SHIFT 18 +#define VIPER_6838_FREQ_MASK (0x7 << VIPER_6838_FREQ_SHIFT) + struct bmips_cpu_priv; struct bmips_cpu_hw { @@ -272,6 +276,26 @@ static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv) } } +static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv) +{ + unsigned int mips_viper_freq; + + mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0); + mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK) + >> VIPER_6838_FREQ_SHIFT; + + switch (mips_viper_freq) { + case 0x0: + return 600000000; + case 0x1: + return 400000000; + case 0x2: + return 240000000; + default: + return 0; + } +} + static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv) { u32 val = readl_be(priv->regs + REG_BCM6328_OTP); @@ -346,6 +370,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm63268 = { .get_cpu_count = bcm6358_get_cpu_count, }; +static const struct bmips_cpu_hw bmips_cpu_bcm6838 = { + .get_cpu_desc = bmips_short_cpu_desc, + .get_cpu_freq = bcm6838_get_cpu_freq, + .get_cpu_count = bcm6358_get_cpu_count, +}; + /* Generic CPU Ops */ static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size) { @@ -444,6 +474,9 @@ static const struct udevice_id bmips_cpu_ids[] = { }, { .compatible = "brcm,bcm63268-cpu", .data = (ulong)&bmips_cpu_bcm63268, + }, { + .compatible = "brcm,bcm6838-cpu", + .data = (ulong)&bmips_cpu_bcm6838, }, { /* sentinel */ } }; diff --git a/drivers/misc/swap_case.c b/drivers/misc/swap_case.c index b777404c09..bffb809f14 100644 --- a/drivers/misc/swap_case.c +++ b/drivers/misc/swap_case.c @@ -118,6 +118,27 @@ static int sandbox_swap_case_read_config(struct udevice *emul, uint offset, *valuep = result; break; } + case PCI_CAPABILITY_LIST: + *valuep = PCI_CAP_ID_PM_OFFSET; + break; + case PCI_CAP_ID_PM_OFFSET: + *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM; + break; + case PCI_CAP_ID_EXP_OFFSET: + *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP; + break; + case PCI_CAP_ID_MSIX_OFFSET: + *valuep = PCI_CAP_ID_MSIX; + break; + case PCI_EXT_CAP_ID_ERR_OFFSET: + *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR; + break; + case PCI_EXT_CAP_ID_VC_OFFSET: + *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC; + break; + case PCI_EXT_CAP_ID_DSN_OFFSET: + *valuep = PCI_EXT_CAP_ID_DSN; + break; } return 0; @@ -142,6 +163,8 @@ static int sandbox_swap_case_write_config(struct udevice *emul, uint offset, debug("w bar %d=%lx\n", barnum, value); *bar = value; + /* space indicator (bit#0) is read-only */ + *bar |= barinfo[barnum].type; break; } } @@ -157,11 +180,11 @@ static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr, for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) { unsigned int size = barinfo[barnum].size; + u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; - if (addr >= plat->bar[barnum] && - addr < plat->bar[barnum] + size) { + if (addr >= base && addr < base + size) { *barnump = barnum; - *offsetp = addr - plat->bar[barnum]; + *offsetp = addr - base; return 0; } } @@ -283,3 +306,10 @@ U_BOOT_DRIVER(sandbox_swap_case_emul) = { .priv_auto_alloc_size = sizeof(struct swap_case_priv), .platdata_auto_alloc_size = sizeof(struct swap_case_platdata), }; + +static struct pci_device_id sandbox_swap_case_supported[] = { + { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_DEVICE_ID), SWAP_CASE_DRV_DATA }, + {}, +}; + +U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported); diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 865fdf4dbb..435ccac594 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -46,8 +46,12 @@ struct dwmci_exynos_priv_data { */ static void exynos_dwmci_clksel(struct dwmci_host *host) { +#ifdef CONFIG_DM_MMC + struct dwmci_exynos_priv_data *priv = + container_of(host, struct dwmci_exynos_priv_data, host); +#else struct dwmci_exynos_priv_data *priv = host->priv; - +#endif dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); } @@ -146,17 +150,11 @@ static int do_dwmci_init(struct dwmci_host *host) } static int exynos_dwmci_get_config(const void *blob, int node, - struct dwmci_host *host) + struct dwmci_host *host, + struct dwmci_exynos_priv_data *priv) { int err = 0; u32 base, timing[3]; - struct dwmci_exynos_priv_data *priv; - - priv = malloc(sizeof(struct dwmci_exynos_priv_data)); - if (!priv) { - pr_err("dwmci_exynos_priv_data malloc fail!\n"); - return -ENOMEM; - } /* Extract device id for each mmc channel */ host->dev_id = pinmux_decode_periph_id(blob, node); @@ -167,7 +165,6 @@ static int exynos_dwmci_get_config(const void *blob, int node, if (host->dev_index > 4) { printf("DWMMC%d: Can't get the dev index\n", host->dev_index); - free(priv); return -EINVAL; } @@ -178,7 +175,6 @@ static int exynos_dwmci_get_config(const void *blob, int node, base = fdtdec_get_addr(blob, node, "reg"); if (!base) { printf("DWMMC%d: Can't get base address\n", host->dev_index); - free(priv); return -EINVAL; } host->ioaddr = (void *)base; @@ -188,7 +184,6 @@ static int exynos_dwmci_get_config(const void *blob, int node, if (err) { printf("DWMMC%d: Can't get sdr-timings for devider\n", host->dev_index); - free(priv); return -EINVAL; } @@ -208,14 +203,13 @@ static int exynos_dwmci_get_config(const void *blob, int node, host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); host->div = fdtdec_get_int(blob, node, "div", 0); - host->priv = priv; - return 0; } static int exynos_dwmci_process_node(const void *blob, int node_list[], int count) { + struct dwmci_exynos_priv_data *priv; struct dwmci_host *host; int i, node, err; @@ -224,11 +218,20 @@ static int exynos_dwmci_process_node(const void *blob, if (node <= 0) continue; host = &dwmci_host[i]; - err = exynos_dwmci_get_config(blob, node, host); + + priv = malloc(sizeof(struct dwmci_exynos_priv_data)); + if (!priv) { + pr_err("dwmci_exynos_priv_data malloc fail!\n"); + return -ENOMEM; + } + + err = exynos_dwmci_get_config(blob, node, host, priv); if (err) { printf("%s: failed to decode dev %d\n", __func__, i); + free(priv); return err; } + host->priv = priv; do_dwmci_init(host); } @@ -266,7 +269,8 @@ static int exynos_dwmmc_probe(struct udevice *dev) struct dwmci_host *host = &priv->host; int err; - err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host); + err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host, + priv); if (err) return err; err = do_dwmci_init(host); @@ -291,6 +295,7 @@ static int exynos_dwmmc_bind(struct udevice *dev) static const struct udevice_id exynos_dwmmc_ids[] = { { .compatible = "samsung,exynos4412-dw-mshc" }, + { .compatible = "samsung,exynos-dwmmc" }, { } }; diff --git a/drivers/pci/pci-emul-uclass.c b/drivers/pci/pci-emul-uclass.c index 79e2c1420e..3822758354 100644 --- a/drivers/pci/pci-emul-uclass.c +++ b/drivers/pci/pci-emul-uclass.c @@ -11,33 +11,39 @@ #include <pci.h> #include <dm/lists.h> -struct sandbox_pci_priv { +struct sandbox_pci_emul_priv { int dev_count; }; int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, - struct udevice **emulp) + struct udevice **containerp, struct udevice **emulp) { struct udevice *dev; int ret; - ret = pci_bus_find_devfn(bus, find_devfn, &dev); + *containerp = NULL; + ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(find_devfn), &dev); if (ret) { debug("%s: Could not find emulator for dev %x\n", __func__, find_devfn); return ret; } + *containerp = dev; - ret = device_find_first_child(dev, emulp); - if (ret) - return ret; + if (device_get_uclass_id(dev) == UCLASS_PCI_GENERIC) { + ret = device_find_first_child(dev, emulp); + if (ret) + return ret; + } else { + *emulp = dev; + } return *emulp ? 0 : -ENODEV; } static int sandbox_pci_emul_post_probe(struct udevice *dev) { - struct sandbox_pci_priv *priv = dev->uclass->priv; + struct sandbox_pci_emul_priv *priv = dev->uclass->priv; priv->dev_count++; sandbox_set_enable_pci_map(true); @@ -47,7 +53,7 @@ static int sandbox_pci_emul_post_probe(struct udevice *dev) static int sandbox_pci_emul_pre_remove(struct udevice *dev) { - struct sandbox_pci_priv *priv = dev->uclass->priv; + struct sandbox_pci_emul_priv *priv = dev->uclass->priv; priv->dev_count--; sandbox_set_enable_pci_map(priv->dev_count > 0); @@ -60,5 +66,5 @@ UCLASS_DRIVER(pci_emul) = { .name = "pci_emul", .post_probe = sandbox_pci_emul_post_probe, .pre_remove = sandbox_pci_emul_pre_remove, - .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv), + .priv_auto_alloc_size = sizeof(struct sandbox_pci_emul_priv), }; diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 46e9c71bdf..e9671d9b76 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -690,7 +690,7 @@ static int pci_find_and_bind_driver(struct udevice *parent, if (ret) goto error; debug("%s: Match found: %s\n", __func__, drv->name); - dev->driver_data = find_id->driver_data; + dev->driver_data = id->driver_data; *devp = dev; return 0; } @@ -745,6 +745,8 @@ int pci_bind_bus_devices(struct udevice *bus) struct udevice *dev; ulong class; + if (!PCI_FUNC(bdf)) + found_multi = false; if (PCI_FUNC(bdf) && !found_multi) continue; /* Check only the first access, we don't expect problems */ @@ -987,19 +989,18 @@ static int pci_uclass_child_post_bind(struct udevice *dev) if (!dev_of_valid(dev)) return 0; - /* - * We could read vendor, device, class if available. But for now we - * just check the address. - */ pplat = dev_get_parent_platdata(dev); + + /* Extract vendor id and device id if available */ + ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device); + + /* Extract the devfn from fdt_pci_addr */ ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg", &addr); - if (ret) { if (ret != -ENOENT) return -EINVAL; } else { - /* extract the devfn from fdt_pci_addr */ pplat->devfn = addr.phys_hi & 0xff00; } @@ -1319,6 +1320,74 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); } +int dm_pci_find_capability(struct udevice *dev, int cap) +{ + u16 status; + u8 header_type; + int ttl = PCI_FIND_CAP_TTL; + u8 id; + u16 ent; + u8 pos; + + dm_pci_read_config16(dev, PCI_STATUS, &status); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); + if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS) + pos = PCI_CB_CAPABILITY_LIST; + else + pos = PCI_CAPABILITY_LIST; + + dm_pci_read_config8(dev, pos, &pos); + while (ttl--) { + if (pos < PCI_STD_HEADER_SIZEOF) + break; + pos &= ~3; + dm_pci_read_config16(dev, pos, &ent); + + id = ent & 0xff; + if (id == 0xff) + break; + if (id == cap) + return pos; + pos = (ent >> 8); + } + + return 0; +} + +int dm_pci_find_ext_capability(struct udevice *dev, int cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + dm_pci_read_config32(dev, pos, &header); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl--) { + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + dm_pci_read_config32(dev, pos, &header); + } + + return 0; +} + UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c index 67cd733e61..119a98d061 100644 --- a/drivers/pci/pci_sandbox.c +++ b/drivers/pci/pci_sandbox.c @@ -10,15 +10,27 @@ #include <inttypes.h> #include <pci.h> +#define FDT_DEV_INFO_CELLS 4 +#define FDT_DEV_INFO_SIZE (FDT_DEV_INFO_CELLS * sizeof(u32)) + +#define SANDBOX_PCI_DEVFN(d, f) ((d << 3) | f) + +struct sandbox_pci_priv { + struct { + u16 vendor; + u16 device; + } vendev[256]; +}; + static int sandbox_pci_write_config(struct udevice *bus, pci_dev_t devfn, uint offset, ulong value, enum pci_size_t size) { struct dm_pci_emul_ops *ops; - struct udevice *emul; + struct udevice *container, *emul; int ret; - ret = sandbox_pci_get_emul(bus, devfn, &emul); + ret = sandbox_pci_get_emul(bus, devfn, &container, &emul); if (ret) return ret == -ENODEV ? 0 : ret; ops = pci_get_emul_ops(emul); @@ -33,14 +45,31 @@ static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn, enum pci_size_t size) { struct dm_pci_emul_ops *ops; - struct udevice *emul; + struct udevice *container, *emul; + struct sandbox_pci_priv *priv = dev_get_priv(bus); int ret; /* Prepare the default response */ *valuep = pci_get_ff(size); - ret = sandbox_pci_get_emul(bus, devfn, &emul); - if (ret) - return ret == -ENODEV ? 0 : ret; + ret = sandbox_pci_get_emul(bus, devfn, &container, &emul); + if (ret) { + if (!container) { + u16 vendor, device; + + devfn = SANDBOX_PCI_DEVFN(PCI_DEV(devfn), + PCI_FUNC(devfn)); + vendor = priv->vendev[devfn].vendor; + device = priv->vendev[devfn].device; + if (offset == PCI_VENDOR_ID && vendor) + *valuep = vendor; + else if (offset == PCI_DEVICE_ID && device) + *valuep = device; + + return 0; + } else { + return ret == -ENODEV ? 0 : ret; + } + } ops = pci_get_emul_ops(emul); if (!ops || !ops->read_config) return -ENOSYS; @@ -48,6 +77,41 @@ static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn, return ops->read_config(emul, offset, valuep, size); } +static int sandbox_pci_probe(struct udevice *dev) +{ + struct sandbox_pci_priv *priv = dev_get_priv(dev); + const fdt32_t *cell; + u8 pdev, pfn, devfn; + int len; + + cell = ofnode_get_property(dev_ofnode(dev), "sandbox,dev-info", &len); + if (!cell) + return 0; + + if ((len % FDT_DEV_INFO_SIZE) == 0) { + int num = len / FDT_DEV_INFO_SIZE; + int i; + + for (i = 0; i < num; i++) { + debug("dev info #%d: %02x %02x %04x %04x\n", i, + fdt32_to_cpu(cell[0]), fdt32_to_cpu(cell[1]), + fdt32_to_cpu(cell[2]), fdt32_to_cpu(cell[3])); + + pdev = fdt32_to_cpu(cell[0]); + pfn = fdt32_to_cpu(cell[1]); + if (pdev > 31 || pfn > 7) + continue; + devfn = SANDBOX_PCI_DEVFN(pdev, pfn); + priv->vendev[devfn].vendor = fdt32_to_cpu(cell[2]); + priv->vendev[devfn].device = fdt32_to_cpu(cell[3]); + + cell += FDT_DEV_INFO_CELLS; + } + } + + return 0; +} + static const struct dm_pci_ops sandbox_pci_ops = { .read_config = sandbox_pci_read_config, .write_config = sandbox_pci_write_config, @@ -63,6 +127,8 @@ U_BOOT_DRIVER(pci_sandbox) = { .id = UCLASS_PCI, .of_match = sandbox_pci_ids, .ops = &sandbox_pci_ops, + .probe = sandbox_pci_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_pci_priv), /* Attach an emulator if we can */ .child_post_bind = dm_scan_fdt_dev, diff --git a/drivers/ram/bmips_ram.c b/drivers/ram/bmips_ram.c index cc37dfa08c..b5f19c983c 100644 --- a/drivers/ram/bmips_ram.c +++ b/drivers/ram/bmips_ram.c @@ -43,6 +43,7 @@ struct bmips_ram_hw { struct bmips_ram_priv { void __iomem *regs; + u32 force_size; const struct bmips_ram_hw *hw; }; @@ -104,7 +105,10 @@ static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info) const struct bmips_ram_hw *hw = priv->hw; info->base = 0x80000000; - info->size = hw->get_ram_size(priv); + if (priv->force_size) + info->size = priv->force_size; + else + info->size = hw->get_ram_size(priv); return 0; } @@ -155,6 +159,8 @@ static int bmips_ram_probe(struct udevice *dev) if (!priv->regs) return -EINVAL; + dev_read_u32(dev, "force-size", &priv->force_size); + priv->hw = hw; return 0; diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 63b232b536..c489deac2b 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -109,7 +109,6 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); __attribute__((weak, alias("serial_null"))); serial_initfunc(atmel_serial_initialize); -serial_initfunc(au1x00_serial_initialize); serial_initfunc(mcf_serial_initialize); serial_initfunc(mpc85xx_serial_initialize); serial_initfunc(mpc8xx_serial_initialize); @@ -164,7 +163,6 @@ void serial_register(struct serial_device *dev) void serial_initialize(void) { atmel_serial_initialize(); - au1x00_serial_initialize(); mcf_serial_initialize(); mpc85xx_serial_initialize(); mpc8xx_serial_initialize(); diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index f320708431..b9b081999a 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -149,14 +149,6 @@ #define gadget_is_dwc3(g) 0 #endif - - -/* - * CONFIG_USB_GADGET_SX2 - * CONFIG_USB_GADGET_AU1X00 - * ... - */ - /** * usb_gadget_controller_number - support bcdDevice id convention * @gadget: the controller being driven diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h new file mode 100644 index 0000000000..e79a98206a --- /dev/null +++ b/include/configs/bmips_bcm6838.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#ifndef __CONFIG_BMIPS_BCM6838_H +#define __CONFIG_BMIPS_BCM6838_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h new file mode 100644 index 0000000000..6126a8879e --- /dev/null +++ b/include/configs/broadcom_bcm968380gerg.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + */ + +#include <configs/bmips_common.h> +#include <configs/bmips_bcm6838.h> + +#define CONFIG_ENV_SIZE (8 * 1024) diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h deleted file mode 100644 index 82860bbaa8..0000000000 --- a/include/configs/dbau1x00.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * This file contains the configuration parameters for the dbau1x00 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ - -#ifdef CONFIG_DBAU1000 -/* Also known as Merlot */ -#define CONFIG_SOC_AU1000 1 -#else -#ifdef CONFIG_DBAU1100 -#define CONFIG_SOC_AU1100 1 -#else -#ifdef CONFIG_DBAU1500 -#define CONFIG_SOC_AU1500 1 -#else -#ifdef CONFIG_DBAU1550 -/* Cabernet */ -#define CONFIG_SOC_AU1550 1 -#else -#error "No valid board set" -#endif -#endif -#endif -#endif - -/* valid baudrates */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "bootfile=/tftpboot/vmlinux.srec\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "" - -#ifdef CONFIG_DBAU1550 -/* Boot from flash by default, revert to bootp */ -#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" -#else /* CONFIG_DBAU1550 */ -#define CONFIG_BOOTCOMMAND "bootp;bootm" -#endif /* CONFIG_DBAU1550 */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MHZ 396 - -#if (CONFIG_SYS_MHZ % 12) != 0 -#error "Invalid CPU frequency - must be multiple of 12!" -#endif - -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#ifdef CONFIG_DBAU1550 - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ - -#else /* CONFIG_DBAU1550 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ - -#endif /* CONFIG_DBAU1550 */ - -#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} - -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -/* We boot from this flash, selected with dip switch */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xB0030000 -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 2 - -#ifdef CONFIG_DBAU1550 -#define MEM_SIZE 192 -#else -#define MEM_SIZE 64 -#endif - -#define CONFIG_MEMSIZE_IN_BYTES - -#ifndef CONFIG_DBAU1550 -/*---ATA PCMCIA ------------------------------------*/ -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 -#define CONFIG_PCMCIA_SLOT_A - -#define CONFIG_ATAPI 1 - -/* We run CF in "true ide" mode or a harddrive via pcmcia */ -#define CONFIG_IDE_PCMCIA 1 - -/* We only support one slot for now */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 8 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET 0 - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 -#endif /* CONFIG_DBAU1550 */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index a7621fc701..cd2a9046af 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -138,6 +138,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ + func(MMC, mmc, 2) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 92811cfc54..67a790ef02 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -41,7 +41,7 @@ /* Console configuration */ -#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" #define CONFIG_DEFAULT_CONSOLE "ttySAC1,115200n8" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ @@ -50,7 +50,7 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_SIZE SZ_16K #define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ #define CONFIG_ENV_OVERWRITE @@ -83,6 +83,12 @@ "bl2 raw 0x1f 0x1d;" \ "tzsw raw 0x83f 0x138\0" +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) + +#include <config_distro_bootcmd.h> + /* * Bootable media layout: * dev: SD eMMC(part boot) @@ -100,21 +106,21 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \ "boot.scr\0" \ - "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \ "${kernelname}\0" \ - "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${ramdisk_addr_r} " \ "${initrdname}\0" \ - "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdt_addr_r} " \ "${fdtfile}\0" \ "check_ramdisk=" \ "if run loadinitrd; then " \ - "setenv initrd_addr ${initrdaddr};" \ + "setenv initrd_addr ${ramdisk_addr_r};" \ "else " \ "setenv initrd_addr -;" \ "fi;\0" \ "check_dtb=" \ "if run loaddtb; then " \ - "setenv fdt_addr ${fdtaddr};" \ + "setenv fdt_addr ${fdt_addr_r};" \ "else " \ "setenv fdt_addr;" \ "fi;\0" \ @@ -125,27 +131,24 @@ "run loadbootscript;" \ "source ${scriptaddr}\0" \ "boot_fit=" \ - "setenv kerneladdr 0x42000000;" \ "setenv kernelname Image.itb;" \ "run loadkernel;" \ "run kernel_args;" \ - "bootm ${kerneladdr}#${boardname}\0" \ + "bootm ${kernel_addr_r}#${boardname}\0" \ "boot_uimg=" \ - "setenv kerneladdr 0x40007FC0;" \ "setenv kernelname uImage;" \ "run check_dtb;" \ "run check_ramdisk;" \ "run loadkernel;" \ "run kernel_args;" \ - "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "bootm ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \ "boot_zimg=" \ - "setenv kerneladdr 0x40007FC0;" \ "setenv kernelname zImage;" \ "run check_dtb;" \ "run check_ramdisk;" \ "run loadkernel;" \ "run kernel_args;" \ - "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "bootz ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \ "if test -e mmc 0 boot.scr; then; " \ "run boot_script; " \ @@ -161,15 +164,16 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \ - "bootdelay=0\0" \ "dfu_alt_system="CONFIG_DFU_ALT \ "dfu_alt_info=Please reset the board\0" \ "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ "consoleoff=set console console=ram; save; reset\0" \ "initrdname=uInitrd\0" \ - "initrdaddr=42000000\0" \ + "ramdisk_addr_r=0x42000000\0" \ "scriptaddr=0x42000000\0" \ - "fdtaddr=40800000\0" + "fdt_addr_r=0x40800000\0" \ + "kernel_addr_r=0x41000000\0" \ + BOOTENV /* GPT */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h deleted file mode 100644 index 01296e08c3..0000000000 --- a/include/configs/pb1x00.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * This file contains the configuration parameters for the dbau1x00 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ - -#ifdef CONFIG_PB1000 -#define CONFIG_SOC_AU1000 1 -#else -#ifdef CONFIG_PB1100 -#define CONFIG_SOC_AU1100 1 -#else -#ifdef CONFIG_PB1500 -#define CONFIG_SOC_AU1500 1 -#else -#error "No valid board set" -#endif -#endif -#endif - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "bootfile=/vmlinux.img\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "" -/* Boot from NFS root */ -#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm" - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MALLOC_LEN 128*1024 - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MIPS_TIMER_FREQ 396000000 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#undef CONFIG_SYS_MEMTEST_START -#define CONFIG_SYS_MEMTEST_START 0x80200000 -#define CONFIG_SYS_MEMTEST_END 0x83800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x4000000 - -/* We boot from this flash, selected with dip switch */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_ADDR 0xB0030000 -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 2 - -#define CONFIG_MEMSIZE_IN_BYTES - -/*---USB -------------------------------------------*/ -#if 0 -#define CONFIG_USB_OHCI -#endif - -/*---ATA PCMCIA ------------------------------------*/ -#if 0 -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 -#define CONFIG_PCMCIA_SLOT_A - -#define CONFIG_ATAPI 1 - -/* We run CF in "true ide" mode or a harddrive via pcmcia */ -#define CONFIG_IDE_PCMCIA 1 - -/* We only support one slot for now */ -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 8 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET 0 - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index 3b0db32ece..c546a5a6d0 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H +#define EXYNOS_FDTFILE_SETTING \ + "fdtfile=exynos5250-snow.dtb\0" + #include <configs/exynos5250-common.h> #include <configs/exynos5-dt-common.h> #include <configs/exynos5-common.h> diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index cd08a7e4d0..ab36b74c4c 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -586,6 +586,19 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type, const char *propname, struct fdt_pci_addr *addr); /** + * ofnode_read_pci_vendev() - look up PCI vendor and device id + * + * Look at the compatible property of a device node that represents a PCI + * device and extract pci vendor id and device id from it. + * + * @param node node to examine + * @param vendor vendor id of the pci device + * @param device device id of the pci device + * @return 0 if ok, negative on error + */ +int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device); + +/** * ofnode_read_addr_cells() - Get the number of address cells for a node * * This walks back up the tree to find the closest #address-cells property diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 9fbaa7d81a..0e882cec59 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -302,7 +302,7 @@ int uclass_first_device_err(enum uclass_id id, struct udevice **devp); int uclass_next_device(struct udevice **devp); /** - * uclass_first_device() - Get the first device in a uclass + * uclass_first_device_check() - Get the first device in a uclass * * The device returned is probed if necessary, and ready for use * @@ -318,7 +318,7 @@ int uclass_next_device(struct udevice **devp); int uclass_first_device_check(enum uclass_id id, struct udevice **devp); /** - * uclass_next_device() - Get the next device in a uclass + * uclass_next_device_check() - Get the next device in a uclass * * The device returned is probed if necessary, and ready for use * diff --git a/include/netdev.h b/include/netdev.h index f27869072f..55001625fb 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -25,7 +25,6 @@ int cpu_eth_init(bd_t *bis); /* Driver initialization prototypes */ int at91emac_register(bd_t *bis, unsigned long iobase); -int au1x00_enet_initialize(bd_t*); int ax88180_initialize(bd_t *bis); int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); int bfin_EMAC_initialize(bd_t *bis); diff --git a/include/pci.h b/include/pci.h index 8e27cbfaf1..938a8390cb 100644 --- a/include/pci.h +++ b/include/pci.h @@ -17,6 +17,7 @@ * Under PCI, each device has 256 bytes of configuration address space, * of which the first 64 bytes are standardized as follows: */ +#define PCI_STD_HEADER_SIZEOF 64 #define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_COMMAND 0x04 /* 16 bits */ @@ -271,21 +272,6 @@ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ -/* From 440ep */ -#define PCI_ERREN 0x48 /* Error Enable */ -#define PCI_ERRSTS 0x49 /* Error Status */ -#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ -#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ -#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ -#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ -#define PCI_CAPID 0x58 /* Capability Identifier */ -#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ -#define PCI_PMC 0x5A /* Power Management Capabilities */ -#define PCI_PMCSR 0x5C /* Power Management Control Status */ -#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ -#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ -#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ - /* Header type 2 (CardBus bridges) */ #define PCI_CB_CAPABILITY_LIST 0x14 /* 0x15 reserved */ @@ -333,7 +319,21 @@ #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ -#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ +#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ +#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ +#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ +#define PCI_CAP_ID_DBG 0x0A /* Debug port */ +#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ +#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ +#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ +#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ +#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ +#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ +#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ +#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ +#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ +#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ +#define PCI_CAP_ID_MAX PCI_CAP_ID_EA #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ #define PCI_CAP_SIZEOF 4 @@ -449,6 +449,10 @@ #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ +#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ +#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ +#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM /* Include the ID list */ @@ -1308,6 +1312,51 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, */ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); +/** + * dm_pci_find_capability() - find a capability + * + * Tell if a device supports a given PCI capability. Returns the + * address of the requested capability structure within the device's + * PCI configuration space or 0 in case the device does not support it. + * + * Possible values for @cap: + * + * %PCI_CAP_ID_MSI Message Signalled Interrupts + * %PCI_CAP_ID_PCIX PCI-X + * %PCI_CAP_ID_EXP PCI Express + * %PCI_CAP_ID_MSIX MSI-X + * + * See PCI_CAP_ID_xxx for the complete capability ID codes. + * + * @dev: PCI device to query + * @cap: capability code + * @return: capability address or 0 if not supported + */ +int dm_pci_find_capability(struct udevice *dev, int cap); + +/** + * dm_pci_find_ext_capability() - find an extended capability + * + * Tell if a device supports a given PCI express extended capability. + * Returns the address of the requested extended capability structure + * within the device's PCI configuration space or 0 in case the device + * does not support it. + * + * Possible values for @cap: + * + * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting + * %PCI_EXT_CAP_ID_VC Virtual Channel + * %PCI_EXT_CAP_ID_DSN Device Serial Number + * %PCI_EXT_CAP_ID_PWR Power Budgeting + * + * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. + * + * @dev: PCI device to query + * @cap: extended capability code + * @return: extended capability address or 0 if not supported + */ +int dm_pci_find_ext_capability(struct udevice *dev, int cap); + #define dm_pci_virt_to_bus(dev, addr, flags) \ dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ @@ -1456,11 +1505,12 @@ struct dm_pci_emul_ops { * * @bus: PCI bus to search * @find_devfn: PCI device and function address (PCI_DEVFN()) + * @containerp: Returns container device if found * @emulp: Returns emulated device if found * @return 0 if found, -ENODEV if not found */ int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, - struct udevice **emulp); + struct udevice **containerp, struct udevice **emulp); #endif /* CONFIG_DM_PCI */ diff --git a/include/serial.h b/include/serial.h index b9ef6d91c9..9cd6f10703 100644 --- a/include/serial.h +++ b/include/serial.h @@ -182,7 +182,6 @@ struct serial_dev_priv { #define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops) void atmel_serial_initialize(void); -void au1x00_serial_initialize(void); void mcf_serial_initialize(void); void mpc85xx_serial_initialize(void); void mpc8xx_serial_initialize(void); diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 0d60da3f28..0ec125160d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -51,7 +51,6 @@ CONFIG_ARMADA100 CONFIG_ARMADA100_FEC CONFIG_ARMADA168 CONFIG_ARMADA_39X -CONFIG_ARMV7_PSCI_0_2 CONFIG_ARMV7_PSCI_1_0 CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE @@ -507,7 +506,6 @@ CONFIG_ENV_OVERWRITE CONFIG_ENV_RANGE CONFIG_ENV_RDADDR CONFIG_ENV_REFLASH -CONFIG_ENV_SECT_SIZE CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS CONFIG_ENV_SETTINGS_NAND_V1 CONFIG_ENV_SETTINGS_NAND_V2 @@ -1684,7 +1682,6 @@ CONFIG_RTC_DS3231 CONFIG_RTC_FTRTC010 CONFIG_RTC_IMXDI CONFIG_RTC_M41T11 -CONFIG_RTC_M41T60 CONFIG_RTC_M41T62 CONFIG_RTC_MC13XXX CONFIG_RTC_MC146818 @@ -1883,7 +1880,6 @@ CONFIG_SPI_ADDR CONFIG_SPI_BOOTING CONFIG_SPI_CS_IS_VALID CONFIG_SPI_DATAFLASH_WRITE_VERIFY -CONFIG_SPI_FLASH_ISSI CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX @@ -3030,7 +3026,6 @@ CONFIG_SYS_GPIO1_PRELIM CONFIG_SYS_GPIO2_DAT CONFIG_SYS_GPIO2_DIR CONFIG_SYS_GPIO2_PRELIM -CONFIG_SYS_GPIO_0_ADDR CONFIG_SYS_GPIO_EN CONFIG_SYS_GPIO_FUNC CONFIG_SYS_GPIO_I2C_SCL @@ -3384,7 +3379,6 @@ CONFIG_SYS_MACB2_BASE CONFIG_SYS_MACB3_BASE CONFIG_SYS_MAIN_PWR_ON CONFIG_SYS_MALLOC_BASE -CONFIG_SYS_MALLOC_LEN CONFIG_SYS_MALLOC_SIMPLE CONFIG_SYS_MAMR CONFIG_SYS_MAPLE @@ -4455,7 +4449,6 @@ CONFIG_SYS_WRITE_SWAPPED_DATA CONFIG_SYS_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB3_ADDR -CONFIG_SYS_XILINX_SPI_LIST CONFIG_SYS_XIMG_LEN CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT @@ -4714,8 +4707,6 @@ CONFIG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE CONFIG_VSC9953 CONFIG_VSC_CROSSBAR -CONFIG_WATCHDOG_BASEADDR -CONFIG_WATCHDOG_IRQ CONFIG_WATCHDOG_NOWAYOUT CONFIG_WATCHDOG_PRESC CONFIG_WATCHDOG_RC @@ -4730,7 +4721,6 @@ CONFIG_X86_REFCODE_ADDR CONFIG_X86_REFCODE_RUN_ADDR CONFIG_XGI_XG22_BASE CONFIG_XILINX_SPI_IDLE_VAL -CONFIG_XILINX_TB_WATCHDOG CONFIG_XR16L2751 CONFIG_XSENGINE CONFIG_XTFPGA diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped index e180ee9308..0f17c5879e 100644 --- a/scripts/dtc/pylibfdt/libfdt.i_shipped +++ b/scripts/dtc/pylibfdt/libfdt.i_shipped @@ -18,7 +18,8 @@ * a struct called fdt_property. That struct causes swig to create a class in * libfdt.py called fdt_property(), which confuses things. */ -static int _fdt_property(void *fdt, const char *name, const char *val, int len) +static int fdt_property_stub(void *fdt, const char *name, const char *val, + int len) { return fdt_property(fdt, name, val, len); } @@ -54,6 +55,7 @@ import struct # Pass this as the 'quiet' parameter to return -ENOTFOUND on NOTFOUND errors, # instead of raising an exception. QUIET_NOTFOUND = (NOTFOUND,) +QUIET_NOSPACE = (NOSPACE,) class FdtException(Exception): @@ -119,23 +121,18 @@ def check_err_null(val, quiet=()): raise FdtException(val) return val +class FdtRo(object): + """Class for a read-only device-tree -class Fdt: - """Device tree class, supporting all operations - - The Fdt object is created is created from a device tree binary file, - e.g. with something like: + This is a base class used by FdtRw (read-write access) and FdtSw + (sequential-write access). It implements read-only access to the + device tree. - fdt = Fdt(open("filename.dtb").read()) - - Operations can then be performed using the methods in this class. Each - method xxx(args...) corresponds to a libfdt function fdt_xxx(fdt, args...). + Here are the three classes and when you should use them: - All methods raise an FdtException if an error occurs. To avoid this - behaviour a 'quiet' parameter is provided for some functions. This - defaults to empty, but you can pass a list of errors that you expect. - If one of these errors occurs, the function will return an error number - (e.g. -NOTFOUND). + FdtRo - read-only access to an existing FDT + FdtRw - read-write access to an existing FDT (most common case) + FdtSw - for creating a new FDT, as well as allowing read-only access """ def __init__(self, data): self._fdt = bytearray(data) @@ -157,12 +154,14 @@ class Fdt: Args: nodeoffset: Node offset of previous node - depth: On input, the depth of the node at nodeoffset. On output, the - depth of the returned node + depth: The depth of the node at nodeoffset. This is used to + calculate the depth of the returned node quiet: Errors to ignore (empty to raise on all errors) Returns: - The offset of the next node, if any + Typle: + Offset of the next node, if any, else a -ve error + Depth of the returned node, if any, else undefined Raises: FdtException if no more nodes found or other error occurs @@ -205,7 +204,7 @@ class Fdt: Returns: Magic word """ - return fdt_magic(self._fdt) & 0xffffffff + return fdt_magic(self._fdt) def totalsize(self): """Return the total size of the device tree @@ -213,7 +212,7 @@ class Fdt: Returns: Total tree size in bytes """ - return check_err(fdt_totalsize(self._fdt)) + return fdt_totalsize(self._fdt) def off_dt_struct(self): """Return the start of the device-tree struct area @@ -221,7 +220,7 @@ class Fdt: Returns: Start offset of struct area """ - return check_err(fdt_off_dt_struct(self._fdt)) + return fdt_off_dt_struct(self._fdt) def off_dt_strings(self): """Return the start of the device-tree string area @@ -229,7 +228,7 @@ class Fdt: Returns: Start offset of string area """ - return check_err(fdt_off_dt_strings(self._fdt)) + return fdt_off_dt_strings(self._fdt) def off_mem_rsvmap(self): """Return the start of the memory reserve map @@ -237,7 +236,7 @@ class Fdt: Returns: Start offset of memory reserve map """ - return check_err(fdt_off_mem_rsvmap(self._fdt)) + return fdt_off_mem_rsvmap(self._fdt) def version(self): """Return the version of the device tree @@ -245,7 +244,7 @@ class Fdt: Returns: Version number of the device tree """ - return check_err(fdt_version(self._fdt)) + return fdt_version(self._fdt) def last_comp_version(self): """Return the last compatible version of the device tree @@ -253,7 +252,7 @@ class Fdt: Returns: Last compatible version number of the device tree """ - return check_err(fdt_last_comp_version(self._fdt)) + return fdt_last_comp_version(self._fdt) def boot_cpuid_phys(self): """Return the physical boot CPU ID @@ -261,7 +260,7 @@ class Fdt: Returns: Physical boot CPU ID """ - return check_err(fdt_boot_cpuid_phys(self._fdt)) + return fdt_boot_cpuid_phys(self._fdt) def size_dt_strings(self): """Return the start of the device-tree string area @@ -269,7 +268,7 @@ class Fdt: Returns: Start offset of string area """ - return check_err(fdt_size_dt_strings(self._fdt)) + return fdt_size_dt_strings(self._fdt) def size_dt_struct(self): """Return the start of the device-tree struct area @@ -277,7 +276,7 @@ class Fdt: Returns: Start offset of struct area """ - return check_err(fdt_size_dt_struct(self._fdt)) + return fdt_size_dt_struct(self._fdt) def num_mem_rsv(self, quiet=()): """Return the number of memory reserve-map records @@ -398,26 +397,90 @@ class Fdt: return pdata return Property(pdata[0], pdata[1]) - def get_property(self, nodeoffset, prop_name, quiet=()): - """Obtains a property by name + def getprop(self, nodeoffset, prop_name, quiet=()): + """Get a property from a node Args: - nodeoffset: Offset to the node to check + nodeoffset: Node offset containing property to get prop_name: Name of property to get quiet: Errors to ignore (empty to raise on all errors) Returns: - Property object, or None if not found + Value of property as a Property object (which can be used as a + bytearray/string), or -ve error number. On failure, returns an + integer error Raises: - FdtException on error (e.g. invalid prop_offset or device - tree format) + FdtError if any error occurs (e.g. the property is not found) """ - pdata = check_err_null( - fdt_get_property(self._fdt, nodeoffset, prop_name), quiet) + pdata = check_err_null(fdt_getprop(self._fdt, nodeoffset, prop_name), + quiet) if isinstance(pdata, (int)): return pdata - return Property(pdata[0], pdata[1]) + return Property(prop_name, bytearray(pdata[0])) + + def get_phandle(self, nodeoffset): + """Get the phandle of a node + + Args: + nodeoffset: Node offset to check + + Returns: + phandle of node, or 0 if the node has no phandle or another error + occurs + """ + return fdt_get_phandle(self._fdt, nodeoffset) + + def parent_offset(self, nodeoffset, quiet=()): + """Get the offset of a node's parent + + Args: + nodeoffset: Node offset to check + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + The offset of the parent node, if any + + Raises: + FdtException if no parent found or other error occurs + """ + return check_err(fdt_parent_offset(self._fdt, nodeoffset), quiet) + + def node_offset_by_phandle(self, phandle, quiet=()): + """Get the offset of a node with the given phandle + + Args: + phandle: Phandle to search for + quiet: Errors to ignore (empty to raise on all errors) + + Returns: + The offset of node with that phandle, if any + + Raises: + FdtException if no node found or other error occurs + """ + return check_err(fdt_node_offset_by_phandle(self._fdt, phandle), quiet) + + +class Fdt(FdtRo): + """Device tree class, supporting all operations + + The Fdt object is created is created from a device tree binary file, + e.g. with something like: + + fdt = Fdt(open("filename.dtb").read()) + + Operations can then be performed using the methods in this class. Each + method xxx(args...) corresponds to a libfdt function fdt_xxx(fdt, args...). + + All methods raise an FdtException if an error occurs. To avoid this + behaviour a 'quiet' parameter is provided for some functions. This + defaults to empty, but you can pass a list of errors that you expect. + If one of these errors occurs, the function will return an error number + (e.g. -NOTFOUND). + """ + def __init__(self, data): + FdtRo.__init__(self, data) @staticmethod def create_empty_tree(size, quiet=()): @@ -435,18 +498,18 @@ class Fdt: return err return Fdt(data) - def open_into(self, size, quiet=()): + def resize(self, size, quiet=()): """Move the device tree into a larger or smaller space This creates a new device tree of size @size and moves the existing device tree contents over to that. It can be used to create more space - in a device tree. + in a device tree. Note that the Fdt object remains the same, but it + now has a new bytearray holding the contents. Args: size: Required new size of device tree in bytes """ fdt = bytearray(size) - fdt[:len(self._fdt)] = self._fdt err = check_err(fdt_open_into(self._fdt, fdt, size), quiet) if err: return err @@ -460,6 +523,9 @@ class Fdt: Args: quiet: Errors to ignore (empty to raise on all errors) + Returns: + Error code, or 0 if OK + Raises: FdtException if any error occurs """ @@ -469,79 +535,12 @@ class Fdt: del self._fdt[self.totalsize():] return err - def getprop(self, nodeoffset, prop_name, quiet=()): - """Get a property from a node - - Args: - nodeoffset: Node offset containing property to get - prop_name: Name of property to get - quiet: Errors to ignore (empty to raise on all errors) - - Returns: - Value of property as a string, or -ve error number - - Raises: - FdtError if any error occurs (e.g. the property is not found) - """ - pdata = check_err_null(fdt_getprop(self._fdt, nodeoffset, prop_name), - quiet) - if isinstance(pdata, (int)): - return pdata - return str(pdata[0]) - - def getprop_obj(self, nodeoffset, prop_name, quiet=()): - """Get a property from a node as a Property object - - Args: - nodeoffset: Node offset containing property to get - prop_name: Name of property to get - quiet: Errors to ignore (empty to raise on all errors) - - Returns: - Property object, or None if not found - - Raises: - FdtError if any error occurs (e.g. the property is not found) - """ - pdata = check_err_null(fdt_getprop(self._fdt, nodeoffset, prop_name), - quiet) - if isinstance(pdata, (int)): - return None - return Property(prop_name, bytearray(pdata[0])) - - def get_phandle(self, nodeoffset): - """Get the phandle of a node - - Args: - nodeoffset: Node offset to check - - Returns: - phandle of node, or 0 if the node has no phandle or another error - occurs - """ - return fdt_get_phandle(self._fdt, nodeoffset) - - def parent_offset(self, nodeoffset, quiet=()): - """Get the offset of a node's parent - - Args: - nodeoffset: Node offset to check - quiet: Errors to ignore (empty to raise on all errors) - - Returns: - The offset of the parent node, if any - - Raises: - FdtException if no parent found or other error occurs - """ - return check_err(fdt_parent_offset(self._fdt, nodeoffset), quiet) - def set_name(self, nodeoffset, name, quiet=()): """Set the name of a node Args: nodeoffset: Node offset of node to update - name: New node name + name: New node name (string without \0) Returns: Error code, or 0 if OK @@ -549,6 +548,8 @@ class Fdt: Raises: FdtException if no parent found or other error occurs """ + if chr(0) in name: + raise ValueError('Property contains embedded nul characters') return check_err(fdt_set_name(self._fdt, nodeoffset, name), quiet) def setprop(self, nodeoffset, prop_name, val, quiet=()): @@ -613,7 +614,8 @@ class Fdt: Args: nodeoffset: Node offset containing the property to create/update prop_name: Name of property - val: Value to write (string without nul terminator) + val: Value to write (string without nul terminator). Unicode is + supposed by encoding to UTF-8 quiet: Errors to ignore (empty to raise on all errors) Returns: @@ -622,7 +624,7 @@ class Fdt: Raises: FdtException if no parent found or other error occurs """ - val += '\0' + val = val.encode('utf-8') + '\0' return check_err(fdt_setprop(self._fdt, nodeoffset, prop_name, val, len(val)), quiet) @@ -638,21 +640,6 @@ class Fdt: """ return check_err(fdt_delprop(self._fdt, nodeoffset, prop_name)) - def node_offset_by_phandle(self, phandle, quiet=()): - """Get the offset of a node with the given phandle - - Args: - phandle: Phandle to search for - quiet: Errors to ignore (empty to raise on all errors) - - Returns: - The offset of node with that phandle, if any - - Raises: - FdtException if no node found or other error occurs - """ - return check_err(fdt_node_offset_by_phandle(self._fdt, phandle), quiet) - def del_node(self, nodeoffset): """Delete a node @@ -696,16 +683,20 @@ class Property(bytearray): return self.as_cell('q') def as_str(self): - return self[:-1] + """Unicode is supported by decoding from UTF-8""" + if self[-1] != 0: + raise ValueError('Property lacks nul termination') + if 0 in self[:-1]: + raise ValueError('Property contains embedded nul characters') + return self[:-1].decode('utf-8') -class FdtSw(object): +class FdtSw(FdtRo): """Software interface to create a device tree from scratch The methods in this class work by adding to an existing 'partial' device tree buffer of a fixed size created by instantiating this class. When the - tree is complete, call finish() to complete the device tree so that it can - be used. + tree is complete, call as_fdt() to obtain a device tree ready to be used. Similarly with nodes, a new node is started with begin_node() and finished with end_node(). @@ -713,58 +704,87 @@ class FdtSw(object): The context manager functions can be used to make this a bit easier: # First create the device tree with a node and property: - with FdtSw(small_size) as sw: - with sw.AddNode('node'): - sw.property_u32('reg', 2) - fdt = sw.AsFdt() + sw = FdtSw() + with sw.add_node('node'): + sw.property_u32('reg', 2) + fdt = sw.as_fdt() # Now we can use it as a real device tree fdt.setprop_u32(0, 'reg', 3) + + The size hint provides a starting size for the space to be used by the + device tree. This will be increased automatically as needed as new items + are added to the tree. """ - def __init__(self, size, quiet=()): - fdtrw = bytearray(size) - err = check_err(fdt_create(fdtrw, size)) - if err: - return err - self._fdtrw = fdtrw + INC_SIZE = 1024 # Expand size by this much when out of space - def __enter__(self): - """Contact manager to use to create a device tree via software""" - return self + def __init__(self, size_hint=None): + """Create a new FdtSw object - def __exit__(self, type, value, traceback): - check_err(fdt_finish(self._fdtrw)) + Args: + size_hint: A hint as to the initial size to use + + Raises: + ValueError if size_hint is negative - def AsFdt(self): + Returns: + FdtSw object on success, else integer error code (if not raising) + """ + if not size_hint: + size_hint = self.INC_SIZE + fdtsw = bytearray(size_hint) + err = check_err(fdt_create(fdtsw, size_hint)) + if err: + return err + self._fdt = fdtsw + + def as_fdt(self): """Convert a FdtSw into an Fdt so it can be accessed as normal - Note that finish() must be called before this function will work. If - you are using the context manager (see 'with' code in the FdtSw class - comment) then this will happen automatically. + Creates a new Fdt object from the work-in-progress device tree. This + does not call fdt_finish() on the current object, so it is possible to + add more nodes/properties and call as_fdt() again to get an updated + tree. Returns: Fdt object allowing access to the newly created device tree """ - return Fdt(self._fdtrw) + fdtsw = bytearray(self._fdt) + check_err(fdt_finish(fdtsw)) + return Fdt(fdtsw) - def resize(self, size, quiet=()): + def check_space(self, val): + """Check if we need to add more space to the FDT + + This should be called with the error code from an operation. If this is + -NOSPACE then the FDT will be expanded to have more space, and True will + be returned, indicating that the operation needs to be tried again. + + Args: + val: Return value from the operation that was attempted + + Returns: + True if the operation must be retried, else False + """ + if check_err(val, QUIET_NOSPACE) < 0: + self.resize(len(self._fdt) + self.INC_SIZE) + return True + return False + + def resize(self, size): """Resize the buffer to accommodate a larger tree Args: size: New size of tree - quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ fdt = bytearray(size) - fdt[:len(self._fdtrw)] = self._fdtrw - err = check_err(fdt_resize(self._fdtrw, fdt, size), quiet) - if err: - return err - self._fdtrw = fdt + err = check_err(fdt_resize(self._fdt, fdt, size)) + self._fdt = fdt - def add_reservemap_entry(self, addr, size, quiet=()): + def add_reservemap_entry(self, addr, size): """Add a new memory reserve map entry Once finished adding, you must call finish_reservemap(). @@ -772,26 +792,24 @@ class FdtSw(object): Args: addr: 64-bit start address size: 64-bit size - quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_add_reservemap_entry(self._fdtrw, addr, size), - quiet) + while self.check_space(fdt_add_reservemap_entry(self._fdt, addr, + size)): + pass - def finish_reservemap(self, quiet=()): + def finish_reservemap(self): """Indicate that there are no more reserve map entries to add - Args: - quiet: Errors to ignore (empty to raise on all errors) - Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_finish_reservemap(self._fdtrw), quiet) + while self.check_space(fdt_finish_reservemap(self._fdt)): + pass - def begin_node(self, name, quiet=()): + def begin_node(self, name): """Begin a new node Use this before adding properties to the node. Then call end_node() to @@ -800,14 +818,14 @@ class FdtSw(object): Args: name: Name of node to begin - quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_begin_node(self._fdtrw, name), quiet) + while self.check_space(fdt_begin_node(self._fdt, name)): + pass - def property_string(self, name, string, quiet=()): + def property_string(self, name, string): """Add a property with a string value The string will be nul-terminated when written to the device tree @@ -815,14 +833,14 @@ class FdtSw(object): Args: name: Name of property to add string: String value of property - quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_property_string(self._fdtrw, name, string), quiet) + while self.check_space(fdt_property_string(self._fdt, name, string)): + pass - def property_u32(self, name, val, quiet=()): + def property_u32(self, name, val): """Add a property with a 32-bit value Write a single-cell value to the device tree @@ -830,14 +848,14 @@ class FdtSw(object): Args: name: Name of property to add val: Value of property - quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_property_u32(self._fdtrw, name, val), quiet) + while self.check_space(fdt_property_u32(self._fdt, name, val)): + pass - def property_u64(self, name, val, quiet=()): + def property_u64(self, name, val): """Add a property with a 64-bit value Write a double-cell value to the device tree in big-endian format @@ -845,14 +863,14 @@ class FdtSw(object): Args: name: Name of property to add val: Value of property - quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_property_u64(self._fdtrw, name, val), quiet) + while self.check_space(fdt_property_u64(self._fdt, name, val)): + pass - def property_cell(self, name, val, quiet=()): + def property_cell(self, name, val): """Add a property with a single-cell value Write a single-cell value to the device tree @@ -863,11 +881,12 @@ class FdtSw(object): quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_property_cell(self._fdtrw, name, val), quiet) + while self.check_space(fdt_property_cell(self._fdt, name, val)): + pass - def property(self, name, val, quiet=()): + def property(self, name, val): """Add a property Write a new property with the given value to the device tree. The value @@ -879,11 +898,13 @@ class FdtSw(object): quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(_fdt_property(self._fdtrw, name, val, len(val)), quiet) + while self.check_space(fdt_property_stub(self._fdt, name, val, + len(val))): + pass - def end_node(self, quiet=()): + def end_node(self): """End a node Use this after adding properties to a node to close it off. You can also @@ -893,24 +914,12 @@ class FdtSw(object): quiet: Errors to ignore (empty to raise on all errors) Raises: - FdtException if no node found or other error occurs - """ - return check_err(fdt_end_node(self._fdtrw), quiet) - - def finish(self, quiet=()): - """Finish writing the device tree - - This closes off the device tree ready for use - - Args: - quiet: Errors to ignore (empty to raise on all errors) - - Raises: - FdtException if no node found or other error occurs + FdtException on any error """ - return check_err(fdt_finish(self._fdtrw), quiet) + while self.check_space(fdt_end_node(self._fdt)): + pass - def AddNode(self, name): + def add_node(self, name): """Create a new context for adding a node When used in a 'with' clause this starts a new node and finishes it @@ -919,7 +928,7 @@ class FdtSw(object): Args: name: Name of node to add """ - return NodeAdder(self._fdtrw, name) + return NodeAdder(self, name) class NodeAdder(): @@ -927,26 +936,30 @@ class NodeAdder(): This allows you to add nodes in a more natural way: - with fdtsw.AddNode('name'): + with fdtsw.add_node('name'): fdtsw.property_string('test', 'value') The node is automatically completed with a call to end_node() when the context exits. """ - def __init__(self, fdt, name): - self._fdt = fdt + def __init__(self, fdtsw, name): + self._fdt = fdtsw self._name = name def __enter__(self): - check_err(fdt_begin_node(self._fdt, self._name)) + self._fdt.begin_node(self._name) def __exit__(self, type, value, traceback): - check_err(fdt_end_node(self._fdt)) + self._fdt.end_node() %} %rename(fdt_property) fdt_property_func; -typedef int fdt32_t; +/* + * fdt32_t is a big-endian 32-bit value defined to uint32_t in libfdt_env.h + * so use the same type here. + */ +typedef uint32_t fdt32_t; %include "libfdt/fdt.h" @@ -1039,16 +1052,17 @@ typedef int fdt32_t; %warnfilter(302) fdt_property; /* These are macros in the header so have to be redefined here */ -int fdt_magic(const void *fdt); -int fdt_totalsize(const void *fdt); -int fdt_off_dt_struct(const void *fdt); -int fdt_off_dt_strings(const void *fdt); -int fdt_off_mem_rsvmap(const void *fdt); -int fdt_version(const void *fdt); -int fdt_last_comp_version(const void *fdt); -int fdt_boot_cpuid_phys(const void *fdt); -int fdt_size_dt_strings(const void *fdt); -int fdt_size_dt_struct(const void *fdt); +uint32_t fdt_magic(const void *fdt); +uint32_t fdt_totalsize(const void *fdt); +uint32_t fdt_off_dt_struct(const void *fdt); +uint32_t fdt_off_dt_strings(const void *fdt); +uint32_t fdt_off_mem_rsvmap(const void *fdt); +uint32_t fdt_version(const void *fdt); +uint32_t fdt_last_comp_version(const void *fdt); +uint32_t fdt_boot_cpuid_phys(const void *fdt); +uint32_t fdt_size_dt_strings(const void *fdt); +uint32_t fdt_size_dt_struct(const void *fdt); + int fdt_property_string(void *fdt, const char *name, const char *val); int fdt_property_cell(void *fdt, const char *name, uint32_t val); @@ -1056,6 +1070,6 @@ int fdt_property_cell(void *fdt, const char *name, uint32_t val); * This function has a stub since the name fdt_property is used for both a * function and a struct, which confuses SWIG. */ -int _fdt_property(void *fdt, const char *name, const char *val, int len); +int fdt_property_stub(void *fdt, const char *name, const char *val, int len); %include <../libfdt/libfdt.h> diff --git a/test/dm/pci.c b/test/dm/pci.c index 47b5d22af8..869970072d 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> #include <asm/io.h> +#include <asm/test.h> #include <dm/test.h> #include <test/ut.h> @@ -20,28 +21,71 @@ static int dm_test_pci_base(struct unit_test_state *uts) } DM_TEST(dm_test_pci_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -/* Test that sandbox PCI bus numbering works correctly */ -static int dm_test_pci_busnum(struct unit_test_state *uts) +/* Test that sandbox PCI bus numbering and device works correctly */ +static int dm_test_pci_busdev(struct unit_test_state *uts) { struct udevice *bus; + struct udevice *swap; + u16 vendor, device; + /* Test bus#0 and its devices */ ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus)); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap)); + vendor = 0; + ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor)); + ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); + device = 0; + ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device)); + ut_asserteq(SANDBOX_PCI_DEVICE_ID, device); + + /* Test bus#1 and its devices */ + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); + + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); + vendor = 0; + ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor)); + ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap)); + device = 0; + ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device)); + ut_asserteq(SANDBOX_PCI_DEVICE_ID, device); + return 0; } -DM_TEST(dm_test_pci_busnum, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +DM_TEST(dm_test_pci_busdev, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); /* Test that we can use the swapcase device correctly */ static int dm_test_pci_swapcase(struct unit_test_state *uts) { - struct udevice *emul, *swap; + struct udevice *swap; ulong io_addr, mem_addr; char *ptr; - /* Check that asking for the device automatically fires up PCI */ - ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul)); + /* Check that asking for the device 0 automatically fires up PCI */ + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap)); + + /* First test I/O */ + io_addr = dm_pci_read_bar32(swap, 0); + outb(2, io_addr); + ut_asserteq(2, inb(io_addr)); + + /* + * Now test memory mapping - note we must unmap and remap to cause + * the swapcase emulation to see our data and response. + */ + mem_addr = dm_pci_read_bar32(swap, 1); + ptr = map_sysmem(mem_addr, 20); + strcpy(ptr, "This is a TesT"); + unmap_sysmem(ptr); + + ptr = map_sysmem(mem_addr, 20); + ut_asserteq_str("tHIS IS A tESt", ptr); + unmap_sysmem(ptr); + + /* Check that asking for the device 1 automatically fires up PCI */ ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); - ut_assert(device_active(swap)); /* First test I/O */ io_addr = dm_pci_read_bar32(swap, 0); @@ -64,3 +108,115 @@ static int dm_test_pci_swapcase(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_pci_swapcase, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that we can dynamically bind the device driver correctly */ +static int dm_test_pci_drvdata(struct unit_test_state *uts) +{ + struct udevice *bus, *swap; + + /* Check that asking for the device automatically fires up PCI */ + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); + + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); + ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap)); + ut_asserteq(SWAP_CASE_DRV_DATA, swap->driver_data); + + return 0; +} +DM_TEST(dm_test_pci_drvdata, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test that devices on PCI bus#2 can be accessed correctly */ +static int dm_test_pci_mixed(struct unit_test_state *uts) +{ + /* PCI bus#2 has both statically and dynamic declared devices */ + struct udevice *bus, *swap; + u16 vendor, device; + ulong io_addr, mem_addr; + char *ptr; + + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 2, &bus)); + + /* Test the dynamic device */ + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x08, 0), &swap)); + vendor = 0; + ut_assertok(dm_pci_read_config16(swap, PCI_VENDOR_ID, &vendor)); + ut_asserteq(SANDBOX_PCI_VENDOR_ID, vendor); + + /* First test I/O */ + io_addr = dm_pci_read_bar32(swap, 0); + outb(2, io_addr); + ut_asserteq(2, inb(io_addr)); + + /* + * Now test memory mapping - note we must unmap and remap to cause + * the swapcase emulation to see our data and response. + */ + mem_addr = dm_pci_read_bar32(swap, 1); + ptr = map_sysmem(mem_addr, 30); + strcpy(ptr, "This is a TesT oN dYNAMIc"); + unmap_sysmem(ptr); + + ptr = map_sysmem(mem_addr, 30); + ut_asserteq_str("tHIS IS A tESt On DynamiC", ptr); + unmap_sysmem(ptr); + + /* Test the static device */ + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(2, 0x1f, 0), &swap)); + device = 0; + ut_assertok(dm_pci_read_config16(swap, PCI_DEVICE_ID, &device)); + ut_asserteq(SANDBOX_PCI_DEVICE_ID, device); + + /* First test I/O */ + io_addr = dm_pci_read_bar32(swap, 0); + outb(2, io_addr); + ut_asserteq(2, inb(io_addr)); + + /* + * Now test memory mapping - note we must unmap and remap to cause + * the swapcase emulation to see our data and response. + */ + mem_addr = dm_pci_read_bar32(swap, 1); + ptr = map_sysmem(mem_addr, 30); + strcpy(ptr, "This is a TesT oN sTATIc"); + unmap_sysmem(ptr); + + ptr = map_sysmem(mem_addr, 30); + ut_asserteq_str("tHIS IS A tESt On StatiC", ptr); + unmap_sysmem(ptr); + + return 0; +} +DM_TEST(dm_test_pci_mixed, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); + +/* Test looking up PCI capability and extended capability */ +static int dm_test_pci_cap(struct unit_test_state *uts) +{ + struct udevice *bus, *swap; + int cap; + + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus)); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap)); + + /* look up PCI_CAP_ID_EXP */ + cap = dm_pci_find_capability(swap, PCI_CAP_ID_EXP); + ut_asserteq(PCI_CAP_ID_EXP_OFFSET, cap); + + /* look up PCI_CAP_ID_PCIX */ + cap = dm_pci_find_capability(swap, PCI_CAP_ID_PCIX); + ut_asserteq(0, cap); + + ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus)); + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap)); + + /* look up PCI_EXT_CAP_ID_DSN */ + cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_DSN); + ut_asserteq(PCI_EXT_CAP_ID_DSN_OFFSET, cap); + + /* look up PCI_EXT_CAP_ID_SRIOV */ + cap = dm_pci_find_ext_capability(swap, PCI_EXT_CAP_ID_SRIOV); + ut_asserteq(0, cap); + + return 0; +} +DM_TEST(dm_test_pci_cap, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); diff --git a/tools/dtoc/fdt.py b/tools/dtoc/fdt.py index d36179bad3..55baa3857f 100644 --- a/tools/dtoc/fdt.py +++ b/tools/dtoc/fdt.py @@ -287,7 +287,7 @@ class Node: fdt_obj = self._fdt._fdt_obj if fdt_obj.setprop_u32(self.Offset(), prop_name, 0, (libfdt.NOSPACE,)) == -libfdt.NOSPACE: - fdt_obj.open_into(fdt_obj.totalsize() + 1024) + fdt_obj.resize(fdt_obj.totalsize() + 1024) fdt_obj.setprop_u32(self.Offset(), prop_name, 0) self.props[prop_name] = Prop(self, -1, prop_name, '\0' * 4) self._fdt.Invalidate() diff --git a/tools/dtoc/test_fdt.py b/tools/dtoc/test_fdt.py index 6fe03ac53d..e88d19f80e 100755 --- a/tools/dtoc/test_fdt.py +++ b/tools/dtoc/test_fdt.py @@ -233,7 +233,7 @@ class TestProp(unittest.TestCase): Return fdt.Prop object for this property """ - p = self.fdt.get_property(self.node.Offset(), prop_name) + p = self.fdt.getprop(self.node.Offset(), prop_name) return fdt.Prop(self.node, -1, prop_name, p) def testMakeProp(self): diff --git a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch index 702c0306ff..702c0306ff 100644 --- a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch +++ b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch |