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-rw-r--r--arch/sh/Kconfig42
-rw-r--r--arch/sh/cpu/sh2/Makefile9
-rw-r--r--arch/sh/cpu/sh2/config.mk15
-rw-r--r--arch/sh/cpu/sh2/cpu.c84
-rw-r--r--arch/sh/cpu/sh2/interrupts.c22
-rw-r--r--arch/sh/cpu/sh2/watchdog.c23
-rw-r--r--arch/sh/cpu/sh3/Makefile12
-rw-r--r--arch/sh/cpu/sh3/config.mk12
-rw-r--r--arch/sh/cpu/sh3/cpu.c67
-rw-r--r--arch/sh/cpu/sh3/interrupts.c25
-rw-r--r--arch/sh/cpu/sh3/watchdog.c26
-rw-r--r--arch/sh/include/asm/config.h2
-rw-r--r--arch/sh/include/asm/cpu_sh2.h30
-rw-r--r--arch/sh/include/asm/cpu_sh3.h30
-rw-r--r--arch/sh/include/asm/cpu_sh7203.h41
-rw-r--r--arch/sh/include/asm/cpu_sh7264.h41
-rw-r--r--arch/sh/include/asm/cpu_sh7269.h26
-rw-r--r--arch/sh/include/asm/cpu_sh7706.h50
-rw-r--r--arch/sh/include/asm/cpu_sh7710.h61
-rw-r--r--arch/sh/include/asm/cpu_sh7720.h206
-rw-r--r--arch/sh/include/asm/processor.h6
-rw-r--r--arch/sh/lib/Makefile5
-rw-r--r--arch/sh/lib/start.S6
-rw-r--r--arch/sh/lib/time.c5
-rw-r--r--board/mpr2/Kconfig9
-rw-r--r--board/mpr2/MAINTAINERS6
-rw-r--r--board/mpr2/Makefile19
-rw-r--r--board/mpr2/lowlevel_init.S117
-rw-r--r--board/mpr2/mpr2.c137
-rw-r--r--board/ms7720se/Kconfig9
-rw-r--r--board/ms7720se/MAINTAINERS6
-rw-r--r--board/ms7720se/Makefile16
-rw-r--r--board/ms7720se/lowlevel_init.S184
-rw-r--r--board/ms7720se/ms7720se.c35
-rw-r--r--board/renesas/rsk7203/Kconfig12
-rw-r--r--board/renesas/rsk7203/MAINTAINERS7
-rw-r--r--board/renesas/rsk7203/Makefile10
-rw-r--r--board/renesas/rsk7203/lowlevel_init.S199
-rw-r--r--board/renesas/rsk7203/rsk7203.c59
-rw-r--r--board/renesas/rsk7264/Kconfig12
-rw-r--r--board/renesas/rsk7264/MAINTAINERS6
-rw-r--r--board/renesas/rsk7264/Makefile7
-rw-r--r--board/renesas/rsk7264/lowlevel_init.S209
-rw-r--r--board/renesas/rsk7264/rsk7264.c60
-rw-r--r--board/renesas/rsk7269/Kconfig12
-rw-r--r--board/renesas/rsk7269/MAINTAINERS6
-rw-r--r--board/renesas/rsk7269/Makefile8
-rw-r--r--board/renesas/rsk7269/lowlevel_init.S179
-rw-r--r--board/renesas/rsk7269/rsk7269.c61
-rw-r--r--board/shmin/Kconfig9
-rw-r--r--board/shmin/MAINTAINERS7
-rw-r--r--board/shmin/Makefile10
-rw-r--r--board/shmin/lowlevel_init.S21
-rw-r--r--board/shmin/shmin.c90
-rw-r--r--configs/mpr2_defconfig31
-rw-r--r--configs/ms7720se_defconfig36
-rw-r--r--configs/rsk7203_defconfig32
-rw-r--r--configs/rsk7264_defconfig15
-rw-r--r--configs/rsk7269_defconfig15
-rw-r--r--configs/shmin_defconfig31
-rw-r--r--doc/README.sh8
-rw-r--r--drivers/serial/serial_sh.c12
-rw-r--r--drivers/serial/serial_sh.h288
-rw-r--r--include/configs/mpr2.h55
-rw-r--r--include/configs/ms7720se.h82
-rw-r--r--include/configs/rsk7203.h63
-rw-r--r--include/configs/rsk7264.h52
-rw-r--r--include/configs/rsk7269.h51
-rw-r--r--include/configs/shmin.h85
-rw-r--r--scripts/config_whitelist.txt7
70 files changed, 17 insertions, 3214 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index a5772da87a..0ce74cf24a 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -1,16 +1,6 @@
menu "SuperH architecture"
depends on SH
-config CPU_SH2
- bool
-
-config CPU_SH2A
- bool
- select CPU_SH2
-
-config CPU_SH3
- bool
-
config CPU_SH4
bool
@@ -31,30 +21,6 @@ choice
prompt "Target select"
optional
-config TARGET_RSK7203
- bool "RSK+ 7203"
- select CPU_SH2A
-
-config TARGET_RSK7264
- bool "RSK2+SH7264"
- select CPU_SH2A
-
-config TARGET_RSK7269
- bool "RSK2+SH7269"
- select CPU_SH2A
-
-config TARGET_MPR2
- bool "Magic Panel Release 2 board"
- select CPU_SH3
-
-config TARGET_MS7720SE
- bool "Support ms7720se"
- select CPU_SH3
-
-config TARGET_SHMIN
- bool "SHMIN"
- select CPU_SH3
-
config TARGET_ESPT
bool "Data Technology ESPT-GIGA board"
select CPU_SH4
@@ -113,16 +79,12 @@ config SYS_ARCH
default "sh"
config SYS_CPU
- default "sh2" if CPU_SH2
- default "sh3" if CPU_SH3
default "sh4" if CPU_SH4
source "arch/sh/lib/Kconfig"
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/espt/Kconfig"
-source "board/mpr2/Kconfig"
-source "board/ms7720se/Kconfig"
source "board/ms7722se/Kconfig"
source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig"
@@ -130,13 +92,9 @@ source "board/renesas/ap325rxa/Kconfig"
source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
-source "board/renesas/rsk7203/Kconfig"
-source "board/renesas/rsk7264/Kconfig"
-source "board/renesas/rsk7269/Kconfig"
source "board/renesas/sh7752evb/Kconfig"
source "board/renesas/sh7753evb/Kconfig"
source "board/renesas/sh7757lcr/Kconfig"
source "board/renesas/sh7763rdp/Kconfig"
-source "board/shmin/Kconfig"
endmenu
diff --git a/arch/sh/cpu/sh2/Makefile b/arch/sh/cpu/sh2/Makefile
deleted file mode 100644
index 1220facc55..0000000000
--- a/arch/sh/cpu/sh2/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-# Copyright (C) 2008 Renesas Solutions Corp.
-
-obj-y = cpu.o interrupts.o watchdog.o
diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk
deleted file mode 100644
index 931964a726..0000000000
--- a/arch/sh/cpu/sh2/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2007-2008
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-ENDIANNESS += -EB
-
-ifdef CONFIG_CPU_SH2A
-PLATFORM_CPPFLAGS += -m2a-nofpu -mb
-else # SH2
-PLATFORM_CPPFLAGS += -m3e -mb
-endif
-PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic)
-
-PLATFORM_LDFLAGS += $(ENDIANNESS)
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
deleted file mode 100644
index a55adfb58b..0000000000
--- a/arch/sh/cpu/sh2/cpu.c
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#define STBCR4 0xFFFE040C
-#define cmt_clock_enable() do {\
- writeb(readb(STBCR4) & ~0x04, STBCR4);\
- } while (0)
-#define scif0_enable() do {\
- writeb(readb(STBCR4) & ~0x80, STBCR4);\
- } while (0)
-#define scif3_enable() do {\
- writeb(readb(STBCR4) & ~0x10, STBCR4);\
- } while (0)
-
-int checkcpu(void)
-{
- puts("CPU: SH2\n");
- return 0;
-}
-
-int cpu_init(void)
-{
- /* SCIF enable */
-#if defined(CONFIG_CONS_SCIF3)
- scif3_enable();
-#else
- scif0_enable();
-#endif
- /* CMT clock enable */
- cmt_clock_enable() ;
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- disable_interrupts();
- return 0;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- reset_cpu(0);
- return 0;
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-
-}
-
-void icache_enable(void)
-{
-}
-
-void icache_disable(void)
-{
-}
-
-int icache_status(void)
-{
- return 0;
-}
-
-void dcache_enable(void)
-{
-}
-
-void dcache_disable(void)
-{
-}
-
-int dcache_status(void)
-{
- return 0;
-}
diff --git a/arch/sh/cpu/sh2/interrupts.c b/arch/sh/cpu/sh2/interrupts.c
deleted file mode 100644
index a5ee41efb9..0000000000
--- a/arch/sh/cpu/sh2/interrupts.c
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-void enable_interrupts(void)
-{
-
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
diff --git a/arch/sh/cpu/sh2/watchdog.c b/arch/sh/cpu/sh2/watchdog.c
deleted file mode 100644
index 28240edf19..0000000000
--- a/arch/sh/cpu/sh2/watchdog.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008,2010 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2008,2010 Renesas Solutions Corp.
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-
-int watchdog_init(void)
-{
- return 0;
-}
-
-void reset_cpu(unsigned long ignored)
-{
- /* Address error with SR.BL=1 first. */
- trigger_address_error();
-
- while (1)
- ;
-}
diff --git a/arch/sh/cpu/sh3/Makefile b/arch/sh/cpu/sh3/Makefile
deleted file mode 100644
index 24aca92890..0000000000
--- a/arch/sh/cpu/sh3/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# (C) Copyright 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-
-obj-y = cpu.o interrupts.o watchdog.o
diff --git a/arch/sh/cpu/sh3/config.mk b/arch/sh/cpu/sh3/config.mk
deleted file mode 100644
index e13ee129da..0000000000
--- a/arch/sh/cpu/sh3/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# (C) Copyright 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-PLATFORM_CPPFLAGS += -m3
diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c
deleted file mode 100644
index 98121c72ba..0000000000
--- a/arch/sh/cpu/sh3/cpu.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-
-int checkcpu(void)
-{
- puts("CPU: SH3\n");
- return 0;
-}
-
-int cpu_init(void)
-{
- return 0;
-}
-
-int cleanup_before_linux(void)
-{
- disable_interrupts();
- return 0;
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- disable_interrupts();
- reset_cpu(0);
- return 0;
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
-
-}
-
-void icache_enable(void)
-{
-}
-
-void icache_disable(void)
-{
-}
-
-int icache_status(void)
-{
- return 0;
-}
-
-void dcache_enable(void)
-{
-}
-
-void dcache_disable(void)
-{
-}
-
-int dcache_status(void)
-{
- return 0;
-}
diff --git a/arch/sh/cpu/sh3/interrupts.c b/arch/sh/cpu/sh3/interrupts.c
deleted file mode 100644
index 144505a674..0000000000
--- a/arch/sh/cpu/sh3/interrupts.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <common.h>
-
-int interrupt_init(void)
-{
- return 0;
-}
-
-void enable_interrupts(void)
-{
-
-}
-
-int disable_interrupts(void)
-{
- return 0;
-}
diff --git a/arch/sh/cpu/sh3/watchdog.c b/arch/sh/cpu/sh3/watchdog.c
deleted file mode 100644
index 40bb33e48e..0000000000
--- a/arch/sh/cpu/sh3/watchdog.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- *
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-
-int watchdog_init(void)
-{
- return 0;
-}
-
-void reset_cpu(unsigned long ignored)
-{
- /* Address error with SR.BL=1 first. */
- trigger_address_error();
-
- while (1)
- ;
-}
diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
index d2862df4a5..df38c82abc 100644
--- a/arch/sh/include/asm/config.h
+++ b/arch/sh/include/asm/config.h
@@ -6,13 +6,11 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#if !defined(CONFIG_CPU_SH2)
#include <asm/processor.h>
/* Timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0x8) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
-#endif
#endif
diff --git a/arch/sh/include/asm/cpu_sh2.h b/arch/sh/include/asm/cpu_sh2.h
deleted file mode 100644
index d98bedd625..0000000000
--- a/arch/sh/include/asm/cpu_sh2.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#ifndef _ASM_CPU_SH2_H_
-#define _ASM_CPU_SH2_H_
-
-/* cache control */
-#define CCR_CACHE_STOP 0x00000008
-#define CCR_CACHE_ENABLE 0x00000005
-#define CCR_CACHE_ICI 0x00000008
-
-#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
-#define CACHE_OC_WAY_SHIFT 13
-#define CACHE_OC_NUM_ENTRIES 256
-#define CACHE_OC_ENTRY_SHIFT 4
-
-#if defined(CONFIG_CPU_SH7203)
-# include <asm/cpu_sh7203.h>
-#elif defined(CONFIG_CPU_SH7264)
-# include <asm/cpu_sh7264.h>
-#elif defined(CONFIG_CPU_SH7269)
-# include <asm/cpu_sh7269.h>
-#else
-# error "Unknown SH2 variant"
-#endif
-
-#endif /* _ASM_CPU_SH2_H_ */
diff --git a/arch/sh/include/asm/cpu_sh3.h b/arch/sh/include/asm/cpu_sh3.h
deleted file mode 100644
index a5d3ff7b60..0000000000
--- a/arch/sh/include/asm/cpu_sh3.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#ifndef _ASM_CPU_SH3_H_
-#define _ASM_CPU_SH3_H_
-
-/* cache control */
-#define CCR_CACHE_STOP 0x00000008
-#define CCR_CACHE_ENABLE 0x00000005
-#define CCR_CACHE_ICI 0x00000008
-
-#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
-#define CACHE_OC_WAY_SHIFT 13
-#define CACHE_OC_NUM_ENTRIES 256
-#define CACHE_OC_ENTRY_SHIFT 4
-
-#if defined(CONFIG_CPU_SH7706)
-#include <asm/cpu_sh7706.h>
-#elif defined(CONFIG_CPU_SH7710)
-#include <asm/cpu_sh7710.h>
-#elif defined(CONFIG_CPU_SH7720)
-#include <asm/cpu_sh7720.h>
-#else
-#error "Unknown SH3 variant"
-#endif
-
-#endif /* _ASM_CPU_SH3_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7203.h b/arch/sh/include/asm/cpu_sh7203.h
deleted file mode 100644
index 77dcac43d3..0000000000
--- a/arch/sh/include/asm/cpu_sh7203.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _ASM_CPU_SH7203_H_
-#define _ASM_CPU_SH7203_H_
-
-/* Cache */
-#define CCR1 0xFFFC1000
-#define CCR CCR1
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-
-/* SDRAM controller */
-
-/* SCIF */
-#define SCSMR_0 0xFFFE8000
-#define SCIF0_BASE SCSMR_0
-
-/* Timer(CMT) */
-#define CMSTR 0xFFFEC000
-#define CMCSR_0 0xFFFEC002
-#define CMCNT_0 0xFFFEC004
-#define CMCOR_0 0xFFFEC006
-#define CMCSR_1 0xFFFEC008
-#define CMCNT_1 0xFFFEC00A
-#define CMCOR_1 0xFFFEC00C
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7203_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7264.h b/arch/sh/include/asm/cpu_sh7264.h
deleted file mode 100644
index a4a4d51597..0000000000
--- a/arch/sh/include/asm/cpu_sh7264.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _ASM_CPU_SH7264_H_
-#define _ASM_CPU_SH7264_H_
-
-/* Cache */
-#define CCR1 0xFFFC1000
-#define CCR CCR1
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-
-/* SDRAM controller */
-
-/* SCIF */
-#define SCSMR_3 0xFFFE9800
-#define SCIF3_BASE SCSMR_3
-
-/* Timer(CMT) */
-#define CMSTR 0xFFFEC000
-#define CMCSR_0 0xFFFEC002
-#define CMCNT_0 0xFFFEC004
-#define CMCOR_0 0xFFFEC006
-#define CMCSR_1 0xFFFEC008
-#define CMCNT_1 0xFFFEC00A
-#define CMCOR_1 0xFFFEC00C
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7264_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7269.h b/arch/sh/include/asm/cpu_sh7269.h
deleted file mode 100644
index 4dea7086d4..0000000000
--- a/arch/sh/include/asm/cpu_sh7269.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef _ASM_CPU_SH7269_H_
-#define _ASM_CPU_SH7269_H_
-
-/* Cache */
-#define CCR1 0xFFFC1000
-#define CCR CCR1
-
-/* SCIF */
-#define SCSMR_0 0xE8007000
-#define SCIF0_BASE SCSMR_0
-#define SCSMR_1 0xE8007800
-#define SCIF1_BASE SCSMR_1
-#define SCSMR_2 0xE8008000
-#define SCIF2_BASE SCSMR_2
-#define SCSMR_3 0xE8008800
-#define SCIF3_BASE SCSMR_3
-#define SCSMR_7 0xE800A800
-#define SCIF7_BASE SCSMR_7
-
-/* Timer(CMT) */
-#define CMSTR 0xFFFEC000
-#define CMCSR_0 0xFFFEC002
-#define CMCNT_0 0xFFFEC004
-#define CMCOR_0 0xFFFEC006
-
-#endif /* _ASM_CPU_SH7269_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h
deleted file mode 100644
index 8066ff719b..0000000000
--- a/arch/sh/include/asm/cpu_sh7706.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef _ASM_CPU_SH7706_H_
-#define _ASM_CPU_SH7706_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000D
-
-/* MMU and Cache control */
-#define MMUCR 0xFFFFFFE0
-#define CCR 0xFFFFFFEC
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-#define FRQCR 0xffffff80
-#define BCR1 0xffffff60
-#define BCR2 0xffffff62
-#define WCR1 0xffffff64
-#define WCR2 0xffffff66
-#define MCR 0xffffff68
-
-/* SDRAM controller */
-#define DCR 0xffffff6a
-#define RTCSR 0xffffff6e
-#define RTCNT 0xffffff70
-#define RTCOR 0xffffff72
-#define RFCR 0xffffff74
-#define SDMR 0xFFFFD000
-#define CS3_R 0xFFFFE460
-
-/* SCIF */
-#define SCSMR_2 0xA4000150
-#define SCIF0_BASE SCSMR_2
-
-/* Timer */
-#define TMU_BASE 0xFFFFFE90
-
-/* On chip oscillator circuits */
-#define WTCNT 0xFFFFFF84
-#define WTCSR 0xFFFFFF86
-
-#endif /* _ASM_CPU_SH7706_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7710.h b/arch/sh/include/asm/cpu_sh7710.h
deleted file mode 100644
index e4ecef7f70..0000000000
--- a/arch/sh/include/asm/cpu_sh7710.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef _ASM_CPU_SH7710_H_
-#define _ASM_CPU_SH7710_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000D
-
-/* MMU and Cache control */
-#define MMUCR 0xFFFFFFE0
-#define CCR 0xFFFFFFEC
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PETCR 0xA4050106
-
-/* Port Data Registers */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-
-/* BSC */
-#define CMNCR 0xA4FD0000
-#define CS0BCR 0xA4FD0004
-#define CS2BCR 0xA4FD0008
-#define CS3BCR 0xA4FD000C
-#define CS4BCR 0xA4FD0010
-#define CS5ABCR 0xA4FD0014
-#define CS5BBCR 0xA4FD0018
-#define CS6ABCR 0xA4FD001C
-#define CS6BBCR 0xA4FD0020
-#define CS0WCR 0xA4FD0024
-#define CS2WCR 0xA4FD0028
-#define CS3WCR 0xA4FD002C
-#define CS4WCR 0xA4FD0030
-#define CS5AWCR 0xA4FD0034
-#define CS5BWCR 0xA4FD0038
-#define CS6AWCR 0xA4FD003C
-#define CS6BWCR 0xA4FD0040
-
-/* SDRAM controller */
-#define SDCR 0xA4FD0044
-#define RTCSR 0xA4FD0048
-#define RTCNT 0xA4FD004C
-#define RTCOR 0xA4FD0050
-
-/* SCIF */
-#define SCSMR_0 0xA4400000
-#define SCIF0_BASE SCSMR_0
-#define SCSMR_0 0xA4410000
-#define SCIF1_BASE SCSMR_1
-
-/* Timer */
-#define TMU_BASE 0xA412FE90
-
-/* On chip oscillator circuits */
-#define FRQCR 0xA415FF80
-#define WTCNT 0xA415FF84
-#define WTCSR 0xA415FF86
-
-#endif /* _ASM_CPU_SH7710_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7720.h b/arch/sh/include/asm/cpu_sh7720.h
deleted file mode 100644
index 5c361acdcb..0000000000
--- a/arch/sh/include/asm/cpu_sh7720.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007 (C)
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright 2008 (C)
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * SH7720 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7720_H_
-#define _ASM_CPU_SH7720_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000000B
-
-/* EXP */
-#define TRA 0xFFFFFFD0
-#define EXPEVT 0xFFFFFFD4
-#define INTEVT 0xFFFFFFD8
-
-/* MMU */
-#define MMUCR 0xFFFFFFE0
-#define PTEH 0xFFFFFFF0
-#define PTEL 0xFFFFFFF4
-#define TTB 0xFFFFFFF8
-
-/* CACHE */
-#define CCR 0xFFFFFFEC
-
-/* INTC */
-#define IPRF 0xA4080000
-#define IPRG 0xA4080002
-#define IPRH 0xA4080004
-#define IPRI 0xA4080006
-#define IPRJ 0xA4080008
-#define IRR5 0xA4080020
-#define IRR6 0xA4080022
-#define IRR7 0xA4080024
-#define IRR8 0xA4080026
-#define IRR9 0xA4080028
-#define IRR0 0xA4140004
-#define IRR1 0xA4140006
-#define IRR2 0xA4140008
-#define IRR3 0xA414000A
-#define IRR4 0xA414000C
-#define ICR1 0xA4140010
-#define ICR2 0xA4140012
-#define PINTER 0xA4140014
-#define IPRC 0xA4140016
-#define IPRD 0xA4140018
-#define IPRE 0xA414001A
-#define ICR0 0xA414FEE0
-#define IPRA 0xA414FEE2
-#define IPRB 0xA414FEE4
-
-/* BSC */
-#define BSC_BASE 0xA4FD0000
-#define CMNCR (BSC_BASE + 0x00)
-#define CS0BCR (BSC_BASE + 0x04)
-#define CS2BCR (BSC_BASE + 0x08)
-#define CS3BCR (BSC_BASE + 0x0C)
-#define CS4BCR (BSC_BASE + 0x10)
-#define CS5ABCR (BSC_BASE + 0x14)
-#define CS5BBCR (BSC_BASE + 0x18)
-#define CS6ABCR (BSC_BASE + 0x1C)
-#define CS6BBCR (BSC_BASE + 0x20)
-#define CS0WCR (BSC_BASE + 0x24)
-#define CS2WCR (BSC_BASE + 0x28)
-#define CS3WCR (BSC_BASE + 0x2C)
-#define CS4WCR (BSC_BASE + 0x30)
-#define CS5AWCR (BSC_BASE + 0x34)
-#define CS5BWCR (BSC_BASE + 0x38)
-#define CS6AWCR (BSC_BASE + 0x3C)
-#define CS6BWCR (BSC_BASE + 0x40)
-#define SDCR (BSC_BASE + 0x44)
-#define RTCSR (BSC_BASE + 0x48)
-#define RTCNR (BSC_BASE + 0x4C)
-#define RTCOR (BSC_BASE + 0x50)
-#define SDMR2 (BSC_BASE + 0x4000)
-#define SDMR3 (BSC_BASE + 0x5000)
-
-/* DMAC */
-
-/* CPG */
-#define UCLKCR 0xA40A0008
-#define FRQCR 0xA415FF80
-
-/* LOW POWER MODE */
-
-/* TMU */
-#define TMU_BASE 0xA412FE90
-
-/* TPU */
-#define TPU_BASE 0xA4480000
-#define TPU_TSTR (TPU_BASE + 0x00)
-#define TPU_TCR0 (TPU_BASE + 0x10)
-#define TPU_TMDR0 (TPU_BASE + 0x14)
-#define TPU_TIOR0 (TPU_BASE + 0x18)
-#define TPU_TIER0 (TPU_BASE + 0x1C)
-#define TPU_TSR0 (TPU_BASE + 0x20)
-#define TPU_TCNT0 (TPU_BASE + 0x24)
-#define TPU_TGRA0 (TPU_BASE + 0x28)
-#define TPU_TGRB0 (TPU_BASE + 0x2C)
-#define TPU_TGRC0 (TPU_BASE + 0x30)
-#define TPU_TGRD0 (TPU_BASE + 0x34)
-#define TPU_TCR1 (TPU_BASE + 0x50)
-#define TPU_TMDR1 (TPU_BASE + 0x54)
-#define TPU_TIOR1 (TPU_BASE + 0x58)
-#define TPU_TIER1 (TPU_BASE + 0x5C)
-#define TPU_TSR1 (TPU_BASE + 0x60)
-#define TPU_TCNT1 (TPU_BASE + 0x64)
-#define TPU_TGRA1 (TPU_BASE + 0x68)
-#define TPU_TGRB1 (TPU_BASE + 0x6C)
-#define TPU_TGRC1 (TPU_BASE + 0x70)
-#define TPU_TGRD1 (TPU_BASE + 0x74)
-#define TPU_TCR2 (TPU_BASE + 0x90)
-#define TPU_TMDR2 (TPU_BASE + 0x94)
-#define TPU_TIOR2 (TPU_BASE + 0x98)
-#define TPU_TIER2 (TPU_BASE + 0x9C)
-#define TPU_TSR2 (TPU_BASE + 0xB0)
-#define TPU_TCNT2 (TPU_BASE + 0xB4)
-#define TPU_TGRA2 (TPU_BASE + 0xB8)
-#define TPU_TGRB2 (TPU_BASE + 0xBC)
-#define TPU_TGRC2 (TPU_BASE + 0xC0)
-#define TPU_TGRD2 (TPU_BASE + 0xC4)
-#define TPU_TCR3 (TPU_BASE + 0xD0)
-#define TPU_TMDR3 (TPU_BASE + 0xD4)
-#define TPU_TIOR3 (TPU_BASE + 0xD8)
-#define TPU_TIER3 (TPU_BASE + 0xDC)
-#define TPU_TSR3 (TPU_BASE + 0xE0)
-#define TPU_TCNT3 (TPU_BASE + 0xE4)
-#define TPU_TGRA3 (TPU_BASE + 0xE8)
-#define TPU_TGRB3 (TPU_BASE + 0xEC)
-#define TPU_TGRC3 (TPU_BASE + 0xF0)
-#define TPU_TGRD3 (TPU_BASE + 0xF4)
-
-/* CMT */
-
-/* SIOF */
-
-/* SCIF */
-#define SCIF0_BASE 0xA4430000
-
-/* SIM */
-
-/* IrDA */
-
-/* IIC */
-
-/* LCDC */
-
-/* USBF */
-
-/* MMCIF */
-
-/* PFC */
-#define PFC_BASE 0xA4050100
-#define PACR (PFC_BASE + 0x00)
-#define PBCR (PFC_BASE + 0x02)
-#define PCCR (PFC_BASE + 0x04)
-#define PDCR (PFC_BASE + 0x06)
-#define PECR (PFC_BASE + 0x08)
-#define PFCR (PFC_BASE + 0x0A)
-#define PGCR (PFC_BASE + 0x0C)
-#define PHCR (PFC_BASE + 0x0E)
-#define PJCR (PFC_BASE + 0x10)
-#define PKCR (PFC_BASE + 0x12)
-#define PLCR (PFC_BASE + 0x14)
-#define PMCR (PFC_BASE + 0x16)
-#define PPCR (PFC_BASE + 0x18)
-#define PRCR (PFC_BASE + 0x1A)
-#define PSCR (PFC_BASE + 0x1C)
-#define PTCR (PFC_BASE + 0x1E)
-#define PUCR (PFC_BASE + 0x20)
-#define PVCR (PFC_BASE + 0x22)
-#define PSELA (PFC_BASE + 0x24)
-#define PSELB (PFC_BASE + 0x26)
-#define PSELC (PFC_BASE + 0x28)
-#define PSELD (PFC_BASE + 0x2A)
-
-/* I/O Port */
-#define PORT_BASE 0xA4050100
-#define PADR (PORT_BASE + 0x40)
-#define PBDR (PORT_BASE + 0x42)
-#define PCDR (PORT_BASE + 0x44)
-#define PDDR (PORT_BASE + 0x46)
-#define PEDR (PORT_BASE + 0x48)
-#define PFDR (PORT_BASE + 0x4A)
-#define PGDR (PORT_BASE + 0x4C)
-#define PHDR (PORT_BASE + 0x4E)
-#define PJDR (PORT_BASE + 0x50)
-#define PKDR (PORT_BASE + 0x52)
-#define PLDR (PORT_BASE + 0x54)
-#define PMDR (PORT_BASE + 0x56)
-#define PPDR (PORT_BASE + 0x58)
-#define PRDR (PORT_BASE + 0x5A)
-#define PSDR (PORT_BASE + 0x5C)
-#define PTDR (PORT_BASE + 0x5E)
-#define PUDR (PORT_BASE + 0x60)
-#define PVDR (PORT_BASE + 0x62)
-
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7720_H_ */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index b07fe542e3..09de94a2e2 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -1,10 +1,4 @@
#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
-#if defined(CONFIG_CPU_SH2)
-# include <asm/cpu_sh2.h>
-#elif defined(CONFIG_CPU_SH3)
-# include <asm/cpu_sh3.h>
-#elif defined(CONFIG_CPU_SH4)
# include <asm/cpu_sh4.h>
#endif
-#endif
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index 4171e2b0b8..9618da1cb3 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -7,17 +7,12 @@ extra-y += start.o
obj-y += board.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
-ifeq ($(CONFIG_CPU_SH2),y)
-obj-y += time_sh2.o
-else
obj-y += time.o
-endif
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
udivsi3-y := udivsi3_i4i-Os.o
ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y)
-udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o
udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o
endif
udivsi3-y += udivsi3.o
diff --git a/arch/sh/lib/start.S b/arch/sh/lib/start.S
index ee79b4fdd0..f5350b9064 100644
--- a/arch/sh/lib/start.S
+++ b/arch/sh/lib/start.S
@@ -12,12 +12,6 @@
.global _start
_start:
-#ifdef CONFIG_CPU_SH2
- .long 0x00000010 /* Ppower ON reset PC*/
- .long 0x00000000
- .long 0x00000010 /* Manual reset PC */
- .long 0x00000000
-#endif
mov.l ._lowlevel_init, r0
100: bsrf r0
nop
diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index fb317f95d5..51e1cc1181 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -14,11 +14,6 @@
#include <asm/processor.h>
#include <asm/io.h>
-#if defined(CONFIG_CPU_SH3)
-#define TSTR 0x2
-#define TCR0 0xc
-#endif /* CONFIG_CPU_SH3 */
-
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
#define TSTR 0x4
#define TCR0 0x10
diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig
deleted file mode 100644
index 54176e8f6f..0000000000
--- a/board/mpr2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MPR2
-
-config SYS_BOARD
- default "mpr2"
-
-config SYS_CONFIG_NAME
- default "mpr2"
-
-endif
diff --git a/board/mpr2/MAINTAINERS b/board/mpr2/MAINTAINERS
deleted file mode 100644
index beedf8dda6..0000000000
--- a/board/mpr2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPR2 BOARD
-M: Mark Jonas <mark.jonas@de.bosch.com>
-S: Maintained
-F: board/mpr2/
-F: include/configs/mpr2.h
-F: configs/mpr2_defconfig
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
deleted file mode 100644
index 6a71803ac7..0000000000
--- a/board/mpr2/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# (C) Copyright 2008
-# Mark Jonas <mark.jonas@de.bosch.com>
-#
-# board/mpr2/Makefile
-#
-
-obj-y := mpr2.o
-extra-y += lowlevel_init.o
diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S
deleted file mode 100644
index e34a7a9a17..0000000000
--- a/board/mpr2/lowlevel_init.S
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * board/mpr2/lowlevel_init.S
- */
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
-/*
- * Set frequency multipliers and dividers in FRQCR.
- */
- write16 WTCSR_A, WTCSR_D
-
- write16 WTCNT_A, WTCNT_D
-
- write16 FRQCR_A, FRQCR_D
-
-/*
- * Setup CS0 (Flash).
- */
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
-/*
- * Setup CS3 (SDRAM).
- */
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 SDCR_A, SDCR_D1
-
- write32 RTCSR_A, RTCSR_D
-
- write32 RTCNT_A, RTCNT_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 SDCR_A, SDCR_D2
-
- mov.l SDMR3_A, r1
- mov.l SDMR3_D, r0
- add r0, r1
- mov #0, r0
- mov.w r0, @r1
-
- rts
- nop
-
- .align 4
-
-/*
- * Configuration for MPR2 A.3 through A.7
- */
-
-/*
- * PLL Settings
- */
-FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
-WTCNT_D: .word 0x5A00 /* start counting at zero */
-WTCSR_D: .word 0xA507 /* divide by 4096 */
-.align 2
-/*
- * Spansion S29GL256N11 @ 48 MHz
- */
-/* 1 idle cycle inserted, normal space, 16 bit */
-CS0BCR_D: .long 0x12490400
-/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
-CS0WCR_D: .long 0x00000340
-
-/*
- * Samsung K4S511632B-UL75 @ 48 MHz
- * Micron MT48LC32M16A2-75 @ 48 MHz
- */
-/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
-CS3BCR_D: .long 0x10004400
-/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
-CS3WCR_D: .long 0x00000091
-/* no refresh, 13 rows, 10 cols, NO bank active mode */
-SDCR_D1: .long 0x00000012
-SDCR_D2: .long 0x00000812 /* refresh */
-RTCSR_D: .long 0xA55A0008 /* 1/4, once */
-RTCNT_D: .long 0xA55A005D /* count 93 */
-RTCOR_D: .long 0xa55a005d /* count 93 */
-/* mode register CL2, burst read and SINGLE WRITE */
-SDMR3_D: .long 0x440
-
-/*
- * Registers
- */
-
-FRQCR_A: .long 0xA415FF80
-WTCNT_A: .long 0xA415FF84
-WTCSR_A: .long 0xA415FF86
-
-#define BSC_BASE 0xA4FD0000
-CS0BCR_A: .long BSC_BASE + 0x04
-CS3BCR_A: .long BSC_BASE + 0x0C
-CS0WCR_A: .long BSC_BASE + 0x24
-CS3WCR_A: .long BSC_BASE + 0x2C
-SDCR_A: .long BSC_BASE + 0x44
-RTCSR_A: .long BSC_BASE + 0x48
-RTCNT_A: .long BSC_BASE + 0x4C
-RTCOR_A: .long BSC_BASE + 0x50
-SDMR3_A: .long BSC_BASE + 0x5000
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
deleted file mode 100644
index 9eb04907a4..0000000000
--- a/board/mpr2/mpr2.c
+++ /dev/null
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- *
- * board/mpr2/mpr2.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: MPR2\n");
- return 0;
-}
-
-int board_init(void)
-{
- /*
- * For MPR2 A.3 through A.7
- */
-
- /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
- __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */
- __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */
-
- /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
- __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
- /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
- __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
- /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
- __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-
- /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
- __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */
- __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
-
- /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
- __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */
-
- /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
- __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */
-
- /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
- __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */
-
- /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
- __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
-
- /* OTH: (00) Other fuction
- * GPO: (01) General Purpose Output
- * GPI: (11) General Purpose Input
- * GPI+: (10) General Purpose Input with internal pull-up
- *-------------------------------------------------------
- * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
- * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */
- __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */
-
- /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
- * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */
- __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */
-
- /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
- * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */
- __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */
-
- /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
- * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */
- __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */
-
- /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
- * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */
- __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */
-
- /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
- * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */
- __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */
-
- /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
- * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */
- __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */
-
- /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
- * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */
- __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */
-
- /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
- * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */
- __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */
-
- /* K7 (x); K6 (x); K5 (x); K4 (x)
- * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */
- __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */
-
- /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
- * L3 TCK; L2 (x); L1 (x); L0 (x); */
- __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */
-
- /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET);
- * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */
- __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */
- __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
-
- /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup);
- * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */
- __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */
- __raw_writeb(0x10, PPDR); /* no current flow through pullup */
-
- /* R7 A25; R6 A24; R5 A23; R4 A22;
- * R3 A21; R2 A20; R1 A19; R0 A0; */
- __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */
-
- /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
- * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */
- __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */
-
- /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
- * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */
- __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */
-
- /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
- * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */
- __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */
-
- /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
- * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */
- __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */
-
- return 0;
-}
diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig
deleted file mode 100644
index 83313279b3..0000000000
--- a/board/ms7720se/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MS7720SE
-
-config SYS_BOARD
- default "ms7720se"
-
-config SYS_CONFIG_NAME
- default "ms7720se"
-
-endif
diff --git a/board/ms7720se/MAINTAINERS b/board/ms7720se/MAINTAINERS
deleted file mode 100644
index 96a80f4e31..0000000000
--- a/board/ms7720se/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MS7720SE BOARD
-M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
-S: Maintained
-F: board/ms7720se/
-F: include/configs/ms7720se.h
-F: configs/ms7720se_defconfig
diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile
deleted file mode 100644
index d3a8e19d0b..0000000000
--- a/board/ms7720se/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007
-# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
-#
-# Copyright (C) 2007
-# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#
-# Copyright (C) 2007
-# Kenati Technologies, Inc.
-#
-# board/ms7720se/Makefile
-#
-
-obj-y := ms7720se.o
-extra-y += lowlevel_init.o
diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S
deleted file mode 100644
index 871d6a81d5..0000000000
--- a/board/ms7720se/lowlevel_init.S
+++ /dev/null
@@ -1,184 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- write16 WTCSR_A, WTCSR_D
-
- write16 WTCNT_A, WTCNT_D
-
- write16 FRQCR_A, FRQCR_D
-
- write16 UCLKCR_A, UCLKCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS2BCR_A, CS2BCR_D
-
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS4BCR_A, CS4BCR_D
-
- write32 CS5ABCR_A, CS5ABCR_D
-
- write32 CS5BBCR_A, CS5BBCR_D
-
- write32 CS6ABCR_A, CS6ABCR_D
-
- write32 CS6BBCR_A, CS6BBCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
- write32 CS2WCR_A, CS2WCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 CS4WCR_A, CS4WCR_D
-
- write32 CS5AWCR_A, CS5AWCR_D
-
- write32 CS5BWCR_A, CS5BWCR_D
-
- write32 CS6AWCR_A, CS6AWCR_D
-
- write32 CS6BWCR_A, CS6BWCR_D
-
- write32 SDCR_A, SDCR_D1
-
- write32 RTCSR_A, RTCSR_D
-
- write32 RTCNT_A RTCNT_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 SDCR_A, SDCR_D2
-
- write16 SDMR3_A, SDMR3_D
-
- write16 PCCR_A, PCCR_D
-
- write16 PDCR_A, PDCR_D
-
- write16 PECR_A, PECR_D
-
- write16 PGCR_A, PGCR_D
-
- write16 PHCR_A, PHCR_D
-
- write16 PPCR_A, PPCR_D
-
- write16 PTCR_A, PTCR_D
-
- write16 PVCR_A, PVCR_D
-
- write16 PSELA_A, PSELA_D
-
- write32 CCR_A, CCR_D
-
- write8 LED_A, LED_D
-
- rts
- nop
-
- .align 4
-
-FRQCR_A: .long 0xA415FF80 /* FRQCR Address */
-WTCNT_A: .long 0xA415FF84
-WTCSR_A: .long 0xA415FF86
-UCLKCR_A: .long 0xA40A0008
-FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
-WTCNT_D: .word 0x5A00
-WTCSR_D: .word 0xA506
-UCLKCR_D: .word 0xA5C0
-
-#define BSC_BASE 0xA4FD0000
-CMNCR_A: .long BSC_BASE
-CS0BCR_A: .long BSC_BASE + 0x04
-CS2BCR_A: .long BSC_BASE + 0x08
-CS3BCR_A: .long BSC_BASE + 0x0C
-CS4BCR_A: .long BSC_BASE + 0x10
-CS5ABCR_A: .long BSC_BASE + 0x14
-CS5BBCR_A: .long BSC_BASE + 0x18
-CS6ABCR_A: .long BSC_BASE + 0x1C
-CS6BBCR_A: .long BSC_BASE + 0x20
-CS0WCR_A: .long BSC_BASE + 0x24
-CS2WCR_A: .long BSC_BASE + 0x28
-CS3WCR_A: .long BSC_BASE + 0x2C
-CS4WCR_A: .long BSC_BASE + 0x30
-CS5AWCR_A: .long BSC_BASE + 0x34
-CS5BWCR_A: .long BSC_BASE + 0x38
-CS6AWCR_A: .long BSC_BASE + 0x3C
-CS6BWCR_A: .long BSC_BASE + 0x40
-SDCR_A: .long BSC_BASE + 0x44
-RTCSR_A: .long BSC_BASE + 0x48
-RTCNT_A: .long BSC_BASE + 0x4C
-RTCOR_A: .long BSC_BASE + 0x50
-SDMR3_A: .long BSC_BASE + 0x58C0
-
-CMNCR_D: .long 0x00000010
-CS0BCR_D: .long 0x36DB0400
-CS2BCR_D: .long 0x36DB0400
-CS3BCR_D: .long 0x36DB4600
-CS4BCR_D: .long 0x36DB0400
-CS5ABCR_D: .long 0x36DB0400
-CS5BBCR_D: .long 0x36DB0200
-CS6ABCR_D: .long 0x36DB0400
-CS6BBCR_D: .long 0x36DB0400
-CS0WCR_D: .long 0x00000B01
-CS2WCR_D: .long 0x00000500
-CS3WCR_D: .long 0x00006D1B
-CS4WCR_D: .long 0x00000500
-CS5AWCR_D: .long 0x00000500
-CS5BWCR_D: .long 0x00000500
-CS6AWCR_D: .long 0x00000500
-CS6BWCR_D: .long 0x00000500
-SDCR_D1: .long 0x00000011
-RTCSR_D: .long 0xA55A0010
-RTCNT_D: .long 0xA55A001F
-RTCOR_D: .long 0xA55A001F
-SDMR3_D: .word 0x0000
-.align 2
-SDCR_D2: .long 0x00000811
-
-#define PFC_BASE 0xA4050100
-PCCR_A: .long PFC_BASE + 0x04
-PDCR_A: .long PFC_BASE + 0x06
-PECR_A: .long PFC_BASE + 0x08
-PGCR_A: .long PFC_BASE + 0x0C
-PHCR_A: .long PFC_BASE + 0x0E
-PPCR_A: .long PFC_BASE + 0x18
-PTCR_A: .long PFC_BASE + 0x1E
-PVCR_A: .long PFC_BASE + 0x22
-PSELA_A: .long PFC_BASE + 0x24
-
-PCCR_D: .word 0x0000
-PDCR_D: .word 0x0000
-PECR_D: .word 0x0000
-PGCR_D: .word 0x0000
-PHCR_D: .word 0x0000
-PPCR_D: .word 0x00AA
-PTCR_D: .word 0x0280
-PVCR_D: .word 0x0000
-PSELA_D: .word 0x0000
-.align 2
-
-CCR_A: .long 0xFFFFFFEC
-!CCR_D: .long 0x0000000D
-CCR_D: .long 0x0000000B
-
-LED_A: .long 0xB6800000
-LED_D: .long 0xFF
diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c
deleted file mode 100644
index a35f72e83b..0000000000
--- a/board/ms7720se/ms7720se.c
+++ /dev/null
@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007
- * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- *
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2007
- * Kenati Technologies, Inc.
- *
- * board/ms7720se/ms7720se.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-#define LED_BASE 0xB0800000
-
-int checkboard(void)
-{
- puts("BOARD: Hitachi UL MS7720SE\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
- outw(value & 0xFF, LED_BASE);
-}
diff --git a/board/renesas/rsk7203/Kconfig b/board/renesas/rsk7203/Kconfig
deleted file mode 100644
index 10b8786411..0000000000
--- a/board/renesas/rsk7203/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_RSK7203
-
-config SYS_BOARD
- default "rsk7203"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7203"
-
-endif
diff --git a/board/renesas/rsk7203/MAINTAINERS b/board/renesas/rsk7203/MAINTAINERS
deleted file mode 100644
index 18d36634cf..0000000000
--- a/board/renesas/rsk7203/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-RSK7203 BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/rsk7203/
-F: include/configs/rsk7203.h
-F: configs/rsk7203_defconfig
diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile
deleted file mode 100644
index 545079e99e..0000000000
--- a/board/renesas/rsk7203/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
-# Copyright (C) 2008 Renesas Solutions Corp.
-#
-# u-boot/board/rsk7203/Makefile
-#
-
-obj-y := rsk7203.o
-extra-y += lowlevel_init.o
diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S
deleted file mode 100644
index f82dd7dc05..0000000000
--- a/board/renesas/rsk7203/lowlevel_init.S
+++ /dev/null
@@ -1,199 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Cache setting */
- write32 CCR1_A ,CCR1_D
-
- /* ConfigurePortPins */
- write16 PECRL3_A, PECRL3_D
-
- write16 PCCRL4_A, PCCRL4_D0
-
- write16 PECRL4_A, PECRL4_D0
-
- write16 PEIORL_A, PEIORL_D0
-
- write16 PCIORL_A, PCIORL_D
-
- write16 PFCRH2_A, PFCRH2_D
-
- write16 PFCRH3_A, PFCRH3_D
-
- write16 PFCRH1_A, PFCRH1_D
-
- write16 PFIORH_A, PFIORH_D
-
- write16 PECRL1_A, PECRL1_D0
-
- write16 PEIORL_A, PEIORL_D1
-
- /* Configure Operating Frequency */
- write16 WTCSR_A, WTCSR_D0
-
- write16 WTCSR_A, WTCSR_D1
-
- write16 WTCNT_A, WTCNT_D
-
- /* Set clock mode*/
- write16 FRQCR_A, FRQCR_D
-
- /* Configure Bus And Memory */
-init_bsc_cs0:
- write16 PCCRL4_A, PCCRL4_D1
-
- write16 PECRL1_A, PECRL1_D1
-
- write32 CMNCR_A, CMNCR_D
-
- write32 CS0BCR_A, CS0BCR_D
-
- write32 CS0WCR_A, CS0WCR_D
-
-init_bsc_cs1:
- write16 PECRL4_A, PECRL4_D1
-
- write32 CS1WCR_A, CS1WCR_D
-
-init_sdram:
- write16 PCCRL2_A, PCCRL2_D
-
- write16 PCCRL4_A, PCCRL4_D2
-
- write16 PCCRL1_A, PCCRL1_D
-
- write16 PCCRL3_A, PCCRL3_D
-
- write32 CS3BCR_A, CS3BCR_D
-
- write32 CS3WCR_A, CS3WCR_D
-
- write32 SDCR_A, SDCR_D
-
- write32 RTCOR_A, RTCOR_D
-
- write32 RTCSR_A, RTCSR_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-PCCRL4_A: .long 0xFFFE3910
-PCCRL4_D0: .word 0x0000
-.align 2
-PECRL4_A: .long 0xFFFE3A10
-PECRL4_D0: .word 0x0000
-.align 2
-PECRL3_A: .long 0xFFFE3A12
-PECRL3_D: .word 0x0000
-.align 2
-PEIORL_A: .long 0xFFFE3A06
-PEIORL_D0: .word 0x1C00
-PEIORL_D1: .word 0x1C02
-PCIORL_A: .long 0xFFFE3906
-PCIORL_D: .word 0x4000
-.align 2
-PFCRH2_A: .long 0xFFFE3A8C
-PFCRH2_D: .word 0x0000
-.align 2
-PFCRH3_A: .long 0xFFFE3A8A
-PFCRH3_D: .word 0x0000
-.align 2
-PFCRH1_A: .long 0xFFFE3A8E
-PFCRH1_D: .word 0x0000
-.align 2
-PFIORH_A: .long 0xFFFE3A84
-PFIORH_D: .word 0x0729
-.align 2
-PECRL1_A: .long 0xFFFE3A16
-PECRL1_D0: .word 0x0033
-.align 2
-
-
-WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .word 0xA518
-WTCSR_D1: .word 0xA51D
-WTCNT_A: .long 0xFFFE0002
-WTCNT_D: .word 0x5A84
-.align 2
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x0104
-.align 2
-
-PCCRL4_D1: .word 0x0010
-PECRL1_D1: .word 0x0133
-
-CMNCR_A: .long 0xFFFC0000
-CMNCR_D: .long 0x00001810
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x10000400
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000B41
-PECRL4_D1: .word 0x0100
-.align 2
-CS1WCR_A: .long 0xFFFC002C
-CS1WCR_D: .long 0x00000B01
-PCCRL4_D2: .word 0x0011
-.align 2
-PCCRL3_A: .long 0xFFFE3912
-PCCRL3_D: .word 0x0011
-.align 2
-PCCRL2_A: .long 0xFFFE3914
-PCCRL2_D: .word 0x1111
-.align 2
-PCCRL1_A: .long 0xFFFE3916
-PCCRL1_D: .word 0x1010
-.align 2
-PDCRL4_A: .long 0xFFFE3990
-PDCRL4_D: .word 0x0011
-.align 2
-PDCRL3_A: .long 0xFFFE3992
-PDCRL3_D: .word 0x00011
-.align 2
-PDCRL2_A: .long 0xFFFE3994
-PDCRL2_D: .word 0x1111
-.align 2
-PDCRL1_A: .long 0xFFFE3996
-PDCRL1_D: .word 0x1000
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x00002892
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000809
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0041
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xa55a0010
-
-SDRAM_MODE: .long 0xFFFC5040
-REPEAT_D: .long 0x00009C40
diff --git a/board/renesas/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c
deleted file mode 100644
index 780c1866be..0000000000
--- a/board/renesas/rsk7203/rsk7203.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- *
- * u-boot/board/rsk7203/rsk7203.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Technology RSK7203\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC9118 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/rsk7264/Kconfig
deleted file mode 100644
index 755d2896fb..0000000000
--- a/board/renesas/rsk7264/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_RSK7264
-
-config SYS_BOARD
- default "rsk7264"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7264"
-
-endif
diff --git a/board/renesas/rsk7264/MAINTAINERS b/board/renesas/rsk7264/MAINTAINERS
deleted file mode 100644
index f6202b70d9..0000000000
--- a/board/renesas/rsk7264/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RSK7264 BOARD
-M: Phil Edworthy <phil.edworthy@renesas.com>
-S: Maintained
-F: board/renesas/rsk7264/
-F: include/configs/rsk7264.h
-F: configs/rsk7264_defconfig
diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile
deleted file mode 100644
index 4efcf5cba9..0000000000
--- a/board/renesas/rsk7264/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Renesas Electronics Europe Ltd.
-#
-
-obj-y := rsk7264.o
-extra-y += lowlevel_init.o
diff --git a/board/renesas/rsk7264/lowlevel_init.S b/board/renesas/rsk7264/lowlevel_init.S
deleted file mode 100644
index 75c251b716..0000000000
--- a/board/renesas/rsk7264/lowlevel_init.S
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on board/renesas/rsk7203/lowlevel_init.S
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Cache setting */
- write32 CCR1_A ,CCR1_D
-
- /* io_set_cpg */
- write8 STBCR3_A, STBCR3_D
- write8 STBCR4_A, STBCR4_D
- write8 STBCR5_A, STBCR5_D
- write8 STBCR6_A, STBCR6_D
- write8 STBCR7_A, STBCR7_D
- write8 STBCR8_A, STBCR8_D
-
- /* ConfigurePortPins */
-
- /* Leaving LED1 ON for sanity test */
- write16 PJCR1_A, PJCR1_D1
- write16 PJCR2_A, PJCR2_D
- write16 PJIOR0_A, PJIOR0_D1
- write16 PJDR0_A, PJDR0_D
- write16 PJPR0_A, PJPR0_D
-
- /* Configure EN_PIN & RS_PIN */
- write16 PGCR2_A, PGCR2_D
- write16 PGIOR0_A, PGIOR0_D
-
- /* Configure the port pins connected to UART */
- write16 PJCR1_A, PJCR1_D2
- write16 PJIOR0_A, PJIOR0_D2
-
- /* Configure Operating Frequency */
- write16 WTCSR_A, WTCSR_D0
- write16 WTCSR_A, WTCSR_D1
- write16 WTCNT_A, WTCNT_D
-
- /* Control of RESBANK */
- write16 IBNR_A, IBNR_D
- /* Enable SCIF3 module */
- write16 STBCR4_A, STBCR4_D
-
- /* Set clock mode*/
- write16 FRQCR_A, FRQCR_D
-
- /* Configure Bus And Memory */
-init_bsc_cs0:
-
-pfc_settings:
- write16 PCCR2_A, PCCR2_D
- write16 PCCR1_A, PCCR1_D
- write16 PCCR0_A, PCCR0_D
-
- write16 PBCR0_A, PBCR0_D
- write16 PBCR1_A, PBCR1_D
- write16 PBCR2_A, PBCR2_D
- write16 PBCR3_A, PBCR3_D
- write16 PBCR4_A, PBCR4_D
- write16 PBCR5_A, PBCR5_D
-
- write16 PDCR0_A, PDCR0_D
- write16 PDCR1_A, PDCR1_D
- write16 PDCR2_A, PDCR2_D
- write16 PDCR3_A, PDCR3_D
-
- write32 CS0WCR_A, CS0WCR_D
- write32 CS0BCR_A, CS0BCR_D
-
-init_bsc_cs2:
- write16 PJCR0_A, PJCR0_D
- write32 CS2WCR_A, CS2WCR_D
-
-init_sdram:
- write32 CS3BCR_A, CS3BCR_D
- write32 CS3WCR_A, CS3WCR_D
- write32 SDCR_A, SDCR_D
- write32 RTCOR_A, RTCOR_D
- write32 RTCSR_A, RTCSR_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x1003
-.align 2
-STBCR3_A: .long 0xFFFE0408
-STBCR3_D: .long 0x00000002
-STBCR4_A: .long 0xFFFE040C
-STBCR4_D: .word 0x0000
-.align 2
-STBCR5_A: .long 0xFFFE0410
-STBCR5_D: .long 0x00000010
-STBCR6_A: .long 0xFFFE0414
-STBCR6_D: .long 0x00000002
-STBCR7_A: .long 0xFFFE0418
-STBCR7_D: .long 0x0000002A
-STBCR8_A: .long 0xFFFE041C
-STBCR8_D: .long 0x0000007E
-PJCR1_A: .long 0xFFFE390C
-PJCR1_D1: .word 0x0000
-PJCR1_D2: .word 0x0022
-PJCR2_A: .long 0xFFFE390A
-PJCR2_D: .word 0x0000
-.align 2
-PJIOR0_A: .long 0xFFFE3912
-PJIOR0_D1: .word 0x0FC0
-PJIOR0_D2: .word 0x0FE0
-PJDR0_A: .long 0xFFFE3916
-PJDR0_D: .word 0x0FBF
-.align 2
-PJPR0_A: .long 0xFFFE391A
-PJPR0_D: .long 0x00000FBF
-PGCR2_A: .long 0xFFFE38CA
-PGCR2_D: .word 0x0000
-.align 2
-PGIOR0_A: .long 0xFFFE38D2
-PGIOR0_D: .word 0x03F0
-.align 2
-WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .word 0x0000
-WTCSR_D1: .word 0x0000
-WTCNT_A: .long 0xFFFE0002
-WTCNT_D: .word 0x0000
-.align 2
-PCCR0_A: .long 0xFFFE384E
-PDCR0_A: .long 0xFFFE386E
-PDCR1_A: .long 0xFFFE386C
-PDCR2_A: .long 0xFFFE386A
-PDCR3_A: .long 0xFFFE3868
-PBCR0_A: .long 0xFFFE382E
-PBCR1_A: .long 0xFFFE382C
-PBCR2_A: .long 0xFFFE382A
-PBCR3_A: .long 0xFFFE3828
-PBCR4_A: .long 0xFFFE3826
-PBCR5_A: .long 0xFFFE3824
-PCCR0_D: .word 0x1111
-PDCR0_D: .word 0x1111
-PDCR1_D: .word 0x1111
-PDCR2_D: .word 0x1111
-PDCR3_D: .word 0x1111
-PBCR0_D: .word 0x1110
-PBCR1_D: .word 0x1111
-PBCR2_D: .word 0x1111
-PBCR3_D: .word 0x1111
-PBCR4_D: .word 0x1111
-PBCR5_D: .word 0x0111
-.align 2
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000B41
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x10000400
-PJCR0_A: .long 0xFFFE390E
-PJCR0_D: .word 0x3300
-.align 2
-CS2WCR_A: .long 0xFFFC0030
-CS2WCR_D: .long 0x00000B01
-PCCR2_A: .long 0xFFFE384A
-PCCR2_D: .word 0x0001
-.align 2
-PCCR1_A: .long 0xFFFE384C
-PCCR1_D: .word 0x1111
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x0000288A
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000812
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0046
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xA55A0010
-IBNR_A: .long 0xFFFE080E
-IBNR_D: .word 0x0000
-.align 2
-SDRAM_MODE: .long 0xFFFC5040
-REPEAT_D: .long 0x00000085
diff --git a/board/renesas/rsk7264/rsk7264.c b/board/renesas/rsk7264/rsk7264.c
deleted file mode 100644
index 8f3b157bf7..0000000000
--- a/board/renesas/rsk7264/rsk7264.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on u-boot/board/rsk7264/rsk7203.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas Technology RSK7264\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC89218 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/renesas/rsk7269/Kconfig b/board/renesas/rsk7269/Kconfig
deleted file mode 100644
index ab5cd0e38f..0000000000
--- a/board/renesas/rsk7269/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_RSK7269
-
-config SYS_BOARD
- default "rsk7269"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "rsk7269"
-
-endif
diff --git a/board/renesas/rsk7269/MAINTAINERS b/board/renesas/rsk7269/MAINTAINERS
deleted file mode 100644
index 698fbdb1df..0000000000
--- a/board/renesas/rsk7269/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-RSK7269 BOARD
-#M: -
-S: Maintained
-F: board/renesas/rsk7269/
-F: include/configs/rsk7269.h
-F: configs/rsk7269_defconfig
diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile
deleted file mode 100644
index c4371f99fb..0000000000
--- a/board/renesas/rsk7269/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2012 Renesas Electronics Europe Ltd.
-# Copyright (C) 2012 Phil Edworthy
-#
-
-obj-y := rsk7269.o
-extra-y += lowlevel_init.o
diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S
deleted file mode 100644
index b7ce60b46d..0000000000
--- a/board/renesas/rsk7269/lowlevel_init.S
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Renesas Electronics Europe Ltd.
- * Copyright (C) 2012 Phil Edworthy
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on board/renesas/rsk7264/lowlevel_init.S
- */
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Flush and enable caches (data cache in write-through mode) */
- write32 CCR1_A ,CCR1_D
-
- /* Disable WDT */
- write16 WTCSR_A, WTCSR_D
- write16 WTCNT_A, WTCNT_D
-
- /* Disable Register Bank interrupts */
- write16 IBNR_A, IBNR_D
-
- /* Set clocks based on 13.225MHz xtal */
- write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
-
- /* Enable all peripherals */
- write8 STBCR3_A, STBCR3_D
- write8 STBCR4_A, STBCR4_D
- write8 STBCR5_A, STBCR5_D
- write8 STBCR6_A, STBCR6_D
- write8 STBCR7_A, STBCR7_D
- write8 STBCR8_A, STBCR8_D
- write8 STBCR9_A, STBCR9_D
- write8 STBCR10_A, STBCR10_D
-
- /* SCIF7 and IIC2 */
- write16 PJCR3_A, PJCR3_D /* TXD7 */
- write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
-
- /* Configure bus (CS0) */
- write16 PFCR3_A, PFCR3_D /* A24 */
- write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
- write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
- write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
- write32 CS0WCR_A, CS0WCR_D
- write32 CS0BCR_A, CS0BCR_D
-
- /* Configure SDRAM (CS3) */
- write16 PCCR2_A, PCCR2_D /* CS3# */
- write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
- write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
- write32 CS3BCR_A, CS3BCR_D
- write32 CS3WCR_A, CS3WCR_D
- write32 SDCR_A, SDCR_D
- write32 RTCOR_A, RTCOR_D
- write32 RTCSR_A, RTCSR_D
-
- /* Configure ethernet (CS1) */
- write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
- write16 PHCR0_A, PHCR0_D
- write16 PFCR2_A, PFCR2_D /* CS1# */
- write32 CS1BCR_A, CS1BCR_D /* Big endian */
- write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
- write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
- write16 PJIOR1_A, PJIOR1_D
-
- /* wait 200us */
- mov.l REPEAT_D, r3
- mov #0, r2
-repeat0:
- add #1, r2
- cmp/hs r3, r2
- bf repeat0
- nop
-
- mov.l SDRAM_MODE, r1
- mov #0, r0
- mov.l r0, @r1
-
- nop
- rts
-
- .align 4
-
-CCR1_A: .long CCR1
-CCR1_D: .long 0x0000090B
-
-STBCR3_A: .long 0xFFFE0408
-STBCR4_A: .long 0xFFFE040C
-STBCR5_A: .long 0xFFFE0410
-STBCR6_A: .long 0xFFFE0414
-STBCR7_A: .long 0xFFFE0418
-STBCR8_A: .long 0xFFFE041C
-STBCR9_A: .long 0xFFFE0440
-STBCR10_A: .long 0xFFFE0444
-STBCR3_D: .long 0x0000001A
-STBCR4_D: .long 0x00000000
-STBCR5_D: .long 0x00000000
-STBCR6_D: .long 0x00000000
-STBCR7_D: .long 0x00000012
-STBCR8_D: .long 0x00000009
-STBCR9_D: .long 0x00000000
-STBCR10_D: .long 0x00000010
-
-WTCSR_A: .long 0xFFFE0000
-WTCNT_A: .long 0xFFFE0002
-WTCSR_D: .word 0xA518
-WTCNT_D: .word 0x5A00
-
-IBNR_A: .long 0xFFFE080E
-IBNR_D: .word 0x0000
-.align 2
-FRQCR_A: .long 0xFFFE0010
-FRQCR_D: .word 0x0015
-.align 2
-
-PJCR3_A: .long 0xFFFE3908
-PJCR3_D: .word 0x5000
-.align 2
-PECR1_A: .long 0xFFFE388C
-PECR1_D: .word 0x2011
-.align 2
-
-PFCR3_A: .long 0xFFFE38A8
-PFCR2_A: .long 0xFFFE38AA
-PBCR5_A: .long 0xFFFE3824
-PFCR3_D: .word 0x0010
-PFCR2_D: .word 0x0101
-PBCR5_D: .word 0x0111
-.align 2
-CS0WCR_A: .long 0xFFFC0028
-CS0WCR_D: .long 0x00000341
-CS0BCR_A: .long 0xFFFC0004
-CS0BCR_D: .long 0x00000400
-
-PCCR2_A: .long 0xFFFE384A
-PCCR1_A: .long 0xFFFE384C
-PCCR0_A: .long 0xFFFE384E
-PCCR2_D: .word 0x0001
-PCCR1_D: .word 0x1111
-PCCR0_D: .word 0x1111
-.align 2
-CS3BCR_A: .long 0xFFFC0010
-CS3BCR_D: .long 0x00004400
-CS3WCR_A: .long 0xFFFC0034
-CS3WCR_D: .long 0x00004912
-SDCR_A: .long 0xFFFC004C
-SDCR_D: .long 0x00000811
-RTCOR_A: .long 0xFFFC0058
-RTCOR_D: .long 0xA55A0035
-RTCSR_A: .long 0xFFFC0050
-RTCSR_D: .long 0xA55A0010
-.align 2
-SDRAM_MODE: .long 0xFFFC5460
-REPEAT_D: .long 0x000033F1
-
-PHCR1_A: .long 0xFFFE38EC
-PHCR0_A: .long 0xFFFE38EE
-PHCR1_D: .word 0x2222
-PHCR0_D: .word 0x2222
-.align 2
-CS1BCR_A: .long 0xFFFC0008
-CS1BCR_D: .long 0x00000400
-CS1WCR_A: .long 0xFFFC002C
-CS1WCR_D: .long 0x00000080
-PJDR1_A: .long 0xFFFE3914
-PJDR1_D: .word 0x0000
-.align 2
-PJIOR1_A: .long 0xFFFE3910
-PJIOR1_D: .word 0x8000
-.align 2
diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c
deleted file mode 100644
index 223234eb24..0000000000
--- a/board/renesas/rsk7269/rsk7269.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Renesas Electronics Europe Ltd.
- * Copyright (C) 2012 Phil Edworthy
- * Copyright (C) 2008 Renesas Solutions Corp.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- *
- * Based on u-boot/board/rsk7264/rsk7264.c
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
- puts("BOARD: Renesas RSK7269\n");
- return 0;
-}
-
-int board_init(void)
-{
- return 0;
-}
-
-void led_set_state(unsigned short value)
-{
-}
-
-/*
- * The RSK board has the SMSC89218 wired up 'incorrectly'.
- * Byte-swapping is necessary, and so poor performance is inevitable.
- * This problem cannot evade by the swap function of CHIP, this can
- * evade by software Byte-swapping.
- * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
- * functions necessary to solve this problem.
- */
-u32 pkt_data_pull(struct eth_device *dev, u32 addr)
-{
- volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
- return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
- | swab16(*(addr_16 + 1));
-}
-
-void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
-{
- addr += dev->iobase;
- *(volatile u16 *)(addr + 2) = swab16((u16)val);
- *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
diff --git a/board/shmin/Kconfig b/board/shmin/Kconfig
deleted file mode 100644
index 467580c67b..0000000000
--- a/board/shmin/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_SHMIN
-
-config SYS_BOARD
- default "shmin"
-
-config SYS_CONFIG_NAME
- default "shmin"
-
-endif
diff --git a/board/shmin/MAINTAINERS b/board/shmin/MAINTAINERS
deleted file mode 100644
index 5dee37bdf7..0000000000
--- a/board/shmin/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-SHMIN BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/shmin/
-F: include/configs/shmin.h
-F: configs/shmin_defconfig
diff --git a/board/shmin/Makefile b/board/shmin/Makefile
deleted file mode 100644
index 697fc20fa4..0000000000
--- a/board/shmin/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2010 Nobuhiro Iwamatsu
-# Copyright (C) 2008 Renesas Solutions Corp.
-#
-# u-boot/board/shmin/Makefile
-#
-
-obj-y := shmin.o
-extra-y += lowlevel_init.o
diff --git a/board/shmin/lowlevel_init.S b/board/shmin/lowlevel_init.S
deleted file mode 100644
index e4b6ae0b13..0000000000
--- a/board/shmin/lowlevel_init.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#include <config.h>
-
-#include <asm/processor.h>
-#include <asm/macro.h>
-
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
- /* Use setting of original bootloader */
- rts
- nop
- .align 2
diff --git a/board/shmin/shmin.c b/board/shmin/shmin.c
deleted file mode 100644
index 91918e9383..0000000000
--- a/board/shmin/shmin.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007 - 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- *
- * board/shmin/shmin.c
- *
- * Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
- puts("BOARD: T-SH7706LAN ");
- if(readb(0xb0008006) == 0xab)
- puts("v2\n");
- else
- puts("v1\n");
- return 0;
-}
-
-int board_init(void)
-{
- writew(0x2980, BCR2);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return ne2k_register();
-}
-
-void led_set_state(unsigned short value)
-{
-
-}
-
-#if defined(CONFIG_FLASH_CFI_LEGACY)
-#include <flash.h>
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- int sect[] = CONFIG_SYS_ATMEL_SECT;
- int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
- int i, j, k;
-
- if (base != CONFIG_SYS_ATMEL_BASE)
- return 0;
-
- info->flash_id = 0x01000000;
- info->portwidth = 1;
- info->chipwidth = 1;
- info->buffer_size = 1;
- info->erase_blk_tout = 16384;
- info->write_tout = 2;
- info->buffer_write_tout = 5;
- info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
- info->cmd_reset = 0x00F0;
- info->interface = FLASH_CFI_X8;
- info->legacy_unlock = 0;
- info->manufacturer_id = (u16) ATM_MANUFACT;
- info->device_id = ATM_ID_LV040;
- info->device_id2 = 0;
- info->ext_addr = 0;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0000;
- info->addr_unlock1 = 0x00000555;
- info->addr_unlock2 = 0x000002AA;
- info->name = "CFI conformant";
- info->size = 0;
- info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
- info->start[0] = base;
-
- for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
- info->size += sect[i] * sectsz[i];
- for (j = 0; j < sect[i]; j++, k++) {
- info->start[k + 1] = info->start[k] + sectsz[i];
- info->protect[k] = 0;
- }
- }
-
- return 1;
-}
-#endif /* CONFIG_FLASH_CFI_LEGACY */
diff --git a/configs/mpr2_defconfig b/configs/mpr2_defconfig
deleted file mode 100644
index 3e50c555ca..0000000000
--- a/configs/mpr2_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_MPR2=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ms7720se_defconfig b/configs/ms7720se_defconfig
deleted file mode 100644
index 1e580f5cd0..0000000000
--- a/configs/ms7720se_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_MS7720SE=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PCMCIA=y
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rsk7203_defconfig b/configs/rsk7203_defconfig
deleted file mode 100644
index 231d699270..0000000000
--- a/configs/rsk7203_defconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0xC7C0000
-CONFIG_TARGET_RSK7203=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_MISC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rsk7264_defconfig b/configs/rsk7264_defconfig
deleted file mode 100644
index 2ae70842a8..0000000000
--- a/configs/rsk7264_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0xCFC0000
-CONFIG_TARGET_RSK7264=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC3,115200"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rsk7269_defconfig b/configs/rsk7269_defconfig
deleted file mode 100644
index 3d2b03cc57..0000000000
--- a/configs/rsk7269_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0xDFC0000
-CONFIG_TARGET_RSK7269=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC7,115200"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/shmin_defconfig b/configs/shmin_defconfig
deleted file mode 100644
index 4686e67efd..0000000000
--- a/configs/shmin_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8DFB0000
-CONFIG_TARGET_SHMIN=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_AUTOBOOT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/doc/README.sh b/doc/README.sh
index 667c7974e5..766a8c8a29 100644
--- a/doc/README.sh
+++ b/doc/README.sh
@@ -23,13 +23,7 @@ U-Boot for Renesas SuperH
2.2. Renesas SH7722
This CPU has the SH4AL-DSP core.
- 2.3. Renesas SH7720
- This CPU has the SH3 core.
-
- 2.4. Renesas SH7710/SH7712
- This CPU has the SH3-DSP core and Ethernet controller.
-
- 2.5. Renesas SH7780
+ 2.3. Renesas SH7780
This CPU has the SH4A core.
================================================================================
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 8f52f9dce4..acfcc2954a 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -19,9 +19,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_CPU_SH7760) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7786)
+#if defined(CONFIG_CPU_SH7780)
static int scif_rxfill(struct uart_port *port)
{
return sci_in(port, SCRFDR) & 0xff;
@@ -38,14 +36,6 @@ static int scif_rxfill(struct uart_port *port)
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
}
}
-#elif defined(CONFIG_ARCH_SH7372)
-static int scif_rxfill(struct uart_port *port)
-{
- if (port->type == PORT_SCIFA)
- return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
- else
- return sci_in(port, SCRFDR);
-}
#else
static int scif_rxfill(struct uart_port *port)
{
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 8aa80d4a37..11deaa9511 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -12,53 +12,16 @@ struct uart_port {
enum sh_clk_mode clk_mode; /* clock mode */
};
-#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
-#include <asm/regs306x.h>
-#endif
-#if defined(CONFIG_H8S2678)
-#include <asm/regs267x.h>
-#endif
-
-#if defined(CONFIG_CPU_SH7706) || \
- defined(CONFIG_CPU_SH7707) || \
- defined(CONFIG_CPU_SH7708) || \
- defined(CONFIG_CPU_SH7709)
-# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
-# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-#elif defined(CONFIG_CPU_SH7705)
-# define SCIF0 0xA4400000
-# define SCIF2 0xA4410000
-# define SCSMR_Ir 0xA44A0000
-# define IRDA_SCIF SCIF0
-# define SCPCR 0xA4000116
-# define SCPDR 0xA4000136
-
-/* Set the clock source,
- * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
- * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
- */
-# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
-#elif defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
# define PORT_PTCR 0xA405011EUL
# define PORT_PVCR 0xA4050122UL
# define SCIF_ORER 0x0200 /* overrun error bit */
-#elif defined(CONFIG_SH_RTS7751R2D)
-# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
-# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7750S) || \
- defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R)
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
@@ -67,24 +30,6 @@ struct uart_port {
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
-#elif defined(CONFIG_CPU_SH7760)
-# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
-# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
-# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
-# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define PACR 0xa4050100
-# define PBCR 0xa4050102
-# define SCSCR_INIT(port) 0x3B
-#elif defined(CONFIG_CPU_SH7343)
-# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
-# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
-# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
-# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
-# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
#elif defined(CONFIG_CPU_SH7722)
# define PADR 0xA4050120
# undef PSDR
@@ -93,11 +38,6 @@ struct uart_port {
# define PSCR 0xA405011E
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7366)
-# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
-# define SCSPTR0 SCPDR0
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7723)
# define SCSPTR0 0xa4050160
# define SCSPTR1 0xa405013e
@@ -116,26 +56,6 @@ struct uart_port {
# define SCSPTR5 0xFFE45020
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH4_202)
-# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
-# define SCIF_BASE_ADDR 0x01030000
-# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
-# define SCIF_PTR2_OFFS 0x0000020
-# define SCIF_LSR2_OFFS 0x0000024
-# define SCSPTR\
- ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
-# define SCLSR2\
- ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
-#elif defined(CONFIG_H8S2678)
-# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
-# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
#elif defined(CONFIG_CPU_SH7757) || \
defined(CONFIG_CPU_SH7752) || \
defined(CONFIG_CPU_SH7753)
@@ -151,51 +71,15 @@ struct uart_port {
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7770)
-# define SCSPTR0 0xff923020 /* 16 bit SCIF */
-# define SCSPTR1 0xff924020 /* 16 bit SCIF */
-# define SCSPTR2 0xff925020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
#elif defined(CONFIG_CPU_SH7780)
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
-#if defined(CONFIG_SH_SH2007)
-/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
-# define SCSCR_INIT(port) 0x38
-#else
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
# define SCSCR_INIT(port) 0x3a
-#endif
-#elif defined(CONFIG_CPU_SH7786)
-# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
-# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
-# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
-# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
-# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
-# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* Overrun error bit */
-# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7201) || \
- defined(CONFIG_CPU_SH7203) || \
- defined(CONFIG_CPU_SH7206) || \
- defined(CONFIG_CPU_SH7263) || \
- defined(CONFIG_CPU_SH7264)
-# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
-# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
-# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
-# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
-# if defined(CONFIG_CPU_SH7201)
-# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
-# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
-# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
-# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
-# endif
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
+#elif defined(CONFIG_RZA1)
# define SCSPTR0 0xe8007020 /* 16 bit SCIF */
# define SCSPTR1 0xe8007820 /* 16 bit SCIF */
# define SCSPTR2 0xe8008020 /* 16 bit SCIF */
@@ -206,19 +90,6 @@ struct uart_port {
# define SCSPTR7 0xe800a820 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ORER 0x0001 /* overrun error bit */
-#elif defined(CONFIG_CPU_SH7619)
-# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
-# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
-# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SHX3)
-# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
-# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
-# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
-# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
-# define SCIF_ORER 0x0001 /* Overrun error bit */
-# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
defined(CONFIG_R7S72100)
# if defined(CONFIG_SCIF_A)
@@ -238,7 +109,6 @@ struct uart_port {
#define SCI_CTRL_FLAGS_TE 0x20 /* all */
#define SCI_CTRL_FLAGS_RE 0x10 /* all */
#if defined(CONFIG_CPU_SH7750) || \
- defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7722) || \
defined(CONFIG_CPU_SH7734) || \
@@ -246,9 +116,7 @@ struct uart_port {
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7763) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7786) || \
- defined(CONFIG_CPU_SHX3)
+ defined(CONFIG_CPU_SH7780)
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
#else
#define SCI_CTRL_FLAGS_REIE 0
@@ -280,12 +148,7 @@ struct uart_port {
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
-#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCIF_ORER 0x0200
@@ -333,12 +196,7 @@ struct uart_port {
#define SCxSR_ORER(port)\
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
-#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
@@ -402,16 +260,6 @@ static inline void sci_##name##_out(struct uart_port *port,\
}\
}
-#ifdef CONFIG_H8300
-/* h8300 don't have SCIF */
-#define CPU_SCIF_FNS(name) \
- static inline unsigned int sci_##name##_in(struct uart_port *port) {\
- return 0;\
- }\
- static inline void sci_##name##_out(struct uart_port *port,\
- unsigned int value) {\
- }
-#else
#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
SCI_IN(scif_size, scif_offset);\
@@ -420,7 +268,6 @@ static inline void sci_##name##_out(struct uart_port *port,\
unsigned int value) {\
SCI_OUT(scif_size, scif_offset, value);\
}
-#endif
#define CPU_SCI_FNS(name, sci_offset, sci_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
@@ -431,33 +278,13 @@ static inline void sci_##name##_out(struct uart_port *port,\
SCI_OUT(sci_size, sci_offset, value);\
}
-#if defined(CONFIG_CPU_SH3) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_SH73A0) || \
+#if defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
-#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
-#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
- sh4_sci_offset, sh4_sci_size, \
- sh3_scif_offset, sh3_scif_size, \
- sh4_scif_offset, sh4_scif_size, \
- h8_sci_offset, h8_sci_size) \
- CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
- sh4_scif_offset, sh4_scif_size)
-#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size) \
- CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
-#elif defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
-#elif defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_R8A7740)
+#elif defined(CONFIG_R8A7740)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scifb_offset, sh4_scifb_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
@@ -476,16 +303,6 @@ static inline void sci_##name##_out(struct uart_port *port,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
#endif
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
- sh4_sci_offset, sh4_sci_size, \
- sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size, \
- h8_sci_offset, h8_sci_size) \
- CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
-#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
- sh4_scif_offset, sh4_scif_size) \
- CPU_SCIF_FNS(name)
#elif defined(CONFIG_CPU_SH7723)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \
@@ -506,11 +323,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#endif
-#if defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
+#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
SCIF_FNS(SCSMR, 0x00, 16)
@@ -525,8 +338,7 @@ SCIF_FNS(SCxTDR, 0x20, 8)
SCIF_FNS(SCxRDR, 0x24, 8)
SCIF_FNS(SCLSR, 0x00, 0)
SCIF_FNS(DL, 0x00, 0) /* dummy */
-#elif defined(CONFIG_ARCH_SH7372) || \
- defined(CONFIG_R8A7740)
+#elif defined(CONFIG_R8A7740)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
@@ -583,9 +395,7 @@ SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
-#if defined(CONFIG_CPU_SH7760) || \
- defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7786)
+#if defined(CONFIG_CPU_SH7780)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
@@ -614,76 +424,17 @@ SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
-/* H8/300 series SCI pins assignment */
-#if defined(__H8300H__) || defined(__H8300S__)
-static const struct __attribute__((packed)) {
- int port; /* GPIO port no */
- unsigned short rx, tx; /* GPIO bit no */
-} h8300_sci_pins[] = {
-#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
- { /* SCI0 */
- .port = H8300_GPIO_P9,
- .rx = H8300_GPIO_B2,
- .tx = H8300_GPIO_B0,
- },
- { /* SCI1 */
- .port = H8300_GPIO_P9,
- .rx = H8300_GPIO_B3,
- .tx = H8300_GPIO_B1,
- },
- { /* SCI2 */
- .port = H8300_GPIO_PB,
- .rx = H8300_GPIO_B7,
- .tx = H8300_GPIO_B6,
- }
-#elif defined(CONFIG_H8S2678)
- { /* SCI0 */
- .port = H8300_GPIO_P3,
- .rx = H8300_GPIO_B2,
- .tx = H8300_GPIO_B0,
- },
- { /* SCI1 */
- .port = H8300_GPIO_P3,
- .rx = H8300_GPIO_B3,
- .tx = H8300_GPIO_B1,
- },
- { /* SCI2 */
- .port = H8300_GPIO_P5,
- .rx = H8300_GPIO_B1,
- .tx = H8300_GPIO_B0,
- }
-#endif
-};
-#endif
-
-#if defined(CONFIG_CPU_SH7706) || \
- defined(CONFIG_CPU_SH7707) || \
- defined(CONFIG_CPU_SH7708) || \
- defined(CONFIG_CPU_SH7709)
-static inline int sci_rxd_in(struct uart_port *port)
-{
- if (port->mapbase == 0xfffffe80)
- return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
- return 1;
-}
-#elif defined(CONFIG_CPU_SH7750) || \
+#if defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7750R) || \
- defined(CONFIG_CPU_SH7750S) || \
- defined(CONFIG_CPU_SH7091)
+ defined(CONFIG_CPU_SH7750S)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
return 1;
}
-#elif defined(__H8300H__) || defined(__H8300S__)
-static inline int sci_rxd_in(struct uart_port *port)
-{
- int ch = (port->mapbase - SMR0) >> 3;
- return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
-}
#else /* default case for non-SCI processors */
static inline int sci_rxd_in(struct uart_port *port)
{
@@ -723,16 +474,9 @@ static inline int sci_rxd_in(struct uart_port *port)
* -- Mitch Davis - 15 Jul 2000
*/
-#if (defined(CONFIG_CPU_SH7780) || \
- defined(CONFIG_CPU_SH7786)) && \
- !defined(CONFIG_SH_SH2007)
+#if defined(CONFIG_CPU_SH7780)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
-#elif defined(CONFIG_CPU_SH7705) || \
- defined(CONFIG_CPU_SH7720) || \
- defined(CONFIG_CPU_SH7721) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377) || \
- defined(CONFIG_ARCH_SH7372) || \
+#elif defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
@@ -745,8 +489,6 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
return ((clk*2)+16*bps)/(16*bps)-1;
}
#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
-#elif defined(__H8300H__) || defined(__H8300S__)
-#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
#elif defined(CONFIG_RCAR_GEN2)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#if defined(CONFIG_SCIF_A)
diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h
deleted file mode 100644
index e8594966e0..0000000000
--- a/include/configs/mpr2.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for MPR2
- *
- * Copyright (C) 2008
- * Mark Jonas <mark.jonas@de.bosch.com>
- */
-
-#ifndef __MPR2_H
-#define __MPR2_H
-
-/* Supported commands */
-
-/* Default environment variables */
-#define CONFIG_BOOTFILE "/boot/zImage"
-#define CONFIG_LOADADDR 0x8E000000
-
-/* CPU and platform */
-#define CONFIG_CPU_SH7720 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* U-Boot internals */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-
-/* Memory */
-#define CONFIG_SYS_SDRAM_BASE 0x8C000000
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-
-/* Flash */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BASE 0xA0000000
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Clocks */
-#define CONFIG_SYS_CLK_FREQ 24000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* UART */
-#define CONFIG_CONS_SCIF0 1
-
-#endif /* __MPR2_H */
diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h
deleted file mode 100644
index f582b5a8e4..0000000000
--- a/include/configs/ms7720se.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Hitachi Solution Engine 7720
- *
- * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#ifndef __MS7720SE_H
-#define __MS7720SE_H
-
-#define CONFIG_CPU_SH7720 1
-
-#define CONFIG_BOOTFILE "/boot/zImage"
-#define CONFIG_LOADADDR 0x8E000000
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#define MS7720SE_SDRAM_BASE 0x8C000000
-#define MS7720SE_FLASH_BASE_1 0xA0000000
-#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
-
-#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
-
-#define CONFIG_SYS_MAX_FLASH_SECT 150
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* PCMCIA */
-#define CONFIG_IDE_PCMCIA 1
-#define CONFIG_MARUBUN_PCCARD 1
-#define CONFIG_PCMCIA_SLOT_A 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
-#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
-#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
-#define CONFIG_SYS_MARUBUN_IO 0xb8600000
-
-#define CONFIG_SYS_PIO_MODE 1
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
-#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
-#define CONFIG_IDE_SWAP_IO
-
-#endif /* __MS7720SE_H */
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
deleted file mode 100644
index 941dbc1046..0000000000
--- a/include/configs/rsk7203.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Technology RSK 7203
- *
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#ifndef __RSK7203_H
-#define __RSK7203_H
-
-#define CONFIG_CPU_SH7203 1
-
-#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#define RSK7203_SDRAM_BASE 0x0C000000
-#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
-#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
-
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
-
-#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT 64
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 33333333
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-#endif /* __RSK7203_H */
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
deleted file mode 100644
index e91e4bd416..0000000000
--- a/include/configs/rsk7264.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas RSK2+SH7264 board
- *
- * Copyright (C) 2011 Renesas Electronics Europe Ltd.
- * Copyright (C) 2008 Nobuhiro Iwamatsu
- * Copyright (C) 2008 Renesas Solutions Corp.
- */
-
-#ifndef __RSK7264_H
-#define __RSK7264_H
-
-#define CONFIG_CPU_SH7264 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-
-/* Serial */
-#define CONFIG_CONS_SCIF3 1
-
-/* Memory */
-/* u-boot relocated to top 256KB of ram */
-#define CONFIG_SYS_SDRAM_BASE 0x0C000000
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
-
-/* Flash */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_ENV_OFFSET (128 * 1024)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 36000000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-#endif /* __RSK7264_H */
diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
deleted file mode 100644
index fc45f46cc6..0000000000
--- a/include/configs/rsk7269.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas RSK2+SH7269 board
- *
- * Copyright (C) 2012 Renesas Electronics Europe Ltd.
- * Copyright (C) 2012 Phil Edworthy
- */
-
-#ifndef __RSK7269_H
-#define __RSK7269_H
-
-#define CONFIG_CPU_SH7269 1
-
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-
-#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
-
-/* Serial */
-#define CONFIG_CONS_SCIF7
-
-/* Memory */
-/* u-boot relocated to top 256KB of ram */
-#define CONFIG_SYS_SDRAM_BASE 0x0C000000
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
-
-/* NOR Flash */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-#define CONFIG_ENV_OFFSET (128 * 1024)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 66125000
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
-#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
-
-#endif /* __RSK7269_H */
diff --git a/include/configs/shmin.h b/include/configs/shmin.h
deleted file mode 100644
index 9aeca97bec..0000000000
--- a/include/configs/shmin.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR)
- *
- * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __SHMIN_H
-#define __SHMIN_H
-
-#define CONFIG_CPU_SH7706 1
-/* T-SH7706LAN */
-#define CONFIG_SHMIN 1
-/* T-SH7706LSR*/
-/* #define CONFIG_T_SH7706LSR 1 */
-
-/*
- * This board has original boot loader. If you write u-boot to 0x0,
- * you should set undef.
- */
-#undef CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* system */
-#define SHMIN_SDRAM_BASE (0x8C000000)
-#define SHMIN_FLASH_BASE_1 (0xA0000000)
-
-#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 }
-
-/* SCIF */
-#define CONFIG_CONS_SCIF0 1
-
-/* memory */
-#define CONFIG_SYS_SDRAM_BASE SHMIN_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START SHMIN_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024))
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_BASE SHMIN_FLASH_BASE_1
-#define CONFIG_SYS_MAX_FLASH_SECT 11
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_MAX_FLASH_SECT
-#define CONFIG_SYS_ATMEL_REGION 4
-#define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
-#define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
-
-#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-
-#ifdef CONFIG_T_SH7706LSR
-#define CONFIG_ENV_ADDR (SHMIN_FLASH_BASE_1 + 70000)
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-/* Board Clock */
-#ifdef CONFIG_T_SH7706LSR
-#define CONFIG_SYS_CLK_FREQ 40000000
-#else
-#define CONFIG_SYS_CLK_FREQ 33333333
-#endif /* CONFIG_T_SH7706LSR */
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-/* Network device */
-#define CONFIG_DRIVER_NE2000
-#define CONFIG_DRIVER_NE2000_BASE (0xb0000300)
-
-#endif /* __SHMIN_H */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 93f5643468..b16bc6ae34 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -270,11 +270,6 @@ CONFIG_CPU_PXA26X
CONFIG_CPU_PXA27X
CONFIG_CPU_PXA300
CONFIG_CPU_R8000
-CONFIG_CPU_SH7203
-CONFIG_CPU_SH7264
-CONFIG_CPU_SH7269
-CONFIG_CPU_SH7706
-CONFIG_CPU_SH7720
CONFIG_CPU_SH7722
CONFIG_CPU_SH7723
CONFIG_CPU_SH7734
@@ -4419,7 +4414,6 @@ CONFIG_TWR
CONFIG_TWR_P1025
CONFIG_TX_DESCR_NUM
CONFIG_TZSW_RESERVED_DRAM_SIZE
-CONFIG_T_SH7706LSR
CONFIG_UART_BR_PRELIM
CONFIG_UART_OR_PRELIM
CONFIG_UBIBLOCK
@@ -4518,7 +4512,6 @@ CONFIG_USB_GADGET_OMAP
CONFIG_USB_GADGET_PXA27X
CONFIG_USB_GADGET_PXA2XX
CONFIG_USB_GADGET_SA1100
-CONFIG_USB_GADGET_SUPERH
CONFIG_USB_INVENTRA_DMA
CONFIG_USB_ISP1301_I2C_ADDR
CONFIG_USB_MAX_CONTROLLER_COUNT