diff options
| -rw-r--r-- | arch/arm/dts/r8a7794-silk-u-boot.dts | 4 | ||||
| -rw-r--r-- | arch/arm/mach-rmobile/Kconfig.32 | 3 | ||||
| -rw-r--r-- | board/renesas/silk/Makefile | 6 | ||||
| -rw-r--r-- | board/renesas/silk/silk.c | 186 | ||||
| -rw-r--r-- | board/renesas/silk/silk_spl.c | 425 | ||||
| -rw-r--r-- | configs/alt_defconfig | 1 | ||||
| -rw-r--r-- | configs/lager_defconfig | 1 | ||||
| -rw-r--r-- | configs/sh7752evb_defconfig | 1 | ||||
| -rw-r--r-- | configs/sh7753evb_defconfig | 1 | ||||
| -rw-r--r-- | configs/sh7757lcr_defconfig | 1 | ||||
| -rw-r--r-- | configs/silk_defconfig | 50 | ||||
| -rw-r--r-- | drivers/clk/renesas/r8a7792-cpg-mssr.c | 10 | ||||
| -rw-r--r-- | drivers/clk/renesas/r8a7794-cpg-mssr.c | 10 | ||||
| -rw-r--r-- | drivers/mmc/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/mmc/sh_mmcif.c | 165 | ||||
| -rw-r--r-- | include/configs/alt.h | 1 | ||||
| -rw-r--r-- | include/configs/lager.h | 1 | ||||
| -rw-r--r-- | include/configs/sh7752evb.h | 1 | ||||
| -rw-r--r-- | include/configs/sh7753evb.h | 1 | ||||
| -rw-r--r-- | include/configs/sh7757lcr.h | 1 | ||||
| -rw-r--r-- | include/configs/silk.h | 66 | ||||
| -rw-r--r-- | scripts/config_whitelist.txt | 1 |
22 files changed, 729 insertions, 213 deletions
diff --git a/arch/arm/dts/r8a7794-silk-u-boot.dts b/arch/arm/dts/r8a7794-silk-u-boot.dts index 435cbc1f65..dcd954e04a 100644 --- a/arch/arm/dts/r8a7794-silk-u-boot.dts +++ b/arch/arm/dts/r8a7794-silk-u-boot.dts @@ -8,3 +8,7 @@ #include "r8a7794-silk.dts" #include "r8a7794-u-boot.dtsi" + +&scif2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index fe123f86ef..a8835f6571 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -68,6 +68,9 @@ config TARGET_SILK bool "Silk board" select DM select DM_SERIAL + select SUPPORT_SPL + select USE_TINY_PRINTF + select SPL_TINY_MEMSET config TARGET_PORTER bool "Porter board" diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile index 8916a8d961..b5c3ad8d93 100644 --- a/board/renesas/silk/Makefile +++ b/board/renesas/silk/Makefile @@ -7,4 +7,8 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := silk.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := silk_spl.o +else +obj-y := silk.o qos.o +endif diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 9e2080bcea..bfe9909daf 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -30,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define CLK2MHZ(clk) (clk / 1000 / 1000) void s_init(void) { struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; @@ -44,150 +43,65 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF2_MSTP719 (1 << 19) -#define ETHER_MSTP813 (1 << 13) -#define IIC1_MSTP323 (1 << 23) -#define MMC0_MSTP315 (1 << 15) -#define SDHI1_MSTP312 (1 << 12) +#define TMU0_MSTP125 BIT(25) +#define MMC0_MSTP315 BIT(15) #define SD1CKCR 0xE6150078 -#define SD1_97500KHZ 0x7 +#define SD_97500KHZ 0x7 int board_early_init_f(void) { /* TMU */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF2 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + /* Set SD1 to the 97.5MHz */ + writel(SD_97500KHZ, SD1CKCR); - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - /* IIC1 / sh-i2c ch1 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); - -#ifdef CONFIG_SH_MMCIF - /* MMC */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); -#endif - -#ifdef CONFIG_SH_SDHI - /* SDHI1 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312); - - /* - * Set SD1 to the 97.5MHz - */ - writel(SD1_97500KHZ, SD1CKCR); -#endif return 0; } -/* LSI pin pull-up control */ -#define PUPR3 0xe606010C -#define PUPR3_ETH 0x006FF800 -#define PUPR1 0xe6060104 -#define PUPR1_DREQ0_N (1 << 20) +#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */ + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7794_pinmux_init(); - - /* Ether Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REFCLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_MAGIC, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ8, NULL); - - /* PHY reset */ - mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH); - gpio_request(GPIO_GP_1_24, NULL); - mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N); - - gpio_direction_output(GPIO_GP_1_24, 0); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); mdelay(20); - gpio_set_value(GPIO_GP_1_24, 1); + gpio_direction_output(ETHERNET_PHY_RESET, 1); udelay(1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { -#ifdef CONFIG_SH_ETHER - int ret = -ENODEV; - u32 val; - unsigned char enetaddr[6]; + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); - - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); - - return ret; -#else return 0; -#endif } -int board_mmc_init(bd_t *bis) +int dram_init_banksize(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_MMCIF - /* MMC0 */ - gpio_request(GPIO_GP_4_31, NULL); - gpio_direction_output(GPIO_GP_4_31, 1); - - ret = mmcif_mmc_init(); -#endif - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD1_DATA0, NULL); - gpio_request(GPIO_FN_SD1_DATA1, NULL); - gpio_request(GPIO_FN_SD1_DATA2, NULL); - gpio_request(GPIO_FN_SD1_DATA3, NULL); - gpio_request(GPIO_FN_SD1_CLK, NULL); - gpio_request(GPIO_FN_SD1_CMD, NULL); - gpio_request(GPIO_FN_SD1_CD, NULL); - - /* SDHI 1 */ - gpio_request(GPIO_GP_4_26, NULL); - gpio_request(GPIO_GP_4_29, NULL); - gpio_direction_output(GPIO_GP_4_26, 1); - gpio_direction_output(GPIO_GP_4_29, 1); - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); -#endif - return ret; + fdtdec_setup_memory_banksize(); + + return 0; } -int dram_init(void) +/* porter has KSZ8041RNLI */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); return 0; } @@ -198,22 +112,38 @@ const struct rmobile_sysinfo sysinfo = { void reset_cpu(ulong addr) { - u8 val; + struct udevice *dev; + const u8 pmic_bus = 1; + const u8 pmic_addr = 0x58; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); - i2c_set_bus_num(1); /* PowerIC connected to ch1 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + data |= BIT(1); + + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } -static const struct sh_serial_platdata serial_platdata = { - .base = SCIF2_BASE, - .type = PORT_SCIF, - .clk = 14745600, - .clk_mode = EXT_CLK, -}; +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; -U_BOOT_DEVICE(silk_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/silk/silk_spl.c b/board/renesas/silk/silk_spl.c new file mode 100644 index 0000000000..5309ce9f08 --- /dev/null +++ b/board/renesas/silk/silk_spl.c @@ -0,0 +1,425 @@ +/* + * board/renesas/silk/silk_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF2_MSTP719 BIT(19) +#define QSPI_MSTP917 BIT(17) + +#define SD1CKCR 0xE6150078 +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x00018040 }, + { 0x0094, 0x00000000 }, + { 0x0098, 0x00000000 }, + { 0x0020, 0x94000000 }, + { 0x0024, 0x00000006 }, + { 0x0028, 0x40000000 }, + { 0x002c, 0x00000155 }, + { 0x0030, 0x00000002 }, + { 0x0034, 0x00000000 }, + { 0x0038, 0x00000000 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x60000000 }, + { 0x0044, 0x36dab6db }, + { 0x0048, 0x926da012 }, + { 0x004c, 0x0008c383 }, + { 0x0050, 0x00000000 }, + { 0x0054, 0x00000140 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x00ec3fff }, + { 0x000c, 0x5bffffff }, + { 0x0010, 0x01bfe1ff }, + { 0x0014, 0x5bffffff }, + { 0x0018, 0x0f4b200f }, + { 0x001c, 0x03ffffff }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0x00000000 }, + { 0x0104, 0x4203fdf0 }, + { 0x0108, 0x00000000 }, + { 0x010c, 0x159007ff }, + { 0x0110, 0x80000000 }, + { 0x0114, 0x00de481f }, + { 0x0118, 0x00000000 }, + }; + + static const struct reg_config pfc_with_unlock2[] = { + { 0x0060, 0xffffffff }, + { 0x0064, 0xfffff000 }, + { 0x0068, 0x55555500 }, + { 0x006c, 0xffffff00 }, + { 0x0070, 0x00000000 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) { + writel(~pfc_with_unlock2[i].val, pfc_base); + writel(pfc_with_unlock2[i].val, + pfc_base | pfc_with_unlock2[i].off); + } +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x2000, 0x3000, 0x4000 + }; + + static const struct reg_config gpio_set[] = { + { 0x2000, 0x24000000 }, + { 0x4000, 0xa4000000 }, + { 0x5000, 0x0084c000 }, + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x01000000 }, + { 0x2000, 0x24000000 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0xa4000000 }, + { 0x5000, 0x00044380 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + writel(BIT(23), gpio_base | 0x5020); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + writel(BIT(23), gpio_base | 0x5000); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x2a103320 }, + { 0x38, 0xff70ff70 }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0280, 0x0000a55a }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x80000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config2[] = { + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0005c000 }, + }; + + static const struct reg_config dbsc_config3r2[] = { + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181224 }, + }; + + static const struct reg_config dbsc_config4[] = { + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf004649b }, + { 0x0290, 0x00000061 }, + { 0x02a0, 0x0000006d }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000073 }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x00000009 }, + { 0x0044, 0x00000007 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x00000009 }, + { 0x0054, 0x000a0009 }, + { 0x0058, 0x00000021 }, + { 0x005c, 0x00000018 }, + { 0x0060, 0x00000005 }, + { 0x0064, 0x00000020 }, + { 0x0068, 0x00000007 }, + { 0x006c, 0x0000000a }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000010 }, + { 0x0078, 0x000000ae }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x50213005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000200 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20042004 }, + { 0x0380, 0x00020003 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c4e1 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fcb6d0 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x85589955 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a852400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300210b4 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000b50 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000010 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x012c00be }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081450 }, + { 0x00e8, 0x00010000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0014, 0x00000001 }, + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf00464db }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) + writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); + + for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) { + writel(dbsc_config3r2[i].val, + dbsc3_0_base | dbsc_config3r2[i].off); + } + + for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) + writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* Set SD1 to the 97.5MHz */ + writel(SD_97500KHZ, SD1CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 172461a7f4..19ae070895 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 1ce7949d74..86fab8c014 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig index db460978aa..ed3946b34b 100644 --- a/configs/sh7752evb_defconfig +++ b/configs/sh7752evb_defconfig @@ -31,6 +31,7 @@ CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig index c747384e1b..96f30b3747 100644 --- a/configs/sh7753evb_defconfig +++ b/configs/sh7753evb_defconfig @@ -30,6 +30,7 @@ CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig index f5cc2a97d8..b6d5f47bc8 100644 --- a/configs/sh7757lcr_defconfig +++ b/configs/sh7757lcr_defconfig @@ -33,6 +33,7 @@ CONFIG_MAC_PARTITION=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MMC=y +CONFIG_SH_MMCIF=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_NETDEVICES=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index bba0ce76e7..309935d08e 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -1,17 +1,37 @@ CONFIG_ARM=y +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0xE6304000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_R8A7794=y CONFIG_TARGET_SILK=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -19,21 +39,43 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DM_GPIO=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_IIC=y +CONFIG_DM_MMC=y +CONFIG_SH_MMCIF=y +CONFIG_RENESAS_SDHI=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MICREL=y -CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y CONFIG_SH_ETHER=y -CONFIG_BAUDRATE=38400 +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_RCAR_GEN2=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_PFC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SH_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index 260bb892d6..4ba18b18be 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -39,7 +39,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7792_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -78,7 +78,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1), }; -static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7792_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7792_CLK_MP), DEF_MOD("jpu", 106, R8A7792_CLK_M2), DEF_MOD("tmu1", 111, R8A7792_CLK_P), @@ -152,10 +152,6 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), }; -static const unsigned int r8a7792_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -179,7 +175,7 @@ static const unsigned int r8a7792_crit_mod_clks[] __initconst = { #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { { 1, 208, 106, 200 }, { 1, 208, 88, 200 }, { 1, 156, 80, 150 }, diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c index 90bac3deed..e8f57c3d01 100644 --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c @@ -40,7 +40,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7794_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), @@ -85,7 +85,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240), }; -static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7794_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7794_CLK_MP), DEF_MOD("vcp0", 101, R8A7794_CLK_ZS), DEF_MOD("vpc0", 103, R8A7794_CLK_ZS), @@ -188,10 +188,6 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { DEF_MOD("scifa5", 1108, R8A7794_CLK_MP), }; -static const unsigned int r8a7794_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -210,7 +206,7 @@ static const unsigned int r8a7794_crit_mod_clks[] __initconst = { */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = { { 1, 208, 88, 200 }, { 1, 156, 66, 150 }, { 2, 240, 102, 230 }, diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6935da2177..4fa8dd83bb 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -266,6 +266,12 @@ config SH_SDHI help Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform +config SH_MMCIF + bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support" + depends on ARCH_RMOBILE || SH + help + Support for the on-chip MMCIF host controller on SuperH/Renesas ARM SoCs platform + config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 1ff59f06d5..26fe125cea 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -11,9 +11,13 @@ #include <watchdog.h> #include <command.h> #include <mmc.h> +#include <clk.h> +#include <dm.h> #include <malloc.h> #include <linux/errno.h> -#include <asm/io.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <linux/sizes.h> #include "sh_mmcif.h" #define DRIVER_NAME "sh_mmcif" @@ -510,10 +514,9 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, return ret; } -static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) +static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host, + struct mmc_cmd *cmd, struct mmc_data *data) { - struct sh_mmcif_host *host = mmc->priv; int ret; WATCHDOG_RESET(); @@ -539,10 +542,8 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, return ret; } -static int sh_mmcif_set_ios(struct mmc *mmc) +static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc) { - struct sh_mmcif_host *host = mmc->priv; - if (mmc->clock) sh_mmcif_clock_control(host, mmc->clock); @@ -558,19 +559,45 @@ static int sh_mmcif_set_ios(struct mmc *mmc) return 0; } -static int sh_mmcif_init(struct mmc *mmc) +static int sh_mmcif_initialize_common(struct sh_mmcif_host *host) { - struct sh_mmcif_host *host = mmc->priv; - sh_mmcif_sync_reset(host); sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); return 0; } +#ifndef CONFIG_DM_MMC +static void *mmc_priv(struct mmc *mmc) +{ + return (void *)mmc->priv; +} + +static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_send_cmd_common(host, cmd, data); +} + +static int sh_mmcif_set_ios(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_set_ios_common(host, mmc); +} + +static int sh_mmcif_initialize(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_initialize_common(host); +} + static const struct mmc_ops sh_mmcif_ops = { - .send_cmd = sh_mmcif_request, - .set_ios = sh_mmcif_set_ios, - .init = sh_mmcif_init, + .send_cmd = sh_mmcif_send_cmd, + .set_ios = sh_mmcif_set_ios, + .init = sh_mmcif_initialize, }; static struct mmc_config sh_mmcif_cfg = { @@ -606,3 +633,115 @@ int mmcif_mmc_init(void) return 0; } + +#else +struct sh_mmcif_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_mmcif_host *host = dev_get_priv(dev); + + return sh_mmcif_send_cmd_common(host, cmd, data); +} + +int sh_mmcif_dm_set_ios(struct udevice *dev) +{ + struct sh_mmcif_host *host = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return sh_mmcif_set_ios_common(host, mmc); +} + +static const struct dm_mmc_ops sh_mmcif_dm_ops = { + .send_cmd = sh_mmcif_dm_send_cmd, + .set_ios = sh_mmcif_dm_set_ios, +}; + +static int sh_mmcif_dm_bind(struct udevice *dev) +{ + struct sh_mmcif_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +static int sh_mmcif_dm_probe(struct udevice *dev) +{ + struct sh_mmcif_plat *plat = dev_get_platdata(dev); + struct sh_mmcif_host *host = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct clk sh_mmcif_clk; + fdt_addr_t base; + int ret; + + base = devfdt_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K); + if (!host->regs) + return -ENOMEM; + + ret = clk_get_by_index(dev, 0, &sh_mmcif_clk); + if (ret) { + debug("failed to get clock, ret=%d\n", ret); + return ret; + } + + ret = clk_enable(&sh_mmcif_clk); + if (ret) { + debug("failed to enable clock, ret=%d\n", ret); + return ret; + } + + host->clk = clk_get_rate(&sh_mmcif_clk); + + plat->cfg.name = dev->name; + plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + + switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", + 1)) { + case 8: + plat->cfg.host_caps |= MMC_MODE_8BIT; + break; + case 4: + plat->cfg.host_caps |= MMC_MODE_4BIT; + break; + case 1: + break; + default: + dev_err(dev, "Invalid \"bus-width\" value\n"); + return -EINVAL; + } + + sh_mmcif_initialize_common(host); + + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk); + plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk); + plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + upriv->mmc = &plat->mmc; + + return 0; +} + +static const struct udevice_id sh_mmcif_sd_match[] = { + { .compatible = "renesas,sh-mmcif" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sh_mmcif_mmc) = { + .name = "sh-mmcif", + .id = UCLASS_MMC, + .of_match = sh_mmcif_sd_match, + .bind = sh_mmcif_dm_bind, + .probe = sh_mmcif_dm_probe, + .priv_auto_alloc_size = sizeof(struct sh_mmcif_host), + .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat), + .ops = &sh_mmcif_dm_ops, +}; +#endif diff --git a/include/configs/alt.h b/include/configs/alt.h index f5e41db156..d6236870b9 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -73,7 +73,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* MMCIF */ -#define CONFIG_SH_MMCIF #define CONFIG_SH_MMCIF_ADDR 0xee200000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/lager.h b/include/configs/lager.h index 45a76f8010..97f7b2c7e7 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -72,7 +72,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 /* MMC */ -#define CONFIG_SH_MMCIF #define CONFIG_SH_MMCIF_ADDR 0xEE220000 #define CONFIG_SH_MMCIF_CLK 97500000 diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h index e192de0623..ff1208f196 100644 --- a/include/configs/sh7752evb.h +++ b/include/configs/sh7752evb.h @@ -60,7 +60,6 @@ #define CONFIG_SH_SPI_BASE 0xfe002000 /* MMCIF */ -#define CONFIG_SH_MMCIF 1 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h index c17bc310bb..9a1d2e3368 100644 --- a/include/configs/sh7753evb.h +++ b/include/configs/sh7753evb.h @@ -60,7 +60,6 @@ #define CONFIG_SH_SPI_BASE 0xfe002000 /* MMCIF */ -#define CONFIG_SH_MMCIF 1 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 6ca13aa5f8..94b4119c58 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -64,7 +64,6 @@ #define CONFIG_SH_SPI_BASE 0xfe002000 /* MMCIF */ -#define CONFIG_SH_MMCIF 1 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 #define CONFIG_SH_MMCIF_CLK 48000000 diff --git a/include/configs/silk.h b/include/configs/silk.h index 5d85c0df93..5f351b5c4b 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -16,12 +16,8 @@ #include "rcar-gen2-common.h" -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC -#endif -#define STACK_AREA_SIZE 0xC000 +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) @@ -49,46 +45,22 @@ /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK -#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) -#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) - -#define CONFIG_SYS_TMU_CLK_DIV 4 - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_SPEED2 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* MMCIF */ -#define CONFIG_SH_MMCIF -#define CONFIG_SH_MMCIF_ADDR 0xee200000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 97500000 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF */ -#define CONFIG_SMSTP2_ENA 0x00002000 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 -/* SCIF2 */ -#define CONFIG_SMSTP7_ENA 0x00080000 +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF2 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __SILK_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 193c7ded3f..9eba487ec4 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1820,7 +1820,6 @@ CONFIG_SH_I2C_8BIT CONFIG_SH_I2C_CLOCK CONFIG_SH_I2C_DATA_HIGH CONFIG_SH_I2C_DATA_LOW -CONFIG_SH_MMCIF CONFIG_SH_MMCIF_ADDR CONFIG_SH_MMCIF_CLK CONFIG_SH_QSPI_BASE |