diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/Kconfig | 19 | ||||
| -rw-r--r-- | arch/powerpc/dts/gazerbeam.dts | 2 | ||||
| -rw-r--r-- | board/gdsys/common/Makefile | 1 | ||||
| -rw-r--r-- | board/gdsys/mpc8308/Kconfig | 29 | ||||
| -rw-r--r-- | board/gdsys/mpc8308/MAINTAINERS | 2 | ||||
| -rw-r--r-- | board/gdsys/mpc8308/Makefile | 1 | ||||
| -rw-r--r-- | board/gdsys/mpc8308/gazerbeam.c | 179 | ||||
| -rw-r--r-- | configs/gazerbeam_defconfig | 196 | ||||
| -rw-r--r-- | include/configs/gazerbeam.h | 137 |
9 files changed, 564 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index fe20e85086..b99288aa83 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -175,6 +175,25 @@ config TARGET_STRIDER select SYS_FSL_ERRATUM_ESDHC111 imply CMD_PCA953X +config TARGET_GAZERBEAM + bool "Support gazerbeam" + select ARCH_MPC8308 + select SYS_FSL_ERRATUM_ESDHC111 + imply ENV_IS_IN_FLASH + help + The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH + Systementwicklung based on the NXP MPC8308 SoC for usage in KVM + appliances. + + Features include: + * Two gigabit ethernet ports + * Multiple USB ports (depending on variant) + * Several gigabit ethernet or optical fiber ports (depending on + variant) + * Several display port inputs and outputs, and supporting redrivers + (depending on variant) + * Several FPGAs with custom logic (depending on variant) + endchoice config MPC83XX_QUICC_ENGINE diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts index 5d171519e0..96c03c77ae 100644 --- a/arch/powerpc/dts/gazerbeam.dts +++ b/arch/powerpc/dts/gazerbeam.dts @@ -10,7 +10,7 @@ * option) any later version. */ -/include/ "gdsys/mpc8308.dtsi" +#include "gdsys/mpc8308.dtsi" /include/ "gdsys/gazerbeam-base.dtsi" diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index ff8d6f4966..7dfe104561 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7 obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o +obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o ifdef CONFIG_OSD obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index e6a4796054..30811889fb 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -71,7 +71,28 @@ config GDSYS_LEGACY_DRIVERS endif -if TARGET_HRCON || TARGET_STRIDER +if TARGET_GAZERBEAM + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "gazerbeam" + +config SYS_FPGA1_BASE + default E0700000 + +config SYS_FPGA1_SIZE + default 1 + +config GDSYS_LEGACY_OSD_CMDS + default y +endif + +if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM choice prompt "FPGA flavor selection" @@ -89,6 +110,12 @@ config SYS_FPGA_FLAVOR_GAZERBEAM endchoice +config EXTENDED_FEATURES + bool "FPGA extended features" + depends on GDSYS_LEGACY_DRIVERS + help + Enable support for the extended features field of the IHS FPGA. + config CMD_IOLOOP bool "Enable 'ioloop' and 'ioreflect' commands" help diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index 755b9a2385..ed1b6fa106 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -6,7 +6,9 @@ F: include/configs/hrcon.h F: configs/hrcon_defconfig F: configs/hrcon_dh_defconfig F: include/configs/strider.h +F: configs/strider_defconfig F: configs/strider_cpu_defconfig F: configs/strider_cpu_dp_defconfig F: configs/strider_con_defconfig F: configs/strider_con_dp_defconfig +F: configs/gazerbeam_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index dc579479f9..9af5fe04d1 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -6,3 +6,4 @@ obj-y := mpc8308.o sdram.o obj-$(CONFIG_TARGET_HRCON) += hrcon.o obj-$(CONFIG_TARGET_STRIDER) += strider.o +obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c new file mode 100644 index 0000000000..cd621744d2 --- /dev/null +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <board.h> +#include <dm.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <misc.h> +#include <tpm-v1.h> +#include <video_osd.h> + +#include "../common/ihs_mdio.h" +#include "../../../drivers/board/gazerbeam.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct ihs_mdio_info ihs_mdio_info[] = { + { .fpga = NULL, .name = "ihs0", .base = 0x58 }, + { .fpga = NULL, .name = "ihs1", .base = 0x58 }, +}; + +static int get_tpm(struct udevice **devp) +{ + int rc; + + rc = uclass_first_device_err(UCLASS_TPM, devp); + if (rc) { + printf("Could not find TPM (ret=%d)\n", rc); + return CMD_RET_FAILURE; + } + + return 0; +} + +int board_early_init_r(void) +{ + struct udevice *board; + struct udevice *serdes; + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + /* Initialize serdes */ + uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes); + + if (board_detect(board)) + puts("Device information detection failed.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + if (mc == 2 || mc == 1) + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22"); + + if (mc == 4) { + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20"); + dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0"); + dev_enable_by_path("/fpga1bus"); + } + + if (mc == 2 || con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video1"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video1"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video1"); + } + + if (con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video0"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video0"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video0"); + } + + return 0; +} + +int checkboard(void) +{ + struct udevice *board; + char *s = env_get("serial#"); + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + puts("Board: Gazerbeam "); + printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC"); + printf("%s", con == VAR_CON ? "CON" : "CPU"); + + if (s) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void display_osd_info(struct udevice *osd, + struct video_osd_info *osd_info) +{ + printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n", + osd->name, osd_info->major_version, osd_info->minor_version, + osd_info->width, osd_info->height); +} + +int last_stage_init(void) +{ + int fpga_hw_rev = 0; + int i; + struct udevice *board; + struct udevice *osd; + struct video_osd_info osd_info; + struct udevice *tpm; + int ret; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + if (board) { + int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev); + + if (res) + printf("Could not determind FPGA HW revision (res = %d)\n", res); + } + + env_set_ulong("fpga_hw_rev", fpga_hw_rev); + + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) || + tpm_continue_self_test(tpm)) { + printf("TPM init failed\n"); + } + + if (fpga_hw_rev >= 4) { + for (i = 0; i < 4; i++) { + struct udevice *rxaui; + char name[8]; + + snprintf(name, sizeof(name), "rxaui%d", i); + /* Disable RXAUI polarity inversion */ + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui); + if (!ret) + misc_set_enabled(rxaui, false); + } + } + + for (uclass_first_device(UCLASS_VIDEO_OSD, &osd); + osd; + uclass_next_device(&osd)) { + video_osd_get_info(osd, &osd_info); + display_osd_info(osd, &osd_info); + } + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fsl_fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig new file mode 100644 index 0000000000..346b1b2eaa --- /dev/null +++ b/configs/gazerbeam_defconfig @@ -0,0 +1,196 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MALLOC_F_LEN=0x600 +CONFIG_IDENT_STRING=" gazerbeam 0.01" +CONFIG_SYS_CLK_FREQ=33333333 +CONFIG_MPC83xx=y +CONFIG_TARGET_GAZERBEAM=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="INIT_RAM" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xE0700000 +CONFIG_LBLAW2_NAME="FPGA1" +CONFIG_LBLAW2_LENGTH_1_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA0" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="FPGA1" +CONFIG_BR2_OR2_BASE=0xE0700000 +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_1_MBYTES=y +CONFIG_OR2_SCY_5=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y +CONFIG_CMD_IOLOOP=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_CPU=y +CONFIG_CMD_BINOP=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_AXI=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_MII_DRIVER=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_HASH=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT2=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_AXI=y +CONFIG_IHS_AXI=y +CONFIG_CLK=y +CONFIG_ICS8N3QV01=y +CONFIG_CPU=y +CONFIG_CPU_MPC83XX=y +CONFIG_BOARD=y +CONFIG_BOARD_GAZERBEAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_IHS=y +CONFIG_MISC=y +CONFIG_GDSYS_RXAUI_CTRL=y +CONFIG_GDSYS_IOEP=y +CONFIG_MPC83XX_SERDES=y +CONFIG_GDSYS_SOC=y +CONFIG_IHS_FPGA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_RAM=y +CONFIG_MPC83XX_SDRAM=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_MCP83XX=y +CONFIG_TIMER=y +CONFIG_MPC83XX_TIMER=y +CONFIG_TPM_ATMEL_TWI=y +CONFIG_TPM_AUTH_SESSIONS=y +# CONFIG_TPM_V2 is not set +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LOGICORE_DP_TX=y +CONFIG_OSD=y +CONFIG_IHS_VIDEO_OUT=y +CONFIG_TPM=y diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h new file mode 100644 index 0000000000..11d367a151 --- /dev/null +++ b/include/configs/gazerbeam.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE + +/* + * Memory test + * TODO: Migrate! + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07e00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Environment + */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +/* TODO: Turn into string option and migrate to Kconfig */ +#define CONFIG_HOSTNAME "gazerbeam" +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + +#endif /* __CONFIG_H */ |