diff options
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 9 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun6i.c | 6 |
2 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d4dff1e346..be9fcfda0e 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -116,7 +116,9 @@ struct sunxi_ccm_reg { u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ - u32 reserved21[13]; + u32 reserved21[5]; + u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */ + u32 reserved21_5[7]; u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ @@ -223,6 +225,11 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31) +#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24) +#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7) +#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16) +#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f) + #if defined(CONFIG_MACH_SUN50I) /* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ #define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 15272c9e71..ed8cd9bbb3 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -148,6 +148,12 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) const int max_n = 32; int k = 1, m = 2; +#ifdef CONFIG_MACH_SUN8I_H3 + clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | + CCM_PLL5_TUN_INIT_FREQ_MASK, + CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); +#endif + if (sigma_delta_enable) writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); |