diff options
211 files changed, 6555 insertions, 4046 deletions
@@ -254,7 +254,7 @@ config BUILD_TARGET default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 default "u-boot.itb" if SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ - ARCH_SUNXI || RISCV) + ARCH_SUNXI || RISCV || ARCH_ZYNQMP) default "u-boot.kwb" if KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "u-boot-with-spl.imx" if ARCH_MX6 && SPL @@ -500,6 +500,7 @@ config SPL_FIT_GENERATOR depends on SPL_FIT default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP + default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV help Specifies a (platform specific) script file to generate the FIT diff --git a/MAINTAINERS b/MAINTAINERS index 438fb225ab..7d2729dfb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -52,7 +52,7 @@ Maintainers List (try to look for most precise areas first) ----------------------------------- ANDROID AB M: Igor Opaniuk <igor.opaniuk@gmail.com> -R: Sam Protsenko <semen.protsenko@linaro.org> +R: Sam Protsenko <joe.skb7@gmail.com> S: Maintained F: cmd/ab_select.c F: common/android_ab.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ee3ca8d182..a623ef5743 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -12,6 +12,7 @@ config ARM64 if ARM64 config POSITION_INDEPENDENT bool "Generate position-independent pre-relocation code" + select INIT_SP_RELATIVE help U-Boot expects to be linked to a specific hard-coded address, and to be loaded to and run from that address. This option lifts that diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d7e625ef1d..04a8cccda5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -282,6 +282,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu111-revA.dtb \ zynqmp-zcu1275-revA.dtb \ zynqmp-zcu1275-revB.dtb \ + zynqmp-zcu1285-revA.dtb \ + zynqmp-zcu208-revA.dtb \ zynqmp-zcu216-revA.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ @@ -872,8 +874,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j721e-r5-common-proc-board.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7622-rfb.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ + mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts new file mode 100644 index 0000000000..ec30f5c6eb --- /dev/null +++ b/arch/arm/dts/mt7622-rfb.dts @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7622.dtsi" +#include "mt7622-u-boot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "mt7622-rfb"; + compatible = "mediatek,mt7622", "mediatek,mt7622-rfb"; + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + aliases { + spi0 = &snfi; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x10000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + + +&pinctrl { + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + snor_pins: snor-pins { + mux { + function = "flash"; + groups = "spi_nor"; + }; + }; + + uart0_pins: uart0 { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-default { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; + + mmc0_pins_default: mmc0default { + mux { + function = "emmc"; + groups = "emmc"; + }; + + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively + */ + conf-cmd-dat { + pins = "NDL0", "NDL1", "NDL2", + "NDL3", "NDL4", "NDL5", + "NDL6", "NDL7", "NRB"; + input-enable; + bias-pull-up; + }; + + conf-clk { + pins = "NCLE"; + bias-pull-down; + }; + + }; + + mmc1_pins_default: mmc1default { + mux { + function = "sd"; + groups = "sd_0"; + }; + /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", + * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, + * DAT2, DAT3, CMD, CLK for SD respectively. + */ + conf-cmd-data { + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", + "I2S2_IN","I2S4_OUT"; + input-enable; + drive-strength = <8>; + bias-pull-up; + }; + conf-clk { + pins = "I2S3_OUT"; + drive-strength = <12>; + bias-pull-down; + }; + conf-cd { + pins = "TXD3"; + bias-pull-up; + }; + + }; +}; + +&snfi { + pinctrl-names = "default", "snfi"; + pinctrl-0 = <&snor_pins>; + pinctrl-1 = <&snfi_pins>; + status = "okay"; + + spi-flash@0{ + compatible = "jedec,spi-nor"; + reg = <0>; + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7622-u-boot.dtsi b/arch/arm/dts/mt7622-u-boot.dtsi new file mode 100644 index 0000000000..b14b1d4344 --- /dev/null +++ b/arch/arm/dts/mt7622-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +&topckgen { + u-boot,dm-pre-reloc; +}; + +&pericfg { + u-boot,dm-pre-reloc; +}; + +&apmixedsys { + u-boot,dm-pre-reloc; +}; + +&timer0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&snfi { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi new file mode 100644 index 0000000000..7dcca5c6af --- /dev/null +++ b/arch/arm/dts/mt7622.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/mt7622-clk.h> + +/ { + compatible = "mediatek,mt7622"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + clock-frequency = <1300000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + clock-frequency = <1300000000>; + }; + }; + + snfi: snfi@1100d000 { + compatible = "mediatek,mtk-snfi-spi"; + reg = <0x1100d000 0x2000>; + clocks = <&pericfg CLK_PERI_NFI_PD>, + <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>, + <&topckgen CLK_TOP_NFI_INFRA_SEL>; + + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>, + <&topckgen CLK_TOP_UNIVPLL2_D8>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + arm,cpu-registers-not-fw-configured; + }; + + timer0: timer@10004000 { + compatible = "mediatek,timer"; + reg = <0x10004000 0x80>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; + clocks = <&system_clk>; + clock-names = "system-clk"; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + infracfg: infracfg@10000000 { + compatible = "mediatek,mt7622-infracfg", + "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: pericfg@10002000 { + compatible = "mediatek,mt7622-pericfg", "syscon"; + reg = <0x10002000 0x1000>; + #clock-cells = <1>; + }; + + scpsys: scpsys@10006000 { + compatible = "mediatek,mt7622-scpsys", + "syscon"; + #power-domain-cells = <1>; + reg = <0x10006000 0x1000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; + infracfg = <&infracfg>; + clocks = <&topckgen CLK_TOP_HIF_SEL>; + clock-names = "hif_sel"; + }; + + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,sysirq"; + reg = <0x10200620 0x20>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + apmixedsys: apmixedsys@10209000 { + compatible = "mediatek,mt7622-apmixedsys"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@10210000 { + compatible = "mediatek,mt7622-topckgen"; + reg = <0x10210000 0x1000>; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@10211000 { + compatible = "mediatek,mt7622-pinctrl"; + reg = <0x10211000 0x1000>; + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + watchdog: watchdog@10212000 { + compatible = "mediatek,wdt"; + reg = <0x10212000 0x800>; + }; + + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10310000 0x1000>, + <0x10320000 0x1000>, + <0x10340000 0x2000>, + <0x10360000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART0_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0x11230000 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, + <&topckgen CLK_TOP_MSDC50_0_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0x11240000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/mt7623-u-boot.dtsi b/arch/arm/dts/mt7623-u-boot.dtsi new file mode 100644 index 0000000000..832c16dca8 --- /dev/null +++ b/arch/arm/dts/mt7623-u-boot.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +&topckgen { + u-boot,dm-pre-reloc; +}; + +&topckgen { + u-boot,dm-pre-reloc; +}; + +&pericfg { + u-boot,dm-pre-reloc; +}; + +&timer0 { + u-boot,dm-pre-reloc; +}; + +&apmixedsys { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 1135b1e1ae..1f45dea575 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -101,21 +101,18 @@ compatible = "mediatek,mt7623-topckgen"; reg = <0x10000000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; infracfg: syscon@10001000 { compatible = "mediatek,mt7623-infracfg", "syscon"; reg = <0x10001000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; pericfg: syscon@10003000 { compatible = "mediatek,mt7623-pericfg", "syscon"; reg = <0x10003000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; pinctrl: pinctrl@10005000 { @@ -155,7 +152,6 @@ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; clocks = <&system_clk>; clock-names = "system-clk"; - u-boot,dm-pre-reloc; }; sysirq: interrupt-controller@10200100 { @@ -170,7 +166,6 @@ compatible = "mediatek,mt7623-apmixedsys"; reg = <0x10209000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; gic: interrupt-controller@10211000 { @@ -215,7 +210,6 @@ <&pericfg CLK_PERI_UART2>; clock-names = "baud", "bus"; status = "disabled"; - u-boot,dm-pre-reloc; }; uart3: serial@11005000 { diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index b0c86219b6..bcedcf20f1 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt7623.dtsi" +#include "mt7623-u-boot.dtsi" / { model = "Bananapi BPI-R2"; diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi b/arch/arm/dts/mt7629-rfb-u-boot.dtsi index 1ef5568518..164afd633b 100644 --- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi @@ -22,3 +22,39 @@ #endif }; }; + +&infracfg { + u-boot,dm-pre-reloc; +}; + +&pericfg { + u-boot,dm-pre-reloc; +}; + +&timer0 { + u-boot,dm-pre-reloc; +}; + +&mcucfg { + u-boot,dm-pre-reloc; +}; + +&dramc { + u-boot,dm-pre-reloc; +}; + +&apmixedsys { + u-boot,dm-pre-reloc; +}; + +&topckgen { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&snfi { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts index 0981f9b3b1..687fe1c029 100644 --- a/arch/arm/dts/mt7629-rfb.dts +++ b/arch/arm/dts/mt7629-rfb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt7629.dtsi" +#include "mt7629-rfb-u-boot.dtsi" / { model = "MediaTek MT7629 RFB"; diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index b0c843bafd..a33a74a556 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -68,14 +68,12 @@ compatible = "mediatek,mt7629-infracfg", "syscon"; reg = <0x10000000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; pericfg: syscon@10002000 { compatible = "mediatek,mt7629-pericfg", "syscon"; reg = <0x10002000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; timer0: timer@10004000 { @@ -85,7 +83,6 @@ clocks = <&topckgen CLK_TOP_CLKXTAL_D4>, <&topckgen CLK_TOP_10M_SEL>; clock-names = "mux", "src"; - u-boot,dm-pre-reloc; }; scpsys: scpsys@10006000 { @@ -103,7 +100,6 @@ compatible = "mediatek,mt7629-mcucfg", "syscon"; reg = <0x10200000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; sysirq: interrupt-controller@10200a80 { @@ -124,21 +120,18 @@ <&topckgen CLK_TOP_MEM_SEL>, <&topckgen CLK_TOP_DMPLL>; clock-names = "phy", "phy_mux", "mem", "mem_mux"; - u-boot,dm-pre-reloc; }; apmixedsys: clock-controller@10209000 { compatible = "mediatek,mt7629-apmixedsys"; reg = <0x10209000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; topckgen: clock-controller@10210000 { compatible = "mediatek,mt7629-topckgen"; reg = <0x10210000 0x1000>; #clock-cells = <1>; - u-boot,dm-pre-reloc; }; watchdog: watchdog@10212000 { @@ -186,7 +179,6 @@ status = "disabled"; assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>; - u-boot,dm-pre-reloc; }; uart1: serial@11003000 { @@ -228,7 +220,6 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - u-boot,dm-pre-reloc; }; ethsys: syscon@1b000000 { diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts new file mode 100644 index 0000000000..296ed93b9e --- /dev/null +++ b/arch/arm/dts/mt8512-bm1-emmc.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + * + */ + +/dts-v1/; + +#include <config.h> +#include "mt8512.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "MT8512 BM1 EMMC"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; + +&pinctrl { + mmc0_pins_default: mmc0default { + mux { + function = "msdc"; + groups = "msdc0"; + }; + + conf-cmd-data { + pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1", + "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4", + "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7"; + input-enable; + drive-strength = <6>; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC0_CLK"; + drive-strength = <6>; + bias-pull-down; + }; + + conf-rst { + pins = "MSDC0_RSTB"; + bias-pull-up; + }; + }; + + uart0_pins: uart0 { + mux { + function = "uart"; + groups = "uart0_0_rxd_txd"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi new file mode 100644 index 0000000000..01a02a7ebf --- /dev/null +++ b/arch/arm/dts/mt8512.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + * + */ + +#include <dt-bindings/clock/mt8512-clk.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt8512"; + interrupt-parent = <&sysirq>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0xc000000 0x40000>, /* GICD */ + <0xc080000 0x200000>; /* GICR */ + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt8512-topckgen"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + topckgen_cg: clock-controller-cg@10000000 { + compatible = "mediatek,mt8512-topckgen-cg"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; + + infracfg: clock-controller@10001000 { + compatible = "mediatek,mt8512-infracfg"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + }; + + pinctrl: pinctrl@10005000 { + compatible = "mediatek,mt8512-pinctrl"; + reg = <0x10005000 0x1000>; + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + watchdog0: watchdog@10007000 { + compatible = "mediatek,wdt"; + reg = <0x10007000 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>; + #reset-cells = <1>; + status = "disabled"; + timeout-sec = <60>; + reset-on-timeout; + }; + + timer0: apxgpt@10008000 { + compatible = "mediatek,timer"; + reg = <0x10008000 0x1000>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_SYS_26M_D2>, + <&topckgen CLK_TOP_CLK32K>, + <&infracfg CLK_INFRA_APXGPT>; + clock-names = "clk13m", + "clk32k", + "bus"; + }; + + apmixedsys: clock-controller@1000c000 { + compatible = "mediatek,mt8512-apmixedsys"; + reg = <0x1000c000 0x1000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200a80 0x50>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0x11002000 0x1000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_CLK26M>, + <&infracfg CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8512-mmc"; + reg = <0x11230000 0x1000>, + <0x11cd0000 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg CLK_INFRA_MSDC0>, + <&infracfg CLK_INFRA_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + +};
\ No newline at end of file diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 07dfa0d107..c35eb2344f 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -62,6 +62,39 @@ regulator-always-on; }; + replicator { + compatible = "arm,coresight-static-replicator"; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + }; + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + }; + amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; @@ -415,5 +448,107 @@ reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; + + etb@f8801000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0xf8801000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@f8803000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0xf8803000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + funnel@f8804000 { + compatible = "arm,coresight-static-funnel", "arm,primecell"; + reg = <0xf8804000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel0_in_port1: endpoint { + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel0_in_port2: endpoint { + }; + }; + /* The other input ports are not connect to anything */ + }; + }; + + ptm@f889c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xf889c000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + cpu = <&cpu0>; + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; + }; + + ptm@f889d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0xf889d000 0x1000>; + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; + cpu = <&cpu1>; + out-ports { + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel0_in_port1>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 1123bfc743..61482017d6 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -47,6 +47,14 @@ }; }; +&nand0 { + status = "okay"; +}; + +&smcc { + status = "okay"; +}; + &spi0 { status = "okay"; num-cs = <4>; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 998298cc9b..8eacd22d7c 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -2,7 +2,7 @@ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2017, Xilinx, Inc. + * (C) Copyright 2017 - 2019, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -173,26 +173,30 @@ }; &gem0 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, - <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, + <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, - <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, + <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, - <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, + <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, - <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, + <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index 9ef55ad0d1..c9464ec8eb 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -61,13 +61,13 @@ clock-accuracy = <100>; }; - dpdma_clk: dpdma_clk { + dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; - drm_clock: drm_clock { + drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 93aa193f01..d376ade834 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -50,55 +50,6 @@ #size-cells = <1>; arasan,has-mdma; num-cs = <2>; - - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1C00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xFCC00000>; - }; - partition@6 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x1 0x0 0x400000>; - }; - partition@7 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x1 0x400000 0x1400000>; - }; - partition@8 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x1 0x1800000 0x400000>; - }; - partition@9 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x1 0x1C00000 0x1400000>; - }; - partition@10 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x1 0x3000000 0x400000>; - }; - partition@11 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x1 0x3400000 0xFCC00000>; - }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 14aa98de73..21118c8cc3 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -11,7 +11,7 @@ /dts-v1/; #include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" +#include "zynqmp-clk-ccf.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> @@ -53,7 +53,7 @@ label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; @@ -95,7 +95,7 @@ linux,default-trigger = "bluetooth-power"; }; - vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ + vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; @@ -120,9 +120,10 @@ regulator-boot-on; }; - sdio_pwrseq: sdio_pwrseq { + sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + post-power-on-delay-ms = <10>; }; ina226 { diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 78110c490e..b580f9263d 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -51,14 +51,14 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -213,25 +213,25 @@ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; - gtr_sel0 { + gtr-sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; - gtr_sel1 { + gtr-sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; - gtr_sel2 { + gtr-sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; - gtr_sel3 { + gtr-sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 2132024a25..38ec188164 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -25,7 +25,7 @@ /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; /* Cleanup from RevA */ - /delete-node/ phy@21; + /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index b4dd101330..d31982fce7 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -51,14 +51,14 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -653,7 +653,6 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; - no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index aabf73dd6d..bff224f78d 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -51,14 +51,14 @@ label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = <KEY_DOWN>; - gpio-key,wakeup; + wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; - heartbeat_led { + heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -566,7 +566,6 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; - no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index 34c4becd43..2ec29b0b5d 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -75,6 +75,10 @@ &sdhci1 { status = "okay"; + /* + * 1.0 revision has level shifter and this property should be + * removed for supporting UHS mode + */ no-1-8-v; xlnx,mio_bank = <1>; }; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts new file mode 100644 index 0000000000..9c18013138 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP ZCU1285 RevA + * + * (C) Copyright 2018 - 2019, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * Siva Durga Prasad Paladugu <sivadur@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZCU1285 RevA"; + compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", + "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + mmc0 = &sdhci1; + i2c = &i2c0; /* EMIO */ + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ina226-u60 { + compatible = "iio-hwmon"; + io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; + }; + ina226-u61 { + compatible = "iio-hwmon"; + io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; + }; + ina226-u63 { + compatible = "iio-hwmon"; + io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; + }; + ina226-u65 { + compatible = "iio-hwmon"; + io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; + }; + ina226-u64 { + compatible = "iio-hwmon"; + io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; + }; +}; + +&dcc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PMBUS */ + max20751@74 { /* u23 */ + compatible = "maxim,max20751"; + reg = <0x74>; + }; + max20751@70 { /* u89 */ + compatible = "maxim,max20751"; + reg = <0x70>; + }; + max15301@a { /* u28 */ + compatible = "maxim,max15301"; + reg = <0xa>; + }; + max15303@b { /* u48 */ + compatible = "maxim,max15303"; + reg = <0xb>; + }; + max15303@d { /* u27 */ + compatible = "maxim,max15303"; + reg = <0xd>; + }; + max15303@e { /* u11 */ + compatible = "maxim,max15303"; + reg = <0xe>; + }; + max15303@f { /* u96 */ + compatible = "maxim,max15303"; + reg = <0xf>; + }; + max15303@11 { /* u47 */ + compatible = "maxim,max15303"; + reg = <0x11>; + }; + max15303@12 { /* u24 */ + compatible = "maxim,max15303"; + reg = <0x12>; + }; + max15301@13 { /* u29 */ + compatible = "maxim,max15301"; + reg = <0x13>; + }; + max15303@14 { /* u51 */ + compatible = "maxim,max15303"; + reg = <0x14>; + }; + max15303@15 { /* u30 */ + compatible = "maxim,max15303"; + reg = <0x15>; + }; + max15303@16 { /* u102 */ + compatible = "maxim,max15303"; + reg = <0x16>; + }; + max15301@17 { /* u50 */ + compatible = "maxim,max15301"; + reg = <0x17>; + }; + max15301@18 { /* u31 */ + compatible = "maxim,max15301"; + reg = <0x18>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* CM_I2C */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYS_EEPROM */ + eeprom: eeprom@54 { /* u101 */ + compatible = "atmel,24c32"; /* 24LC32A */ + reg = <0x54>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* FMC1 */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* FMC2 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* ANALOG_PMBUS */ + u60: ina226@40 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u60"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + u61: ina226@41 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u61"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + u63: ina226@42 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u63"; + reg = <0x42>; + shunt-resistor = <1000>; + }; + u65: ina226@43 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u65"; + reg = <0x43>; + shunt-resistor = <1000>; + }; + u64: ina226@44 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-u64"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* ANALOG_CM_I2C */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* FMC3 */ + }; + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&uart0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + xlnx,mio_bank = <1>; +}; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts new file mode 100644 index 0000000000..9181060b89 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU208 + * + * (C) Copyright 2017 - 2019, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> + +/ { + model = "ZynqMP ZCU208 RevA"; + compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + xlnx,eeprom = &eeprom; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_DOWN>; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + ina226-vccint { + compatible = "iio-hwmon"; + io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; + }; + ina226-vccint-io-bram-ps { + compatible = "iio-hwmon"; + io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; + }; + ina226-vcc1v8 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; + }; + ina226-vcc1v2 { + compatible = "iio-hwmon"; + io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; + }; + ina226-vadj-fmc { + compatible = "iio-hwmon"; + io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; + }; + ina226-mgtavcc { + compatible = "iio-hwmon"; + io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; + }; + ina226-mgt1v2 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; + }; + ina226-mgt1v8 { + compatible = "iio-hwmon"; + io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; + }; + ina226-vccint-ams { + compatible = "iio-hwmon"; + io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; + }; + ina226-dac-avtt { + compatible = "iio-hwmon"; + io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; + }; + ina226-dac-avccaux { + compatible = "iio-hwmon"; + io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; + }; + ina226-adc-avcc { + compatible = "iio-hwmon"; + io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; + }; + ina226-adc-avccaux { + compatible = "iio-hwmon"; + io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; + }; + ina226-dac-avcc { + compatible = "iio-hwmon"; + io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: ethernet-phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ + "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ + "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ + "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ + "", "", "BUTTON", "LED", "", /* 20 - 24 */ + "", "PMU_INPUT", "", "", "", /* 25 - 29 */ + "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ + "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ + "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ + "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ + "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ + "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ + "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ + "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ + "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ + "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ + "", "", /* 78 - 79 */ + "", "", "", "", "", /* 80 - 84 */ + "", "", "", "", "", /* 85 -89 */ + "", "", "", "", "", /* 90 - 94 */ + "", "", "", "", "", /* 95 - 99 */ + "", "", "", "", "", /* 100 - 104 */ + "", "", "", "", "", /* 105 - 109 */ + "", "", "", "", "", /* 110 - 114 */ + "", "", "", "", "", /* 115 - 119 */ + "", "", "", "", "", /* 120 - 124 */ + "", "", "", "", "", /* 125 - 129 */ + "", "", "", "", "", /* 130 - 134 */ + "", "", "", "", "", /* 135 - 139 */ + "", "", "", "", "", /* 140 - 144 */ + "", "", "", "", "", /* 145 - 149 */ + "", "", "", "", "", /* 150 - 154 */ + "", "", "", "", "", /* 155 - 159 */ + "", "", "", "", "", /* 160 - 164 */ + "", "", "", "", "", /* 165 - 169 */ + "", "", "", ""; /* 170 - 174 */ +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u15: gpio@20 { /* u15 */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ + "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ + "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ + "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ + }; + + i2c-mux@75 { /* u17 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + vccint: ina226@40 { /* u65 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + vccint_io_bram_ps: ina226@41 { /* u57 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-io-bram-ps"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + vcc1v8: ina226@42 { /* u60 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v8"; + reg = <0x42>; + shunt-resistor = <2000>; + }; + vcc1v2: ina226@43 { /* u58 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vcc1v2"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + vadj_fmc: ina226@45 { /* u62 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vadj-fmc"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + mgtavcc: ina226@46 { /* u67 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgtavcc"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + mgt1v2: ina226@47 { /* u63 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v2"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + mgt1v8: ina226@48 { /* u64 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-mgt1v8"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + vccint_ams: ina226@49 { /* u61 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-vccint-ams"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + dac_avtt: ina226@4a { /* u59 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avtt"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + dac_avccaux: ina226@4b { /* u124 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avccaux"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + adc_avcc: ina226@4c { /* u75 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avcc"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + adc_avccaux: ina226@4d { /* u71 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-adc-avccaux"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + dac_avcc: ina226@4e { /* u77 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + label = "ina226-dac-avcc"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* u104 - ir35215 0x10/0x40 */ + /* u127 - ir38164 0x1b/0x4b */ + /* u112 - ir38164 0x13/0x43 */ + /* u123 - ir38164 0x1c/0x4c */ + + irps5401_44: irps54012@44 { /* IRPS5401 - u53 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x44>; /* i2c addr 0x14 */ + }; + irps5401_45: irps54012@45 { /* IRPS5401 - u55 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x45>; /* i2c addr 0x15 */ + }; + /* J21 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; + /* u38 MPS430 */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@74 { + compatible = "nxp,pca9548"; /* u20 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c_eeprom: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u21 */ + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + i2c_si5341: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u43 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c_si570_user_c0: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c0"; + }; + }; + i2c_si570_mgt: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + clock-output-names = "si570_mgt"; + }; + }; + i2c_8a34001: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* U409B - 8a34001 */ + }; + i2c_clk104: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* CLK104_SDA */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* RFMCP connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u22 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c_si570_user_c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + clock-output-names = "si570_user_c1"; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; + /* MSP430 */ +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + disable-wp; + xlnx,mio_bank = <1>; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index dd9cd7b38f..c294e1b51a 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -253,7 +253,7 @@ #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; - shunt-resistor = <2000>; + shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; @@ -302,7 +302,7 @@ #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; - shunt-resistor = <2000>; + shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; @@ -401,7 +401,7 @@ * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ - compatible = "atmel,24c08"; + compatible = "atmel,24c128"; reg = <0x54>; }; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b453941baf..9e7fae83f7 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -25,7 +25,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; @@ -34,7 +34,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; @@ -43,7 +43,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; @@ -52,7 +52,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; @@ -74,7 +74,7 @@ }; }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { @@ -252,7 +252,7 @@ }; }; - amba_apu: amba_apu@0 { + amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; @@ -626,12 +626,12 @@ compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; + gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; - gpio-controller; power-domains = <&zynqmp_firmware PD_GPIO>; }; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index ad453a60c1..17b84db5a8 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -6,9 +6,21 @@ config SYS_SOC config SYS_VENDOR default "mediatek" +config MT8512 + bool "MediaTek MT8512 SoC" + default n + choice prompt "MediaTek board select" +config TARGET_MT7622 + bool "MediaTek MT7622 SoC" + select ARM64 + help + The MediaTek MT7622 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB3.0, SD and MMC cards, NAND, SNFI, PWM, PCIe, + Gigabit Ethernet, I2C, built-in Wi-Fi, and PCIe. + config TARGET_MT7623 bool "MediaTek MT7623 SoC" select CPU_V7A @@ -29,6 +41,16 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT8512 + bool "MediaTek MT8512 M1 Board" + select ARM64 + select MT8512 + help + The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo + chip and several DDR3 and DDR4 options. + config TARGET_MT8516 bool "MediaTek MT8516 SoC" select ARM64 @@ -49,8 +71,10 @@ config TARGET_MT8518 endchoice +source "board/mediatek/mt7622/Kconfig" source "board/mediatek/mt7623/Kconfig" source "board/mediatek/mt7629/Kconfig" +source "board/mediatek/mt8512/Kconfig" source "board/mediatek/mt8518/Kconfig" source "board/mediatek/pumpkin/Kconfig" diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index b9b2355e03..290d2c709f 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -3,6 +3,8 @@ obj-y += cpu.o obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_MT8512) += mt8512/ +obj-$(CONFIG_TARGET_MT7622) += mt7622/ obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ diff --git a/arch/arm/mach-mediatek/mt7622/Makefile b/arch/arm/mach-mediatek/mt7622/Makefile new file mode 100644 index 0000000000..886ab7e4eb --- /dev/null +++ b/arch/arm/mach-mediatek/mt7622/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c new file mode 100644 index 0000000000..1e527c0485 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7622/init.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/armv8/mmu.h> + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT7622\n"); + return 0; +} + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + return fdtdec_setup_mem_size_base(); + +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +static struct mm_region mt7622_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; +struct mm_region *mem_map = mt7622_mem_map; diff --git a/arch/arm/mach-mediatek/mt8512/Makefile b/arch/arm/mach-mediatek/mt8512/Makefile new file mode 100644 index 0000000000..007eb4a367 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8512/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c new file mode 100644 index 0000000000..a38b5d12d9 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Configuration for MediaTek MT8512 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <wdt.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8512-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +phys_size_t get_effective_memsize(void) +{ + /* limit stack below tee reserve memory */ + return gd->ram_size - 6 * SZ_1M; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = get_effective_memsize(); + + return 0; +} + +void reset_cpu(ulong addr) +{ + struct udevice *watchdog_dev = NULL; + + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) + psci_system_reset(); + + wdt_expire_now(watchdog_dev, 0); +} + +int print_cpuinfo(void) +{ + debug("CPU: MediaTek MT8512\n"); + return 0; +} + +static struct mm_region mt8512_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8512_mem_map; diff --git a/arch/arm/mach-mediatek/mt8512/lowlevel_init.S b/arch/arm/mach-mediatek/mt8512/lowlevel_init.S new file mode 100644 index 0000000000..ad392120f4 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8512/lowlevel_init.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + /* Define in src\bsp\trustzone\atf\v1.2\ */ + /* mt8xxx\plat\mediatek\common\sip_svc.h */ + /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/ + ldr x0, =0xC2000200 + SMC #0 + ret diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h index 5412ed6827..89eb565c94 100644 --- a/arch/arm/mach-zynq/include/mach/hardware.h +++ b/arch/arm/mach-zynq/include/mach/hardware.h @@ -9,13 +9,8 @@ #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 -#define ZYNQ_QSPI_BASEADDR 0xE000D000 -#define ZYNQ_SMC_BASEADDR 0xE000E000 -#define ZYNQ_NAND_BASEADDR 0xE1000000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 -#define ZYNQ_USB_BASEADDR0 0xE0002000 -#define ZYNQ_USB_BASEADDR1 0xE0003000 #define ZYNQ_OCM_BASEADDR 0xFFFC0000 /* Bootmode setting values */ diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 6cf17eb94e..d82a737a69 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -117,17 +117,6 @@ config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED config ZYNQ_SDHCI_MAX_FREQ default 200000000 -config SPL_ZYNQMP_TWO_SDHCI - bool "Enable booting from both SDHCIs" - depends on SPL - help - This option reflects that board has two SDHCI controllers which - platform can use as boot device. This option ensures that SPL will - setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for - SDHCI0 controller. Platforms which have only one SDHCI controller - shouldn't enable this option because it for software SDHCI0 or SDHCI1 - are both covered by BOOT_DEVICE_MMC1. - config SPL_ZYNQMP_ALT_BOOTMODE hex default 0x0 if JTAG_MODE diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index f71ff7b3d2..64e5320acc 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -66,7 +66,9 @@ struct xfsbl_atf_handoff_params { }; #ifdef CONFIG_SPL_OS_BOOT -void handoff_setup(void) +struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr) { struct xfsbl_atf_handoff_params *atfhandoffparams; @@ -76,11 +78,16 @@ void handoff_setup(void) atfhandoffparams->magic[2] = 'N'; atfhandoffparams->magic[3] = 'X'; - atfhandoffparams->num_entries = 1; - atfhandoffparams->partition[0].entry_point = CONFIG_SYS_TEXT_BASE; - atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 << - FSBL_FLAGS_EL_SHIFT; + atfhandoffparams->num_entries = 0; + if (bl33_entry) { + atfhandoffparams->partition[0].entry_point = bl33_entry; + atfhandoffparams->partition[0].flags = FSBL_FLAGS_EL2 << + FSBL_FLAGS_EL_SHIFT; + atfhandoffparams->num_entries++; + } writel(CONFIG_SPL_TEXT_BASE, &pmu_base->gen_storage6); + + return NULL; } #endif diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index a0d776166d..fd361c5ce8 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -7,8 +7,6 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define ARASAN_NAND_BASEADDR 0xFF100000 - #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 #define ZYNQMP_TCM_SIZE 0x40000 diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h index 15e54c0493..e37acda2f8 100644 --- a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h +++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h @@ -21,5 +21,6 @@ void prog_reg(unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value); int psu_init(void); +unsigned long psu_post_config_data(void); #endif /* _PSU_INIT_GPL_H_ */ diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 10b70761de..2974ffbc2f 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -46,8 +46,6 @@ struct zynqmp_ipi_msg { int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); unsigned int zynqmp_get_silicon_version(void); -void handoff_setup(void); - int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_mmio_read(const u32 address, u32 *value); diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh new file mode 100755 index 0000000000..1e770ba111 --- /dev/null +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh @@ -0,0 +1,123 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0+ +# +# script to generate FIT image source for Xilinx ZynqMP boards with +# ARM Trusted Firmware and multiple device trees (given on the command line) +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +BL33="u-boot-nodtb.bin" +[ -z "$BL31" ] && BL31="bl31.bin" +# Can be also done as ${CROSS_COMPILE}readelf -l bl31.elf | awk '/Entry point/ { print $3 }' +[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000" + +if [ -z "$BL33_LOAD_ADDR" ];then + BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h` +fi + +DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h` +if [ ! -z "$DTB_LOAD_ADDR" ]; then + DTB_LOAD="load = <$DTB_LOAD_ADDR>;" +else + DTB_LOAD="" +fi + +if [ -z "$*" ]; then + DT=arch/arm/dts/${DEVICE_TREE}.dtb +else + DT=$* +fi + +if [ ! -f $BL31 ]; then + echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2 + BL31=/dev/null + # But U-Boot proper could be loaded in EL3 by specifying + # firmware = "uboot"; + # instead of "atf" in config node +fi + +cat << __HEADER_EOF +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + + images { + uboot { + description = "U-Boot (64-bit)"; + data = /incbin/("$BL33"); + type = "firmware"; + os = "u-boot"; + arch = "arm64"; + compression = "none"; + load = <$BL33_LOAD_ADDR>; + entry = <$BL33_LOAD_ADDR>; + hash { + algo = "md5"; + }; + }; + atf { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + os = "arm-trusted-firmware"; + arch = "arm64"; + compression = "none"; + load = <$ATF_LOAD_ADDR>; + entry = <$ATF_LOAD_ADDR>; + hash { + algo = "md5"; + }; + }; +__HEADER_EOF + +DEFAULT=1 +cnt=1 +for dtname in $DT +do + cat << __FDT_IMAGE_EOF + fdt_$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + $DTB_LOAD + hash { + algo = "md5"; + }; + }; +__FDT_IMAGE_EOF + +[ "x$(basename $dtname .dtb)" = "x${DEVICE_TREE}" ] && DEFAULT=$cnt + +cnt=$((cnt+1)) +done + +cat << __CONF_HEADER_EOF + }; + configurations { + default = "config_$DEFAULT"; + +__CONF_HEADER_EOF + +cnt=1 +for dtname in $DT +do +cat << __CONF_SECTION1_EOF + config_$cnt { + description = "$(basename $dtname .dtb)"; + firmware = "atf"; + loadables = "uboot"; + fdt = "fdt_$cnt"; + }; +__CONF_SECTION1_EOF +cnt=$((cnt+1)) +done + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c index b357de3235..b6abdfd608 100644 --- a/arch/arm/mach-zynqmp/psu_spl_init.c +++ b/arch/arm/mach-zynqmp/psu_spl_init.c @@ -77,3 +77,12 @@ __weak int psu_init(void) */ return -1; } + +__weak unsigned long psu_post_config_data(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. + */ + return 0; +} diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 6ba42bb42f..896657f51c 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -13,6 +13,7 @@ #include <asm/io.h> #include <asm/spl.h> #include <asm/arch/hardware.h> +#include <asm/arch/psu_init_gpl.h> #include <asm/arch/sys_proto.h> void board_init_f(ulong dummy) @@ -27,13 +28,6 @@ void board_init_f(ulong dummy) #endif /* Delay is required for clocks to be propagated */ udelay(1000000); - - debug("Clearing BSS 0x%p - 0x%p\n", __bss_start, __bss_end); - /* Clear the BSS */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* No need to call timer init - it is empty for ZynqMP */ - board_init_r(NULL, 0); } static void ps_mode_reset(ulong mode) @@ -60,9 +54,20 @@ void spl_board_init(void) preloader_console_init(); ps_mode_reset(MODE_RESET); board_init(); + psu_post_config_data(); } #endif +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + + if (spl_boot_list[0] == BOOT_DEVICE_MMC1) + spl_boot_list[1] = BOOT_DEVICE_MMC2; + if (spl_boot_list[0] == BOOT_DEVICE_MMC2) + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} + u32 spl_boot_device(void) { u32 reg = 0; @@ -86,11 +91,7 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_MMC_SUPPORT case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ -/* if both controllers enabled, then these two are the second controller */ -#ifdef CONFIG_SPL_ZYNQMP_TWO_SDHCI return BOOT_DEVICE_MMC2; -/* else, fall through, the one SDHCI controller that is enabled is number 1 */ -#endif case SD_MODE: case EMMC_MODE: return BOOT_DEVICE_MMC1; @@ -119,8 +120,6 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { - handoff_setup(); - return 0; } #endif @@ -131,6 +130,6 @@ int board_fit_config_name_match(const char *name) /* Just empty function now - can't decide what to choose */ debug("%s: %s\n", __func__, name); - return 0; + return -1; } #endif diff --git a/board/mediatek/mt7622/Kconfig b/board/mediatek/mt7622/Kconfig new file mode 100644 index 0000000000..d0abdc0a67 --- /dev/null +++ b/board/mediatek/mt7622/Kconfig @@ -0,0 +1,17 @@ +if TARGET_MT7622 + +config SYS_BOARD + default "mt7622" + +config SYS_CONFIG_NAME + default "mt7622" + +config MTK_BROM_HEADER_INFO + string + default "lk=1" + +config MTK_BROM_HEADER_INFO + string + default "media=nor" + +endif diff --git a/board/mediatek/mt7622/MAINTAINERS b/board/mediatek/mt7622/MAINTAINERS new file mode 100644 index 0000000000..a3e0e75ca0 --- /dev/null +++ b/board/mediatek/mt7622/MAINTAINERS @@ -0,0 +1,6 @@ +MT7622 +M: Sam Shih <sam.shih@mediatek.com> +S: Maintained +F: board/mediatek/mt7622 +F: include/configs/mt7622.h +F: configs/mt7622_rfb_defconfig diff --git a/board/mediatek/mt7622/Makefile b/board/mediatek/mt7622/Makefile new file mode 100644 index 0000000000..2c54d86fff --- /dev/null +++ b/board/mediatek/mt7622/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt7622_rfb.o + diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c new file mode 100644 index 0000000000..b9296bede2 --- /dev/null +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <common.h> +#include <config.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + return 0; +} + +int board_late_init(void) +{ + gd->env_valid = 1; //to load environment variable from persistent store + env_relocate(); + return 0; +} diff --git a/board/mediatek/mt8512/Kconfig b/board/mediatek/mt8512/Kconfig new file mode 100644 index 0000000000..87bd1fbe69 --- /dev/null +++ b/board/mediatek/mt8512/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MT8512 + +config SYS_BOARD + default "mt8512" + +config SYS_CONFIG_NAME + default "mt8512" + + +config MTK_BROM_HEADER_INFO + string + default "media=nor" + +endif diff --git a/board/mediatek/mt8512/MAINTAINERS b/board/mediatek/mt8512/MAINTAINERS new file mode 100644 index 0000000000..966b1a749d --- /dev/null +++ b/board/mediatek/mt8512/MAINTAINERS @@ -0,0 +1,6 @@ +MT8512 +M: Mingming lee <mingming.lee@mediatek.com> +S: Maintained +F: board/mediatek/mt8512 +F: include/configs/mt8512.h +F: configs/mt8512_bm1_emmc_defconfig diff --git a/board/mediatek/mt8512/Makefile b/board/mediatek/mt8512/Makefile new file mode 100644 index 0000000000..c1f596b39d --- /dev/null +++ b/board/mediatek/mt8512/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt8512.o diff --git a/board/mediatek/mt8512/mt8512.c b/board/mediatek/mt8512/mt8512.c new file mode 100644 index 0000000000..726111d7d3 --- /dev/null +++ b/board/mediatek/mt8512/mt8512.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#include <common.h> +#include <dm.h> +#include <wdt.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->ram_base + 0x100; + + debug("gd->fdt_blob is %p\n", gd->fdt_blob); + return 0; +} diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c index 500dcce4da..80f2b83b58 100644 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c @@ -220,10 +220,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0XF8000004, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U), diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README index 6171ce66f4..9375be8495 100644 --- a/board/solidrun/clearfog/README +++ b/board/solidrun/clearfog/README @@ -20,12 +20,6 @@ of "/dev/sdX" here! Install U-Boot on eMMC: ----------------------- -The ROM loads the bootloader from eMMC first boot partition at offset 0. This -is unlike load from SD card that is at offset 512. As a result, the offset of -the main U-Boot image on the eMMC boot partition changes. Set -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x140 for SPL to load U-Boot from -the correct location. - To make SPL load the main U-Boot image from the eMMC boot partition enable eMMC boot acknowledgement and boot partition with the following U-Boot command: diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c index 8be3fb1e35..360beaef8e 100644 --- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c @@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c index afec4038d3..ae4666f7d5 100644 --- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -173,14 +173,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c index d90a350d3f..717955808d 100644 --- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c @@ -171,14 +171,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index cb272eafda..73fc1be014 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -44,6 +44,15 @@ config XILINX_OF_BOARD_DTB_ADDR hex default 0x1000 if ARCH_VERSAL default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP - depends on OF_BOARD + depends on OF_BOARD || OF_SEPARATE help Offset in the memory where the board configuration DTB is placed. + +config BOOT_SCRIPT_OFFSET + hex "Boot script offset" + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL + default 0xFC0000 if ARCH_ZYNQ + default 0x3E80000 if ARCH_ZYNQMP + default 0x7F80000 if ARCH_VERSAL + help + Specifies distro boot script offset in NAND/NOR flash. diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 1c28263cb8..ae5fe2729f 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <asm/sections.h> #include <dm/uclass.h> #include <i2c.h> @@ -37,16 +38,32 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) return ret; } -#if defined(CONFIG_OF_BOARD) +#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE) void *board_fdt_blob_setup(void) { - static void *fw_dtb = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; + static void *fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; - if (fdt_magic(fw_dtb) != FDT_MAGIC) { - printf("DTB is not passed via %p\n", fw_dtb); - return NULL; - } + if (fdt_magic(fdt_blob) == FDT_MAGIC) + return fdt_blob; - return fw_dtb; + debug("DTB is not passed via %p\n", fdt_blob); + +#ifdef CONFIG_SPL_BUILD + /* FDT is at end of BSS unless it is in a different memory region */ + if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS)) + fdt_blob = (ulong *)&_image_binary_end; + else + fdt_blob = (ulong *)&__bss_end; +#else + /* FDT is at end of image */ + fdt_blob = (ulong *)&_end; +#endif + + if (fdt_magic(fdt_blob) == FDT_MAGIC) + return fdt_blob; + + debug("DTB is also not passed via %p\n", fdt_blob); + + return NULL; } #endif diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 23bb6b9623..9fa9e76e66 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -130,7 +130,14 @@ int board_late_init(void) break; case EMMC_MODE: puts("EMMC_MODE\n"); - mode = "mmc0"; + if (uclass_get_device_by_name(UCLASS_MMC, + "sdhci@f1050000", &dev)) { + puts("Boot from EMMC but without SD1 enabled!\n"); + return -1; + } + debug("mmc1 device found at %p, seq %d\n", dev, dev->seq); + mode = "mmc"; + bootseq = dev->seq; break; case SD_MODE: puts("SD_MODE\n"); @@ -196,6 +203,8 @@ int board_late_init(void) initrd_hi = round_down(initrd_hi, SZ_16M); env_set_addr("initrd_high", (void *)initrd_hi); + env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); + return 0; } diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 8d33015439..6a2acee108 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -14,7 +14,7 @@ spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F endif ifeq ($(init-objs),) -hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) +hw-platform-y :=$(shell echo $(DEVICE_TREE)) init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\ $(hw-platform-y)/ps7_init_gpl.o) endif diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index cffabe825a..420a5ca663 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -50,7 +50,7 @@ int board_late_init(void) env_set("modeboot", "sdboot"); break; case ZYNQ_BM_JTAG: - mode = "pxe dhcp"; + mode = "jtag pxe dhcp"; env_set("modeboot", "jtagboot"); break; default: @@ -76,6 +76,8 @@ int board_late_init(void) env_set("boot_targets", new_targets); + env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); + return 0; } diff --git a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c index 218307f861..82f270c2e1 100644 --- a/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-cc108/ps7_init_gpl.c @@ -227,10 +227,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), @@ -474,10 +470,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), @@ -714,10 +706,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0XE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0XF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c index 5366956e5b..75095ee3d4 100644 --- a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c @@ -219,10 +219,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0xF8000004, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index 39afd82195..337af2d964 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -7894,70 +7836,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12094,70 +11972,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index 88ff7947f2..248c72861c 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -3666,64 +3666,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -8046,70 +7988,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12359,70 +12237,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index e9e4e4d077..c84ee6b1f2 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -3635,64 +3635,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -7984,70 +7926,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12266,70 +12144,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c index 95cc25a03e..b4663818dd 100644 --- a/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm010/ps7_init_gpl.c @@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -461,10 +457,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -699,10 +691,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c index 209f5ed7aa..254a512ccb 100644 --- a/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm011-x16/ps7_init_gpl.c @@ -212,10 +212,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -446,10 +442,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -678,10 +670,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), diff --git a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c index 31c497b3e6..f4362b943b 100644 --- a/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm011/ps7_init_gpl.c @@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -442,10 +438,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), @@ -672,10 +664,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00245A55U), diff --git a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c index e966304e4a..621de09cc6 100644 --- a/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm012/ps7_init_gpl.c @@ -221,10 +221,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU), @@ -467,10 +463,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU), @@ -711,10 +703,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), EMIT_MASKWRITE(0xE000E018, 0x00001000U, 0x00001000U), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000E014, 0x00FFFFFFU, 0x00049BAAU), diff --git a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c index 5770c4d5d3..eefd46d932 100644 --- a/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc770-xm013/ps7_init_gpl.c @@ -210,10 +210,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -439,10 +435,6 @@ static unsigned long ps7_peripherals_init_data_2_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), @@ -666,10 +658,6 @@ static unsigned long ps7_peripherals_init_data_1_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000003EU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x00000FFFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKDELAY(0xF8F00200, 1), diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index df7d3535dd..7a15ea5729 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -3627,64 +3627,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -7860,70 +7802,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U @@ -12026,70 +11904,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE - // .. START: UART REGISTERS - // .. BDIV = 0x6 - // .. ==> 0XE0001034[7:0] = 0x00000006U - // .. ==> MASK : 0x000000FFU VAL : 0x00000006U - // .. - EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), - // .. CD = 0x3e - // .. ==> 0XE0001018[15:0] = 0x0000003EU - // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU - // .. - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), - // .. STPBRK = 0x0 - // .. ==> 0XE0001000[8:8] = 0x00000000U - // .. ==> MASK : 0x00000100U VAL : 0x00000000U - // .. STTBRK = 0x0 - // .. ==> 0XE0001000[7:7] = 0x00000000U - // .. ==> MASK : 0x00000080U VAL : 0x00000000U - // .. RSTTO = 0x0 - // .. ==> 0XE0001000[6:6] = 0x00000000U - // .. ==> MASK : 0x00000040U VAL : 0x00000000U - // .. TXDIS = 0x0 - // .. ==> 0XE0001000[5:5] = 0x00000000U - // .. ==> MASK : 0x00000020U VAL : 0x00000000U - // .. TXEN = 0x1 - // .. ==> 0XE0001000[4:4] = 0x00000001U - // .. ==> MASK : 0x00000010U VAL : 0x00000010U - // .. RXDIS = 0x0 - // .. ==> 0XE0001000[3:3] = 0x00000000U - // .. ==> MASK : 0x00000008U VAL : 0x00000000U - // .. RXEN = 0x1 - // .. ==> 0XE0001000[2:2] = 0x00000001U - // .. ==> MASK : 0x00000004U VAL : 0x00000004U - // .. TXRES = 0x1 - // .. ==> 0XE0001000[1:1] = 0x00000001U - // .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. RXRES = 0x1 - // .. ==> 0XE0001000[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. - EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), - // .. IRMODE = 0x0 - // .. ==> 0XE0001004[11:11] = 0x00000000U - // .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. UCLKEN = 0x0 - // .. ==> 0XE0001004[10:10] = 0x00000000U - // .. ==> MASK : 0x00000400U VAL : 0x00000000U - // .. CHMODE = 0x0 - // .. ==> 0XE0001004[9:8] = 0x00000000U - // .. ==> MASK : 0x00000300U VAL : 0x00000000U - // .. NBSTOP = 0x0 - // .. ==> 0XE0001004[7:6] = 0x00000000U - // .. ==> MASK : 0x000000C0U VAL : 0x00000000U - // .. PAR = 0x4 - // .. ==> 0XE0001004[5:3] = 0x00000004U - // .. ==> MASK : 0x00000038U VAL : 0x00000020U - // .. CHRL = 0x0 - // .. ==> 0XE0001004[2:1] = 0x00000000U - // .. ==> MASK : 0x00000006U VAL : 0x00000000U - // .. CLKS = 0x0 - // .. ==> 0XE0001004[0:0] = 0x00000000U - // .. ==> MASK : 0x00000001U VAL : 0x00000000U - // .. - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), - // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U diff --git a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c index d4f0ee796f..5d573868cb 100644 --- a/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zturn/ps7_init_gpl.c @@ -222,14 +222,6 @@ static unsigned long ps7_peripherals_init_data[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0xF8000004, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), - EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U), diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c index f1b9357780..7c6bc9fa3f 100644 --- a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c @@ -235,10 +235,6 @@ static unsigned long ps7_peripherals_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), EMIT_WRITE(0xF8000004, 0x0000767BU), - EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), - EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), - EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), - EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00004000U), diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c index c41283704c..fda6d18dd9 100644 --- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c @@ -3647,64 +3647,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. FINISH: LOCK IT BACK */ /* .. START: SRAM/NOR SET OPMODE */ /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -7944,70 +7886,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. FINISH: LOCK IT BACK */ /* .. START: SRAM/NOR SET OPMODE */ /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. IRMODE = 0x0 */ - /* .. ==> 0XE0001004[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. UCLKEN = 0x0 */ - /* .. ==> 0XE0001004[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -12172,70 +12050,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. FINISH: LOCK IT BACK */ /* .. START: SRAM/NOR SET OPMODE */ /* .. FINISH: SRAM/NOR SET OPMODE */ - /* .. START: UART REGISTERS */ - /* .. BDIV = 0x6 */ - /* .. ==> 0XE0001034[7:0] = 0x00000006U */ - /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ - /* .. */ - EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x7c */ - /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ - /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), - /* .. STPBRK = 0x0 */ - /* .. ==> 0XE0001000[8:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ - /* .. STTBRK = 0x0 */ - /* .. ==> 0XE0001000[7:7] = 0x00000000U */ - /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */ - /* .. RSTTO = 0x0 */ - /* .. ==> 0XE0001000[6:6] = 0x00000000U */ - /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */ - /* .. TXDIS = 0x0 */ - /* .. ==> 0XE0001000[5:5] = 0x00000000U */ - /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */ - /* .. TXEN = 0x1 */ - /* .. ==> 0XE0001000[4:4] = 0x00000001U */ - /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */ - /* .. RXDIS = 0x0 */ - /* .. ==> 0XE0001000[3:3] = 0x00000000U */ - /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */ - /* .. RXEN = 0x1 */ - /* .. ==> 0XE0001000[2:2] = 0x00000001U */ - /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */ - /* .. TXRES = 0x1 */ - /* .. ==> 0XE0001000[1:1] = 0x00000001U */ - /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ - /* .. RXRES = 0x1 */ - /* .. ==> 0XE0001000[0:0] = 0x00000001U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ - /* .. */ - EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U), - /* .. IRMODE = 0x0 */ - /* .. ==> 0XE0001004[11:11] = 0x00000000U */ - /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */ - /* .. UCLKEN = 0x0 */ - /* .. ==> 0XE0001004[10:10] = 0x00000000U */ - /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */ - /* .. CHMODE = 0x0 */ - /* .. ==> 0XE0001004[9:8] = 0x00000000U */ - /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */ - /* .. NBSTOP = 0x0 */ - /* .. ==> 0XE0001004[7:6] = 0x00000000U */ - /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */ - /* .. PAR = 0x4 */ - /* .. ==> 0XE0001004[5:3] = 0x00000004U */ - /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */ - /* .. CHRL = 0x0 */ - /* .. ==> 0XE0001004[2:1] = 0x00000000U */ - /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */ - /* .. CLKS = 0x0 */ - /* .. ==> 0XE0001004[0:0] = 0x00000000U */ - /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ - /* .. */ - EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), - /* .. FINISH: UART REGISTERS */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile index 5ace6cc1b4..174f4ed24b 100644 --- a/board/xilinx/zynqmp/Makefile +++ b/board/xilinx/zynqmp/Makefile @@ -14,7 +14,7 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN endif ifeq ($(init-objs),) -hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) +hw-platform-y :=$(shell echo $(DEVICE_TREE)) init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\ $(hw-platform-y)/psu_init_gpl.o) endif diff --git a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c index ac3f716392..d030e79770 100644 --- a/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c +++ b/board/xilinx/zynqmp/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0/psu_init_gpl.c @@ -506,14 +506,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c index ac4a073e1b..be9992c90f 100644 --- a/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c @@ -479,14 +479,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-a2197-g-revA b/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA index a64c140b86..a64c140b86 120000 --- a/board/xilinx/zynqmp/zynqmp-a2197-g-revA +++ b/board/xilinx/zynqmp/zynqmp-g-a2197-00-revA diff --git a/board/xilinx/zynqmp/zynqmp-a2197-m-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA index a64c140b86..a64c140b86 120000 --- a/board/xilinx/zynqmp/zynqmp-a2197-m-revA +++ b/board/xilinx/zynqmp/zynqmp-m-a2197-01-revA diff --git a/board/xilinx/zynqmp/zynqmp-a2197-p-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA index a64c140b86..a64c140b86 120000 --- a/board/xilinx/zynqmp/zynqmp-a2197-p-revA +++ b/board/xilinx/zynqmp/zynqmp-m-a2197-02-revA diff --git a/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA new file mode 120000 index 0000000000..a64c140b86 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-m-a2197-03-revA @@ -0,0 +1 @@ +zynqmp-a2197-revA
\ No newline at end of file diff --git a/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA new file mode 120000 index 0000000000..a64c140b86 --- /dev/null +++ b/board/xilinx/zynqmp/zynqmp-p-a2197-00-revA @@ -0,0 +1 @@ +zynqmp-a2197-revA
\ No newline at end of file diff --git a/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c index af6b49a973..b8ea291f8b 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c @@ -388,10 +388,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c index a5a33b9f17..520fff28f9 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c @@ -378,10 +378,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U); psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c index d1090fae4a..d3eb713e9e 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c @@ -427,10 +427,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c index f73e997f7d..6b0705df38 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/psu_init_gpl.c @@ -475,10 +475,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c index 9ead77d069..59de4373b6 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/psu_init_gpl.c @@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c index 9ead77d069..59de4373b6 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/psu_init_gpl.c @@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c index 9ead77d069..59de4373b6 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/psu_init_gpl.c @@ -477,14 +477,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00000018U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c index db07456c15..e0b71abd51 100644 --- a/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/psu_init_gpl.c @@ -471,14 +471,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c index e1fdabaeb9..e01915f7ed 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c @@ -409,7 +409,6 @@ static unsigned long psu_mio_init_data(void) psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); @@ -499,14 +498,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); @@ -990,3 +981,9 @@ int psu_init(void) return 1; return 0; } + +unsigned long psu_post_config_data(void) +{ + psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); + return 0; +} diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c index 3e981d8419..6adbf5e234 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/psu_init_gpl.c @@ -479,14 +479,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c index 5f21c47475..8ecd9ee90b 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c @@ -486,14 +486,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0xC5ACCE55U); psu_mask_write(0xFE980004, 0x80000000U, 0x80000000U); psu_mask_write(0xFE980FB0, 0xFFFFFFFFU, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c index 12ef5b4b0a..4805e5a3b9 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c @@ -455,14 +455,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); psu_mask_write(0xFD4AB120, 0x00000007U, 0x00000007U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c index fcd6a46ad9..15f0be1a43 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c @@ -463,14 +463,6 @@ static unsigned long psu_peripherals_init_data(void) psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U); psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U); - psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U); - psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U); - psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU); - psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U); - psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U); psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index aac2eb7bc1..8bdc67748e 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -580,8 +580,17 @@ int board_late_init(void) break; case EMMC_MODE: puts("EMMC_MODE\n"); - mode = "mmc0"; - env_set("modeboot", "emmcboot"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@ff160000", &dev) && + uclass_get_device_by_name(UCLASS_MMC, + "sdhci@ff160000", &dev)) { + puts("Boot from EMMC but without SD0 enabled!\n"); + return -1; + } + debug("mmc0 device found at %p, seq %d\n", dev, dev->seq); + + mode = "mmc"; + bootseq = dev->seq; break; case SD_MODE: puts("SD_MODE\n"); @@ -658,6 +667,8 @@ int board_late_init(void) initrd_hi = round_down(initrd_hi, SZ_16M); env_set_addr("initrd_high", (void *)initrd_hi); + env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); + reset_reason(); return 0; diff --git a/cmd/blk_common.c b/cmd/blk_common.c index c5514cf8f8..cc6e161ba0 100644 --- a/cmd/blk_common.c +++ b/cmd/blk_common.c @@ -32,7 +32,8 @@ int blk_common_cmd(int argc, char * const argv[], enum if_type if_type, return 0; } else if (strncmp(argv[1], "part", 4) == 0) { if (blk_list_part(if_type)) - printf("\nno %s devices available\n", if_name); + printf("\nno %s partition table available\n", + if_name); return 0; } return CMD_RET_USAGE; diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 61488daa3c..76f39dc04f 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -329,6 +329,18 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR Address on the MMC to load U-Boot from, when the MMC is being used in raw mode. Units: MMC sectors (1 sector = 512 bytes). +config SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET + hex "U-Boot main hardware partition image offset" + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR + default 0x0 + help + On some platforms SPL location depends on hardware partition. The ROM + code skips the MBR sector when loading SPL from main hardware data + partition. This adds offset to the main U-Boot image. Set this symbol + to the number of skipped sectors. + + If unsure, leave the default. + config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION bool "MMC Raw mode: by partition" help @@ -488,7 +500,7 @@ config TPL_HASH_SUPPORT this option to build system-specific drivers for hash acceleration as part of an SPL build. -config SPL_DMA_SUPPORT +config SPL_DMA bool "Support DMA drivers" help Enable DMA (direct-memory-access) drivers in SPL. These drivers diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c index df29274207..702367b2a2 100644 --- a/common/spl/spl_atf.c +++ b/common/spl/spl_atf.c @@ -18,20 +18,7 @@ static struct bl2_to_bl31_params_mem bl31_params_mem; static struct bl31_params *bl2_to_bl31_params; -/** - * bl2_plat_get_bl31_params() - prepare params for bl31. - * - * This function assigns a pointer to the memory that the platform has kept - * aside to pass platform specific and trusted firmware related information - * to BL31. This memory is allocated by allocating memory to - * bl2_to_bl31_params_mem structure which is a superset of all the - * structure whose information is passed to BL31 - * NOTE: This function should be called only once and should be done - * before generating params to BL31 - * - * @return bl31 params structure pointer - */ -static struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, +__weak struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, uintptr_t bl33_entry, uintptr_t fdt_addr) { @@ -112,7 +99,7 @@ static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry, static int spl_fit_images_find(void *blob, int os) { - int parent, node, ndepth; + int parent, node, ndepth = 0; const void *data; if (!blob) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 2ede096e61..3e6a17c110 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -49,6 +49,16 @@ static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf); } +static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part) +{ +#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR) + if (part == 0) + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET; +#endif + + return 0; +} + static __maybe_unused int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct mmc *mmc, unsigned long sector) @@ -325,7 +335,7 @@ int spl_mmc_load(struct spl_image_info *spl_image, static struct mmc *mmc; u32 boot_mode; int err = 0; - __maybe_unused int part; + __maybe_unused int part = 0; /* Perform peripheral init only once */ if (!mmc) { @@ -391,7 +401,8 @@ int spl_mmc_load(struct spl_image_info *spl_image, return err; #endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR - err = mmc_load_image_raw_sector(spl_image, mmc, raw_sect); + err = mmc_load_image_raw_sector(spl_image, mmc, + raw_sect + spl_mmc_raw_uboot_offset(part)); if (!err) return err; #endif diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 0c6a2e9193..6386157b49 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -23,7 +23,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 3c57dfb031..4eb83497d1 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -28,7 +28,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 87f391c2b0..260649b06f 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -29,7 +29,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index cd9090621b..4911bbcfbf 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -26,7 +26,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig deleted file mode 100644 index 43aacf322b..0000000000 --- a/configs/avnet_ultra96_rev1_defconfig +++ /dev/null @@ -1,90 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff010000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000 -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_BOOTMENU=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="avnet-ultra96-rev1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -# CONFIG_NETDEVICES is not set -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQ_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_WDT=y -CONFIG_WDT_CDNS=y -CONFIG_SPL_GZIP=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig index 177558db41..71e0d2726e 100644 --- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig +++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig @@ -7,7 +7,6 @@ CONFIG_DEBUG_UART_BASE=0xff000000 CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y CONFIG_DEBUG_UART=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y @@ -57,5 +56,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_PANIC_HANG=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 787c6360a7..b48a4abfcb 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -26,7 +26,8 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x1 +CONFIG_SPL_DM_GPIO=y CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 8535aaecee..dc1300d901 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -25,7 +25,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 537b3b625d..ea19c2db33 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -29,7 +29,7 @@ CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_BOOTCOUNT_LIMIT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_SAVEENV=y CONFIG_SPL_I2C_SUPPORT=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 676dee81da..7551db805e 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -29,7 +29,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 012c2f608e..f09cd354f6 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -23,7 +23,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 70f9cc722b..8c8b638b14 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -28,7 +28,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 15dc7a77e5..564aa6c447 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -30,7 +30,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index b22a79ba8f..5441b429cf 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -30,7 +30,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_POWER_SUPPORT=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index ecaa047cee..8a456bf50a 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -30,7 +30,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_POWER_SUPPORT=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 5f80663cb6..5008178116 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -30,7 +30,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index aaa7e31a93..c7a1e15a79 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -24,7 +24,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0 CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_DM_GPIO=y CONFIG_SPL_FORCE_MMC_BOOT=y CONFIG_SPL_MMC_TINY=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index 38561259ad..26c0a3e15b 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -19,7 +19,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_BOUNCE_BUFFER=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index a3e2e16c84..86ecfc467d 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -20,7 +20,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 81464add3f..a0df286f3a 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -24,7 +24,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_SPL_RAW_IMAGE_SUPPORT=y CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index a3e2e16c84..86ecfc467d 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -20,7 +20,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="icorem6qdl> " diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig index a344ad1457..bb3fc6ce00 100644 --- a/configs/imx6ul_geam_nand_defconfig +++ b/configs/imx6ul_geam_nand_defconfig @@ -20,7 +20,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="geam6ul> " diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig index 27ec906661..df32505a80 100644 --- a/configs/imx6ul_isiot_nand_defconfig +++ b/configs/imx6ul_isiot_nand_defconfig @@ -20,7 +20,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="isiotmx6ul> " diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig new file mode 100644 index 0000000000..e1917e70e7 --- /dev/null +++ b/configs/mt7622_rfb_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7622=y +CONFIG_SYS_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_FIT=y +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_LOG_MAX_LEVEL=6 +CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" +CONFIG_SYS_PROMPT="MT7622> " +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SMC=y +CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7622=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SNFI_SPI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_TIMER=y +CONFIG_MTK_TIMER=y +CONFIG_WDT_MTK=y +CONFIG_LZ4=y +CONFIG_LZO=y +CONFIG_HEXDUMP=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 58e93d5da6..d6ccae1942 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7623=y CONFIG_SYS_TEXT_BASE=0x81e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ENV_SIZE=0x1000 diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig new file mode 100644 index 0000000000..ee3b8e1ed1 --- /dev/null +++ b/configs/mt8512_bm1_emmc_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_SYS_TEXT_BASE=0x44e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_MT8512=y +CONFIG_SYS_PROMPT="MT8512> " +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_OF_LIBFDT=y +# CONFIG_FDT_DEBUG is not set +CONFIG_LZMA=y +CONFIG_LZ4=y +CONFIG_LZO=y +CONFIG_GZIP=y +CONFIG_BZIP2=y +CONFIG_CMD_BOOTMENU=y +CONFIG_MENU_SHOW=y +CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb" +CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc" +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MT8512=y +CONFIG_PINCONF=y +CONFIG_DM_GPIO=y +CONFIG_RAM=y +CONFIG_BAUDRATE=921600 +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_WDT=y +CONFIG_WDT_MTK=y +CONFIG_CLK=y +CONFIG_TIMER=y +CONFIG_MTK_TIMER=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +# CONFIG_ENV_IS_IN_MMC is not set diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index d2506f2567..c79eedb50f 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -25,7 +25,7 @@ CONFIG_BOOTDELAY=3 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index c2cc796650..e7378151fa 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -25,7 +25,7 @@ CONFIG_BOOTDELAY=3 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig index 96bb5325b5..f8329d718d 100644 --- a/configs/platinum_picon_defconfig +++ b/configs/platinum_picon_defconfig @@ -20,7 +20,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig index c818eaac56..46a02cdefc 100644 --- a/configs/platinum_titanium_defconfig +++ b/configs/platinum_titanium_defconfig @@ -20,7 +20,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_MISC_INIT_R=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 11428e1e03..6488bca2c0 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -9,7 +9,6 @@ CONFIG_FIT_VERBOSE=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=5 CONFIG_SUPPORT_RAW_INITRD=y -# CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig deleted file mode 100644 index 0e6d8b518a..0000000000 --- a/configs/xilinx_zynqmp_a2197_revA_defconfig +++ /dev/null @@ -1,113 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA" -CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-g-a2197-00-revA zynqmp-p-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig deleted file mode 100644 index faf7e45a9a..0000000000 --- a/configs/xilinx_zynqmp_e_a2197_00_revA_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-e-a2197-00-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig deleted file mode 100644 index abef223df8..0000000000 --- a/configs/xilinx_zynqmp_g_a2197_00_revA_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-g-a2197-00-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig deleted file mode 100644 index db5eccc436..0000000000 --- a/configs/xilinx_zynqmp_m_a2197_01_revA_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-01-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig deleted file mode 100644 index 9228ce186e..0000000000 --- a/configs/xilinx_zynqmp_m_a2197_02_revA_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-02-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig b/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig deleted file mode 100644 index af2ab307d8..0000000000 --- a/configs/xilinx_zynqmp_m_a2197_03_revA_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-m-a2197-03-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index e861cf6910..d953c91a66 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -49,4 +49,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set # CONFIG_MMC is not set +CONFIG_PANIC_HANG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 644223633b..cb2983d247 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -55,4 +55,5 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_PANIC_HANG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 5b468f1cfa..f7bec364c3 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -55,4 +55,5 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_PANIC_HANG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index d490f357b7..01e0971991 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -51,4 +51,5 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ARASAN=y CONFIG_SYS_NAND_MAX_CHIPS=2 +CONFIG_PANIC_HANG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 21aafe1d27..20e76cb11e 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -50,4 +50,5 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ARASAN=y +CONFIG_PANIC_HANG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 902dceb0f6..c6e03cd256 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -62,4 +62,5 @@ CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI=y CONFIG_ZYNQMP_GQSPI=y +CONFIG_PANIC_HANG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig b/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig deleted file mode 100644 index ba2cbaba58..0000000000 --- a/configs/xilinx_zynqmp_p_a2197_00_revA_defconfig +++ /dev/null @@ -1,112 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal" -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-p-a2197-00-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index c7e365d009..2327eeee4a 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -16,10 +17,14 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_FPGA_LOADBP=y @@ -29,15 +34,19 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SDRAM=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_BOARD=y -CONFIG_ENV_IS_IN_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" +CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y @@ -53,7 +62,9 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y CONFIG_XILINX_GPIO=y +CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_I2C_MUX=y @@ -65,29 +76,41 @@ CONFIG_I2C_EEPROM=y CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 CONFIG_SYS_I2C_EEPROM_ADDR=0x0 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_ARASAN=y +CONFIG_SYS_NAND_MAX_CHIPS=2 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_MARVELL=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TI=y CONFIG_PHY_VITESSE=y +CONFIG_PHY_XILINX_GMII2RGMII=y CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_ZYNQ_GEM=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_ZYNQ_SERIAL=y CONFIG_SPI=y +CONFIG_ZYNQ_SPI=y CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -101,4 +124,13 @@ CONFIG_USB_GADGET_MANUFACTURER="Xilinx" CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_FUNCTION_THOR=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_WDT=y +CONFIG_WDT_CDNS=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_GZIP=y +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig deleted file mode 100644 index 73617cedd2..0000000000 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -# CONFIG_SPL_FS_FAT is not set -# CONFIG_SPL_LIBDISK_SUPPORT is not set -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -# CONFIG_CMD_NET is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_MISC=y -# CONFIG_MMC is not set -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig deleted file mode 100644 index 3341af1444..0000000000 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -# CONFIG_SPL_FS_FAT is not set -# CONFIG_SPL_LIBDISK_SUPPORT is not set -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -# CONFIG_CMD_NET is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_MISC=y -# CONFIG_MMC is not set -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig deleted file mode 100644 index 7c10770d28..0000000000 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ /dev/null @@ -1,95 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_ZYNQMP_USB=y -CONFIG_SPL_ZYNQMP_TWO_SDHCI=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_HS200_SUPPORT=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig deleted file mode 100644 index f05050da98..0000000000 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ /dev/null @@ -1,87 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -# CONFIG_SPL_FS_FAT is not set -# CONFIG_SPL_LIBDISK_SUPPORT is not set -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND_LOCK_UNLOCK=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_MISC=y -# CONFIG_MMC is not set -CONFIG_DM_MMC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_ARASAN=y -CONFIG_SYS_NAND_MAX_CHIPS=2 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig deleted file mode 100644 index 9099c582e5..0000000000 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ /dev/null @@ -1,82 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff010000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm017-dc3" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_MISC=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_ARASAN=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig deleted file mode 100644 index 499bf1b278..0000000000 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_MISC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig deleted file mode 100644 index e1cc924251..0000000000 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_MISC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig deleted file mode 100644 index d53a0366e5..0000000000 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ /dev/null @@ -1,87 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff010000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000 -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_BOOTMENU=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_BIND=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -# CONFIG_NETDEVICES is not set -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQ_SPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_USB_ETHER=y -CONFIG_USB_ETH_CDC=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_SPL_GZIP=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig deleted file mode 100644 index 04daccfc88..0000000000 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-rev1.0" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_GPIO_HOG=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig deleted file mode 100644 index c5a3c619ba..0000000000 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ /dev/null @@ -1,111 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_GPIO_HOG=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_SPL_GZIP=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig deleted file mode 100644 index 23341d609d..0000000000 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ /dev/null @@ -1,110 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_SYS_ALT_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SDRAM=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_GPIO_HOG=y -CONFIG_XILINX_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig deleted file mode 100644 index 8a81111f4b..0000000000 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ /dev/null @@ -1,91 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig deleted file mode 100644 index 7068ad39a9..0000000000 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ /dev/null @@ -1,95 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu104-revC" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig deleted file mode 100644 index 2878d2d008..0000000000 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu106-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Xilinx" -CONFIG_USB_GADGET_VENDOR_NUM=0x03FD -CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 -CONFIG_USB_FUNCTION_THOR=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig deleted file mode 100644 index 40cae18ab6..0000000000 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ /dev/null @@ -1,93 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu111-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig deleted file mode 100644 index 279fa5d435..0000000000 --- a/configs/xilinx_zynqmp_zcu1275_revA_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -# CONFIG_SPL_FS_FAT is not set -# CONFIG_SPL_LIBDISK_SUPPORT is not set -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -# CONFIG_CMD_NET is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revA" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SPL_DM=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_MISC=y -# CONFIG_MMC is not set -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig deleted file mode 100644 index 0a334260ed..0000000000 --- a/configs/xilinx_zynqmp_zcu1275_revB_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -# CONFIG_SPL_FS_FAT is not set -# CONFIG_SPL_LIBDISK_SUPPORT is not set -CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_NET is not set -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu1275-revB" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_CLK_ZYNQMP=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_MISC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_PHY_XILINX_GMII2RGMII=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu216_revA_defconfig b/configs/xilinx_zynqmp_zcu216_revA_defconfig deleted file mode 100644 index 48d760a962..0000000000 --- a/configs/xilinx_zynqmp_zcu216_revA_defconfig +++ /dev/null @@ -1,94 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_SPL=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_ZYNQMP_USB=y -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_ATF=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y -CONFIG_CMD_FPGA_LOADP=y -CONFIG_CMD_FPGA_LOAD_SECURE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu216-revA" -CONFIG_ENV_IS_IN_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI_AHCI=y -CONFIG_SATA_CEVA=y -CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_CADENCE=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20 -CONFIG_SYS_I2C_EEPROM_ADDR=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SF_DUAL_FLASH=y -CONFIG_SPI_FLASH_ISSI=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TI=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_FIXED=y -CONFIG_PHY_GIGE=y -CONFIG_MII=y -CONFIG_ZYNQ_GEM=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_ZYNQ_SERIAL=y -CONFIG_SPI=y -CONFIG_ZYNQMP_GQSPI=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/doc/README.SPL b/doc/README.SPL index 3c931ec720..929b9672b0 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -59,7 +59,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) CONFIG_SPL_POWER_SUPPORT (drivers/power/libpower.o) CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/raw/libnand.o) CONFIG_SPL_DRIVERS_MISC_SUPPORT (drivers/misc) -CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) +CONFIG_SPL_DMA (drivers/dma/libdma.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/raw/nand_spl_load.o) CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) diff --git a/drivers/Makefile b/drivers/Makefile index e7b5d22b1d..23501fd743 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -45,7 +45,7 @@ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ obj-$(CONFIG_SPL_DM_RESET) += reset/ -obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ +obj-$(CONFIG_SPL_DMA) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USB_ETHER) += net/phy/ diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 9aa8537004..93cb490eb5 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -344,6 +344,34 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) return clk_get_by_index(dev, index, clk); } +int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) +{ + int index; + + debug("%s(node=%p, name=%s, clk=%p)\n", __func__, + ofnode_get_name(node), name, clk); + clk->dev = NULL; + + index = ofnode_stringlist_search(node, "clock-names", name); + if (index < 0) { + debug("fdt_stringlist_search() failed: %d\n", index); + return index; + } + + return clk_get_by_index_nodev(node, index, clk); +} + +int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk) +{ + int ret; + + ret = clk_get_by_name_nodev(node, name, clk); + if (ret == -ENODATA) + return 0; + + return ret; +} + int clk_release_all(struct clk *clk, int count) { int i, ret; @@ -391,7 +419,7 @@ int clk_free(struct clk *clk) const struct clk_ops *ops; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -406,7 +434,7 @@ ulong clk_get_rate(struct clk *clk) const struct clk_ops *ops; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -422,7 +450,7 @@ struct clk *clk_get_parent(struct clk *clk) struct clk *pclk; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return NULL; pdev = dev_get_parent(clk->dev); @@ -439,7 +467,7 @@ long long clk_get_parent_rate(struct clk *clk) struct clk *pclk; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; pclk = clk_get_parent(clk); @@ -462,7 +490,7 @@ ulong clk_set_rate(struct clk *clk, ulong rate) const struct clk_ops *ops; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -477,7 +505,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) const struct clk_ops *ops; debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -494,7 +522,7 @@ int clk_enable(struct clk *clk) int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -554,7 +582,7 @@ int clk_disable(struct clk *clk) int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -678,7 +706,7 @@ struct clk *devm_clk_get_optional(struct udevice *dev, const char *id) { struct clk *clk = devm_clk_get(dev, id); - if (IS_ERR(clk)) + if (PTR_ERR(clk) == -ENODATA) return NULL; return clk; diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index f51126793e..2c20eddb0b 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -13,8 +13,15 @@ static ulong clk_fixed_rate_get_rate(struct clk *clk) return to_clk_fixed_rate(clk->dev)->fixed_rate; } +/* avoid clk_enable() return -ENOSYS */ +static int dummy_enable(struct clk *clk) +{ + return 0; +} + const struct clk_ops clk_fixed_rate_ops = { .get_rate = clk_fixed_rate_get_rate, + .enable = dummy_enable, }; static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e92bcd4efe..237fd17f16 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,7 +3,9 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o # SoC Drivers +obj-$(CONFIG_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o +obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c new file mode 100644 index 0000000000..a5b61a190b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7622 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/arch-mediatek/reset.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt7622-clk.h> + +#include "clk-mtk.h" + +#define MT7622_CLKSQ_STB_CON0 0x20 +#define MT7622_PLL_ISO_CON0 0x2c +#define MT7622_PLL_FMAX (2500UL * MHZ) +#define MT7622_CON0_RST_BAR BIT(24) + +#define MCU_AXI_DIV 0x640 +#define AXI_DIV_MSK GENMASK(4, 0) +#define AXI_DIV_SEL(x) (x) + +#define MCU_BUS_MUX 0x7c0 +#define MCU_BUS_MSK GENMASK(10, 9) +#define MCU_BUS_SEL(x) ((x) << 9) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT7622_CON0_RST_BAR, \ + .fmax = MT7622_PLL_FMAX, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, + 21, 0x204, 24, 0x204, 0), + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + 21, 0x214, 24, 0x214, 0), + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + 7, 0x224, 24, 0x224, 14), + PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, + 21, 0x300, 1, 0x304, 0), + PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, + 21, 0x314, 1, 0x318, 0), + PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0, + 31, 0x324, 1, 0x328, 0), + PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0, + 31, 0x334, 1, 0x338, 0), + PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0, + 21, 0x344, 1, 0x348, 0), + PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, + 21, 0x358, 1, 0x35c, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), + FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4), + FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), + FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), + FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), + FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), + FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), + FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10), + FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28), + FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112), + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), + FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48), + FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), + FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80), + FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7), + FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), + FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), + FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1), + FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), + FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1), + FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1), + FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2), + FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4), + FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), + FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), + FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), +}; + +static const int axi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL_D7 +}; + +static const int mem_parents[] = { + CLK_XTAL, + CLK_TOP_DMPLL +}; + +static const int ddrphycfg_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8 +}; + +static const int eth_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + -1, + CLK_TOP_UNIVPLL_D7 +}; + +static const int pwm_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int f10m_ref_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL4_D16 +}; + +static const int nfi_infra_parents[] = { + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D4 +}; + +static const int flash_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D80_D4, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int uart_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi0_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int spi1_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int msdc30_0_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D16, + CLK_TOP_UNIV48M +}; + +static const int a1sys_hp_parents[] = { + CLK_XTAL, + CLK_TOP_AUD1PLL, + CLK_TOP_AUD2PLL, + CLK_XTAL +}; + +static const int intdir_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL_D2, + CLK_TOP_SGMIIPLL +}; + +static const int aud_intbus_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL3_D2 +}; + +static const int pmicspi_parents[] = { + CLK_XTAL, + -1, + -1, + -1, + -1, + CLK_TOP_UNIVPLL2_D16 +}; + +static const int atb_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int audio_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_UNIVPLL1_D16 +}; + +static const int usb20_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_XTAL +}; + +static const int aud1_parents[] = { + CLK_XTAL, + CLK_TOP_AUD1PLL +}; + +static const int asm_l_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int apll1_ck_parents[] = { + CLK_TOP_AUD1_SEL, + CLK_TOP_AUD2_SEL +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23), + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31), + + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31), + + /* CLK_CFG_5 */ + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, + CLK_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), + MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23), + MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31), + + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7), + MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23), + + /* CLK_AUDDIV_0 */ + MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1), + MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1), + MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1), + MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1), + MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1), + MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1), +}; + +/* infracfg */ +static const struct mtk_gate_regs infra_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +#define GATE_INFRA(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_cgs[] = { + GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0), + GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), + GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5), + GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16), + GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18), + GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22), +}; + +/* pericfg */ +static const struct mtk_gate_regs peri0_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x10, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs peri1_cg_regs = { + .set_ofs = 0xC, + .clr_ofs = 0x14, + .sta_ofs = 0x1C, +}; + +#define GATE_PERI0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_PERI1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate peri_cgs[] = { + /* PERI0 */ + GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), + GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2), + GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3), + GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4), + GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5), + GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6), + GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7), + GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8), + GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), + GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), + GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), + GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17), + GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), + GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), + GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22), + GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23), + GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), + GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), + GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), + GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), + GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), + GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), + GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31), + + /* PERI1 */ + GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1), + GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2), +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = ð_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), + GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), + GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), + GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), + GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9), +}; + +static const struct mtk_gate_regs sgmii_cg_regs = { + .sta_ofs = 0xE4, +}; + +#define GATE_SGMII(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &sgmii_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + +static const struct mtk_gate sgmii_cgs[] = { + GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2), + GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4), + GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), +}; + +static const struct mtk_clk_tree mt7622_clk_tree = { + .xtal_rate = 25 * MHZ, + .xtal2_rate = 25 * MHZ, + .fdivs_offs = CLK_TOP_TO_USB3_SYS, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt7622_mcucfg_probe(struct udevice *dev) +{ + void __iomem *base; + + base = dev_read_addr_ptr(dev); + if (!base) + return -ENOENT; + + clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, + AXI_DIV_SEL(0x12)); + clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK, + MCU_BUS_SEL(0x1)); + + return 0; +} + +static int mt7622_apmixedsys_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + int ret; + + ret = mtk_common_clk_init(dev, &mt7622_clk_tree); + if (ret) + return ret; + + /* reduce clock square disable time */ + // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0); + writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0); + + /* extend pwr/iso control timing to 1us */ + writel(0x80008, priv->base + MT7622_PLL_ISO_CON0); + + return 0; +} + +static int mt7622_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7622_clk_tree); +} + +static int mt7622_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs); +} + +static int mt7622_pericfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs); +} + +static int mt7622_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); +} + +static int mt7622_ethsys_bind(struct udevice *dev) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RESET_MEDIATEK) + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); +#endif + + return ret; +} + +static int mt7622_sgmiisys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs); +} + +static const struct udevice_id mt7622_apmixed_compat[] = { + { .compatible = "mediatek,mt7622-apmixedsys" }, + { } +}; + +static const struct udevice_id mt7622_topckgen_compat[] = { + { .compatible = "mediatek,mt7622-topckgen" }, + { } +}; + +static const struct udevice_id mt7622_infracfg_compat[] = { + { .compatible = "mediatek,mt7622-infracfg", }, + { } +}; + +static const struct udevice_id mt7622_pericfg_compat[] = { + { .compatible = "mediatek,mt7622-pericfg", }, + { } +}; + +static const struct udevice_id mt7622_ethsys_compat[] = { + { .compatible = "mediatek,mt7622-ethsys", }, + { } +}; + +static const struct udevice_id mt7622_sgmiisys_compat[] = { + { .compatible = "mediatek,mt7622-sgmiisys", }, + { } +}; + +static const struct udevice_id mt7622_mcucfg_compat[] = { + { .compatible = "mediatek,mt7622-mcucfg" }, + { } +}; + +U_BOOT_DRIVER(mtk_mcucfg) = { + .name = "mt7622-mcucfg", + .id = UCLASS_SYSCON, + .of_match = mt7622_mcucfg_compat, + .probe = mt7622_mcucfg_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7622-clock-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt7622_apmixed_compat, + .probe = mt7622_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7622-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7622_topckgen_compat, + .probe = mt7622_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7622-clock-infracfg", + .id = UCLASS_CLK, + .of_match = mt7622_infracfg_compat, + .probe = mt7622_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_pericfg) = { + .name = "mt7622-clock-pericfg", + .id = UCLASS_CLK, + .of_match = mt7622_pericfg_compat, + .probe = mt7622_pericfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7622-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7622_ethsys_compat, + .probe = mt7622_ethsys_probe, + .bind = mt7622_ethsys_bind, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + +U_BOOT_DRIVER(mtk_clk_sgmiisys) = { + .name = "mt7622-clock-sgmiisys", + .id = UCLASS_CLK, + .of_match = mt7622_sgmiisys_compat, + .probe = mt7622_sgmiisys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 30a919f224..858be85d15 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -539,6 +539,29 @@ static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), }; +static const struct mtk_gate_regs ssusb_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_SSUSB(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &ssusb_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + +static const struct mtk_gate ssusb_cgs[] = { + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0), + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1), + GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5), + GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6), + GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7), + GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8), +}; + static const struct mtk_clk_tree mt7629_clk_tree = { .xtal_rate = 40 * MHZ, .xtal2_rate = 20 * MHZ, @@ -621,6 +644,11 @@ static int mt7629_sgmiisys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs); } +static int mt7629_ssusbsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs); +} + static const struct udevice_id mt7629_apmixed_compat[] = { { .compatible = "mediatek,mt7629-apmixedsys" }, { } @@ -651,6 +679,11 @@ static const struct udevice_id mt7629_sgmiisys_compat[] = { { } }; +static const struct udevice_id mt7629_ssusbsys_compat[] = { + { .compatible = "mediatek,mt7629-ssusbsys" }, + { } +}; + static const struct udevice_id mt7629_mcucfg_compat[] = { { .compatible = "mediatek,mt7629-mcucfg" }, { } @@ -722,3 +755,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = { .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; + +U_BOOT_DRIVER(mtk_clk_ssusbsys) = { + .name = "mt7629-clock-ssusbsys", + .id = UCLASS_CLK, + .of_match = mt7629_ssusbsys_compat, + .probe = mt7629_ssusbsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c new file mode 100644 index 0000000000..cb168f146b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -0,0 +1,873 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT8512 SoC + * + * Copyright (C) 2019 BayLibre, SAS + * Author: Chen Zhong <chen.zhong@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt8512-clk.h> + +#include "clk-mtk.h" + +#define MT8512_PLL_FMAX (3800UL * MHZ) +#define MT8512_PLL_FMIN (1500UL * MHZ) +#define MT8512_CON0_RST_BAR BIT(23) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT8512_CON0_RST_BAR, \ + .fmax = MT8512_PLL_FMAX, \ + .fmin = MT8512_PLL_FMIN, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, + 0, 22, 0x0310, 24, 0x0310, 0, 0), + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001, + HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), + PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001, + HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), + PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, + 0, 22, 0x0354, 24, 0x0354, 0, 0), + PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, + 0, 32, 0x0320, 24, 0x0324, 0, 0x0320), + PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, + 0, 32, 0x0364, 24, 0x0368, 0, 0x0364), + PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001, + 0, 22, 0x0378, 24, 0x0378, 0, 0), + PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, + 0, 22, 0x0394, 24, 0x0394, 0, 0), + PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001, + 0, 22, 0x03A4, 24, 0x03A4, 0, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000), + FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32), + FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), + FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), + FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2), + FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4), + FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8), + FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16), + FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32), + FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64), + FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13), + FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2), + FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4), + FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1), + FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8), + FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16), + FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1), + FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), + FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16), + FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2), + FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1), + FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2), + FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4), + FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8), + FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1), + FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2), + FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2), +}; + +static const int axi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int mem_parents[] = { + CLK_TOP_DSPPLL, + CLK_TOP_IPPLL, + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3 +}; + +static const int uart_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int spis_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int msdc50_0_hc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL2_D2 +}; + +static const int msdc50_0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int msdc50_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int audio_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL2_D4 +}; + +static const int aud_intbus_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_APLL2_D8, + CLK_TOP_SYS_26M_D2, + CLK_TOP_APLL1_D8, + CLK_TOP_UNIVPLL3_D4 +}; + +static const int hapll1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1, + CLK_TOP_APLL1_D2, + CLK_TOP_APLL1_D3, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL1_D8, + CLK_TOP_APLL1_D16, + CLK_TOP_SYS_26M_D2 +}; + +static const int hapll2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2, + CLK_TOP_APLL2_D2, + CLK_TOP_APLL2_D3, + CLK_TOP_APLL2_D4, + CLK_TOP_APLL2_D8, + CLK_TOP_APLL2_D16, + CLK_TOP_SYS_26M_D2 +}; + +static const int asm_l_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int aud_spdif_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2, + CLK_TOP_DSPPLL +}; + +static const int aud_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1 +}; + +static const int aud_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2 +}; + +static const int ssusb_sys_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2 +}; + +static const int spm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D8 +}; + +static const int i2c_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYS_26M_D2, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_CLK32K +}; + +static const int pwm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int dsp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_DSPPLL_D2, + CLK_TOP_DSPPLL_D4, + CLK_TOP_DSPPLL_D8, + CLK_TOP_APLL2_D4, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int nfi2x_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5 +}; + +static const int spinfi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2 +}; + +static const int ecc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3 +}; + +static const int gcpu_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2 +}; + +static const int gcpu_cpm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int mbist_diag_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYS_26M_D2 +}; + +static const int ip0_nna_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_DSPPLL_D2, + CLK_TOP_DSPPLL_D4, + CLK_TOP_IPPLL, + CLK_TOP_SYS_26M_D2, + CLK_TOP_IPPLL_D2, + CLK_TOP_MSDCPLL_D2 +}; + +static const int ip2_wfst_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_IPPLL, + CLK_TOP_IPPLL_D2, + CLK_TOP_SYS_26M_D2, + CLK_TOP_MSDCPLL +}; + +static const int sflash_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D16, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_USB20_192M_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int sram_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_APLL1, + CLK_TOP_APLL2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYS_26M_D2 +}; + +static const int mm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D3 +}; + +static const int dpi0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_TCONPLL_D2, + CLK_TOP_TCONPLL_D4, + CLK_TOP_TCONPLL_D8, + CLK_TOP_TCONPLL_D16, + CLK_TOP_TCONPLL_D32, + CLK_TOP_TCONPLL_D64 +}; + +static const int dbg_atclk_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5 +}; + +static const int occ_104m_parents[] = { + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int occ_68m_parents[] = { + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int occ_182m_parents[] = { + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, + 0x040, 0x044, 0x048, 0, 3, 7, + 0x4, 0, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents, + 0x040, 0x044, 0x048, 8, 2, 15, + 0x4, 1, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents, + 0x040, 0x044, 0x048, 16, 1, 23, + 0x4, 2, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents, + 0x040, 0x044, 0x048, 24, 3, 31, + 0x4, 3, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_1 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents, + 0x050, 0x054, 0x058, 0, 3, 7, + 0x4, 4, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, + 0x050, 0x054, 0x058, 8, 2, 15, + 0x4, 5, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, + 0x050, 0x054, 0x058, 16, 2, 23, + 0x4, 6, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, + 0x050, 0x054, 0x058, 24, 3, 31, + 0x4, 7, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_2 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, + 0x060, 0x064, 0x068, 0, 3, 7, + 0x4, 8, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents, + 0x060, 0x064, 0x068, 8, 3, 15, + 0x4, 9, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents, + 0x060, 0x064, 0x068, 16, 2, 23, + 0x4, 10, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + 0x060, 0x064, 0x068, 24, 3, 31, + 0x4, 11, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_3 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents, + 0x070, 0x074, 0x078, 0, 3, 7, + 0x4, 12, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents, + 0x070, 0x074, 0x078, 8, 3, 15, + 0x4, 13, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents, + 0x070, 0x074, 0x078, 16, 3, 23, + 0x4, 14, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents, + 0x070, 0x074, 0x078, 24, 3, 31, + 0x4, 15, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_4 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 0, 2, 7, + 0x4, 16, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 8, 2, 15, + 0x4, 17, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 16, 2, 23, + 0x4, 18, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, + 0x080, 0x084, 0x088, 24, 2, 31, + 0x4, 19, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_5 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents, + 0x090, 0x094, 0x098, 0, 1, 7, + 0x4, 20, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents, + 0x090, 0x094, 0x098, 8, 1, 15, + 0x4, 21, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, + 0x090, 0x094, 0x098, 16, 2, 23, + 0x4, 22, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, + 0x090, 0x094, 0x098, 24, 2, 31, + 0x4, 23, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_6 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents, + 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, + 0x4, 24, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents, + 0x0a0, 0x0a4, 0x0a8, 8, 3, 15, + 0x4, 25, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents, + 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, + 0x4, 26, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents, + 0x0a0, 0x0a4, 0x0a8, 24, 3, 31, + 0x4, 27, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_7 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents, + 0x0b0, 0x0b4, 0x0b8, 0, 3, 7, + 0x4, 28, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents, + 0x0b0, 0x0b4, 0x0b8, 8, 3, 15, + 0x4, 29, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents, + 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, + 0x4, 30, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents, + 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, + 0x4, 31, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_8 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, + 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, + 0x8, 0, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents, + 0x0c0, 0x0c4, 0x0c8, 8, 1, 15, + 0x8, 1, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents, + 0x0c0, 0x0c4, 0x0c8, 16, 3, 23, + 0x8, 2, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents, + 0x0c0, 0x0c4, 0x0c8, 24, 3, 31, + 0x8, 3, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_9 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents, + 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, + 0x8, 4, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents, + 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, + 0x8, 5, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents, + 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, + 0x8, 6, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents, + 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, + 0x8, 7, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_10 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents, + 0x0e0, 0x0e4, 0x0e8, 0, 3, 7, + 0x8, 8, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, + 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, + 0x8, 9, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents, + 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, + 0x8, 10, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents, + 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, + 0x8, 11, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_11 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents, + 0x0ec, 0x0f0, 0x0f4, 0, 2, 7, + 0x8, 12, CLK_MUX_SETCLR_UPD), +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x104, + .sta_ofs = 0x104, +}; + +#define GATE_TOP0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_TOP1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate top_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), + GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), + GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), + GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), + /* TOP1 */ + GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9), + GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), + GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x294, + .clr_ofs = 0x294, + .sta_ofs = 0x294, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra3_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra4_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +static const struct mtk_gate_regs infra5_cg_regs = { + .set_ofs = 0xd0, + .clr_ofs = 0xd4, + .sta_ofs = 0xd8, +}; + +#define GATE_INFRA0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA2(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA3(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA4(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra4_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA5(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra5_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6), + GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8), + GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9), + GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10), + GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15), + GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16), + GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17), + GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18), + GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19), + GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20), + GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21), + GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22), + GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23), + GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24), + GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26), + GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28), + GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1), + GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2), + GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4), + GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8), + GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9), + GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18), + GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24), + GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25), + GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29), + /* INFRA3 */ + GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0), + GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1), + GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3), + GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4), + GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6), + GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27), + /* INFRA4 */ + GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7), + GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8), + GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9), + GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10), + GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22), + GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23), + GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24), + GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25), + GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26), + /* INFRA5 */ + GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1), + GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2), + GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3), + GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7), + GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9), + GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11), +}; + +static const struct mtk_clk_tree mt8512_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_SYSPLL1_D2, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt8512_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8512_clk_tree); +} + +static int mt8512_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8512_clk_tree); +} + +static int mt8512_topckgen_cg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks); +} + +static int mt8512_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks); +} + +static const struct udevice_id mt8512_apmixed_compat[] = { + { .compatible = "mediatek,mt8512-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8512_topckgen_compat[] = { + { .compatible = "mediatek,mt8512-topckgen", }, + { } +}; + +static const struct udevice_id mt8512_topckgen_cg_compat[] = { + { .compatible = "mediatek,mt8512-topckgen-cg", }, + { } +}; + +static const struct udevice_id mt8512_infracfg_compat[] = { + { .compatible = "mediatek,mt8512-infracfg", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8512-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8512_apmixed_compat, + .probe = mt8512_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8512-topckgen", + .id = UCLASS_CLK, + .of_match = mt8512_topckgen_compat, + .probe = mt8512_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { + .name = "mt8512-topckgen-cg", + .id = UCLASS_CLK, + .of_match = mt8512_topckgen_cg_compat, + .probe = mt8512_topckgen_cg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt8512-infracfg", + .id = UCLASS_CLK, + .of_match = mt8512_infracfg_compat, + .probe = mt8512_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 6c6b500d9b..09ae2d4860 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -39,7 +39,7 @@ * this function is recursively called to find the parent to calculate * the accurate frequency. */ -static int mtk_clk_find_parent_rate(struct clk *clk, int id, +static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, const struct driver *drv) { struct clk parent = { .id = id, }; @@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, if (++index == mux->num_parents) return -EINVAL; - /* switch mux to a select parent */ - val = readl(base + mux->mux_reg); - val &= ~(mux->mux_mask << mux->mux_shift); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = (mux->mux_mask << mux->mux_shift); + writel(val, base + mux->mux_clr_reg); - val |= index << mux->mux_shift; - writel(val, base + mux->mux_reg); + val = (index << mux->mux_shift); + writel(val, base + mux->mux_set_reg); + + if (mux->upd_shift >= 0) + writel(BIT(mux->upd_shift), base + mux->upd_reg); + } else { + /* switch mux to a select parent */ + val = readl(base + mux->mux_reg); + val &= ~(mux->mux_mask << mux->mux_shift); + + val |= index << mux->mux_shift; + writel(val, base + mux->mux_reg); + } return 0; } @@ -84,11 +95,13 @@ static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, { int pcwbits = pll->pcwbits; int pcwfbits; + int ibits; u64 vco; u8 c = 0; /* The fractional part of the PLL divider. */ - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; vco = (u64)fin * pcw; @@ -113,7 +126,7 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; - u32 val; + u32 val, chg; /* set postdiv */ val = readl(priv->base + pll->pd_reg); @@ -129,11 +142,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) /* set pcw */ val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); val |= pcw << pll->pcw_shift; - val &= ~CON1_PCW_CHG; - writel(val, priv->base + pll->pcw_reg); - val |= CON1_PCW_CHG; - writel(val, priv->base + pll->pcw_reg); + if (pll->pcw_chg_reg) { + chg = readl(priv->base + pll->pcw_chg_reg); + chg |= CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + writel(chg, priv->base + pll->pcw_chg_reg); + } else { + val |= CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + } udelay(20); } @@ -150,8 +168,9 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; - unsigned long fmin = 1000 * MHZ; + unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ; u64 _pcw; + int ibits; u32 val; if (freq > pll->fmax) @@ -164,7 +183,8 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, } /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */ - _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS); + ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; + _pcw = ((u64)freq << val) << (pll->pcwbits - ibits); do_div(_pcw, priv->tree->xtal2_rate); *pcw = (u32)_pcw; @@ -265,7 +285,7 @@ static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, return rate; } -static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; @@ -287,7 +307,7 @@ static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) return mtk_factor_recalc_rate(fdiv, rate); } -static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux = &priv->tree->muxes[off]; @@ -332,9 +352,14 @@ static int mtk_topckgen_enable(struct clk *clk) return 0; /* enable clock gate */ - val = readl(priv->base + mux->gate_reg); - val &= ~BIT(mux->gate_shift); - writel(val, priv->base + mux->gate_reg); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = BIT(mux->gate_shift); + writel(val, priv->base + mux->mux_clr_reg); + } else { + val = readl(priv->base + mux->gate_reg); + val &= ~BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + } if (mux->flags & CLK_DOMAIN_SCPSYS) { /* enable scpsys clock off control */ @@ -360,9 +385,14 @@ static int mtk_topckgen_disable(struct clk *clk) return 0; /* disable clock gate */ - val = readl(priv->base + mux->gate_reg); - val |= BIT(mux->gate_shift); - writel(val, priv->base + mux->gate_reg); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = BIT(mux->gate_shift); + writel(val, priv->base + mux->mux_set_reg); + } else { + val = readl(priv->base + mux->gate_reg); + val |= BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + } return 0; } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index dce93253ad..c7dc980861 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -12,6 +12,7 @@ #define HAVE_RST_BAR BIT(0) #define CLK_DOMAIN_SCPSYS BIT(0) +#define CLK_MUX_SETCLR_UPD BIT(1) #define CLK_GATE_SETCLR BIT(0) #define CLK_GATE_SETCLR_INV BIT(1) @@ -36,9 +37,12 @@ struct mtk_pll_data { u32 flags; u32 rst_bar_mask; u64 fmax; + u64 fmin; int pcwbits; + int pcwibits; u32 pcw_reg; int pcw_shift; + u32 pcw_chg_reg; }; /** @@ -102,9 +106,13 @@ struct mtk_composite { const int id; const int *parent; u32 mux_reg; + u32 mux_set_reg; + u32 mux_clr_reg; + u32 upd_reg; u32 gate_reg; u32 mux_mask; signed char mux_shift; + signed char upd_shift; signed char gate_shift; signed char num_parents; u16 flags; @@ -137,6 +145,24 @@ struct mtk_composite { .flags = 0, \ } +#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ + _mux_clr_ofs, _shift, _width, _gate, \ + _upd_ofs, _upd, _flags) { \ + .id = _id, \ + .mux_reg = _mux_ofs, \ + .mux_set_reg = _mux_set_ofs, \ + .mux_clr_reg = _mux_clr_ofs, \ + .upd_reg = _upd_ofs, \ + .upd_shift = _upd, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _mux_ofs, \ + .gate_shift = _gate, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = _flags, \ + } + struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index dea58b5581..2a2aa2f4f1 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -187,6 +187,5 @@ static const struct udevice_id zynqmp_firmware_ids[] = { U_BOOT_DRIVER(zynqmp_firmware) = { .id = UCLASS_FIRMWARE, .name = "zynqmp-firmware", - .probe = dm_scan_fdt_dev, .of_match = zynqmp_firmware_ids, }; diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index eaa584a4df..d4870818a8 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -12,8 +12,8 @@ #include <mmc.h> #include <errno.h> #include <malloc.h> +#include <mapmem.h> #include <stdbool.h> -#include <watchdog.h> #include <asm/gpio.h> #include <dm/pinctrl.h> #include <linux/bitops.h> @@ -135,6 +135,25 @@ #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) +/* EMMC_TOP_CONTROL mask */ +#define PAD_RXDLY_SEL BIT(0) +#define DELAY_EN BIT(1) +#define PAD_DAT_RD_RXDLY2 (0x1f << 2) +#define PAD_DAT_RD_RXDLY (0x1f << 7) +#define PAD_DAT_RD_RXDLY_S 7 +#define PAD_DAT_RD_RXDLY2_SEL BIT(12) +#define PAD_DAT_RD_RXDLY_SEL BIT(13) +#define DATA_K_VALUE_SEL BIT(14) +#define SDC_RX_ENH_EN BIT(15) + +/* EMMC_TOP_CMD mask */ +#define PAD_CMD_RXDLY2 (0x1f << 0) +#define PAD_CMD_RXDLY (0x1f << 5) +#define PAD_CMD_RXDLY_S 5 +#define PAD_CMD_RD_RXDLY2_SEL BIT(10) +#define PAD_CMD_RD_RXDLY_SEL BIT(11) +#define PAD_CMD_TX_DLY (0x1f << 12) + /* SDC_CFG_BUSWIDTH */ #define MSDC_BUS_1BITS 0x0 #define MSDC_BUS_4BITS 0x1 @@ -219,6 +238,21 @@ struct mtk_sd_regs { u32 sdc_fifo_cfg; }; +struct msdc_top_regs { + u32 emmc_top_control; + u32 emmc_top_cmd; + u32 emmc50_pad_ctl0; + u32 emmc50_pad_ds_tune; + u32 emmc50_pad_dat0_tune; + u32 emmc50_pad_dat1_tune; + u32 emmc50_pad_dat2_tune; + u32 emmc50_pad_dat3_tune; + u32 emmc50_pad_dat4_tune; + u32 emmc50_pad_dat5_tune; + u32 emmc50_pad_dat6_tune; + u32 emmc50_pad_dat7_tune; +}; + struct msdc_compatible { u8 clk_div_bits; u8 sclk_cycle_shift; @@ -249,6 +283,7 @@ struct msdc_tune_para { struct msdc_host { struct mtk_sd_regs *base; + struct msdc_top_regs *top_base; struct mmc *mmc; struct msdc_compatible *dev_comp; @@ -495,6 +530,7 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd, blocks = data->blocks; writel(CMD_INTS_MASK, &host->base->msdc_int); + writel(DATA_INTS_MASK, &host->base->msdc_int); writel(blocks, &host->base->sdc_blk_num); writel(cmd->cmdarg, &host->base->sdc_arg); writel(rawcmd, &host->base->sdc_cmd); @@ -641,13 +677,9 @@ static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) u32 size; int ret; - WATCHDOG_RESET(); - if (data->flags == MMC_DATA_WRITE) host->last_data_write = 1; - writel(DATA_INTS_MASK, &host->base->msdc_int); - size = data->blocks * data->blocksize; if (data->flags == MMC_DATA_WRITE) @@ -964,6 +996,36 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) return delay_phase; } +static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) +{ + void __iomem *tune_reg = &host->base->pad_tune; + + if (host->dev_comp->pad_tune0) + tune_reg = &host->base->pad_tune0; + + if (host->top_base) + clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY, + value << PAD_CMD_RXDLY_S); + else + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, + value << MSDC_PAD_TUNE_CMDRDLY_S); +} + +static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) +{ + void __iomem *tune_reg = &host->base->pad_tune; + + if (host->dev_comp->pad_tune0) + tune_reg = &host->base->pad_tune0; + + if (host->top_base) + clrsetbits_le32(&host->top_base->emmc_top_control, + PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S); + else + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, + value << MSDC_PAD_TUNE_DATRRDLY_S); +} + static int hs400_tune_response(struct udevice *dev, u32 opcode) { struct msdc_plat *plat = dev_get_platdata(dev); @@ -1010,7 +1072,7 @@ static int hs400_tune_response(struct udevice *dev, u32 opcode) PAD_CMD_TUNE_RX_DLY3_S); final_delay = final_cmd_delay.final_phase; - dev_err(dev, "Final cmd pad delay: %x\n", final_delay); + dev_info(dev, "Final cmd pad delay: %x\n", final_delay); return final_delay == 0xff ? -EIO : 0; } @@ -1217,21 +1279,14 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode) u32 rise_delay = 0, fall_delay = 0; struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; u8 final_delay, final_maxlen; - void __iomem *tune_reg = &host->base->pad_tune; int i, ret; - if (host->dev_comp->pad_tune0) - tune_reg = &host->base->pad_tune0; - clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); for (i = 0; i < PAD_DELAY_MAX; i++) { - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - i << MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - i << MSDC_PAD_TUNE_DATRRDLY_S); - + msdc_set_cmd_delay(host, i); + msdc_set_data_delay(host, i); ret = mmc_send_tuning(mmc, opcode, NULL); if (!ret) rise_delay |= (1 << i); @@ -1246,11 +1301,8 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode) setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); for (i = 0; i < PAD_DELAY_MAX; i++) { - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - i << MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - i << MSDC_PAD_TUNE_DATRRDLY_S); - + msdc_set_cmd_delay(host, i); + msdc_set_data_delay(host, i); ret = mmc_send_tuning(mmc, opcode, NULL); if (!ret) fall_delay |= (1 << i); @@ -1263,27 +1315,17 @@ skip_fall: if (final_maxlen == final_rise_delay.maxlen) { clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - final_rise_delay.final_phase << - MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - final_rise_delay.final_phase << - MSDC_PAD_TUNE_DATRRDLY_S); final_delay = final_rise_delay.final_phase; } else { setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - final_fall_delay.final_phase << - MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - final_fall_delay.final_phase << - MSDC_PAD_TUNE_DATRRDLY_S); final_delay = final_fall_delay.final_phase; } - dev_err(dev, "Final pad delay: %x\n", final_delay); + msdc_set_cmd_delay(host, final_delay); + msdc_set_data_delay(host, final_delay); + dev_info(dev, "Final pad delay: %x\n", final_delay); return final_delay == 0xff ? -EIO : 0; } @@ -1400,8 +1442,12 @@ static void msdc_init_hw(struct msdc_host *host) 3 << MSDC_PB2_RESPWAIT_S); if (host->dev_comp->enhance_rx) { - setbits_le32(&host->base->sdc_adv_cfg0, - SDC_RX_ENHANCE_EN); + if (host->top_base) + setbits_le32(&host->top_base->emmc_top_control, + SDC_RX_ENH_EN); + else + setbits_le32(&host->base->sdc_adv_cfg0, + SDC_RX_ENHANCE_EN); } else { clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPSTSENSEL_M, @@ -1476,7 +1522,6 @@ static int msdc_drv_probe(struct udevice *dev) cfg->f_min = host->src_clk_freq / (4 * 255); else cfg->f_min = host->src_clk_freq / (4 * 4095); - cfg->f_max = host->src_clk_freq / 2; cfg->b_max = 1024; cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; @@ -1502,11 +1547,19 @@ static int msdc_ofdata_to_platdata(struct udevice *dev) struct msdc_plat *plat = dev_get_platdata(dev); struct msdc_host *host = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; + fdt_addr_t base, top_base; int ret; - host->base = (void *)dev_read_addr(dev); - if (!host->base) + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) return -EINVAL; + host->base = map_sysmem(base, 0); + + top_base = dev_read_addr_index(dev, 1); + if (top_base == FDT_ADDR_T_NONE) + host->top_base = NULL; + else + host->top_base = map_sysmem(top_base, 0); ret = mmc_of_parse(dev, cfg); if (ret) @@ -1568,6 +1621,15 @@ static const struct msdc_compatible mt7620_compat = { .enhance_rx = false }; +static const struct msdc_compatible mt7622_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, +}; + static const struct msdc_compatible mt7623_compat = { .clk_div_bits = 12, .sclk_cycle_shift = 20, @@ -1579,6 +1641,16 @@ static const struct msdc_compatible mt7623_compat = { .enhance_rx = false }; +static const struct msdc_compatible mt8512_compat = { + .clk_div_bits = 12, + .sclk_cycle_shift = 20, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, +}; + static const struct msdc_compatible mt8516_compat = { .clk_div_bits = 12, .sclk_cycle_shift = 20, @@ -1601,7 +1673,9 @@ static const struct msdc_compatible mt8183_compat = { static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat }, + { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, + { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, {} diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 16165f8839..5de72fb46c 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -236,6 +236,7 @@ endif config NAND_ARASAN bool "Configure Arasan Nand" select SYS_NAND_SELF_INIT + select DM_MTD imply CMD_NAND help This enables Nand driver support for Arasan nand flash @@ -280,6 +281,7 @@ endif config NAND_ZYNQ bool "Support for Zynq Nand controller" select SYS_NAND_SELF_INIT + select DM_MTD imply CMD_NAND help This enables Nand driver support for Nand flash controller diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index 2cd3f64dc6..d1b1a4263a 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -15,14 +15,25 @@ #include <linux/mtd/nand_ecc.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#include <dm.h> #include <nand.h> -struct arasan_nand_info { - void __iomem *nand_base; +struct nand_config { u32 page; bool on_die_ecc_enabled; }; +struct nand_drv { + struct nand_regs *reg; + struct nand_config config; +}; + +struct arasan_nand_info { + struct udevice *dev; + struct nand_drv nand_ctrl; + struct nand_chip nand_chip; +}; + struct nand_regs { u32 pkt_reg; u32 memadr_reg1; @@ -54,8 +65,6 @@ struct nand_regs { u32 data_if_reg; }; -#define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR) - struct arasan_nand_command_format { u8 cmd1; u8 cmd2; @@ -259,30 +268,32 @@ static u32 buf_index; static struct nand_ecclayout nand_oob; -static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; - static void arasan_nand_select_chip(struct mtd_info *mtd, int chip) { + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(nand_chip); u32 reg_val; - reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val = readl(&info->reg->memadr_reg2); if (chip == 0) { reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); + writel(reg_val, &info->reg->memadr_reg2); } else if (chip == 1) { reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; - writel(reg_val, &arasan_nand_base->memadr_reg2); + writel(reg_val, &info->reg->memadr_reg2); } } -static void arasan_nand_enable_ecc(void) +static void arasan_nand_enable_ecc(struct mtd_info *mtd) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 reg_val; - reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val = readl(&info->reg->cmd_reg); reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; - writel(reg_val, &arasan_nand_base->cmd_reg); + writel(reg_val, &info->reg->cmd_reg); } static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) @@ -323,7 +334,8 @@ static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) { struct nand_chip *chip = mtd_to_nand(mtd); - struct arasan_nand_info *nand = nand_get_controller_data(chip); + struct nand_drv *info = nand_get_controller_data(chip); + struct nand_config *nand = &info->config; u32 reg_val, i, pktsize, pktnum; u32 *bufptr = (u32 *)buf; u32 timeout; @@ -340,20 +352,20 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) else pktnum = size/pktsize; - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK | ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK; - writel(reg_val, &arasan_nand_base->intsts_enr); + writel(reg_val, &info->reg->intsts_enr); - reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val = readl(&info->reg->pkt_reg); reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize; - writel(reg_val, &arasan_nand_base->pkt_reg); + writel(reg_val, &info->reg->pkt_reg); if (!nand->on_die_ecc_enabled) { - arasan_nand_enable_ecc(); + arasan_nand_enable_ecc(mtd); addr_cycles = arasan_nand_get_addrcycle(mtd); if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) return ERR_ADDR_CYCLE; @@ -361,13 +373,13 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) | NAND_CMD_RNDOUT | (addr_cycles << ARASAN_NAND_CMD_ADDR_CYCL_SHIFT), - &arasan_nand_base->ecc_sprcmd_reg); + &info->reg->ecc_sprcmd_reg); } - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + writel(curr_cmd->pgm, &info->reg->pgm_reg); while (rdcount < pktnum) { timeout = ARASAN_NAND_POLL_TIMEOUT; - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { udelay(1); timeout--; @@ -380,20 +392,20 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) rdcount++; if (pktnum == rdcount) { - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; - writel(reg_val, &arasan_nand_base->intsts_enr); + writel(reg_val, &info->reg->intsts_enr); } else { - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, - &arasan_nand_base->intsts_enr); + &info->reg->intsts_enr); } - reg_val = readl(&arasan_nand_base->intsts_reg); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); for (i = 0; i < pktsize/4; i++) - bufptr[i] = readl(&arasan_nand_base->buf_dataport); + bufptr[i] = readl(&info->reg->buf_dataport); bufptr += pktsize/4; @@ -402,12 +414,12 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) break; writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, - &arasan_nand_base->intsts_enr); + &info->reg->intsts_enr); } timeout = ARASAN_NAND_POLL_TIMEOUT; - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { udelay(1); timeout--; @@ -417,21 +429,21 @@ static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) return -ETIMEDOUT; } - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->intsts_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); if (!nand->on_die_ecc_enabled) { - if (readl(&arasan_nand_base->intsts_reg) & + if (readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) { printf("arasan rd_page:sbiterror\n"); return -1; } - if (readl(&arasan_nand_base->intsts_reg) & + if (readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_ERR_EN_MASK) { mtd->ecc_stats.failed++; printf("arasan rd_page:multibiterror\n"); @@ -455,9 +467,11 @@ static int arasan_nand_read_page_hwecc(struct mtd_info *mtd, return status; } -static void arasan_nand_fill_tx(const u8 *buf, int len) +static void arasan_nand_fill_tx(struct mtd_info *mtd, const u8 *buf, int len) { - u32 __iomem *nand = &arasan_nand_base->buf_dataport; + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); + u32 __iomem *nand = &info->reg->buf_dataport; if (((unsigned long)buf & 0x3) != 0) { if (((unsigned long)buf & 0x1) != 0) { @@ -499,13 +513,14 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const u8 *buf, int oob_required, int page) { + struct nand_drv *info = nand_get_controller_data(chip); + struct nand_config *nand = &info->config; u32 reg_val, i, pktsize, pktnum; const u32 *bufptr = (const u32 *)buf; u32 timeout = ARASAN_NAND_POLL_TIMEOUT; u32 size = mtd->writesize; u32 rdcount = 0; u8 column_addr_cycles; - struct arasan_nand_info *nand = nand_get_controller_data(chip); if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) pktsize = ARASAN_NAND_PKTSIZE_1K; @@ -517,25 +532,25 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, else pktnum = size/pktsize; - reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val = readl(&info->reg->pkt_reg); reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize; - writel(reg_val, &arasan_nand_base->pkt_reg); + writel(reg_val, &info->reg->pkt_reg); if (!nand->on_die_ecc_enabled) { - arasan_nand_enable_ecc(); + arasan_nand_enable_ecc(mtd); column_addr_cycles = (chip->onfi_params.addr_cycles & ARASAN_NAND_COL_ADDR_CYCL_MASK) >> ARASAN_NAND_COL_ADDR_CYCL_SHIFT; writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)), - &arasan_nand_base->ecc_sprcmd_reg); + &info->reg->ecc_sprcmd_reg); } - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + writel(curr_cmd->pgm, &info->reg->pgm_reg); while (rdcount < pktnum) { timeout = ARASAN_NAND_POLL_TIMEOUT; - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { udelay(1); timeout--; @@ -549,21 +564,21 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, rdcount++; if (pktnum == rdcount) { - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; - writel(reg_val, &arasan_nand_base->intsts_enr); + writel(reg_val, &info->reg->intsts_enr); } else { - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, - &arasan_nand_base->intsts_enr); + &info->reg->intsts_enr); } - reg_val = readl(&arasan_nand_base->intsts_reg); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); for (i = 0; i < pktsize/4; i++) - writel(bufptr[i], &arasan_nand_base->buf_dataport); + writel(bufptr[i], &info->reg->buf_dataport); bufptr += pktsize/4; @@ -571,12 +586,12 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, break; writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, - &arasan_nand_base->intsts_enr); + &info->reg->intsts_enr); } timeout = ARASAN_NAND_POLL_TIMEOUT; - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { udelay(1); timeout--; @@ -586,12 +601,12 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, return -ETIMEDOUT; } - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->intsts_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); if (oob_required) chip->ecc.write_oob(mtd, chip, nand->page); @@ -620,22 +635,25 @@ static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, return status; } -static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd) +static int arasan_nand_reset(struct mtd_info *mtd, + struct arasan_nand_command_format *curr_cmd) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 timeout = ARASAN_NAND_POLL_TIMEOUT; u32 cmd_reg = 0; writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - cmd_reg = readl(&arasan_nand_base->cmd_reg); + &info->reg->intsts_enr); + cmd_reg = readl(&info->reg->cmd_reg); cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK; cmd_reg |= curr_cmd->cmd1 | (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); - writel(cmd_reg, &arasan_nand_base->cmd_reg); - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + writel(cmd_reg, &info->reg->cmd_reg); + writel(curr_cmd->pgm, &info->reg->pgm_reg); - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { udelay(1); timeout--; @@ -646,10 +664,10 @@ static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd) } writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); + &info->reg->intsts_enr); writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); return 0; } @@ -688,12 +706,14 @@ static u8 arasan_nand_page(struct mtd_info *mtd) static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, int column, int page_addr, struct mtd_info *mtd) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 reg_val, page; u8 page_val, addr_cycles; writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->cmd_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->cmd_reg); reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; reg_val |= curr_cmd->cmd1 | (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); @@ -711,7 +731,7 @@ static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, reg_val |= (addr_cycles << ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); - writel(reg_val, &arasan_nand_base->cmd_reg); + writel(reg_val, &info->reg->cmd_reg); if (page_addr == -1) page_addr = 0; @@ -719,30 +739,32 @@ static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & ARASAN_NAND_MEM_ADDR1_PAGE_MASK; column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; - writel(page|column, &arasan_nand_base->memadr_reg1); + writel(page | column, &info->reg->memadr_reg1); - reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val = readl(&info->reg->memadr_reg2); reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); - writel(reg_val, &arasan_nand_base->memadr_reg2); + writel(reg_val, &info->reg->memadr_reg2); return 0; } static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 reg_val; u32 timeout = ARASAN_NAND_POLL_TIMEOUT; - reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val = readl(&info->reg->pkt_reg); reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len; - writel(reg_val, &arasan_nand_base->pkt_reg); - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + writel(reg_val, &info->reg->pkt_reg); + writel(curr_cmd->pgm, &info->reg->pgm_reg); - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { udelay(1); timeout--; @@ -751,19 +773,19 @@ static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) if (!timeout) puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n"); - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; - writel(reg_val, &arasan_nand_base->intsts_enr); + writel(reg_val, &info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->intsts_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); - arasan_nand_fill_tx(buf, len); + arasan_nand_fill_tx(mtd, buf, len); timeout = ARASAN_NAND_POLL_TIMEOUT; - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { udelay(1); timeout--; @@ -771,24 +793,26 @@ static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) if (!timeout) puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n"); - writel(readl(&arasan_nand_base->intsts_enr) | + writel(readl(&info->reg->intsts_enr) | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - writel(readl(&arasan_nand_base->intsts_reg) | + &info->reg->intsts_enr); + writel(readl(&info->reg->intsts_reg) | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); } static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, int column, int page_addr, struct mtd_info *mtd) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 reg_val, page; u32 timeout = ARASAN_NAND_POLL_TIMEOUT; u8 row_addr_cycles; writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->cmd_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->cmd_reg); reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; reg_val |= curr_cmd->cmd1 | (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); @@ -801,21 +825,21 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, reg_val |= (row_addr_cycles << ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); - writel(reg_val, &arasan_nand_base->cmd_reg); + writel(reg_val, &info->reg->cmd_reg); page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & ARASAN_NAND_MEM_ADDR1_COL_MASK; column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK; writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT), - &arasan_nand_base->memadr_reg1); + &info->reg->memadr_reg1); - reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val = readl(&info->reg->memadr_reg2); reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); - writel(reg_val, &arasan_nand_base->memadr_reg2); - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + writel(reg_val, &info->reg->memadr_reg2); + writel(curr_cmd->pgm, &info->reg->pgm_reg); - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { udelay(1); timeout--; @@ -825,12 +849,12 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, return -ETIMEDOUT; } - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->intsts_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); return 0; } @@ -838,13 +862,15 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, int column, int page_addr, struct mtd_info *mtd) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 reg_val; u32 timeout = ARASAN_NAND_POLL_TIMEOUT; u8 addr_cycles; writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->cmd_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->cmd_reg); reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; reg_val |= curr_cmd->cmd1 | (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); @@ -857,16 +883,16 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, reg_val |= (addr_cycles << ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); - writel(reg_val, &arasan_nand_base->cmd_reg); + writel(reg_val, &info->reg->cmd_reg); - reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val = readl(&info->reg->pkt_reg); reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1; - writel(reg_val, &arasan_nand_base->pkt_reg); + writel(reg_val, &info->reg->pkt_reg); - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); - while (!(readl(&arasan_nand_base->intsts_reg) & + writel(curr_cmd->pgm, &info->reg->pgm_reg); + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { udelay(1); timeout--; @@ -877,12 +903,12 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, return -ETIMEDOUT; } - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->intsts_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); return 0; } @@ -890,14 +916,16 @@ static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, int column, int page_addr, struct mtd_info *mtd) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 reg_val, addr_cycles, page; u8 page_val; - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, - &arasan_nand_base->intsts_enr); + &info->reg->intsts_enr); - reg_val = readl(&arasan_nand_base->cmd_reg); + reg_val = readl(&info->reg->cmd_reg); reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; reg_val |= curr_cmd->cmd1 | (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); @@ -919,7 +947,7 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, return ERR_ADDR_CYCLE; reg_val |= (addr_cycles << 28); - writel(reg_val, &arasan_nand_base->cmd_reg); + writel(reg_val, &info->reg->cmd_reg); if (page_addr == -1) page_addr = 0; @@ -927,12 +955,12 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & ARASAN_NAND_MEM_ADDR1_PAGE_MASK; column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; - writel(page | column, &arasan_nand_base->memadr_reg1); + writel(page | column, &info->reg->memadr_reg1); - reg_val = readl(&arasan_nand_base->memadr_reg2); + reg_val = readl(&info->reg->memadr_reg2); reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); - writel(reg_val, &arasan_nand_base->memadr_reg2); + writel(reg_val, &info->reg->memadr_reg2); buf_index = 0; @@ -941,19 +969,21 @@ static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) { + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 reg_val, i; u32 *bufptr = (u32 *)buf; u32 timeout = ARASAN_NAND_POLL_TIMEOUT; - reg_val = readl(&arasan_nand_base->pkt_reg); + reg_val = readl(&info->reg->pkt_reg); reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size; - writel(reg_val, &arasan_nand_base->pkt_reg); + writel(reg_val, &info->reg->pkt_reg); - writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); + writel(curr_cmd->pgm, &info->reg->pgm_reg); - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { udelay(1); timeout--; @@ -962,26 +992,26 @@ static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) if (!timeout) puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n"); - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; - writel(reg_val, &arasan_nand_base->intsts_enr); + writel(reg_val, &info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->intsts_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); buf_index = 0; for (i = 0; i < size / 4; i++) - bufptr[i] = readl(&arasan_nand_base->buf_dataport); + bufptr[i] = readl(&info->reg->buf_dataport); if (size & 0x03) - bufptr[i] = readl(&arasan_nand_base->buf_dataport); + bufptr[i] = readl(&info->reg->buf_dataport); timeout = ARASAN_NAND_POLL_TIMEOUT; - while (!(readl(&arasan_nand_base->intsts_reg) & + while (!(readl(&info->reg->intsts_reg) & ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { udelay(1); timeout--; @@ -990,17 +1020,18 @@ static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) if (!timeout) puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n"); - reg_val = readl(&arasan_nand_base->intsts_enr); + reg_val = readl(&info->reg->intsts_enr); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); - reg_val = readl(&arasan_nand_base->intsts_reg); + &info->reg->intsts_enr); + reg_val = readl(&info->reg->intsts_reg); writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_reg); + &info->reg->intsts_reg); } static u8 arasan_nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(chip); u32 size; u8 val; struct nand_onfi_params *p; @@ -1016,7 +1047,7 @@ static u8 arasan_nand_read_byte(struct mtd_info *mtd) else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) size = 4; else if (curr_cmd->cmd1 == NAND_CMD_STATUS) - return readb(&arasan_nand_base->flash_sts_reg); + return readb(&info->reg->flash_sts_reg); else size = 8; chip->read_buf(mtd, &buf_data[0], size); @@ -1031,13 +1062,14 @@ static u8 arasan_nand_read_byte(struct mtd_info *mtd) static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - u32 i, ret = 0; struct nand_chip *chip = mtd_to_nand(mtd); - struct arasan_nand_info *nand = nand_get_controller_data(chip); + struct nand_drv *info = nand_get_controller_data(chip); + struct nand_config *nand = &info->config; + u32 i, ret = 0; curr_cmd = NULL; writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, - &arasan_nand_base->intsts_enr); + &info->reg->intsts_enr); if ((command == NAND_CMD_READOOB) && (mtd->writesize > 512)) { @@ -1060,7 +1092,7 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, } if (curr_cmd->cmd1 == NAND_CMD_RESET) - ret = arasan_nand_reset(curr_cmd); + ret = arasan_nand_reset(mtd, curr_cmd); if ((curr_cmd->cmd1 == NAND_CMD_READID) || (curr_cmd->cmd1 == NAND_CMD_PARAM) || @@ -1088,7 +1120,7 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, static void arasan_check_ondie(struct mtd_info *mtd) { struct nand_chip *nand_chip = mtd_to_nand(mtd); - struct arasan_nand_info *nand = nand_get_controller_data(nand_chip); + struct nand_config *nand = nand_get_controller_data(nand_chip); u8 maf_id, dev_id; u8 get_feature[4]; u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00}; @@ -1131,9 +1163,10 @@ static void arasan_check_ondie(struct mtd_info *mtd) static int arasan_nand_ecc_init(struct mtd_info *mtd) { + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct nand_drv *info = nand_get_controller_data(nand_chip); int found = -1; u32 regval, eccpos_start, i, eccaddr; - struct nand_chip *nand_chip = mtd_to_nand(mtd); for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) { if ((ecc_matrix[i].pagesize == mtd->writesize) && @@ -1157,14 +1190,14 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd) regval = eccaddr | (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) | (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT); - writel(regval, &arasan_nand_base->ecc_reg); + writel(regval, &info->reg->ecc_reg); if (ecc_matrix[found].bch) { - regval = readl(&arasan_nand_base->memadr_reg2); + regval = readl(&info->reg->memadr_reg2); regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK; regval |= (ecc_matrix[found].bchval << ARASAN_NAND_MEM_ADDR2_BCH_SHIFT); - writel(regval, &arasan_nand_base->memadr_reg2); + writel(regval, &info->reg->memadr_reg2); } nand_oob.eccbytes = ecc_matrix[found].eccsize; @@ -1184,21 +1217,18 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd) return 0; } -static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) +static int arasan_probe(struct udevice *dev) { - struct arasan_nand_info *nand; + struct arasan_nand_info *arasan = dev_get_priv(dev); + struct nand_chip *nand_chip = &arasan->nand_chip; + struct nand_drv *info = &arasan->nand_ctrl; + struct nand_config *nand = &info->config; struct mtd_info *mtd; int err = -1; - nand = calloc(1, sizeof(struct arasan_nand_info)); - if (!nand) { - printf("%s: failed to allocate\n", __func__); - return err; - } - - nand->nand_base = arasan_nand_base; + info->reg = (struct nand_regs *)dev_read_addr(dev); mtd = nand_to_mtd(nand_chip); - nand_set_controller_data(nand_chip, nand); + nand_set_controller_data(nand_chip, &arasan->nand_ctrl); #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE nand_chip->options |= NAND_NO_SUBPAGE_WRITE; @@ -1214,8 +1244,8 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) nand_chip->write_buf = arasan_nand_write_buf; nand_chip->bbt_options = NAND_BBT_USE_FLASH; - writel(0x0, &arasan_nand_base->cmd_reg); - writel(0x0, &arasan_nand_base->pgm_reg); + writel(0x0, &info->reg->cmd_reg); + writel(0x0, &info->reg->pgm_reg); /* first scan to find the device and get the page size */ if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) { @@ -1253,7 +1283,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) goto fail; } - if (nand_register(devnum, mtd)) { + if (nand_register(0, mtd)) { printf("Nand Register Fail\n"); goto fail; } @@ -1264,10 +1294,26 @@ fail: return err; } +static const struct udevice_id arasan_nand_dt_ids[] = { + {.compatible = "arasan,nfc-v3p10",}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(arasan_nand) = { + .name = "arasan-nand", + .id = UCLASS_MTD, + .of_match = arasan_nand_dt_ids, + .probe = arasan_probe, + .priv_auto_alloc_size = sizeof(struct arasan_nand_info), +}; + void board_nand_init(void) { - struct nand_chip *nand = &nand_chip[0]; + struct udevice *dev; + int ret; - if (arasan_nand_init(nand, 0)) - puts("NAND init failed\n"); + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(arasan_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret); } diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index e932a58bf6..28db4153f5 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -11,12 +11,14 @@ #include <asm/io.h> #include <linux/errno.h> #include <nand.h> +#include <linux/ioport.h> #include <linux/mtd/mtd.h> #include <linux/mtd/rawnand.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand_ecc.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#include <dm.h> /* The NAND flash driver defines */ #define ZYNQ_NAND_CMD_PHASE 1 @@ -120,22 +122,31 @@ struct zynq_nand_smc_regs { u32 reserved2[2]; u32 eval0r; /* 0x418 */ }; -#define zynq_nand_smc_base ((struct zynq_nand_smc_regs __iomem *)\ - ZYNQ_SMC_BASEADDR) /* - * struct zynq_nand_info - Defines the NAND flash driver instance + * struct nand_config - Defines the NAND flash driver instance * @parts: Pointer to the mtd_partition structure * @nand_base: Virtual address of the NAND flash device * @end_cmd_pending: End command is pending * @end_cmd: End command */ -struct zynq_nand_info { +struct nand_config { void __iomem *nand_base; u8 end_cmd_pending; u8 end_cmd; }; +struct nand_drv { + struct zynq_nand_smc_regs *reg; + struct nand_config config; +}; + +struct zynq_nand_info { + struct udevice *dev; + struct nand_drv nand_ctrl; + struct nand_chip nand_chip; +}; + /* * struct zynq_nand_command_format - Defines NAND flash command format * @start_cmd: First cycle command (Start command) @@ -239,16 +250,18 @@ static struct nand_bbt_descr bbt_mirror_descr = { * * returns: status for command completion, -1 for Timeout */ -static int zynq_nand_waitfor_ecc_completion(void) +static int zynq_nand_waitfor_ecc_completion(struct mtd_info *mtd) { + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct nand_drv *smc = nand_get_controller_data(nand_chip); unsigned long timeout; u32 status; /* Wait max 10us */ timeout = 10; - status = readl(&zynq_nand_smc_base->esr); + status = readl(&smc->reg->esr); while (status & ZYNQ_NAND_ECC_BUSY) { - status = readl(&zynq_nand_smc_base->esr); + status = readl(&smc->reg->esr); if (timeout == 0) return -1; timeout--; @@ -266,33 +279,35 @@ static int zynq_nand_waitfor_ecc_completion(void) * * returns: 0 on success or error value on failure */ -static int zynq_nand_init_nand_flash(int option) +static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option) { + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct nand_drv *smc = nand_get_controller_data(nand_chip); u32 status; /* disable interrupts */ - writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr); + writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr); #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS /* Initialize the NAND interface by setting cycles and operation mode */ - writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr); + writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr); #endif if (option & NAND_BUSWIDTH_16) - writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor); + writel(ZYNQ_NAND_SET_OPMODE_16BIT, &smc->reg->sor); else - writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor); + writel(ZYNQ_NAND_SET_OPMODE_8BIT, &smc->reg->sor); - writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr); + writel(ZYNQ_NAND_DIRECT_CMD, &smc->reg->dcr); /* Wait till the ECC operation is complete */ - status = zynq_nand_waitfor_ecc_completion(); + status = zynq_nand_waitfor_ecc_completion(mtd); if (status < 0) { printf("%s: Timeout\n", __func__); return status; } /* Set the command1 and command2 register */ - writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r); - writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r); + writel(ZYNQ_NAND_ECC_CMD1, &smc->reg->emcmd1r); + writel(ZYNQ_NAND_ECC_CMD2, &smc->reg->emcmd2r); return 0; } @@ -311,12 +326,14 @@ static int zynq_nand_init_nand_flash(int option) static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, u8 *ecc_code) { + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct nand_drv *smc = nand_get_controller_data(nand_chip); u32 ecc_value = 0; u8 ecc_reg, ecc_byte; u32 ecc_status; /* Wait till the ECC operation is complete */ - ecc_status = zynq_nand_waitfor_ecc_completion(); + ecc_status = zynq_nand_waitfor_ecc_completion(mtd); if (ecc_status < 0) { printf("%s: Timeout\n", __func__); return ecc_status; @@ -324,7 +341,7 @@ static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data, for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) { /* Read ECC value for each block */ - ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg); + ecc_value = readl(&smc->reg->eval0r + ecc_reg); /* Get the ecc status from ecc read value */ ecc_status = (ecc_value >> 24) & 0xFF; @@ -779,10 +796,11 @@ static void zynq_nand_select_chip(struct mtd_info *mtd, int chip) static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_drv *smc = nand_get_controller_data(chip); const struct zynq_nand_command_format *curr_cmd = NULL; u8 addr_cycles = 0; - struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv; + struct nand_config *xnand = &smc->config; void *cmd_addr; unsigned long cmd_data = 0; unsigned long cmd_phase_addr = 0; @@ -821,7 +839,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, curr_cmd = &zynq_nand_commands[index]; /* Clear interrupt */ - writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr); + writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &smc->reg->cfr); /* Get the command phase address */ if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE) @@ -918,7 +936,7 @@ static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command, */ static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); /* Make sure that buf is 32 bit aligned */ if (((unsigned long)buf & 0x3) != 0) { @@ -966,7 +984,7 @@ static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) */ static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) { - struct nand_chip *chip = mtd->priv; + struct nand_chip *chip = mtd_to_nand(mtd); const u32 *nand = chip->IO_ADDR_W; /* Make sure that buf is 32 bit aligned */ @@ -1016,13 +1034,15 @@ static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) */ static int zynq_nand_device_ready(struct mtd_info *mtd) { + struct nand_chip *nand_chip = mtd_to_nand(mtd); + struct nand_drv *smc = nand_get_controller_data(nand_chip); u32 csr_val; - csr_val = readl(&zynq_nand_smc_base->csr); + csr_val = readl(&smc->reg->csr); /* Check the raw_int_status1 bit */ if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) { /* Clear the interrupt condition */ - writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr); + writel(ZYNQ_MEMC_SR_INT_ST1, &smc->reg->cfr); return 1; } @@ -1046,10 +1066,15 @@ static int zynq_nand_check_is_16bit_bw_flash(void) return is_16bit_bw; } -static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +static int zynq_nand_probe(struct udevice *dev) { - struct zynq_nand_info *xnand; + struct zynq_nand_info *zynq = dev_get_priv(dev); + struct nand_chip *nand_chip = &zynq->nand_chip; + struct nand_drv *smc = &zynq->nand_ctrl; + struct nand_config *xnand = &smc->config; struct mtd_info *mtd; + struct resource res; + ofnode of_nand; unsigned long ecc_page_size; u8 maf_id, dev_id, i; u8 get_feature[4]; @@ -1059,17 +1084,20 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) int err = -1; int is_16bit_bw; - xnand = calloc(1, sizeof(struct zynq_nand_info)); - if (!xnand) { - printf("%s: failed to allocate\n", __func__); + smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev); + of_nand = dev_read_subnode(dev, "flash@e1000000"); + if (!ofnode_valid(of_nand)) { + printf("Failed to find nand node in dt\n"); + goto fail; + } + if (ofnode_read_resource(of_nand, 0, &res)) { + printf("Failed to get nand resource\n"); goto fail; } - xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR; + xnand->nand_base = (void __iomem *)res.start; mtd = nand_to_mtd(nand_chip); - - nand_chip->priv = xnand; - mtd->priv = nand_chip; + nand_set_controller_data(nand_chip, &zynq->nand_ctrl); /* Set address of NAND IO lines */ nand_chip->IO_ADDR_R = xnand->nand_base; @@ -1100,7 +1128,7 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) nand_chip->bbt_options = NAND_BBT_USE_FLASH; /* Initialize the NAND flash interface on NAND controller */ - if (zynq_nand_init_nand_flash(nand_chip->options) < 0) { + if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) { printf("%s: nand flash init failed\n", __func__); goto fail; } @@ -1148,9 +1176,9 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) if (ondie_ecc_enabled) { /* Bypass the controller ECC block */ - ecc_cfg = readl(&zynq_nand_smc_base->emcr); + ecc_cfg = readl(&smc->reg->emcr); ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK; - writel(ecc_cfg, &zynq_nand_smc_base->emcr); + writel(ecc_cfg, &smc->reg->emcr); /* The software ECC routines won't work * with the SMC controller @@ -1198,19 +1226,19 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) ecc_page_size = 0x1; /* Set the ECC memory config register */ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), - &zynq_nand_smc_base->emcr); + &smc->reg->emcr); break; case 1024: ecc_page_size = 0x2; /* Set the ECC memory config register */ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), - &zynq_nand_smc_base->emcr); + &smc->reg->emcr); break; case 2048: ecc_page_size = 0x3; /* Set the ECC memory config register */ writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size), - &zynq_nand_smc_base->emcr); + &smc->reg->emcr); break; default: nand_chip->ecc.mode = NAND_ECC_SOFT; @@ -1235,7 +1263,7 @@ static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) printf("%s: nand_scan_tail failed\n", __func__); goto fail; } - if (nand_register(devnum, mtd)) + if (nand_register(0, mtd)) goto fail; return 0; fail: @@ -1243,12 +1271,26 @@ fail: return err; } -static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; +static const struct udevice_id zynq_nand_dt_ids[] = { + {.compatible = "arm,pl353-smc-r2p1",}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(zynq_nand) = { + .name = "zynq-nand", + .id = UCLASS_MTD, + .of_match = zynq_nand_dt_ids, + .probe = zynq_nand_probe, + .priv_auto_alloc_size = sizeof(struct zynq_nand_info), +}; void board_nand_init(void) { - struct nand_chip *nand = &nand_chip[0]; + struct udevice *dev; + int ret; - if (zynq_nand_init(nand, 0)) - puts("ZYNQ NAND init failed\n"); + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(zynq_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret); } diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 78f94148b4..c3fe8e3c56 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -173,6 +173,7 @@ struct emac_bd { #endif }; +/* Reduce amount of BUFs if you have limited amount of memory */ #define RX_BUF 32 /* Page table entries are set to 1MB, or multiples of 1MB * (not < 1MB). driver uses less bd's so use 1MB bdspace. diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 3701481256..fd33062ae4 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -204,9 +204,8 @@ static int mtk_phy_init(struct phy *phy) struct mtk_phy_instance *instance = tphy->phys[phy->id]; int ret; - /* we may use a fixed-clock here */ ret = clk_enable(&instance->ref_clk); - if (ret && ret != -ENOSYS) + if (ret) return ret; switch (instance->type) { @@ -339,7 +338,8 @@ static int mtk_tphy_probe(struct udevice *dev) tphy->phys[index] = instance; index++; - err = clk_get_by_index_nodev(subnode, 0, &instance->ref_clk); + err = clk_get_optional_nodev(subnode, "ref", + &instance->ref_clk); if (err) return err; } diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 22ee62362b..58df508d7e 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -4,6 +4,10 @@ config PINCTRL_MTK depends on PINCTRL_GENERIC bool +config PINCTRL_MT7622 + bool "MT7622 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT7623 bool "MT7623 SoC pinctrl driver" select PINCTRL_MTK @@ -12,6 +16,10 @@ config PINCTRL_MT7629 bool "MT7629 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT8512 + bool "MT8512 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT8516 bool "MT8516 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 0ab7b1595b..d7e8cf1727 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -3,7 +3,9 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o # SoC Drivers +obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c new file mode 100644 index 0000000000..1aa323c009 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1) + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = { + PIN_FIELD(0, 0, 0x320, 0x10, 16, 4), + PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4), + PIN_FIELD(5, 5, 0x320, 0x10, 0, 4), + PINS_FIELD(6, 7, 0x300, 0x10, 4, 4), + PIN_FIELD(8, 9, 0x350, 0x10, 20, 4), + PINS_FIELD(10, 13, 0x300, 0x10, 8, 4), + PIN_FIELD(14, 15, 0x320, 0x10, 4, 4), + PIN_FIELD(16, 17, 0x320, 0x10, 20, 4), + PIN_FIELD(18, 21, 0x310, 0x10, 16, 4), + PIN_FIELD(22, 22, 0x380, 0x10, 16, 4), + PINS_FIELD(23, 24, 0x300, 0x10, 24, 4), + PINS_FIELD(25, 36, 0x300, 0x10, 12, 4), + PINS_FIELD(37, 50, 0x300, 0x10, 20, 4), + PIN_FIELD(51, 70, 0x330, 0x10, 4, 4), + PINS_FIELD(71, 72, 0x300, 0x10, 16, 4), + PIN_FIELD(73, 76, 0x310, 0x10, 0, 4), + PIN_FIELD(77, 77, 0x320, 0x10, 28, 4), + PIN_FIELD(78, 78, 0x320, 0x10, 12, 4), + PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4), + PIN_FIELD(83, 83, 0x350, 0x10, 28, 4), + PIN_FIELD(84, 84, 0x330, 0x10, 0, 4), + PIN_FIELD(85, 90, 0x360, 0x10, 4, 4), + PIN_FIELD(91, 94, 0x390, 0x10, 16, 4), + PIN_FIELD(95, 97, 0x380, 0x10, 20, 4), + PIN_FIELD(98, 101, 0x390, 0x10, 0, 4), + PIN_FIELD(102, 102, 0x360, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = { + PIN_FIELD(0, 102, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_di_range[] = { + PIN_FIELD(0, 102, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_do_range[] = { + PIN_FIELD(0, 102, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = { + PIN_FIELD(0, 31, 0x920, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x820, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = { + PIN_FIELD(0, 31, 0x930, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x830, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = { + PIN_FIELD(0, 31, 0x940, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x840, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = { + PIN_FIELD(0, 31, 0x960, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x860, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = { + PIN_FIELD(0, 31, 0x970, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x870, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1), +}; + +static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range), + [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range), + [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range), +}; + +static const struct mtk_pin_desc mt7622_pins[] = { + MT7622_PIN(0, "GPIO_A"), + MT7622_PIN(1, "I2S1_IN"), + MT7622_PIN(2, "I2S1_OUT"), + MT7622_PIN(3, "I2S_BCLK"), + MT7622_PIN(4, "I2S_WS"), + MT7622_PIN(5, "I2S_MCLK"), + MT7622_PIN(6, "TXD0"), + MT7622_PIN(7, "RXD0"), + MT7622_PIN(8, "SPI_WP"), + MT7622_PIN(9, "SPI_HOLD"), + MT7622_PIN(10, "SPI_CLK"), + MT7622_PIN(11, "SPI_MOSI"), + MT7622_PIN(12, "SPI_MISO"), + MT7622_PIN(13, "SPI_CS"), + MT7622_PIN(14, "I2C_SDA"), + MT7622_PIN(15, "I2C_SCL"), + MT7622_PIN(16, "I2S2_IN"), + MT7622_PIN(17, "I2S3_IN"), + MT7622_PIN(18, "I2S4_IN"), + MT7622_PIN(19, "I2S2_OUT"), + MT7622_PIN(20, "I2S3_OUT"), + MT7622_PIN(21, "I2S4_OUT"), + MT7622_PIN(22, "GPIO_B"), + MT7622_PIN(23, "MDC"), + MT7622_PIN(24, "MDIO"), + MT7622_PIN(25, "G2_TXD0"), + MT7622_PIN(26, "G2_TXD1"), + MT7622_PIN(27, "G2_TXD2"), + MT7622_PIN(28, "G2_TXD3"), + MT7622_PIN(29, "G2_TXEN"), + MT7622_PIN(30, "G2_TXC"), + MT7622_PIN(31, "G2_RXD0"), + MT7622_PIN(32, "G2_RXD1"), + MT7622_PIN(33, "G2_RXD2"), + MT7622_PIN(34, "G2_RXD3"), + MT7622_PIN(35, "G2_RXDV"), + MT7622_PIN(36, "G2_RXC"), + MT7622_PIN(37, "NCEB"), + MT7622_PIN(38, "NWEB"), + MT7622_PIN(39, "NREB"), + MT7622_PIN(40, "NDL4"), + MT7622_PIN(41, "NDL5"), + MT7622_PIN(42, "NDL6"), + MT7622_PIN(43, "NDL7"), + MT7622_PIN(44, "NRB"), + MT7622_PIN(45, "NCLE"), + MT7622_PIN(46, "NALE"), + MT7622_PIN(47, "NDL0"), + MT7622_PIN(48, "NDL1"), + MT7622_PIN(49, "NDL2"), + MT7622_PIN(50, "NDL3"), + MT7622_PIN(51, "MDI_TP_P0"), + MT7622_PIN(52, "MDI_TN_P0"), + MT7622_PIN(53, "MDI_RP_P0"), + MT7622_PIN(54, "MDI_RN_P0"), + MT7622_PIN(55, "MDI_TP_P1"), + MT7622_PIN(56, "MDI_TN_P1"), + MT7622_PIN(57, "MDI_RP_P1"), + MT7622_PIN(58, "MDI_RN_P1"), + MT7622_PIN(59, "MDI_RP_P2"), + MT7622_PIN(60, "MDI_RN_P2"), + MT7622_PIN(61, "MDI_TP_P2"), + MT7622_PIN(62, "MDI_TN_P2"), + MT7622_PIN(63, "MDI_TP_P3"), + MT7622_PIN(64, "MDI_TN_P3"), + MT7622_PIN(65, "MDI_RP_P3"), + MT7622_PIN(66, "MDI_RN_P3"), + MT7622_PIN(67, "MDI_RP_P4"), + MT7622_PIN(68, "MDI_RN_P4"), + MT7622_PIN(69, "MDI_TP_P4"), + MT7622_PIN(70, "MDI_TN_P4"), + MT7622_PIN(71, "PMIC_SCL"), + MT7622_PIN(72, "PMIC_SDA"), + MT7622_PIN(73, "SPIC1_CLK"), + MT7622_PIN(74, "SPIC1_MOSI"), + MT7622_PIN(75, "SPIC1_MISO"), + MT7622_PIN(76, "SPIC1_CS"), + MT7622_PIN(77, "GPIO_D"), + MT7622_PIN(78, "WATCHDOG"), + MT7622_PIN(79, "RTS3_N"), + MT7622_PIN(80, "CTS3_N"), + MT7622_PIN(81, "TXD3"), + MT7622_PIN(82, "RXD3"), + MT7622_PIN(83, "PERST0_N"), + MT7622_PIN(84, "PERST1_N"), + MT7622_PIN(85, "WLED_N"), + MT7622_PIN(86, "EPHY_LED0_N"), + MT7622_PIN(87, "AUXIN0"), + MT7622_PIN(88, "AUXIN1"), + MT7622_PIN(89, "AUXIN2"), + MT7622_PIN(90, "AUXIN3"), + MT7622_PIN(91, "TXD4"), + MT7622_PIN(92, "RXD4"), + MT7622_PIN(93, "RTS4_N"), + MT7622_PIN(94, "CTS4_N"), + MT7622_PIN(95, "PWM1"), + MT7622_PIN(96, "PWM2"), + MT7622_PIN(97, "PWM3"), + MT7622_PIN(98, "PWM4"), + MT7622_PIN(99, "PWM5"), + MT7622_PIN(100, "PWM6"), + MT7622_PIN(101, "PWM7"), + MT7622_PIN(102, "GPIO_E"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. The + * hardware probably has multiple combinations of these pinouts. + */ + +/* EMMC */ +static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; +static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7622_emmc_rst_pins[] = { 37, }; +static int mt7622_emmc_rst_funcs[] = { 1, }; + +/* LED for EPHY */ +static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; +static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; +static int mt7622_ephy0_led_pins[] = { 86, }; +static int mt7622_ephy0_led_funcs[] = { 0, }; +static int mt7622_ephy1_led_pins[] = { 91, }; +static int mt7622_ephy1_led_funcs[] = { 2, }; +static int mt7622_ephy2_led_pins[] = { 92, }; +static int mt7622_ephy2_led_funcs[] = { 2, }; +static int mt7622_ephy3_led_pins[] = { 93, }; +static int mt7622_ephy3_led_funcs[] = { 2, }; +static int mt7622_ephy4_led_pins[] = { 94, }; +static int mt7622_ephy4_led_funcs[] = { 2, }; + +/* Embedded Switch */ +static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, }; +static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; +static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, }; +static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, }; +/* RGMII via ESW */ +static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 70, }; +static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* RGMII via GMAC1 */ +static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 70, }; +static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, }; + +/* RGMII via GMAC2 */ +static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, + 33, 34, 35, 36, }; +static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* I2C */ +static int mt7622_i2c0_pins[] = { 14, 15, }; +static int mt7622_i2c0_funcs[] = { 0, 0, }; +static int mt7622_i2c1_0_pins[] = { 55, 56, }; +static int mt7622_i2c1_0_funcs[] = { 0, 0, }; +static int mt7622_i2c1_1_pins[] = { 73, 74, }; +static int mt7622_i2c1_1_funcs[] = { 3, 3, }; +static int mt7622_i2c1_2_pins[] = { 87, 88, }; +static int mt7622_i2c1_2_funcs[] = { 0, 0, }; +static int mt7622_i2c2_0_pins[] = { 57, 58, }; +static int mt7622_i2c2_0_funcs[] = { 0, 0, }; +static int mt7622_i2c2_1_pins[] = { 75, 76, }; +static int mt7622_i2c2_1_funcs[] = { 3, 3, }; +static int mt7622_i2c2_2_pins[] = { 89, 90, }; +static int mt7622_i2c2_2_funcs[] = { 0, 0, }; + +/* I2S */ +static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; +static int mt7622_i2s1_in_data_pins[] = { 1, }; +static int mt7622_i2s1_in_data_funcs[] = { 0, }; +static int mt7622_i2s2_in_data_pins[] = { 16, }; +static int mt7622_i2s2_in_data_funcs[] = { 0, }; +static int mt7622_i2s3_in_data_pins[] = { 17, }; +static int mt7622_i2s3_in_data_funcs[] = { 0, }; +static int mt7622_i2s4_in_data_pins[] = { 18, }; +static int mt7622_i2s4_in_data_funcs[] = { 0, }; +static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; +static int mt7622_i2s1_out_data_pins[] = { 2, }; +static int mt7622_i2s1_out_data_funcs[] = { 0, }; +static int mt7622_i2s2_out_data_pins[] = { 19, }; +static int mt7622_i2s2_out_data_funcs[] = { 0, }; +static int mt7622_i2s3_out_data_pins[] = { 20, }; +static int mt7622_i2s3_out_data_funcs[] = { 0, }; +static int mt7622_i2s4_out_data_pins[] = { 21, }; +static int mt7622_i2s4_out_data_funcs[] = { 0, }; + +/* IR */ +static int mt7622_ir_0_tx_pins[] = { 16, }; +static int mt7622_ir_0_tx_funcs[] = { 4, }; +static int mt7622_ir_1_tx_pins[] = { 59, }; +static int mt7622_ir_1_tx_funcs[] = { 5, }; +static int mt7622_ir_2_tx_pins[] = { 99, }; +static int mt7622_ir_2_tx_funcs[] = { 3, }; +static int mt7622_ir_0_rx_pins[] = { 17, }; +static int mt7622_ir_0_rx_funcs[] = { 4, }; +static int mt7622_ir_1_rx_pins[] = { 60, }; +static int mt7622_ir_1_rx_funcs[] = { 5, }; +static int mt7622_ir_2_rx_pins[] = { 100, }; +static int mt7622_ir_2_rx_funcs[] = { 3, }; + +/* MDIO */ +static int mt7622_mdc_mdio_pins[] = { 23, 24, }; +static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; + +/* PCIE */ +static int mt7622_pcie0_0_waken_pins[] = { 14, }; +static int mt7622_pcie0_0_waken_funcs[] = { 2, }; +static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; +static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; +static int mt7622_pcie0_1_waken_pins[] = { 79, }; +static int mt7622_pcie0_1_waken_funcs[] = { 4, }; +static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; +static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; +static int mt7622_pcie1_0_waken_pins[] = { 14, }; +static int mt7622_pcie1_0_waken_funcs[] = { 3, }; +static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; +static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; + +static int mt7622_pcie0_pad_perst_pins[] = { 83, }; +static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; +static int mt7622_pcie1_pad_perst_pins[] = { 84, }; +static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; + +/* PMIC bus */ +static int mt7622_pmic_bus_pins[] = { 71, 72, }; +static int mt7622_pmic_bus_funcs[] = { 0, 0, }; + +/* Parallel NAND */ +static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, }; +static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* PWM */ +static int mt7622_pwm_ch1_0_pins[] = { 51, }; +static int mt7622_pwm_ch1_0_funcs[] = { 3, }; +static int mt7622_pwm_ch1_1_pins[] = { 73, }; +static int mt7622_pwm_ch1_1_funcs[] = { 4, }; +static int mt7622_pwm_ch1_2_pins[] = { 95, }; +static int mt7622_pwm_ch1_2_funcs[] = { 0, }; +static int mt7622_pwm_ch2_0_pins[] = { 52, }; +static int mt7622_pwm_ch2_0_funcs[] = { 3, }; +static int mt7622_pwm_ch2_1_pins[] = { 74, }; +static int mt7622_pwm_ch2_1_funcs[] = { 4, }; +static int mt7622_pwm_ch2_2_pins[] = { 96, }; +static int mt7622_pwm_ch2_2_funcs[] = { 0, }; +static int mt7622_pwm_ch3_0_pins[] = { 53, }; +static int mt7622_pwm_ch3_0_funcs[] = { 3, }; +static int mt7622_pwm_ch3_1_pins[] = { 75, }; +static int mt7622_pwm_ch3_1_funcs[] = { 4, }; +static int mt7622_pwm_ch3_2_pins[] = { 97, }; +static int mt7622_pwm_ch3_2_funcs[] = { 0, }; +static int mt7622_pwm_ch4_0_pins[] = { 54, }; +static int mt7622_pwm_ch4_0_funcs[] = { 3, }; +static int mt7622_pwm_ch4_1_pins[] = { 67, }; +static int mt7622_pwm_ch4_1_funcs[] = { 3, }; +static int mt7622_pwm_ch4_2_pins[] = { 76, }; +static int mt7622_pwm_ch4_2_funcs[] = { 4, }; +static int mt7622_pwm_ch4_3_pins[] = { 98, }; +static int mt7622_pwm_ch4_3_funcs[] = { 0, }; +static int mt7622_pwm_ch5_0_pins[] = { 68, }; +static int mt7622_pwm_ch5_0_funcs[] = { 3, }; +static int mt7622_pwm_ch5_1_pins[] = { 77, }; +static int mt7622_pwm_ch5_1_funcs[] = { 4, }; +static int mt7622_pwm_ch5_2_pins[] = { 99, }; +static int mt7622_pwm_ch5_2_funcs[] = { 0, }; +static int mt7622_pwm_ch6_0_pins[] = { 69, }; +static int mt7622_pwm_ch6_0_funcs[] = { 3, }; +static int mt7622_pwm_ch6_1_pins[] = { 78, }; +static int mt7622_pwm_ch6_1_funcs[] = { 4, }; +static int mt7622_pwm_ch6_2_pins[] = { 81, }; +static int mt7622_pwm_ch6_2_funcs[] = { 4, }; +static int mt7622_pwm_ch6_3_pins[] = { 100, }; +static int mt7622_pwm_ch6_3_funcs[] = { 0, }; +static int mt7622_pwm_ch7_0_pins[] = { 70, }; +static int mt7622_pwm_ch7_0_funcs[] = { 3, }; +static int mt7622_pwm_ch7_1_pins[] = { 82, }; +static int mt7622_pwm_ch7_1_funcs[] = { 4, }; +static int mt7622_pwm_ch7_2_pins[] = { 101, }; +static int mt7622_pwm_ch7_2_funcs[] = { 0, }; + +/* SD */ +static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; +static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; +static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; +static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +/* Serial NAND */ +static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; +static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +/* SPI NOR */ +static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; +static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; + +/* SPIC */ +static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; +static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; +static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; +static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; +static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; +static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; +static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; +static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; +static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; +static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; + +/* TDM */ +static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; +static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; +static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_0_out_data_pins[] = { 20, }; +static int mt7622_tdm_0_out_data_funcs[] = { 3, }; +static int mt7622_tdm_0_in_data_pins[] = { 21, }; +static int mt7622_tdm_0_in_data_funcs[] = { 3, }; +static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; +static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; +static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_1_out_data_pins[] = { 55, }; +static int mt7622_tdm_1_out_data_funcs[] = { 3, }; +static int mt7622_tdm_1_in_data_pins[] = { 56, }; +static int mt7622_tdm_1_in_data_funcs[] = { 3, }; + +/* UART */ +static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; +static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; +static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; +static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; +static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; +static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; +static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; +static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; +static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; +static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; +static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; +static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; +static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; +static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; +static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; +static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; +static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; +static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; +static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; +static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; +static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; +static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; +static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; +static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; +static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; +static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; + +/* Watchdog */ +static int mt7622_watchdog_pins[] = { 78, }; +static int mt7622_watchdog_funcs[] = { 0, }; + +/* WLAN LED */ +static int mt7622_wled_pins[] = { 85, }; +static int mt7622_wled_funcs[] = { 0, }; + +static const struct mtk_group_desc mt7622_groups[] = { + PINCTRL_PIN_GROUP("emmc", mt7622_emmc), + PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst), + PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds), + PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led), + PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led), + PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led), + PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led), + PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led), + PINCTRL_PIN_GROUP("esw", mt7622_esw), + PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1), + PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4), + PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw), + PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1), + PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2), + PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0), + PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0), + PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1), + PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2), + PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0), + PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1), + PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2), + PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data), + PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data), + PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data), + PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data), + PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data), + PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data), + PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data), + PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data), + PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx), + PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx), + PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx), + PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx), + PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx), + PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx), + PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio), + PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken), + PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq), + PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken), + PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq), + PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken), + PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq), + PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst), + PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst), + PINCTRL_PIN_GROUP("par_nand", mt7622_pnand), + PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus), + PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0), + PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1), + PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2), + PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0), + PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1), + PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2), + PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0), + PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1), + PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2), + PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0), + PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1), + PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2), + PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3), + PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0), + PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1), + PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2), + PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0), + PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1), + PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2), + PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3), + PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0), + PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1), + PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2), + PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0), + PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1), + PINCTRL_PIN_GROUP("snfi", mt7622_snfi), + PINCTRL_PIN_GROUP("spi_nor", mt7622_spi), + PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0), + PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1), + PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0), + PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1), + PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0), + PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold), + PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws", + mt7622_tdm_0_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws", + mt7622_tdm_0_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data), + PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data), + PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws", + mt7622_tdm_1_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws", + mt7622_tdm_1_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data), + PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data), + PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx), + PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx), + PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts), + PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx), + PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts), + PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx), + PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts), + PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx), + PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts), + PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx), + PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts), + PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx), + PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx), + PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx), + PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts), + PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx), + PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx), + PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts), + PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx), + PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts), + PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog), + PINCTRL_PIN_GROUP("wled", mt7622_wled), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", }; +static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1", + "esw_p2_p3_p4", "mdc_mdio", + "rgmii_via_gmac1", + "rgmii_via_gmac2", + "rgmii_via_esw", }; +static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", + "i2c1_2", "i2c2_0", "i2c2_1", + "i2c2_2", }; +static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws", + "i2s_in_mclk_bclk_ws", + "i2s1_in_data", "i2s2_in_data", + "i2s3_in_data", "i2s4_in_data", + "i2s1_out_data", "i2s2_out_data", + "i2s3_out_data", "i2s4_out_data", }; +static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx", + "ir_0_rx", "ir_1_rx", "ir_2_rx"}; +static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led", + "ephy1_led", "ephy2_led", + "ephy3_led", "ephy4_led", + "wled", }; +static const char *const mt7622_flash_groups[] = { "par_nand", "snfi", + "spi_nor"}; +static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken", + "pcie0_0_clkreq", "pcie0_1_waken", + "pcie0_1_clkreq", "pcie1_0_waken", + "pcie1_0_clkreq", "pcie0_pad_perst", + "pcie1_pad_perst", }; +static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", }; +static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", + "pwm_ch1_2", "pwm_ch2_0", + "pwm_ch2_1", "pwm_ch2_2", + "pwm_ch3_0", "pwm_ch3_1", + "pwm_ch3_2", "pwm_ch4_0", + "pwm_ch4_1", "pwm_ch4_2", + "pwm_ch4_3", "pwm_ch5_0", + "pwm_ch5_1", "pwm_ch5_2", + "pwm_ch6_0", "pwm_ch6_1", + "pwm_ch6_2", "pwm_ch6_3", + "pwm_ch7_0", "pwm_ch7_1", + "pwm_ch7_2", }; +static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", }; +static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1", + "spic1_0", "spic1_1", "spic2_0", + "spic2_0_wp_hold", }; +static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws", + "tdm_0_in_mclk_bclk_ws", + "tdm_0_out_data", + "tdm_0_in_data", + "tdm_1_out_mclk_bclk_ws", + "tdm_1_in_mclk_bclk_ws", + "tdm_1_out_data", + "tdm_1_in_data", }; + +static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx", + "uart1_0_tx_rx", "uart1_0_rts_cts", + "uart1_1_tx_rx", "uart1_1_rts_cts", + "uart2_0_tx_rx", "uart2_0_rts_cts", + "uart2_1_tx_rx", "uart2_1_rts_cts", + "uart2_2_tx_rx", "uart2_2_rts_cts", + "uart2_3_tx_rx", + "uart3_0_tx_rx", + "uart3_1_tx_rx", "uart3_1_rts_cts", + "uart4_0_tx_rx", + "uart4_1_tx_rx", "uart4_1_rts_cts", + "uart4_2_tx_rx", + "uart4_2_rts_cts",}; +static const char *const mt7622_wdt_groups[] = { "watchdog", }; + +static const struct mtk_function_desc mt7622_functions[] = { + {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)}, + {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)}, + {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)}, + {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)}, + {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)}, + {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)}, + {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)}, + {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)}, + {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)}, + {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)}, + {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)}, + {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)}, + {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)}, + {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)}, + {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, +}; + +static struct mtk_pinctrl_soc mt7622_data = { + .name = "mt7622_pinctrl", + .reg_cal = mt7622_reg_cals, + .pins = mt7622_pins, + .npins = ARRAY_SIZE(mt7622_pins), + .grps = mt7622_groups, + .ngrps = ARRAY_SIZE(mt7622_groups), + .funcs = mt7622_functions, + .nfuncs = ARRAY_SIZE(mt7622_functions), + .gpio_mode = 1, + .rev = MTK_PINCTRL_V0, +}; + +static int mtk_pinctrl_mt7622_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7622_data); +} + +static const struct udevice_id mt7622_pctrl_match[] = { + { .compatible = "mediatek,mt7622-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7622_pinctrl) = { + .name = "mt7622_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7622_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7622_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv), +}; + + diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index fd37dfa442..d58d840e08 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -1242,6 +1242,8 @@ static struct mtk_pinctrl_soc mt7623_data = { .ngrps = ARRAY_SIZE(mt7623_groups), .funcs = mt7623_functions, .nfuncs = ARRAY_SIZE(mt7623_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; /* diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index aa6d1c2d91..37640dd2b6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -387,6 +387,8 @@ static struct mtk_pinctrl_soc mt7629_data = { .ngrps = ARRAY_SIZE(mt7629_groups), .funcs = mt7629_functions, .nfuncs = ARRAY_SIZE(mt7629_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; static int mtk_pinctrl_mt7629_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c b/drivers/pinctrl/mediatek/pinctrl-mt8512.c new file mode 100644 index 0000000000..af43754a4d --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, false) +#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, true) +#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 30, false) + +static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = { + PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = { + PIN_FIELD(0, 115, 0x140, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_di_range[] = { + PIN_FIELD(0, 115, 0x000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_do_range[] = { + PIN_FIELD(0, 115, 0x860, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = { + PIN_FIELD(0, 115, 0x900, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = { + PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = { + PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1), + PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1), + PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1), + PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1), + PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1), + PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1), + PIN_FIELD(20, 20, 0x410, 0x10, 6, 1), + PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1), + PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1), + PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1), + PIN_FIELD(32, 32, 0x410, 0x10, 10, 1), + PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1), + PIN_FIELD(40, 40, 0x410, 0x10, 12, 1), + PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1), + PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1), + PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1), + PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1), + PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1), + PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1), + PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1), + PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1), + PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1), + PIN_FIELD(70, 70, 0x410, 0x10, 22, 1), + PIN_FIELD(71, 71, 0x410, 0x10, 23, 1), + PIN_FIELD(72, 72, 0x410, 0x10, 24, 1), + PIN_FIELD(73, 73, 0x410, 0x10, 25, 1), + PIN_FIELD(74, 74, 0x410, 0x10, 26, 1), + PIN_FIELD(75, 75, 0x410, 0x10, 27, 1), + PIN_FIELD(76, 76, 0x410, 0x10, 28, 1), + PIN_FIELD(77, 77, 0x410, 0x10, 29, 1), + PIN_FIELD(78, 78, 0x410, 0x10, 30, 1), + PIN_FIELD(79, 79, 0x410, 0x10, 31, 1), + PIN_FIELD(80, 80, 0x420, 0x10, 0, 1), + PIN_FIELD(81, 81, 0x420, 0x10, 1, 1), + PIN_FIELD(82, 82, 0x420, 0x10, 2, 1), + PIN_FIELD(83, 83, 0x420, 0x10, 3, 1), + PIN_FIELD(84, 84, 0x420, 0x10, 4, 1), + PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1), + PIN_FIELD(87, 87, 0x420, 0x10, 6, 1), + PIN_FIELDS(88, 91, 0x420, 0x10, 7, 1), + PIN_FIELDS(92, 98, 0x420, 0x10, 8, 1), + PIN_FIELDS(99, 101, 0x420, 0x10, 9, 1), + PIN_FIELDS(102, 104, 0x420, 0x10, 10, 1), + PIN_FIELDS(105, 111, 0x420, 0x10, 11, 1), + PIN_FIELDS(112, 115, 0x420, 0x10, 12, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_smt_range[] = { + PIN_FIELDS(0, 2, 0x470, 0x10, 0, 1), + PIN_FIELDS(3, 5, 0x470, 0x10, 1, 1), + PIN_FIELDS(6, 7, 0x470, 0x10, 2, 1), + PIN_FIELDS(8, 11, 0x470, 0x10, 3, 1), + PIN_FIELDS(12, 15, 0x470, 0x10, 4, 1), + PIN_FIELDS(16, 19, 0x470, 0x10, 5, 1), + PIN_FIELD(20, 20, 0x470, 0x10, 6, 1), + PIN_FIELDS(21, 25, 0x470, 0x10, 7, 1), + PIN_FIELDS(26, 27, 0x470, 0x10, 8, 1), + PIN_FIELDS(28, 31, 0x470, 0x10, 9, 1), + PIN_FIELD(32, 32, 0x470, 0x10, 10, 1), + PIN_FIELDS(33, 39, 0x470, 0x10, 11, 1), + PIN_FIELD(40, 40, 0x470, 0x10, 12, 1), + PIN_FIELDS(41, 43, 0x470, 0x10, 13, 1), + PIN_FIELDS(44, 47, 0x470, 0x10, 14, 1), + PIN_FIELDS(48, 51, 0x470, 0x10, 15, 1), + PIN_FIELDS(52, 53, 0x470, 0x10, 16, 1), + PIN_FIELDS(54, 57, 0x470, 0x10, 17, 1), + PIN_FIELDS(58, 63, 0x470, 0x10, 18, 1), + PIN_FIELDS(64, 65, 0x470, 0x10, 19, 1), + PIN_FIELDS(66, 67, 0x470, 0x10, 20, 1), + PIN_FIELDS(68, 69, 0x470, 0x10, 21, 1), + PIN_FIELD(70, 70, 0x470, 0x10, 22, 1), + PIN_FIELD(71, 71, 0x470, 0x10, 23, 1), + PIN_FIELD(72, 72, 0x470, 0x10, 24, 1), + PIN_FIELD(73, 73, 0x470, 0x10, 25, 1), + PIN_FIELD(74, 74, 0x470, 0x10, 26, 1), + PIN_FIELD(75, 75, 0x470, 0x10, 27, 1), + PIN_FIELD(76, 76, 0x470, 0x10, 28, 1), + PIN_FIELD(77, 77, 0x470, 0x10, 29, 1), + PIN_FIELD(78, 78, 0x470, 0x10, 30, 1), + PIN_FIELD(79, 79, 0x470, 0x10, 31, 1), + PIN_FIELD(80, 80, 0x480, 0x10, 0, 1), + PIN_FIELD(81, 81, 0x480, 0x10, 1, 1), + PIN_FIELD(82, 82, 0x480, 0x10, 2, 1), + PIN_FIELD(83, 83, 0x480, 0x10, 3, 1), + PIN_FIELD(84, 84, 0x480, 0x10, 4, 1), + PIN_FIELDS(85, 86, 0x480, 0x10, 5, 1), + PIN_FIELD(87, 87, 0x480, 0x10, 6, 1), + PIN_FIELDS(88, 91, 0x480, 0x10, 7, 1), + PIN_FIELDS(92, 98, 0x480, 0x10, 8, 1), + PIN_FIELDS(99, 101, 0x480, 0x10, 9, 1), + PIN_FIELDS(102, 104, 0x480, 0x10, 10, 1), + PIN_FIELDS(105, 111, 0x480, 0x10, 11, 1), + PIN_FIELDS(112, 115, 0x480, 0x10, 12, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = { + PIN_FIELDS(0, 2, 0x710, 0x10, 0, 4), + PIN_FIELDS(3, 5, 0x710, 0x10, 4, 4), + PIN_FIELDS(6, 7, 0x710, 0x10, 8, 4), + PIN_FIELDS(8, 11, 0x710, 0x10, 12, 4), + PIN_FIELDS(12, 15, 0x710, 0x10, 16, 4), + PIN_FIELDS(16, 19, 0x710, 0x10, 20, 4), + PIN_FIELD(20, 20, 0x710, 0x10, 24, 4), + PIN_FIELDS(21, 25, 0x710, 0x10, 28, 4), + PIN_FIELDS(26, 27, 0x720, 0x10, 0, 4), + PIN_FIELDS(28, 31, 0x720, 0x10, 4, 4), + PIN_FIELD(32, 32, 0x720, 0x10, 8, 4), + PIN_FIELDS(33, 39, 0x720, 0x10, 12, 4), + PIN_FIELD(40, 40, 0x720, 0x10, 16, 4), + PIN_FIELDS(41, 43, 0x720, 0x10, 20, 4), + PIN_FIELDS(44, 47, 0x720, 0x10, 24, 4), + PIN_FIELDS(48, 51, 0x720, 0x10, 28, 4), + PIN_FIELDS(52, 53, 0x730, 0x10, 0, 4), + PIN_FIELDS(54, 57, 0x730, 0x10, 4, 4), + PIN_FIELDS(58, 63, 0x730, 0x10, 8, 4), + PIN_FIELDS(64, 65, 0x730, 0x10, 12, 4), + PIN_FIELDS(66, 67, 0x730, 0x10, 16, 4), + PIN_FIELDS(68, 69, 0x730, 0x10, 20, 4), + PIN_FIELD(70, 70, 0x730, 0x10, 24, 4), + PIN_FIELD(71, 71, 0x730, 0x10, 28, 4), + PIN_FIELDS(72, 75, 0x740, 0x10, 0, 4), + PIN_FIELDS(76, 79, 0x740, 0x10, 16, 4), + PIN_FIELD(80, 80, 0x750, 0x10, 0, 4), + PIN_FIELD(81, 81, 0x750, 0x10, 4, 4), + PIN_FIELD(82, 82, 0x750, 0x10, 8, 4), + PIN_FIELDS(83, 86, 0x740, 0x10, 16, 4), + PIN_FIELD(87, 87, 0x750, 0x10, 24, 4), + PIN_FIELDS(88, 91, 0x750, 0x10, 28, 4), + PIN_FIELDS(92, 98, 0x760, 0x10, 0, 4), + PIN_FIELDS(99, 101, 0x760, 0x10, 4, 4), + PIN_FIELDS(102, 104, 0x760, 0x10, 8, 4), + PIN_FIELDS(105, 111, 0x760, 0x10, 12, 4), + PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4), +}; + +static const struct mtk_pin_reg_calc mt8512_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8512_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8512_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8512_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8512_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8512_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8512_pin_drv_range), +}; + +static const struct mtk_pin_desc mt8512_pins[] = { + MTK_PIN(0, "GPIO0", DRV_GRP4), + MTK_PIN(1, "GPIO1", DRV_GRP4), + MTK_PIN(2, "GPIO2", DRV_GRP4), + MTK_PIN(3, "GPIO3", DRV_GRP4), + MTK_PIN(4, "GPIO4", DRV_GRP4), + MTK_PIN(5, "GPIO5", DRV_GRP4), + MTK_PIN(6, "GPIO6", DRV_GRP4), + MTK_PIN(7, "GPIO7", DRV_GRP4), + MTK_PIN(8, "GPIO8", DRV_GRP4), + MTK_PIN(9, "GPIO9", DRV_GRP4), + MTK_PIN(10, "GPIO10", DRV_GRP4), + MTK_PIN(11, "GPIO11", DRV_GRP4), + MTK_PIN(12, "GPIO12", DRV_GRP4), + MTK_PIN(13, "GPIO13", DRV_GRP4), + MTK_PIN(14, "GPIO14", DRV_GRP4), + MTK_PIN(15, "GPIO15", DRV_GRP4), + MTK_PIN(16, "GPIO16", DRV_GRP4), + MTK_PIN(17, "GPIO17", DRV_GRP4), + MTK_PIN(18, "GPIO18", DRV_GRP4), + MTK_PIN(19, "GPIO19", DRV_GRP4), + MTK_PIN(20, "GPIO20", DRV_GRP4), + MTK_PIN(21, "AUDIO_SYNC", DRV_GRP4), + MTK_PIN(22, "WIFI_INTB", DRV_GRP4), + MTK_PIN(23, "BT_INTB", DRV_GRP4), + MTK_PIN(24, "BT_STEREO", DRV_GRP4), + MTK_PIN(25, "RSTNB", DRV_GRP4), + MTK_PIN(26, "USB_ID", DRV_GRP4), + MTK_PIN(27, "USB_DRV", DRV_GRP4), + MTK_PIN(28, "EINT_GAUGEING", DRV_GRP4), + MTK_PIN(29, "CHG_IRQ", DRV_GRP4), + MTK_PIN(30, "CHG_OTG", DRV_GRP4), + MTK_PIN(31, "CHG_CEB", DRV_GRP4), + MTK_PIN(32, "FL_EN", DRV_GRP4), + MTK_PIN(33, "WAN_SMS_RDY", DRV_GRP4), + MTK_PIN(34, "SOC2WAN_RESET", DRV_GRP4), + MTK_PIN(35, "WAN_FM_RDY", DRV_GRP4), + MTK_PIN(36, "WAN_DIS", DRV_GRP4), + MTK_PIN(37, "WAN_VBUS_EN", DRV_GRP4), + MTK_PIN(38, "WAN_VBAT_EN", DRV_GRP4), + MTK_PIN(39, "WAN_PWR_EN", DRV_GRP4), + MTK_PIN(40, "KPROW0", DRV_GRP4), + MTK_PIN(41, "KPROW1", DRV_GRP4), + MTK_PIN(42, "KPCOL0", DRV_GRP4), + MTK_PIN(43, "KPCOL1", DRV_GRP4), + MTK_PIN(44, "PWM0", DRV_GRP4), + MTK_PIN(45, "PWM1", DRV_GRP4), + MTK_PIN(46, "PWM2", DRV_GRP4), + MTK_PIN(47, "PWM3", DRV_GRP4), + MTK_PIN(48, "JTMS", DRV_GRP4), + MTK_PIN(49, "JTCK", DRV_GRP4), + MTK_PIN(50, "JTDI", DRV_GRP4), + MTK_PIN(51, "JTDO", DRV_GRP4), + MTK_PIN(52, "URXD0", DRV_GRP4), + MTK_PIN(53, "UTXD0", DRV_GRP4), + MTK_PIN(54, "URXD1", DRV_GRP4), + MTK_PIN(55, "UTXD1", DRV_GRP4), + MTK_PIN(56, "URTS1", DRV_GRP4), + MTK_PIN(57, "UCTS1", DRV_GRP4), + MTK_PIN(58, "RTC32K_CK", DRV_GRP4), + MTK_PIN(59, "PMIC_DVS_REQ0", DRV_GRP4), + MTK_PIN(60, "PMIC_DVS_REQ1", DRV_GRP4), + MTK_PIN(61, "WATCHDOG", DRV_GRP4), + MTK_PIN(62, "PMIC_INT", DRV_GRP4), + MTK_PIN(63, "SUSPEND", DRV_GRP4), + MTK_PIN(64, "SDA0", DRV_GRP4), + MTK_PIN(65, "SCL0", DRV_GRP4), + MTK_PIN(66, "SDA1", DRV_GRP4), + MTK_PIN(67, "SCL1", DRV_GRP4), + MTK_PIN(68, "SDA2", DRV_GRP4), + MTK_PIN(69, "SCL2", DRV_GRP4), + MTK_PIN(70, "MSDC1_CMD", DRV_GRP4), + MTK_PIN(71, "MSDC1_CLK", DRV_GRP4), + MTK_PIN(72, "MSDC1_DAT0", DRV_GRP4), + MTK_PIN(73, "MSDC1_DAT1", DRV_GRP4), + MTK_PIN(74, "MSDC1_DAT2", DRV_GRP4), + MTK_PIN(75, "MSDC1_DAT3", DRV_GRP4), + MTK_PIN(76, "MSDC0_DAT7", DRV_GRP4), + MTK_PIN(77, "MSDC0_DAT6", DRV_GRP4), + MTK_PIN(78, "MSDC0_DAT5", DRV_GRP4), + MTK_PIN(79, "MSDC0_DAT4", DRV_GRP4), + MTK_PIN(80, "MSDC0_RSTB", DRV_GRP4), + MTK_PIN(81, "MSDC0_CMD", DRV_GRP4), + MTK_PIN(82, "MSDC0_CLK", DRV_GRP4), + MTK_PIN(83, "MSDC0_DAT3", DRV_GRP4), + MTK_PIN(84, "MSDC0_DAT2", DRV_GRP4), + MTK_PIN(85, "MSDC0_DAT1", DRV_GRP4), + MTK_PIN(86, "MSDC0_DAT0", DRV_GRP4), + MTK_PIN(87, "SPDIF", DRV_GRP4), + MTK_PIN(88, "PCM_CLK", DRV_GRP4), + MTK_PIN(89, "PCM_SYNC", DRV_GRP4), + MTK_PIN(90, "PCM_RX", DRV_GRP4), + MTK_PIN(91, "PCM_TX", DRV_GRP4), + MTK_PIN(92, "I2SIN_MCLK", DRV_GRP4), + MTK_PIN(93, "I2SIN_LRCK", DRV_GRP4), + MTK_PIN(94, "I2SIN_BCK", DRV_GRP4), + MTK_PIN(95, "I2SIN_DAT0", DRV_GRP4), + MTK_PIN(96, "I2SIN_DAT1", DRV_GRP4), + MTK_PIN(97, "I2SIN_DAT2", DRV_GRP4), + MTK_PIN(98, "I2SIN_DAT3", DRV_GRP4), + MTK_PIN(99, "DMIC0_CLK", DRV_GRP4), + MTK_PIN(100, "DMIC0_DAT0", DRV_GRP4), + MTK_PIN(101, "DMIC0_DAT1", DRV_GRP4), + MTK_PIN(102, "DMIC1_CLK", DRV_GRP4), + MTK_PIN(103, "DMIC1_DAT0", DRV_GRP4), + MTK_PIN(104, "DMIC1_DAT1", DRV_GRP4), + MTK_PIN(105, "I2SO_BCK", DRV_GRP4), + MTK_PIN(106, "I2SO_LRCK", DRV_GRP4), + MTK_PIN(107, "I2SO_MCLK", DRV_GRP4), + MTK_PIN(108, "I2SO_DAT0", DRV_GRP4), + MTK_PIN(109, "I2SO_DAT1", DRV_GRP4), + MTK_PIN(110, "I2SO_DAT2", DRV_GRP4), + MTK_PIN(111, "I2SO_DAT3", DRV_GRP4), + MTK_PIN(112, "SPI_CSB", DRV_GRP4), + MTK_PIN(113, "SPI_CLK", DRV_GRP4), + MTK_PIN(114, "SPI_MISO", DRV_GRP4), + MTK_PIN(115, "SPI_MOSI", DRV_GRP4), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART */ +static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; +static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; +static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; +static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd", + "uart1_0_rxd_txd", + "uart2_0_rxd_txd", }; + +/* SNAND */ +static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; +static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; + +/* MMC0 */ +static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, }; +static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static const struct mtk_group_desc mt8512_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8512_uart1_0_rxd_txd), + PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8512_uart2_0_rxd_txd), + + PINCTRL_PIN_GROUP("msdc0", mt8512_msdc0), + + PINCTRL_PIN_GROUP("snfi", mt8512_snfi), +}; + +static const char *const mt8512_msdc_groups[] = { "msdc0" }; + +static const struct mtk_function_desc mt8512_functions[] = { + {"uart", mt8512_uart_groups, ARRAY_SIZE(mt8512_uart_groups)}, + {"msdc", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, + {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, +}; + +static struct mtk_pinctrl_soc mt8512_data = { + .name = "mt8512_pinctrl", + .reg_cal = mt8512_reg_cals, + .pins = mt8512_pins, + .npins = ARRAY_SIZE(mt8512_pins), + .grps = mt8512_groups, + .ngrps = ARRAY_SIZE(mt8512_groups), + .funcs = mt8512_functions, + .nfuncs = ARRAY_SIZE(mt8512_functions), +}; + +static int mtk_pinctrl_mt8512_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8512_data); +} + +static const struct udevice_id mt8512_pctrl_match[] = { + { .compatible = "mediatek,mt8512-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8512_pinctrl) = { + .name = "mt8512_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8512_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt8512_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 829b30e5a2..62e339e931 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -369,6 +369,8 @@ static struct mtk_pinctrl_soc mt8516_data = { .ngrps = ARRAY_SIZE(mt8516_groups), .funcs = mt8516_functions, .nfuncs = ARRAY_SIZE(mt8516_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; static int mtk_pinctrl_mt8516_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c index 8d2cd948f6..91427aed4b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c @@ -389,6 +389,8 @@ static struct mtk_pinctrl_soc mt8518_data = { .ngrps = ARRAY_SIZE(mt8518_groups), .funcs = mt8518_functions, .nfuncs = ARRAY_SIZE(mt8518_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; static int mtk_pinctrl_mt8518_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 3004335c57..c7351f32bb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -294,7 +294,72 @@ static const struct pinconf_param mtk_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, }; -int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) + +int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg) +{ + int err, disable, pullup; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + + if (disable) { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0); + if (err) + return err; + + } else { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup); + if (err) + return err; + } + + return 0; +} + +int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg) +{ + int err, disable, pullup; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + + if (disable) { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0); + if (err) + return err; + } else { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL, + pullup); + if (err) + return err; + } + + return 0; +} + +int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg) +{ + int err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0); + if (err) + return err; + return 0; +} + +int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg) { struct mtk_pinctrl_priv *priv = dev_get_priv(dev); const struct mtk_pin_desc *desc = &priv->soc->pins[pin]; @@ -309,7 +374,30 @@ int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) */ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { arg = (arg / tb->step - 1) * tb->scal; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4, + arg & 0x1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8, + (arg & 0x2) >> 1); + if (err) + return err; + } + + return 0; +} + + +int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_pin_desc *desc = &priv->soc->pins[pin]; + const struct mtk_drive_desc *tb; + int err = -ENOTSUPP; + tb = &mtk_drive[desc->drv_n]; + if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { + arg = (arg / tb->step - 1) * tb->scal; err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg); if (err) return err; @@ -322,21 +410,17 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, unsigned int param, unsigned int arg) { int err = 0; + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int rev = priv->soc->rev; switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: - arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : - (param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2; - - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL, - arg & 1); - if (err) - goto err; - - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, - !!(arg & 2)); + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_bias_set_v0(dev, pin, param); + else + err = mtk_pinconf_bias_set_v1(dev, pin, param); if (err) goto err; break; @@ -349,10 +433,8 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, goto err; break; case PIN_CONFIG_INPUT_ENABLE: - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1); - if (err) - goto err; - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0); + if (rev == MTK_PINCTRL_V1) + err = mtk_pinconf_input_enable_v1(dev, pin, param); if (err) goto err; break; @@ -381,7 +463,10 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, goto err; break; case PIN_CONFIG_DRIVE_STRENGTH: - err = mtk_pinconf_drive_set(dev, pin, arg); + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_drive_set_v0(dev, pin, arg); + else + err = mtk_pinconf_drive_set_v1(dev, pin, arg); if (err) goto err; break; @@ -475,7 +560,10 @@ static int mtk_gpio_direction_output(struct udevice *dev, static int mtk_gpio_request(struct udevice *dev, unsigned int off, const char *label) { - return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0); + struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent); + + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, + priv->soc->gpio_mode); } static int mtk_gpio_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 86559f0f14..e815761450 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -3,10 +3,12 @@ * Copyright (C) 2018 MediaTek Inc. * Author: Ryder Lee <ryder.lee@mediatek.com> */ - #ifndef __PINCTRL_MEDIATEK_H__ #define __PINCTRL_MEDIATEK_H__ +#define MTK_PINCTRL_V0 0x0 +#define MTK_PINCTRL_V1 0x1 + #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } #define MTK_PIN(_number, _name, _drv_n) { \ .number = _number, \ @@ -40,8 +42,12 @@ enum { PINCTRL_PIN_REG_DIR, PINCTRL_PIN_REG_DI, PINCTRL_PIN_REG_DO, - PINCTRL_PIN_REG_IES, PINCTRL_PIN_REG_SMT, + PINCTRL_PIN_REG_PD, + PINCTRL_PIN_REG_PU, + PINCTRL_PIN_REG_E4, + PINCTRL_PIN_REG_E8, + PINCTRL_PIN_REG_IES, PINCTRL_PIN_REG_PULLEN, PINCTRL_PIN_REG_PULLSEL, PINCTRL_PIN_REG_DRV, @@ -161,6 +167,8 @@ struct mtk_pinctrl_soc { int ngrps; const struct mtk_function_desc *funcs; int nfuncs; + int gpio_mode; + int rev; }; /** diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index c67e8804b1..0bf8a16447 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -60,6 +60,7 @@ #define DCM_TOP_EN BIT(0) enum scp_domain_type { + SCPSYS_MT7622, SCPSYS_MT7623, SCPSYS_MT7629, }; @@ -328,6 +329,7 @@ static int mtk_power_domain_hook(struct udevice *dev) case SCPSYS_MT7623: scpd->data = scp_domain_mt7623; break; + case SCPSYS_MT7622: case SCPSYS_MT7629: scpd->data = scp_domain_mt7629; break; @@ -379,6 +381,10 @@ static int mtk_power_domain_probe(struct udevice *dev) static const struct udevice_id mtk_power_domain_ids[] = { { + .compatible = "mediatek,mt7622-scpsys", + .data = SCPSYS_MT7622, + }, + { .compatible = "mediatek,mt7623-scpsys", .data = SCPSYS_MT7623, }, diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87d4c..bd95f70b61 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -100,6 +100,7 @@ config CONS_INDEX config DM_SERIAL bool "Enable Driver Model for serial drivers" depends on DM + select SYS_MALLOC_F help Enable driver model for serial. This replaces drivers/serial/serial.c with the serial uclass, which @@ -136,6 +137,7 @@ config SERIAL_SEARCH_ALL config SPL_DM_SERIAL bool "Enable Driver Model for serial drivers in SPL" depends on DM_SERIAL && SPL_DM + select SYS_SPL_MALLOC_F default y help Enable driver model for serial in SPL. This replaces @@ -146,6 +148,7 @@ config SPL_DM_SERIAL config TPL_DM_SERIAL bool "Enable Driver Model for serial drivers in TPL" depends on DM_SERIAL && TPL_DM + select SYS_TPL_MALLOC_F default y if TPL && DM_SERIAL help Enable driver model for serial in TPL. This replaces diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index af910e9efc..0ca108ee3d 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -170,21 +170,25 @@ static int spi_post_probe(struct udevice *bus) #endif #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_spi_ops *ops = spi_get_ops(bus); - - if (ops->claim_bus) - ops->claim_bus += gd->reloc_off; - if (ops->release_bus) - ops->release_bus += gd->reloc_off; - if (ops->set_wordlen) - ops->set_wordlen += gd->reloc_off; - if (ops->xfer) - ops->xfer += gd->reloc_off; - if (ops->set_speed) - ops->set_speed += gd->reloc_off; - if (ops->set_mode) - ops->set_mode += gd->reloc_off; - if (ops->cs_info) - ops->cs_info += gd->reloc_off; + static int reloc_done; + + if (!reloc_done) { + if (ops->claim_bus) + ops->claim_bus += gd->reloc_off; + if (ops->release_bus) + ops->release_bus += gd->reloc_off; + if (ops->set_wordlen) + ops->set_wordlen += gd->reloc_off; + if (ops->xfer) + ops->xfer += gd->reloc_off; + if (ops->set_speed) + ops->set_speed += gd->reloc_off; + if (ops->set_mode) + ops->set_mode += gd->reloc_off; + if (ops->cs_info) + ops->cs_info += gd->reloc_off; + reloc_done++; + } #endif return 0; diff --git a/dts/Kconfig b/dts/Kconfig index 64c98dd723..d3313dd08f 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -25,6 +25,7 @@ menu "Device Tree Control" config OF_CONTROL bool "Run-time configuration via Device Tree" select DTC + select OF_LIBFDT if !OF_PLATDATA help This feature provides for run-time configuration of U-Boot via a flattened device tree. @@ -42,6 +43,7 @@ config OF_BOARD_FIXUP config SPL_OF_CONTROL bool "Enable run-time configuration via Device Tree in SPL" depends on SPL && OF_CONTROL + select SPL_OF_LIBFDT if !SPL_OF_PLATDATA help Some boards use device tree in U-Boot but only have 4KB of SRAM which is not enough to support device tree. Disable this option to @@ -50,6 +52,7 @@ config SPL_OF_CONTROL config TPL_OF_CONTROL bool "Enable run-time configuration via Device Tree in TPL" depends on TPL && OF_CONTROL + select TPL_OF_LIBFDT if !TPL_OF_PLATDATA help Some boards use device tree in U-Boot but only have 4KB of SRAM which is not enough to support device tree. Enable this option to diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index 296c0cf9b8..17a31ec788 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -8,6 +8,8 @@ #ifndef _ASM_GENERIC_SECTIONS_H_ #define _ASM_GENERIC_SECTIONS_H_ +#include <linux/types.h> + /* References to section boundaries */ extern char _text[], _stext[], _etext[]; diff --git a/include/clk.h b/include/clk.h index a5ee53d94a..3336301815 100644 --- a/include/clk.h +++ b/include/clk.h @@ -155,6 +155,34 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk); int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk); /** + * clk_get_by_name_nodev - Get/request a clock by name without a device. + * + * This is a version of clk_get_by_name() that does not use a device. + * + * @node: The client ofnode. + * @name: The name of the clock to request, within the client's list of + * clocks. + * @clock: A pointer to a clock struct to initialize. + * @return 0 if OK, or a negative error code. + */ +int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk); + +/** + * clock_get_optional_nodev - Get/request an optinonal clock by name + * without a device. + * @node: The client ofnode. + * @name: The name of the clock to request. + * @name: The name of the clock to request, within the client's list of + * clocks. + * @clock: A pointer to a clock struct to initialize. + * + * Behaves the same as clk_get_by_name_nodev() except where there is + * no clock producer, in this case, skip the error number -ENODATA, and + * the function returns 0. + */ +int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk); + +/** * devm_clk_get - lookup and obtain a managed reference to a clock producer. * @dev: device for clock "consumer" * @id: clock consumer ID @@ -230,6 +258,18 @@ static inline int clk_get_by_name(struct udevice *dev, const char *name, return -ENOSYS; } +static inline int +clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) +{ + return -ENOSYS; +} + +static inline int +clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk) +{ + return -ENOSYS; +} + static inline int clk_release_all(struct clk *clk, int count) { return -ENOSYS; diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h new file mode 100644 index 0000000000..dfd506ed24 --- /dev/null +++ b/include/configs/mt7622.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7629 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef __MT7622_H +#define __MT7622_H + +#include <linux/sizes.h> + +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_BOOTM_LEN SZ_64M +#define CONFIG_SYS_CBSIZE SZ_1K +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* Uboot definition */ +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* SPL -> Uboot */ +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) +/* UBoot -> Kernel */ +#define CONFIG_LOADADDR 0x4007ff28 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* DRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 + +/* Ethernet */ +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.3 + +#endif diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h new file mode 100644 index 0000000000..253a54332c --- /dev/null +++ b/include/configs/mt8512.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT8512 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#ifndef __MT8512_H +#define __MT8512_H + +#include <linux/sizes.h> + +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +#define CONFIG_CPU_ARMV8 + +#define COUNTER_FREQUENCY 13000000 + +#define CONFIG_SYS_LOAD_ADDR 0x41000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Uboot definition */ +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +/* ENV Setting */ +#if defined(CONFIG_MMC_MTK) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OVERWRITE + +/* MMC offset in block unit,and block size is 0x200 */ +#define ENV_BOOT_READ_IMAGE \ + "boot_rd_img=mmc dev 0" \ + ";mmc read ${loadaddr} 0x27000 0x8000" \ + ";iminfo ${loadaddr}\0" +#endif + +/* Console configuration */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define ENV_BOOT_CMD \ + "mtk_boot=run boot_rd_img;bootm;\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6c000000\0" \ + ENV_DEVICE_SETTINGS \ + ENV_BOOT_READ_IMAGE \ + ENV_BOOT_CMD \ + "bootcmd=run mtk_boot;\0" \ + +#endif diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index f426127edc..dec5001b5f 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -92,7 +92,6 @@ "kernel_size_r=0x10000000\0" \ "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ - "script_offset_f=0x7F80000\0" \ "script_size_f=0x80000\0" #if defined(CONFIG_MMC_SDHCI_ZYNQ) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ee1ceebf12..010738363d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -94,7 +94,6 @@ /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_PANIC_HANG #define CONFIG_SYS_MAXARGS 64 /* Ethernet driver */ @@ -114,7 +113,6 @@ "kernel_addr_r=0x18000000\0" \ "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ - "script_offset_f=0x3e80000\0" \ "script_size_f=0x80000\0" \ #if defined(CONFIG_MMC_SDHCI_ZYNQ) @@ -243,7 +241,11 @@ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ # define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */ -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +# if defined(CONFIG_SPL_LOAD_FIT) +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" +# else +# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +# endif #endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 189ca81bbe..2d53237df4 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -176,7 +176,16 @@ #define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ "nor " +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_QSPI(func) \ BOOT_TARGET_DEVICES_NAND(func) \ @@ -194,7 +203,6 @@ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" \ "scriptaddr=0x20000\0" \ - "script_offset_f=0xFC0000\0" \ "script_size_f=0x40000\0" \ "fdt_addr_r=0x1f00000\0" \ "pxefile_addr_r=0x2000000\0" \ diff --git a/include/dma.h b/include/dma.h index 6c55aa3a00..5b247b5b06 100644 --- a/include/dma.h +++ b/include/dma.h @@ -304,6 +304,7 @@ int dma_send(struct dma *dma, void *src, size_t len, void *metadata); int dma_get_cfg(struct dma *dma, u32 cfg_id, void **cfg_data); #endif /* CONFIG_DMA_CHANNELS */ +#if CONFIG_IS_ENABLED(DMA) /* * dma_get_device - get a DMA device which supports transfer * type of transfer_type @@ -327,5 +328,15 @@ int dma_get_device(u32 transfer_type, struct udevice **devp); transferred and on failure return error code. */ int dma_memcpy(void *dst, void *src, size_t len); +#else +static inline int dma_get_device(u32 transfer_type, struct udevice **devp) +{ + return -ENOSYS; +} +static inline int dma_memcpy(void *dst, void *src, size_t len) +{ + return -ENOSYS; +} +#endif /* CONFIG_DMA */ #endif /* _DMA_H_ */ diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h new file mode 100644 index 0000000000..22b8d08b60 --- /dev/null +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ +#ifndef _DT_BINDINGS_CLK_MT7622_H +#define _DT_BINDINGS_CLK_MT7622_H + +/* TOPCKGEN */ + +/* FIXED_CLKS */ +#define CLK_TOP_TO_U2_PHY 0 +#define CLK_TOP_TO_U2_PHY_1P 1 +#define CLK_TOP_PCIE0_PIPE_EN 2 +#define CLK_TOP_PCIE1_PIPE_EN 3 +#define CLK_TOP_SSUSB_TX250M 4 +#define CLK_TOP_SSUSB_EQ_RX250M 5 +#define CLK_TOP_SSUSB_CDR_REF 6 +#define CLK_TOP_SSUSB_CDR_FB 7 +#define CLK_TOP_SATA_ASIC 8 +#define CLK_TOP_SATA_RBC 9 +/* FIXED_DIVS */ +#define CLK_TOP_TO_USB3_SYS 10 +#define CLK_TOP_P1_1MHZ 11 +#define CLK_TOP_4MHZ 12 +#define CLK_TOP_P0_1MHZ 13 +#define CLK_TOP_TXCLK_SRC_PRE 14 +#define CLK_TOP_RTC 15 +#define CLK_TOP_MEMPLL 16 +#define CLK_TOP_DMPLL 17 +#define CLK_TOP_SYSPLL_D2 18 +#define CLK_TOP_SYSPLL1_D2 19 +#define CLK_TOP_SYSPLL1_D4 20 +#define CLK_TOP_SYSPLL1_D8 21 +#define CLK_TOP_SYSPLL2_D4 22 +#define CLK_TOP_SYSPLL2_D8 23 +#define CLK_TOP_SYSPLL_D5 24 +#define CLK_TOP_SYSPLL3_D2 25 +#define CLK_TOP_SYSPLL3_D4 26 +#define CLK_TOP_SYSPLL4_D2 27 +#define CLK_TOP_SYSPLL4_D4 28 +#define CLK_TOP_SYSPLL4_D16 29 +#define CLK_TOP_UNIVPLL 30 +#define CLK_TOP_UNIVPLL_D2 31 +#define CLK_TOP_UNIVPLL1_D2 32 +#define CLK_TOP_UNIVPLL1_D4 33 +#define CLK_TOP_UNIVPLL1_D8 34 +#define CLK_TOP_UNIVPLL1_D16 35 +#define CLK_TOP_UNIVPLL2_D2 36 +#define CLK_TOP_UNIVPLL2_D4 37 +#define CLK_TOP_UNIVPLL2_D8 38 +#define CLK_TOP_UNIVPLL2_D16 39 +#define CLK_TOP_UNIVPLL_D5 40 +#define CLK_TOP_UNIVPLL3_D2 41 +#define CLK_TOP_UNIVPLL3_D4 42 +#define CLK_TOP_UNIVPLL3_D16 43 +#define CLK_TOP_UNIVPLL_D7 44 +#define CLK_TOP_UNIVPLL_D80_D4 45 +#define CLK_TOP_UNIV48M 46 +#define CLK_TOP_SGMIIPLL 47 +#define CLK_TOP_SGMIIPLL_D2 48 +#define CLK_TOP_AUD1PLL 49 +#define CLK_TOP_AUD2PLL 50 +#define CLK_TOP_AUD_I2S2_MCK 51 +#define CLK_TOP_TO_USB3_REF 52 +#define CLK_TOP_PCIE1_MAC_EN 53 +#define CLK_TOP_PCIE0_MAC_EN 54 +#define CLK_TOP_ETH_500M 55 +/* TOP_MUXES */ +#define CLK_TOP_AXI_SEL 56 +#define CLK_TOP_MEM_SEL 57 +#define CLK_TOP_DDRPHYCFG_SEL 58 +#define CLK_TOP_ETH_SEL 59 +#define CLK_TOP_PWM_SEL 60 +#define CLK_TOP_F10M_REF_SEL 61 +#define CLK_TOP_NFI_INFRA_SEL 62 +#define CLK_TOP_FLASH_SEL 63 +#define CLK_TOP_UART_SEL 64 +#define CLK_TOP_SPI0_SEL 65 +#define CLK_TOP_SPI1_SEL 66 +#define CLK_TOP_MSDC50_0_SEL 67 +#define CLK_TOP_MSDC30_0_SEL 68 +#define CLK_TOP_MSDC30_1_SEL 69 +#define CLK_TOP_A1SYS_HP_SEL 70 +#define CLK_TOP_A2SYS_HP_SEL 71 +#define CLK_TOP_INTDIR_SEL 72 +#define CLK_TOP_AUD_INTBUS_SEL 73 +#define CLK_TOP_PMICSPI_SEL 74 +#define CLK_TOP_SCP_SEL 75 +#define CLK_TOP_ATB_SEL 76 +#define CLK_TOP_HIF_SEL 77 +#define CLK_TOP_AUDIO_SEL 78 +#define CLK_TOP_U2_SEL 79 +#define CLK_TOP_AUD1_SEL 80 +#define CLK_TOP_AUD2_SEL 81 +#define CLK_TOP_IRRX_SEL 82 +#define CLK_TOP_IRTX_SEL 83 +#define CLK_TOP_ASM_L_SEL 84 +#define CLK_TOP_ASM_M_SEL 85 +#define CLK_TOP_ASM_H_SEL 86 +#define CLK_TOP_APLL1_SEL 87 +#define CLK_TOP_APLL2_SEL 88 +#define CLK_TOP_I2S0_MCK_SEL 89 +#define CLK_TOP_I2S1_MCK_SEL 90 +#define CLK_TOP_I2S2_MCK_SEL 91 +#define CLK_TOP_I2S3_MCK_SEL 92 +#define CLK_TOP_APLL1_DIV 93 +#define CLK_TOP_APLL2_DIV 94 +#define CLK_TOP_I2S0_MCK_DIV 95 +#define CLK_TOP_I2S1_MCK_DIV 96 +#define CLK_TOP_I2S2_MCK_DIV 97 +#define CLK_TOP_I2S3_MCK_DIV 98 +#define CLK_TOP_A1SYS_HP_DIV 99 +#define CLK_TOP_A2SYS_HP_DIV 100 +#define CLK_TOP_APLL1_DIV_PD 101 +#define CLK_TOP_APLL2_DIV_PD 102 +#define CLK_TOP_I2S0_MCK_DIV_PD 103 +#define CLK_TOP_I2S1_MCK_DIV_PD 104 +#define CLK_TOP_I2S2_MCK_DIV_PD 105 +#define CLK_TOP_I2S3_MCK_DIV_PD 106 + +/* INFRACFG */ + +#define CLK_INFRA_DBGCLK_PD 0 +#define CLK_INFRA_TRNG 1 +#define CLK_INFRA_AUDIO_PD 2 +#define CLK_INFRA_IRRX_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_PMIC_PD 5 + +/* PERICFG */ + +#define CLK_PERI_THERM_PD 0 +#define CLK_PERI_PWM1_PD 1 +#define CLK_PERI_PWM2_PD 2 +#define CLK_PERI_PWM3_PD 3 +#define CLK_PERI_PWM4_PD 4 +#define CLK_PERI_PWM5_PD 5 +#define CLK_PERI_PWM6_PD 6 +#define CLK_PERI_PWM7_PD 7 +#define CLK_PERI_PWM_PD 8 +#define CLK_PERI_AP_DMA_PD 9 +#define CLK_PERI_MSDC30_0_PD 10 +#define CLK_PERI_MSDC30_1_PD 11 +#define CLK_PERI_UART0_PD 12 +#define CLK_PERI_UART1_PD 13 +#define CLK_PERI_UART2_PD 14 +#define CLK_PERI_UART3_PD 15 +#define CLK_PERI_BTIF_PD 16 +#define CLK_PERI_I2C0_PD 17 +#define CLK_PERI_I2C1_PD 18 +#define CLK_PERI_I2C2_PD 19 +#define CLK_PERI_SPI1_PD 20 +#define CLK_PERI_AUXADC_PD 21 +#define CLK_PERI_SPI0_PD 22 +#define CLK_PERI_SNFI_PD 23 +#define CLK_PERI_NFI_PD 24 +#define CLK_PERI_NFIECC_PD 25 +#define CLK_PERI_FLASH_PD 26 +#define CLK_PERI_IRTX_PD 27 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIV2PLL 2 +#define CLK_APMIXED_ETH1PLL 3 +#define CLK_APMIXED_ETH2PLL 4 +#define CLK_APMIXED_AUD1PLL 5 +#define CLK_APMIXED_AUD2PLL 6 +#define CLK_APMIXED_TRGPLL 7 +#define CLK_APMIXED_SGMIPLL 8 + +/* AUDIOSYS */ + +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_HDMI 1 +#define CLK_AUDIO_SPDF 2 +#define CLK_AUDIO_APLL 3 +#define CLK_AUDIO_I2SIN1 4 +#define CLK_AUDIO_I2SIN2 5 +#define CLK_AUDIO_I2SIN3 6 +#define CLK_AUDIO_I2SIN4 7 +#define CLK_AUDIO_I2SO1 8 +#define CLK_AUDIO_I2SO2 9 +#define CLK_AUDIO_I2SO3 10 +#define CLK_AUDIO_I2SO4 11 +#define CLK_AUDIO_ASRCI1 12 +#define CLK_AUDIO_ASRCI2 13 +#define CLK_AUDIO_ASRCO1 14 +#define CLK_AUDIO_ASRCO2 15 +#define CLK_AUDIO_INTDIR 16 +#define CLK_AUDIO_A1SYS 17 +#define CLK_AUDIO_A2SYS 18 +#define CLK_AUDIO_UL1 19 +#define CLK_AUDIO_UL2 20 +#define CLK_AUDIO_UL3 21 +#define CLK_AUDIO_UL4 22 +#define CLK_AUDIO_UL5 23 +#define CLK_AUDIO_UL6 24 +#define CLK_AUDIO_DL1 25 +#define CLK_AUDIO_DL2 26 +#define CLK_AUDIO_DL3 27 +#define CLK_AUDIO_DL4 28 +#define CLK_AUDIO_DL5 29 +#define CLK_AUDIO_DL6 30 +#define CLK_AUDIO_DLMCH 31 +#define CLK_AUDIO_ARB1 32 +#define CLK_AUDIO_AWB 33 +#define CLK_AUDIO_AWB3 34 +#define CLK_AUDIO_DAI 35 +#define CLK_AUDIO_MOD 36 +#define CLK_AUDIO_ASRCI3 37 +#define CLK_AUDIO_ASRCI4 38 +#define CLK_AUDIO_ASRCO3 39 +#define CLK_AUDIO_ASRCO4 40 +#define CLK_AUDIO_MEM_ASRC1 41 +#define CLK_AUDIO_MEM_ASRC2 42 +#define CLK_AUDIO_MEM_ASRC3 43 +#define CLK_AUDIO_MEM_ASRC4 44 +#define CLK_AUDIO_MEM_ASRC5 45 +#define CLK_AUDIO_AFE_CONN 46 +#define CLK_AUDIO_NR_CLK 47 + +/* SSUSBSYS */ + +#define CLK_SSUSB_U2_PHY_1P_EN 0 +#define CLK_SSUSB_U2_PHY_EN 1 +#define CLK_SSUSB_REF_EN 2 +#define CLK_SSUSB_SYS_EN 3 +#define CLK_SSUSB_MCU_EN 4 +#define CLK_SSUSB_DMA_EN 5 +#define CLK_SSUSB_NR_CLK 6 + +/* PCIESYS */ + +#define CLK_PCIE_P1_AUX_EN 0 +#define CLK_PCIE_P1_OBFF_EN 1 +#define CLK_PCIE_P1_AHB_EN 2 +#define CLK_PCIE_P1_AXI_EN 3 +#define CLK_PCIE_P1_MAC_EN 4 +#define CLK_PCIE_P1_PIPE_EN 5 +#define CLK_PCIE_P0_AUX_EN 6 +#define CLK_PCIE_P0_OBFF_EN 7 +#define CLK_PCIE_P0_AHB_EN 8 +#define CLK_PCIE_P0_AXI_EN 9 +#define CLK_PCIE_P0_MAC_EN 10 +#define CLK_PCIE_P0_PIPE_EN 11 +#define CLK_SATA_AHB_EN 12 +#define CLK_SATA_AXI_EN 13 +#define CLK_SATA_ASIC_EN 14 +#define CLK_SATA_RBC_EN 15 +#define CLK_SATA_PM_EN 16 +#define CLK_PCIE_NR_CLK 17 + +/* ETHSYS */ + +#define CLK_ETH_HSDMA_EN 0 +#define CLK_ETH_ESW_EN 1 +#define CLK_ETH_GP2_EN 2 +#define CLK_ETH_GP1_EN 3 +#define CLK_ETH_GP0_EN 4 + +/* SGMIISYS */ + +#define CLK_SGMII_TX250M_EN 0 +#define CLK_SGMII_RX250M_EN 1 +#define CLK_SGMII_CDR_REF 2 +#define CLK_SGMII_CDR_FB 3 + +#endif /* _DT_BINDINGS_CLK_MT7622_H */ + diff --git a/include/dt-bindings/clock/mt8512-clk.h b/include/dt-bindings/clock/mt8512-clk.h new file mode 100644 index 0000000000..fdc3474c01 --- /dev/null +++ b/include/dt-bindings/clock/mt8512-clk.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT8512_H +#define _DT_BINDINGS_CLK_MT8512_H + +/* TOPCKGEN */ + +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_CLK32K 1 +#define CLK_TOP_SYSPLL1_D2 2 +#define CLK_TOP_SYSPLL1_D4 3 +#define CLK_TOP_SYSPLL1_D8 4 +#define CLK_TOP_SYSPLL1_D16 5 +#define CLK_TOP_SYSPLL_D3 6 +#define CLK_TOP_SYSPLL2_D2 7 +#define CLK_TOP_SYSPLL2_D4 8 +#define CLK_TOP_SYSPLL2_D8 9 +#define CLK_TOP_SYSPLL_D5 10 +#define CLK_TOP_SYSPLL3_D4 11 +#define CLK_TOP_SYSPLL_D7 12 +#define CLK_TOP_SYSPLL4_D2 13 +#define CLK_TOP_UNIVPLL 14 +#define CLK_TOP_UNIVPLL_D2 15 +#define CLK_TOP_UNIVPLL1_D2 16 +#define CLK_TOP_UNIVPLL1_D4 17 +#define CLK_TOP_UNIVPLL1_D8 18 +#define CLK_TOP_UNIVPLL_D3 19 +#define CLK_TOP_UNIVPLL2_D2 20 +#define CLK_TOP_UNIVPLL2_D4 21 +#define CLK_TOP_UNIVPLL2_D8 22 +#define CLK_TOP_UNIVPLL_D5 23 +#define CLK_TOP_UNIVPLL3_D2 24 +#define CLK_TOP_UNIVPLL3_D4 25 +#define CLK_TOP_TCONPLL_D2 26 +#define CLK_TOP_TCONPLL_D4 27 +#define CLK_TOP_TCONPLL_D8 28 +#define CLK_TOP_TCONPLL_D16 29 +#define CLK_TOP_TCONPLL_D32 30 +#define CLK_TOP_TCONPLL_D64 31 +#define CLK_TOP_USB20_192M 32 +#define CLK_TOP_USB20_192M_D2 33 +#define CLK_TOP_USB20_192M_D4_T 34 +#define CLK_TOP_APLL1 35 +#define CLK_TOP_APLL1_D2 36 +#define CLK_TOP_APLL1_D3 37 +#define CLK_TOP_APLL1_D4 38 +#define CLK_TOP_APLL1_D8 39 +#define CLK_TOP_APLL1_D16 40 +#define CLK_TOP_APLL2 41 +#define CLK_TOP_APLL2_D2 42 +#define CLK_TOP_APLL2_D3 43 +#define CLK_TOP_APLL2_D4 44 +#define CLK_TOP_APLL2_D8 45 +#define CLK_TOP_APLL2_D16 46 +#define CLK_TOP_CLK26M 47 +#define CLK_TOP_SYS_26M_D2 48 +#define CLK_TOP_MSDCPLL 49 +#define CLK_TOP_MSDCPLL_D2 50 +#define CLK_TOP_DSPPLL 51 +#define CLK_TOP_DSPPLL_D2 52 +#define CLK_TOP_DSPPLL_D4 53 +#define CLK_TOP_DSPPLL_D8 54 +#define CLK_TOP_IPPLL 55 +#define CLK_TOP_IPPLL_D2 56 +#define CLK_TOP_NFI2X_CK_D2 57 +#define CLK_TOP_AXI_SEL 58 +#define CLK_TOP_MEM_SEL 59 +#define CLK_TOP_UART_SEL 60 +#define CLK_TOP_SPI_SEL 61 +#define CLK_TOP_SPIS_SEL 62 +#define CLK_TOP_MSDC50_0_HC_SEL 63 +#define CLK_TOP_MSDC2_2_HC_SEL 64 +#define CLK_TOP_MSDC50_0_SEL 65 +#define CLK_TOP_MSDC50_2_SEL 66 +#define CLK_TOP_MSDC30_1_SEL 67 +#define CLK_TOP_AUDIO_SEL 68 +#define CLK_TOP_AUD_INTBUS_SEL 69 +#define CLK_TOP_HAPLL1_SEL 70 +#define CLK_TOP_HAPLL2_SEL 71 +#define CLK_TOP_A2SYS_SEL 72 +#define CLK_TOP_A1SYS_SEL 73 +#define CLK_TOP_ASM_L_SEL 74 +#define CLK_TOP_ASM_M_SEL 75 +#define CLK_TOP_ASM_H_SEL 76 +#define CLK_TOP_AUD_SPDIF_SEL 77 +#define CLK_TOP_AUD_1_SEL 78 +#define CLK_TOP_AUD_2_SEL 79 +#define CLK_TOP_SSUSB_SYS_SEL 80 +#define CLK_TOP_SSUSB_XHCI_SEL 81 +#define CLK_TOP_SPM_SEL 82 +#define CLK_TOP_I2C_SEL 83 +#define CLK_TOP_PWM_SEL 84 +#define CLK_TOP_DSP_SEL 85 +#define CLK_TOP_NFI2X_SEL 86 +#define CLK_TOP_SPINFI_SEL 87 +#define CLK_TOP_ECC_SEL 88 +#define CLK_TOP_GCPU_SEL 89 +#define CLK_TOP_GCPU_CPM_SEL 90 +#define CLK_TOP_MBIST_DIAG_SEL 91 +#define CLK_TOP_IP0_NNA_SEL 92 +#define CLK_TOP_IP1_NNA_SEL 93 +#define CLK_TOP_IP2_WFST_SEL 94 +#define CLK_TOP_SFLASH_SEL 95 +#define CLK_TOP_SRAM_SEL 96 +#define CLK_TOP_MM_SEL 97 +#define CLK_TOP_DPI0_SEL 98 +#define CLK_TOP_DBG_ATCLK_SEL 99 +#define CLK_TOP_OCC_104M_SEL 100 +#define CLK_TOP_OCC_68M_SEL 101 +#define CLK_TOP_OCC_182M_SEL 102 + +/* TOPCKGEN Gates */ +#define CLK_TOP_CONN_32K 0 +#define CLK_TOP_CONN_26M 1 +#define CLK_TOP_DSP_32K 2 +#define CLK_TOP_DSP_26M 3 +#define CLK_TOP_USB20_48M_EN 4 +#define CLK_TOP_UNIVPLL_48M_EN 5 +#define CLK_TOP_SSUSB_TOP_CK_EN 6 +#define CLK_TOP_SSUSB_PHY_CK_EN 7 +#define CLK_TOP_I2SI1_MCK 8 +#define CLK_TOP_TDMIN_MCK 9 +#define CLK_TOP_I2SO1_MCK 10 + +/* INFRASYS */ + +#define CLK_INFRA_DSP_AXI 0 +#define CLK_INFRA_APXGPT 1 +#define CLK_INFRA_ICUSB 2 +#define CLK_INFRA_GCE 3 +#define CLK_INFRA_THERM 4 +#define CLK_INFRA_PWM_HCLK 5 +#define CLK_INFRA_PWM1 6 +#define CLK_INFRA_PWM2 7 +#define CLK_INFRA_PWM3 8 +#define CLK_INFRA_PWM4 9 +#define CLK_INFRA_PWM5 10 +#define CLK_INFRA_PWM 11 +#define CLK_INFRA_UART0 12 +#define CLK_INFRA_UART1 13 +#define CLK_INFRA_UART2 14 +#define CLK_INFRA_DSP_UART 15 +#define CLK_INFRA_GCE_26M 16 +#define CLK_INFRA_CQDMA_FPC 17 +#define CLK_INFRA_BTIF 18 +#define CLK_INFRA_SPI 19 +#define CLK_INFRA_MSDC0 20 +#define CLK_INFRA_MSDC1 21 +#define CLK_INFRA_DVFSRC 22 +#define CLK_INFRA_GCPU 23 +#define CLK_INFRA_TRNG 24 +#define CLK_INFRA_AUXADC 25 +#define CLK_INFRA_AUXADC_MD 26 +#define CLK_INFRA_AP_DMA 27 +#define CLK_INFRA_DEBUGSYS 28 +#define CLK_INFRA_AUDIO 29 +#define CLK_INFRA_FLASHIF 30 +#define CLK_INFRA_PWM_FB6 31 +#define CLK_INFRA_PWM_FB7 32 +#define CLK_INFRA_AUD_ASRC 33 +#define CLK_INFRA_AUD_26M 34 +#define CLK_INFRA_SPIS 35 +#define CLK_INFRA_CQ_DMA 36 +#define CLK_INFRA_AP_MSDC0 37 +#define CLK_INFRA_MD_MSDC0 38 +#define CLK_INFRA_MSDC0_SRC 39 +#define CLK_INFRA_MSDC1_SRC 40 +#define CLK_INFRA_IRRX_26M 41 +#define CLK_INFRA_IRRX_32K 42 +#define CLK_INFRA_I2C0_AXI 43 +#define CLK_INFRA_I2C1_AXI 44 +#define CLK_INFRA_I2C2_AXI 45 +#define CLK_INFRA_NFI 46 +#define CLK_INFRA_NFIECC 47 +#define CLK_INFRA_NFI_HCLK 48 +#define CLK_INFRA_SUSB_133 49 +#define CLK_INFRA_USB_SYS 50 +#define CLK_INFRA_USB_XHCI 51 +#define CLK_INFRA_NR_CLK 52 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL2 2 +#define CLK_APMIXED_MSDCPLL 3 +#define CLK_APMIXED_APLL1 4 +#define CLK_APMIXED_APLL2 5 +#define CLK_APMIXED_IPPLL 6 +#define CLK_APMIXED_DSPPLL 7 +#define CLK_APMIXED_TCONPLL 8 +#define CLK_APMIXED_NR_CLK 9 + +#endif /* _DT_BINDINGS_CLK_MT8512_H */ diff --git a/include/spl.h b/include/spl.h index 02aa1ff85d..cd4669f5aa 100644 --- a/include/spl.h +++ b/include/spl.h @@ -462,6 +462,26 @@ int spl_ymodem_load_image(struct spl_image_info *spl_image, void spl_invoke_atf(struct spl_image_info *spl_image); /** + * bl2_plat_get_bl31_params() - prepare params for bl31. + * @bl32_entry address of BL32 executable (secure) + * @bl33_entry address of BL33 executable (non secure) + * @fdt_addr address of Flat Device Tree + * + * This function assigns a pointer to the memory that the platform has kept + * aside to pass platform specific and trusted firmware related information + * to BL31. This memory is allocated by allocating memory to + * bl2_to_bl31_params_mem structure which is a superset of all the + * structure whose information is passed to BL31 + * NOTE: This function should be called only once and should be done + * before generating params to BL31 + * + * @return bl31 params structure pointer + */ +struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, + uintptr_t bl33_entry, + uintptr_t fdt_addr); + +/** * spl_optee_entry - entry function for optee * * args defind in op-tee project diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py index 356d9a20f2..84b3f95850 100755 --- a/test/py/tests/test_fit.py +++ b/test/py/tests/test_fit.py @@ -83,13 +83,16 @@ base_fdt = ''' /dts-v1/; / { - model = "Sandbox Verified Boot Test"; - compatible = "sandbox"; + #address-cells = <1>; + #size-cells = <0>; + + model = "Sandbox Verified Boot Test"; + compatible = "sandbox"; reset@0 { compatible = "sandbox,reset"; + reg = <0>; }; - }; ''' diff --git a/test/py/tests/test_hush_if_test.py b/test/py/tests/test_hush_if_test.py index bba8d41d96..d117921a6a 100644 --- a/test/py/tests/test_hush_if_test.py +++ b/test/py/tests/test_hush_if_test.py @@ -7,6 +7,10 @@ import os import os.path import pytest +# TODO: These tests should be converted to a C test. +# For more information please take a look at the thread +# https://lists.denx.de/pipermail/u-boot/2019-October/388732.html + pytestmark = pytest.mark.buildconfigspec('hush_parser') # The list of "if test" conditions to test. @@ -52,6 +56,33 @@ subtests = ( ('test 123 -ge 123', True), ('test 123 -ge 456', False), + # Octal tests + + ('test 010 -eq 010', True), + ('test 010 -eq 011', False), + + ('test 010 -ne 011', True), + ('test 010 -ne 010', False), + + # Hexadecimal tests + + ('test 0x2000000 -gt 0x2000001', False), + ('test 0x2000000 -gt 0x2000000', False), + ('test 0x2000000 -gt 0x1ffffff', True), + + # Mixed tests + + ('test 010 -eq 10', False), + ('test 010 -ne 10', True), + ('test 0xa -eq 10', True), + ('test 0xa -eq 012', True), + + ('test 2000000 -gt 0x1ffffff', False), + ('test 0x2000000 -gt 1ffffff', True), + ('test 0x2000000 -lt 1ffffff', False), + ('test 0x2000000 -eq 2000000', False), + ('test 0x2000000 -ne 2000000', True), + ('test -z ""', True), ('test -z "aaa"', False), |