diff options
39 files changed, 1059 insertions, 928 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index f07d9209a7..ce4376b100 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -25,6 +25,10 @@ PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string +# Enable gc-sections to enable generation of smaller images. +PLATFORM_LDFLAGS += --gc-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections + # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; # see "[PATCH,rs6000] make -mno-spe work as expected" on # http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 3f80700711..fc5d951e9a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -34,6 +34,9 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <post.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> DECLARE_GLOBAL_DATA_PTR; @@ -282,3 +285,219 @@ void mpc85xx_reginfo(void) print_laws(); print_lbc_regs(); } + +#if CONFIG_POST & CONFIG_SYS_POST_MEMORY + +/* Board-specific functions defined in each board's ddr.c */ +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn); +unsigned int + setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); + +static void dump_spd_ddr_reg(void) +{ + int i, j, k, m; + u8 *p_8; + u32 *p_32; + ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + generic_spd_eeprom_t + spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + fsl_ddr_get_spd(spd[i], i); + + puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("Byte (hex) "); + k = 1; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) + printf("Dimm%d ", k++); + } + puts("\n"); + for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { + m = 0; + printf("%3d (0x%02x) ", k, k); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + p_8 = (u8 *) &spd[i][j]; + if (p_8[k]) { + printf("0x%02x ", p_8[k]); + m++; + } else + puts(" "); + } + } + if (m) + puts("\n"); + else + puts("\r"); + } + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + switch (i) { + case 0: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; + break; +#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR + case 1: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; + break; +#endif + default: + printf("%s unexpected controller number = %u\n", + __func__, i); + return; + } + } + printf("DDR registers dump for all controllers " + "(zero vaule is omitted)...\n"); + puts("Offset (hex) "); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); + puts("\n"); + for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { + m = 0; + printf("%6d (0x%04x)", k * 4, k * 4); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + p_32 = (u32 *) ddr[i]; + if (p_32[k]) { + printf(" 0x%08x", p_32[k]); + m++; + } else + puts(" "); + } + if (m) + puts("\n"); + else + puts("\r"); + } + puts("\n"); +} + +/* invalid the TLBs for DDR and setup new ones to cover p_addr */ +static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) +{ + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + + ptr = vstart; + + while (ptr < (vstart + size)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + + /* Setup new tlb to cover the physical address */ + setup_ddr_tlbs_phys(p_addr, size>>20); + + ptr = vstart; + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); + } else { + printf("TLB error in function %s\n", __func__); + return -1; + } + + return 0; +} + +/* + * slide the testing window up to test another area + * for 32_bit system, the maximum testable memory is limited to + * CONFIG_MAX_MEM_MAPPED + */ +int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + phys_addr_t test_cap, p_addr; + phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + test_cap = p_size; +#else + test_cap = gd->ram_size; +#endif + p_addr = (*vstart) + (*size) + (*phys_offset); + if (p_addr < test_cap - 1) { + p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + if (reset_tlb(p_addr, p_size, phys_offset) == -1) + return -1; + *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *size = (u32) p_size; + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)(*vstart) + (*phys_offset), + (u64)(*vstart) + (*phys_offset) + (*size) - 1); + } else + return 1; + + return 0; +} + +/* initialization for testing area */ +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + + *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ + *phys_offset = 0; + +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + puts("Cannot test more than "); + print_size(CONFIG_MAX_MEM_MAPPED, + " without proper 36BIT support.\n"); + } +#endif + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)(*vstart) + (*phys_offset), + (u64)(*vstart) + (*phys_offset) + (*size) - 1); + + return 0; +} + +/* invalid TLBs for DDR and remap as normal after testing */ +int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + + /* disable the TLBs for this testing */ + ptr = *vstart; + + while (ptr < (*vstart) + (*size)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + + puts("Remap DDR "); + setup_ddr_tlbs(gd->ram_size>>20); + puts("\n"); + + return 0; +} + +void arch_memory_failure_handle(void) +{ + dump_spd_ddr_reg(); +} +#endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 45403641cf..53e0596554 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -48,6 +48,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) ulong spin_tbl_addr = get_spin_phys_addr(); u32 bootpg = determine_mp_bootpg(); u32 id = get_my_id(); + const char *enable_method; off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { @@ -63,10 +64,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) fdt_setprop_string(blob, off, "status", "disabled"); } + + if (hold_cores_in_reset(0)) { +#ifdef CONFIG_FSL_CORENET + /* Cores held in reset, use BRR to release */ + enable_method = "fsl,brr-holdoff"; +#else + /* Cores held in reset, use EEBPCR to release */ + enable_method = "fsl,eebpcr-holdoff"; +#endif + } else { + /* Cores out of reset and in a spin-loop */ + enable_method = "spin-table"; + + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } + fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); + enable_method); } else { printf ("cpu NULL\n"); } diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 603baef1bd..a019b1bdb1 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -36,6 +36,27 @@ u32 get_my_id() return mfspr(SPRN_PIR); } +/* + * Determine if U-Boot should keep secondary cores in reset, or let them out + * of reset and hold them in a spinloop + */ +int hold_cores_in_reset(int verbose) +{ + const char *s = getenv("mp_holdoff"); + + /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */ + if (s && (*s == 'y' || *s == 'Y' || *s == '1')) { + if (verbose) { + puts("Secondary cores are being held in reset.\n"); + puts("See 'mp_holdoff' environment variable\n"); + } + + return 1; + } + + return 0; +} + int cpu_reset(int nr) { volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); @@ -51,6 +72,9 @@ int cpu_status(int nr) { u32 *table, id = get_my_id(); + if (hold_cores_in_reset(1)) + return 0; + if (nr == id) { table = (u32 *)get_spin_virt_addr(); printf("table base @ 0x%p\n", table); @@ -133,6 +157,9 @@ int cpu_release(int nr, int argc, char * const argv[]) u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY; u64 boot_addr; + if (hold_cores_in_reset(1)) + return 0; + if (nr == get_my_id()) { printf("Invalid to release the boot core.\n\n"); return 1; @@ -353,6 +380,10 @@ void setup_mp(void) ulong fixup = (ulong)&__secondary_start_page; u32 bootpg = determine_mp_bootpg(); + /* Some OSes expect secondary cores to be held in reset */ + if (hold_cores_in_reset(0)) + return; + /* Store the bootpg's SDRAM address for use by secondary CPU cores */ __bootpg_addr = bootpg; diff --git a/arch/powerpc/cpu/mpc85xx/mp.h b/arch/powerpc/cpu/mpc85xx/mp.h index 3422cc1070..87bac37152 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.h +++ b/arch/powerpc/cpu/mpc85xx/mp.h @@ -6,6 +6,7 @@ ulong get_spin_phys_addr(void); ulong get_spin_virt_addr(void); u32 get_my_id(void); +int hold_cores_in_reset(int verbose); #define BOOT_ENTRY_ADDR_UPPER 0 #define BOOT_ENTRY_ADDR_LOWER 1 diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index f2833a5df7..e3a71aec5c 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -245,7 +245,8 @@ void init_addr_map(void) } #endif -unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) +unsigned int +setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; @@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) tlb_size = (camsize - 10) / 2; - set_tlb(1, ram_tlb_address, ram_tlb_address, + set_tlb(1, ram_tlb_address, p_addr, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1); size -= 1ULL << camsize; memsize -= 1ULL << camsize; ram_tlb_address += 1UL << camsize; + p_addr += 1UL << camsize; } if (memsize) print_size(memsize, " left unmapped\n"); - - /* - * Confirm that the requested amount of memory was mapped. - */ return memsize_in_meg; } + +unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) +{ + return + setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} #endif /* !CONFIG_NAND_SPL */ diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index c88b1f35b9..85042c5254 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -25,8 +25,7 @@ #endif OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + PHDRS { text PT_LOAD; @@ -38,42 +37,16 @@ SECTIONS /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } .text : { - *(.text) - *(.got1) + *(.text*) } :text _etext = .; PROVIDE (etext = .); .rodata : { - *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } :text - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -81,23 +54,19 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - *(.got) + KEEP(*(.got)) _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS + *(.data*) + *(.sdata*) } _edata = .; PROVIDE (edata = .); @@ -126,7 +95,7 @@ SECTIONS .resetvec RESET_VECTOR_ADDRESS : { - *(.resetvec) + KEEP(*(.resetvec)) } :text = 0xffff . = RESET_VECTOR_ADDRESS + 0x4; @@ -145,9 +114,8 @@ SECTIONS __bss_start = .; .bss (NOLOAD) : { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) + *(.sbss*) + *(.bss*) *(COMMON) } :bss diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk index ca2f8376ed..bce0fb374b 100644 --- a/arch/powerpc/cpu/mpc86xx/config.mk +++ b/arch/powerpc/cpu/mpc86xx/config.mk @@ -25,3 +25,10 @@ PLATFORM_RELFLAGS += -fPIC -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -mstring PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float + +# Enable gc-sections to enable generation of smaller images. +PLATFORM_LDFLAGS += --gc-sections +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections + +# Use default linker script. Board port can override in board/*/config.mk +LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc86xx/u-boot.lds diff --git a/board/sbc8641d/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 4cea3b30f0..4bfcb90641 100644 --- a/board/sbc8641d/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -60,19 +60,14 @@ SECTIONS lib/crc32.o (.text) arch/powerpc/lib/extable.o (.text) lib/zlib.o (.text) - *(.text) - *(.got1) + *(.text*) } _etext = .; PROVIDE (etext = .); .rodata : { - *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -80,23 +75,19 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - *(.got) + KEEP(*(.got)) _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS + *(.data*) + *(.sdata*) } _edata = .; PROVIDE (edata = .); @@ -121,9 +112,8 @@ SECTIONS __bss_start = .; .bss (NOLOAD) : { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) + *(.sbss*) + *(.bss*) *(COMMON) . = ALIGN(4); } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index e82082e74c..3fec100377 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1184,6 +1184,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, unsigned int sr_it; unsigned int zq_en; unsigned int wrlvl_en; + int cs_en = 1; memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); @@ -1250,16 +1251,23 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, * and each controller uses rank interleaving within * itself. Therefore the starting and ending address * on each controller is twice the amount present on - * each controller. + * each controller. If any CS is not included in the + * interleaving, the memory on that CS is not accssible + * and the total memory size is reduced. The CS is also + * disabled. */ unsigned long long ctlr_density = 0; switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { case FSL_DDR_CS0_CS1: case FSL_DDR_CS0_CS1_AND_CS2_CS3: ctlr_density = dimm_params[0].rank_density * 2; + if (i > 1) + cs_en = 0; break; case FSL_DDR_CS2_CS3: ctlr_density = dimm_params[0].rank_density; + if (i > 0) + cs_en = 0; break; case FSL_DDR_CS0_CS1_CS2_CS3: /* @@ -1379,8 +1387,11 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ); debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); - set_csn_config(dimm_number, i, ddr, popts, dimm_params); - set_csn_config_2(i, ddr); + if (cs_en) { + set_csn_config(dimm_number, i, ddr, popts, dimm_params); + set_csn_config_2(i, ddr); + } else + printf("CS%d is disabled.\n", i); } set_ddr_eor(ddr, popts); diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 88c47d1aed..54e60bb1ae 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -27,6 +27,7 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/mp.h> +#include <asm/fsl_enet.h> #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -215,3 +216,26 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev) fdt_del_node_and_alias(blob, "crypto"); } #endif + +int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) +{ + static const char *fsl_phy_enet_if_str[] = { + [MII] = "mii", + [RMII] = "rmii", + [GMII] = "gmii", + [RGMII] = "rgmii", + [RGMII_ID] = "rgmii-id", + [RGMII_RXID] = "rgmii-rxid", + [SGMII] = "sgmii", + [TBI] = "tbi", + [RTBI] = "rtbi", + [XAUI] = "xgmii", + [FSL_ETH_IF_NONE] = "", + }; + + if (phyc > ARRAY_SIZE(fsl_phy_enet_if_str)) + return fdt_setprop_string(blob, offset, "phy-connection-type", ""); + + return fdt_setprop_string(blob, offset, "phy-connection-type", + fsl_phy_enet_if_str[phyc]); +} diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c index 186936f23e..53236a36f8 100644 --- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c +++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c @@ -138,7 +138,10 @@ static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | - (1 << 7) | (1 << 0xe) | (1 << 0xf), + (1 << 7) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .cfg = (1 << 3) | (1 << 0xe) | (1 << 0xf), }, }; #elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index d576eb85e3..17d4b319bc 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -213,4 +213,10 @@ typedef struct memctl_options_s { } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); + +typedef struct fixed_ddr_parm{ + int min_freq; + int max_freq; + fsl_ddr_cfg_regs_t *ddr_settings; +} fixed_ddr_parm_t; #endif diff --git a/arch/powerpc/include/asm/fsl_enet.h b/arch/powerpc/include/asm/fsl_enet.h new file mode 100644 index 0000000000..4fb2857f3e --- /dev/null +++ b/arch/powerpc/include/asm/fsl_enet.h @@ -0,0 +1,33 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __ASM_PPC_FSL_ENET_H +#define __ASM_PPC_FSL_ENET_H + +enum fsl_phy_enet_if { + MII, + RMII, + GMII, + RGMII, + RGMII_ID, + RGMII_RXID, + RGMII_TXID, + SGMII, + TBI, + RTBI, + XAUI, + FSL_ETH_IF_NONE, +}; + +int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc); + +#endif /* __ASM_PPC_FSL_ENET_H */ diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 8aa725523a..7a56fa2ce3 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o -COBJS-$(CONFIG_DDR_SPD) += ddr.o +COBJS-y += ddr.o +COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 48d95d6a63..68c63ac027 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -29,7 +29,6 @@ #include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/fsl_law.h> -#include <asm/fsl_ddr_sdram.h> #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> @@ -196,20 +195,6 @@ int misc_init_r(void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - - setup_ddr_tlbs(dram_size / 0x100000); - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_MP void board_lmb_reserve(struct lmb *lmb) { diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 18adf2f9c5..2ee018868b 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -8,9 +8,103 @@ #include <common.h> #include <i2c.h> - +#include <hwconfig.h> +#include <asm/mmu.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); + + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +extern fixed_ddr_parm_t fixed_ddr_parm_0[]; +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) +extern fixed_ddr_parm_t fixed_ddr_parm_1[]; +#endif + +phys_size_t fixed_sdram(void) +{ + int i; + sys_info_t sysinfo; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + unsigned int lawbar1_target_id; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) && + (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_1[i].ddr_settings, + sizeof(ddr_cfg_regs)); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); +#endif + + /* + * setup laws for DDR. If not interleaving, presuming half memory on + * DDR1 and the other half on DDR2 + */ + if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + LAW_TRGT_IF_DDR_INTRLV) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } else { +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) + /* We require both controllers have identical DIMMs */ + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + lawbar1_target_id = LAW_TRGT_IF_DDR_2; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } +#else + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } +#endif + } + return ddr_size; +} static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) { @@ -190,3 +284,38 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Enable ZQ calibration */ popts->zq_en = 1; } + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + int use_spd = 0; + + puts("Initializing...."); + +#ifdef CONFIG_DDR_SPD + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ + if (hwconfig_sub("fsl_ddr", "sdram")) { + if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) + use_spd = 1; + else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) + use_spd = 0; + else + use_spd = 1; + } else + use_spd = 1; +#endif + + if (use_spd) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("using fixed parameters\n"); + dram_size = fixed_sdram(); + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c new file mode 100644 index 0000000000..4ad89ff48a --- /dev/null +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -0,0 +1,356 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> + +#define DATARATE_800MHZ 800000000 +#define DATARATE_900MHZ 900000000 +#define DATARATE_1000MHZ 1000000000 +#define DATARATE_1200MHZ 1200000000 +#define DATARATE_1300MHZ 1300000000 + +#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 +#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 +#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 +#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 +#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 +#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 +#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 +#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF +#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 +#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 +#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 +#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce +#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 +#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 +#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 +#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 +#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = { + .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800}, + {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900}, + {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000}, + {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200}, + {0, 0, NULL} +}; + +fixed_ddr_parm_t fixed_ddr_parm_1[] = { + {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd}, + {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd}, + {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd}, + {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd}, + {0, 0, NULL} +}; diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 59ada9ca75..0babd2648a 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2010 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -22,6 +22,7 @@ #include <spd_sdram.h> #include <asm/mmu.h> #include <asm/io.h> +#include <asm/fsl_enet.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -396,10 +397,8 @@ void ft_board_setup(void *blob, bd_t *bd) prop = fdt_getprop(blob, path, "phy-connection-type", 0); if (prop && (strcmp(prop, "rgmii-id") == 0)) - fdt_setprop(blob, path, - "phy-connection-type", - "rgmii-rxid", - sizeof("rgmii-rxid")); + fdt_fixup_phy_connection(blob, path, + RGMII_RXID); } #endif #if defined(CONFIG_HAS_ETH1) @@ -410,10 +409,8 @@ void ft_board_setup(void *blob, bd_t *bd) prop = fdt_getprop(blob, path, "phy-connection-type", 0); if (prop && (strcmp(prop, "rgmii-id") == 0)) - fdt_setprop(blob, path, - "phy-connection-type", - "rgmii-rxid", - sizeof("rgmii-rxid")); + fdt_fixup_phy_connection(blob, path, + RGMII_RXID); } #endif } diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 32a87adb9e..51dd692c2e 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2007,2010 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * CREDITS: Kim Phillips contribute to LIBFDT code @@ -15,6 +15,7 @@ #include <i2c.h> #include <asm/io.h> #include <asm/fsl_mpc83xx_serdes.h> +#include <asm/fsl_enet.h> #include <spd_sdram.h> #include <tsec.h> #include <libfdt.h> @@ -136,7 +137,6 @@ int board_eth_init(bd_t *bd) static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias, int phy_addr) { - const char *phy_type = "sgmii"; const u32 *ph; int off; int err; @@ -148,8 +148,8 @@ static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias, return; } - err = fdt_setprop(blob, off, "phy-connection-type", phy_type, - strlen(phy_type) + 1); + err = fdt_fixup_phy_connection(blob, off, SGMII); + if (err) { printf("WARNING: could not set phy-connection-type for %s: " "%s.\n", alias, fdt_strerror(err)); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 795e5654e8..743e712b84 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -622,8 +622,8 @@ void ft_board_setup(void *blob, bd_t *bd) break; } - err = fdt_setprop_string(blob, nodeoff, "phy-connection-type", - "rmii"); + err = fdt_fixup_phy_connection(blob, nodeoff, RMII); + if (err < 0) { printf("WARNING: could not set phy-connection-type " "%s.\n", fdt_strerror(err)); diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds deleted file mode 100644 index 9c98b2a3cf..0000000000 --- a/board/freescale/mpc8610hpcd/u-boot.lds +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - - /* Read-only sections, merged into text segment: */ - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc86xx/start.o (.text) - arch/powerpc/cpu/mpc86xx/traps.o (.text) - arch/powerpc/cpu/mpc86xx/interrupts.o (.text) - arch/powerpc/cpu/mpc86xx/cpu_init.o (.text) - arch/powerpc/cpu/mpc86xx/cpu.o (.text) - arch/powerpc/cpu/mpc86xx/speed.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index fee310a67f..092ead6653 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -142,56 +142,26 @@ int first_free_busno = 0; void pci_init_board(void) { + struct fsl_pci_info pci_info[2]; + int pcie_ep; + int num = 0; + #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - struct pci_region *r = hose->regions; volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; + uint devdisr = in_be32(&gur->devdisr); uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) - >> MPC8641_PORBMSR_HA_SHIFT; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - debug("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); /* * Activate ULI1575 legacy chip by performing a fake @@ -201,45 +171,22 @@ void pci_init_board(void) + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); } else { - puts("PCI-EXPRESS 1: Disabled\n"); + puts(" PCIE1: disabled\n"); } -} #else - puts("PCI-EXPRESS1: Disabled\n"); + puts(" PCIE1: disabled\n"); #endif /* CONFIG_PCIE1 */ #ifdef CONFIG_PCIE2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - struct pci_region *r = hose->regions; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); -} + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); #else - puts("PCI-EXPRESS 2: Disabled\n"); + puts(" PCIE2: disabled\n"); #endif /* CONFIG_PCIE2 */ } diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds deleted file mode 100644 index 5bf0f2d46b..0000000000 --- a/board/freescale/mpc8641hpcn/u-boot.lds +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright 2006, 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - - /* Read-only sections, merged into text segment: */ - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc86xx/start.o (.text) - arch/powerpc/cpu/mpc86xx/traps.o (.text) - arch/powerpc/cpu/mpc86xx/interrupts.o (.text) - arch/powerpc/cpu/mpc86xx/cpu_init.o (.text) - arch/powerpc/cpu/mpc86xx/cpu.o (.text) - arch/powerpc/cpu/mpc86xx/speed.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - drivers/bios_emulator/atibios.o (.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 54b2d0b166..d954d2f6f7 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -206,100 +206,45 @@ int first_free_busno = 0; void pci_init_board(void) { + struct fsl_pci_info pci_info[2]; volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; + uint devdisr = in_be32(&gur->devdisr); uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; + int pcie_ep; + int num = 0; #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - struct pci_region *r = hose->regions; -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) - >> MPC8641_PORBMSR_HA_SHIFT; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - debug("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - puts("PCI-EXPRESS 1: Disabled\n"); + puts(" PCIE1: disabled\n"); } -} #else - puts("PCI-EXPRESS1: Disabled\n"); + puts(" PCIE1: disabled\n"); #endif /* CONFIG_PCIE1 */ #ifdef CONFIG_PCIE2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - struct pci_region *r = hose->regions; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); -} + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); #else - puts("PCI-EXPRESS 2: Disabled\n"); + puts(" PCIE2: disabled\n"); #endif /* CONFIG_PCIE2 */ - } diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index 7e9a2c7494..e684ba2c2a 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -71,7 +71,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #ifdef CONFIG_PCIE1 - SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), #else /* !CONFIG_PCIE1 */ SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), #endif /* CONFIG_PCIE1 */ @@ -79,7 +79,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ #ifdef CONFIG_PCIE1 - SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), #endif /* CONFIG_PCIE */ }; diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 71fe3ab496..75dd348aa5 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M PCI express MEM First half */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 256M Non-cacheable, guarded * 0xd0000000 256M PCI express MEM Second half */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000, - CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000, + CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), #else /* !CONFIG_PCIE */ @@ -155,7 +155,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 9: 16M Non-cacheable, guarded * 0xef000000 16M PCI express IO */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif /* CONFIG_PCIE */ @@ -205,7 +205,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 256M Non-cacheable, guarded * 0xc0000000 256M PCI express MEM First half */ - SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), #else /* !CONFIG_PCIE */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index dda2cb6ed1..2c3885f23c 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -38,6 +38,7 @@ #include <asm/immap_85xx.h> #include <asm/fsl_pci.h> #include <asm/io.h> +#include <linux/compiler.h> #include <ioports.h> #include <flash.h> #include <libfdt.h> @@ -534,7 +535,6 @@ void local_bus_init (void) /* * Initialize PCI Devices, report devices found. */ -static int first_free_busno; #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; @@ -544,144 +544,77 @@ static struct pci_controller pci1_hose; static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -static inline void init_pci1(void) +void pci_init_board (void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_PCI1 - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - - /* PORDEVSR[15] */ - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; - /* PORDEVSR[14] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - /* PORPLLSR[16] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + struct fsl_pci_info pci_info[2]; + int first_free_busno = 0; + int num = 0; + int pcie_ep; + __maybe_unused int pcie_configured; - int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + u32 pordevsr = in_be32(&gur->pordevsr); + __maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; +#ifdef CONFIG_PCI1 + uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ + uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD; - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333333) ? "33" : (pci_speed == 66666666) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", + pcie_ep ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter"); - - /* outbound memory */ - pci_set_region (r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region (r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - printf (" PCI on bus %02x..%02x\n", - hose->first_busno, hose->last_busno); - - first_free_busno = hose->last_busno + 1; + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { + if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) { ushort reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - uint dev = PCI_BDF(hose->first_busno, 0, 0); + uint dev = PCI_BDF(0, 0, 0); /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) puts ("PCI-X will only work at 66 MHz\n"); - pci_hose_write_config_word (hose, dev, PCIX_COMMAND, - reg16); + pci_write_config_word(dev, PCIX_COMMAND, reg16); } #endif } else { - puts ("PCI1: disabled\n"); + printf(" PCI1: disabled\n"); } -#else /* !CONFIG_PCI1 */ - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ -#endif /* CONFIG_PCI1 */ -} +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); +#endif -static inline void init_pcie1(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCIE1 - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep; - struct pci_region *r = hose->regions; - - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("PCIe: %s, base address %x", - pcie_ep ? "Endpoint" : "Root complex", (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (", with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - puts ("\n"); - - /* outbound memory */ - pci_set_region (r++, - CONFIG_SYS_PCIE1_MEM_BASE, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region (r++, - CONFIG_SYS_PCIE1_IO_BASE, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf (" PCIe on bus %02x..%02x\n", - hose->first_busno, hose->last_busno); - - first_free_busno = hose->last_busno + 1; - + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected as %s\n", + pcie_ep ? "Endpoint" : "Root Complex"); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf ("PCIe: disabled\n"); + printf(" PCIE1: disabled\n"); } -#else /* !CONFIG_PCIE1 */ - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); #endif /* CONFIG_PCIE1 */ } -void pci_init_board (void) -{ - init_pci1(); - init_pcie1(); -} - #ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup (void *blob, bd_t *bd) { diff --git a/board/xes/xpedite5170/u-boot.lds b/board/xes/xpedite5170/u-boot.lds deleted file mode 100644 index 4cea3b30f0..0000000000 --- a/board/xes/xpedite5170/u-boot.lds +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2006, 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - - /* Read-only sections, merged into text segment: */ - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc86xx/start.o (.text) - arch/powerpc/cpu/mpc86xx/traps.o (.text) - arch/powerpc/cpu/mpc86xx/interrupts.o (.text) - arch/powerpc/cpu/mpc86xx/cpu_init.o (.text) - arch/powerpc/cpu/mpc86xx/cpu.o (.text) - arch/powerpc/cpu/mpc86xx/speed.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/common/image.c b/common/image.c index 385464d3eb..89c10b8596 100644 --- a/common/image.c +++ b/common/image.c @@ -1176,8 +1176,10 @@ static int fit_check_fdt (const void *fit, int fdt_noffset, int verify) * @of_flat_tree: pointer to a char* variable, will hold fdt start address * @of_size: pointer to a ulong variable, will hold fdt length * - * boot_relocate_fdt() determines if the of_flat_tree address is within - * the bootmap and if not relocates it into that region + * boot_relocate_fdt() allocates a region of memory within the bootmap and + * relocates the of_flat_tree into that region, even if the fdt is already in + * the bootmap. It also expands the size of the fdt by CONFIG_SYS_FDT_PAD + * bytes. * * of_flat_tree and of_size are set to final (after relocation) values * @@ -1189,9 +1191,10 @@ static int fit_check_fdt (const void *fit, int fdt_noffset, int verify) int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, char **of_flat_tree, ulong *of_size) { - char *fdt_blob = *of_flat_tree; - ulong relocate = 0; + void *fdt_blob = *of_flat_tree; + void *of_start = 0; ulong of_len = 0; + int err; /* nothing to do */ if (*of_size == 0) @@ -1202,62 +1205,32 @@ int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, goto error; } -#ifndef CONFIG_SYS_NO_FLASH - /* move the blob if it is in flash (set relocate) */ - if (addr2info ((ulong)fdt_blob) != NULL) - relocate = 1; -#endif - - /* - * The blob needs to be inside the boot mapping. - */ - if (fdt_blob < (char *)bootmap_base) - relocate = 1; - - if ((fdt_blob + *of_size + CONFIG_SYS_FDT_PAD) >= - ((char *)CONFIG_SYS_BOOTMAPSZ + bootmap_base)) - relocate = 1; - - /* move flattend device tree if needed */ - if (relocate) { - int err; - ulong of_start = 0; - - /* position on a 4K boundary before the alloc_current */ - /* Pad the FDT by a specified amount */ - of_len = *of_size + CONFIG_SYS_FDT_PAD; - of_start = (unsigned long)lmb_alloc_base(lmb, of_len, 0x1000, - (CONFIG_SYS_BOOTMAPSZ + bootmap_base)); - - if (of_start == 0) { - puts("device tree - allocation error\n"); - goto error; - } + /* position on a 4K boundary before the alloc_current */ + /* Pad the FDT by a specified amount */ + of_len = *of_size + CONFIG_SYS_FDT_PAD; + of_start = (void *)(unsigned long)lmb_alloc_base(lmb, of_len, 0x1000, + (CONFIG_SYS_BOOTMAPSZ + bootmap_base)); - debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", - (ulong)fdt_blob, (ulong)fdt_blob + *of_size - 1, - of_len, of_len); - - printf (" Loading Device Tree to %08lx, end %08lx ... ", - of_start, of_start + of_len - 1); + if (of_start == 0) { + puts("device tree - allocation error\n"); + goto error; + } - err = fdt_open_into (fdt_blob, (void *)of_start, of_len); - if (err != 0) { - fdt_error ("fdt move failed"); - goto error; - } - puts ("OK\n"); + debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n", + fdt_blob, fdt_blob + *of_size - 1, of_len, of_len); - *of_flat_tree = (char *)of_start; - *of_size = of_len; - } else { - *of_flat_tree = fdt_blob; - of_len = *of_size + CONFIG_SYS_FDT_PAD; - lmb_reserve(lmb, (ulong)fdt_blob, of_len); - fdt_set_totalsize(*of_flat_tree, of_len); + printf (" Loading Device Tree to %p, end %p ... ", + of_start, of_start + of_len - 1); - *of_size = of_len; + err = fdt_open_into (fdt_blob, of_start, of_len); + if (err != 0) { + fdt_error ("fdt move failed"); + goto error; } + puts ("OK\n"); + + *of_flat_tree = of_start; + *of_size = of_len; set_working_fdt_addr(*of_flat_tree); return 0; diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index e108a0d50c..1657ef6170 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -78,6 +78,20 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig. Syntax is: hwconfig=fsl_ddr:addr_hash=true + +Memory testing options for mpc85xx +================================== +1. Memory test can be done once U-boot prompt comes up using mtest, or +2. Memory test can be done with Power-On-Self-Test function, activated at + compile time. + + In order to enable the POST memory test, CONFIG_POST needs to be + defined in board configuraiton header file. By default, POST memory test + performs a fast test. A slow test can be enabled by changing the flag at + compiling time. To test memory bigger than 2GB, 36BIT support is needed. + Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB + window to physical address so that all physical memory can be tested. + Combination of hwconfig ======================= Hwconfig can be combined with multiple parameters, for example, on a supported diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 56eee7bee6..d626d68cb0 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright 2007, 2010 Freescale Semiconductor, Inc. * * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007 * @@ -311,7 +311,8 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis) i)); /* Set Node address */ - if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) + if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) || + ((db->srom[0] == 0x00) && (db->srom[1] == 0x00))) /* SROM absent, so write MAC address to ID Table */ set_mac_addr(dev); else { /*Exist SROM*/ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 48033d750c..282ab23751 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * @@ -324,9 +324,9 @@ static int uec_set_mac_duplex(uec_private_t *uec, int duplex) } static int uec_set_mac_if_mode(uec_private_t *uec, - enet_interface_type_e if_mode, int speed) + enum fsl_phy_enet_if if_mode, int speed) { - enet_interface_type_e enet_if_mode; + enum fsl_phy_enet_if enet_if_mode; uec_info_t *uec_info; uec_t *uec_regs; u32 upsmr; @@ -521,7 +521,7 @@ static void adjust_link(struct eth_device *dev) struct uec_mii_info *mii_info = uec->mii_info; extern void change_phy_interface_mode(struct eth_device *dev, - enet_interface_type_e mode, int speed); + enum fsl_phy_enet_if mode, int speed); uec_regs = uec->uec_regs; if (mii_info->link) { @@ -539,7 +539,7 @@ static void adjust_link(struct eth_device *dev) } if (mii_info->speed != uec->oldspeed) { - enet_interface_type_e mode = \ + enum fsl_phy_enet_if mode = \ uec->uec_info->enet_interface_type; if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { switch (mii_info->speed) { diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 2a9e2dcd9c..94eb9a26d7 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * based on source code of Shlomi Gridish @@ -25,6 +25,7 @@ #include "qe.h" #include "uccf.h" +#include <asm/fsl_enet.h> #define MAX_TX_THREADS 8 #define MAX_RX_THREADS 8 @@ -660,21 +661,6 @@ typedef enum uec_num_of_threads { UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ } uec_num_of_threads_e; -/* UEC ethernet interface type -*/ -typedef enum enet_interface_type { - MII, - RMII, - RGMII, - GMII, - RGMII_ID, - RGMII_RXID, - RGMII_TXID, - TBI, - RTBI, - SGMII -} enet_interface_type_e; - /* UEC initialization info struct */ #define STD_UEC_INFO(num) \ @@ -705,7 +691,7 @@ typedef struct uec_info { u16 rx_bd_ring_len; u16 tx_bd_ring_len; u8 phy_address; - enet_interface_type_e enet_interface_type; + enum fsl_phy_enet_if enet_interface_type; int speed; } uec_info_t; diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 9be784e6ad..35f2368a80 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2005 Freescale Semiconductor, Inc. + * Copyright (C) 2005,2010 Freescale Semiconductor, Inc. * * Author: Shlomi Gridish * @@ -485,7 +485,7 @@ static int marvell_init(struct uec_mii_info *mii_info) { struct eth_device *edev = mii_info->dev; uec_private_t *uec = edev->priv; - enum enet_interface_type iface = uec->uec_info->enet_interface_type; + enum fsl_phy_enet_if iface = uec->uec_info->enet_interface_type; int speed = uec->uec_info->speed; if ((speed == 1000) && @@ -853,7 +853,7 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) } void marvell_phy_interface_mode (struct eth_device *dev, - enet_interface_type_e type, + enum fsl_phy_enet_if type, int speed ) { @@ -907,7 +907,7 @@ void marvell_phy_interface_mode (struct eth_device *dev, } void change_phy_interface_mode (struct eth_device *dev, - enet_interface_type_e type, int speed) + enum fsl_phy_enet_if type, int speed) { #ifdef CONFIG_PHY_MODE_NEED_CHANGE marvell_phy_interface_mode (dev, type, speed); diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index e7cdb92fb0..8c7d5287c8 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -77,8 +77,9 @@ #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 59655b1c6f..d5c116f5b8 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -380,11 +380,11 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000) -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000) +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ #ifdef CONFIG_PCIE1 @@ -393,16 +393,16 @@ * Addresses are mapped 1-1. */ #ifdef CONFIG_TQM_BIGFLASH -#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000 #else /* !CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000 #endif /* CONFIG_TQM_BIGFLASH */ -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ #endif /* CONFIG_PCIE1 */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c021d82611..85147d0021 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -86,6 +86,7 @@ #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ #endif +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST @@ -129,68 +130,10 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 -#ifdef CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 -#else -#define CONFIG_SYS_SDRAM_SIZE 4096 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x01031000 -#define CONFIG_SYS_DDR_TIMING_0 0x55440804 -#define CONFIG_SYS_DDR_TIMING_1 0x74713a66 -#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b -#define CONFIG_SYS_DDR_MODE_1 0x00421850 -#define CONFIG_SYS_DDR_MODE_2 0x00100000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x10400100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03401500 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 -#define CONFIG_SYS_DDR_CONTROL 0xc7048000 -#define CONFIG_SYS_DDR_CONTROL2 0x24400011 -#define CONFIG_SYS_DDR_CDR1 0x00000000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 -#define CONFIG_SYS_DDR_DEBUG_18 0x40100400 - -#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff -#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG -#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG -#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 -#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 -#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 -#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 -#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 -#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 -#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL -#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL -#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT -#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL -#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 -#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 -#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL -#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL -#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL -#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 -#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 -#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 -#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN -#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS -#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE -#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 - -#endif +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * Local Bus Definitions diff --git a/include/post.h b/include/post.h index 625da5593f..daa9047118 100644 --- a/include/post.h +++ b/include/post.h @@ -57,8 +57,8 @@ #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) #elif defined (CONFIG_MPC85xx) -#include <asm/cpm_85xx.h> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) +#include <asm/immap_85xx.h> +#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr)) #elif defined (CONFIG_4xx) #define _POST_WORD_ADDR \ |