diff options
| -rw-r--r-- | board/amcc/acadia/acadia.c | 55 | ||||
| -rw-r--r-- | board/amcc/acadia/config.mk | 11 | ||||
| -rw-r--r-- | board/amcc/acadia/cpr.c | 40 | ||||
| -rw-r--r-- | board/amcc/acadia/flash.c | 1108 | ||||
| -rw-r--r-- | board/amcc/acadia/memory.c | 555 | ||||
| -rw-r--r-- | board/amcc/acadia/u-boot.lds | 13 | ||||
| -rw-r--r-- | board/amcc/bamboo/bamboo.c | 1 | ||||
| -rw-r--r-- | board/amcc/bamboo/bamboo.h | 10 | ||||
| -rw-r--r-- | board/amcc/katmai/katmai.c | 1 | ||||
| -rw-r--r-- | board/amcc/sequoia/sequoia.c | 4 | ||||
| -rw-r--r-- | common/serial.c | 4 | ||||
| -rw-r--r-- | cpu/ppc4xx/Makefile | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 115 | ||||
| -rw-r--r-- | cpu/ppc4xx/gpio.c | 214 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 51 | ||||
| -rw-r--r-- | include/asm-ppc/gpio.h | 56 | ||||
| -rw-r--r-- | include/configs/acadia.h | 300 | ||||
| -rw-r--r-- | include/configs/sequoia.h | 15 | ||||
| -rw-r--r-- | include/ppc440.h | 23 | ||||
| -rw-r--r-- | include/serial.h | 2 |
20 files changed, 511 insertions, 2069 deletions
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index c8aaad2d78..7d0046a22f 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -26,9 +26,6 @@ extern void board_pll_init_f(void); -/* Some specific Acadia Defines */ -#define CPLD_BASE 0x80000000 - void liveoak_gpio_init(void) { /* @@ -54,62 +51,12 @@ void liveoak_gpio_init(void) out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */ } -#if 0 /* test-only: not called at all??? */ -void ext_bus_cntlr_init(void) -{ -#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, EBC_PB4AP); - mtebc(pb4cr, EBC_PB4CR); -#endif -} -#endif - int board_early_init_f(void) { unsigned int reg; -#if 0 /* test-only */ - /* - * If CRAM memory and SPI/NAND boot, and if the CRAM memory is - * already initialized by the pre-loader then we can't reinitialize - * CPR registers, GPIO registers and EBC registers as this will - * have the effect of un-initializing CRAM. - */ - spr_reg = (volatile unsigned long) mfspr(SPRG7); - if (spr_reg != LOAK_CRAM) { /* != CRAM */ - board_pll_init_f(); - liveoak_gpio_init(); - ext_bus_cntlr_init(); - - mtebc(pb1ap, CFG_EBC_PB1AP); - mtebc(pb1cr, CFG_EBC_PB1CR); - - mtebc(pb2ap, CFG_EBC_PB2AP); - mtebc(pb2cr, CFG_EBC_PB2CR); - } -#else board_pll_init_f(); liveoak_gpio_init(); -/* ext_bus_cntlr_init(); */ -#endif - -#if 0 /* test-only (orig) */ - /* - * If we boot from NAND Flash, we are running in - * RAM, so disable the EBC_CS0 so that it goes back - * to the NOR Flash. It will be enabled later - * for the NAND Flash on EBC_CS1 - */ - mfsdr(sdrultra0, reg); - mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); -#endif -#if 0 /* test-only */ - /* configure for NAND */ - mfsdr(sdrultra0, reg); - reg &= ~SDR_ULTRA0_CSN_MASK; - reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS; - mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); -#endif /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); @@ -128,7 +75,7 @@ int board_early_init_f(void) int misc_init_f(void) { /* Set EPLD to take PHY out of reset */ - out8(CPLD_BASE + 0x05, 0x00); + out8(CFG_CPLD_BASE + 0x05, 0x00); udelay(100000); return 0; diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk index 79b948e46b..1524bad772 100644 --- a/board/amcc/acadia/config.mk +++ b/board/amcc/acadia/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 +# (C) Copyright 2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -27,15 +27,6 @@ ifndef TEXT_BASE TEXT_BASE = 0xFFFC0000 endif -ifeq ($(CONFIG_NAND_U_BOOT),y) -LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds -endif - -ifeq ($(CONFIG_SPI_U_BOOT),y) -LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds -PAD_TO = 0x00840000 -endif - ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG endif diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c index 10d8290e62..9dcce35c89 100644 --- a/board/amcc/acadia/cpr.c +++ b/board/amcc/acadia/cpr.c @@ -76,19 +76,19 @@ void board_pll_init_f(void) * | UART0 | 28.57 | 7 (0x07)| * | UART1 | 28.57 | 7 (0x07)| * | DAC | 28.57 | 7 (0xA7)| - * | ADC | 4 | 50 (0x32)| + * | ADC | 4 | 50 (0x32)| * | PWM | 28.57 | 7 (0x07)| * | EMAC | 4 | 50 (0x32)| * ----------------------------------- */ /* Initialize PLL */ - mtcpr(cprpllc, 0x20000238); - mtcpr(cprplld, 0x03010400); + mtcpr(cprpllc, 0x20000238); + mtcpr(cprplld, 0x03010400); mtcpr(cprprimad, 0x03050a0a); - mtcpr(cprperc0, 0x00000000); - mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0x07323200); + mtcpr(cprperc0, 0x00000000); + mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0x07323200); mtcpr(cprclkupd, 0x40000000); } @@ -117,11 +117,11 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033C); - mtcpr(cprplld, 0x0a010000); + mtcpr(cprpllc, 0x0000033C); + mtcpr(cprplld, 0x0a010000); mtcpr(cprprimad, 0x02040808); - mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xA6A60300); + mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xA6A60300); mtcpr(cprclkupd, 0x40000000); } @@ -143,20 +143,20 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x000003BC); - mtcpr(cprplld, 0x06060600); + mtcpr(cprpllc, 0x000003BC); + mtcpr(cprplld, 0x06060600); mtcpr(cprprimad, 0x02020004); - mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xC8C81600); + mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xC8C81600); mtcpr(cprclkupd, 0x40000000); } -#endif /* CPU_<speed>_405EZ */ +#endif /* CPU_<speed>_405EZ */ #if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) /* * Get timebase clock frequency */ -unsigned long get_tbclk (void) +unsigned long get_tbclk(void) { unsigned long cpr_plld; unsigned long cpr_primad; @@ -184,12 +184,12 @@ unsigned long get_tbclk (void) /* * Determine FBK_DIV. */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; + pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); + if (pllFbkDiv == 0) + pllFbkDiv = 256; freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; return (freqProcessor); } -#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ +#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/acadia/flash.c b/board/amcc/acadia/flash.c deleted file mode 100644 index 39a11f9387..0000000000 --- a/board/amcc/acadia/flash.c +++ /dev/null @@ -1,1108 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <ppc4xx.h> -#include <asm/processor.h> - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 - */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { - {0xffc00001}, /* 0:boot from big flash */ -}; - -/* - * include common flash code (for amcc boards) - */ -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CFG_FLASH_2ND_16BIT_DEV -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_MX: - printf("MIXC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_MXLV320T: - printf ("MXLV320T (32 Mbit, top sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CFG_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) { - return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CFG_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CFG_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -#ifdef CFG_FLASH_2ND_16BIT_DEV - -#undef CFG_FLASH_WORD_SIZE -#define CFG_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - int n; - CFG_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - -#if 0 /* TODO: remove ifdef when Flash responds correctly */ - switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } -#endif /* TODO: remove ifdef when Flash responds correctly */ - - /* - * TODO: Start - * uncomment block above when Flash responds correctly. - * also remove the lines below: - */ - info->flash_id = FLASH_MAN_AMD; - DEBUGF("FLASH MANUFACT: FLASH_MAN_AMD\n"); - /* TODO: End */ - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - -#if 0 /* TODO: remove ifdef when Flash responds correctly */ - switch (value) { - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: - info->flash_id += FLASH_MXLV320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } -#endif /* TODO: remove ifdef when Flash responds correctly */ - - /* - * TODO: Start - * uncomment block above when Flash responds correctly. - * also remove the lines below: - */ - DEBUGF("\nFLASH DEVICEID: FLASH_AM320T\n"); - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; /* => 4 MB */ - /* TODO: End */ - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n=0; n<2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else if ( ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ) { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - else { - if (info->flash_id & FLASH_BTYPE){ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address,(A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -/* - * TODO: FIX: this wait loop sometimes fails: DQ7 indicates the erase command - * never was accepted (i.e. didn't start) - why???? - */ -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last, counter = 0; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - DEBUGF("DQ7_2: start = 0x%08lx\n", start); - last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now); - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - udelay(1000000); /* 1 sec */ - putc('.'); - counter++; - if (counter > 5) { - return -1; - } - DEBUGF("DQ7_2: now = 0x%08lx, last = 0x%08lx\n", now, last); - } - return 0; -} - -static void wr_flash_cmd(ulong sector, ushort addr, CFG_FLASH_WORD_SIZE value) -{ - int fw_size; - - fw_size = sizeof(value); - switch (fw_size) - { - case 1: - out8((ulong)(sector + addr), value); - break; - case 2: - out16((ulong)(sector + (addr << 1)), value); - break; - default: - printf("flash_erase: error incorrect chip programing size.\n"); - } - return; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect, count = 0; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first, count = 0; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - /* - * TODO: fix code - */ - wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00800080); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA); - wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055); - wr_flash_cmd((ulong)addr2, 0, (CFG_FLASH_WORD_SIZE) 0x00300030); - udelay(2000000); /* 2 sec */ - wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0); - -#if 0 - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ -#endif - } - l_sect = sect; - printf(".."); - printf(".."); - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - count++; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - - if (count > 0) { - return 0; - } else { - return 1; - } -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} -#endif /* CFG_FLASH_2ND_16BIT_DEV */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - index = 0; - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 0f1de71c1b..5375d36c9b 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -21,541 +21,80 @@ * MA 02111-1307 USA */ +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + #include <common.h> #include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> -#define CRAM_BANK0_BASE 0x0 -#define CRAM_DIDR 0x00100000 -#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43 -#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343 -#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */ -#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */ -#define CRAM_DEVID_NOT_SUPPORTED 0x00000000 - -#define PSRAM_PASS 0x50415353 /* "PASS" */ -#define PSRAM_FAIL 0x4641494C /* "FAIL" */ - -static u32 is_cram_inited(void); -static u32 is_cram(void); -static long int cram_init(u32); -static void cram_bcr_write(u32); -void udelay (unsigned long); - +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ void sdram_init(void) { - volatile unsigned long spr_reg; - - /* - * If CRAM not initialized or CRAM looks initialized because this - * is after a warm reboot then set SPRG7 to indicate CRAM needs - * initialization. Note that CRAM is initialized by the SPI and - * NAND preloader. - */ - spr_reg = (volatile unsigned long) mfspr(SPRG6); - if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) { - mtspr(SPRG7, LOAK_NONE); /* "NONE" */ - } - -#if 1 - /* - * When running the NAND SPL, the normal EBC configuration is not - * done, so We need to enable EPLD access on EBC_CS_2 and the memory - * on EBC_CS_3 - */ - - /* Enable CPLD - Needed for PSRAM Access */ - - - /* Init SDRAM by setting EBC Bank 3 for PSRAM */ - mtebc(pb1ap, CFG_EBC_PB1AP); - mtebc(pb1cr, CFG_EBC_PB1CR); - - mtebc(pb2ap, CFG_EBC_PB2AP); - mtebc(pb2cr, CFG_EBC_PB2CR); - - /* pre-boot loader code: we are in OCM */ - mtspr(SPRG6, LOAK_SPL); /* "SPL " */ - mtspr(SPRG7, LOAK_OCM); /* "OCM " */ -#endif - return; } static void cram_bcr_write(u32 wr_val) { - u32 tmp_reg; - u32 val; - volatile u32 gpio_reg; - - /* # Program CRAM write */ - - /* - * set CRAM_CRE = 0x1 - * set wr_val = wr_val << 2 - */ - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg | 0x00000400); - wr_val = wr_val << 2; - /* wr_val = 0x1c048; */ - + wr_val <<= 2; - /* - * # stop PLL clock before programming CRAM - * set EPLD0_MUX_CTL.OESPR3 = 1 - * delay 2 - */ + /* set CRAM_CRE to 1 */ + gpio_write_bit(CFG_GPIO_CRAM_CRE, 1); + /* Write BCR to CRAM on CS1 */ + out32(wr_val + 0x00200000, 0); + debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); - /* - * # CS1 - * read 0x00200000 - * #shift 2 bit left before write - * set val = wr_val + 0x00200000 - * write dmem val 0 - * read 0x00200000 val - * print val/8x - */ - tmp_reg = in32(0x00200000); - val = wr_val + 0x00200000; - /* val = 0x0021c048; */ - out32(val, 0x0000); - udelay(100000); - val = in32(0x00200000); + /* Write BCR to CRAM on CS2 */ + out32(wr_val + 0x02200000, 0); + debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); - debug("CRAM VAL: %x for CS1 ", val); + sync(); + eieio(); - /* - * # CS2 - * read 0x02200000 - * #shift 2 bit left before write - * set val = wr_val + 0x02200000 - * write dmem val 0 - * read 0x02200000 val - * print val/8x - */ - tmp_reg = in32(0x02200000); - val = wr_val + 0x02200000; - /* val = 0x0221c048; */ - out32(val, 0x0000); - udelay(100000); - val = in32(0x02200000); + /* set CRAM_CRE back to 0 (normal operation) */ + gpio_write_bit(CFG_GPIO_CRAM_CRE, 0); - debug("CRAM VAL: %x for CS2 ", val); - - /* - * # Start PLL clock before programming CRAM - * set EPLD0_MUX_CTL.OESPR3 = 0 - */ - - - /* - * set CRAMCR = 0x1 - */ - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg | 0x00000400); - - /* - * # read CRAM config BCR ( bit19:18 = 10b ) - * #read 0x00200000 - * # 1001_1001_0001_1111 ( 991f ) => - * #10_0110_0100_0111_1100 => 2647c => 0022647c - * #0011_0010_0011_1110 (323e) - * # - */ - - /* - * set EPLD0_MUX_CTL.CRAMCR = 0x0 - */ - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF); return; } -static u32 is_cram_inited() -{ - volatile unsigned long spr_reg; - - /* - * If CRAM is initialized already, then don't reinitialize it again. - * In the case of NAND boot and SPI boot, CRAM will already be - * initialized by the pre-loader - */ - spr_reg = (volatile unsigned long) mfspr(SPRG7); - if (spr_reg == LOAK_CRAM) { - return 1; - } else { - return 0; - } -} - -/****** - * return 0 if not CRAM - * return 1 if CRAM and it's already inited by preloader - * else return cram_id (CRAM Device Identification Register) - ******/ -static u32 is_cram(void) -{ - u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L; - volatile u32 gpio_reg; - volatile u32 cram_id = 0; - - if (is_cram_inited() == 1) { - /* this is CRAM and it is already inited (by preloader) */ - cram_id = 1; - } else { - /* - * # CRAM CLOCK - * set GPIO0_TCR.G8 = 1 - * set GPIO0_OSRL.G8 = 0 - * set GPIO0_OR.G8 = 0 - */ - gpio_reg = in32(GPIO0_TCR); - gpio_TCR = gpio_reg; - out32(GPIO0_TCR, gpio_reg | 0x00800000); - gpio_reg = in32(GPIO0_OSRL); - gpio_OSRL = gpio_reg; - out32(GPIO0_OSRL, gpio_reg & 0xffffbfff); - gpio_reg = in32(GPIO0_OR); - gpio_OR = gpio_reg; - out32(GPIO0_OR, gpio_reg & 0xff7fffff); - - /* - * # CRAM Addreaa Valid - * set GPIO0_TCR.G10 = 1 - * set GPIO0_OSRL.G10 = 0 - * set GPIO0_OR.G10 = 0 - */ - gpio_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, gpio_reg | 0x00200000); - gpio_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, gpio_reg & 0xfffffbff); - gpio_reg = in32(GPIO0_OR); - out32(GPIO0_OR, gpio_reg & 0xffdfffff); - - /* - * # config input (EBC_WAIT) - * set GPIO0_ISR1L.G9 = 1 - * set GPIO0_TCR.G9 = 0 - */ - gpio_reg = in32(GPIO0_ISR1L); - gpio_ISR1L = gpio_reg; - out32(GPIO0_ISR1L, gpio_reg | 0x00001000); - gpio_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, gpio_reg & 0xffbfffff); - - /* - * Enable CRE to read Registers - * set GPIO0_TCR.21 = 1 - * set GPIO1_OR.21 = 1 - */ - gpio_reg = in32(GPIO1_TCR); - out32(GPIO1_TCR, gpio_reg | 0x00000400); - - gpio_reg = in32(GPIO1_OR); - out32(GPIO1_OR, gpio_reg | 0x00000400); - - - - - /* Read Version ID */ - cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR); - udelay(100000); - - asm volatile(" sync"); - asm volatile(" eieio"); - - debug("Cram ID: %X ", cram_id); - - switch (cram_id) { - case MICRON_MT45W8MW16BGX_CRAM_ID: - case MICRON_MT45W8MW16BGX_CRAM_ID2: - /* supported CRAM vendor/part */ - break; - case CRAM_DEVID_NOT_SUPPORTED: - default: - /* check for DIDR Vendor ID of Micron */ - if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) == - MICRON_DIDR_VENDOR_ID) - { - /* supported CRAM vendor */ - break; - } - /* this is not CRAM or not supported CRAM vendor/part */ - cram_id = 0; - /* - * reset the GPIO registers to the values that were - * there before this routine - */ - out32(GPIO0_TCR, gpio_TCR); - out32(GPIO0_OSRL, gpio_OSRL); - out32(GPIO0_OR, gpio_OR); - out32(GPIO0_ISR1L, gpio_ISR1L); - break; - } - } - - return cram_id; -} - -static long int cram_init(u32 already_inited) -{ - volatile u32 tmp_reg; - u32 cram_wr_val; - - if (already_inited == 0) return 0; - - /* - * If CRAM is initialized already, then don't reinitialize it again. - * In the case of NAND boot and SPI boot, CRAM will already be - * initialized by the pre-loader - */ - if (already_inited != 1) - { - /* - * #o CRAM Card - * # - CRAMCRE @reg16 = 1; for CRAM to use - * # - CRAMCRE @reg16 = 0; for CRAM to program - * - * # enable CRAM SEL, move from setEPLD.cmd - * set EPLD0_MUX_CTL.OECRAM = 0 - * set EPLD0_MUX_CTL.CRAMCR = 1 - * set EPLD0_ETHRSTBOOT.SLCRAM = 0 - * #end - */ - - - /* - * #1. EBC need to program READY, CLK, ADV for ASync mode - * # config output - */ - - /* - * # CRAM CLOCK - * set GPIO0_TCR.G8 = 1 - * set GPIO0_OSRL.G8 = 0 - * set GPIO0_OR.G8 = 0 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00800000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg & 0xffffbfff); - tmp_reg = in32(GPIO0_OR); - out32(GPIO0_OR, tmp_reg & 0xff7fffff); - - /* - * # CRAM Addreaa Valid - * set GPIO0_TCR.G10 = 1 - * set GPIO0_OSRL.G10 = 0 - * set GPIO0_OR.G10 = 0 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00200000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg & 0xfffffbff); - tmp_reg = in32(GPIO0_OR); - out32(GPIO0_OR, tmp_reg & 0xffdfffff); - - /* - * # config input (EBC_WAIT) - * set GPIO0_ISR1L.G9 = 1 - * set GPIO0_TCR.G9 = 0 - */ - tmp_reg = in32(GPIO0_ISR1L); - out32(GPIO0_ISR1L, tmp_reg | 0x00001000); - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg & 0xffbfffff); - - /* - * # config CS4 from GPIO - * set GPIO0_TCR.G0 = 1 - * set GPIO0_OSRL.G0 = 1 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x80000000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg | 0x40000000); - - /* - * #2. EBC in Async mode - * # set EBC0_PB1AP = 0x078f0ec0 - * set EBC0_PB1AP = 0x078f1ec0 - * set EBC0_PB2AP = 0x078f1ec0 - */ - mtebc(pb1ap, 0x078F1EC0); - mtebc(pb2ap, 0x078F1EC0); - - /* - * #set EBC0_PB1CR = 0x000bc000 - * #enable CS2 for CRAM - * set EBC0_PB2CR = 0x020bc000 - */ - mtebc(pb1cr, 0x000BC000); - mtebc(pb2cr, 0x020BC000); - - /* - * #3. set CRAM in Sync mode - * #exec cm_bcr_write.cmd { 0x701f } - * #3. set CRAM in Sync mode (full drv strength) - * exec cm_bcr_write.cmd { 0x701F } - */ - cram_wr_val = 0x7012; /* CRAM burst setting */ - cram_bcr_write(cram_wr_val); - - /* - * #4. EBC in Sync mode - * #set EBC0_PB1AP = 0x9f800fc0 - * #set EBC0_PB1AP = 0x900001c0 - * set EBC0_PB2AP = 0x9C0201c0 - * set EBC0_PB2AP = 0x9C0201c0 - */ - mtebc(pb1ap, 0x9C0201C0); - mtebc(pb2ap, 0x9C0201C0); - - /* - * #5. EBC need to program READY, CLK, ADV for Sync mode - * # config output - * set GPIO0_TCR.G8 = 1 - * set GPIO0_OSRL.G8 = 1 - * set GPIO0_TCR.G10 = 1 - * set GPIO0_OSRL.G10 = 1 - */ - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00800000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg | 0x00004000); - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg | 0x00200000); - tmp_reg = in32(GPIO0_OSRL); - out32(GPIO0_OSRL, tmp_reg | 0x00000400); - - /* - * # config input - * set GPIO0_ISR1L.G9 = 1 - * set GPIO0_TCR.G9 = 0 - */ - tmp_reg = in32(GPIO0_ISR1L); - out32(GPIO0_ISR1L, tmp_reg | 0x00001000); - tmp_reg = in32(GPIO0_TCR); - out32(GPIO0_TCR, tmp_reg & 0xffbfffff); - - /* - * # config EBC to use RDY - * set SDR0_ULTRA0.EBCREN = 1 - */ - mfsdr(sdrultra0, tmp_reg); - mtsdr(sdrultra0, tmp_reg | 0x04000000); - - /* - * set EPLD0_MUX_CTL.OESPR3 = 0 - */ - - - mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */ - } /* if (already_inited != 1) */ - - return (64 * 1024 * 1024); -} - -/****** - * return 0 if not PSRAM - * return 1 if is PSRAM - ******/ -static int is_psram(u32 addr) -{ - u32 test_pattern = 0xdeadbeef; - volatile u32 readback; - - if (addr == CFG_SDRAM_BASE) { - /* This is to temp enable OE for PSRAM */ - out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); - udelay(10000); - } - - out32(addr, test_pattern); - asm volatile(" sync"); - asm volatile(" eieio"); - - readback = (volatile u32) in32(addr); - asm volatile(" sync"); - asm volatile(" eieio"); - if (readback == test_pattern) { - return 1; - } else { - return 0; - } -} - -static long int psram_init(void) +long int initdram(int board_type) { - u32 readback; - long psramsize = 0; - int i; - - /* This is to temp enable OE for PSRAM */ - out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); - udelay(10000); + u32 val; - /* - * PSRAM bank 1: read then write to address 0x00000000 - */ - for (i = 0; i < 100; i++) { - if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) { - readback = PSRAM_PASS; - } else { - readback = PSRAM_FAIL; - break; - } - } - if (readback == PSRAM_PASS) { - debug("psram_init(bank0): pass\n"); - psramsize = (16 * 1024 * 1024); - } else { - debug("psram_init(bank0): fail\n"); - return 0; - } + /* 1. EBC need to program READY, CLK, ADV for ASync mode */ + gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); -#if 0 - /* - * PSRAM bank 1: read then write to address 0x01000000 - */ - for (i = 0; i < 100; i++) { - if (is_psram((1 << 24) + (i*256)) == 1) { - readback = PSRAM_PASS; - } else { - readback = PSRAM_FAIL; - break; - } - } - if (readback == PSRAM_PASS) { - debug("psram_init(bank1): pass\n"); - psramsize = psramsize + (16 * 1024 * 1024); - } -#endif + /* 2. EBC in Async mode */ + mtebc(pb1ap, 0x078F1EC0); + mtebc(pb2ap, 0x078F1EC0); + mtebc(pb1cr, 0x000BC000); + mtebc(pb2cr, 0x020BC000); - mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */ + /* 3. Set CRAM in Sync mode */ + cram_bcr_write(0x7012); /* CRAM burst setting */ - return psramsize; -} + /* 4. EBC in Sync mode */ + mtebc(pb1ap, 0x9C0201C0); + mtebc(pb2ap, 0x9C0201C0); -long int initdram(int board_type) -{ - long int sram_size; - u32 cram_inited; + /* Set GPIO pins back to alternate function */ + gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - /* Determine Attached Memory Expansion Card*/ - cram_inited = is_cram(); - if (cram_inited != 0) { /* CRAM */ - debug("CRAM Expansion Card attached\n"); - sram_size = cram_init(cram_inited); - } else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */ - debug("PSRAM Expansion Card attached\n"); - sram_size = psram_init(); - } else { /* no SRAM */ - debug("No Memory Card Attached!!\n"); - sram_size = 0; - } + /* Config EBC to use RDY */ + mfsdr(sdrultra0, val); + mtsdr(sdrultra0, val | 0x04000000); - return sram_size; + return (CFG_MBYTES_RAM << 20); } int testdram(void) diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds index be030923b8..b08c9994bd 100644 --- a/board/amcc/acadia/u-boot.lds +++ b/board/amcc/acadia/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index c93ba6e3ca..b5bb145808 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/gpio.h> #include <spd_sdram.h> #include <ppc440.h> #include "bamboo.h" diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index 1ce6366da4..447486297a 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -264,19 +264,9 @@ #define TRUE 1 #define FALSE 0 -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ - #define GPIO0 0 #define GPIO1 1 - /*#define MAX_SELECTION_NB CORE_NB */ #define MAX_CORE_SELECT_NB 22 diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index fbf1a98ab3..286bdc1f21 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -27,6 +27,7 @@ #include <asm/processor.h> #include <i2c.h> #include <asm-ppc/io.h> +#include <asm-ppc/gpio.h> #include "../cpu/ppc4xx/440spe_pcie.h" diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index daaffe06d3..930fa71cb9 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -363,8 +363,8 @@ int checkboard(void) printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); #endif - rev = *(u8 *)(CFG_CPLD + 0); - val = *(u8 *)(CFG_CPLD + 5) & 0x01; + rev = *(u8 *)(CFG_BCSR_BASE + 0); + val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { diff --git a/common/serial.c b/common/serial.c index 605d4e34be..13e9f30e41 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,7 @@ struct serial_device *default_serial_console (void) || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) #if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; @@ -91,7 +91,7 @@ void serial_initialize (void) #endif #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) serial_register(&serial0_device); serial_register(&serial1_device); #endif diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 96f0f62eb6..4068b53208 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -29,7 +29,7 @@ START = start.o resetvec.o kgdb.o SOBJS = dcr.o COBJS = 405gp_pci.o 4xx_enet.o \ bedbug_405.o commproc.o \ - cpu.o cpu_init.o i2c.o interrupts.o \ + cpu.o cpu_init.o gpio.o i2c.o interrupts.o \ miiphy.o ndfc.o sdram.o serial.o \ 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \ tlb.o traps.o usb_ohci.o usbdev.o \ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 9d1cd1343d..66e8637260 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -25,6 +25,7 @@ #include <watchdog.h> #include <ppc4xx_enet.h> #include <asm/processor.h> +#include <asm/gpio.h> #include <ppc4xx.h> #if defined(CONFIG_405GP) || defined(CONFIG_405EP) @@ -98,118 +99,6 @@ DECLARE_GLOBAL_DATA_PTR; # endif #endif /* CFG_INIT_DCACHE_CS */ -#if defined(CFG_440_GPIO_TABLE) -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; - -void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX]) -{ - unsigned char i=0, j=0, reg_offset = 0, gpio_core; - unsigned long gpio_reg, gpio_core_add; - - for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) { - j = 0; - reg_offset = 0; - /* GPIO config of the GPIOs 0 to 31 */ - for (i=0; i<GPIO_MAX; i++, j++) { - if (i == GPIO_MAX/2) { - reg_offset = 4; - j = i-16; - } - - gpio_core_add = (*gpio_tab)[gpio_core][i].add; - - if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) || - ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { - - switch ((*gpio_tab)[gpio_core][i].alt_nb) { - case GPIO_SEL: - break; - - case GPIO_ALT1: - gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT2: - gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT3: - gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - - if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) || - ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { - - switch ((*gpio_tab)[gpio_core][i].alt_nb) { - case GPIO_SEL: - if (gpio_core == GPIO0) { - gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j)); - out32(GPIO0_TCR, gpio_reg); - } - - if (gpio_core == GPIO1) { - gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j)); - out32(GPIO1_TCR, gpio_reg); - } - - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT1: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT2: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT3: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) - & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - } - } -} -#endif /* CFG_440_GPIO_TABLE */ - /* * Breath some life into the CPU... * @@ -248,7 +137,7 @@ cpu_init_f (void) #endif /* CONFIG_405EP */ #if defined(CFG_440_GPIO_TABLE) - set_chip_gpio_configuration(&gpio_tab); + gpio_set_chip_configuration(); #endif /* CFG_440_GPIO_TABLE */ /* diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c new file mode 100644 index 0000000000..dd84e58a1f --- /dev/null +++ b/cpu/ppc4xx/gpio.c @@ -0,0 +1,214 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> + +#if defined(CFG_440_GPIO_TABLE) +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; +#endif + +#if defined(GPIO0_OSRL) +/* Only some 4xx variants support alternate funtions on the GPIO's */ +void gpio_config(int pin, int in_out, int gpio_alt, int out_val) +{ + u32 mask; + u32 mask2; + u32 val; + u32 offs = 0; + u32 offs2 = 0; + int pin2 = pin << 1; + + if (pin >= GPIO_MAX) { + offs = 0x100; + pin -= GPIO_MAX; + } + + if (pin >= GPIO_MAX/2) { + offs2 = 0x100; + pin2 = (pin - GPIO_MAX/2) << 1; + } + + mask = 0x80000000 >> pin; + mask2 = 0xc0000000 >> (pin2 << 1); + + /* first set TCR to 0 */ + out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask); + + if (in_out == GPIO_OUT) { + val = in32(GPIO0_OSRL + offs + offs2) & ~mask2; + switch (gpio_alt) { + case GPIO_ALT1: + val |= GPIO_ALT1_SEL >> pin2; + break; + case GPIO_ALT2: + val |= GPIO_ALT2_SEL >> pin2; + break; + case GPIO_ALT3: + val |= GPIO_ALT3_SEL >> pin2; + break; + } + out32(GPIO0_OSRL + offs + offs2, val); + + /* setup requested output value */ + if (out_val == GPIO_OUT_0) + out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask); + else if (out_val == GPIO_OUT_1) + out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask); + + /* now configure TCR to drive output if selected */ + out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask); + } else { + val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2; + val |= GPIO_IN_SEL >> pin2; + out32(GPIO0_ISR1L + offs + offs2, val); + } +} +#endif /* GPIO_OSRL */ + +void gpio_write_bit(int pin, int val) +{ + u32 offs = 0; + + if (pin >= GPIO_MAX) { + offs = 0x100; + pin -= GPIO_MAX; + } + + if (val) + out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin)); + else + out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin)); +} + +#if defined(CFG_440_GPIO_TABLE) +void gpio_set_chip_configuration(void) +{ + unsigned char i=0, j=0, offs=0, gpio_core; + unsigned long reg, core_add; + + for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) { + j = 0; + offs = 0; + /* GPIO config of the GPIOs 0 to 31 */ + for (i=0; i<GPIO_MAX; i++, j++) { + if (i == GPIO_MAX/2) { + offs = 4; + j = i-16; + } + + core_add = gpio_tab[gpio_core][i].add; + + if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) || + (gpio_tab[gpio_core][i].in_out == GPIO_BI)) { + + switch (gpio_tab[gpio_core][i].alt_nb) { + case GPIO_SEL: + break; + + case GPIO_ALT1: + reg = in32(GPIO_IS1(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS1(core_add+offs), reg); + break; + + case GPIO_ALT2: + reg = in32(GPIO_IS2(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS2(core_add+offs), reg); + break; + + case GPIO_ALT3: + reg = in32(GPIO_IS3(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS3(core_add+offs), reg); + break; + } + } + + if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) || + (gpio_tab[gpio_core][i].in_out == GPIO_BI)) { + + switch (gpio_tab[gpio_core][i].alt_nb) { + case GPIO_SEL: + if (gpio_core == GPIO0) { + reg = in32(GPIO0_TCR) | (0x80000000 >> (j)); + out32(GPIO0_TCR, reg); + } + + if (gpio_core == GPIO1) { + reg = in32(GPIO1_TCR) | (0x80000000 >> (j)); + out32(GPIO1_TCR, reg); + } + + reg = in32(GPIO_OS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + out32(GPIO_OS(core_add+offs), reg); + reg = in32(GPIO_TS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + out32(GPIO_TS(core_add+offs), reg); + break; + + case GPIO_ALT1: + reg = in32(GPIO_OS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_OS(core_add+offs), reg); + reg = in32(GPIO_TS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_TS(core_add+offs), reg); + break; + + case GPIO_ALT2: + reg = in32(GPIO_OS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_OS(core_add+offs), reg); + reg = in32(GPIO_TS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_TS(core_add+offs), reg); + break; + + case GPIO_ALT3: + reg = in32(GPIO_OS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_OS(core_add+offs), reg); + reg = in32(GPIO_TS(core_add+offs)) + & ~(GPIO_MASK >> (j*2)); + reg = reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_TS(core_add+offs), reg); + break; + } + } + } + } +} +#endif /* CFG_440_GPIO_TABLE */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index d918b3ec1f..3b1586c0ae 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -2,6 +2,7 @@ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> + * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. @@ -757,7 +758,6 @@ _start: #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) -/* test-only... (clean up later when NAND booting is supported) */ #if defined(CONFIG_405EZ) /******************************************************************** * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 @@ -786,41 +786,7 @@ _start: mtdcr ocmdsisdpc,r4 isync - -#if defined(CONFIG_NAND_SPL) - /* - * 405EZ can boot from NAND Flash. - * If we are booting the SPL (Pre-loader), copy code from - * the mapped 4K NAND Flash to the OCM - */ - li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 - mtctr r4 - lis r2,CFG_NAND_BOOT_SPL_SRC@h - ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l -spl_loop: - lwzu r4,4(r2) - stwu r4,4(r3) - bdnz spl_loop - - /* - * Jump to code in OCM Ram - */ - bl 00f -00: mflr r10 - lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h - ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l - sub r10,r10,r3 - addi r10,r10,28 - mtlr r10 - blr -start_ram: - sync - isync -#endif -#else -/* ...test-only */ +#else /* CONFIG_405EZ */ /******************************************************************** * Setup OCM - On Chip Memory *******************************************************************/ @@ -828,14 +794,15 @@ start_ram: lis r0, 0x7FFF ori r0, r0, 0xFFFF mfdcr r3, ocmiscntl /* get instr-side IRAM config */ - mfdcr r4, ocmdscntl /* get data-side IRAM config */ - and r3, r3, r0 /* disable data-side IRAM */ - and r4, r4, r0 /* disable data-side IRAM */ - mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ - mtdcr ocmdscntl, r4 /* set data-side IRAM config */ + mfdcr r4, ocmdscntl /* get data-side IRAM config */ + and r3, r3, r0 /* disable data-side IRAM */ + and r4, r4, r0 /* disable data-side IRAM */ + mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ + mtdcr ocmdscntl, r4 /* set data-side IRAM config */ isync - addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */ + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l mtdcr ocmdsarc, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ mtdcr ocmdscntl, r4 diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h new file mode 100644 index 0000000000..114dc92db9 --- /dev/null +++ b/include/asm-ppc/gpio.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* 4xx PPC's have 2 GPIO controllers */ +#if defined(CONFIG_405EZ) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define GPIO_GROUP_MAX 2 +#else +#define GPIO_GROUP_MAX 1 +#endif + +#define GPIO_MAX 32 +#define GPIO_ALT1_SEL 0x40000000 +#define GPIO_ALT2_SEL 0x80000000 +#define GPIO_ALT3_SEL 0xc0000000 +#define GPIO_IN_SEL 0x40000000 +#define GPIO_MASK 0xc0000000 + +#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) + +#ifndef __ASSEMBLY__ +typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; +typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; +typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t; + +typedef struct { + unsigned long add; /* gpio core base address */ + gpio_driver_t in_out; /* Driver Setting */ + gpio_select_t alt_nb; /* Selected Alternate */ +} gpio_param_s; +#endif + +void gpio_config(int pin, int in_out, int gpio_alt, int out_val); +void gpio_write_bit(int pin, int val); +void gpio_set_chip_configuration(void); diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 9e02ca31b4..35b6a519e3 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -31,20 +31,18 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_ACADIA 1 /* Board is Acadia */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ -#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_ACADIA 1 /* Board is Acadia */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */ #define CONFIG_NO_SERIAL_EEPROM /*#undef CONFIG_NO_SERIAL_EEPROM*/ #ifdef CONFIG_NO_SERIAL_EEPROM - /*---------------------------------------------------------------------------- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, * assuming a 66MHz input clock to the 405EZ. @@ -59,24 +57,125 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFE000000 #define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xfe000000 #define CFG_MONITOR_BASE TEXT_BASE +#define CFG_CPLD_BASE 0x80000000 +#define CFG_NAND_ADDR 0xd0000000 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ -/* - * Define here the location of the environment variables (FLASH). - * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only - * supported for backward compatibility. - */ +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else - #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ #endif +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * RAM (CRAM) + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_RAM 64 /* 64MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#if 0 /* test-only... */ +/*----------------------------------------------------------------------- + * SPI stuff - Define to include SPI control + *----------------------------------------------------------------------- + */ +#define CONFIG_SPI +#endif + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -122,13 +221,6 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_NET_MULTI 1 -#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - #define CONFIG_USB_OHCI #define CONFIG_USB_STORAGE @@ -166,7 +258,6 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ CFG_CMD_USB) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -174,76 +265,34 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* +/*----------------------------------------------------------------------- * Miscellaneous configurable options - */ + *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -/*----------------------------------------------------------------------- - * Serial Port - *----------------------------------------------------------------------*/ -#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ -#define CFG_BASE_BAUD 691200 -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/*----------------------------------------------------------------------- - * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F - -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 - -#if 0 /* test-only... */ -/*----------------------------------------------------------------------- - * SPI stuff - Define to include SPI control - *----------------------------------------------------------------------- - */ -#define CONFIG_SPI -#endif - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -251,39 +300,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH related - *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ - -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif - #ifdef TEST_ONLY_NAND /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 -#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS) +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #endif @@ -297,50 +320,42 @@ #endif /*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in data cache) - */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 - -/* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 -#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - -#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup - */ -#define CFG_NAND 0xd0000000 + *----------------------------------------------------------------------*/ #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (Flash) initialization */ +/* Memory Bank 0 (Flash) initialization */ #define CFG_EBC_PB0AP 0x03337200 -#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */ +#define CFG_EBC_PB0CR 0xfe0bc000 -/* Memory Bank 1 (CRAM) initialization */ +/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/ +/* Memory Bank 1 (CRAM) initialization */ #define CFG_EBC_PB1AP 0x030400c0 #define CFG_EBC_PB1CR 0x000bc000 -/* Memory Bank 2 (CRAM) initialization */ +/* Memory Bank 2 (CRAM) initialization */ #define CFG_EBC_PB2AP 0x030400c0 #define CFG_EBC_PB2CR 0x020bc000 /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) -/* Memory Bank 4 (CPLD) initialization */ +/* Memory Bank 4 (CPLD) initialization */ #define CFG_EBC_PB4AP 0x04006000 -#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */ +#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000) #define CFG_EBC_CFG 0xf8400000 /*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CFG_GPIO_CRAM_CLK 8 +#define CFG_GPIO_CRAM_WAIT 9 +#define CFG_GPIO_CRAM_ADV 10 +#define CFG_GPIO_CRAM_CRE (32 + 21) + +/*----------------------------------------------------------------------- * Definitions for GPIO_0 setup (PPC405EZ specific) * * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs @@ -389,25 +404,6 @@ #define CFG_GPIO1_TSRL 0x00000000 #define CFG_GPIO1_TCR 0xFFFF8014 -/*----------------------------------------------------------------------- - * EPLD Regs. - */ -#define EPLD_BASE 0x80000000 -#define EPLD_ETHRSTBOOT 0x10 -#define EPLD_CTRL 0x14 -#define EPLD_MUXOE 0x16 - -/* - * State definations - */ -#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */ -#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */ -#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */ -#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */ -#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */ -#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */ -#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */ - /* * Internal Definitions * diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 29f3b408d2..8a319250de 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -75,9 +75,7 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ - #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -381,9 +379,6 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_FLASH CFG_FLASH_BASE -#define CFG_NAND 0xD0000000 -#define CFG_CPLD 0xC0000000 /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting @@ -392,25 +387,25 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) #else #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017200 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) +#define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 -#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) #endif /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x24814580 -#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) +#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) /*----------------------------------------------------------------------- * NAND FLASH diff --git a/include/ppc440.h b/include/ppc440.h index 9b15c2c565..51e6b9b28c 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -3290,29 +3290,6 @@ #define GPIO1_ISR3H (GPIO1_BASE+0x44) #endif -#define GPIO_GROUP_MAX 2 -#define GPIO_MAX 32 -#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ -#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ -#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ -#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ -#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ - /* For the other GPIO number, you must shift */ - -#define GPIO_VAL(gpio) (0x80000000 >> (gpio)) - -#ifndef __ASSEMBLY__ - -typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; -typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; - -typedef struct { unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ -} gpio_param_s; - -#endif /* __ASSEMBLY__ */ - /* * Macros for accessing the indirect EBC registers */ diff --git a/include/serial.h b/include/serial.h index 48800595d7..f7412fd173 100644 --- a/include/serial.h +++ b/include/serial.h @@ -23,7 +23,7 @@ extern struct serial_device serial_scc_device; extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CFG_NS16550_SERIAL) |