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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/dts/r8a7790-lager-u-boot.dts4
-rw-r--r--arch/arm/dts/r8a7793-gose-u-boot.dts4
-rw-r--r--arch/arm/dts/r8a7794-alt-u-boot.dts4
-rw-r--r--arch/arm/dts/rk3188-radxarock-u-boot.dtsi24
-rw-r--r--arch/arm/dts/rk3188-radxarock.dts6
-rw-r--r--arch/arm/dts/rk3188.dtsi8
-rw-r--r--arch/arm/mach-rmobile/Kconfig.329
-rw-r--r--arch/arm/mach-rockchip/Kconfig1
-rw-r--r--arch/arm/mach-rockchip/Makefile2
-rwxr-xr-xarch/arm/mach-rockchip/make_fit_atf.py2
-rw-r--r--arch/arm/mach-rockchip/rk3188-board-spl.c2
-rw-r--r--arch/arm/mach-rockchip/rk322x-board-spl.c2
-rw-r--r--board/renesas/alt/Makefile6
-rw-r--r--board/renesas/alt/alt.c209
-rw-r--r--board/renesas/alt/alt_spl.c411
-rw-r--r--board/renesas/gose/Makefile8
-rw-r--r--board/renesas/gose/gose.c190
-rw-r--r--board/renesas/gose/gose_spl.c408
-rw-r--r--board/renesas/lager/Makefile6
-rw-r--r--board/renesas/lager/lager.c206
-rw-r--r--board/renesas/lager/lager_spl.c396
-rw-r--r--board/renesas/silk/silk.c2
-rw-r--r--configs/alt_defconfig49
-rw-r--r--configs/chromebit_mickey_defconfig1
-rw-r--r--configs/chromebook_jerry_defconfig1
-rw-r--r--configs/chromebook_minnie_defconfig1
-rw-r--r--configs/evb-rk3128_defconfig1
-rw-r--r--configs/evb-rk3229_defconfig1
-rw-r--r--configs/evb-rk3288_defconfig1
-rw-r--r--configs/evb-rk3328_defconfig1
-rw-r--r--configs/evb-rk3399_defconfig4
-rw-r--r--configs/fennec-rk3288_defconfig1
-rw-r--r--configs/firefly-rk3288_defconfig1
-rw-r--r--configs/firefly-rk3399_defconfig1
-rw-r--r--configs/gose_defconfig49
-rw-r--r--configs/lager_defconfig49
-rw-r--r--configs/miqi-rk3288_defconfig1
-rw-r--r--configs/phycore-rk3288_defconfig1
-rw-r--r--configs/popmetal-rk3288_defconfig1
-rw-r--r--configs/puma-rk3399_defconfig3
-rw-r--r--configs/r8a77965_salvator-x_defconfig3
-rw-r--r--configs/rock2_defconfig1
-rw-r--r--configs/rock_defconfig4
-rw-r--r--configs/tinker-rk3288_defconfig1
-rw-r--r--configs/vyasa-rk3288_defconfig1
-rw-r--r--drivers/clk/rockchip/clk_rk3036.c11
-rw-r--r--drivers/clk/rockchip/clk_rk3128.c11
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c13
-rw-r--r--drivers/clk/rockchip/clk_rv1108.c10
-rw-r--r--drivers/fpga/socfpga_arria10.c10
-rw-r--r--drivers/timer/rockchip_timer.c2
-rw-r--r--include/configs/alt.h71
-rw-r--r--include/configs/firefly-rk3288.h3
-rw-r--r--include/configs/gose.h64
-rw-r--r--include/configs/lager.h65
-rw-r--r--include/configs/rk3036_common.h3
-rw-r--r--include/configs/rk3128_common.h2
-rw-r--r--include/configs/rk3188_common.h5
-rw-r--r--include/configs/rk322x_common.h3
-rw-r--r--include/configs/rk3288_common.h3
-rw-r--r--include/configs/rv1108_common.h3
62 files changed, 1717 insertions, 650 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7212fc5afa..c930fa2846 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1185,6 +1185,7 @@ config ARCH_ROCKCHIP
imply TPL_SYSRESET
imply ADC
imply SARADC_ROCKCHIP
+ imply SYS_NS16550
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
diff --git a/arch/arm/dts/r8a7790-lager-u-boot.dts b/arch/arm/dts/r8a7790-lager-u-boot.dts
index a3f15777a6..a42d61c450 100644
--- a/arch/arm/dts/r8a7790-lager-u-boot.dts
+++ b/arch/arm/dts/r8a7790-lager-u-boot.dts
@@ -8,3 +8,7 @@
#include "r8a7790-lager.dts"
#include "r8a7790-u-boot.dtsi"
+
+&scif0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r8a7793-gose-u-boot.dts b/arch/arm/dts/r8a7793-gose-u-boot.dts
index 0c16dde4c7..ed6f391c62 100644
--- a/arch/arm/dts/r8a7793-gose-u-boot.dts
+++ b/arch/arm/dts/r8a7793-gose-u-boot.dts
@@ -8,3 +8,7 @@
#include "r8a7793-gose.dts"
#include "r8a7793-u-boot.dtsi"
+
+&scif0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/r8a7794-alt-u-boot.dts b/arch/arm/dts/r8a7794-alt-u-boot.dts
index 8a14e46a7a..e179335d3a 100644
--- a/arch/arm/dts/r8a7794-alt-u-boot.dts
+++ b/arch/arm/dts/r8a7794-alt-u-boot.dts
@@ -8,3 +8,7 @@
#include "r8a7794-alt.dts"
#include "r8a7794-u-boot.dtsi"
+
+&scif2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
new file mode 100644
index 0000000000..26f5707bb8
--- /dev/null
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&cru {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ status = "okay";
+ u-boot,dm-spl;
+};
+
+&timer3 {
+ compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+ u-boot,dm-spl;
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts
index 5f5b5e9a1f..0fc4f54af2 100644
--- a/arch/arm/dts/rk3188-radxarock.dts
+++ b/arch/arm/dts/rk3188-radxarock.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3188.dtsi"
+#include "rk3188-radxarock-u-boot.dtsi"
/ {
model = "Radxa Rock";
@@ -356,11 +357,6 @@
status = "okay";
};
-&uart2 {
- status = "okay";
- u-boot,dm-spl;
-};
-
&uart3 {
status = "okay";
};
diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi
index f4d438eb66..aeb5b80e14 100644
--- a/arch/arm/dts/rk3188.dtsi
+++ b/arch/arm/dts/rk3188.dtsi
@@ -105,7 +105,6 @@
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
- u-boot,dm-spl;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -124,6 +123,12 @@
};
};
+ timer3: timer@2000e000 {
+ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+ reg = <0x2000e000 0x20>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
usbphy: phy {
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
@@ -156,7 +161,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-spl;
gpio0: gpio0@2000a000 {
compatible = "rockchip,gpio-bank";
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index a8835f6571..84c1a6d07b 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -42,6 +42,9 @@ config TARGET_GOSE
bool "Gose board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_KOELSCH
bool "Koelsch board"
@@ -55,6 +58,9 @@ config TARGET_LAGER
bool "Lager board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_KZM9G
bool "KZM9D board"
@@ -63,6 +69,9 @@ config TARGET_ALT
bool "Alt board"
select DM
select DM_SERIAL
+ select SUPPORT_SPL
+ select USE_TINY_PRINTF
+ select SPL_TINY_MEMSET
config TARGET_SILK
bool "Silk board"
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 0adaed4367..007cb22a34 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
select DEBUG_UART_BOARD_INIT
- select SYS_NS16550
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
into a big and little cluster with 4 cores each) Cortex-A53 including
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index e1b0519b1f..096dbac25b 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -40,8 +40,10 @@ endif
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
ifndef CONFIG_ARM64
+ifndef CONFIG_ROCKCHIP_RK3188
obj-y += rk_timer.o
endif
+endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index 7c6dd57678..9a404d1d32 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -13,8 +13,6 @@ import getopt
# pip install pyelftools
from elftools.elf.elffile import ELFFile
-from elftools.elf.sections import SymbolTableSection
-from elftools.elf.segments import Segment, InterpSegment, NoteSegment
ELF_SEG_P_TYPE='p_type'
ELF_SEG_P_PADDR='p_paddr'
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 74771d3a0b..3ccc4f1205 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -131,8 +131,6 @@ void board_init_f(ulong dummy)
hang();
}
- rockchip_timer_init();
-
ret = rockchip_get_clk(&dev);
if (ret) {
debug("CLK init failed: %d\n", ret);
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
index 206abfafcd..d3d0446574 100644
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -95,7 +95,7 @@ void board_init_f(ulong dummy)
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}
diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile
index 22ab1f43d9..53418699b2 100644
--- a/board/renesas/alt/Makefile
+++ b/board/renesas/alt/Makefile
@@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := alt.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := alt_spl.o
+else
+obj-y := alt.o qos.o
+endif
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index f2200ef081..7598b1a4b9 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -43,176 +43,65 @@ void s_init(void)
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF2_MSTP719 (1 << 19)
-#define ETHER_MSTP813 (1 << 13)
-#define IIC1_MSTP323 (1 << 23)
-#define MMC0_MSTP315 (1 << 15)
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI1_MSTP312 (1 << 12)
+#define TMU0_MSTP125 BIT(25)
+#define MMC0_MSTP315 BIT(15)
#define SD1CKCR 0xE6150078
-#define SD1_97500KHZ 0x7
+#define SD_97500KHZ 0x7
int board_early_init_f(void)
{
/* TMU */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF2 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+ /* Set SD1 to the 97.5MHz */
+ writel(SD_97500KHZ, SD1CKCR);
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
- /* IIC1 / sh-i2c ch1 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
-
-#ifdef CONFIG_SH_MMCIF
- /* MMC */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
-#endif
-
-#ifdef CONFIG_SH_SDHI
- /* SDHI0, 1 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);
-
- /*
- * SD0 clock is set to 97.5MHz by default.
- * Set SD1 to the 97.5MHz as well.
- */
- writel(SD1_97500KHZ, SD1CKCR);
-#endif
return 0;
}
+#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7794_pinmux_init();
-
- /* Ether Enable */
-#if defined(CONFIG_R8A7794_ETHERNET_B)
- gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
- gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
- gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
- gpio_request(GPIO_FN_ETH_LINK_B, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
- gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
- gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
- gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
- gpio_request(GPIO_FN_ETH_MDC_B, NULL);
-#else
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
-#endif
- gpio_request(GPIO_FN_IRQ8, NULL);
-
- /* PHY reset */
- gpio_request(GPIO_GP_1_24, NULL);
- gpio_direction_output(GPIO_GP_1_24, 0);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
mdelay(20);
- gpio_set_value(GPIO_GP_1_24, 1);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
udelay(1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
-#ifdef CONFIG_SH_ETHER
- int ret = -ENODEV;
- u32 val;
- unsigned char enetaddr[6];
-
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
-
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
-
- return ret;
-#else
return 0;
-#endif
}
-int board_mmc_init(bd_t *bis)
+int dram_init_banksize(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_MMCIF
- gpio_request(GPIO_GP_4_31, NULL);
- gpio_set_value(GPIO_GP_4_31, 1);
-
- ret = mmcif_mmc_init();
-#endif
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DATA0, NULL);
- gpio_request(GPIO_FN_SD0_DATA1, NULL);
- gpio_request(GPIO_FN_SD0_DATA2, NULL);
- gpio_request(GPIO_FN_SD0_DATA3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD1_DATA0, NULL);
- gpio_request(GPIO_FN_SD1_DATA1, NULL);
- gpio_request(GPIO_FN_SD1_DATA2, NULL);
- gpio_request(GPIO_FN_SD1_DATA3, NULL);
- gpio_request(GPIO_FN_SD1_CLK, NULL);
- gpio_request(GPIO_FN_SD1_CMD, NULL);
- gpio_request(GPIO_FN_SD1_CD, NULL);
-
- /* SDHI 0 */
- gpio_request(GPIO_GP_2_26, NULL);
- gpio_request(GPIO_GP_2_29, NULL);
- gpio_direction_output(GPIO_GP_2_26, 1);
- gpio_direction_output(GPIO_GP_2_29, 1);
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
- if (ret)
- return ret;
+ fdtdec_setup_memory_banksize();
- /* SDHI 1 */
- gpio_request(GPIO_GP_4_26, NULL);
- gpio_request(GPIO_GP_4_29, NULL);
- gpio_direction_output(GPIO_GP_4_26, 1);
- gpio_direction_output(GPIO_GP_4_29, 1);
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
-#endif
- return ret;
+ return 0;
}
-int dram_init(void)
+/* KSZ8041RNLI */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
return 0;
}
@@ -223,22 +112,38 @@ const struct rmobile_sysinfo sysinfo = {
void reset_cpu(ulong addr)
{
- u8 val;
+ struct udevice *dev;
+ const u8 pmic_bus = 1;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
- i2c_set_bus_num(1); /* PowerIC connected to ch1 */
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
+
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
+
+ data |= BIT(1);
+
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF2_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
-U_BOOT_DEVICE(alt_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
diff --git a/board/renesas/alt/alt_spl.c b/board/renesas/alt/alt_spl.c
new file mode 100644
index 0000000000..f893a49257
--- /dev/null
+++ b/board/renesas/alt/alt_spl.c
@@ -0,0 +1,411 @@
+/*
+ * board/renesas/alt/alt_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF2_MSTP719 BIT(19)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD1CKCR 0xE6150078
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x00000000 },
+ { 0x0094, 0x00000000 },
+ { 0x0098, 0x00000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x40000000 },
+ { 0x002c, 0x00000155 },
+ { 0x0030, 0x00000002 },
+ { 0x0034, 0x00000000 },
+ { 0x0038, 0x00000000 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x60000000 },
+ { 0x0044, 0x36dab6db },
+ { 0x0048, 0x926da012 },
+ { 0x004c, 0x0008c383 },
+ { 0x0050, 0x00000000 },
+ { 0x0054, 0x00000140 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x00ec3fff },
+ { 0x000c, 0x5bffffff },
+ { 0x0010, 0x01bfe1ff },
+ { 0x0014, 0x5bffffff },
+ { 0x0018, 0x0f4b200f },
+ { 0x001c, 0x03ffffff },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0x00000000 },
+ { 0x0104, 0x4203fc00 },
+ { 0x0108, 0x00000000 },
+ { 0x010c, 0x159007ff },
+ { 0x0110, 0x80000000 },
+ { 0x0114, 0x00de481f },
+ { 0x0118, 0x00000000 },
+ };
+
+ static const struct reg_config pfc_with_unlock2[] = {
+ { 0x0060, 0xffffffff },
+ { 0x0064, 0xfffff000 },
+ { 0x0068, 0x55555500 },
+ { 0x006c, 0xffffff00 },
+ { 0x0070, 0x00000000 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
+ writel(~pfc_with_unlock2[i].val, pfc_base);
+ writel(pfc_with_unlock2[i].val,
+ pfc_base | pfc_with_unlock2[i].off);
+ }
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x2000, 0x3000, 0x4000, 0x5000
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x2000, 0x24000000 },
+ { 0x4000, 0xa4000000 },
+ { 0x5000, 0x0004c000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x01000000 },
+ { 0x2000, 0x24000000 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0xa4000000 },
+ { 0x5000, 0x0084c380 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0xff70ff70 },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0280, 0x0000a55a },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0005c000 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf00464db },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000006d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x00000009 },
+ { 0x0044, 0x00000007 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x00000009 },
+ { 0x0054, 0x000a0009 },
+ { 0x0058, 0x00000021 },
+ { 0x005c, 0x00000018 },
+ { 0x0060, 0x00000005 },
+ { 0x0064, 0x0000001b },
+ { 0x0068, 0x00000007 },
+ { 0x006c, 0x0000000a },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000010 },
+ { 0x0078, 0x000000ae },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x50213005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000200 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20082008 },
+ { 0x0380, 0x00020003 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c4e1 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcb6d0 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x85589955 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a852400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300210b4 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000b50 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000010 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081450 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+ /* Set SD1 to the 97.5MHz */
+ writel(SD_97500KHZ, SD1CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile
index e09ae1e414..c6a1dc21cd 100644
--- a/board/renesas/gose/Makefile
+++ b/board/renesas/gose/Makefile
@@ -1,9 +1,13 @@
#
-# board/renesas/alt/Makefile
+# board/renesas/gose/Makefile
#
# Copyright (C) 2014 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := gose.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := gose_spl.o
+else
+obj-y := gose.o qos.o
+endif
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 99d4ba6fd8..c9209701dd 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -46,13 +46,7 @@ void s_init(void)
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF0_MSTP721 (1 << 21)
-#define ETHER_MSTP813 (1 << 13)
-
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI1_MSTP312 (1 << 12)
-#define SDHI2_MSTP311 (1 << 11)
+#define TMU0_MSTP125 BIT(25)
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE615026C
@@ -60,143 +54,59 @@ void s_init(void)
int board_early_init_f(void)
{
- /* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
-
- /* SDHI */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3,
- SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311);
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD1 and SD2 to the 97.5MHz as well.
+ */
writel(SD_97500KHZ, SD1CKCR);
writel(SD_97500KHZ, SD2CKCR);
return 0;
}
-#define PUPR5 0xE6060114
-#define PUPR5_ETH 0x3FFC0000
-#define PUPR5_ETH_MAGIC (1 << 27)
+#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7793_pinmux_init();
-
- /* ETHER Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REFCLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ0, NULL);
-
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
- gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
- mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
-
- gpio_direction_output(GPIO_GP_5_22, 0);
- mdelay(20);
- gpio_set_value(GPIO_GP_5_22, 1);
- udelay(1);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
+ mdelay(10);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
- int ret = -ENODEV;
- u32 val;
- unsigned char enetaddr[6];
-
-#ifdef CONFIG_SH_ETHER
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
-
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
-#endif
-
- return ret;
+ return 0;
}
-int board_mmc_init(bd_t *bis)
+int dram_init_banksize(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DATA0, NULL);
- gpio_request(GPIO_FN_SD0_DATA1, NULL);
- gpio_request(GPIO_FN_SD0_DATA2, NULL);
- gpio_request(GPIO_FN_SD0_DATA3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD2_DATA0, NULL);
- gpio_request(GPIO_FN_SD2_DATA1, NULL);
- gpio_request(GPIO_FN_SD2_DATA2, NULL);
- gpio_request(GPIO_FN_SD2_DATA3, NULL);
- gpio_request(GPIO_FN_SD2_CLK, NULL);
- gpio_request(GPIO_FN_SD2_CMD, NULL);
- gpio_request(GPIO_FN_SD2_CD, NULL);
-
- /* SDHI 0 */
- gpio_request(GPIO_GP_7_17, NULL);
- gpio_request(GPIO_GP_2_12, NULL);
- gpio_direction_output(GPIO_GP_7_17, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
- if (ret)
- return ret;
-
- /* SDHI 1 */
- gpio_request(GPIO_GP_7_18, NULL);
- gpio_request(GPIO_GP_2_13, NULL);
- gpio_direction_output(GPIO_GP_7_18, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
- if (ret)
- return ret;
-
- /* SDHI 2 */
- gpio_request(GPIO_GP_7_19, NULL);
- gpio_request(GPIO_GP_2_26, NULL);
- gpio_direction_output(GPIO_GP_7_19, 1); /* power on */
- gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
+ fdtdec_setup_memory_banksize();
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
- return ret;
+ return 0;
}
-int dram_init(void)
+/* KSZ8041RNLI */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
return 0;
}
@@ -207,22 +117,38 @@ const struct rmobile_sysinfo sysinfo = {
void reset_cpu(ulong addr)
{
- u8 val;
+ struct udevice *dev;
+ const u8 pmic_bus = 6;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
+
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
+
+ data |= BIT(1);
- i2c_set_bus_num(2); /* PowerIC connected to ch2 */
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF0_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ const u32 load_magic = 0xb33fc0de;
-U_BOOT_DEVICE(gose_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ return ENVL_SPI_FLASH;
+}
diff --git a/board/renesas/gose/gose_spl.c b/board/renesas/gose/gose_spl.c
new file mode 100644
index 0000000000..17b9da69d0
--- /dev/null
+++ b/board/renesas/gose/gose_spl.c
@@ -0,0 +1,408 @@
+/*
+ * board/renesas/gose/gose_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF0_MSTP721 BIT(21)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x60000000 },
+ { 0x0094, 0x60000000 },
+ { 0x0098, 0x00800200 },
+ { 0x009c, 0x00000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x000244c8 },
+ { 0x002c, 0x00000000 },
+ { 0x0030, 0x00002400 },
+ { 0x0034, 0x01520000 },
+ { 0x0038, 0x00724003 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x00000000 },
+ { 0x0044, 0x00000000 },
+ { 0x0048, 0x00000000 },
+ { 0x004c, 0x00000000 },
+ { 0x0050, 0x00000000 },
+ { 0x0054, 0x00000000 },
+ { 0x0058, 0x00000000 },
+ { 0x005c, 0x00000000 },
+ { 0x0160, 0x00000000 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x00ec3fff },
+ { 0x000c, 0x3bc001e7 },
+ { 0x0010, 0x5bffffff },
+ { 0x0014, 0x1ffffffb },
+ { 0x0018, 0x01bffff0 },
+ { 0x001c, 0xcf7fffff },
+ { 0x0074, 0x0381fc00 },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0xffffffdf },
+ { 0x0104, 0xc883c3ff },
+ { 0x0108, 0x1201f3c9 },
+ { 0x010c, 0x00000000 },
+ { 0x0110, 0xffffeb04 },
+ { 0x0114, 0xc003ffff },
+ { 0x0118, 0x0800000f },
+ { 0x011c, 0x001800f0 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x2000, 0x04381000 },
+ { 0x5000, 0x00000000 },
+ { 0x5800, 0x000e0000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x00000000 },
+ { 0x2000, 0x04381010 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0x00000000 },
+ { 0x5000, 0x00400000 },
+ { 0x5400, 0x00000000 },
+ { 0x5800, 0x000e0380 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x2a103320 },
+ { 0x38, 0xff70ff70 },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0280, 0x0000a55a },
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config2[] = {
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0001c000 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf00464db },
+ { 0x0290, 0x00000061 },
+ { 0x02a0, 0x0000006d },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000073 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x0f030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000006 },
+ { 0x0064, 0x00000020 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000200 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20042004 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000001f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c561 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fcdb60 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d9cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868400 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
+ writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
index 0e44c69fd6..379368fdfc 100644
--- a/board/renesas/lager/Makefile
+++ b/board/renesas/lager/Makefile
@@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0
#
-obj-y := lager.o qos.o ../rcar-common/common.o
+ifdef CONFIG_SPL_BUILD
+obj-y := lager_spl.o
+else
+obj-y := lager.o qos.o
+endif
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 3566bcc788..505efb5bc4 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -57,105 +57,60 @@ void s_init(void)
qos_init();
}
-#define TMU0_MSTP125 (1 << 25)
-#define SCIF0_MSTP721 (1 << 21)
-#define ETHER_MSTP813 (1 << 13)
-#define MMC1_MSTP305 (1 << 5)
+#define TMU0_MSTP125 BIT(25)
-#define MSTPSR3 0xE6150048
-#define SMSTPCR3 0xE615013C
-#define SDHI0_MSTP314 (1 << 14)
-#define SDHI1_MSTP313 (1 << 13)
-#define SDHI2_MSTP312 (1 << 12)
-
-#define SD2CKCR 0xE6150078
-#define SD2_97500KHZ 0x7
+#define SD1CKCR 0xE6150078
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
int board_early_init_f(void)
{
- /* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
- /* ETHER */
- mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
- /* eMMC */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
- /* SDHI0, 2 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312);
/*
* SD0 clock is set to 97.5MHz by default.
- * Set SD2 to the 97.5MHz as well.
+ * Set SD1 and SD2 to the 97.5MHz as well.
*/
- writel(SD2_97500KHZ, SD2CKCR);
+ writel(SD_97500KHZ, SD1CKCR);
+ writel(SD_97500KHZ, SD2CKCR);
return 0;
}
-DECLARE_GLOBAL_DATA_PTR;
+#define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- /* Init PFC controller */
- r8a7790_pinmux_init();
-
- /* ETHER Enable */
- gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
- gpio_request(GPIO_FN_ETH_RX_ER, NULL);
- gpio_request(GPIO_FN_ETH_RXD0, NULL);
- gpio_request(GPIO_FN_ETH_RXD1, NULL);
- gpio_request(GPIO_FN_ETH_LINK, NULL);
- gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
- gpio_request(GPIO_FN_ETH_MDIO, NULL);
- gpio_request(GPIO_FN_ETH_TXD1, NULL);
- gpio_request(GPIO_FN_ETH_TX_EN, NULL);
- gpio_request(GPIO_FN_ETH_MAGIC, NULL);
- gpio_request(GPIO_FN_ETH_TXD0, NULL);
- gpio_request(GPIO_FN_ETH_MDC, NULL);
- gpio_request(GPIO_FN_IRQ0, NULL);
-
- gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
- gpio_direction_output(GPIO_GP_5_31, 0);
- mdelay(20);
- gpio_set_value(GPIO_GP_5_31, 1);
- udelay(1);
+ /* Force ethernet PHY out of reset */
+ gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+ gpio_direction_output(ETHERNET_PHY_RESET, 0);
+ mdelay(10);
+ gpio_direction_output(ETHERNET_PHY_RESET, 1);
return 0;
}
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_ETHER
- u32 val;
- unsigned char enetaddr[6];
+ if (fdtdec_setup_memory_size() != 0)
+ return -EINVAL;
- ret = sh_eth_initialize(bis);
- if (!eth_env_get_enetaddr("ethaddr", enetaddr))
- return ret;
-
- /* Set Mac address */
- val = enetaddr[0] << 24 | enetaddr[1] << 16 |
- enetaddr[2] << 8 | enetaddr[3];
- writel(val, CXR24);
-
- val = enetaddr[4] << 8 | enetaddr[5];
- writel(val, CXR25);
+ return 0;
+}
-#endif
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
- return ret;
+ return 0;
}
-/* lager has KSZ8041NL/RNL */
-#define PHY_CONTROL1 0x1E
-#define PHY_LED_MODE 0xC0000
+/* KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
#define PHY_LED_MODE_ACK 0x4000
int board_phy_config(struct phy_device *phydev)
{
@@ -167,97 +122,44 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
-int board_mmc_init(bd_t *bis)
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_ARCH_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
{
- int ret = -ENODEV;
-
-#ifdef CONFIG_SH_MMCIF
- gpio_request(GPIO_FN_MMC1_D0, NULL);
- gpio_request(GPIO_FN_MMC1_D1, NULL);
- gpio_request(GPIO_FN_MMC1_D2, NULL);
- gpio_request(GPIO_FN_MMC1_D3, NULL);
- gpio_request(GPIO_FN_MMC1_D4, NULL);
- gpio_request(GPIO_FN_MMC1_D5, NULL);
- gpio_request(GPIO_FN_MMC1_D6, NULL);
- gpio_request(GPIO_FN_MMC1_D7, NULL);
- gpio_request(GPIO_FN_MMC1_CLK, NULL);
- gpio_request(GPIO_FN_MMC1_CMD, NULL);
-
- ret = mmcif_mmc_init();
-#endif
-
-#ifdef CONFIG_SH_SDHI
- gpio_request(GPIO_FN_SD0_DAT0, NULL);
- gpio_request(GPIO_FN_SD0_DAT1, NULL);
- gpio_request(GPIO_FN_SD0_DAT2, NULL);
- gpio_request(GPIO_FN_SD0_DAT3, NULL);
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD2_DAT0, NULL);
- gpio_request(GPIO_FN_SD2_DAT1, NULL);
- gpio_request(GPIO_FN_SD2_DAT2, NULL);
- gpio_request(GPIO_FN_SD2_DAT3, NULL);
- gpio_request(GPIO_FN_SD2_CLK, NULL);
- gpio_request(GPIO_FN_SD2_CMD, NULL);
- gpio_request(GPIO_FN_SD2_CD, NULL);
+ struct udevice *dev;
+ const u8 pmic_bus = 2;
+ const u8 pmic_addr = 0x58;
+ u8 data;
+ int ret;
- /*
- * SDHI 0
- * need JP3 set to pin-1 side on board.
- */
- gpio_request(GPIO_GP_5_24, NULL);
- gpio_request(GPIO_GP_5_29, NULL);
- gpio_direction_output(GPIO_GP_5_24, 1); /* power on */
- gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */
+ ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+ if (ret)
+ hang();
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_16BIT_BUF);
+ ret = dm_i2c_read(dev, 0x13, &data, 1);
if (ret)
- return ret;
+ hang();
- /* SDHI 2 */
- gpio_request(GPIO_GP_5_25, NULL);
- gpio_request(GPIO_GP_5_30, NULL);
- gpio_direction_output(GPIO_GP_5_25, 1); /* power on */
- gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */
+ data |= BIT(1);
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
-#endif
- return ret;
+ ret = dm_i2c_write(dev, 0x13, &data, 1);
+ if (ret)
+ hang();
}
-
-int dram_init(void)
+enum env_location env_get_location(enum env_operation op, int prio)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ const u32 load_magic = 0xb33fc0de;
- return 0;
-}
+ /* Block environment access if loaded using JTAG */
+ if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+ (op != ENVOP_INIT))
+ return ENVL_UNKNOWN;
-const struct rmobile_sysinfo sysinfo = {
- CONFIG_ARCH_RMOBILE_BOARD_STRING
-};
-
-void reset_cpu(ulong addr)
-{
- u8 val;
+ if (prio)
+ return ENVL_UNKNOWN;
- i2c_set_bus_num(3); /* PowerIC connected to ch3 */
- i2c_init(400000, 0);
- i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
- val |= 0x02;
- i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ return ENVL_SPI_FLASH;
}
-
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF0_BASE,
- .type = PORT_SCIF,
- .clk = 14745600,
- .clk_mode = EXT_CLK,
-};
-
-U_BOOT_DEVICE(lager_serials) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
diff --git a/board/renesas/lager/lager_spl.c b/board/renesas/lager/lager_spl.c
new file mode 100644
index 0000000000..5730eb2f1e
--- /dev/null
+++ b/board/renesas/lager/lager_spl.c
@@ -0,0 +1,396 @@
+/*
+ * board/renesas/lager/lager_spl.c
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#include <spl.h>
+
+#define TMU0_MSTP125 BIT(25)
+#define SCIF0_MSTP721 BIT(21)
+#define QSPI_MSTP917 BIT(17)
+
+#define SD2CKCR 0xE615026C
+#define SD_97500KHZ 0x7
+
+struct reg_config {
+ u16 off;
+ u32 val;
+};
+
+static void dbsc_wait(u16 reg)
+{
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+
+ while (!(readl(dbsc3_0_base + reg) & BIT(0)))
+ ;
+}
+
+static void spl_init_sys(void)
+{
+ u32 r0 = 0;
+
+ writel(0xa5a5a500, 0xe6020004);
+ writel(0xa5a5a500, 0xe6030004);
+
+ asm volatile(
+ /* ICIALLU - Invalidate I$ to PoU */
+ "mcr 15, 0, %0, cr7, cr5, 0 \n"
+ /* BPIALL - Invalidate branch predictors */
+ "mcr 15, 0, %0, cr7, cr5, 6 \n"
+ /* Set SCTLR[IZ] */
+ "mrc 15, 0, %0, cr1, cr0, 0 \n"
+ "orr %0, #0x1800 \n"
+ "mcr 15, 0, %0, cr1, cr0, 0 \n"
+ "isb sy \n"
+ :"=r"(r0));
+}
+
+static void spl_init_pfc(void)
+{
+ static const struct reg_config pfc_with_unlock[] = {
+ { 0x0090, 0x00000000 },
+ { 0x0094, 0x00000000 },
+ { 0x0098, 0xc0000000 },
+ { 0x0020, 0x00000000 },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x00000000 },
+ { 0x002c, 0x20000000 },
+ { 0x0030, 0x00001249 },
+ { 0x0034, 0x00000278 },
+ { 0x0038, 0x00000841 },
+ { 0x003c, 0x00000000 },
+ { 0x0040, 0x00000000 },
+ { 0x0044, 0x10000000 },
+ { 0x0048, 0x00000001 },
+ { 0x004c, 0x0004aab0 },
+ { 0x0050, 0x37301b00 },
+ { 0x0054, 0x00048da3 },
+ { 0x0058, 0x089044a1 },
+ { 0x005c, 0x2a3a55b4 },
+ { 0x0160, 0x00000003 },
+ { 0x0004, 0xffffffff },
+ { 0x0008, 0x2aef3fff },
+ { 0x000c, 0x3fffffff },
+ { 0x0010, 0xff7fc07f },
+ { 0x0014, 0x7f3ff3f8 },
+ { 0x0018, 0x1cfdfff7 },
+ };
+
+ static const struct reg_config pfc_without_unlock[] = {
+ { 0x0100, 0x1fffffff },
+ { 0x0104, 0xffff0318 },
+ { 0x0108, 0x387fffe1 },
+ { 0x010c, 0x00803f80 },
+ { 0x0110, 0x1520009f },
+ { 0x0114, 0x00000000 },
+ { 0x0118, 0x00000000 },
+ };
+
+ static const u32 pfc_base = 0xe6060000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
+ writel(~pfc_with_unlock[i].val, pfc_base);
+ writel(pfc_with_unlock[i].val,
+ pfc_base | pfc_with_unlock[i].off);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
+ writel(pfc_without_unlock[i].val,
+ pfc_base | pfc_without_unlock[i].off);
+}
+
+static void spl_init_gpio(void)
+{
+ static const u16 gpio_offs[] = {
+ 0x1000, 0x3000, 0x4000, 0x5000
+ };
+
+ static const struct reg_config gpio_set[] = {
+ { 0x4000, 0x00c00000 },
+ { 0x5000, 0x63020000 },
+ };
+
+ static const struct reg_config gpio_clr[] = {
+ { 0x1000, 0x00000000 },
+ { 0x3000, 0x00000000 },
+ { 0x4000, 0x00c00000 },
+ { 0x5000, 0xe3020000 },
+ };
+
+ static const u32 gpio_base = 0xe6050000;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x20 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
+ writel(0, gpio_base | 0x00 | gpio_offs[i]);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
+ writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
+
+ for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
+ writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
+}
+
+static void spl_init_lbsc(void)
+{
+ static const struct reg_config lbsc_config[] = {
+ { 0x00, 0x00000020 },
+ { 0x08, 0x00002020 },
+ { 0x30, 0x02150326 },
+ { 0x38, 0x077f077f },
+ };
+
+ static const u16 lbsc_offs[] = {
+ 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
+ };
+
+ static const u32 lbsc_base = 0xfec00200;
+
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
+ writel(lbsc_config[i].val,
+ lbsc_base | lbsc_config[i].off);
+ writel(lbsc_config[i].val,
+ lbsc_base | (lbsc_config[i].off + 4));
+ }
+
+ for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
+ writel(0, lbsc_base | lbsc_offs[i]);
+}
+
+static void spl_init_dbsc(void)
+{
+ static const struct reg_config dbsc_config1[] = {
+ { 0x0018, 0x21000000 },
+ { 0x0018, 0x11000000 },
+ { 0x0018, 0x10000000 },
+ { 0x0280, 0x0000a55a },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x80000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config4[] = {
+ { 0x0290, 0x00000010 },
+ { 0x02a0, 0xf004649b },
+ { 0x0290, 0x0000000f },
+ { 0x02a0, 0x00181ee4 },
+ { 0x0290, 0x00000060 },
+ { 0x02a0, 0x330657b2 },
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000071 },
+ { 0x0020, 0x00000007 },
+ { 0x0024, 0x10030a02 },
+ { 0x0030, 0x00000001 },
+ { 0x00b0, 0x00000000 },
+ { 0x0040, 0x0000000b },
+ { 0x0044, 0x00000008 },
+ { 0x0048, 0x00000000 },
+ { 0x0050, 0x0000000b },
+ { 0x0054, 0x000c000b },
+ { 0x0058, 0x00000027 },
+ { 0x005c, 0x0000001c },
+ { 0x0060, 0x00000005 },
+ { 0x0064, 0x00000018 },
+ { 0x0068, 0x00000008 },
+ { 0x006c, 0x0000000c },
+ { 0x0070, 0x00000009 },
+ { 0x0074, 0x00000012 },
+ { 0x0078, 0x000000d0 },
+ { 0x007c, 0x00140005 },
+ { 0x0080, 0x00050004 },
+ { 0x0084, 0x70233005 },
+ { 0x0088, 0x000c0000 },
+ { 0x008c, 0x00000300 },
+ { 0x0090, 0x00000040 },
+ { 0x0100, 0x00000001 },
+ { 0x00c0, 0x00020001 },
+ { 0x00c8, 0x20082008 },
+ { 0x0380, 0x00020002 },
+ { 0x0390, 0x0000000f },
+ };
+
+ static const struct reg_config dbsc_config5[] = {
+ { 0x0244, 0x00000011 },
+ { 0x0290, 0x00000006 },
+ { 0x02a0, 0x0005c000 },
+ { 0x0290, 0x00000003 },
+ { 0x02a0, 0x0300c481 },
+ { 0x0290, 0x00000023 },
+ { 0x02a0, 0x00fdb6c0 },
+ { 0x0290, 0x00000011 },
+ { 0x02a0, 0x1000040b },
+ { 0x0290, 0x00000012 },
+ { 0x02a0, 0x9d5cbb66 },
+ { 0x0290, 0x00000013 },
+ { 0x02a0, 0x1a868300 },
+ { 0x0290, 0x00000014 },
+ { 0x02a0, 0x300214d8 },
+ { 0x0290, 0x00000015 },
+ { 0x02a0, 0x00000d70 },
+ { 0x0290, 0x00000016 },
+ { 0x02a0, 0x00000006 },
+ { 0x0290, 0x00000017 },
+ { 0x02a0, 0x00000018 },
+ { 0x0290, 0x0000001a },
+ { 0x02a0, 0x910035c7 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config6[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x00000181 },
+ { 0x0018, 0x11000000 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config7[] = {
+ { 0x0290, 0x00000001 },
+ { 0x02a0, 0x0000fe01 },
+ { 0x0290, 0x00000004 },
+ };
+
+ static const struct reg_config dbsc_config8[] = {
+ { 0x0304, 0x00000000 },
+ { 0x00f4, 0x01004c20 },
+ { 0x00f8, 0x014000aa },
+ { 0x00e0, 0x00000140 },
+ { 0x00e4, 0x00081860 },
+ { 0x00e8, 0x00010000 },
+ { 0x0014, 0x00000001 },
+ { 0x0010, 0x00000001 },
+ { 0x0280, 0x00000000 },
+ };
+
+ static const u32 dbsc3_0_base = DBSC3_0_BASE;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
+ writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
+ writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
+
+ dbsc_wait(0x240);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
+ writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
+ writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
+ writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
+
+ dbsc_wait(0x2a0);
+
+ for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
+ writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
+
+}
+
+static void spl_init_qspi(void)
+{
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+ static const u32 qspi_base = 0xe6b10000;
+
+ writeb(0x08, qspi_base + 0x00);
+ writeb(0x00, qspi_base + 0x01);
+ writeb(0x06, qspi_base + 0x02);
+ writeb(0x01, qspi_base + 0x0a);
+ writeb(0x00, qspi_base + 0x0b);
+ writeb(0x00, qspi_base + 0x0c);
+ writeb(0x00, qspi_base + 0x0d);
+ writeb(0x00, qspi_base + 0x0e);
+
+ writew(0xe080, qspi_base + 0x10);
+
+ writeb(0xc0, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x18);
+ writeb(0x00, qspi_base + 0x08);
+ writeb(0x48, qspi_base + 0x00);
+}
+
+void board_init_f(ulong dummy)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD2 to the 97.5MHz as well.
+ */
+ writel(SD_97500KHZ, SD2CKCR);
+
+ spl_init_sys();
+ spl_init_pfc();
+ spl_init_gpio();
+ spl_init_lbsc();
+ spl_init_dbsc();
+ spl_init_qspi();
+}
+
+void spl_board_init(void)
+{
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const u32 jtag_magic = 0x1337c0de;
+ const u32 load_magic = 0xb33fc0de;
+
+ /*
+ * If JTAG probe sets special word at 0xe6300020, then it must
+ * put U-Boot into RAM and SPL will start it from RAM.
+ */
+ if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
+ printf("JTAG boot detected!\n");
+
+ while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
+ ;
+
+ spl_boot_list[0] = BOOT_DEVICE_RAM;
+ spl_boot_list[1] = BOOT_DEVICE_NONE;
+
+ return;
+ }
+
+ /* Boot from SPI NOR with YMODEM UART fallback. */
+ spl_boot_list[0] = BOOT_DEVICE_SPI;
+ spl_boot_list[1] = BOOT_DEVICE_UART;
+ spl_boot_list[2] = BOOT_DEVICE_NONE;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index bfe9909daf..c932c255a0 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -114,7 +114,7 @@ void reset_cpu(ulong addr)
{
struct udevice *dev;
const u8 pmic_bus = 1;
- const u8 pmic_addr = 0x58;
+ const u8 pmic_addr = 0x5a;
u8 data;
int ret;
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index 19ae070895..9867a5f4d5 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -1,17 +1,37 @@
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE6304000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7794=y
CONFIG_TARGET_ALT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
@@ -19,22 +39,43 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index d8ab84b8e4..d1728ef639 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -71,7 +71,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 5dabae5434..43d93f4637 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -72,7 +72,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index c54c00f484..706809ca53 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -71,7 +71,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index 5407cbaf22..796d0ec92e 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -34,7 +34,6 @@ CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 549a16673a..710b0b4e1a 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -46,7 +46,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index d625fb1c5f..7695277daf 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index a52e37ac74..78ae24b56b 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -44,7 +44,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index b36f232dcb..08c0ab0e27 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
@@ -25,6 +26,8 @@ CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
@@ -56,7 +59,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index d1f7f777ed..efdd583cf6 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0f254c0972..b252d27464 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 984c3f4ed6..19c0b11040 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -58,7 +58,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index baa8d85e48..8edb9a8345 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -1,17 +1,37 @@
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE6304000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7793=y
CONFIG_TARGET_GOSE=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
@@ -19,21 +39,42 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 86fab8c014..17fc8ae06e 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -1,17 +1,37 @@
CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_RMOBILE=y
-CONFIG_SYS_TEXT_BASE=0xE8080000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_TEXT_BASE=0x50000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_R8A7790=y
CONFIG_TARGET_LAGER=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot"
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
@@ -19,22 +39,43 @@ CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_CLK=y
+CONFIG_CLK_RENESAS=y
+CONFIG_DM_GPIO=y
+CONFIG_RCAR_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_RCAR_IIC=y
+CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
+CONFIG_RENESAS_SDHI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MICREL=y
-CONFIG_NETDEVICES=y
+CONFIG_DM_ETH=y
CONFIG_SH_ETHER=y
-CONFIG_BAUDRATE=38400
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_RCAR_GEN2=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_PFC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SH_QSPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
CONFIG_USB_STORAGE=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index af5b9cc6a4..f44537c88f 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 66decf0653..d78b6d57b6 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 8343a4ab4d..2670b4b75a 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 4324a82e76..e6539a7da8 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -80,10 +80,11 @@ CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ISL1208=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
diff --git a/configs/r8a77965_salvator-x_defconfig b/configs/r8a77965_salvator-x_defconfig
index 986c076d51..fdce7f7c65 100644
--- a/configs/r8a77965_salvator-x_defconfig
+++ b/configs/r8a77965_salvator-x_defconfig
@@ -39,6 +39,9 @@ CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index a59599ebbc..cd9a821974 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index c4a236ccf6..08ca78d03b 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -5,6 +5,9 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3188=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ROCKCHIP_TIMER=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
@@ -47,7 +50,6 @@ CONFIG_RAM=y
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_ROCKCHIP_USB2_PHY=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index d5c705ae46..fb6bfa57ad 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -66,7 +66,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index bf1de5a56e..9e4e96a4f2 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 560222b96c..5e11318042 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -317,11 +317,19 @@ static struct clk_ops rk3036_clk_ops = {
.set_rate = rk3036_clk_set_rate,
};
-static int rk3036_clk_probe(struct udevice *dev)
+static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3036_clk_probe(struct udevice *dev)
+{
+ struct rk3036_clk_priv *priv = dev_get_priv(dev);
+
rkclk_init(priv->cru);
return 0;
@@ -367,6 +375,7 @@ U_BOOT_DRIVER(rockchip_rk3036_cru) = {
.id = UCLASS_CLK,
.of_match = rk3036_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
+ .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
.ops = &rk3036_clk_ops,
.bind = rk3036_clk_bind,
.probe = rk3036_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index 132d50dda3..7b479e79bb 100644
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -546,11 +546,19 @@ static struct clk_ops rk3128_clk_ops = {
.set_rate = rk3128_clk_set_rate,
};
+static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3128_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
static int rk3128_clk_probe(struct udevice *dev)
{
struct rk3128_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3128_cru *)dev_read_addr(dev);
rkclk_init(priv->cru);
return 0;
@@ -590,6 +598,7 @@ U_BOOT_DRIVER(rockchip_rk3128_cru) = {
.id = UCLASS_CLK,
.of_match = rk3128_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
+ .ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
.ops = &rk3128_clk_ops,
.bind = rk3128_clk_bind,
.probe = rk3128_clk_probe,
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 3a36d04096..78ada2d2db 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -893,12 +893,25 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par
return -ENOENT;
}
+static int rk3288_clk_enable(struct clk *clk)
+{
+ switch (clk->id) {
+ case HCLK_USBHOST0:
+ case HCLK_HSIC:
+ return 0;
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
static struct clk_ops rk3288_clk_ops = {
.get_rate = rk3288_clk_get_rate,
.set_rate = rk3288_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3288_clk_set_parent,
#endif
+ .enable = rk3288_clk_enable,
};
static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 958fc78592..42341a8566 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -209,12 +209,19 @@ static void rkclk_init(struct rv1108_cru *cru)
printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
}
-static int rv1108_clk_probe(struct udevice *dev)
+static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
+ return 0;
+}
+
+static int rv1108_clk_probe(struct udevice *dev)
+{
+ struct rv1108_clk_priv *priv = dev_get_priv(dev);
+
rkclk_init(priv->cru);
return 0;
@@ -260,6 +267,7 @@ U_BOOT_DRIVER(clk_rv1108) = {
.id = UCLASS_CLK,
.of_match = rv1108_clk_ids,
.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
+ .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
.ops = &rv1108_clk_ops,
.bind = rv1108_clk_bind,
.probe = rv1108_clk_probe,
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index d5763965dd..685e8e271a 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -111,12 +111,12 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
- /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
- * timeout at 1000ms
+ /*
+ * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
+ * de-asserted, timeout at 1000ms
*/
- return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
- mask,
- false, FPGA_TIMEOUT_MSEC, false);
+ return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
+ true, FPGA_TIMEOUT_MSEC, false);
}
static int wait_for_f2s_nstatus_pin(unsigned long value)
diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c
index 07d14482d6..b847bc40c4 100644
--- a/drivers/timer/rockchip_timer.c
+++ b/drivers/timer/rockchip_timer.c
@@ -152,6 +152,8 @@ static const struct timer_ops rockchip_timer_ops = {
};
static const struct udevice_id rockchip_timer_ids[] = {
+ { .compatible = "rockchip,rk3188-timer" },
+ { .compatible = "rockchip,rk3288-timer" },
{ .compatible = "rockchip,rk3368-timer" },
{}
};
diff --git a/include/configs/alt.h b/include/configs/alt.h
index d6236870b9..619660b2bd 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -15,12 +15,8 @@
#include "rcar-gen2-common.h"
-#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
-#endif
-#define STACK_AREA_SIZE 0xC000
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
@@ -41,52 +37,29 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
-
-#define CONFIG_SYS_TMU_CLK_DIV 4
-
-/* i2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SYS_I2C_SH_SPEED1 400000
-#define CONFIG_SYS_I2C_SH_SPEED2 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* MMCIF */
-#define CONFIG_SH_MMCIF_ADDR 0xee200000
-#define CONFIG_SH_MMCIF_CLK 48000000
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF2 */
-#define CONFIG_SMSTP7_ENA 0x00080000
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
+
+#define CONFIG_SYS_TMU_CLK_DIV 4
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __ALT_H */
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index d6bb9f6fb4..2b0ac9ec5f 100644
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -10,8 +10,7 @@
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
- "stderr=serial,vidconsole\0" \
- "preboot=usb start\0"
+ "stderr=serial,vidconsole\0"
#include <configs/rk3288_common.h>
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 3531621910..af6189e4c1 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -14,21 +14,15 @@
#include "rcar-gen2-common.h"
-/* STACK */
-#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
-#endif
-
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
- (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE 0x40000000
-#define RCAR_GEN2_SDRAM_SIZE 0x40000000
-#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000
+#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024)
/* SCIF */
@@ -41,45 +35,29 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_SYS_TMU_CLK_DIV 4
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
-#define CONFIG_SYS_I2C_SH_SPEED0 400000
-#define CONFIG_SYS_I2C_SH_SPEED1 400000
-#define CONFIG_SYS_I2C_SH_SPEED2 400000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 10000000
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA 0x00200000
+#define CONFIG_SYS_TMU_CLK_DIV 4
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __GOSE_H */
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 97f7b2c7e7..3bd4d51fc3 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -15,14 +15,9 @@
#include "rcar-gen2-common.h"
-/* STACK */
-#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
-#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
-#else
-#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
-#endif
-#define STACK_AREA_SIZE 0xC000
-#define LOW_LEVEL_MERAM_STACK \
+#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
+#define STACK_AREA_SIZE 0x00100000
+#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
/* MEMORY */
@@ -32,60 +27,38 @@
/* SCIF */
-/* SPI */
+/* FLASH */
#define CONFIG_SPI
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_RCAR
-#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
-#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
-#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
-
-#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
-
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
-#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
-#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
-#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_SYS_TMU_CLK_DIV 4
-/* USB */
-#define CONFIG_USB_EHCI_RMOBILE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-
-/* MMC */
-#define CONFIG_SH_MMCIF_ADDR 0xEE220000
-#define CONFIG_SH_MMCIF_CLK 97500000
-
-/* Module stop status bits */
-/* INTC-RT */
-#define CONFIG_SMSTP0_ENA 0x00400000
-/* MSIF */
-#define CONFIG_SMSTP2_ENA 0x00002000
-/* INTC-SYS, IRQC */
-#define CONFIG_SMSTP4_ENA 0x00000180
-/* SCIF0 */
-#define CONFIG_SMSTP7_ENA 0x00200000
-
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ 97500000
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+/* SPL support */
+#define CONFIG_SPL_TEXT_BASE 0xe6300000
+#define CONFIG_SPL_STACK 0xe6340000
+#define CONFIG_SPL_MAX_SIZE 0x4000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ 65000000
+#endif
#endif /* __LAGER_H */
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index f39a272e6d..c5ec864b1e 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10081fff
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index bd8019c6a5..c593f18fdb 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -19,8 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 94f8cda853..e07facd9c3 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -17,11 +17,6 @@
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
-#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */
-#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 7f9c7fbfd5..0fb72214f4 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -18,11 +18,10 @@
#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10088000
-#define CONFIG_SPL_TEXT_BASE 0x10081004
+#define CONFIG_SPL_TEXT_BASE 0x10081000
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 78595b86ec..23dbfecf01 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -19,8 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550_MEM32
-
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
#endif
@@ -73,6 +71,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x0fffffff\0" \
"initrd_high=0x0fffffff\0" \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 349c53c289..cd204e9718 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)