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-rw-r--r--arch/arm/mach-sunxi/dram_sunxi_dw.c18
-rw-r--r--configs/pine_h64_defconfig1
-rw-r--r--drivers/net/sun8i_emac.c20
-rw-r--r--drivers/phy/allwinner/phy-sun4i-usb.c6
4 files changed, 27 insertions, 18 deletions
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 5d84798ca4..a462538521 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -79,15 +79,15 @@ enum {
MBUS_QOS_HIGHEST
};
-inline void mbus_configure_port(u8 port,
- bool bwlimit,
- bool priority,
- u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
- u8 waittime, /* 0 .. 0xf */
- u8 acs, /* 0 .. 0xff */
- u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
- u16 bwl1,
- u16 bwl2)
+static inline void mbus_configure_port(u8 port,
+ bool bwlimit,
+ bool priority,
+ u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
+ u8 waittime, /* 0 .. 0xf */
+ u8 acs, /* 0 .. 0xff */
+ u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
+ u16 bwl1,
+ u16 bwl2)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig
index 8937c51bd0..87871fd19f 100644
--- a/configs/pine_h64_defconfig
+++ b/configs/pine_h64_defconfig
@@ -10,5 +10,6 @@ CONFIG_SPL_SPI_SUNXI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
+CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 99e24c6348..e2b05ace8f 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -111,6 +111,7 @@ enum emac_variant {
H3_EMAC,
A64_EMAC,
R40_GMAC,
+ H6_EMAC,
};
struct emac_dma_desc {
@@ -300,9 +301,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
if (priv->variant == R40_GMAC) {
/* Select RGMII for R40 */
reg = readl(priv->sysctl_reg + 0x164);
- reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
- CCM_GMAC_CTRL_GPIT_RGMII |
- CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
+ reg |= SC_ETCS_INT_GMII |
+ SC_EPIT |
+ (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
writel(reg, priv->sysctl_reg + 0x164);
return 0;
@@ -310,14 +311,16 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
reg = readl(priv->sysctl_reg + 0x30);
- if (priv->variant == H3_EMAC) {
+ if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, &reg);
if (ret)
return ret;
}
reg &= ~(SC_ETCS_MASK | SC_EPIT);
- if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
+ if (priv->variant == H3_EMAC ||
+ priv->variant == A64_EMAC ||
+ priv->variant == H6_EMAC)
reg &= ~SC_RMII_EN;
switch (priv->interface) {
@@ -329,7 +332,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
break;
case PHY_INTERFACE_MODE_RMII:
if (priv->variant == H3_EMAC ||
- priv->variant == A64_EMAC) {
+ priv->variant == A64_EMAC ||
+ priv->variant == H6_EMAC) {
reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
break;
}
@@ -535,7 +539,7 @@ static int parse_phy_pins(struct udevice *dev)
if (priv->variant == H3_EMAC)
sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
- else if (priv->variant == R40_GMAC)
+ else if (priv->variant == R40_GMAC || priv->variant == H6_EMAC)
sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
else
sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
@@ -1032,6 +1036,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = {
.data = (uintptr_t)A83T_EMAC },
{.compatible = "allwinner,sun8i-r40-gmac",
.data = (uintptr_t)R40_GMAC },
+ {.compatible = "allwinner,sun50i-h6-emac",
+ .data = (uintptr_t)H6_EMAC },
{ }
};
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index b4bae22c2c..f050645044 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -282,7 +282,8 @@ static int sun4i_usb_phy_init(struct phy *phy)
return ret;
}
- if (data->cfg->type == sun8i_a83t_phy) {
+ if (data->cfg->type == sun8i_a83t_phy ||
+ data->cfg->type == sun50i_h6_phy) {
if (phy->id == 0) {
val = readl(data->base + data->cfg->phyctl_offset);
val |= PHY_CTL_VBUSVLDEXT;
@@ -324,7 +325,8 @@ static int sun4i_usb_phy_exit(struct phy *phy)
int ret;
if (phy->id == 0) {
- if (data->cfg->type == sun8i_a83t_phy) {
+ if (data->cfg->type == sun8i_a83t_phy ||
+ data->cfg->type == sun50i_h6_phy) {
void __iomem *phyctl = data->base +
data->cfg->phyctl_offset;