diff options
| -rw-r--r-- | post/board/lwmon5/dspic.c | 2 | ||||
| -rw-r--r-- | post/board/lwmon5/fpga.c | 4 | ||||
| -rw-r--r-- | post/board/lwmon5/gdc.c | 2 |
3 files changed, 6 insertions, 2 deletions
diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c index 897a852e40..65b96bcc24 100644 --- a/post/board/lwmon5/dspic.c +++ b/post/board/lwmon5/dspic.c @@ -94,9 +94,9 @@ int dspic_post_test(int flags) } data = dspic_read(DSPIC_SYS_ERROR_REG); - if (data != 0) ret = 1; if (data == -1) { post_log("dsPIC : failed read system error\n"); + ret = 1; } else { post_log("dsPIC SYS-ERROR code: 0x%04X\n", data); } diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c index 7a36c168c9..dca7a30a98 100644 --- a/post/board/lwmon5/fpga.c +++ b/post/board/lwmon5/fpga.c @@ -39,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; #define FPGA_VERSION_REG 0xC4000040 #define FPGA_RAM_START 0xC4200000 #define FPGA_RAM_END 0xC4203FFF +#define FPGA_STAT 0xC400000C #define FPGA_PWM_CTRL_REG 0xC4000020 #define FPGA_PWM_TV_REG 0xC4000024 @@ -93,6 +94,9 @@ int fpga_post_test(int flags) post_log("FPGA : version %u.%u\n", (version >> 8) & 0xFF, version & 0xFF); + /* Enable write to FPGA RAM */ + out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000); + read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000); post_log("FPGA RAM size: %d bytes\n", read_value); diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c index 42da370192..73d5935ce5 100644 --- a/post/board/lwmon5/gdc.c +++ b/post/board/lwmon5/gdc.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define GDC_SCRATCH_REG 0xC1FF8044 +#define GDC_SCRATCH_REG 0xC1FF8008 #define GDC_VERSION_REG 0xC1FF8084 #define GDC_RAM_START 0xC0000000 #define GDC_RAM_END 0xC2000000 |