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-rw-r--r--board/amcc/sequoia/sdram.c6
-rw-r--r--board/amcc/sequoia/sequoia.c58
-rw-r--r--common/cmd_nand.c2
-rw-r--r--cpu/ppc4xx/cpu.c6
-rw-r--r--drivers/mtd/Makefile2
-rw-r--r--include/configs/davinci_dvevm.h2
-rw-r--r--include/configs/davinci_schmoogie.h2
-rw-r--r--include/configs/davinci_sffsdr.h2
-rw-r--r--include/configs/davinci_sonata.h2
-rw-r--r--include/configs/kilauea.h13
-rw-r--r--include/configs/sequoia.h15
11 files changed, 93 insertions, 17 deletions
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index c26e6ee218..6df4c6d9b3 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -44,7 +44,7 @@ extern void denali_core_search_data_eye(void);
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
-#define get_bus_freq(val) 133000000
+#define get_bus_freq(val) 133333333
#endif
/*************************************************************************
@@ -55,11 +55,7 @@ extern void denali_core_search_data_eye(void);
phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#if !defined(CONFIG_NAND_SPL)
ulong speed = get_bus_freq(0);
-#else
- ulong speed = 133333333; /* 133MHz is on the safe side */
-#endif
mtsdram(DDR0_02, 0x00000000);
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index d6668e29b9..e824b8fa4a 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@@ -35,7 +35,8 @@ DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-ulong flash_get_size (ulong base, int banknum);
+extern void __ft_board_setup(void *blob, bd_t *bd);
+ulong flash_get_size(ulong base, int banknum);
int board_early_init_f(void)
{
@@ -513,3 +514,56 @@ int post_hotkeys_pressed(void)
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
+
+#if defined(CONFIG_NAND_U_BOOT)
+/*
+ * On NAND-booting sequoia, we need to patch the chips select numbers
+ * in the dtb (CS0 - NAND, CS3 - NOR)
+ */
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+ int len;
+ int nodeoffset;
+ struct fdt_property *prop;
+ u32 *reg;
+ char path[32];
+
+ /* First do common fdt setup */
+ __ft_board_setup(blob, bd);
+
+ /* And now configure NOR chip select to 3 instead of 0 */
+ strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
+ nodeoffset = fdt_path_offset(blob, path);
+ prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+ if (prop == NULL) {
+ printf("Unable to update NOR chip select for NAND booting\n");
+ return;
+ }
+ reg = (u32 *)&prop->data[0];
+ reg[0] = 3;
+ rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+ if (rc) {
+ printf("Unable to update property NOR mappings, err=%s\n",
+ fdt_strerror(rc));
+ return;
+ }
+
+ /* And now configure NAND chip select to 0 instead of 3 */
+ strcpy(path, "/plb/opb/ebc/ndfc@3,0");
+ nodeoffset = fdt_path_offset(blob, path);
+ prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+ if (prop == NULL) {
+ printf("Unable to update NDFC chip select for NAND booting\n");
+ return;
+ }
+ reg = (u32 *)&prop->data[0];
+ reg[0] = 0;
+ rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+ if (rc) {
+ printf("Unable to update property NDFC mappings, err=%s\n",
+ fdt_strerror(rc));
+ return;
+ }
+}
+#endif /* CONFIG_NAND_U_BOOT */
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index e142d76661..ff5bc6e27d 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -390,7 +390,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
else
ret = nand_write_skip_bad(nand, off, &size,
(u_char *)addr);
- } else if (s != NULL && !strcmp(s, ".oob")) {
+ } else if (!strcmp(s, ".oob")) {
/* out-of-band data */
mtd_oob_ops_t ops = {
.oobbuf = (u8 *)addr,
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index d09c4c2153..9a6a8d7c9b 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -586,7 +586,11 @@ int checkcpu (void)
#endif /* I2C_BOOTROM */
#if defined(SDR0_PINSTP_SHIFT)
printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
- printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
+ printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
+#ifdef CONFIG_NAND_U_BOOT
+ puts(", booting from NAND");
+#endif /* CONFIG_NAND_U_BOOT */
+ putc('\n');
#endif /* SDR0_PINSTP_SHIFT */
#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index b665a97f15..ed3f91e2a4 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libmtd.a
-COBJS-$(CONFIG_CMD_UBI) += mtdcore.o mtdpart.o
+COBJS-$(CONFIG_MTD_PARTITIONS) += mtdcore.o mtdpart.o
COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o
COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index b43beaa03e..fae430ba6f 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -85,7 +85,7 @@
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 2c97a00167..923e4777be 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -52,7 +52,7 @@
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 9354c2ffb0..73a59db871 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -54,7 +54,7 @@
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 0865d0d33b..70d2c7d0c5 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -85,7 +85,7 @@
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 26cb854394..97bac99597 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -430,12 +430,23 @@
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
+/*
+ * Don't run the memory POST on the NAND-booting version. It will
+ * overwrite part of the U-Boot image which is already loaded from NAND
+ * to SDRAM.
+ */
+#if defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_SYS_POST_MEMORY_ON 0
+#else
+#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
+#endif
+
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
CONFIG_SYS_POST_CPU | \
CONFIG_SYS_POST_ETHER | \
CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_MEMORY_ON | \
CONFIG_SYS_POST_UART)
/* Define here the base-addresses of the UARTs to test in POST */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index a3e2fcef44..fa226b28cb 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -301,13 +301,24 @@
#define CONFIG_SYS_POST_FPU_ON 0
#endif
+/*
+ * Don't run the memory POST on the NAND-booting version. It will
+ * overwrite part of the U-Boot image which is already loaded from NAND
+ * to SDRAM.
+ */
+#if defined(CONFIG_NAND_U_BOOT)
+#define CONFIG_SYS_POST_MEMORY_ON 0
+#else
+#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
+#endif
+
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
CONFIG_SYS_POST_CPU | \
CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU_ON | \
+ CONFIG_SYS_POST_FPU_ON | \
CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
+ CONFIG_SYS_POST_MEMORY_ON | \
CONFIG_SYS_POST_SPR | \
CONFIG_SYS_POST_UART)
generated by cgit (git 2.34.1) at 2024-12-28 20:29:13 +0000