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-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/Makefile56
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/bcm5221.c232
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/dm9161.c225
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/ether.c316
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/i2c.c192
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/ks8721.c249
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S169
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/lxt972.c192
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/reset.c71
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/spi.c151
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/timer.c160
-rw-r--r--arch/arm/cpu/arm920t/at91rm9200/usb.c53
12 files changed, 2066 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm920t/at91rm9200/Makefile b/arch/arm/cpu/arm920t/at91rm9200/Makefile
new file mode 100644
index 0000000000..114d8adeb2
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS += lowlevel_init.o
+
+COBJS += bcm5221.o
+COBJS += dm9161.o
+COBJS += ether.o
+COBJS += i2c.o
+COBJS-$(CONFIG_KS8721_PHY) += ks8721.o
+COBJS += lxt972.o
+COBJS += reset.o
+COBJS += spi.o
+COBJS += timer.o
+COBJS += usb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
new file mode 100644
index 0000000000..8de3cba738
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
@@ -0,0 +1,232 @@
+/*
+ * Broadcom BCM5221 Ethernet PHY
+ *
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#ifdef CONFIG_DRIVER_ETHER
+
+#include <bcm5221.h>
+
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ * bcm5221_IsPhyConnected
+ * Description:
+ * Reads the 2 PHY ID registers
+ * Arguments:
+ * p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ * TRUE - if id read successfully
+ * FALSE- if error
+ */
+unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+ unsigned short Id1, Id2;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1);
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) &&
+ ((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK)))
+ return TRUE;
+
+ return FALSE;
+}
+
+/*
+ * Name:
+ * bcm5221_GetLinkSpeed
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
+ * MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+ unsigned short stat1, stat2;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1))
+ return FALSE;
+
+ if (!(stat1 & BCM5221_LINK_STATUS)) /* link status up? */
+ return FALSE;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2))
+ return FALSE;
+
+ if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
+ /*set Emac for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
+ /*set MII for 100BaseTX and Half Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_SPD;
+ return TRUE;
+ }
+
+ if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
+ /*set MII for 10BaseT and Half Duplex */
+ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ return TRUE;
+ }
+ return FALSE;
+}
+
+
+/*
+ * Name:
+ * bcm5221_InitPhy
+ * Description:
+ * MAC starts checking its link by using parallel detection and
+ * Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac)
+{
+ unsigned char ret = TRUE;
+ unsigned short IntValue;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+
+ if (!bcm5221_GetLinkSpeed (p_mac)) {
+ /* Try another time */
+ ret = bcm5221_GetLinkSpeed (p_mac);
+ }
+
+ /* Disable PHY Interrupts */
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue);
+ /* clear FDX LED and INTR Enable */
+ IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE);
+ /* set FDX, SPD, Link, INTR masks */
+ IntValue |= (BCM5221_FDX_MASK | BCM5221_SPD_MASK |
+ BCM5221_LINK_MASK | BCM5221_INTR_MASK);
+ at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ return (ret);
+}
+
+
+/*
+ * Name:
+ * bcm5221_AutoNegotiate
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
+ * MAC configuration registers
+ * Arguments:
+ * dev - pointer to struct net_device
+ * Return value:
+ * TRUE - if link status set successfully
+ * FALSE - if link status not set
+ */
+unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+ unsigned short value;
+ unsigned short PhyAnar;
+ unsigned short PhyAnalpar;
+
+ /* Set bcm5221 control register */
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
+ return FALSE;
+ value &= ~BCM5221_AUTONEG; /* remove autonegotiation enable */
+ value |= BCM5221_ISOLATE; /* Electrically isolate PHY */
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
+ return FALSE;
+
+ /* Set the Auto_negotiation Advertisement Register */
+ /* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+ PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX |
+ BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3;
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar))
+ return FALSE;
+
+ /* Read the Control Register */
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
+ return FALSE;
+
+ value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE;
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
+ return FALSE;
+ /* Restart Auto_negotiation */
+ value |= BCM5221_RESTART_AUTONEG;
+ value &= ~BCM5221_ISOLATE;
+ if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
+ return FALSE;
+
+ /*check AutoNegotiate complete */
+ udelay (10000);
+ at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value);
+ if (!(value & BCM5221_AUTONEG_COMP))
+ return FALSE;
+
+ /* Get the AutoNeg Link partner base page */
+ if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar))
+ return FALSE;
+
+ if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) {
+ /*set MII for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) {
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return TRUE;
+ }
+ return FALSE;
+}
+
+#endif
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
new file mode 100644
index 0000000000..6d4384f41a
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#ifdef CONFIG_DRIVER_ETHER
+#include <dm9161.h>
+
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ * dm9161_IsPhyConnected
+ * Description:
+ * Reads the 2 PHY ID registers
+ * Arguments:
+ * p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ * TRUE - if id read successfully
+ * FALSE- if error
+ */
+unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+ unsigned short Id1, Id2;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
+ at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
+ ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+ return TRUE;
+
+ return FALSE;
+}
+
+/*
+ * Name:
+ * dm9161_GetLinkSpeed
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
+ * MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+ unsigned short stat1, stat2;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+ return FALSE;
+
+ if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */
+ return FALSE;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+ return FALSE;
+
+ if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+ /*set Emac for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) {
+ /*set MII for 100BaseTX and Half Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_SPD;
+ return TRUE;
+ }
+
+ if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+ /*set MII for 10BaseT and Half Duplex */
+ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ return TRUE;
+ }
+ return FALSE;
+}
+
+
+/*
+ * Name:
+ * dm9161_InitPhy
+ * Description:
+ * MAC starts checking its link by using parallel detection and
+ * Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+{
+ UCHAR ret = TRUE;
+ unsigned short IntValue;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+
+ if (!dm9161_GetLinkSpeed (p_mac)) {
+ /* Try another time */
+ ret = dm9161_GetLinkSpeed (p_mac);
+ }
+
+ /* Disable PHY Interrupts */
+ at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
+ /* set FDX, SPD, Link, INTR masks */
+ IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
+ DM9161_LINK_MASK | DM9161_INTR_MASK);
+ at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ return (ret);
+}
+
+
+/*
+ * Name:
+ * dm9161_AutoNegotiate
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
+ * MAC configuration registers
+ * Arguments:
+ * dev - pointer to struct net_device
+ * Return value:
+ * TRUE - if link status set successfully
+ * FALSE - if link status not set
+ */
+UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+ unsigned short value;
+ unsigned short PhyAnar;
+ unsigned short PhyAnalpar;
+
+ /* Set dm9161 control register */
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+ value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */
+ value |= DM9161_ISOLATE; /* Electrically isolate PHY */
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+
+ /* Set the Auto_negotiation Advertisement Register */
+ /* MII advertising for Next page, 100BaseTxFD and HD, */
+ /* 10BaseTFD and HD, IEEE 802.3 */
+ PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
+ DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+ return FALSE;
+
+ /* Read the Control Register */
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+
+ value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+ /* Restart Auto_negotiation */
+ value |= DM9161_RESTART_AUTONEG;
+ value &= ~DM9161_ISOLATE;
+ if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+ return FALSE;
+
+ /*check AutoNegotiate complete */
+ udelay (10000);
+ at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
+ if (!(value & DM9161_AUTONEG_COMP))
+ return FALSE;
+
+ /* Get the AutoNeg Link partner base page */
+ if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+ return FALSE;
+
+ if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+ /*set MII for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return TRUE;
+ }
+
+ if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return TRUE;
+ }
+ return FALSE;
+}
+
+#endif
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c
new file mode 100644
index 0000000000..91eab95eed
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/ether.c
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <miiphy.h>
+#include <asm/mach-types.h>
+
+/* ----- Ethernet Buffer definitions ----- */
+
+typedef struct {
+ unsigned long addr, size;
+} rbf_t;
+
+#define RBF_ADDR 0xfffffffc
+#define RBF_OWNER (1<<0)
+#define RBF_WRAP (1<<1)
+#define RBF_BROADCAST (1<<31)
+#define RBF_MULTICAST (1<<30)
+#define RBF_UNICAST (1<<29)
+#define RBF_EXTERNAL (1<<28)
+#define RBF_UNKOWN (1<<27)
+#define RBF_SIZE 0x07ff
+#define RBF_LOCAL4 (1<<26)
+#define RBF_LOCAL3 (1<<25)
+#define RBF_LOCAL2 (1<<24)
+#define RBF_LOCAL1 (1<<23)
+
+#define RBF_FRAMEMAX 64
+#define RBF_FRAMELEN 0x600
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if defined(CONFIG_CMD_NET)
+
+/* alignment as per Errata #11 (64 bytes) is insufficient! */
+rbf_t rbfdt[RBF_FRAMEMAX] __attribute__((aligned(512)));
+rbf_t *rbfp;
+
+unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN]
+ __attribute__((aligned(4)));
+
+/* structure to interface the PHY */
+AT91S_PhyOps PhyOps;
+
+AT91PS_EMAC p_mac;
+
+/*********** EMAC Phy layer Management functions *************************/
+/*
+ * Name:
+ * at91rm9200_EmacEnableMDIO
+ * Description:
+ * Enables the MDIO bit in MAC control register
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * none
+ */
+void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
+{
+ /* Mac CTRL reg set for MDIO enable */
+ p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
+}
+
+/*
+ * Name:
+ * at91rm9200_EmacDisableMDIO
+ * Description:
+ * Disables the MDIO bit in MAC control register
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * none
+ */
+void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
+{
+ /* Mac CTRL reg set for MDIO disable */
+ p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
+}
+
+
+/*
+ * Name:
+ * at91rm9200_EmacReadPhy
+ * Description:
+ * Reads data from the PHY register
+ * Arguments:
+ * dev - pointer to struct net_device
+ * RegisterAddress - unsigned char
+ * pInput - pointer to value read from register
+ * Return value:
+ * TRUE - if data read successfully
+ */
+UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
+ unsigned char RegisterAddress,
+ unsigned short *pInput)
+{
+ p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
+ (AT91C_EMAC_RW_R) |
+ (RegisterAddress << 18) |
+ (AT91C_EMAC_CODE_802_3);
+
+ udelay (10000);
+
+ *pInput = (unsigned short) p_mac->EMAC_MAN;
+
+ return TRUE;
+}
+
+
+/*
+ * Name:
+ * at91rm9200_EmacWritePhy
+ * Description:
+ * Writes data to the PHY register
+ * Arguments:
+ * dev - pointer to struct net_device
+ * RegisterAddress - unsigned char
+ * pOutput - pointer to value to be written in the register
+ * Return value:
+ * TRUE - if data read successfully
+ */
+UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
+ unsigned char RegisterAddress,
+ unsigned short *pOutput)
+{
+ p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
+ AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
+ (RegisterAddress << 18) | *pOutput;
+
+ udelay (10000);
+
+ return TRUE;
+}
+
+int eth_init (bd_t * bd)
+{
+ int ret;
+ int i;
+ uchar enetaddr[6];
+
+ p_mac = AT91C_BASE_EMAC;
+
+ /* PIO Disable Register */
+ *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
+ AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
+ AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
+ AT91C_PA7_ETXCK_EREFCK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+ *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
+ *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
+#else
+ *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
+ AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
+ AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+
+ /* Select B Register */
+ *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
+ AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
+ AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
+#endif
+
+ *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
+
+ p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
+
+ /* Init Ethernet buffers */
+ for (i = 0; i < RBF_FRAMEMAX; i++) {
+ rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
+ rbfdt[i].size = 0;
+ }
+ rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
+ rbfp = &rbfdt[0];
+
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+
+ /* The CSB337 originally used a version of the MicroMonitor bootloader
+ * which saved Ethernet addresses in the "wrong" order. Operating
+ * systems (like Linux) know this, and apply a workaround. Replicate
+ * that MicroMonitor behavior so we avoid needing to make such OS code
+ * care about which bootloader was used.
+ */
+ if (machine_is_csb337()) {
+ p_mac->EMAC_SA2H = (enetaddr[0] << 8) | (enetaddr[1]);
+ p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16)
+ | (enetaddr[4] << 8) | (enetaddr[5]);
+ } else {
+ p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
+ | (enetaddr[1] << 8) | (enetaddr[0]);
+ p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]);
+ }
+
+ p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
+ p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
+
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
+ & ~AT91C_EMAC_CLK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+ p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
+#endif
+
+#if (AT91C_MASTER_CLOCK > 40000000)
+ /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
+ p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
+#endif
+
+ p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
+
+ at91rm9200_GetPhyInterface (& PhyOps);
+
+ if (!PhyOps.IsPhyConnected (p_mac))
+ printf ("PHY not connected!!\n\r");
+
+ /* MII management start from here */
+ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
+ if (!(ret = PhyOps.Init (p_mac))) {
+ printf ("MAC: error during MII initialization\n");
+ return 0;
+ }
+ } else {
+ printf ("No link\n\r");
+ return 0;
+ }
+
+ return 0;
+}
+
+int eth_send (volatile void *packet, int length)
+{
+ while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
+ p_mac->EMAC_TAR = (long) packet;
+ p_mac->EMAC_TCR = length;
+ while (p_mac->EMAC_TCR & 0x7ff);
+ p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
+ return 0;
+}
+
+int eth_rx (void)
+{
+ int size;
+
+ if (!(rbfp->addr & RBF_OWNER))
+ return 0;
+
+ size = rbfp->size & RBF_SIZE;
+ NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
+
+ rbfp->addr &= ~RBF_OWNER;
+ if (rbfp->addr & RBF_WRAP)
+ rbfp = &rbfdt[0];
+ else
+ rbfp++;
+
+ p_mac->EMAC_RSR |= AT91C_EMAC_REC;
+
+ return size;
+}
+
+void eth_halt (void)
+{
+};
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+int at91rm9200_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
+{
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy (p_mac, reg, value);
+ at91rm9200_EmacDisableMDIO (p_mac);
+ return 0;
+}
+
+int at91rm9200_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacWritePhy (p_mac, reg, &value);
+ at91rm9200_EmacDisableMDIO (p_mac);
+ return 0;
+}
+
+#endif
+
+int at91rm9200_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
+#endif
+ return 0;
+}
+
+#endif
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/i2c.c b/arch/arm/cpu/arm920t/at91rm9200/i2c.c
new file mode 100644
index 0000000000..1711088ad3
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/i2c.c
@@ -0,0 +1,192 @@
+/*
+ * i2c Support for Atmel's AT91RM9200 Two-Wire Interface
+ *
+ * (c) Rick Bronson
+ *
+ * Borrowed heavily from original work by:
+ * Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
+ *
+ * Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+*/
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include <at91rm9200_i2c.h>
+
+/* define DEBUG */
+
+/*
+ * Poll the i2c status register until the specified bit is set.
+ * Returns 0 if timed out (100 msec)
+ */
+static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
+ int loop_cntr = 10000;
+ do {
+ udelay(10);
+ } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
+
+ return (loop_cntr > 0);
+}
+
+/*
+ * Generic i2c master transfer entrypoint
+ *
+ * rw == 1 means that this is a read
+ */
+static int
+at91_xfer(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len, int rw)
+{
+ AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
+ int length;
+ unsigned char *buf;
+ /* Set the TWI Master Mode Register */
+ twi->TWI_MMR = (chip << 16) | (alen << 8)
+ | ((rw == 1) ? AT91C_TWI_MREAD : 0);
+
+ /* Set TWI Internal Address Register with first messages data field */
+ if (alen > 0)
+ twi->TWI_IADR = addr;
+
+ length = len;
+ buf = buffer;
+ if (length && buf) { /* sanity check */
+ if (rw) {
+ twi->TWI_CR = AT91C_TWI_START;
+ while (length--) {
+ if (!length)
+ twi->TWI_CR = AT91C_TWI_STOP;
+ /* Wait until transfer is finished */
+ if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
+ debug ("at91_i2c: timeout 1\n");
+ return 1;
+ }
+ *buf++ = twi->TWI_RHR;
+ }
+ if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+ debug ("at91_i2c: timeout 2\n");
+ return 1;
+ }
+ } else {
+ twi->TWI_CR = AT91C_TWI_START;
+ while (length--) {
+ twi->TWI_THR = *buf++;
+ if (!length)
+ twi->TWI_CR = AT91C_TWI_STOP;
+ if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
+ debug ("at91_i2c: timeout 3\n");
+ return 1;
+ }
+ }
+ /* Wait until transfer is finished */
+ if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
+ debug ("at91_i2c: timeout 4\n");
+ return 1;
+ }
+ }
+ }
+ return 0;
+}
+
+int
+i2c_probe(unsigned char chip)
+{
+ unsigned char buffer[1];
+
+ return at91_xfer(chip, 0, 0, buffer, 1, 1);
+}
+
+int
+i2c_read (unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len)
+{
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+ /* we only allow one address byte */
+ if (alen > 1)
+ return 1;
+ /* XXX assume an ATMEL AT24C16 */
+ if (alen == 1) {
+#if 0 /* EEPROM code already sets this correctly */
+ chip |= (addr >> 8) & 0xff;
+#endif
+ addr = addr & 0xff;
+ }
+#endif
+ return at91_xfer(chip, addr, alen, buffer, len, 1);
+}
+
+int
+i2c_write(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len)
+{
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+ int i;
+ unsigned char *buf;
+
+ /* we only allow one address byte */
+ if (alen > 1)
+ return 1;
+ /* XXX assume an ATMEL AT24C16 */
+ if (alen == 1) {
+ buf = buffer;
+ /* do single byte writes */
+ for (i = 0; i < len; i++) {
+#if 0 /* EEPROM code already sets this correctly */
+ chip |= (addr >> 8) & 0xff;
+#endif
+ addr = addr & 0xff;
+ if (at91_xfer(chip, addr, alen, buf++, 1, 0))
+ return 1;
+ addr++;
+ }
+ return 0;
+ }
+#endif
+ return at91_xfer(chip, addr, alen, buffer, len, 0);
+}
+
+/*
+ * Main initialization routine
+ */
+void
+i2c_init(int speed, int slaveaddr)
+{
+ AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
+
+ *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ *AT91C_PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */
+
+ twi->TWI_IDR = 0x3ff; /* Disable all interrupts */
+ twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */
+ twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */
+
+ /* Here, CKDIV = 1 and CHDIV=CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
+ twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
+
+ debug ("Found AT91 i2c\n");
+ return;
+}
+
+#endif /* CONFIG_HARD_I2C */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
new file mode 100644
index 0000000000..9fe379369a
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2006
+ * Author : Eric Benard (Eukrea Electromatique)
+ * based on dm9161.c which is :
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <ks8721.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ * ks8721_isphyconnected
+ * Description:
+ * Reads the 2 PHY ID registers
+ * Arguments:
+ * p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ * 1 - if id read successfully
+ * 0 - if error
+ */
+unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac)
+{
+ unsigned short id1, id2;
+
+ at91rm9200_EmacEnableMDIO(p_mac);
+ at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_PHYID1, &id1);
+ at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_PHYID2, &id2);
+ at91rm9200_EmacDisableMDIO(p_mac);
+
+ if ((id1 == (KS8721_PHYID_OUI >> 6)) &&
+ ((id2 >> 10) == (KS8721_PHYID_OUI & KS8721_LSB_MASK))) {
+ if ((id2 & KS8721_MODELMASK) == KS8721BL_MODEL)
+ printf("Micrel KS8721bL PHY detected : ");
+ else
+ printf("Unknown Micrel PHY detected : ");
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Name:
+ * ks8721_getlinkspeed
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
+ * MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
+ * 1 - if link status set succesfully
+ * 0 - if link status not set
+ */
+unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac)
+{
+ unsigned short stat1;
+
+ if (!at91rm9200_EmacReadPhy(p_mac, KS8721_BMSR, &stat1))
+ return 0;
+
+ if (!(stat1 & KS8721_LINK_STATUS)) {
+ /* link status up? */
+ printf("Link Down !\n");
+ return 0;
+ }
+
+ if (stat1 & KS8721_100BASE_TX_FD) {
+ /* set Emac for 100BaseTX and Full Duplex */
+ printf("100BT FD\n");
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return 1;
+ }
+
+ if (stat1 & KS8721_10BASE_T_FD) {
+ /* set MII for 10BaseT and Full Duplex */
+ printf("10BT FD\n");
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return 1;
+ }
+
+ if (stat1 & KS8721_100BASE_T4_HD) {
+ /* set MII for 100BaseTX and Half Duplex */
+ printf("100BT HD\n");
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_SPD;
+ return 1;
+ }
+
+ if (stat1 & KS8721_10BASE_T_HD) {
+ /* set MII for 10BaseT and Half Duplex */
+ printf("10BT HD\n");
+ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ return 1;
+ }
+ return 0;
+}
+
+/*
+ * Name:
+ * ks8721_initphy
+ * Description:
+ * MAC starts checking its link by using parallel detection and
+ * Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * 1 - if link status set succesfully
+ * 0 - if link status not set
+ */
+unsigned char ks8721_initphy(AT91PS_EMAC p_mac)
+{
+ unsigned char ret = 1;
+ unsigned short intvalue;
+
+ at91rm9200_EmacEnableMDIO(p_mac);
+
+ /* Try another time */
+ if (!ks8721_getlinkspeed(p_mac))
+ ret = ks8721_getlinkspeed(p_mac);
+
+ /* Disable PHY Interrupts */
+ intvalue = 0;
+ at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_MDINTR, &intvalue);
+ at91rm9200_EmacDisableMDIO(p_mac);
+
+ return ret;
+}
+
+/*
+ * Name:
+ * ks8721_autonegotiate
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
+ * MAC configuration registers
+ * Arguments:
+ * dev - pointer to struct net_device
+ * Return value:
+ * 1 - if link status set successfully
+ * 0 - if link status not set
+ */
+unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status)
+{
+ unsigned short value;
+ unsigned short phyanar;
+ unsigned short phyanalpar;
+
+ /* Set ks8721 control register */
+ if (!at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value))
+ return 0;
+
+ /* remove autonegotiation enable */
+ value &= ~KS8721_AUTONEG;
+ /* Electrically isolate PHY */
+ value |= KS8721_ISOLATE;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ /*
+ * Set the Auto_negotiation Advertisement Register
+ * MII advertising for Next page, 100BaseTxFD and HD,
+ * 10BaseTFD and HD, IEEE 802.3
+ */
+ phyanar = KS8721_NP | KS8721_TX_FDX | KS8721_TX_HDX |
+ KS8721_10_FDX | KS8721_10_HDX | KS8721_AN_IEEE_802_3;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_ANAR, &phyanar)) {
+ return 0;
+ }
+ /* Read the Control Register */
+ if (!at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ value |= KS8721_SPEED_SELECT | KS8721_AUTONEG | KS8721_DUPLEX_MODE;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ /* Restart Auto_negotiation */
+ value |= KS8721_RESTART_AUTONEG;
+ value &= ~KS8721_ISOLATE;
+ if (!at91rm9200_EmacWritePhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
+ return 0;
+ }
+ /* Check AutoNegotiate complete */
+ udelay(10000);
+ at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_BMSR, &value);
+ if (!(value & KS8721_AUTONEG_COMP))
+ return 0;
+
+ /* Get the AutoNeg Link partner base page */
+ if (!at91rm9200_EmacReadPhy(p_mac,
+ CONFIG_PHY_ADDRESS | KS8721_ANLPAR, &phyanalpar)) {
+ return 0;
+ }
+
+ if ((phyanar & KS8721_TX_FDX) && (phyanalpar & KS8721_TX_FDX)) {
+ /* Set MII for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ return 1;
+ }
+
+ if ((phyanar & KS8721_10_FDX) && (phyanalpar & KS8721_10_FDX)) {
+ /* Set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ return 1;
+ }
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
new file mode 100644
index 0000000000..d8bb96004b
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -0,0 +1,169 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * some parameters for the board
+ *
+ * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
+ * turn is based on the boot.bin code from ATMEL
+ *
+ */
+#include <asm/arch/AT91RM9200.h>
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+ .word TEXT_BASE-PHYS_FLASH_1
+#else
+ .word TEXT_BASE
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Get the CKGR Base Address */
+ ldr r1, =AT91C_BASE_CKGR
+ /* Main oscillator Enable register */
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
+ ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
+#else
+ ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
+#endif
+ str r0, [r1, #AT91C_CKGR_MOR]
+ /* Add loop to compensate Main Oscillator startup time */
+ ldr r0, =0x00000010
+LoopOsc:
+ subs r0, r0, #1
+ bhi LoopOsc
+
+ /* memory control configuration */
+ /* this isn't very elegant, but what the heck */
+ ldr r0, =SMRDATA
+ ldr r1, _MTEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #80
+0:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 0b
+ /* delay - this is all done by guess */
+ ldr r0, =0x00010000
+ /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
+1:
+ subs r0, r0, #1
+ bhi 1b
+ ldr r0, =SMRDATA1
+ ldr r1, _MTEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #176
+2:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne 2b
+
+ /* switch from FastBus to Asynchronous clock mode */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF)
+ mcr p15, 0, r0, c1, c0, 0
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+
+SMRDATA:
+ .word AT91C_EBI_CFGR
+ .word CONFIG_SYS_EBI_CFGR_VAL
+ .word AT91C_SMC_CSR0
+ .word CONFIG_SYS_SMC_CSR0_VAL
+ .word AT91C_PLLAR
+ .word CONFIG_SYS_PLLAR_VAL
+ .word AT91C_PLLBR
+ .word CONFIG_SYS_PLLBR_VAL
+ .word AT91C_MCKR
+ .word CONFIG_SYS_MCKR_VAL
+ /* here there's a delay */
+SMRDATA1:
+ .word AT91C_PIOC_ASR
+ .word CONFIG_SYS_PIOC_ASR_VAL
+ .word AT91C_PIOC_BSR
+ .word CONFIG_SYS_PIOC_BSR_VAL
+ .word AT91C_PIOC_PDR
+ .word CONFIG_SYS_PIOC_PDR_VAL
+ .word AT91C_EBI_CSA
+ .word CONFIG_SYS_EBI_CSA_VAL
+ .word AT91C_SDRC_CR
+ .word CONFIG_SYS_SDRC_CR_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL1
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL2
+ .word CONFIG_SYS_SDRAM1
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_TR
+ .word CONFIG_SYS_SDRC_TR_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL3
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ /* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
new file mode 100644
index 0000000000..260d393cf0
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
@@ -0,0 +1,192 @@
+/*
+ *
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Adapted for KwikByte KB920x board: 22APR2005
+ */
+
+#include <common.h>
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <miiphy.h>
+#include <lxt971a.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ * lxt972_IsPhyConnected
+ * Description:
+ * Reads the 2 PHY ID registers
+ * Arguments:
+ * p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ * TRUE - if id read successfully
+ * FALSE- if error
+ */
+unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+ unsigned short Id1, Id2;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1);
+ at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2);
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0))
+ return TRUE;
+
+ return FALSE;
+}
+
+/*
+ * Name:
+ * lxt972_GetLinkSpeed
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
+ * MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+ unsigned short stat1;
+
+ if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1))
+ return FALSE;
+
+ if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link status up? */
+ return FALSE;
+
+ if (stat1 & PHY_LXT971_STAT2_100BTX) {
+
+ if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
+
+ /*set Emac for 100BaseTX and Full Duplex */
+ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+ } else {
+
+ /*set Emac for 100BaseTX and Half Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_SPD;
+ }
+
+ return TRUE;
+
+ } else {
+
+ if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
+
+ /*set MII for 10BaseT and Full Duplex */
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+ | AT91C_EMAC_FD;
+ } else {
+
+ /*set MII for 10BaseT and Half Duplex */
+ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ }
+
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+/*
+ * Name:
+ * lxt972_InitPhy
+ * Description:
+ * MAC starts checking its link by using parallel detection and
+ * Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ * p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ * TRUE - if link status set succesfully
+ * FALSE - if link status not set
+ */
+UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
+{
+ UCHAR ret = TRUE;
+
+ at91rm9200_EmacEnableMDIO (p_mac);
+
+ if (!lxt972_GetLinkSpeed (p_mac)) {
+ /* Try another time */
+ ret = lxt972_GetLinkSpeed (p_mac);
+ }
+
+ /* Disable PHY Interrupts */
+ at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0);
+
+ at91rm9200_EmacDisableMDIO (p_mac);
+
+ return (ret);
+}
+
+
+/*
+ * Name:
+ * lxt972_AutoNegotiate
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
+ * MAC configuration registers
+ * Arguments:
+ * dev - pointer to struct net_device
+ * Return value:
+ * TRUE - if link status set successfully
+ * FALSE - if link status not set
+ */
+UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+ unsigned short value;
+
+ /* Set lxt972 control register */
+ if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value))
+ return FALSE;
+
+ /* Restart Auto_negotiation */
+ value |= PHY_BMCR_RST_NEG;
+ if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value))
+ return FALSE;
+
+ /*check AutoNegotiate complete */
+ udelay (10000);
+ at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value);
+ if (!(value & PHY_BMSR_AUTN_COMP))
+ return FALSE;
+
+ return (lxt972_GetLinkSpeed (p_mac));
+}
+
+#endif
+
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm920t/at91rm9200/reset.c b/arch/arm/cpu/arm920t/at91rm9200/reset.c
new file mode 100644
index 0000000000..945ea2c248
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/reset.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+void board_reset(void) __attribute__((__weak__));
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * or toggle a GPIO pin on the AT91RM9200DK board
+ */
+void reset_cpu (ulong ignored)
+{
+
+#if defined(CONFIG_AT91RM9200_USART)
+ /*shutdown the console to avoid strange chars during reset */
+ serial_exit();
+#endif
+
+ if (board_reset)
+ board_reset();
+
+ /* this is the way Linux does it */
+
+ /* FIXME:
+ * These defines should be moved into
+ * include/asm-arm/arch-at91rm9200/AT91RM9200.h
+ * as soon as the whitespace fix gets applied.
+ */
+ #define AT91C_ST_RSTEN (0x1 << 16)
+ #define AT91C_ST_EXTEN (0x1 << 17)
+ #define AT91C_ST_WDRST (0x1 << 0)
+ #define ST_WDMR *((unsigned long *)0xfffffd08) /* watchdog mode register */
+ #define ST_CR *((unsigned long *)0xfffffd00) /* system clock control register */
+
+ ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+ ST_CR = AT91C_ST_WDRST;
+
+ while (1);
+ /* Never reached */
+}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/spi.c b/arch/arm/cpu/arm920t/at91rm9200/spi.c
new file mode 100644
index 0000000000..f3cb5d8c2c
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/spi.c
@@ -0,0 +1,151 @@
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
+ the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS (0xC << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+#define AT91C_TIMEOUT_WRDY 200000
+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0: NPCS0%1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
+
+/*-------------------------------------------------------------------*/
+/* SPI DataFlash Init */
+/*-------------------------------------------------------------------*/
+void AT91F_SpiInit(void)
+{
+ /* Configure PIOs */
+ AT91C_BASE_PIOA->PIO_ASR =
+ AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
+ AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
+ AT91C_PA2_SPCK;
+ AT91C_BASE_PIOA->PIO_PDR =
+ AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
+ AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
+ AT91C_PA2_SPCK;
+ /* Enable CLock */
+ AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
+
+ /* Reset the SPI */
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
+
+ /* Configure SPI in Master Mode with No CS selected !!! */
+ AT91C_BASE_SPI->SPI_MR =
+ AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+ /* Configure CS0 and CS3 */
+ *(AT91C_SPI_CSR + 0) =
+ AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+ *(AT91C_SPI_CSR + 3) =
+ AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+}
+
+void AT91F_SpiEnable(int cs)
+{
+ switch(cs) {
+ case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI->SPI_MR |=
+ ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) &
+ AT91C_SPI_PCS);
+ break;
+ case 3: /* Configure SPI CS3 for Serial DataFlash Card */
+ /* Set up PIO SDC_TYPE to switch on DataFlash Card */
+ /* and not MMC/SDCard */
+ AT91C_BASE_PIOB->PIO_PER =
+ AT91C_PIO_PB7; /* Set in PIO mode */
+ AT91C_BASE_PIOB->PIO_OER =
+ AT91C_PIO_PB7; /* Configure in output */
+ /* Clear Output */
+ AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
+ /* Configure PCS */
+ AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+ AT91C_BASE_SPI->SPI_MR |=
+ ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+ break;
+ }
+
+ /* SPI_Enable */
+ AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; }
+
+/*---------------------------------------------------------------------------*/
+/* \fn AT91F_SpiWrite */
+/* \brief Set the PDC registers for a transfert */
+/*---------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+ unsigned int timeout;
+
+ pDesc->state = BUSY;
+
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+ /* Initialize the Transmit and Receive Pointer */
+ AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+ AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+ /* Intialize the Transmit and Receive Counters */
+ AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+ AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+
+ if ( pDesc->tx_data_size != 0 ) {
+ /* Initialize the Next Transmit and Next Receive Pointer */
+ AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+ AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+ /* Intialize the Next Transmit and Next Receive Counters */
+ AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
+ AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+ }
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked();
+ timeout = 0;
+
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+ while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
+ ((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT));
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ pDesc->state = IDLE;
+
+ if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){
+ printf("Error Timeout\n\r");
+ return DATAFLASH_ERROR;
+ }
+
+ return DATAFLASH_OK;
+}
+#endif
diff --git a/arch/arm/cpu/arm920t/at91rm9200/timer.c b/arch/arm/cpu/arm920t/at91rm9200/timer.c
new file mode 100644
index 0000000000..9c54bbedbe
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/timer.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <asm/io.h>*/
+#include <asm/arch/hardware.h>
+/*#include <asm/proc/ptrace.h>*/
+
+/* the number of clocks per CONFIG_SYS_HZ */
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
+AT91PS_TC tmr;
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init (void)
+{
+ tmr = AT91C_BASE_TC0;
+
+ /* enables TC1.0 clock */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */
+
+ *AT91C_TCB0_BCR = 0;
+ *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
+ tmr->TC_CCR = AT91C_TC_CLKDIS;
+#define AT91C_TC_CMR_CPCTRG (1 << 14)
+ /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
+ tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
+
+ tmr->TC_IDR = ~0ul;
+ tmr->TC_RC = TIMER_LOAD_VAL;
+ lastinc = 0;
+ tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
+ timestamp = 0;
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+void __udelay (unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastinc = READ_TIMER;
+ timestamp = 0;
+}
+
+ulong get_timer_raw (void)
+{
+ ulong now = READ_TIMER;
+
+ if (now >= lastinc) {
+ /* normal mode */
+ timestamp += now - lastinc;
+ } else {
+ /* we have an overflow ... */
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
+ }
+ lastinc = now;
+
+ return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+ return get_timer_raw()/TIMER_LOAD_VAL;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+ ulong endtime;
+ signed long diff;
+
+ tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+ tmo *= usec;
+ tmo /= 1000;
+
+ endtime = get_timer_raw () + tmo;
+
+ do {
+ ulong now = get_timer_raw ();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ ulong tbclk;
+
+ tbclk = CONFIG_SYS_HZ;
+ return tbclk;
+}
diff --git a/arch/arm/cpu/arm920t/at91rm9200/usb.c b/arch/arm/cpu/arm920t/at91rm9200/usb.c
new file mode 100644
index 0000000000..72355dcf9a
--- /dev/null
+++ b/arch/arm/cpu/arm920t/at91rm9200/usb.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2006
+ * DENX Software Engineering <mk@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+# ifdef CONFIG_AT91RM9200
+
+#include <asm/arch/hardware.h>
+
+int usb_cpu_init(void)
+{
+ /* Enable USB host clock. */
+ *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */
+ return 0;
+}
+
+int usb_cpu_stop(void)
+{
+ /* Initialization failed */
+ *AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */
+ *AT91C_PMC_SCDR = AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
+ return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+ return usb_cpu_stop();
+}
+
+# endif /* CONFIG_AT91RM9200 */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
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