7 files changed, 1 insertions, 349 deletions

diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index 8faf34b87e..948b764193 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -11,7 +11,6 @@ obj-y	+= cpu.o
 
 obj-$(CONFIG_EP93XX) += ep93xx/
 obj-$(CONFIG_IMX) += imx/
-obj-$(CONFIG_S3C24X0) += s3c24x0/
 
 # some files can only build in ARM mode
 
diff --git a/arch/arm/cpu/arm920t/ep93xx/speed.c b/arch/arm/cpu/arm920t/ep93xx/speed.c
index 9dc60b6ff2..f0ab7d4e3d 100644
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ b/arch/arm/cpu/arm920t/ep93xx/speed.c
@@ -39,7 +39,7 @@ static ulong get_PLLCLK(uint32_t *pllreg)
 }
 
 /* return FCLK frequency */
-ulong get_FCLK()
+ulong get_FCLK(void)
 {
 	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
deleted file mode 100644
index e78f8a017c..0000000000
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
-obj-y	+= speed.o
-obj-y	+= timer.o
diff --git a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
deleted file mode 100644
index fede51a160..0000000000
--- a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2010
- * David Mueller <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-typedef ulong (*getfreq)(void);
-
-static const getfreq freq_f[] = {
-	get_FCLK,
-	get_HCLK,
-	get_PCLK,
-};
-
-static const char freq_c[] = { 'F', 'H', 'P' };
-
-int print_cpuinfo(void)
-{
-	int i;
-	char buf[32];
-/* the S3C2400 seems to be lacking a CHIP ID register */
-#ifndef CONFIG_S3C2400
-	ulong cpuid;
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	cpuid = readl(&gpio->gstatus1);
-	printf("CPUID: %8lX\n", cpuid);
-#endif
-	for (i = 0; i < ARRAY_SIZE(freq_f); i++)
-		printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]()));
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c
deleted file mode 100644
index 3701c5d9a3..0000000000
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* This code should work for both the S3C2400 and the S3C2410
- * as they seem to have the same PLL and clock machinery inside.
- * The different address mapping is handled by the s3c24xx.h files below.
- */
-
-#include <common.h>
-#ifdef CONFIG_S3C24X0
-
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#define MPLL 0
-#define UPLL 1
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-static ulong get_PLLCLK(int pllreg)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	ulong r, m, p, s;
-
-	if (pllreg == MPLL)
-		r = readl(&clk_power->mpllcon);
-	else if (pllreg == UPLL)
-		r = readl(&clk_power->upllcon);
-	else
-		hang();
-
-	m = ((r & 0xFF000) >> 12) + 8;
-	p = ((r & 0x003F0) >> 4) + 2;
-	s = r & 0x3;
-
-#if defined(CONFIG_S3C2440)
-	if (pllreg == MPLL)
-		return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
-#endif
-	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
-
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
-	return get_PLLCLK(MPLL);
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-#ifdef CONFIG_S3C2440
-	switch (readl(&clk_power->clkdivn) & 0x6) {
-	default:
-	case 0:
-		return get_FCLK();
-	case 2:
-		return get_FCLK() / 2;
-	case 4:
-		return (readl(&clk_power->camdivn) & (1 << 9)) ?
-			get_FCLK() / 8 : get_FCLK() / 4;
-	case 6:
-		return (readl(&clk_power->camdivn) & (1 << 8)) ?
-			get_FCLK() / 6 : get_FCLK() / 3;
-	}
-#else
-	return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
-#endif
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-	return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
-	return get_PLLCLK(UPLL);
-}
-
-#endif /* CONFIG_S3C24X0 */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c
deleted file mode 100644
index ba1e616b82..0000000000
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#ifdef CONFIG_S3C24X0
-
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init(void)
-{
-	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
-	ulong tmr;
-
-	/* use PWM Timer 4 because it has no output */
-	/* prescaler for Timer 4 is 16 */
-	writel(0x0f00, &timers->tcfg0);
-	if (gd->arch.tbu == 0) {
-		/*
-		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
-		 * (default) and prescaler = 16. Should be 10390
-		 * @33.25MHz and 15625 @ 50 MHz
-		 */
-		gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
-		gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
-	}
-	/* load value for 10 ms timeout */
-	writel(gd->arch.tbu, &timers->tcntb4);
-	/* auto load, manual update of timer 4 */
-	tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
-	writel(tmr, &timers->tcon);
-	/* auto load, start timer 4 */
-	tmr = (tmr & ~0x0700000) | 0x0500000;
-	writel(tmr, &timers->tcon);
-	gd->arch.lastinc = 0;
-	gd->arch.tbl = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_ticks();
-
-	tmo = usec / 1000;
-	tmo *= (gd->arch.tbu * 100);
-	tmo /= 1000;
-
-	while ((ulong) (get_ticks() - start) < tmo)
-		/*NOP*/;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong tmr = get_ticks();
-
-	return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
-}
-
-void udelay_masked(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= (gd->arch.tbu * 100);
-		tmo /= 1000;
-	} else {
-		tmo = usec * (gd->arch.tbu * 100);
-		tmo /= (1000 * 1000);
-	}
-
-	endtime = get_ticks() + tmo;
-
-	do {
-		ulong now = get_ticks();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
-	ulong now = readl(&timers->tcnto4) & 0xffff;
-
-	if (gd->arch.lastinc >= now) {
-		/* normal mode */
-		gd->arch.tbl += gd->arch.lastinc - now;
-	} else {
-		/* we have an overflow ... */
-		gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
-	}
-	gd->arch.lastinc = now;
-
-	return gd->arch.tbl;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-/*
- * reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu(ulong ignored)
-{
-	struct s3c24x0_watchdog *watchdog;
-
-	watchdog = s3c24x0_get_base_watchdog();
-
-	/* Disable watchdog */
-	writel(0x0000, &watchdog->wtcon);
-
-	/* Initialize watchdog timer count register */
-	writel(0x0001, &watchdog->wtcnt);
-
-	/* Enable watchdog timer; assert reset at timer timeout */
-	writel(0x0021, &watchdog->wtcon);
-
-	while (1)
-		/* loop forever and wait for reset to happen */;
-
-	/*NOTREACHED*/
-}
-
-#endif /* CONFIG_S3C24X0 */
diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
index 3ada6d026f..3880a402d8 100644
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -50,43 +50,6 @@ copyex:
 	bne	copyex
 #endif
 
-#ifdef CONFIG_S3C24X0
-	/* turn off the watchdog */
-
-# if defined(CONFIG_S3C2400)
-#  define pWTCON	0x15300000
-#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
-#  define CLKDIVN	0x14800014	/* clock divisor register */
-#else
-#  define pWTCON	0x53000000
-#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
-#  define INTSUBMSK	0x4A00001C
-#  define CLKDIVN	0x4C000014	/* clock divisor register */
-# endif
-
-	ldr	r0, =pWTCON
-	mov	r1, #0x0
-	str	r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTMR - default
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =INTMSK
-	str	r1, [r0]
-# if defined(CONFIG_S3C2410)
-	ldr	r1, =0x3ff
-	ldr	r0, =INTSUBMSK
-	str	r1, [r0]
-# endif
-
-	/* FCLK:HCLK:PCLK = 1:2:4 */
-	/* default FCLK is 120 MHz ! */
-	ldr	r0, =CLKDIVN
-	mov	r1, #3
-	str	r1, [r0]
-#endif	/* CONFIG_S3C24X0 */
-
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!