diff options
Diffstat (limited to 'arch/arm/cpu/arm926ejs')
-rw-r--r-- | arch/arm/cpu/arm926ejs/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/Makefile | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/cpu.c | 85 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/dram.c | 117 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/timer.c | 201 |
9 files changed, 0 insertions, 588 deletions
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index f5944cc965..63fa159db6 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -16,9 +16,7 @@ endif obj-$(CONFIG_ARMADA100) += armada100/ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ -obj-$(CONFIG_MB86R0x) += mb86r0x/ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ -obj-$(CONFIG_PANTHEON) += pantheon/ obj-$(if $(filter spear,$(SOC)),y) += spear/ diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile deleted file mode 100644 index 365892c413..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = clock.o reset.o timer.o diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c deleted file mode 100644 index 1f6f66eba2..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -/* - * Get the peripheral bus frequency depending on pll pin settings - */ -ulong get_bus_freq(ulong dummy) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - uint32_t pllmode; - - pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; - - if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) - return 40000000; - - return 41164767; -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c deleted file mode 100644 index 7bd77ff202..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -/* - * Reset the cpu by setting software reset request bit - */ -void reset_cpu(ulong ignored) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - - writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); - while (1) - /* NOP */; - /* Never reached */ -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c deleted file mode 100644 index bb078196d0..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * (C) Copyright 2010 - * Matthias Weisser, Graf-Syteco <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <div64.h> -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -#define TIMER_LOAD_VAL 0xffffffff -#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= TIMER_FREQ; - do_div(usec, 1000000); - - return usec; -} - -/* nothing really to do with interrupts, just starts up a counter. */ -int timer_init(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong ctrl = readl(&timer->control); - - writel(TIMER_LOAD_VAL, &timer->load); - - ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | - MB86R0x_TIMER_SIZE_32; - - writel(ctrl, &timer->control); - - /* capture current value time */ - lastdec = readl(&timer->value); - timestamp = 0; /* start "advancing" time stamp from 0 */ - - return 0; -} - -/* - * timer without interrupts - */ -unsigned long long get_ticks(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong now = readl(&timer->value); - - if (now <= lastdec) { - /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - timestamp += lastdec - now; - } else { - /* we have rollover of incrementer */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = usec_to_tick(usec); - tmp = get_ticks(); /* get current timestamp */ - - while ((get_ticks() - tmp) < tmo) /* loop till event */ - /*NOP*/; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; - - tbclk = TIMER_FREQ; - return tbclk; -} diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile deleted file mode 100644 index 988341f8fb..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2011 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Lei Wen <leiwen@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpu.o timer.o dram.o diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c deleted file mode 100644 index 4e2a177c0d..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/pantheon.h> - -#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) -#define SET_MRVL_ID (1<<8) -#define L2C_RAM_SEL (1<<4) - -int arch_cpu_init(void) -{ - u32 val; - struct panthcpu_registers *cpuregs = - (struct panthcpu_registers*) PANTHEON_CPU_BASE; - - struct panthapb_registers *apbclkres = - (struct panthapb_registers*) PANTHEON_APBC_BASE; - - struct panthmpmu_registers *mpmu = - (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; - - struct panthapmu_registers *apmu = - (struct panthapmu_registers *) PANTHEON_APMU_BASE; - - /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ - val = readl(&cpuregs->cpu_conf); - val = val | SET_MRVL_ID; - writel(val, &cpuregs->cpu_conf); - - /* Turn on clock gating (PMUM_CCGR) */ - writel(0xFFFFFFFF, &mpmu->ccgr); - - /* Turn on clock gating (PMUM_ACGR) */ - writel(0xFFFFFFFF, &mpmu->acgr); - - /* Turn on uart2 clock */ - writel(UARTCLK14745KHZ, &apbclkres->uart0); - - /* Enable GPIO clock */ - writel(APBC_APBCLK, &apbclkres->gpio); - -#ifdef CONFIG_I2C_MV - /* Enable I2C clock */ - writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); - writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); -#endif - -#ifdef CONFIG_MV_SDHCI - /* Enable mmc clock */ - writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, - &apmu->sd1); - writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, - &apmu->sd3); -#endif - - icache_enable(); - - return 0; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - u32 id; - struct panthcpu_registers *cpuregs = - (struct panthcpu_registers*) PANTHEON_CPU_BASE; - - id = readl(&cpuregs->chip_id); - printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); - return 0; -} -#endif - -#ifdef CONFIG_I2C_MV -void i2c_clk_enable(void) -{ -} -#endif diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c deleted file mode 100644 index f77e3d0ab5..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/dram.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com>, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pantheon.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Pantheon DRAM controller supports upto 8 banks - * for chip select 0 and 1 - */ - -/* - * DDR Memory Control Registers - * Refer Datasheet 4.4 - */ -struct panthddr_map_registers { - u32 cs; /* Memory Address Map Register -CS */ - u32 pad[3]; -}; - -struct panthddr_registers { - u8 pad[0x100 - 0x000]; - struct panthddr_map_registers mmap[2]; -}; - -/* - * panth_sdram_base - reads SDRAM Base Address Register - */ -u32 panth_sdram_base(int chip_sel) -{ - struct panthddr_registers *ddr_regs = - (struct panthddr_registers *)PANTHEON_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; - return result; -} - -/* - * panth_sdram_size - reads SDRAM size - */ -u32 panth_sdram_size(int chip_sel) -{ - struct panthddr_registers *ddr_regs = - (struct panthddr_registers *)PANTHEON_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs); - result = (result >> 16) & 0xF; - if (result < 0x7) { - printf("Unknown DRAM Size\n"); - return -1; - } else { - return ((0x8 << (result - 0x7)) * 1024 * 1024); - } -} - -#ifndef CONFIG_SYS_BOARD_DRAM_INIT -int dram_init(void) -{ - int i; - - gd->ram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = panth_sdram_base(i); - gd->bd->bi_dram[i].size = panth_sdram_size(i); - /* - * It is assumed that all memory banks are consecutive - * and without gaps. - * If the gap is found, ram_size will be reported for - * consecutive memory only - */ - if (gd->bd->bi_dram[i].start != gd->ram_size) - break; - - gd->ram_size += gd->bd->bi_dram[i].size; - - } - - for (; i < CONFIG_NR_DRAM_BANKS; i++) { - /* - * If above loop terminated prematurely, we need to set - * remaining banks' start address & size as 0. Otherwise other - * u-boot functions and Linux kernel gets wrong values which - * could result in crash - */ - gd->bd->bi_dram[i].start = 0; - gd->bd->bi_dram[i].size = 0; - } - return 0; -} - -/* - * If this function is not defined here, - * board.c alters dram bank zero configuration defined above. - */ -void dram_init_banksize(void) -{ - dram_init(); -} -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c deleted file mode 100644 index 6382d3b0cf..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/timer.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/pantheon.h> - -/* - * Timer registers - * Refer 6.2.9 in Datasheet - */ -struct panthtmr_registers { - u32 clk_ctrl; /* Timer clk control reg */ - u32 match[9]; /* Timer match registers */ - u32 count[3]; /* Timer count registers */ - u32 status[3]; - u32 ie[3]; - u32 preload[3]; /* Timer preload value */ - u32 preload_ctrl[3]; - u32 wdt_match_en; - u32 wdt_match_r; - u32 wdt_val; - u32 wdt_sts; - u32 icr[3]; - u32 wdt_icr; - u32 cer; /* Timer count enable reg */ - u32 cmr; - u32 ilr[3]; - u32 wcr; - u32 wfar; - u32 wsar; - u32 cvwr[3]; -}; - -#define TIMER 0 /* Use TIMER 0 */ -/* Each timer has 3 match registers */ -#define MATCH_CMP(x) ((3 * TIMER) + x) -#define TIMER_LOAD_VAL 0xffffffff -#define COUNT_RD_REQ 0x1 - -DECLARE_GLOBAL_DATA_PTR; -/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */ - -/* - * For preventing risk of instability in reading counter value, - * first set read request to register cvwr and then read same - * register after it captures counter value. - */ -ulong read_timer(void) -{ - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_TIMER_BASE; - volatile int loop=100; - ulong val; - - writel(COUNT_RD_REQ, &panthtimers->cvwr); - while (loop--) - val = readl(&panthtimers->cvwr); - - /* - * This stop gcc complain and prevent loop mistake init to 0 - */ - val = readl(&panthtimers->cvwr); - - return val; -} - -ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (now >= gd->arch.tbl) { - /* normal mode */ - gd->arch.tbu += now - gd->arch.tbl; - } else { - /* we have an overflow ... */ - gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl; - } - gd->arch.tbl = now; - - return gd->arch.tbu; -} - -ulong get_timer(ulong base) -{ - return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - - base); -} - -void __udelay(unsigned long usec) -{ - ulong delayticks; - ulong endtime; - - delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); - endtime = get_timer_masked() + delayticks; - - while (get_timer_masked() < endtime) - ; -} - -/* - * init the Timer - */ -int timer_init(void) -{ - struct panthapb_registers *apb1clkres = - (struct panthapb_registers *) PANTHEON_APBC_BASE; - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_TIMER_BASE; - - /* Enable Timer clock at 3.25 MHZ */ - writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); - - /* load value into timer */ - writel(0x0, &panthtimers->clk_ctrl); - /* Use Timer 0 Match Resiger 0 */ - writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]); - /* Preload value is 0 */ - writel(0x0, &panthtimers->preload[TIMER]); - /* Enable match comparator 0 for Timer 0 */ - writel(0x1, &panthtimers->preload_ctrl[TIMER]); - - /* Enable timer 0 */ - writel(0x1, &panthtimers->cer); - /* init the gd->arch.tbu and gd->arch.tbl value */ - gd->arch.tbl = read_timer(); - gd->arch.tbu = 0; - - return 0; -} - -#define MPMU_APRR_WDTR (1<<4) -#define TMR_WFAR 0xbaba /* WDT Register First key */ -#define TMP_WSAR 0xeb10 /* WDT Register Second key */ - -/* - * This function uses internal Watchdog Timer - * based reset mechanism. - * Steps to write watchdog registers (protected access) - * 1. Write key value to TMR_WFAR reg. - * 2. Write key value to TMP_WSAR reg. - * 3. Perform write operation. - */ -void reset_cpu (unsigned long ignored) -{ - struct panthmpmu_registers *mpmu = - (struct panthmpmu_registers *) PANTHEON_MPMU_BASE; - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE; - u32 val; - - /* negate hardware reset to the WDT after system reset */ - val = readl(&mpmu->aprr); - val = val | MPMU_APRR_WDTR; - writel(val, &mpmu->aprr); - - /* reset/enable WDT clock */ - writel(APBC_APBCLK, &mpmu->wdtpcr); - - /* clear previous WDT status */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0, &panthtimers->wdt_sts); - - /* set match counter */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0xf, &panthtimers->wdt_match_r); - - /* enable WDT reset */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0x3, &panthtimers->wdt_match_en); - - /*enable functional WDT clock */ - writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} |