diff options
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/ddr.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 888cf1f732..6acf30c5db 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -120,12 +120,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); /* Perform hardware leveling for DDR3 */ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { - udelay(1000); writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | @@ -289,19 +292,14 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) void config_ddr_phy(const struct emif_regs *regs, int nr) { /* - * Disable initialization and refreshes for now until we - * finish programming EMIF regs. - * Also set time between rising edge of DDR_RESET to rising - * edge of DDR_CKE to > 500us per memory spec. + * Disable initialization and refreshes for now until we finish + * programming EMIF regs and set time between rising edge of + * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec. + * We currently hardcode a value based on a max expected frequency + * of 400MHz. */ -#ifndef CONFIG_AM43XX - setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, - EMIF_REG_INITREF_DIS_MASK); -#endif - if (regs->zq_config) - /* Set time between rising edge of DDR_RESET to rising - * edge of DDR_CKE to > 500us per memory spec. */ - writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(EMIF_REG_INITREF_DIS_MASK | 0x3100, + &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); |