diff options
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 697d6e02da..9a9c764b4d 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -195,6 +195,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } } +#ifndef CONFIG_OMAP44XX static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -405,6 +406,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) else dra7_ddr3_init(base, regs); } +#endif #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) @@ -1178,7 +1180,7 @@ static void do_sdram_init(u32 base) #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ /* - * Initializing the LPDDR2 device can not happen from SDRAM. + * Initializing the DDR device can not happen from SDRAM. * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ @@ -1186,15 +1188,19 @@ static void do_sdram_init(u32 base) if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); +#ifndef CONFIG_OMAP44XX else ddr3_init(base, regs); +#endif } +#ifdef CONFIG_OMAP54X if (warm_reset() && (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { set_lpmode_selfrefresh(base); emif_reset_phy(base); omap5_ddr3_leveling(base, regs); } +#endif /* Write to the shadow registers */ emif_update_timings(base, regs); |