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Diffstat (limited to 'arch/arm/cpu/armv7/omap4')
-rw-r--r--arch/arm/cpu/armv7/omap4/clocks.c85
-rw-r--r--arch/arm/cpu/armv7/omap4/hwinit.c24
-rw-r--r--arch/arm/cpu/armv7/omap4/sdram_elpida.c4
3 files changed, 66 insertions, 47 deletions
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index e2189f729f..c568951a91 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -46,8 +46,6 @@
#define puts(s)
#endif
-#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
-
struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
const u32 sys_clk_array[8] = {
@@ -275,47 +273,70 @@ void scale_vcores(void)
{
u32 volt, omap_rev;
- setup_sri2c();
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
omap_rev = omap_revision();
- /* TPS - supplies vdd_mpu on 4460 */
- if (omap_rev >= OMAP4460_ES1_0) {
- volt = 1203;
- do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
- }
/*
- * VCORE 1
- *
- * 4430 : supplies vdd_mpu
- * Setting a high voltage for Nitro mode as smart reflex is not enabled.
- * We use the maximum possible value in the AVS range because the next
- * higher voltage in the discrete range (code >= 0b111010) is way too
- * high
- *
- * 4460 : supplies vdd_core
+ * Scale Voltage rails:
+ * 1. VDD_CORE
+ * 3. VDD_MPU
+ * 3. VDD_IVA
*/
if (omap_rev < OMAP4460_ES1_0) {
+ /*
+ * OMAP4430:
+ * VDD_CORE = TWL6030 VCORE3
+ * VDD_MPU = TWL6030 VCORE1
+ * VDD_IVA = TWL6030 VCORE2
+ */
+ volt = 1200;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+
+ /*
+ * note on VDD_MPU:
+ * Setting a high voltage for Nitro mode as smart reflex is not
+ * enabled. We use the maximum possible value in the AVS range
+ * because the next higher voltage in the discrete range
+ * (code >= 0b111010) is way too high.
+ */
volt = 1325;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+ volt = 1200;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
} else {
+ /*
+ * OMAP4460:
+ * VDD_CORE = TWL6030 VCORE1
+ * VDD_MPU = TPS62361
+ * VDD_IVA = TWL6030 VCORE2
+ */
volt = 1200;
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+ /* TPS62361 */
+ volt = 1203;
+ do_scale_tps62361(TPS62361_VSEL0_GPIO,
+ TPS62361_REG_ADDR_SET1, volt);
+ /* VCORE 2 - supplies vdd_iva */
+ volt = 1200;
+ do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
}
+}
- /* VCORE 2 - supplies vdd_iva */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+u32 get_offset_code(u32 offset)
+{
+ u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
- /*
- * VCORE 3
- * 4430 : supplies vdd_core
- * 4460 : not connected
- */
- if (omap_rev < OMAP4460_ES1_0) {
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
- }
+ if (omap_revision() == OMAP4430_ES1_0)
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+ else
+ offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+ offset_code = (offset + step - 1) / step;
+
+ /* The code starts at 1 not 0 */
+ return ++offset_code;
}
/*
@@ -355,7 +376,6 @@ void enable_basic_clocks(void)
&prcm->cm_l4per_gptimer2_clkctrl,
&prcm->cm_wkup_wdtimer2_clkctrl,
&prcm->cm_l4per_uart3_clkctrl,
- &prcm->cm_l3init_fsusb_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
0
};
@@ -432,10 +452,6 @@ void enable_non_essential_clocks(void)
};
u32 *const clk_modules_hw_auto_non_essential[] = {
- &prcm->cm_mpu_m3_mpu_m3_clkctrl,
- &prcm->cm_ivahd_ivahd_clkctrl,
- &prcm->cm_ivahd_sl2_clkctrl,
- &prcm->cm_dsp_dsp_clkctrl,
&prcm->cm_l3_2_gpmc_clkctrl,
&prcm->cm_l3instr_l3_3_clkctrl,
&prcm->cm_l3instr_l3_instr_clkctrl,
@@ -482,7 +498,6 @@ void enable_non_essential_clocks(void)
&prcm->cm_dss_dss_clkctrl,
&prcm->cm_sgx_sgx_clkctrl,
&prcm->cm_l3init_hsusbhost_clkctrl,
- &prcm->cm_l3init_fsusb_clkctrl,
0
};
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 91f83205ed..187e93887b 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -37,7 +37,7 @@
DECLARE_GLOBAL_DATA_PTR;
-u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -59,8 +59,8 @@ void do_io_settings(void)
u32 lpddr2io;
struct control_lpddr2io_regs *lpddr2io_regs =
(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- struct omap4_sys_ctrl_regs *const ctrl =
- (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+ struct omap_sys_ctrl_regs *const ctrl =
+ (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
@@ -129,40 +129,40 @@ void init_omap_revision(void)
switch (arm_rev) {
case MIDR_CORTEX_A9_R0P1:
- *omap4_revision = OMAP4430_ES1_0;
+ *omap_si_rev = OMAP4430_ES1_0;
break;
case MIDR_CORTEX_A9_R1P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4_CONTROL_ID_CODE_ES2_0:
- *omap4_revision = OMAP4430_ES2_0;
+ *omap_si_rev = OMAP4430_ES2_0;
break;
case OMAP4_CONTROL_ID_CODE_ES2_1:
- *omap4_revision = OMAP4430_ES2_1;
+ *omap_si_rev = OMAP4430_ES2_1;
break;
case OMAP4_CONTROL_ID_CODE_ES2_2:
- *omap4_revision = OMAP4430_ES2_2;
+ *omap_si_rev = OMAP4430_ES2_2;
break;
default:
- *omap4_revision = OMAP4430_ES2_0;
+ *omap_si_rev = OMAP4430_ES2_0;
break;
}
break;
case MIDR_CORTEX_A9_R1P3:
- *omap4_revision = OMAP4430_ES2_3;
+ *omap_si_rev = OMAP4430_ES2_3;
break;
case MIDR_CORTEX_A9_R2P10:
switch (readl(CONTROL_ID_CODE)) {
case OMAP4460_CONTROL_ID_CODE_ES1_1:
- *omap4_revision = OMAP4460_ES1_1;
+ *omap_si_rev = OMAP4460_ES1_1;
break;
case OMAP4460_CONTROL_ID_CODE_ES1_0:
default:
- *omap4_revision = OMAP4460_ES1_0;
+ *omap_si_rev = OMAP4460_ES1_0;
break;
}
break;
default:
- *omap4_revision = OMAP4430_SILICON_ID_INVALID;
+ *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
break;
}
}
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index a5ec7d3dcc..b5389606b6 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -89,6 +89,10 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
+
+/* Dummy registers for OMAP44xx */
+const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
generated by cgit (git 2.34.1) at 2025-02-21 14:01:33 +0000