6 files changed, 59 insertions, 59 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index eb5f4b686e..7653148c67 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -113,11 +113,27 @@ int spl_board_load_image(void)
 
 void s_init(void)
 {
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
-	/* Magic (undocmented) value taken from boot0, without this DRAM
-	 * access gets messed up (seems cache related) */
+	/*
+	 * Undocumented magic taken from boot0, without this DRAM
+	 * access gets messed up (seems cache related).
+	 * The boot0 sources describe this as: "config ema for cache sram"
+	 */
+#if defined CONFIG_MACH_SUN6I
 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#elif defined CONFIG_MACH_SUN8I_A23
+	uint version;
+
+	/* Unlock sram version info reg, read it, relock */
+	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+	version = readl(SUNXI_SRAMC_BASE + 0x24);
+	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+
+	if ((version & 0xffff0000) == 0x16500000)
+		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+	else /* 0x1661 ? */
+		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
 #endif
+
 #if defined CONFIG_MACH_SUN6I || \
     defined CONFIG_MACH_SUN7I || \
     defined CONFIG_MACH_SUN8I
@@ -136,6 +152,7 @@ void s_init(void)
 	timer_init();
 	gpio_init();
 	i2c_init_board();
+	eth_init_board();
 }
 
 #ifdef CONFIG_SPL_BUILD
@@ -243,30 +260,3 @@ void enable_caches(void)
 	dcache_enable();
 }
 #endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-	__maybe_unused int rc;
-
-#ifdef CONFIG_MACPWR
-	gpio_request(CONFIG_MACPWR, "macpwr");
-	gpio_direction_output(CONFIG_MACPWR, 1);
-	mdelay(200);
-#endif
-
-#ifdef CONFIG_SUNXI_GMAC
-	rc = sunxi_gmac_initialize(bis);
-	if (rc < 0) {
-		printf("sunxi: failed to initialize gmac\n");
-		return rc;
-	}
-#endif
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 5cc5d25d2b..0b8fc94711 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
 __weak void clock_init_sec(void)
@@ -28,3 +29,37 @@ int clock_init(void)
 
 	return 0;
 }
+
+/* These functions are shared between various SoCs so put them here. */
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (port == 5) {
+		if (state)
+			prcm_apb0_enable(
+				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+		else
+			prcm_apb0_disable(
+				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+		return 0;
+	}
+
+	/* set the apb clock gate and reset for twi */
+	if (state) {
+		setbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+		setbits_le32(&ccm->apb2_reset_cfg,
+			     1 << (APB2_RESET_TWI_SHIFT + port));
+	} else {
+		clrbits_le32(&ccm->apb2_reset_cfg,
+			     1 << (APB2_RESET_TWI_SHIFT + port));
+		clrbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+	}
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 700b605ab3..15272c9e71 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -85,32 +85,6 @@ void clock_init_uart(void)
 #endif
 }
 
-int clock_twi_onoff(int port, int state)
-{
-	struct sunxi_ccm_reg *const ccm =
-		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-	if (port == 5) {
-		if (state)
-			prcm_apb0_enable(
-				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
-		else
-			prcm_apb0_disable(
-				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
-		return 0;
-	}
-
-	/* set the apb clock gate for twi */
-	if (state)
-		setbits_le32(&ccm->apb2_gate,
-			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-	else
-		clrbits_le32(&ccm->apb2_gate,
-			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-
-	return 0;
-}
-
 #ifdef CONFIG_SPL_BUILD
 void clock_set_pll1(unsigned int clk)
 {
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
index 27179ba19c..180634c838 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
@@ -43,10 +43,10 @@ int clock_twi_onoff(int port, int state)
 		setbits_le32(&ccm->apb1_gate,
 			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
 		setbits_le32(&ccm->apb1_reset_cfg,
-			     1 << (APB1_RESET_UART_SHIFT + port));
+			     1 << (APB1_RESET_TWI_SHIFT + port));
 	} else {
 		clrbits_le32(&ccm->apb1_reset_cfg,
-			     1 << (APB1_RESET_UART_SHIFT + port));
+			     1 << (APB1_RESET_TWI_SHIFT + port));
 		clrbits_le32(&ccm->apb1_gate,
 			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
 	}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
index 7c46acdbf2..55df1b9d54 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
@@ -280,7 +280,7 @@ static int mctl_channel_init(struct dram_para *para)
 
 	writel(0x94be6fa3, MCTL_PROTECT);
 	udelay(100);
-	clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 26);
+	clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16);
 	writel(0x0, MCTL_PROTECT);
 	udelay(100);
 
diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c
index 6ac96ccf86..0749fbdadc 100644
--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
@@ -76,6 +76,7 @@ static int get_vbus_gpio(int index)
 	case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
 	case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
 	case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+	case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
 	}
 	return -EINVAL;
 }