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-rw-r--r--arch/arm/cpu/armv7/Kconfig8
-rw-r--r--arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c68
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c16
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c3
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c44
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c50
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock.c35
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun6i.c26
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun9i.c4
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c2
-rw-r--r--arch/arm/cpu/armv7/sunxi/usb_phy.c1
11 files changed, 182 insertions, 75 deletions
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 6c5d5dd8e0..afeaac84de 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -31,4 +31,12 @@ config ARMV7_VIRT
---help---
Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
+config ARMV7_LPAE
+ boolean "Use LPAE page table format" if EXPERT
+ depends on CPU_V7
+ default n
+ ---help---
+ Say Y here to use the long descriptor page table format. This is
+ required if U-Boot runs in HYP mode.
+
endif
diff --git a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c
index 9fa6e6991f..87987308ac 100644
--- a/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c
+++ b/arch/arm/cpu/armv7/omap5/dra7xx_iodelay.c
@@ -138,8 +138,8 @@ static u32 get_cfg_reg(u16 a_delay, u16 g_delay, u32 cpde, u32 fpde)
return reg;
}
-static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
- int niodelays)
+int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+ int niodelays)
{
struct iodelay_cfg_entry *iodelay = (struct iodelay_cfg_entry *)array;
u32 reg, cpde, fpde, i;
@@ -166,16 +166,14 @@ static int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
return 0;
}
-void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
- struct iodelay_cfg_entry const *iodelay,
- int niodelays)
+int __recalibrate_iodelay_start(void)
{
int ret = 0;
/* IO recalibration should be done only from SRAM */
if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
- return;
+ return -1;
}
/* unlock IODELAY CONFIG registers */
@@ -191,23 +189,27 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
goto err;
ret = update_delay_mechanism((*ctrl)->iodelay_config_base);
- if (ret)
- goto err;
- /* Configure Mux settings */
- do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+err:
+ return ret;
+}
- /* Configure Manual IO timing modes */
- ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
- if (ret)
- goto err;
+void __recalibrate_iodelay_end(int ret)
+{
- ret = isolate_io(DEISOLATE_IO);
+ /* IO recalibration should be done only from SRAM */
+ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+ puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+ return;
+ }
+
+ if (!ret)
+ ret = isolate_io(DEISOLATE_IO);
-err:
/* lock IODELAY CONFIG registers */
writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
CFG_REG_8_OFFSET);
+
/*
* UART cannot be used during IO recalibration sequence as IOs are in
* isolation. So error handling and debug prints are done after
@@ -232,7 +234,41 @@ err:
case ERR_FPDE:
puts("IODELAY: FPDE calculation failed\n");
break;
+ case -1:
+ puts("IODELAY: Wrong Context call?\n");
+ break;
default:
debug("IODELAY: IO delay recalibration successfully completed\n");
}
+
+ return;
+}
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+ struct iodelay_cfg_entry const *iodelay,
+ int niodelays)
+{
+ int ret = 0;
+
+ /* IO recalibration should be done only from SRAM */
+ if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) {
+ puts("IODELAY recalibration called from invalid context - use only from SPL in SRAM\n");
+ return;
+ }
+
+ ret = __recalibrate_iodelay_start();
+ if (ret)
+ goto err;
+
+ /* Configure Mux settings */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads);
+
+ /* Configure Manual IO timing modes */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+ if (ret)
+ goto err;
+
+err:
+ __recalibrate_iodelay_end(ret);
+
}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 7f8c0a423b..b69c0d1371 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -743,6 +743,18 @@ const struct ctrl_ioregs ioregs_dra72x_es1 = {
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
+const struct ctrl_ioregs ioregs_dra72x_es2 = {
+ .ctrl_ddrch = 0x40404040,
+ .ctrl_lpddr2ch = 0x40404040,
+ .ctrl_ddr3ch = 0x60606060,
+ .ctrl_ddrio_0 = 0x00094A40,
+ .ctrl_ddrio_1 = 0x00000000,
+ .ctrl_ddrio_2 = 0x00000000,
+ .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+ .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
+ .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
+};
+
void __weak hw_data_init(void)
{
u32 omap_rev = omap_revision();
@@ -775,6 +787,7 @@ void __weak hw_data_init(void)
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra72x_dplls;
*omap_vcores = &dra722_volts;
@@ -809,6 +822,9 @@ void get_ioregs(const struct ctrl_ioregs **regs)
case DRA722_ES1_0:
*regs = &ioregs_dra72x_es1;
break;
+ case DRA722_ES2_0:
+ *regs = &ioregs_dra72x_es2;
+ break;
default:
printf("\n INVALID OMAP REVISION ");
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 8f184df2ab..e3ac8bbe95 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -373,6 +373,9 @@ void init_omap_revision(void)
case DRA722_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA722_ES1_0;
break;
+ case DRA722_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = DRA722_ES2_0;
+ break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7dc5bb7e4a..7712923d85 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -398,6 +398,45 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
0x0
};
+const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = {
+ 0x04040100,
+ 0x006B009F,
+ 0x006B00A2,
+ 0x006B00A8,
+ 0x006B00A8,
+ 0x006B00B2,
+ 0x002F002F,
+ 0x002F002F,
+ 0x002F002F,
+ 0x002F002F,
+ 0x002F002F,
+ 0x00600073,
+ 0x00600071,
+ 0x0060007C,
+ 0x0060007E,
+ 0x00600084,
+ 0x00400053,
+ 0x00400051,
+ 0x0040005C,
+ 0x0040005E,
+ 0x00400064,
+ 0x00800080,
+ 0x00800080,
+ 0x40010080,
+ 0x08102040,
+ 0x005B008F,
+ 0x005B0092,
+ 0x005B0098,
+ 0x005B0098,
+ 0x005B00A2,
+ 0x00300043,
+ 0x00300041,
+ 0x0030004C,
+ 0x0030004E,
+ 0x00300054,
+ 0x00000077
+};
+
const struct lpddr2_mr_regs mr_regs = {
.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
.mr2 = 0x6,
@@ -441,6 +480,10 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
break;
+ case DRA722_ES2_0:
+ *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
+ *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
+ break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
@@ -670,6 +713,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
case DRA752_ES1_1:
case DRA752_ES2_0:
case DRA722_ES1_0:
+ case DRA722_ES2_0:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index eb5f4b686e..7653148c67 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -113,11 +113,27 @@ int spl_board_load_image(void)
void s_init(void)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
- /* Magic (undocmented) value taken from boot0, without this DRAM
- * access gets messed up (seems cache related) */
+ /*
+ * Undocumented magic taken from boot0, without this DRAM
+ * access gets messed up (seems cache related).
+ * The boot0 sources describe this as: "config ema for cache sram"
+ */
+#if defined CONFIG_MACH_SUN6I
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#elif defined CONFIG_MACH_SUN8I_A23
+ uint version;
+
+ /* Unlock sram version info reg, read it, relock */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+ version = readl(SUNXI_SRAMC_BASE + 0x24);
+ clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
+
+ if ((version & 0xffff0000) == 0x16500000)
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+ else /* 0x1661 ? */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#endif
+
#if defined CONFIG_MACH_SUN6I || \
defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN8I
@@ -136,6 +152,7 @@ void s_init(void)
timer_init();
gpio_init();
i2c_init_board();
+ eth_init_board();
}
#ifdef CONFIG_SPL_BUILD
@@ -243,30 +260,3 @@ void enable_caches(void)
dcache_enable();
}
#endif
-
-#ifdef CONFIG_CMD_NET
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- __maybe_unused int rc;
-
-#ifdef CONFIG_MACPWR
- gpio_request(CONFIG_MACPWR, "macpwr");
- gpio_direction_output(CONFIG_MACPWR, 1);
- mdelay(200);
-#endif
-
-#ifdef CONFIG_SUNXI_GMAC
- rc = sunxi_gmac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize gmac\n");
- return rc;
- }
-#endif
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 5cc5d25d2b..0b8fc94711 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -12,6 +12,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
__weak void clock_init_sec(void)
@@ -28,3 +29,37 @@ int clock_init(void)
return 0;
}
+
+/* These functions are shared between various SoCs so put them here. */
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
+int clock_twi_onoff(int port, int state)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (port == 5) {
+ if (state)
+ prcm_apb0_enable(
+ PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+ else
+ prcm_apb0_disable(
+ PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+ return 0;
+ }
+
+ /* set the apb clock gate and reset for twi */
+ if (state) {
+ setbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+ setbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
+ } else {
+ clrbits_le32(&ccm->apb2_reset_cfg,
+ 1 << (APB2_RESET_TWI_SHIFT + port));
+ clrbits_le32(&ccm->apb2_gate,
+ CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+ }
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 700b605ab3..15272c9e71 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -85,32 +85,6 @@ void clock_init_uart(void)
#endif
}
-int clock_twi_onoff(int port, int state)
-{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- if (port == 5) {
- if (state)
- prcm_apb0_enable(
- PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
- else
- prcm_apb0_disable(
- PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
- return 0;
- }
-
- /* set the apb clock gate for twi */
- if (state)
- setbits_le32(&ccm->apb2_gate,
- CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
- else
- clrbits_le32(&ccm->apb2_gate,
- CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-
- return 0;
-}
-
#ifdef CONFIG_SPL_BUILD
void clock_set_pll1(unsigned int clk)
{
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
index 27179ba19c..180634c838 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
@@ -43,10 +43,10 @@ int clock_twi_onoff(int port, int state)
setbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
setbits_le32(&ccm->apb1_reset_cfg,
- 1 << (APB1_RESET_UART_SHIFT + port));
+ 1 << (APB1_RESET_TWI_SHIFT + port));
} else {
clrbits_le32(&ccm->apb1_reset_cfg,
- 1 << (APB1_RESET_UART_SHIFT + port));
+ 1 << (APB1_RESET_TWI_SHIFT + port));
clrbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
}
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
index 7c46acdbf2..55df1b9d54 100644
--- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c
@@ -280,7 +280,7 @@ static int mctl_channel_init(struct dram_para *para)
writel(0x94be6fa3, MCTL_PROTECT);
udelay(100);
- clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 26);
+ clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16);
writel(0x0, MCTL_PROTECT);
udelay(100);
diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c
index 6ac96ccf86..0749fbdadc 100644
--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
@@ -76,6 +76,7 @@ static int get_vbus_gpio(int index)
case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
}
return -EINVAL;
}
generated by cgit (git 2.34.1) at 2025-01-20 09:13:04 +0000