11 files changed, 466 insertions, 165 deletions

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 00610a0d59..0769a645c3 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -29,11 +29,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
+#include <div64.h>
 
 enum pll_clocks {
 	PLL1_CLOCK = 0,
 	PLL2_CLOCK,
 	PLL3_CLOCK,
+	PLL4_CLOCK,
 	PLL_CLOCKS,
 };
 
@@ -41,25 +43,65 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
 	[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
 	[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
 	[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
+#ifdef	CONFIG_MX53
+	[PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
+#endif
 };
 
 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 
 /*
- * Calculate the frequency of this pll.
+ * Calculate the frequency of PLLn.
  */
-static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
+static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
 {
-	u32 mfi, mfn, mfd, pd;
+	uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
+	uint64_t refclk, temp;
+	int32_t mfn_abs;
+
+	ctrl = readl(&pll->ctrl);
+
+	if (ctrl & MXC_DPLLC_CTL_HFSM) {
+		mfn = __raw_readl(&pll->hfs_mfn);
+		mfd = __raw_readl(&pll->hfs_mfd);
+		op = __raw_readl(&pll->hfs_op);
+	} else {
+		mfn = __raw_readl(&pll->mfn);
+		mfd = __raw_readl(&pll->mfd);
+		op = __raw_readl(&pll->op);
+	}
 
-	mfn = __raw_readl(&pll->mfn);
-	mfd = __raw_readl(&pll->mfd) + 1;
-	mfi = __raw_readl(&pll->op);
-	pd = (mfi  & 0xF) + 1;
-	mfi = (mfi >> 4) & 0xF;
-	mfi = (mfi >= 5) ? mfi : 5;
+	mfd &= MXC_DPLLC_MFD_MFD_MASK;
+	mfn &= MXC_DPLLC_MFN_MFN_MASK;
+	pdf = op & MXC_DPLLC_OP_PDF_MASK;
+	mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
+
+	/* 21.2.3 */
+	if (mfi < 5)
+		mfi = 5;
+
+	/* Sign extend */
+	if (mfn >= 0x04000000) {
+		mfn |= 0xfc000000;
+		mfn_abs = -mfn;
+	} else
+		mfn_abs = mfn;
+
+	refclk = infreq * 2;
+	if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
+		refclk *= 2;
+
+	refclk /= pdf + 1;
+	temp = refclk * mfn_abs;
+	do_div(temp, mfd + 1);
+	ret = refclk * mfi;
+
+	if ((int)mfn < 0)
+		ret -= temp;
+	else
+		ret += temp;
 
-	return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+	return ret;
 }
 
 /*
@@ -99,18 +141,35 @@ static u32 get_periph_clk(void)
 }
 
 /*
+ * Get the rate of ahb clock.
+ */
+static u32 get_ahb_clk(void)
+{
+	uint32_t freq, div, reg;
+
+	freq = get_periph_clk();
+
+	reg = __raw_readl(&mxc_ccm->cbcdr);
+	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+			MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
+
+	return freq / div;
+}
+
+/*
  * Get the rate of ipg clock.
  */
 static u32 get_ipg_clk(void)
 {
-	u32 ahb_podf, ipg_podf;
-
-	ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
-	ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-			MXC_CCM_CBCDR_IPG_PODF_OFFSET;
-	ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-			MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-	return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
+	uint32_t freq, reg, div;
+
+	freq = get_ahb_clk();
+
+	reg = __raw_readl(&mxc_ccm->cbcdr);
+	div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+			MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+
+	return freq / div;
 }
 
 /*
@@ -237,7 +296,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_ARM_CLK:
 		return get_mcu_main_clk();
 	case MXC_AHB_CLK:
-		break;
+		return get_ahb_clk();
 	case MXC_IPG_CLK:
 		return get_ipg_clk();
 	case MXC_IPG_PERCLK:
@@ -274,13 +333,20 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	u32 freq;
 
 	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("pll1: %dMHz\n", freq / 1000000);
+	printf("PLL1       %8d MHz\n", freq / 1000000);
 	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("pll2: %dMHz\n", freq / 1000000);
+	printf("PLL2       %8d MHz\n", freq / 1000000);
 	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("pll3: %dMHz\n", freq / 1000000);
-	printf("ipg clock     : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
-	printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
+	printf("PLL3       %8d MHz\n", freq / 1000000);
+#ifdef	CONFIG_MX53
+	freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
+	printf("PLL4       %8d MHz\n", freq / 1000000);
+#endif
+
+	printf("\n");
+	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index ea9f8ec491..0b96b4789f 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -33,6 +33,12 @@ COBJS	+= gpio.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS	+= spl.o
+ifdef CONFIG_SPL_NAND_SUPPORT
+COBJS	+= spl_nand.o
+endif
+ifdef CONFIG_SPL_MMC_SUPPORT
+COBJS	+= spl_mmc.o
+endif
 endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index d1776522b7..c76fea6188 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -26,6 +26,7 @@
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <asm/arch/sys_proto.h>
+#include <nand.h>
 #include <mmc.h>
 #include <fat.h>
 #include <timestamp_autogenerated.h>
@@ -37,14 +38,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct spl_image_info spl_image;
+
 /* Define global data structure pointer to it*/
 static gd_t gdata __attribute__ ((section(".data")));
 static bd_t bdata __attribute__ ((section(".data")));
-static const char *image_name;
-static u8 image_os;
-static u32 image_load_addr;
-static u32 image_entry_point;
-static u32 image_size;
 
 inline void hang(void)
 {
@@ -65,154 +63,40 @@ void board_init_f(ulong dummy)
 	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
 }
 
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
-	switch (omap_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-		omap_mmc_init(0);
-		break;
-	case BOOT_DEVICE_MMC2:
-		omap_mmc_init(1);
-		break;
-	}
-	return 0;
-}
-#endif
-
-static void parse_image_header(const struct image_header *header)
+void spl_parse_image_header(const struct image_header *header)
 {
 	u32 header_size = sizeof(struct image_header);
 
 	if (__be32_to_cpu(header->ih_magic) == IH_MAGIC) {
-		image_size = __be32_to_cpu(header->ih_size) + header_size;
-		image_entry_point = __be32_to_cpu(header->ih_load);
+		spl_image.size = __be32_to_cpu(header->ih_size) + header_size;
+		spl_image.entry_point = __be32_to_cpu(header->ih_load);
 		/* Load including the header */
-		image_load_addr = image_entry_point - header_size;
-		image_os = header->ih_os;
-		image_name = (const char *)&header->ih_name;
+		spl_image.load_addr = spl_image.entry_point - header_size;
+		spl_image.os = header->ih_os;
+		spl_image.name = (const char *)&header->ih_name;
 		debug("spl: payload image: %s load addr: 0x%x size: %d\n",
-			image_name, image_load_addr, image_size);
+			spl_image.name, spl_image.load_addr, spl_image.size);
 	} else {
 		/* Signature not found - assume u-boot.bin */
 		printf("mkimage signature not found - ih_magic = %x\n",
 			header->ih_magic);
 		puts("Assuming u-boot.bin ..\n");
 		/* Let's assume U-Boot will not be more than 200 KB */
-		image_size = 200 * 1024;
-		image_entry_point = CONFIG_SYS_TEXT_BASE;
-		image_load_addr = CONFIG_SYS_TEXT_BASE;
-		image_os = IH_OS_U_BOOT;
-		image_name = "U-Boot";
-	}
-}
-
-static void mmc_load_image_raw(struct mmc *mmc)
-{
-	u32 image_size_sectors, err;
-	const struct image_header *header;
-
-	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
-						sizeof(struct image_header));
-
-	/* read image header to find the image size & load address */
-	err = mmc->block_dev.block_read(0,
-			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
-			(void *)header);
-
-	if (err <= 0)
-		goto end;
-
-	parse_image_header(header);
-
-	/* convert size to sectors - round up */
-	image_size_sectors = (image_size + MMCSD_SECTOR_SIZE - 1) /
-				MMCSD_SECTOR_SIZE;
-
-	/* Read the header too to avoid extra memcpy */
-	err = mmc->block_dev.block_read(0,
-			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
-			image_size_sectors, (void *)image_load_addr);
-
-end:
-	if (err <= 0) {
-		printf("spl: mmc blk read err - %d\n", err);
-		hang();
+		spl_image.size = 200 * 1024;
+		spl_image.entry_point = CONFIG_SYS_TEXT_BASE;
+		spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
+		spl_image.os = IH_OS_U_BOOT;
+		spl_image.name = "U-Boot";
 	}
 }
 
-static void mmc_load_image_fat(struct mmc *mmc)
-{
-	s32 err;
-	struct image_header *header;
-
-	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
-						sizeof(struct image_header));
-
-	err = fat_register_device(&mmc->block_dev,
-				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
-	if (err) {
-		printf("spl: fat register err - %d\n", err);
-		hang();
-	}
-
-	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
-				(u8 *)header, sizeof(struct image_header));
-	if (err <= 0)
-		goto end;
-
-	parse_image_header(header);
-
-	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
-				(u8 *)image_load_addr, 0);
-
-end:
-	if (err <= 0) {
-		printf("spl: error reading image %s, err - %d\n",
-			CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err);
-		hang();
-	}
-}
-
-static void mmc_load_image(void)
-{
-	struct mmc *mmc;
-	int err;
-	u32 boot_mode;
-
-	mmc_initialize(gd->bd);
-	/* We register only one device. So, the dev id is always 0 */
-	mmc = find_mmc_device(0);
-	if (!mmc) {
-		puts("spl: mmc device not found!!\n");
-		hang();
-	}
-
-	err = mmc_init(mmc);
-	if (err) {
-		printf("spl: mmc init failed: err - %d\n", err);
-		hang();
-	}
-
-	boot_mode = omap_boot_mode();
-	if (boot_mode == MMCSD_MODE_RAW) {
-		debug("boot mode - RAW\n");
-		mmc_load_image_raw(mmc);
-	} else if (boot_mode == MMCSD_MODE_FAT) {
-		debug("boot mode - FAT\n");
-		mmc_load_image_fat(mmc);
-	} else {
-		puts("spl: wrong MMC boot mode\n");
-		hang();
-	}
-}
-
-void jump_to_image_no_args(void)
+static void jump_to_image_no_args(void)
 {
 	typedef void (*image_entry_noargs_t)(void)__attribute__ ((noreturn));
 	image_entry_noargs_t image_entry =
-			(image_entry_noargs_t) image_entry_point;
+			(image_entry_noargs_t) spl_image.entry_point;
 
+	debug("image entry point: 0x%X\n", spl_image.entry_point);
 	image_entry();
 }
 
@@ -228,17 +112,24 @@ void board_init_r(gd_t *id, ulong dummy)
 	boot_device = omap_boot_device();
 	debug("boot device - %d\n", boot_device);
 	switch (boot_device) {
+#ifdef CONFIG_SPL_MMC_SUPPORT
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
-		mmc_load_image();
+		spl_mmc_load_image();
 		break;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	case BOOT_DEVICE_NAND:
+		spl_nand_load_image();
+		break;
+#endif
 	default:
 		printf("SPL: Un-supported Boot Device - %d!!!\n", boot_device);
 		hang();
 		break;
 	}
 
-	switch (image_os) {
+	switch (spl_image.os) {
 	case IH_OS_U_BOOT:
 		debug("Jumping to U-Boot\n");
 		jump_to_image_no_args();
@@ -249,6 +140,7 @@ void board_init_r(gd_t *id, ulong dummy)
 	}
 }
 
+/* This requires UART clocks to be enabled */
 void preloader_console_init(void)
 {
 	const char *u_boot_rev = U_BOOT_VERSION;
@@ -259,7 +151,6 @@ void preloader_console_init(void)
 	gd->flags |= GD_FLG_RELOC;
 	gd->baudrate = CONFIG_BAUDRATE;
 
-	setup_clocks_for_console();
 	serial_init();		/* serial communications setup */
 
 	/* Avoid a second "U-Boot" coming from this string */
diff --git a/arch/arm/cpu/armv7/omap-common/spl_mmc.c b/arch/arm/cpu/armv7/omap-common/spl_mmc.c
new file mode 100644
index 0000000000..1d1e50c3c4
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/spl_mmc.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/sys_proto.h>
+#include <mmc.h>
+#include <fat.h>
+#include <timestamp_autogenerated.h>
+#include <version_autogenerated.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	switch (omap_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+		omap_mmc_init(0);
+		break;
+	case BOOT_DEVICE_MMC2:
+		omap_mmc_init(1);
+		break;
+	}
+	return 0;
+}
+#endif
+
+static void mmc_load_image_raw(struct mmc *mmc)
+{
+	u32 image_size_sectors, err;
+	const struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	/* read image header to find the image size & load address */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, 1,
+			(void *)header);
+
+	if (err <= 0)
+		goto end;
+
+	spl_parse_image_header(header);
+
+	/* convert size to sectors - round up */
+	image_size_sectors = (spl_image.size + MMCSD_SECTOR_SIZE - 1) /
+				MMCSD_SECTOR_SIZE;
+
+	/* Read the header too to avoid extra memcpy */
+	err = mmc->block_dev.block_read(0,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
+			image_size_sectors, (void *)spl_image.load_addr);
+
+end:
+	if (err <= 0) {
+		printf("spl: mmc blk read err - %d\n", err);
+		hang();
+	}
+}
+
+static void mmc_load_image_fat(struct mmc *mmc)
+{
+	s32 err;
+	struct image_header *header;
+
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+						sizeof(struct image_header));
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)header, sizeof(struct image_header));
+	if (err <= 0)
+		goto end;
+
+	spl_parse_image_header(header);
+
+	err = file_fat_read(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME,
+				(u8 *)spl_image.load_addr, 0);
+
+end:
+	if (err <= 0) {
+		printf("spl: error reading image %s, err - %d\n",
+			CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME, err);
+		hang();
+	}
+}
+
+void spl_mmc_load_image(void)
+{
+	struct mmc *mmc;
+	int err;
+	u32 boot_mode;
+
+	mmc_initialize(gd->bd);
+	/* We register only one device. So, the dev id is always 0 */
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	err = mmc_init(mmc);
+	if (err) {
+		printf("spl: mmc init failed: err - %d\n", err);
+		hang();
+	}
+	boot_mode = omap_boot_mode();
+	if (boot_mode == MMCSD_MODE_RAW) {
+		debug("boot mode - RAW\n");
+		mmc_load_image_raw(mmc);
+	} else if (boot_mode == MMCSD_MODE_FAT) {
+		debug("boot mode - FAT\n");
+		mmc_load_image_fat(mmc);
+	} else {
+		puts("spl: wrong MMC boot mode\n");
+		hang();
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c
new file mode 100644
index 0000000000..af02a59557
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/sys_proto.h>
+#include <nand.h>
+#include <timestamp_autogenerated.h>
+#include <version_autogenerated.h>
+#include <asm/omap_common.h>
+
+
+void spl_nand_load_image(void)
+{
+	struct image_header *header;
+	switch (omap_boot_mode()) {
+	case NAND_MODE_HW_ECC:
+		debug("spl: nand - using hw ecc\n");
+		gpmc_init();
+		nand_init();
+		break;
+	default:
+		puts("spl: ERROR: This bootmode is not implemented - hanging");
+		hang();
+	}
+
+	/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
+	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+
+#ifdef CONFIG_NAND_ENV_DST
+	nand_spl_load_image(CONFIG_ENV_OFFSET,
+		CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+	spl_parse_image_header(header);
+	nand_spl_load_image(CONFIG_ENV_OFFSET, spl_image.size,
+		(void *)image_load_addr);
+#ifdef CONFIG_ENV_OFFSET_REDUND
+	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND,
+		CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+	spl_parse_image_header(header);
+	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, spl_image.size,
+		(void *)image_load_addr);
+#endif
+#endif
+	/* Load u-boot */
+	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+		CONFIG_SYS_NAND_PAGE_SIZE, (void *)header);
+	spl_parse_image_header(header);
+	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+		spl_image.size, (void *)spl_image.load_addr);
+	nand_deselect();
+}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 0448bc93ff..1b3ef69a99 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -39,6 +39,7 @@
 #include <asm/cache.h>
 #include <asm/armv7.h>
 #include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
@@ -56,6 +57,41 @@ static const struct gpio_bank gpio_bank_34xx[6] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
 
+#ifdef CONFIG_SPL_BUILD
+/*
+* We use static variables because global data is not ready yet.
+* Initialized data is available in SPL right from the beginning.
+* We would not typically need to save these parameters in regular
+* U-Boot. This is needed only in SPL at the moment.
+*/
+u32 omap3_boot_device = BOOT_DEVICE_NAND;
+
+/* auto boot mode detection is not possible for OMAP3 - hard code */
+u32 omap_boot_mode(void)
+{
+	switch (omap_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+		return MMCSD_MODE_RAW;
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FAT;
+		break;
+	case BOOT_DEVICE_NAND:
+		return NAND_MODE_HW_ECC;
+		break;
+	default:
+		puts("spl: ERROR:  unknown device - can't select boot mode\n");
+		hang();
+	}
+}
+
+u32 omap_boot_device(void)
+{
+	return omap3_boot_device;
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
@@ -197,6 +233,10 @@ void s_init(void)
 
 	per_clocks_enable();
 
+#ifdef CONFIG_SPL_BUILD
+	preloader_console_init();
+#endif
+
 	if (!in_sdram)
 		mem_init();
 }
@@ -245,7 +285,7 @@ void abort(void)
 {
 }
 
-#ifdef CONFIG_NAND_OMAP_GPMC
+#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
 /******************************************************************************
  * OMAP3 specific command to switch between NAND HW and SW ecc
  *****************************************************************************/
@@ -273,7 +313,7 @@ U_BOOT_CMD(
 	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
 );
 
-#endif /* CONFIG_NAND_OMAP_GPMC */
+#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
 
 #ifdef CONFIG_DISPLAY_BOARDINFO
 /**
@@ -410,3 +450,9 @@ void enable_caches(void)
 	dcache_enable();
 }
 #endif
+
+void omap_rev_string(char *omap_rev_string)
+{
+	sprintf(omap_rev_string, "OMAP3, sorry revision detection" \
+		" unimplemented");
+}
diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk
new file mode 100644
index 0000000000..b34fa6417b
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap3/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2011 Linaro Limited
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# (C) Copyright 2010
+# Texas Instruments, <www.ti.com>
+#
+# Aneesh V <aneesh@ti.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y	+= $(OBJTREE)/MLO
+else
+ALL-y	+= $(obj)u-boot.img
+endif
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 67e8ceb55a..a308ebdb6a 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -35,6 +35,16 @@
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
 
+.global save_boot_params
+save_boot_params:
+#ifdef CONFIG_SPL_BUILD
+	ldr	r4, =omap3_boot_device
+	ldr	r5, [r0, #0x4]
+	and	r5, r5, #0xff
+	str	r5, [r4]
+#endif
+	bx	lr
+
 .global omap3_gp_romcode_call
 omap3_gp_romcode_call:
 	PUSH {r4-r12, lr} @ Save all registers from ROM code!
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 2a7970b4d0..0dd1955431 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -8,6 +8,9 @@
  * Copyright (C) 2004-2010
  * Texas Instruments Incorporated - http://www.ti.com/
  *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
  * Author :
  *     Vaibhav Hiremath <hvaibhav@ti.com>
  *
@@ -133,13 +136,40 @@ void do_sdrc_init(u32 cs, u32 early)
 		sdelay(0x20000);
 	}
 
+/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
+ * to prevent this to be build in non-SPL build */
+#ifdef CONFIG_SPL_BUILD
+	/* If we use a SPL there is no x-loader nor config header so we have
+	 * to do the job ourselfs
+	 */
+	if (cs == CS0) {
+		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+		/* General SDRC config */
+		writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
+		writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
+
+		/* AC timings */
+		writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+		writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+
+		/* Initialize */
+		writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+		writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+		writel(V_MR, &sdrc_base->cs[cs].mr);
+	}
+#endif
+
 	/*
 	 * SDRC timings are set up by x-load or config header
 	 * We don't need to redo them here.
 	 * Older x-loads configure only CS0
 	 * configure CS1 to handle this ommission
 	 */
-	if (cs) {
+	if (cs == CS1) {
 		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 		sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 		writel(readl(&sdrc_base->cs[CS0].mcfg),
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index bdb151d7f6..22887aec05 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -44,13 +44,13 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
 				"UNKNOWN",
 				"UNKNOWN",
 				"3.1.2"};
-#endif /* CONFIG_DISPLAY_CPUINFO */
 
 /* this is the revision table for 37xx CPUs */
 static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
 				"1.0",
 				"1.1",
 				"1.2"};
+#endif /* CONFIG_DISPLAY_CPUINFO */
 
 /*****************************************************************
  * dieid_num_r(void) - read and set die ID
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 309b244ad2..8584fdd590 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -257,6 +257,7 @@ void s_init(void)
 	watchdog_init();
 	set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
+	setup_clocks_for_console();
 	preloader_console_init();
 	do_io_settings();
 #endif