diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 42 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/ddr.c | 10 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 26 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 78 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 5 |
6 files changed, 55 insertions, 114 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index e6f227548a..ff932aa7ed 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -97,7 +97,7 @@ void enable_enet_clk(unsigned char enable) { u32 mask, *addr; - if (is_cpu_type(MXC_CPU_MX6UL)) { + if (is_mx6ul()) { mask = MXC_CCM_CCGR3_ENET_MASK; addr = &imx_ccm->CCGR3; } else { @@ -117,7 +117,7 @@ void enable_uart_clk(unsigned char enable) { u32 mask; - if (is_cpu_type(MXC_CPU_MX6UL)) + if (is_mx6ul()) mask = MXC_CCM_CCGR5_UART_MASK; else mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; @@ -168,7 +168,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) reg &= ~mask; __raw_writel(reg, &imx_ccm->CCGR2); } else { - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { + if (is_mx6sx() || is_mx6ul()) { mask = MXC_CCM_CCGR6_I2C4_MASK; addr = &imx_ccm->CCGR6; } else { @@ -279,7 +279,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) switch (pll) { case PLL_BUS: - if (!is_cpu_type(MXC_CPU_MX6UL)) { + if (!is_mx6ul()) { if (pfd_num == 3) { /* No PFD3 on PPL2 */ return 0; @@ -379,8 +379,8 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf; reg = __raw_readl(&imx_ccm->cscmr1); - if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || - is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { + if (is_mx6sl() || is_mx6sx() || + is_mx6dqp() || is_mx6ul()) { if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) return MXC_HCLK; /* OSC 24Mhz */ } @@ -396,8 +396,7 @@ static u32 get_uart_clk(void) u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); - if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) || - is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) { + if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) { if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) freq = MXC_HCLK; } @@ -416,8 +415,7 @@ static u32 get_cspi_clk(void) cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) || - is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) { + if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) { if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) return MXC_HCLK / (cspi_podf + 1); } @@ -479,14 +477,13 @@ static u32 get_mmdc_ch0_clk(void) u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || - is_cpu_type(MXC_CPU_MX6SL)) { + if (is_mx6sx() || is_mx6ul() || is_mx6sl()) { podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >> MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET; - if (is_cpu_type(MXC_CPU_MX6SL)) { + if (is_mx6sl()) { if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL) freq = MXC_HCLK; else @@ -618,7 +615,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) debug("mxs_set_lcdclk, freq = %dKHz\n", freq); - if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) { + if (!is_mx6sx() && !is_mx6ul()) { debug("This chip not support lcd!\n"); return; } @@ -630,7 +627,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) return; } - if (is_cpu_type(MXC_CPU_MX6SX)) { + if (is_mx6sx()) { reg = readl(&imx_ccm->cscdr2); /* Can't change clocks when clock not from pre-mux */ if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0) @@ -711,7 +708,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) MXC_CCM_CBCMR_LCDIF1_PODF_MASK, ((postd - 1) << MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET)); - } else if (is_cpu_type(MXC_CPU_MX6SX)) { + } else if (is_mx6sx()) { /* Setting LCDIF2 for i.MX6SX */ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; @@ -737,7 +734,7 @@ int enable_lcdif_clock(u32 base_addr) u32 reg = 0; u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask; - if (is_cpu_type(MXC_CPU_MX6SX)) { + if (is_mx6sx()) { if ((base_addr != LCDIF1_BASE_ADDR) && (base_addr != LCDIF2_BASE_ADDR)) { puts("Wrong LCD interface!\n"); @@ -752,7 +749,7 @@ int enable_lcdif_clock(u32 base_addr) MXC_CCM_CCGR3_DISP_AXI_MASK) : (MXC_CCM_CCGR3_LCDIF1_PIX_MASK | MXC_CCM_CCGR3_DISP_AXI_MASK); - } else if (is_cpu_type(MXC_CPU_MX6UL)) { + } else if (is_mx6ul()) { if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; @@ -850,8 +847,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); } else if (fec_id == 1) { /* Only i.MX6SX/UL support ENET2 */ - if (!(is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX6UL))) + if (!(is_mx6sx() || is_mx6ul())) return -EINVAL; reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); @@ -1044,7 +1040,7 @@ int enable_pcie_clock(void) #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb - if (is_cpu_type(MXC_CPU_MX6SX)) + if (is_mx6sx()) lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF; else lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF; @@ -1228,7 +1224,7 @@ static void disable_ldb_di_clock_sources(void) /* Make sure PFDs are disabled at boot. */ reg = readl(&mxc_ccm->analog_pfd_528); /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */ - if (is_cpu_type(MXC_CPU_MX6DL)) + if (is_mx6sdl()) reg |= 0x80008080; else reg |= 0x80808080; @@ -1251,7 +1247,7 @@ static void enable_ldb_di_clock_sources(void) int reg; reg = readl(&mxc_ccm->analog_pfd_528); - if (is_cpu_type(MXC_CPU_MX6DL)) + if (is_mx6sdl()) reg &= ~(0x80008080); else reg &= ~(0x80808080); diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 1e7ae28933..f151eec545 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -888,8 +888,7 @@ void mx6sdl_dram_iocfg(unsigned width, #define MR(val, ba, cmd, cs1) \ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) #define MMDC1(entry, value) do { \ - if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \ - !is_cpu_type(MXC_CPU_MX6SL)) \ + if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \ mmdc1->entry = value; \ } while (0) @@ -1197,12 +1196,11 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, u16 mem_speed = ddr3_cfg->mem_speed; mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; - if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && - !is_cpu_type(MXC_CPU_MX6SL)) + if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; /* Limit mem_speed for MX6D/MX6Q */ - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + if (is_mx6dq() || is_mx6dqp()) { if (mem_speed > 1066) mem_speed = 1066; /* 1066 MT/s */ @@ -1221,7 +1219,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports * up to 528 MHz, so reduce the clock to fit chip specs */ - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + if (is_mx6dq() || is_mx6dqp()) { if (clock > 528) clock = 528; /* 528 MHz */ } diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index d4b22ad7f3..88fcfdc2aa 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -108,6 +108,12 @@ u32 get_cpu_rev(void) #define OCOTP_CFG3_SPEED_1GHZ 2 #define OCOTP_CFG3_SPEED_1P2GHZ 3 +/* + * For i.MX6UL + */ +#define OCOTP_CFG3_SPEED_528MHZ 1 +#define OCOTP_CFG3_SPEED_696MHZ 2 + u32 get_cpu_speed_grade_hz(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -120,17 +126,26 @@ u32 get_cpu_speed_grade_hz(void) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; + if (is_mx6ul()) { + if (val == OCOTP_CFG3_SPEED_528MHZ) + return 528000000; + else if (val == OCOTP_CFG3_SPEED_696MHZ) + return 69600000; + else + return 0; + } + switch (val) { /* Valid for IMX6DQ */ case OCOTP_CFG3_SPEED_1P2GHZ: - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + if (is_mx6dq() || is_mx6dqp()) return 1200000000; /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ case OCOTP_CFG3_SPEED_1GHZ: return 996000000; /* Valid for IMX6DQ */ case OCOTP_CFG3_SPEED_850MHZ: - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + if (is_mx6dq() || is_mx6dqp()) return 852000000; /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ case OCOTP_CFG3_SPEED_800MHZ: @@ -278,7 +293,7 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) + if (is_mx6sx() || is_mx6ul() || is_mx6sl()) reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); else reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); @@ -444,8 +459,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs; - if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) && - dev_id == 1) { + if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) { u32 value = readl(&fuse->mac_addr2); mac[0] = value >> 24 ; mac[1] = value >> 16 ; @@ -509,7 +523,7 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2; - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) + if (is_mx6sx() || is_mx6ul()) return; /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 073bbc6d01..ef46c92b09 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -441,3 +441,11 @@ void s_init(void) return; } + +void reset_misc(void) +{ +#ifdef CONFIG_VIDEO_MXS + lcdif_power_down(); +#endif +} + diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 5b91446a8d..62dd275f7e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -364,82 +364,6 @@ struct vcores_data omap5430_volts_es2 = { .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, }; -struct vcores_data dra752_volts = { - .mpu.value = VDD_MPU_DRA7, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, - .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS659038_REG_ADDR_SMPS12, - .mpu.pmic = &tps659038, - .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - - .eve.value = VDD_EVE_DRA7, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, - .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS659038_REG_ADDR_SMPS45, - .eve.pmic = &tps659038, - .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - - .gpu.value = VDD_GPU_DRA7, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, - .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS659038_REG_ADDR_SMPS6, - .gpu.pmic = &tps659038, - .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - - .core.value = VDD_CORE_DRA7, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, - .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS659038_REG_ADDR_SMPS7, - .core.pmic = &tps659038, - - .iva.value = VDD_IVA_DRA7, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, - .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS659038_REG_ADDR_SMPS8, - .iva.pmic = &tps659038, - .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, -}; - -struct vcores_data dra722_volts = { - .mpu.value = VDD_MPU_DRA7, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, - .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS65917_REG_ADDR_SMPS1, - .mpu.pmic = &tps659038, - .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - - .core.value = VDD_CORE_DRA7, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, - .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS65917_REG_ADDR_SMPS2, - .core.pmic = &tps659038, - - /* - * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x - * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. - */ - .gpu.value = VDD_GPU_DRA7, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, - .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS65917_REG_ADDR_SMPS3, - .gpu.pmic = &tps659038, - .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - - .eve.value = VDD_EVE_DRA7, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, - .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS65917_REG_ADDR_SMPS3, - .eve.pmic = &tps659038, - .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - - .iva.value = VDD_IVA_DRA7, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, - .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS65917_REG_ADDR_SMPS3, - .iva.pmic = &tps659038, - .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, -}; - /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -802,7 +726,6 @@ void __weak hw_data_init(void) case DRA752_ES2_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break; @@ -810,7 +733,6 @@ void __weak hw_data_init(void) case DRA722_ES2_0: *prcm = &dra7xx_prcm; *dplls_data = &dra72x_dplls; - *omap_vcores = &dra722_volts; *ctrl = &dra7xx_ctrl; break; diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b18094447b..691e5d3fe1 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -66,8 +66,10 @@ save_boot_params_ret: /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_cp15 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY bl cpu_init_crit #endif +#endif bl _main @@ -250,7 +252,8 @@ skip_errata_621766: mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) /************************************************************************* * * CPU_init_critical registers |