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-rw-r--r--arch/arm/cpu/armv7/Makefile3
-rw-r--r--arch/arm/cpu/armv7/ls102xa/fdt.c2
-rw-r--r--arch/arm/cpu/armv7/mx5/Kconfig47
-rw-r--r--arch/arm/cpu/armv7/smccc-call.S56
-rw-r--r--arch/arm/cpu/armv7/start.S12
-rw-r--r--arch/arm/cpu/armv7/sunxi/psci.c35
6 files changed, 145 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 02e8778be5..5fac252c0e 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,12 +12,13 @@ obj-y += cache_v7.o cache_v7_asm.o
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_LS102XA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_ARCH_LS1021A),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
endif
+obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index ae5e794230..d21ad39f8a 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -94,8 +94,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
}
#endif
- fdt_fixup_ethernet(blob);
-
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
val = gd->cpu_clk;
diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig
index 7b55747612..ef37c351d0 100644
--- a/arch/arm/cpu/armv7/mx5/Kconfig
+++ b/arch/arm/cpu/armv7/mx5/Kconfig
@@ -14,24 +14,63 @@ choice
prompt "MX5 board select"
optional
-config TARGET_USBARMORY
- bool "Support USB armory"
- select CPU_V7
+config TARGET_M53EVK
+ bool "Support m53evk"
+ select MX53
+ select SUPPORT_SPL
+
+config TARGET_MX51EVK
+ bool "Support mx51evk"
+ select BOARD_LATE_INIT
+ select MX51
+
+config TARGET_MX53ARD
+ bool "Support mx53ard"
+ select MX53
config TARGET_MX53CX9020
bool "Support CX9020"
select BOARD_LATE_INIT
- select CPU_V7
select MX53
select DM
select DM_SERIAL
+config TARGET_MX53EVK
+ bool "Support mx53evk"
+ select BOARD_LATE_INIT
+ select MX53
+
+config TARGET_MX53LOCO
+ bool "Support mx53loco"
+ select BOARD_LATE_INIT
+ select MX53
+
+config TARGET_MX53SMD
+ bool "Support mx53smd"
+ select MX53
+
+config TARGET_TS4800
+ bool "Support TS4800"
+ select MX51
+ select SYS_FSL_ERRATUM_ESDHC_A001
+
+config TARGET_USBARMORY
+ bool "Support USB armory"
+ select MX53
+
endchoice
config SYS_SOC
default "mx5"
+source "board/aries/m53evk/Kconfig"
source "board/beckhoff/mx53cx9020/Kconfig"
+source "board/freescale/mx51evk/Kconfig"
+source "board/freescale/mx53ard/Kconfig"
+source "board/freescale/mx53evk/Kconfig"
+source "board/freescale/mx53loco/Kconfig"
+source "board/freescale/mx53smd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
+source "board/technologic/ts4800/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/smccc-call.S b/arch/arm/cpu/armv7/smccc-call.S
new file mode 100644
index 0000000000..c2fdbadbb0
--- /dev/null
+++ b/arch/arm/cpu/armv7/smccc-call.S
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2015, Linaro Limited
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <linux/linkage.h>
+
+#include <asm/opcodes-sec.h>
+#include <asm/opcodes-virt.h>
+
+#define UNWIND(x...)
+ /*
+ * Wrap c macros in asm macros to delay expansion until after the
+ * SMCCC asm macro is expanded.
+ */
+ .macro SMCCC_SMC
+ __SMC(0)
+ .endm
+
+ .macro SMCCC_HVC
+ __HVC(0)
+ .endm
+
+ .macro SMCCC instr
+UNWIND( .fnstart)
+ mov r12, sp
+ push {r4-r7}
+UNWIND( .save {r4-r7})
+ ldm r12, {r4-r7}
+ \instr
+ pop {r4-r7}
+ ldr r12, [sp, #(4 * 4)]
+ stm r12, {r0-r3}
+ bx lr
+UNWIND( .fnend)
+ .endm
+
+/*
+ * void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
+ * unsigned long a3, unsigned long a4, unsigned long a5,
+ * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
+ * struct arm_smccc_quirk *quirk)
+ */
+ENTRY(__arm_smccc_smc)
+ SMCCC SMCCC_SMC
+ENDPROC(__arm_smccc_smc)
+
+/*
+ * void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
+ * unsigned long a3, unsigned long a4, unsigned long a5,
+ * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
+ * struct arm_smccc_quirk *quirk)
+ */
+ENTRY(__arm_smccc_hvc)
+ SMCCC SMCCC_HVC
+ENDPROC(__arm_smccc_hvc)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 1a6aee9442..f06fd28940 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -283,6 +283,18 @@ skip_errata_621766:
skip_errata_725233:
#endif
+#ifdef CONFIG_ARM_ERRATA_852421
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 24 @ set bit #24
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_852423
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 12 @ set bit #12
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 104dc909bc..b3a34de1aa 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -27,6 +27,17 @@
#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+/*
+ * R40 is different from other single cluster SoCs.
+ *
+ * The power clamps are located in the unused space after the per-core
+ * reset controls for core 3. The secondary core entry address register
+ * is in the SRAM controller address range.
+ */
+#define SUN8I_R40_PWROFF (0x110)
+#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
+#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
+
static void __secure cp15_write_cntp_tval(u32 tval)
{
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -68,7 +79,8 @@ static void __secure __mdelay(u32 ms)
static void __secure clamp_release(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_H3)
+ defined(CONFIG_MACH_SUN8I_H3) || \
+ defined(CONFIG_MACH_SUN8I_R40)
u32 tmp = 0x1ff;
do {
tmp >>= 1;
@@ -82,7 +94,8 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
static void __secure clamp_set(u32 __maybe_unused *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_H3)
+ defined(CONFIG_MACH_SUN8I_H3) || \
+ defined(CONFIG_MACH_SUN8I_R40)
writel(0xff, clamp);
#endif
}
@@ -115,7 +128,17 @@ static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
on, 0);
}
-#else /* ! CONFIG_MACH_SUN7I */
+#elif defined CONFIG_MACH_SUN8I_R40
+static void __secure sunxi_cpu_set_power(int cpu, bool on)
+{
+ struct sunxi_cpucfg_reg *cpucfg =
+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+ sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
+ (void *)cpucfg + SUN8I_R40_PWROFF,
+ on, 0);
+}
+#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_prcm_reg *prcm =
@@ -213,7 +236,13 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
psci_save_target_pc(cpu, pc);
/* Set secondary core power on PC */
+#ifdef CONFIG_MACH_SUN8I_R40
+ /* secondary core entry address is programmed differently */
+ writel((u32)&psci_cpu_entry,
+ SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+#else
writel((u32)&psci_cpu_entry, &cpucfg->priv0);
+#endif
/* Assert reset on target CPU */
writel(0, &cpucfg->cpu[cpu].rst);
generated by cgit (git 2.34.1) at 2025-01-10 04:07:33 +0000